diff --git a/sys/arm64/arm64/db_trace.c b/sys/arm64/arm64/db_trace.c index 4bc6af26a023..7b0fdeaeba29 100644 --- a/sys/arm64/arm64/db_trace.c +++ b/sys/arm64/arm64/db_trace.c @@ -1,162 +1,169 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_ddb.h" #include #include #include #include #include #include #include #include #include #include #define FRAME_NORMAL 0 #define FRAME_SYNC 1 #define FRAME_IRQ 2 #define FRAME_SERROR 3 #define FRAME_UNHANDLED 4 +void +db_md_list_breakpoints(void) +{ + + dbg_show_breakpoint(); +} + void db_md_list_watchpoints(void) { dbg_show_watchpoint(); } static void __nosanitizeaddress db_stack_trace_cmd(struct thread *td, struct unwind_state *frame) { c_db_sym_t sym; const char *name; db_expr_t value; db_expr_t offset; int frame_type; while (1) { sym = db_search_symbol(frame->pc, DB_STGY_ANY, &offset); if (sym == C_DB_SYM_NULL) { value = 0; name = "(null)"; } else db_symbol_values(sym, &name, &value); db_printf("%s() at ", name); db_printsym(frame->pc, DB_STGY_PROC); db_printf("\n"); if (strcmp(name, "handle_el0_sync") == 0 || strcmp(name, "handle_el1h_sync") == 0) frame_type = FRAME_SYNC; else if (strcmp(name, "handle_el0_irq") == 0 || strcmp(name, "handle_el1h_irq") == 0) frame_type = FRAME_IRQ; else if (strcmp(name, "handle_serror") == 0) frame_type = FRAME_SERROR; else if (strcmp(name, "handle_empty_exception") == 0) frame_type = FRAME_UNHANDLED; else frame_type = FRAME_NORMAL; if (frame_type != FRAME_NORMAL) { struct trapframe *tf; tf = (struct trapframe *)(uintptr_t)frame->fp - 1; if (!__is_aligned(tf, _Alignof(struct trapframe)) || !kstack_contains(td, (vm_offset_t)tf, sizeof(*tf))) { db_printf("--- invalid trapframe %p\n", tf); break; } switch (frame_type) { case FRAME_SYNC: db_printf("--- exception, esr %#lx\n", tf->tf_esr); break; case FRAME_IRQ: db_printf("--- interrupt\n"); break; case FRAME_SERROR: db_printf("--- system error, esr %#lx\n", tf->tf_esr); break; case FRAME_UNHANDLED: db_printf("--- unhandled exception, esr %#lx\n", tf->tf_esr); break; default: __assert_unreachable(); break; } frame->fp = tf->tf_x[29]; frame->pc = ADDR_MAKE_CANONICAL(tf->tf_elr); if (!INKERNEL(frame->fp)) break; } else { if (strcmp(name, "fork_trampoline") == 0) break; if (!unwind_frame(td, frame)) break; } } } int __nosanitizeaddress db_trace_thread(struct thread *thr, int count) { struct unwind_state frame; struct pcb *ctx; if (thr != curthread) { ctx = kdb_thr_ctx(thr); frame.fp = (uintptr_t)ctx->pcb_x[PCB_FP]; frame.pc = (uintptr_t)ctx->pcb_x[PCB_LR]; db_stack_trace_cmd(thr, &frame); } else db_trace_self(); return (0); } void __nosanitizeaddress db_trace_self(void) { struct unwind_state frame; frame.fp = (uintptr_t)__builtin_frame_address(0); frame.pc = (uintptr_t)db_trace_self; db_stack_trace_cmd(curthread, &frame); } diff --git a/sys/arm64/arm64/debug_monitor.c b/sys/arm64/arm64/debug_monitor.c index 3d8e753e1c45..2e1a956ad75c 100644 --- a/sys/arm64/arm64/debug_monitor.c +++ b/sys/arm64/arm64/debug_monitor.c @@ -1,618 +1,717 @@ /*- * Copyright (c) 2014 The FreeBSD Foundation * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_ddb.h" #include "opt_gdb.h" #include #include #include #include #include #include #include #include #include #include #include #include #ifdef DDB +#include #include +#include #include #endif enum dbg_t { DBG_TYPE_BREAKPOINT = 0, DBG_TYPE_WATCHPOINT = 1, }; static int dbg_watchpoint_num; static int dbg_breakpoint_num; static struct debug_monitor_state kernel_monitor = { .dbg_flags = DBGMON_KERNEL }; +static int dbg_setup_breakpoint(struct debug_monitor_state *monitor, + vm_offset_t addr); +static int dbg_remove_breakpoint(struct debug_monitor_state *monitor, + vm_offset_t addr); static int dbg_setup_watchpoint(struct debug_monitor_state *, vm_offset_t, vm_size_t, enum dbg_access_t); static int dbg_remove_watchpoint(struct debug_monitor_state *, vm_offset_t, vm_size_t); /* Called from the exception handlers */ void dbg_monitor_enter(struct thread *); void dbg_monitor_exit(struct thread *, struct trapframe *); /* Watchpoints/breakpoints control register bitfields */ #define DBG_WATCH_CTRL_LEN_1 (0x1 << 5) #define DBG_WATCH_CTRL_LEN_2 (0x3 << 5) #define DBG_WATCH_CTRL_LEN_4 (0xf << 5) #define DBG_WATCH_CTRL_LEN_8 (0xff << 5) #define DBG_WATCH_CTRL_LEN_MASK(x) ((x) & (0xff << 5)) #define DBG_WATCH_CTRL_EXEC (0x0 << 3) #define DBG_WATCH_CTRL_LOAD (0x1 << 3) #define DBG_WATCH_CTRL_STORE (0x2 << 3) #define DBG_WATCH_CTRL_ACCESS_MASK(x) ((x) & (0x3 << 3)) /* Common for breakpoint and watchpoint */ #define DBG_WB_CTRL_EL1 (0x1 << 1) #define DBG_WB_CTRL_EL0 (0x2 << 1) #define DBG_WB_CTRL_ELX_MASK(x) ((x) & (0x3 << 1)) #define DBG_WB_CTRL_E (0x1 << 0) #define DBG_REG_BASE_BVR 0 #define DBG_REG_BASE_BCR (DBG_REG_BASE_BVR + 16) #define DBG_REG_BASE_WVR (DBG_REG_BASE_BCR + 16) #define DBG_REG_BASE_WCR (DBG_REG_BASE_WVR + 16) /* Watchpoint/breakpoint helpers */ #define DBG_WB_WVR "wvr" #define DBG_WB_WCR "wcr" #define DBG_WB_BVR "bvr" #define DBG_WB_BCR "bcr" #define DBG_WB_READ(reg, num, val) do { \ __asm __volatile("mrs %0, dbg" reg #num "_el1" : "=r" (val)); \ } while (0) #define DBG_WB_WRITE(reg, num, val) do { \ __asm __volatile("msr dbg" reg #num "_el1, %0" :: "r" (val)); \ } while (0) #define READ_WB_REG_CASE(reg, num, offset, val) \ case (num + offset): \ DBG_WB_READ(reg, num, val); \ break #define WRITE_WB_REG_CASE(reg, num, offset, val) \ case (num + offset): \ DBG_WB_WRITE(reg, num, val); \ break #define SWITCH_CASES_READ_WB_REG(reg, offset, val) \ READ_WB_REG_CASE(reg, 0, offset, val); \ READ_WB_REG_CASE(reg, 1, offset, val); \ READ_WB_REG_CASE(reg, 2, offset, val); \ READ_WB_REG_CASE(reg, 3, offset, val); \ READ_WB_REG_CASE(reg, 4, offset, val); \ READ_WB_REG_CASE(reg, 5, offset, val); \ READ_WB_REG_CASE(reg, 6, offset, val); \ READ_WB_REG_CASE(reg, 7, offset, val); \ READ_WB_REG_CASE(reg, 8, offset, val); \ READ_WB_REG_CASE(reg, 9, offset, val); \ READ_WB_REG_CASE(reg, 10, offset, val); \ READ_WB_REG_CASE(reg, 11, offset, val); \ READ_WB_REG_CASE(reg, 12, offset, val); \ READ_WB_REG_CASE(reg, 13, offset, val); \ READ_WB_REG_CASE(reg, 14, offset, val); \ READ_WB_REG_CASE(reg, 15, offset, val) #define SWITCH_CASES_WRITE_WB_REG(reg, offset, val) \ WRITE_WB_REG_CASE(reg, 0, offset, val); \ WRITE_WB_REG_CASE(reg, 1, offset, val); \ WRITE_WB_REG_CASE(reg, 2, offset, val); \ WRITE_WB_REG_CASE(reg, 3, offset, val); \ WRITE_WB_REG_CASE(reg, 4, offset, val); \ WRITE_WB_REG_CASE(reg, 5, offset, val); \ WRITE_WB_REG_CASE(reg, 6, offset, val); \ WRITE_WB_REG_CASE(reg, 7, offset, val); \ WRITE_WB_REG_CASE(reg, 8, offset, val); \ WRITE_WB_REG_CASE(reg, 9, offset, val); \ WRITE_WB_REG_CASE(reg, 10, offset, val); \ WRITE_WB_REG_CASE(reg, 11, offset, val); \ WRITE_WB_REG_CASE(reg, 12, offset, val); \ WRITE_WB_REG_CASE(reg, 13, offset, val); \ WRITE_WB_REG_CASE(reg, 14, offset, val); \ WRITE_WB_REG_CASE(reg, 15, offset, val) #ifdef DDB static uint64_t dbg_wb_read_reg(int reg, int n) { uint64_t val = 0; switch (reg + n) { SWITCH_CASES_READ_WB_REG(DBG_WB_WVR, DBG_REG_BASE_WVR, val); SWITCH_CASES_READ_WB_REG(DBG_WB_WCR, DBG_REG_BASE_WCR, val); SWITCH_CASES_READ_WB_REG(DBG_WB_BVR, DBG_REG_BASE_BVR, val); SWITCH_CASES_READ_WB_REG(DBG_WB_BCR, DBG_REG_BASE_BCR, val); default: printf("trying to read from wrong debug register %d\n", n); } return val; } #endif /* DDB */ static void dbg_wb_write_reg(int reg, int n, uint64_t val) { switch (reg + n) { SWITCH_CASES_WRITE_WB_REG(DBG_WB_WVR, DBG_REG_BASE_WVR, val); SWITCH_CASES_WRITE_WB_REG(DBG_WB_WCR, DBG_REG_BASE_WCR, val); SWITCH_CASES_WRITE_WB_REG(DBG_WB_BVR, DBG_REG_BASE_BVR, val); SWITCH_CASES_WRITE_WB_REG(DBG_WB_BCR, DBG_REG_BASE_BCR, val); default: printf("trying to write to wrong debug register %d\n", n); return; } isb(); } #if defined(DDB) || defined(GDB) +int +kdb_cpu_set_breakpoint(vm_offset_t addr) +{ + return (dbg_setup_breakpoint(NULL, addr)); +} + +int +kdb_cpu_clr_breakpoint(vm_offset_t addr) +{ + return (dbg_remove_breakpoint(NULL, addr)); +} + void kdb_cpu_set_singlestep(void) { KASSERT((READ_SPECIALREG(daif) & PSR_D) == PSR_D, ("%s: debug exceptions are not masked", __func__)); kdb_frame->tf_spsr |= PSR_SS; /* * TODO: Handle single stepping over instructions that access * the DAIF values. On a read the value will be incorrect. */ kernel_monitor.dbg_flags &= ~PSR_DAIF; kernel_monitor.dbg_flags |= kdb_frame->tf_spsr & PSR_DAIF; kdb_frame->tf_spsr |= (PSR_A | PSR_I | PSR_F); WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) | MDSCR_SS | MDSCR_KDE); /* * Disable breakpoints and watchpoints, e.g. stepping * over watched instruction will trigger break exception instead of * single-step exception and locks CPU on that instruction for ever. */ if ((kernel_monitor.dbg_flags & DBGMON_ENABLED) != 0) { WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) & ~MDSCR_MDE); } } void kdb_cpu_clear_singlestep(void) { KASSERT((READ_SPECIALREG(daif) & PSR_D) == PSR_D, ("%s: debug exceptions are not masked", __func__)); kdb_frame->tf_spsr &= ~PSR_DAIF; kdb_frame->tf_spsr |= kernel_monitor.dbg_flags & PSR_DAIF; WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) & ~(MDSCR_SS | MDSCR_KDE)); /* Restore breakpoints and watchpoints */ if ((kernel_monitor.dbg_flags & DBGMON_ENABLED) != 0) { WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) | MDSCR_MDE); if ((kernel_monitor.dbg_flags & DBGMON_KERNEL) != 0) { WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) | MDSCR_KDE); } } } int kdb_cpu_set_watchpoint(vm_offset_t addr, vm_size_t size, int access) { enum dbg_access_t dbg_access; switch (access) { case KDB_DBG_ACCESS_R: dbg_access = HW_BREAKPOINT_R; break; case KDB_DBG_ACCESS_W: dbg_access = HW_BREAKPOINT_W; break; case KDB_DBG_ACCESS_RW: dbg_access = HW_BREAKPOINT_RW; break; default: return (EINVAL); } return (dbg_setup_watchpoint(NULL, addr, size, dbg_access)); } int kdb_cpu_clr_watchpoint(vm_offset_t addr, vm_size_t size) { return (dbg_remove_watchpoint(NULL, addr, size)); } #endif /* DDB || GDB */ #ifdef DDB +void +dbg_show_breakpoint(void) +{ + db_breakpoint_t bkpt; + uint32_t bcr; + uint64_t addr; + int i; + + db_printf("\nhardware breakpoints:\n"); + db_printf(" break status count address symbol\n"); + db_printf(" ----- -------- ----- ------------------ ------------------\n"); + for (i = 0; i < dbg_breakpoint_num; i++) { + bcr = dbg_wb_read_reg(DBG_REG_BASE_BCR, i); + if ((bcr & DBG_WB_CTRL_E) != 0) { + addr = dbg_wb_read_reg(DBG_REG_BASE_BVR, i); + bkpt = db_find_breakpoint_here(addr); + db_printf(" %-5d %-8s %-5d 0x%16lx ", + i, "enabled", bkpt == NULL ? -1 : bkpt->count, + addr); + db_printsym((db_addr_t)addr, DB_STGY_ANY); + db_printf("\n"); + } else { + db_printf(" %-5d disabled\n", i); + } + } +} + static const char * dbg_watchtype_str(uint32_t type) { switch (type) { case DBG_WATCH_CTRL_EXEC: return ("execute"); case DBG_WATCH_CTRL_STORE: return ("write"); case DBG_WATCH_CTRL_LOAD: return ("read"); case DBG_WATCH_CTRL_LOAD | DBG_WATCH_CTRL_STORE: return ("read/write"); default: return ("invalid"); } } static int dbg_watchtype_len(uint32_t len) { switch (len) { case DBG_WATCH_CTRL_LEN_1: return (1); case DBG_WATCH_CTRL_LEN_2: return (2); case DBG_WATCH_CTRL_LEN_4: return (4); case DBG_WATCH_CTRL_LEN_8: return (8); default: return (0); } } void dbg_show_watchpoint(void) { uint32_t wcr, len, type; uint64_t addr; int i; db_printf("\nhardware watchpoints:\n"); db_printf(" watch status type len address symbol\n"); db_printf(" ----- -------- ---------- --- ------------------ ------------------\n"); for (i = 0; i < dbg_watchpoint_num; i++) { wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i); if ((wcr & DBG_WB_CTRL_E) != 0) { type = DBG_WATCH_CTRL_ACCESS_MASK(wcr); len = DBG_WATCH_CTRL_LEN_MASK(wcr); addr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i); db_printf(" %-5d %-8s %10s %3d 0x%16lx ", i, "enabled", dbg_watchtype_str(type), dbg_watchtype_len(len), addr); db_printsym((db_addr_t)addr, DB_STGY_ANY); db_printf("\n"); } else { db_printf(" %-5d disabled\n", i); } } } #endif /* DDB */ static int dbg_find_free_slot(struct debug_monitor_state *monitor, enum dbg_t type) { uint64_t *reg; u_int max, i; switch(type) { case DBG_TYPE_BREAKPOINT: max = dbg_breakpoint_num; reg = monitor->dbg_bcr; break; case DBG_TYPE_WATCHPOINT: max = dbg_watchpoint_num; reg = monitor->dbg_wcr; break; default: printf("Unsupported debug type\n"); return (i); } for (i = 0; i < max; i++) { if ((reg[i] & DBG_WB_CTRL_E) == 0) return (i); } return (-1); } static int dbg_find_slot(struct debug_monitor_state *monitor, enum dbg_t type, vm_offset_t addr) { uint64_t *reg_addr, *reg_ctrl; u_int max, i; switch(type) { case DBG_TYPE_BREAKPOINT: max = dbg_breakpoint_num; reg_addr = monitor->dbg_bvr; reg_ctrl = monitor->dbg_bcr; break; case DBG_TYPE_WATCHPOINT: max = dbg_watchpoint_num; reg_addr = monitor->dbg_wvr; reg_ctrl = monitor->dbg_wcr; break; default: printf("Unsupported debug type\n"); return (i); } for (i = 0; i < max; i++) { if (reg_addr[i] == addr && (reg_ctrl[i] & DBG_WB_CTRL_E) != 0) return (i); } return (-1); } +static int +dbg_setup_breakpoint(struct debug_monitor_state *monitor, vm_offset_t addr) +{ + uint64_t bcr_priv; + u_int i; + + if (monitor == NULL) + monitor = &kernel_monitor; + + i = dbg_find_free_slot(monitor, DBG_TYPE_BREAKPOINT); + if (i == -1) { + printf("Can not find slot for breakpoint, max %d" + " breakpoints supported\n", dbg_breakpoint_num); + return (EBUSY); + } + + if ((monitor->dbg_flags & DBGMON_KERNEL) == 0) + bcr_priv = DBG_WB_CTRL_EL0; + else + bcr_priv = DBG_WB_CTRL_EL1; + + monitor->dbg_bvr[i] = addr; + monitor->dbg_bcr[i] = (0xf << 5) | bcr_priv | DBG_WB_CTRL_E; + monitor->dbg_enable_count++; + monitor->dbg_flags |= DBGMON_ENABLED; + dbg_register_sync(monitor); + + return (0); +} + +static int +dbg_remove_breakpoint(struct debug_monitor_state *monitor, vm_offset_t addr) +{ + u_int i; + + if (monitor == NULL) + monitor = &kernel_monitor; + + i = dbg_find_slot(monitor, DBG_TYPE_BREAKPOINT, addr); + if (i == -1) { + printf("Can not find breakpoint for address 0%lx\n", addr); + return (i); + } + + monitor->dbg_bvr[i] = 0; + monitor->dbg_bcr[i] = 0; + monitor->dbg_enable_count--; + if (monitor->dbg_enable_count == 0) + monitor->dbg_flags &= ~DBGMON_ENABLED; + dbg_register_sync(monitor); + + return (0); +} + static int dbg_setup_watchpoint(struct debug_monitor_state *monitor, vm_offset_t addr, vm_size_t size, enum dbg_access_t access) { uint64_t wcr_size, wcr_priv, wcr_access; u_int i; if (monitor == NULL) monitor = &kernel_monitor; i = dbg_find_free_slot(monitor, DBG_TYPE_WATCHPOINT); if (i == -1) { printf("Can not find slot for watchpoint, max %d" " watchpoints supported\n", dbg_watchpoint_num); return (EBUSY); } switch(size) { case 1: wcr_size = DBG_WATCH_CTRL_LEN_1; break; case 2: wcr_size = DBG_WATCH_CTRL_LEN_2; break; case 4: wcr_size = DBG_WATCH_CTRL_LEN_4; break; case 8: wcr_size = DBG_WATCH_CTRL_LEN_8; break; default: printf("Unsupported address size for watchpoint: %zu\n", size); return (EINVAL); } if ((monitor->dbg_flags & DBGMON_KERNEL) == 0) wcr_priv = DBG_WB_CTRL_EL0; else wcr_priv = DBG_WB_CTRL_EL1; switch(access) { case HW_BREAKPOINT_X: wcr_access = DBG_WATCH_CTRL_EXEC; break; case HW_BREAKPOINT_R: wcr_access = DBG_WATCH_CTRL_LOAD; break; case HW_BREAKPOINT_W: wcr_access = DBG_WATCH_CTRL_STORE; break; case HW_BREAKPOINT_RW: wcr_access = DBG_WATCH_CTRL_LOAD | DBG_WATCH_CTRL_STORE; break; default: printf("Unsupported access type for watchpoint: %d\n", access); return (EINVAL); } monitor->dbg_wvr[i] = addr; monitor->dbg_wcr[i] = wcr_size | wcr_access | wcr_priv | DBG_WB_CTRL_E; monitor->dbg_enable_count++; monitor->dbg_flags |= DBGMON_ENABLED; dbg_register_sync(monitor); return (0); } static int dbg_remove_watchpoint(struct debug_monitor_state *monitor, vm_offset_t addr, vm_size_t size) { u_int i; if (monitor == NULL) monitor = &kernel_monitor; i = dbg_find_slot(monitor, DBG_TYPE_WATCHPOINT, addr); if (i == -1) { printf("Can not find watchpoint for address 0%lx\n", addr); return (EINVAL); } monitor->dbg_wvr[i] = 0; monitor->dbg_wcr[i] = 0; monitor->dbg_enable_count--; if (monitor->dbg_enable_count == 0) monitor->dbg_flags &= ~DBGMON_ENABLED; dbg_register_sync(monitor); return (0); } void dbg_register_sync(struct debug_monitor_state *monitor) { uint64_t mdscr; int i; if (monitor == NULL) monitor = &kernel_monitor; for (i = 0; i < dbg_breakpoint_num; i++) { dbg_wb_write_reg(DBG_REG_BASE_BCR, i, monitor->dbg_bcr[i]); dbg_wb_write_reg(DBG_REG_BASE_BVR, i, monitor->dbg_bvr[i]); } for (i = 0; i < dbg_watchpoint_num; i++) { dbg_wb_write_reg(DBG_REG_BASE_WCR, i, monitor->dbg_wcr[i]); dbg_wb_write_reg(DBG_REG_BASE_WVR, i, monitor->dbg_wvr[i]); } mdscr = READ_SPECIALREG(mdscr_el1); if ((monitor->dbg_flags & DBGMON_ENABLED) == 0) { mdscr &= ~(MDSCR_MDE | MDSCR_KDE); } else { mdscr |= MDSCR_MDE; if ((monitor->dbg_flags & DBGMON_KERNEL) == DBGMON_KERNEL) mdscr |= MDSCR_KDE; } WRITE_SPECIALREG(mdscr_el1, mdscr); isb(); } void dbg_monitor_init(void) { uint64_t aa64dfr0; u_int i; /* Find out many breakpoints and watchpoints we can use */ aa64dfr0 = READ_SPECIALREG(id_aa64dfr0_el1); dbg_watchpoint_num = ID_AA64DFR0_WRPs_VAL(aa64dfr0); dbg_breakpoint_num = ID_AA64DFR0_BRPs_VAL(aa64dfr0); if (bootverbose && PCPU_GET(cpuid) == 0) { printf("%d watchpoints and %d breakpoints supported\n", dbg_watchpoint_num, dbg_breakpoint_num); } /* * We have limited number of {watch,break}points, each consists of * two registers: * - wcr/bcr regsiter configurates corresponding {watch,break}point * behaviour * - wvr/bvr register keeps address we are hunting for * * Reset all breakpoints and watchpoints. */ for (i = 0; i < dbg_watchpoint_num; i++) { dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0); dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0); } for (i = 0; i < dbg_breakpoint_num; i++) { dbg_wb_write_reg(DBG_REG_BASE_BCR, i, 0); dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0); } dbg_enable(); } void dbg_monitor_enter(struct thread *thread) { int i; if ((kernel_monitor.dbg_flags & DBGMON_ENABLED) != 0) { /* Install the kernel version of the registers */ dbg_register_sync(&kernel_monitor); } else if ((thread->td_pcb->pcb_dbg_regs.dbg_flags & DBGMON_ENABLED) != 0) { /* Disable the user breakpoints until we return to userspace */ for (i = 0; i < dbg_watchpoint_num; i++) { dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0); dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0); } for (i = 0; i < dbg_breakpoint_num; ++i) { dbg_wb_write_reg(DBG_REG_BASE_BCR, i, 0); dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0); } WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) & ~(MDSCR_MDE | MDSCR_KDE)); isb(); } } void dbg_monitor_exit(struct thread *thread, struct trapframe *frame) { int i; /* * PSR_D is an aarch64-only flag. On aarch32, it switches * the processor to big-endian, so avoid setting it for * 32bits binaries. */ if (!(SV_PROC_FLAG(thread->td_proc, SV_ILP32))) frame->tf_spsr |= PSR_D; if ((thread->td_pcb->pcb_dbg_regs.dbg_flags & DBGMON_ENABLED) != 0) { /* Install the thread's version of the registers */ dbg_register_sync(&thread->td_pcb->pcb_dbg_regs); frame->tf_spsr &= ~PSR_D; } else if ((kernel_monitor.dbg_flags & DBGMON_ENABLED) != 0) { /* Disable the kernel breakpoints until we re-enter */ for (i = 0; i < dbg_watchpoint_num; i++) { dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0); dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0); } for (i = 0; i < dbg_breakpoint_num; ++i) { dbg_wb_write_reg(DBG_REG_BASE_BCR, i, 0); dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0); } WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) & ~(MDSCR_MDE | MDSCR_KDE)); isb(); } } diff --git a/sys/arm64/arm64/gdb_machdep.c b/sys/arm64/arm64/gdb_machdep.c index 7b21675ea927..04c69e5f6079 100644 --- a/sys/arm64/arm64/gdb_machdep.c +++ b/sys/arm64/arm64/gdb_machdep.c @@ -1,129 +1,136 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2020 The FreeBSD Foundation * * This software was developed by Mitchell Horne under sponsorship from * the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include void * gdb_cpu_getreg(int regnum, size_t *regsz) { *regsz = gdb_cpu_regsz(regnum); if (kdb_thread == curthread) { switch (regnum) { case GDB_REG_LR: return (&kdb_frame->tf_lr); case GDB_REG_SP: return (&kdb_frame->tf_sp); case GDB_REG_PC: return (&kdb_frame->tf_elr); case GDB_REG_CSPR: return (&kdb_frame->tf_spsr); default: if (regnum >= GDB_REG_X0 && regnum <= GDB_REG_X29) return (&kdb_frame->tf_x[regnum - GDB_REG_X0]); break; } } switch (regnum) { case GDB_REG_SP: return (&kdb_thrctx->pcb_sp); case GDB_REG_PC: /* FALLTHROUGH */ case GDB_REG_LR: return (&kdb_thrctx->pcb_x[PCB_LR]); default: if (regnum >= GDB_REG_X19 && regnum <= GDB_REG_X29) return (&kdb_thrctx->pcb_x[regnum - GDB_REG_X19]); break; } return (NULL); } void gdb_cpu_setreg(int regnum, void *val) { register_t regval = *(register_t *)val; /* For curthread, keep the pcb and trapframe in sync. */ if (kdb_thread == curthread) { switch (regnum) { case GDB_REG_PC: kdb_frame->tf_elr = regval; break; case GDB_REG_SP: kdb_frame->tf_sp = regval; break; default: if (regnum >= GDB_REG_X0 && regnum <= GDB_REG_X29) { kdb_frame->tf_x[regnum] = regval; } break; } } switch (regnum) { case GDB_REG_PC: /* FALLTHROUGH */ case GDB_REG_LR: kdb_thrctx->pcb_x[PCB_LR] = regval; break; case GDB_REG_SP: kdb_thrctx->pcb_sp = regval; break; default: if (regnum >= GDB_REG_X19 && regnum <= GDB_REG_X29) { kdb_thrctx->pcb_x[regnum - GDB_REG_X19] = regval; } break; } } int gdb_cpu_signal(int type, int code __unused) { switch (type) { case EXCP_WATCHPT_EL1: case EXCP_SOFTSTP_EL1: case EXCP_BRKPT_EL1: case EXCP_BRK: return (SIGTRAP); } return (SIGEMT); } void gdb_cpu_stop_reason(int type, int code __unused) { - if (type == EXCP_WATCHPT_EL1) { + switch (type) { + case EXCP_WATCHPT_EL1: gdb_tx_str("watch:"); gdb_tx_varhex((uintmax_t)READ_SPECIALREG(far_el1)); gdb_tx_char(';'); + break; + case EXCP_BRKPT_EL1: + gdb_tx_str("hwbreak:;"); + break; + default: + break; } } diff --git a/sys/arm64/include/db_machdep.h b/sys/arm64/include/db_machdep.h index 45b97443aec5..5dc496ca851d 100644 --- a/sys/arm64/include/db_machdep.h +++ b/sys/arm64/include/db_machdep.h @@ -1,126 +1,129 @@ /*- * Copyright (c) 2014 Andrew Turner * Copyright (c) 2014-2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef _MACHINE_DB_MACHDEP_H_ #define _MACHINE_DB_MACHDEP_H_ #include #include #include #define T_BREAKPOINT (EXCP_BRK) #define T_HW_BREAKPOINT (EXCP_BRKPT_EL1) #define T_SINGLESTEP (EXCP_SOFTSTP_EL1) #define T_WATCHPOINT (EXCP_WATCHPT_EL1) +#define HAS_HW_BREAKPOINT +#define NHBREAKPOINTS 16 + typedef vm_offset_t db_addr_t; typedef long db_expr_t; #define PC_REGS() ((db_addr_t)kdb_thrctx->pcb_x[PCB_LR]) #define BKPT_INST (0xd4200000) #define BKPT_SIZE (4) #define BKPT_SET(inst) (BKPT_INST) #define BKPT_SKIP do { \ kdb_frame->tf_elr += BKPT_SIZE; \ kdb_thrctx->pcb_x[PCB_LR] += BKPT_SIZE; \ } while (0) #define db_clear_single_step kdb_cpu_clear_singlestep #define db_set_single_step kdb_cpu_set_singlestep #define IS_BREAKPOINT_TRAP(type, code) \ (type == T_BREAKPOINT || type == T_HW_BREAKPOINT) #define IS_SSTEP_TRAP(type, code) (type == T_SINGLESTEP) #define IS_WATCHPOINT_TRAP(type, code) (type == T_WATCHPOINT) #define inst_trap_return(ins) (0) /* ret */ #define inst_return(ins) (((ins) & 0xfffffc1fu) == 0xd65f0000) #define inst_call(ins) (((ins) & 0xfc000000u) == 0x94000000u || /* BL */ \ ((ins) & 0xfffffc1fu) == 0xd63f0000u) /* BLR */ #define inst_load(ins) ({ \ uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \ is_load_instr(tmp_instr); \ }) #define inst_store(ins) ({ \ uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \ is_store_instr(tmp_instr); \ }) #define is_load_instr(ins) ((((ins) & 0x3b000000u) == 0x18000000u) || /* literal */ \ (((ins) & 0x3f400000u) == 0x08400000u) || /* exclusive */ \ (((ins) & 0x3bc00000u) == 0x28400000u) || /* no-allocate pair */ \ ((((ins) & 0x3b200c00u) == 0x38000400u) && \ (((ins) & 0x3be00c00u) != 0x38000400u) && \ (((ins) & 0xffe00c00u) != 0x3c800400u)) || /* immediate post-indexed */ \ ((((ins) & 0x3b200c00u) == 0x38000c00u) && \ (((ins) & 0x3be00c00u) != 0x38000c00u) && \ (((ins) & 0xffe00c00u) != 0x3c800c00u)) || /* immediate pre-indexed */ \ ((((ins) & 0x3b200c00u) == 0x38200800u) && \ (((ins) & 0x3be00c00u) != 0x38200800u) && \ (((ins) & 0xffe00c00u) != 0x3ca00c80u)) || /* register offset */ \ ((((ins) & 0x3b200c00u) == 0x38000800u) && \ (((ins) & 0x3be00c00u) != 0x38000800u)) || /* unprivileged */ \ ((((ins) & 0x3b200c00u) == 0x38000000u) && \ (((ins) & 0x3be00c00u) != 0x38000000u) && \ (((ins) & 0xffe00c00u) != 0x3c800000u)) || /* unscaled immediate */ \ ((((ins) & 0x3b000000u) == 0x39000000u) && \ (((ins) & 0x3bc00000u) != 0x39000000u) && \ (((ins) & 0xffc00000u) != 0x3d800000u)) || /* unsigned immediate */ \ (((ins) & 0x3bc00000u) == 0x28400000u) || /* pair (offset) */ \ (((ins) & 0x3bc00000u) == 0x28c00000u) || /* pair (post-indexed) */ \ (((ins) & 0x3bc00000u) == 0x29800000u)) /* pair (pre-indexed) */ #define is_store_instr(ins) ((((ins) & 0x3f400000u) == 0x08000000u) || /* exclusive */ \ (((ins) & 0x3bc00000u) == 0x28000000u) || /* no-allocate pair */ \ ((((ins) & 0x3be00c00u) == 0x38000400u) || \ (((ins) & 0xffe00c00u) == 0x3c800400u)) || /* immediate post-indexed */ \ ((((ins) & 0x3be00c00u) == 0x38000c00u) || \ (((ins) & 0xffe00c00u) == 0x3c800c00u)) || /* immediate pre-indexed */ \ ((((ins) & 0x3be00c00u) == 0x38200800u) || \ (((ins) & 0xffe00c00u) == 0x3ca00800u)) || /* register offset */ \ (((ins) & 0x3be00c00u) == 0x38000800u) || /* unprivileged */ \ ((((ins) & 0x3be00c00u) == 0x38000000u) || \ (((ins) & 0xffe00c00u) == 0x3c800000u)) || /* unscaled immediate */ \ ((((ins) & 0x3bc00000u) == 0x39000000u) || \ (((ins) & 0xffc00000u) == 0x3d800000u)) || /* unsigned immediate */ \ (((ins) & 0x3bc00000u) == 0x28000000u) || /* pair (offset) */ \ (((ins) & 0x3bc00000u) == 0x28800000u) || /* pair (post-indexed) */ \ (((ins) & 0x3bc00000u) == 0x29800000u)) /* pair (pre-indexed) */ #define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + 4)) #define DB_ELFSIZE 64 #endif /* !_MACHINE_DB_MACHDEP_H_ */ diff --git a/sys/arm64/include/debug_monitor.h b/sys/arm64/include/debug_monitor.h index 578e90db7f12..8698f21a7c2a 100644 --- a/sys/arm64/include/debug_monitor.h +++ b/sys/arm64/include/debug_monitor.h @@ -1,64 +1,65 @@ /*- * Copyright (c) 2014 The FreeBSD Foundation * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef _MACHINE_DEBUG_MONITOR_H_ #define _MACHINE_DEBUG_MONITOR_H_ #define DBG_BRP_MAX 16 #define DBG_WRP_MAX 16 struct debug_monitor_state { uint32_t dbg_enable_count; uint32_t dbg_flags; #define DBGMON_ENABLED (1 << 0) #define DBGMON_KERNEL (1 << 1) uint64_t dbg_bcr[DBG_BRP_MAX]; uint64_t dbg_bvr[DBG_BRP_MAX]; uint64_t dbg_wcr[DBG_WRP_MAX]; uint64_t dbg_wvr[DBG_WRP_MAX]; }; #ifdef _KERNEL enum dbg_access_t { HW_BREAKPOINT_X = 0, HW_BREAKPOINT_R = 1, HW_BREAKPOINT_W = 2, HW_BREAKPOINT_RW = HW_BREAKPOINT_R | HW_BREAKPOINT_W, }; void dbg_monitor_init(void); void dbg_register_sync(struct debug_monitor_state *); #ifdef DDB +void dbg_show_breakpoint(void); void dbg_show_watchpoint(void); #endif #endif /* _KERNEL */ #endif /* _MACHINE_DEBUG_MONITOR_H_ */ diff --git a/sys/arm64/include/kdb.h b/sys/arm64/include/kdb.h index aa36e7e756f9..3148b7df7d1b 100644 --- a/sys/arm64/include/kdb.h +++ b/sys/arm64/include/kdb.h @@ -1,55 +1,57 @@ /*- * Copyright (c) 2014 Andrew Turner * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef _MACHINE_KDB_H_ #define _MACHINE_KDB_H_ #include #define KDB_STOPPEDPCB(pc) &stoppcbs[pc->pc_cpuid] void kdb_cpu_clear_singlestep(void); void kdb_cpu_set_singlestep(void); +int kdb_cpu_set_breakpoint(vm_offset_t addr); +int kdb_cpu_clr_breakpoint(vm_offset_t addr); int kdb_cpu_set_watchpoint(vm_offset_t addr, size_t size, int access); int kdb_cpu_clr_watchpoint(vm_offset_t addr, size_t size); static __inline void kdb_cpu_sync_icache(unsigned char *addr, size_t size) { cpu_icache_sync_range(addr, size); } static __inline void kdb_cpu_trap(int type, int code) { } #endif /* _MACHINE_KDB_H_ */