diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c index c598d9e17847..555b2be9fc4a 100644 --- a/lib/libpmc/libpmc.c +++ b/lib/libpmc/libpmc.c @@ -1,3961 +1,1865 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2003-2008 Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "libpmcinternal.h" /* Function prototypes */ -#if defined(__i386__) -static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -#endif #if defined(__amd64__) || defined(__i386__) -static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); -static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -#endif -#if defined(__i386__) -static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); #endif #if defined(__amd64__) || defined(__i386__) static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif #if defined(__arm__) #if defined(__XSCALE__) static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif #if defined(__aarch64__) static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif #if defined(__mips__) static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif /* __mips__ */ static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #if defined(__powerpc__) static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif /* __powerpc__ */ #define PMC_CALL(cmd, params) \ syscall(pmc_syscall, PMC_OP_##cmd, (params)) /* * Event aliases provide a way for the user to ask for generic events * like "cache-misses", or "instructions-retired". These aliases are * mapped to the appropriate canonical event descriptions using a * lookup table. */ struct pmc_event_alias { const char *pm_alias; const char *pm_spec; }; static const struct pmc_event_alias *pmc_mdep_event_aliases; /* * The pmc_event_descr structure maps symbolic names known to the user * to integer codes used by the PMC KLD. */ struct pmc_event_descr { const char *pm_ev_name; enum pmc_event pm_ev_code; }; /* * The pmc_class_descr structure maps class name prefixes for * event names to event tables and other PMC class data. */ struct pmc_class_descr { const char *pm_evc_name; size_t pm_evc_name_size; enum pmc_class pm_evc_class; const struct pmc_event_descr *pm_evc_event_table; size_t pm_evc_event_table_size; int (*pm_evc_allocate_pmc)(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pa); }; #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) #undef __PMC_EV #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, /* * PMC_CLASSDEP_TABLE(NAME, CLASS) * * Define a table mapping event names and aliases to HWPMC event IDs. */ #define PMC_CLASSDEP_TABLE(N, C) \ static const struct pmc_event_descr N##_event_table[] = \ { \ __PMC_EV_##C() \ } PMC_CLASSDEP_TABLE(iaf, IAF); -PMC_CLASSDEP_TABLE(k7, K7); PMC_CLASSDEP_TABLE(k8, K8); -PMC_CLASSDEP_TABLE(p4, P4); -PMC_CLASSDEP_TABLE(p5, P5); -PMC_CLASSDEP_TABLE(p6, P6); PMC_CLASSDEP_TABLE(xscale, XSCALE); PMC_CLASSDEP_TABLE(armv7, ARMV7); PMC_CLASSDEP_TABLE(armv8, ARMV8); PMC_CLASSDEP_TABLE(mips24k, MIPS24K); PMC_CLASSDEP_TABLE(mips74k, MIPS74K); PMC_CLASSDEP_TABLE(octeon, OCTEON); -PMC_CLASSDEP_TABLE(ucf, UCF); PMC_CLASSDEP_TABLE(ppc7450, PPC7450); PMC_CLASSDEP_TABLE(ppc970, PPC970); PMC_CLASSDEP_TABLE(e500, E500); static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; #undef __PMC_EV_ALIAS #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, -static const struct pmc_event_descr atom_event_table[] = -{ - __PMC_EV_ALIAS_ATOM() -}; - -static const struct pmc_event_descr atom_silvermont_event_table[] = -{ - __PMC_EV_ALIAS_ATOM_SILVERMONT() -}; - -static const struct pmc_event_descr core_event_table[] = -{ - __PMC_EV_ALIAS_CORE() -}; - - -static const struct pmc_event_descr core2_event_table[] = -{ - __PMC_EV_ALIAS_CORE2() -}; - -static const struct pmc_event_descr corei7_event_table[] = -{ - __PMC_EV_ALIAS_COREI7() -}; - -static const struct pmc_event_descr nehalem_ex_event_table[] = -{ - __PMC_EV_ALIAS_COREI7() -}; - -static const struct pmc_event_descr haswell_event_table[] = -{ - __PMC_EV_ALIAS_HASWELL() -}; - -static const struct pmc_event_descr haswell_xeon_event_table[] = -{ - __PMC_EV_ALIAS_HASWELL_XEON() -}; - -static const struct pmc_event_descr broadwell_event_table[] = -{ - __PMC_EV_ALIAS_BROADWELL() -}; - -static const struct pmc_event_descr broadwell_xeon_event_table[] = -{ - __PMC_EV_ALIAS_BROADWELL_XEON() -}; - -static const struct pmc_event_descr skylake_event_table[] = -{ - __PMC_EV_ALIAS_SKYLAKE() -}; - -static const struct pmc_event_descr skylake_xeon_event_table[] = -{ - __PMC_EV_ALIAS_SKYLAKE_XEON() -}; - -static const struct pmc_event_descr ivybridge_event_table[] = -{ - __PMC_EV_ALIAS_IVYBRIDGE() -}; - -static const struct pmc_event_descr ivybridge_xeon_event_table[] = -{ - __PMC_EV_ALIAS_IVYBRIDGE_XEON() -}; - -static const struct pmc_event_descr sandybridge_event_table[] = -{ - __PMC_EV_ALIAS_SANDYBRIDGE() -}; - -static const struct pmc_event_descr sandybridge_xeon_event_table[] = -{ - __PMC_EV_ALIAS_SANDYBRIDGE_XEON() -}; - -static const struct pmc_event_descr westmere_event_table[] = -{ - __PMC_EV_ALIAS_WESTMERE() -}; - -static const struct pmc_event_descr westmere_ex_event_table[] = -{ - __PMC_EV_ALIAS_WESTMERE() -}; - -static const struct pmc_event_descr corei7uc_event_table[] = -{ - __PMC_EV_ALIAS_COREI7UC() -}; - -static const struct pmc_event_descr haswelluc_event_table[] = -{ - __PMC_EV_ALIAS_HASWELLUC() -}; - -static const struct pmc_event_descr broadwelluc_event_table[] = -{ - __PMC_EV_ALIAS_BROADWELLUC() -}; - -static const struct pmc_event_descr sandybridgeuc_event_table[] = -{ - __PMC_EV_ALIAS_SANDYBRIDGEUC() -}; - -static const struct pmc_event_descr westmereuc_event_table[] = -{ - __PMC_EV_ALIAS_WESTMEREUC() -}; - static const struct pmc_event_descr cortex_a8_event_table[] = { __PMC_EV_ALIAS_ARMV7_CORTEX_A8() }; static const struct pmc_event_descr cortex_a9_event_table[] = { __PMC_EV_ALIAS_ARMV7_CORTEX_A9() }; static const struct pmc_event_descr cortex_a53_event_table[] = { __PMC_EV_ALIAS_ARMV8_CORTEX_A53() }; static const struct pmc_event_descr cortex_a57_event_table[] = { __PMC_EV_ALIAS_ARMV8_CORTEX_A57() }; /* * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) * * Map a CPU to the PMC classes it supports. */ #define PMC_MDEP_TABLE(N,C,...) \ static const enum pmc_class N##_pmc_classes[] = { \ PMC_CLASS_##C, __VA_ARGS__ \ } -PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); -PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(broadwell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(broadwell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(skylake, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(skylake_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); -PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); -PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); -PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); PMC_MDEP_TABLE(cortex_a53, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); PMC_MDEP_TABLE(cortex_a57, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K); PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450, PMC_CLASS_TSC); PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970, PMC_CLASS_TSC); PMC_MDEP_TABLE(e500, E500, PMC_CLASS_SOFT, PMC_CLASS_E500, PMC_CLASS_TSC); PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); static const struct pmc_event_descr tsc_event_table[] = { __PMC_EV_TSC() }; #undef PMC_CLASS_TABLE_DESC #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ static const struct pmc_class_descr NAME##_class_table_descr = \ { \ .pm_evc_name = #CLASS "-", \ .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ .pm_evc_class = PMC_CLASS_##CLASS , \ .pm_evc_event_table = EVENTS##_event_table , \ .pm_evc_event_table_size = \ PMC_EVENT_TABLE_SIZE(EVENTS), \ .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ } -#if defined(__i386__) || defined(__amd64__) -PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); -PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); -PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap); -PMC_CLASS_TABLE_DESC(core, IAP, core, iap); -PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); -PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); -PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap); -PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); -PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap); -PMC_CLASS_TABLE_DESC(broadwell, IAP, broadwell, iap); -PMC_CLASS_TABLE_DESC(broadwell_xeon, IAP, broadwell_xeon, iap); -PMC_CLASS_TABLE_DESC(skylake, IAP, skylake, iap); -PMC_CLASS_TABLE_DESC(skylake_xeon, IAP, skylake_xeon, iap); -PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); -PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); -PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); -PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); -PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); -PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap); -PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); -PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); -PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); -PMC_CLASS_TABLE_DESC(broadwelluc, UCP, broadwelluc, ucp); -PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); -PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); -#endif -#if defined(__i386__) -PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); -#endif #if defined(__i386__) || defined(__amd64__) PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); -PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); -#endif -#if defined(__i386__) -PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); -PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); #endif #if defined(__i386__) || defined(__amd64__) PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); #endif #if defined(__arm__) #if defined(__XSCALE__) PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); #endif PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7); PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7); #endif #if defined(__aarch64__) PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64); PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64); #endif #if defined(__mips__) PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips); PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); #endif /* __mips__ */ #if defined(__powerpc__) PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc); #endif static struct pmc_class_descr soft_class_table_descr = { .pm_evc_name = "SOFT-", .pm_evc_name_size = sizeof("SOFT-") - 1, .pm_evc_class = PMC_CLASS_SOFT, .pm_evc_event_table = NULL, .pm_evc_event_table_size = 0, .pm_evc_allocate_pmc = soft_allocate_pmc }; #undef PMC_CLASS_TABLE_DESC static const struct pmc_class_descr **pmc_class_table; #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass static const enum pmc_class *pmc_mdep_class_list; static size_t pmc_mdep_class_list_size; /* * Mapping tables, mapping enumeration values to human readable * strings. */ static const char * pmc_capability_names[] = { #undef __PMC_CAP #define __PMC_CAP(N,V,D) #N , __PMC_CAPS() }; struct pmc_class_map { enum pmc_class pm_class; const char *pm_name; }; static const struct pmc_class_map pmc_class_names[] = { #undef __PMC_CLASS #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } , __PMC_CLASSES() }; struct pmc_cputype_map { enum pmc_cputype pm_cputype; const char *pm_name; }; static const struct pmc_cputype_map pmc_cputype_names[] = { #undef __PMC_CPU #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , __PMC_CPUS() }; static const char * pmc_disposition_names[] = { #undef __PMC_DISP #define __PMC_DISP(D) #D , __PMC_DISPOSITIONS() }; static const char * pmc_mode_names[] = { #undef __PMC_MODE #define __PMC_MODE(M,N) #M , __PMC_MODES() }; static const char * pmc_state_names[] = { #undef __PMC_STATE #define __PMC_STATE(S) #S , __PMC_STATES() }; /* * Filled in by pmc_init(). */ static int pmc_syscall = -1; static struct pmc_cpuinfo cpu_info; static struct pmc_op_getdyneventinfo soft_event_info; /* Event masks for events */ struct pmc_masks { const char *pm_name; const uint64_t pm_value; }; #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } #define NULLMASK { .pm_name = NULL } #if defined(__amd64__) || defined(__i386__) static int pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) { const struct pmc_masks *pm; char *q, *r; int c; if (pmask == NULL) /* no mask keywords */ return (-1); q = strchr(p, '='); /* skip '=' */ if (*++q == '\0') /* no more data */ return (-1); c = 0; /* count of mask keywords seen */ while ((r = strsep(&q, "+")) != NULL) { for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); pm++) ; if (pm->pm_name == NULL) /* not found */ return (-1); *evmask |= pm->pm_value; c++; } return (c); } #endif #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } -#if defined(__i386__) - -/* - * AMD K7 (Athlon) CPUs. - */ - -static struct pmc_event_alias k7_aliases[] = { - EV_ALIAS("branches", "k7-retired-branches"), - EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), - EV_ALIAS("cycles", "tsc"), - EV_ALIAS("dc-misses", "k7-dc-misses"), - EV_ALIAS("ic-misses", "k7-ic-misses"), - EV_ALIAS("instructions", "k7-retired-instructions"), - EV_ALIAS("interrupts", "k7-hardware-interrupts"), - EV_ALIAS(NULL, NULL) -}; - -#define K7_KW_COUNT "count" -#define K7_KW_EDGE "edge" -#define K7_KW_INV "inv" -#define K7_KW_OS "os" -#define K7_KW_UNITMASK "unitmask" -#define K7_KW_USR "usr" - -static int -k7_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - char *e, *p, *q; - int c, has_unitmask; - uint32_t count, unitmask; - - pmc_config->pm_md.pm_amd.pm_amd_config = 0; - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - - if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || - pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || - pe == PMC_EV_K7_DC_WRITEBACKS) { - has_unitmask = 1; - unitmask = AMD_PMC_UNITMASK_MOESI; - } else - unitmask = has_unitmask = 0; - - while ((p = strsep(&ctrspec, ",")) != NULL) { - if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - - pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_amd.pm_amd_config |= - AMD_PMC_TO_COUNTER(count); - - } else if (KWMATCH(p, K7_KW_EDGE)) { - pmc_config->pm_caps |= PMC_CAP_EDGE; - } else if (KWMATCH(p, K7_KW_INV)) { - pmc_config->pm_caps |= PMC_CAP_INVERT; - } else if (KWMATCH(p, K7_KW_OS)) { - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { - if (has_unitmask == 0) - return (-1); - unitmask = 0; - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - while ((c = tolower(*q++)) != 0) - if (c == 'm') - unitmask |= AMD_PMC_UNITMASK_M; - else if (c == 'o') - unitmask |= AMD_PMC_UNITMASK_O; - else if (c == 'e') - unitmask |= AMD_PMC_UNITMASK_E; - else if (c == 's') - unitmask |= AMD_PMC_UNITMASK_S; - else if (c == 'i') - unitmask |= AMD_PMC_UNITMASK_I; - else if (c == '+') - continue; - else - return (-1); - - if (unitmask == 0) - return (-1); - - } else if (KWMATCH(p, K7_KW_USR)) { - pmc_config->pm_caps |= PMC_CAP_USER; - } else - return (-1); - } - - if (has_unitmask) { - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - pmc_config->pm_md.pm_amd.pm_amd_config |= - AMD_PMC_TO_UNITMASK(unitmask); - } - - return (0); - -} - -#endif - #if defined(__amd64__) || defined(__i386__) - -/* - * Intel Core (Family 6, Model E) PMCs. - */ - -static struct pmc_event_alias core_aliases[] = { - EV_ALIAS("branches", "iap-br-instr-ret"), - EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), - EV_ALIAS("cycles", "tsc-tsc"), - EV_ALIAS("ic-misses", "iap-icache-misses"), - EV_ALIAS("instructions", "iap-instr-ret"), - EV_ALIAS("interrupts", "iap-core-hw-int-rx"), - EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), - EV_ALIAS(NULL, NULL) -}; - /* - * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) - * and Atom (Family 6, model 1CH) PMCs. + * AMD K8 PMCs. * - * We map aliases to events on the fixed-function counters if these - * are present. Note that not all CPUs in this family contain fixed-function - * counters. */ -static struct pmc_event_alias core2_aliases[] = { - EV_ALIAS("branches", "iap-br-inst-retired.any"), - EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), - EV_ALIAS("cycles", "tsc-tsc"), - EV_ALIAS("ic-misses", "iap-l1i-misses"), - EV_ALIAS("instructions", "iaf-instr-retired.any"), - EV_ALIAS("interrupts", "iap-hw-int-rcv"), - EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), - EV_ALIAS(NULL, NULL) -}; - -static struct pmc_event_alias core2_aliases_without_iaf[] = { - EV_ALIAS("branches", "iap-br-inst-retired.any"), - EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), - EV_ALIAS("cycles", "tsc-tsc"), - EV_ALIAS("ic-misses", "iap-l1i-misses"), - EV_ALIAS("instructions", "iap-inst-retired.any_p"), - EV_ALIAS("interrupts", "iap-hw-int-rcv"), - EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), +static struct pmc_event_alias k8_aliases[] = { + EV_ALIAS("branches", "k8-fr-retired-taken-branches"), + EV_ALIAS("branch-mispredicts", + "k8-fr-retired-taken-branches-mispredicted"), + EV_ALIAS("cycles", "tsc"), + EV_ALIAS("dc-misses", "k8-dc-miss"), + EV_ALIAS("ic-misses", "k8-ic-miss"), + EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), + EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), + EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), EV_ALIAS(NULL, NULL) }; -#define atom_aliases core2_aliases -#define atom_aliases_without_iaf core2_aliases_without_iaf -#define atom_silvermont_aliases core2_aliases -#define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf -#define corei7_aliases core2_aliases -#define corei7_aliases_without_iaf core2_aliases_without_iaf -#define nehalem_ex_aliases core2_aliases -#define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf -#define haswell_aliases core2_aliases -#define haswell_aliases_without_iaf core2_aliases_without_iaf -#define haswell_xeon_aliases core2_aliases -#define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf -#define broadwell_aliases core2_aliases -#define broadwell_aliases_without_iaf core2_aliases_without_iaf -#define broadwell_xeon_aliases core2_aliases -#define broadwell_xeon_aliases_without_iaf core2_aliases_without_iaf -#define skylake_aliases core2_aliases -#define skylake_aliases_without_iaf core2_aliases_without_iaf -#define skylake_xeon_aliases core2_aliases -#define skylake_xeon_aliases_without_iaf core2_aliases_without_iaf -#define ivybridge_aliases core2_aliases -#define ivybridge_aliases_without_iaf core2_aliases_without_iaf -#define ivybridge_xeon_aliases core2_aliases -#define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf -#define sandybridge_aliases core2_aliases -#define sandybridge_aliases_without_iaf core2_aliases_without_iaf -#define sandybridge_xeon_aliases core2_aliases -#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf -#define westmere_aliases core2_aliases -#define westmere_aliases_without_iaf core2_aliases_without_iaf -#define westmere_ex_aliases core2_aliases -#define westmere_ex_aliases_without_iaf core2_aliases_without_iaf - -#define IAF_KW_OS "os" -#define IAF_KW_USR "usr" -#define IAF_KW_ANYTHREAD "anythread" - -/* - * Parse an event specifier for Intel fixed function counters. - */ -static int -iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - char *p; - - (void) pe; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; - - while ((p = strsep(&ctrspec, ",")) != NULL) { - if (KWMATCH(p, IAF_KW_OS)) - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - else if (KWMATCH(p, IAF_KW_USR)) - pmc_config->pm_caps |= PMC_CAP_USER; - else if (KWMATCH(p, IAF_KW_ANYTHREAD)) - pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; - else - return (-1); - } - - return (0); -} +#define __K8MASK(N,V) PMCMASK(N,(1 << (V))) /* - * Core/Core2 support. + * Parsing tables */ -#define IAP_KW_AGENT "agent" -#define IAP_KW_ANYTHREAD "anythread" -#define IAP_KW_CACHESTATE "cachestate" -#define IAP_KW_CMASK "cmask" -#define IAP_KW_CORE "core" -#define IAP_KW_EDGE "edge" -#define IAP_KW_INV "inv" -#define IAP_KW_OS "os" -#define IAP_KW_PREFETCH "prefetch" -#define IAP_KW_SNOOPRESPONSE "snoopresponse" -#define IAP_KW_SNOOPTYPE "snooptype" -#define IAP_KW_TRANSITION "trans" -#define IAP_KW_USR "usr" -#define IAP_KW_RSP "rsp" - -static struct pmc_masks iap_core_mask[] = { - PMCMASK(all, (0x3 << 14)), - PMCMASK(this, (0x1 << 14)), +/* fp dispatched fpu ops */ +static const struct pmc_masks k8_mask_fdfo[] = { + __K8MASK(add-pipe-excluding-junk-ops, 0), + __K8MASK(multiply-pipe-excluding-junk-ops, 1), + __K8MASK(store-pipe-excluding-junk-ops, 2), + __K8MASK(add-pipe-junk-ops, 3), + __K8MASK(multiply-pipe-junk-ops, 4), + __K8MASK(store-pipe-junk-ops, 5), NULLMASK }; -static struct pmc_masks iap_agent_mask[] = { - PMCMASK(this, 0), - PMCMASK(any, (0x1 << 13)), +/* ls segment register loads */ +static const struct pmc_masks k8_mask_lsrl[] = { + __K8MASK(es, 0), + __K8MASK(cs, 1), + __K8MASK(ss, 2), + __K8MASK(ds, 3), + __K8MASK(fs, 4), + __K8MASK(gs, 5), + __K8MASK(hs, 6), NULLMASK }; -static struct pmc_masks iap_prefetch_mask[] = { - PMCMASK(both, (0x3 << 12)), - PMCMASK(only, (0x1 << 12)), - PMCMASK(exclude, 0), +/* ls locked operation */ +static const struct pmc_masks k8_mask_llo[] = { + __K8MASK(locked-instructions, 0), + __K8MASK(cycles-in-request, 1), + __K8MASK(cycles-to-complete, 2), NULLMASK }; -static struct pmc_masks iap_cachestate_mask[] = { - PMCMASK(i, (1 << 8)), - PMCMASK(s, (1 << 9)), - PMCMASK(e, (1 << 10)), - PMCMASK(m, (1 << 11)), +/* dc refill from {l2,system} and dc copyback */ +static const struct pmc_masks k8_mask_dc[] = { + __K8MASK(invalid, 0), + __K8MASK(shared, 1), + __K8MASK(exclusive, 2), + __K8MASK(owner, 3), + __K8MASK(modified, 4), NULLMASK }; -static struct pmc_masks iap_snoopresponse_mask[] = { - PMCMASK(clean, (1 << 8)), - PMCMASK(hit, (1 << 9)), - PMCMASK(hitm, (1 << 11)), +/* dc one bit ecc error */ +static const struct pmc_masks k8_mask_dobee[] = { + __K8MASK(scrubber, 0), + __K8MASK(piggyback, 1), NULLMASK }; -static struct pmc_masks iap_snooptype_mask[] = { - PMCMASK(cmp2s, (1 << 8)), - PMCMASK(cmp2i, (1 << 9)), +/* dc dispatched prefetch instructions */ +static const struct pmc_masks k8_mask_ddpi[] = { + __K8MASK(load, 0), + __K8MASK(store, 1), + __K8MASK(nta, 2), NULLMASK }; -static struct pmc_masks iap_transition_mask[] = { - PMCMASK(any, 0x00), - PMCMASK(frequency, 0x10), +/* dc dcache accesses by locks */ +static const struct pmc_masks k8_mask_dabl[] = { + __K8MASK(accesses, 0), + __K8MASK(misses, 1), NULLMASK }; -static struct pmc_masks iap_rsp_mask_i7_wm[] = { - PMCMASK(DMND_DATA_RD, (1 << 0)), - PMCMASK(DMND_RFO, (1 << 1)), - PMCMASK(DMND_IFETCH, (1 << 2)), - PMCMASK(WB, (1 << 3)), - PMCMASK(PF_DATA_RD, (1 << 4)), - PMCMASK(PF_RFO, (1 << 5)), - PMCMASK(PF_IFETCH, (1 << 6)), - PMCMASK(OTHER, (1 << 7)), - PMCMASK(UNCORE_HIT, (1 << 8)), - PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), - PMCMASK(OTHER_CORE_HITM, (1 << 10)), - PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), - PMCMASK(REMOTE_DRAM, (1 << 13)), - PMCMASK(LOCAL_DRAM, (1 << 14)), - PMCMASK(NON_DRAM, (1 << 15)), +/* bu internal l2 request */ +static const struct pmc_masks k8_mask_bilr[] = { + __K8MASK(ic-fill, 0), + __K8MASK(dc-fill, 1), + __K8MASK(tlb-reload, 2), + __K8MASK(tag-snoop, 3), + __K8MASK(cancelled, 4), NULLMASK }; -static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { - PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), - PMCMASK(REQ_DMND_RFO, (1ULL << 1)), - PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), - PMCMASK(REQ_WB, (1ULL << 3)), - PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), - PMCMASK(REQ_PF_RFO, (1ULL << 5)), - PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), - PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)), - PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)), - PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)), - PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)), - PMCMASK(REQ_STRM_ST, (1ULL << 11)), - PMCMASK(REQ_OTHER, (1ULL << 15)), - PMCMASK(RES_ANY, (1ULL << 16)), - PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), - PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), - PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), - PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), - PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), - PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), - PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), - PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), - PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), - PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), - PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), - PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), - PMCMASK(RES_NON_DRAM, (1ULL << 37)), +/* bu fill request l2 miss */ +static const struct pmc_masks k8_mask_bfrlm[] = { + __K8MASK(ic-fill, 0), + __K8MASK(dc-fill, 1), + __K8MASK(tlb-reload, 2), NULLMASK }; -/* Broadwell is defined to use the same mask as Haswell */ -static struct pmc_masks iap_rsp_mask_haswell[] = { - PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), - PMCMASK(REQ_DMND_RFO, (1ULL << 1)), - PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), - PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), - PMCMASK(REQ_PF_RFO, (1ULL << 5)), - PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), - PMCMASK(REQ_OTHER, (1ULL << 15)), - PMCMASK(RES_ANY, (1ULL << 16)), - PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), - PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), - PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), - PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), - PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), - PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), - /* - * For processor type 06_45H 22 is L4_HIT_LOCAL_L4 - * and 23, 24 and 25 are also defined. - */ - PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), - PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), - PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), - PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), - PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), - PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), - PMCMASK(RES_NON_DRAM, (1ULL << 37)), +/* bu fill into l2 */ +static const struct pmc_masks k8_mask_bfil[] = { + __K8MASK(dirty-l2-victim, 0), + __K8MASK(victim-from-l2, 1), NULLMASK }; -static struct pmc_masks iap_rsp_mask_skylake[] = { - PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), - PMCMASK(REQ_DMND_RFO, (1ULL << 1)), - PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), - PMCMASK(REQ_PF_DATA_RD, (1ULL << 7)), - PMCMASK(REQ_PF_RFO, (1ULL << 8)), - PMCMASK(REQ_STRM_ST, (1ULL << 11)), - PMCMASK(REQ_OTHER, (1ULL << 15)), - PMCMASK(RES_ANY, (1ULL << 16)), - PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), - PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), - PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), - PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), - PMCMASK(RES_SUPPLIER_L4_HIT, (1ULL << 22)), - PMCMASK(RES_SUPPLIER_DRAM, (1ULL << 26)), - PMCMASK(RES_SUPPLIER_SPL_HIT, (1ULL << 30)), - PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), - PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), - PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), - PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), - PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), - PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), - PMCMASK(RES_NON_DRAM, (1ULL << 37)), +/* fr retired fpu instructions */ +static const struct pmc_masks k8_mask_frfi[] = { + __K8MASK(x87, 0), + __K8MASK(mmx-3dnow, 1), + __K8MASK(packed-sse-sse2, 2), + __K8MASK(scalar-sse-sse2, 3), NULLMASK }; - -static int -iap_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - char *e, *p, *q; - uint64_t cachestate, evmask, rsp; - int count, n; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | - PMC_CAP_QUALIFIER); - pmc_config->pm_md.pm_iap.pm_iap_config = 0; - - cachestate = evmask = rsp = 0; - - /* Parse additional modifiers if present */ - while ((p = strsep(&ctrspec, ",")) != NULL) { - - n = 0; - if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_iap.pm_iap_config |= - IAP_CMASK(count); - } else if (KWMATCH(p, IAP_KW_EDGE)) { - pmc_config->pm_caps |= PMC_CAP_EDGE; - } else if (KWMATCH(p, IAP_KW_INV)) { - pmc_config->pm_caps |= PMC_CAP_INVERT; - } else if (KWMATCH(p, IAP_KW_OS)) { - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - } else if (KWMATCH(p, IAP_KW_USR)) { - pmc_config->pm_caps |= PMC_CAP_USER; - } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { - pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; - } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { - n = pmc_parse_mask(iap_core_mask, p, &evmask); - if (n != 1) - return (-1); - } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { - n = pmc_parse_mask(iap_agent_mask, p, &evmask); - if (n != 1) - return (-1); - } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { - n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); - if (n != 1) - return (-1); - } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { - n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && - KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { - n = pmc_parse_mask(iap_transition_mask, p, &evmask); - if (n != 1) - return (-1); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || - cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || - cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || - cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { - if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { - n = pmc_parse_mask(iap_snoopresponse_mask, p, - &evmask); - } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { - n = pmc_parse_mask(iap_snooptype_mask, p, - &evmask); - } else - return (-1); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || - cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE || - cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX || - cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) { - if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); - } else - return (-1); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || - cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || - cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE || - cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) { - if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); - } else - return (-1); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL || - cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) { - if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); - } else - return (-1); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL || - cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL_XEON) { - /* Broadwell is defined to use same mask as haswell */ - if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); - } else - return (-1); - - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SKYLAKE || - cpu_info.pm_cputype == PMC_CPU_INTEL_SKYLAKE_XEON) { - if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_skylake, p, &rsp); - } else - return (-1); - - } else - return (-1); - - if (n < 0) /* Parsing failed. */ - return (-1); - } - - pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; - - /* - * If the event requires a 'cachestate' qualifier but was not - * specified by the user, use a sensible default. - */ - switch (pe) { - case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ - case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ - case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ - case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ - case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ - case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ - case PMC_EV_IAP_EVENT_32H: /* Core */ - case PMC_EV_IAP_EVENT_40H: /* Core */ - case PMC_EV_IAP_EVENT_41H: /* Core */ - case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ - if (cachestate == 0) - cachestate = (0xF << 8); - break; - case PMC_EV_IAP_EVENT_77H: /* Atom */ - /* IAP_EVENT_77H only accepts a cachestate qualifier on the - * Atom processor - */ - if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) - cachestate = (0xF << 8); - break; - default: - break; - } - - pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; - pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; - - return (0); -} - -/* - * Intel Uncore. - */ - -static int -ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - (void) pe; - (void) ctrspec; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; - - return (0); -} - -#define UCP_KW_CMASK "cmask" -#define UCP_KW_EDGE "edge" -#define UCP_KW_INV "inv" - -static int -ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - char *e, *p, *q; - int count, n; - - (void) pe; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | - PMC_CAP_QUALIFIER); - pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; - - /* Parse additional modifiers if present */ - while ((p = strsep(&ctrspec, ",")) != NULL) { - - n = 0; - if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_ucp.pm_ucp_config |= - UCP_CMASK(count); - } else if (KWMATCH(p, UCP_KW_EDGE)) { - pmc_config->pm_caps |= PMC_CAP_EDGE; - } else if (KWMATCH(p, UCP_KW_INV)) { - pmc_config->pm_caps |= PMC_CAP_INVERT; - } else - return (-1); - - if (n < 0) /* Parsing failed. */ - return (-1); - } - - return (0); -} - -/* - * AMD K8 PMCs. - * - * These are very similar to AMD K7 PMCs, but support more kinds of - * events. - */ - -static struct pmc_event_alias k8_aliases[] = { - EV_ALIAS("branches", "k8-fr-retired-taken-branches"), - EV_ALIAS("branch-mispredicts", - "k8-fr-retired-taken-branches-mispredicted"), - EV_ALIAS("cycles", "tsc"), - EV_ALIAS("dc-misses", "k8-dc-miss"), - EV_ALIAS("ic-misses", "k8-ic-miss"), - EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), - EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), - EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), - EV_ALIAS(NULL, NULL) -}; - -#define __K8MASK(N,V) PMCMASK(N,(1 << (V))) - -/* - * Parsing tables - */ - -/* fp dispatched fpu ops */ -static const struct pmc_masks k8_mask_fdfo[] = { - __K8MASK(add-pipe-excluding-junk-ops, 0), - __K8MASK(multiply-pipe-excluding-junk-ops, 1), - __K8MASK(store-pipe-excluding-junk-ops, 2), - __K8MASK(add-pipe-junk-ops, 3), - __K8MASK(multiply-pipe-junk-ops, 4), - __K8MASK(store-pipe-junk-ops, 5), - NULLMASK -}; - -/* ls segment register loads */ -static const struct pmc_masks k8_mask_lsrl[] = { - __K8MASK(es, 0), - __K8MASK(cs, 1), - __K8MASK(ss, 2), - __K8MASK(ds, 3), - __K8MASK(fs, 4), - __K8MASK(gs, 5), - __K8MASK(hs, 6), - NULLMASK -}; - -/* ls locked operation */ -static const struct pmc_masks k8_mask_llo[] = { - __K8MASK(locked-instructions, 0), - __K8MASK(cycles-in-request, 1), - __K8MASK(cycles-to-complete, 2), - NULLMASK -}; - -/* dc refill from {l2,system} and dc copyback */ -static const struct pmc_masks k8_mask_dc[] = { - __K8MASK(invalid, 0), - __K8MASK(shared, 1), - __K8MASK(exclusive, 2), - __K8MASK(owner, 3), - __K8MASK(modified, 4), - NULLMASK -}; - -/* dc one bit ecc error */ -static const struct pmc_masks k8_mask_dobee[] = { - __K8MASK(scrubber, 0), - __K8MASK(piggyback, 1), - NULLMASK -}; - -/* dc dispatched prefetch instructions */ -static const struct pmc_masks k8_mask_ddpi[] = { - __K8MASK(load, 0), - __K8MASK(store, 1), - __K8MASK(nta, 2), - NULLMASK -}; - -/* dc dcache accesses by locks */ -static const struct pmc_masks k8_mask_dabl[] = { - __K8MASK(accesses, 0), - __K8MASK(misses, 1), - NULLMASK -}; - -/* bu internal l2 request */ -static const struct pmc_masks k8_mask_bilr[] = { - __K8MASK(ic-fill, 0), - __K8MASK(dc-fill, 1), - __K8MASK(tlb-reload, 2), - __K8MASK(tag-snoop, 3), - __K8MASK(cancelled, 4), - NULLMASK -}; - -/* bu fill request l2 miss */ -static const struct pmc_masks k8_mask_bfrlm[] = { - __K8MASK(ic-fill, 0), - __K8MASK(dc-fill, 1), - __K8MASK(tlb-reload, 2), - NULLMASK -}; - -/* bu fill into l2 */ -static const struct pmc_masks k8_mask_bfil[] = { - __K8MASK(dirty-l2-victim, 0), - __K8MASK(victim-from-l2, 1), - NULLMASK -}; - -/* fr retired fpu instructions */ -static const struct pmc_masks k8_mask_frfi[] = { - __K8MASK(x87, 0), - __K8MASK(mmx-3dnow, 1), - __K8MASK(packed-sse-sse2, 2), - __K8MASK(scalar-sse-sse2, 3), - NULLMASK -}; - -/* fr retired fastpath double op instructions */ -static const struct pmc_masks k8_mask_frfdoi[] = { - __K8MASK(low-op-pos-0, 0), - __K8MASK(low-op-pos-1, 1), - __K8MASK(low-op-pos-2, 2), - NULLMASK -}; +/* fr retired fastpath double op instructions */ +static const struct pmc_masks k8_mask_frfdoi[] = { + __K8MASK(low-op-pos-0, 0), + __K8MASK(low-op-pos-1, 1), + __K8MASK(low-op-pos-2, 2), + NULLMASK +}; /* fr fpu exceptions */ static const struct pmc_masks k8_mask_ffe[] = { __K8MASK(x87-reclass-microfaults, 0), __K8MASK(sse-retype-microfaults, 1), __K8MASK(sse-reclass-microfaults, 2), __K8MASK(sse-and-x87-microtraps, 3), NULLMASK }; /* nb memory controller page access event */ static const struct pmc_masks k8_mask_nmcpae[] = { __K8MASK(page-hit, 0), __K8MASK(page-miss, 1), __K8MASK(page-conflict, 2), NULLMASK }; -/* nb memory controller turnaround */ -static const struct pmc_masks k8_mask_nmct[] = { - __K8MASK(dimm-turnaround, 0), - __K8MASK(read-to-write-turnaround, 1), - __K8MASK(write-to-read-turnaround, 2), - NULLMASK -}; - -/* nb memory controller bypass saturation */ -static const struct pmc_masks k8_mask_nmcbs[] = { - __K8MASK(memory-controller-hi-pri-bypass, 0), - __K8MASK(memory-controller-lo-pri-bypass, 1), - __K8MASK(dram-controller-interface-bypass, 2), - __K8MASK(dram-controller-queue-bypass, 3), - NULLMASK -}; - -/* nb sized commands */ -static const struct pmc_masks k8_mask_nsc[] = { - __K8MASK(nonpostwrszbyte, 0), - __K8MASK(nonpostwrszdword, 1), - __K8MASK(postwrszbyte, 2), - __K8MASK(postwrszdword, 3), - __K8MASK(rdszbyte, 4), - __K8MASK(rdszdword, 5), - __K8MASK(rdmodwr, 6), - NULLMASK -}; - -/* nb probe result */ -static const struct pmc_masks k8_mask_npr[] = { - __K8MASK(probe-miss, 0), - __K8MASK(probe-hit, 1), - __K8MASK(probe-hit-dirty-no-memory-cancel, 2), - __K8MASK(probe-hit-dirty-with-memory-cancel, 3), - NULLMASK -}; - -/* nb hypertransport bus bandwidth */ -static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ - __K8MASK(command, 0), - __K8MASK(data, 1), - __K8MASK(buffer-release, 2), - __K8MASK(nop, 3), - NULLMASK -}; - -#undef __K8MASK - -#define K8_KW_COUNT "count" -#define K8_KW_EDGE "edge" -#define K8_KW_INV "inv" -#define K8_KW_MASK "mask" -#define K8_KW_OS "os" -#define K8_KW_USR "usr" - -static int -k8_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - char *e, *p, *q; - int n; - uint32_t count; - uint64_t evmask; - const struct pmc_masks *pm, *pmask; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - pmc_config->pm_md.pm_amd.pm_amd_config = 0; - - pmask = NULL; - evmask = 0; - -#define __K8SETMASK(M) pmask = k8_mask_##M - - /* setup parsing tables */ - switch (pe) { - case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: - __K8SETMASK(fdfo); - break; - case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: - __K8SETMASK(lsrl); - break; - case PMC_EV_K8_LS_LOCKED_OPERATION: - __K8SETMASK(llo); - break; - case PMC_EV_K8_DC_REFILL_FROM_L2: - case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: - case PMC_EV_K8_DC_COPYBACK: - __K8SETMASK(dc); - break; - case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: - __K8SETMASK(dobee); - break; - case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: - __K8SETMASK(ddpi); - break; - case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: - __K8SETMASK(dabl); - break; - case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: - __K8SETMASK(bilr); - break; - case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: - __K8SETMASK(bfrlm); - break; - case PMC_EV_K8_BU_FILL_INTO_L2: - __K8SETMASK(bfil); - break; - case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: - __K8SETMASK(frfi); - break; - case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: - __K8SETMASK(frfdoi); - break; - case PMC_EV_K8_FR_FPU_EXCEPTIONS: - __K8SETMASK(ffe); - break; - case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: - __K8SETMASK(nmcpae); - break; - case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: - __K8SETMASK(nmct); - break; - case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: - __K8SETMASK(nmcbs); - break; - case PMC_EV_K8_NB_SIZED_COMMANDS: - __K8SETMASK(nsc); - break; - case PMC_EV_K8_NB_PROBE_RESULT: - __K8SETMASK(npr); - break; - case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: - case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: - case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: - __K8SETMASK(nhbb); - break; - - default: - break; /* no options defined */ - } - - while ((p = strsep(&ctrspec, ",")) != NULL) { - if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - - pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_amd.pm_amd_config |= - AMD_PMC_TO_COUNTER(count); - - } else if (KWMATCH(p, K8_KW_EDGE)) { - pmc_config->pm_caps |= PMC_CAP_EDGE; - } else if (KWMATCH(p, K8_KW_INV)) { - pmc_config->pm_caps |= PMC_CAP_INVERT; - } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { - if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) - return (-1); - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } else if (KWMATCH(p, K8_KW_OS)) { - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - } else if (KWMATCH(p, K8_KW_USR)) { - pmc_config->pm_caps |= PMC_CAP_USER; - } else - return (-1); - } - - /* other post processing */ - switch (pe) { - case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: - case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: - case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: - case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: - case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: - case PMC_EV_K8_FR_FPU_EXCEPTIONS: - /* XXX only available in rev B and later */ - break; - case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: - /* XXX only available in rev C and later */ - break; - case PMC_EV_K8_LS_LOCKED_OPERATION: - /* XXX CPU Rev A,B evmask is to be zero */ - if (evmask & (evmask - 1)) /* > 1 bit set */ - return (-1); - if (evmask == 0) { - evmask = 0x01; /* Rev C and later: #instrs */ - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } - break; - default: - if (evmask == 0 && pmask != NULL) { - for (pm = pmask; pm->pm_name; pm++) - evmask |= pm->pm_value; - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } - } - - if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) - pmc_config->pm_md.pm_amd.pm_amd_config = - AMD_PMC_TO_UNITMASK(evmask); - - return (0); -} - -#endif - -#if defined(__amd64__) || defined(__i386__) - -/* - * Intel P4 PMCs - */ - -static struct pmc_event_alias p4_aliases[] = { - EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), - EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), - EV_ALIAS("cycles", "tsc"), - EV_ALIAS("instructions", - "p4-instr-retired,mask=nbogusntag+nbogustag"), - EV_ALIAS("unhalted-cycles", "p4-global-power-events"), - EV_ALIAS(NULL, NULL) -}; - -#define P4_KW_ACTIVE "active" -#define P4_KW_ACTIVE_ANY "any" -#define P4_KW_ACTIVE_BOTH "both" -#define P4_KW_ACTIVE_NONE "none" -#define P4_KW_ACTIVE_SINGLE "single" -#define P4_KW_BUSREQTYPE "busreqtype" -#define P4_KW_CASCADE "cascade" -#define P4_KW_EDGE "edge" -#define P4_KW_INV "complement" -#define P4_KW_OS "os" -#define P4_KW_MASK "mask" -#define P4_KW_PRECISE "precise" -#define P4_KW_TAG "tag" -#define P4_KW_THRESHOLD "threshold" -#define P4_KW_USR "usr" - -#define __P4MASK(N,V) PMCMASK(N, (1 << (V))) - -static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ - __P4MASK(dd, 0), - __P4MASK(db, 1), - __P4MASK(di, 2), - __P4MASK(bd, 3), - __P4MASK(bb, 4), - __P4MASK(bi, 5), - __P4MASK(id, 6), - __P4MASK(ib, 7), - NULLMASK -}; - -static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ - __P4MASK(tcmiss, 0), - NULLMASK, -}; - -static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ - __P4MASK(hit, 0), - __P4MASK(miss, 1), - __P4MASK(hit-uc, 2), - NULLMASK -}; - -static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ - __P4MASK(st-rb-full, 2), - __P4MASK(64k-conf, 3), - NULLMASK -}; - -static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ - __P4MASK(lsc, 0), - __P4MASK(ssc, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ - __P4MASK(split-ld, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ - __P4MASK(split-st, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ - __P4MASK(no-sta, 1), - __P4MASK(no-std, 3), - __P4MASK(partial-data, 4), - __P4MASK(unalgn-addr, 5), - NULLMASK -}; - -static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ - __P4MASK(dtmiss, 0), - __P4MASK(itmiss, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ - __P4MASK(rd-2ndl-hits, 0), - __P4MASK(rd-2ndl-hite, 1), - __P4MASK(rd-2ndl-hitm, 2), - __P4MASK(rd-3rdl-hits, 3), - __P4MASK(rd-3rdl-hite, 4), - __P4MASK(rd-3rdl-hitm, 5), - __P4MASK(rd-2ndl-miss, 8), - __P4MASK(rd-3rdl-miss, 9), - __P4MASK(wr-2ndl-miss, 10), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ - __P4MASK(all-read, 5), - __P4MASK(all-write, 6), - __P4MASK(mem-uc, 7), - __P4MASK(mem-wc, 8), - __P4MASK(mem-wt, 9), - __P4MASK(mem-wp, 10), - __P4MASK(mem-wb, 11), - __P4MASK(own, 13), - __P4MASK(other, 14), - __P4MASK(prefetch, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ - __P4MASK(all-read, 5), - __P4MASK(all-write, 6), - __P4MASK(mem-uc, 7), - __P4MASK(mem-wc, 8), - __P4MASK(mem-wt, 9), - __P4MASK(mem-wp, 10), - __P4MASK(mem-wb, 11), - __P4MASK(own, 13), - __P4MASK(other, 14), - __P4MASK(prefetch, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ - __P4MASK(drdy-drv, 0), - __P4MASK(drdy-own, 1), - __P4MASK(drdy-other, 2), - __P4MASK(dbsy-drv, 3), - __P4MASK(dbsy-own, 4), - __P4MASK(dbsy-other, 5), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ - __P4MASK(req-type0, 0), - __P4MASK(req-type1, 1), - __P4MASK(req-len0, 2), - __P4MASK(req-len1, 3), - __P4MASK(req-io-type, 5), - __P4MASK(req-lock-type, 6), - __P4MASK(req-cache-type, 7), - __P4MASK(req-split-type, 8), - __P4MASK(req-dem-type, 9), - __P4MASK(req-ord-type, 10), - __P4MASK(mem-type0, 11), - __P4MASK(mem-type1, 12), - __P4MASK(mem-type2, 13), - NULLMASK -}; - -static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ - __P4MASK(allp0, 3), - __P4MASK(allp2, 4), - NULLMASK -}; - -static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ - __P4MASK(running, 0), - NULLMASK -}; - -static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ - __P4MASK(cisc, 0), - NULLMASK -}; - -static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ - __P4MASK(from-tc-build, 0), - __P4MASK(from-tc-deliver, 1), - __P4MASK(from-rom, 2), - NULLMASK -}; - -static const struct pmc_masks p4_mask_rmbt[] = { - /* retired mispred branch type */ - __P4MASK(conditional, 1), - __P4MASK(call, 2), - __P4MASK(return, 3), - __P4MASK(indirect, 4), - NULLMASK -}; - -static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ - __P4MASK(conditional, 1), - __P4MASK(call, 2), - __P4MASK(retired, 3), - __P4MASK(indirect, 4), - NULLMASK -}; - -static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ - __P4MASK(sbfull, 5), - NULLMASK -}; - -static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ - __P4MASK(wcb-evicts, 0), - __P4MASK(wcb-full-evict, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_fee[] = { /* front end event */ - __P4MASK(nbogus, 0), - __P4MASK(bogus, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ee[] = { /* execution event */ - __P4MASK(nbogus0, 0), - __P4MASK(nbogus1, 1), - __P4MASK(nbogus2, 2), - __P4MASK(nbogus3, 3), - __P4MASK(bogus0, 4), - __P4MASK(bogus1, 5), - __P4MASK(bogus2, 6), - __P4MASK(bogus3, 7), - NULLMASK -}; - -static const struct pmc_masks p4_mask_re[] = { /* replay event */ - __P4MASK(nbogus, 0), - __P4MASK(bogus, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ - __P4MASK(nbogusntag, 0), - __P4MASK(nbogustag, 1), - __P4MASK(bogusntag, 2), - __P4MASK(bogustag, 3), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ - __P4MASK(nbogus, 0), - __P4MASK(bogus, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ut[] = { /* uop type */ - __P4MASK(tagloads, 1), - __P4MASK(tagstores, 2), - NULLMASK -}; - -static const struct pmc_masks p4_mask_br[] = { /* branch retired */ - __P4MASK(mmnp, 0), - __P4MASK(mmnm, 1), - __P4MASK(mmtp, 2), - __P4MASK(mmtm, 3), - NULLMASK -}; - -static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ - __P4MASK(nbogus, 0), - NULLMASK -}; - -static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ - __P4MASK(fpsu, 0), - __P4MASK(fpso, 1), - __P4MASK(poao, 2), - __P4MASK(poau, 3), - __P4MASK(prea, 4), - NULLMASK -}; - -static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ - __P4MASK(clear, 0), - __P4MASK(moclear, 2), - __P4MASK(smclear, 3), - NULLMASK -}; - -/* P4 event parser */ -static int -p4_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - - char *e, *p, *q; - int count, has_tag, has_busreqtype, n; - uint32_t cccractivemask; - uint64_t evmask; - const struct pmc_masks *pm, *pmask; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = - pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; - - pmask = NULL; - evmask = 0; - cccractivemask = 0x3; - has_tag = has_busreqtype = 0; - -#define __P4SETMASK(M) do { \ - pmask = p4_mask_##M; \ -} while (0) - - switch (pe) { - case PMC_EV_P4_TC_DELIVER_MODE: - __P4SETMASK(tcdm); - break; - case PMC_EV_P4_BPU_FETCH_REQUEST: - __P4SETMASK(bfr); - break; - case PMC_EV_P4_ITLB_REFERENCE: - __P4SETMASK(ir); - break; - case PMC_EV_P4_MEMORY_CANCEL: - __P4SETMASK(memcan); - break; - case PMC_EV_P4_MEMORY_COMPLETE: - __P4SETMASK(memcomp); - break; - case PMC_EV_P4_LOAD_PORT_REPLAY: - __P4SETMASK(lpr); - break; - case PMC_EV_P4_STORE_PORT_REPLAY: - __P4SETMASK(spr); - break; - case PMC_EV_P4_MOB_LOAD_REPLAY: - __P4SETMASK(mlr); - break; - case PMC_EV_P4_PAGE_WALK_TYPE: - __P4SETMASK(pwt); - break; - case PMC_EV_P4_BSQ_CACHE_REFERENCE: - __P4SETMASK(bcr); - break; - case PMC_EV_P4_IOQ_ALLOCATION: - __P4SETMASK(ia); - has_busreqtype = 1; - break; - case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: - __P4SETMASK(iae); - has_busreqtype = 1; - break; - case PMC_EV_P4_FSB_DATA_ACTIVITY: - __P4SETMASK(fda); - break; - case PMC_EV_P4_BSQ_ALLOCATION: - __P4SETMASK(ba); - break; - case PMC_EV_P4_SSE_INPUT_ASSIST: - __P4SETMASK(sia); - break; - case PMC_EV_P4_PACKED_SP_UOP: - __P4SETMASK(psu); - break; - case PMC_EV_P4_PACKED_DP_UOP: - __P4SETMASK(pdu); - break; - case PMC_EV_P4_SCALAR_SP_UOP: - __P4SETMASK(ssu); - break; - case PMC_EV_P4_SCALAR_DP_UOP: - __P4SETMASK(sdu); - break; - case PMC_EV_P4_64BIT_MMX_UOP: - __P4SETMASK(64bmu); - break; - case PMC_EV_P4_128BIT_MMX_UOP: - __P4SETMASK(128bmu); - break; - case PMC_EV_P4_X87_FP_UOP: - __P4SETMASK(xfu); - break; - case PMC_EV_P4_X87_SIMD_MOVES_UOP: - __P4SETMASK(xsmu); - break; - case PMC_EV_P4_GLOBAL_POWER_EVENTS: - __P4SETMASK(gpe); - break; - case PMC_EV_P4_TC_MS_XFER: - __P4SETMASK(tmx); - break; - case PMC_EV_P4_UOP_QUEUE_WRITES: - __P4SETMASK(uqw); - break; - case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: - __P4SETMASK(rmbt); - break; - case PMC_EV_P4_RETIRED_BRANCH_TYPE: - __P4SETMASK(rbt); - break; - case PMC_EV_P4_RESOURCE_STALL: - __P4SETMASK(rs); - break; - case PMC_EV_P4_WC_BUFFER: - __P4SETMASK(wb); - break; - case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: - case PMC_EV_P4_B2B_CYCLES: - case PMC_EV_P4_BNR: - case PMC_EV_P4_SNOOP: - case PMC_EV_P4_RESPONSE: - break; - case PMC_EV_P4_FRONT_END_EVENT: - __P4SETMASK(fee); - break; - case PMC_EV_P4_EXECUTION_EVENT: - __P4SETMASK(ee); - break; - case PMC_EV_P4_REPLAY_EVENT: - __P4SETMASK(re); - break; - case PMC_EV_P4_INSTR_RETIRED: - __P4SETMASK(insret); - break; - case PMC_EV_P4_UOPS_RETIRED: - __P4SETMASK(ur); - break; - case PMC_EV_P4_UOP_TYPE: - __P4SETMASK(ut); - break; - case PMC_EV_P4_BRANCH_RETIRED: - __P4SETMASK(br); - break; - case PMC_EV_P4_MISPRED_BRANCH_RETIRED: - __P4SETMASK(mbr); - break; - case PMC_EV_P4_X87_ASSIST: - __P4SETMASK(xa); - break; - case PMC_EV_P4_MACHINE_CLEAR: - __P4SETMASK(machclr); - break; - default: - return (-1); - } - - /* process additional flags */ - while ((p = strsep(&ctrspec, ",")) != NULL) { - if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) - cccractivemask = 0x0; - else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) - cccractivemask = 0x1; - else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) - cccractivemask = 0x2; - else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) - cccractivemask = 0x3; - else - return (-1); - - } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { - if (has_busreqtype == 0) - return (-1); - - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - evmask = (evmask & ~0x1F) | (count & 0x1F); - } else if (KWMATCH(p, P4_KW_CASCADE)) - pmc_config->pm_caps |= PMC_CAP_CASCADE; - else if (KWMATCH(p, P4_KW_EDGE)) - pmc_config->pm_caps |= PMC_CAP_EDGE; - else if (KWMATCH(p, P4_KW_INV)) - pmc_config->pm_caps |= PMC_CAP_INVERT; - else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { - if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) - return (-1); - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } else if (KWMATCH(p, P4_KW_OS)) - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - else if (KWMATCH(p, P4_KW_PRECISE)) - pmc_config->pm_caps |= PMC_CAP_PRECISE; - else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { - if (has_tag == 0) - return (-1); - - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - - pmc_config->pm_caps |= PMC_CAP_TAGGING; - pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= - P4_ESCR_TO_TAG_VALUE(count); - } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - - pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= - ~P4_CCCR_THRESHOLD_MASK; - pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= - P4_CCCR_TO_THRESHOLD(count); - } else if (KWMATCH(p, P4_KW_USR)) - pmc_config->pm_caps |= PMC_CAP_USER; - else - return (-1); - } - - /* other post processing */ - if (pe == PMC_EV_P4_IOQ_ALLOCATION || - pe == PMC_EV_P4_FSB_DATA_ACTIVITY || - pe == PMC_EV_P4_BSQ_ALLOCATION) - pmc_config->pm_caps |= PMC_CAP_EDGE; - - /* fill in thread activity mask */ - pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= - P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); - - if (evmask) - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - - switch (pe) { - case PMC_EV_P4_FSB_DATA_ACTIVITY: - if ((evmask & 0x06) == 0x06 || - (evmask & 0x18) == 0x18) - return (-1); /* can't have own+other bits together */ - if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ - evmask = 0x1D; - break; - case PMC_EV_P4_MACHINE_CLEAR: - /* only one bit is allowed to be set */ - if ((evmask & (evmask - 1)) != 0) - return (-1); - if (evmask == 0) { - evmask = 0x1; /* 'CLEAR' */ - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } - break; - default: - if (evmask == 0 && pmask) { - for (pm = pmask; pm->pm_name; pm++) - evmask |= pm->pm_value; - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } - } - - pmc_config->pm_md.pm_p4.pm_p4_escrconfig = - P4_ESCR_TO_EVENT_MASK(evmask); - - return (0); -} - -#endif - -#if defined(__i386__) - -/* - * Pentium style PMCs - */ - -static struct pmc_event_alias p5_aliases[] = { - EV_ALIAS("branches", "p5-taken-branches"), - EV_ALIAS("cycles", "tsc"), - EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), - EV_ALIAS("ic-misses", "p5-code-cache-miss"), - EV_ALIAS("instructions", "p5-instructions-executed"), - EV_ALIAS("interrupts", "p5-hardware-interrupts"), - EV_ALIAS("unhalted-cycles", - "p5-number-of-cycles-not-in-halt-state"), - EV_ALIAS(NULL, NULL) -}; - -static int -p5_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ -} - -/* - * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, - * and Pentium M CPUs. - */ - -static struct pmc_event_alias p6_aliases[] = { - EV_ALIAS("branches", "p6-br-inst-retired"), - EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), - EV_ALIAS("cycles", "tsc"), - EV_ALIAS("dc-misses", "p6-dcu-lines-in"), - EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), - EV_ALIAS("instructions", "p6-inst-retired"), - EV_ALIAS("interrupts", "p6-hw-int-rx"), - EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), - EV_ALIAS(NULL, NULL) -}; - -#define P6_KW_CMASK "cmask" -#define P6_KW_EDGE "edge" -#define P6_KW_INV "inv" -#define P6_KW_OS "os" -#define P6_KW_UMASK "umask" -#define P6_KW_USR "usr" - -static struct pmc_masks p6_mask_mesi[] = { - PMCMASK(m, 0x01), - PMCMASK(e, 0x02), - PMCMASK(s, 0x04), - PMCMASK(i, 0x08), - NULLMASK -}; - -static struct pmc_masks p6_mask_mesihw[] = { - PMCMASK(m, 0x01), - PMCMASK(e, 0x02), - PMCMASK(s, 0x04), - PMCMASK(i, 0x08), - PMCMASK(nonhw, 0x00), - PMCMASK(hw, 0x10), - PMCMASK(both, 0x30), - NULLMASK -}; - -static struct pmc_masks p6_mask_hw[] = { - PMCMASK(nonhw, 0x00), - PMCMASK(hw, 0x10), - PMCMASK(both, 0x30), - NULLMASK -}; - -static struct pmc_masks p6_mask_any[] = { - PMCMASK(self, 0x00), - PMCMASK(any, 0x20), - NULLMASK -}; - -static struct pmc_masks p6_mask_ekp[] = { - PMCMASK(nta, 0x00), - PMCMASK(t1, 0x01), - PMCMASK(t2, 0x02), - PMCMASK(wos, 0x03), - NULLMASK -}; - -static struct pmc_masks p6_mask_pps[] = { - PMCMASK(packed-and-scalar, 0x00), - PMCMASK(scalar, 0x01), - NULLMASK -}; - -static struct pmc_masks p6_mask_mite[] = { - PMCMASK(packed-multiply, 0x01), - PMCMASK(packed-shift, 0x02), - PMCMASK(pack, 0x04), - PMCMASK(unpack, 0x08), - PMCMASK(packed-logical, 0x10), - PMCMASK(packed-arithmetic, 0x20), - NULLMASK -}; - -static struct pmc_masks p6_mask_fmt[] = { - PMCMASK(mmxtofp, 0x00), - PMCMASK(fptommx, 0x01), - NULLMASK -}; - -static struct pmc_masks p6_mask_sr[] = { - PMCMASK(es, 0x01), - PMCMASK(ds, 0x02), - PMCMASK(fs, 0x04), - PMCMASK(gs, 0x08), +/* nb memory controller turnaround */ +static const struct pmc_masks k8_mask_nmct[] = { + __K8MASK(dimm-turnaround, 0), + __K8MASK(read-to-write-turnaround, 1), + __K8MASK(write-to-read-turnaround, 2), NULLMASK }; -static struct pmc_masks p6_mask_eet[] = { - PMCMASK(all, 0x00), - PMCMASK(freq, 0x02), +/* nb memory controller bypass saturation */ +static const struct pmc_masks k8_mask_nmcbs[] = { + __K8MASK(memory-controller-hi-pri-bypass, 0), + __K8MASK(memory-controller-lo-pri-bypass, 1), + __K8MASK(dram-controller-interface-bypass, 2), + __K8MASK(dram-controller-queue-bypass, 3), NULLMASK }; -static struct pmc_masks p6_mask_efur[] = { - PMCMASK(all, 0x00), - PMCMASK(loadop, 0x01), - PMCMASK(stdsta, 0x02), +/* nb sized commands */ +static const struct pmc_masks k8_mask_nsc[] = { + __K8MASK(nonpostwrszbyte, 0), + __K8MASK(nonpostwrszdword, 1), + __K8MASK(postwrszbyte, 2), + __K8MASK(postwrszdword, 3), + __K8MASK(rdszbyte, 4), + __K8MASK(rdszdword, 5), + __K8MASK(rdmodwr, 6), NULLMASK }; -static struct pmc_masks p6_mask_essir[] = { - PMCMASK(sse-packed-single, 0x00), - PMCMASK(sse-packed-single-scalar-single, 0x01), - PMCMASK(sse2-packed-double, 0x02), - PMCMASK(sse2-scalar-double, 0x03), +/* nb probe result */ +static const struct pmc_masks k8_mask_npr[] = { + __K8MASK(probe-miss, 0), + __K8MASK(probe-hit, 1), + __K8MASK(probe-hit-dirty-no-memory-cancel, 2), + __K8MASK(probe-hit-dirty-with-memory-cancel, 3), NULLMASK }; -static struct pmc_masks p6_mask_esscir[] = { - PMCMASK(sse-packed-single, 0x00), - PMCMASK(sse-scalar-single, 0x01), - PMCMASK(sse2-packed-double, 0x02), - PMCMASK(sse2-scalar-double, 0x03), +/* nb hypertransport bus bandwidth */ +static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ + __K8MASK(command, 0), + __K8MASK(data, 1), + __K8MASK(buffer-release, 2), + __K8MASK(nop, 3), NULLMASK }; -/* P6 event parser */ +#undef __K8MASK + +#define K8_KW_COUNT "count" +#define K8_KW_EDGE "edge" +#define K8_KW_INV "inv" +#define K8_KW_MASK "mask" +#define K8_KW_OS "os" +#define K8_KW_USR "usr" + static int -p6_allocate_pmc(enum pmc_event pe, char *ctrspec, +k8_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { - char *e, *p, *q; - uint64_t evmask; - int count, n; - const struct pmc_masks *pm, *pmask; + char *e, *p, *q; + int n; + uint32_t count; + uint64_t evmask; + const struct pmc_masks *pm, *pmask; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; + pmc_config->pm_md.pm_amd.pm_amd_config = 0; + pmask = NULL; evmask = 0; -#define P6MASKSET(M) pmask = p6_mask_ ## M - - switch(pe) { - case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; - case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; - case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; - case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; - case PMC_EV_P6_BUS_DRDY_CLOCKS: - case PMC_EV_P6_BUS_LOCK_CLOCKS: - case PMC_EV_P6_BUS_TRAN_BRD: - case PMC_EV_P6_BUS_TRAN_RFO: - case PMC_EV_P6_BUS_TRANS_WB: - case PMC_EV_P6_BUS_TRAN_IFETCH: - case PMC_EV_P6_BUS_TRAN_INVAL: - case PMC_EV_P6_BUS_TRAN_PWR: - case PMC_EV_P6_BUS_TRANS_P: - case PMC_EV_P6_BUS_TRANS_IO: - case PMC_EV_P6_BUS_TRAN_DEF: - case PMC_EV_P6_BUS_TRAN_BURST: - case PMC_EV_P6_BUS_TRAN_ANY: - case PMC_EV_P6_BUS_TRAN_MEM: - P6MASKSET(any); break; - case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: - case PMC_EV_P6_EMON_KNI_PREF_MISS: - P6MASKSET(ekp); break; - case PMC_EV_P6_EMON_KNI_INST_RETIRED: - case PMC_EV_P6_EMON_KNI_COMP_INST_RET: - P6MASKSET(pps); break; - case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: - P6MASKSET(mite); break; - case PMC_EV_P6_FP_MMX_TRANS: - P6MASKSET(fmt); break; - case PMC_EV_P6_SEG_RENAME_STALLS: - case PMC_EV_P6_SEG_REG_RENAMES: - P6MASKSET(sr); break; - case PMC_EV_P6_EMON_EST_TRANS: - P6MASKSET(eet); break; - case PMC_EV_P6_EMON_FUSED_UOPS_RET: - P6MASKSET(efur); break; - case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: - P6MASKSET(essir); break; - case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: - P6MASKSET(esscir); break; - default: - pmask = NULL; +#define __K8SETMASK(M) pmask = k8_mask_##M + + /* setup parsing tables */ + switch (pe) { + case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: + __K8SETMASK(fdfo); + break; + case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: + __K8SETMASK(lsrl); + break; + case PMC_EV_K8_LS_LOCKED_OPERATION: + __K8SETMASK(llo); + break; + case PMC_EV_K8_DC_REFILL_FROM_L2: + case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: + case PMC_EV_K8_DC_COPYBACK: + __K8SETMASK(dc); + break; + case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: + __K8SETMASK(dobee); + break; + case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: + __K8SETMASK(ddpi); + break; + case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: + __K8SETMASK(dabl); + break; + case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: + __K8SETMASK(bilr); + break; + case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: + __K8SETMASK(bfrlm); + break; + case PMC_EV_K8_BU_FILL_INTO_L2: + __K8SETMASK(bfil); + break; + case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: + __K8SETMASK(frfi); + break; + case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: + __K8SETMASK(frfdoi); + break; + case PMC_EV_K8_FR_FPU_EXCEPTIONS: + __K8SETMASK(ffe); + break; + case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: + __K8SETMASK(nmcpae); + break; + case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: + __K8SETMASK(nmct); + break; + case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: + __K8SETMASK(nmcbs); + break; + case PMC_EV_K8_NB_SIZED_COMMANDS: + __K8SETMASK(nsc); + break; + case PMC_EV_K8_NB_PROBE_RESULT: + __K8SETMASK(npr); + break; + case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: + case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: + case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: + __K8SETMASK(nhbb); break; - } - /* Pentium M PMCs have a few events with different semantics */ - if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { - if (pe == PMC_EV_P6_L2_LD || - pe == PMC_EV_P6_L2_LINES_IN || - pe == PMC_EV_P6_L2_LINES_OUT) - P6MASKSET(mesihw); - else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) - P6MASKSET(hw); + default: + break; /* no options defined */ } - /* Parse additional modifiers if present */ while ((p = strsep(&ctrspec, ",")) != NULL) { - if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { + if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); + count = strtol(q, &e, 0); if (e == q || *e != '\0') return (-1); + pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_ppro.pm_ppro_config |= - P6_EVSEL_TO_CMASK(count); - } else if (KWMATCH(p, P6_KW_EDGE)) { + pmc_config->pm_md.pm_amd.pm_amd_config |= + AMD_PMC_TO_COUNTER(count); + + } else if (KWMATCH(p, K8_KW_EDGE)) { pmc_config->pm_caps |= PMC_CAP_EDGE; - } else if (KWMATCH(p, P6_KW_INV)) { + } else if (KWMATCH(p, K8_KW_INV)) { pmc_config->pm_caps |= PMC_CAP_INVERT; - } else if (KWMATCH(p, P6_KW_OS)) { - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { - evmask = 0; + } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) return (-1); - if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || - pe == PMC_EV_P6_BUS_LOCK_CLOCKS || - pe == PMC_EV_P6_BUS_TRAN_BRD || - pe == PMC_EV_P6_BUS_TRAN_RFO || - pe == PMC_EV_P6_BUS_TRAN_IFETCH || - pe == PMC_EV_P6_BUS_TRAN_INVAL || - pe == PMC_EV_P6_BUS_TRAN_PWR || - pe == PMC_EV_P6_BUS_TRAN_DEF || - pe == PMC_EV_P6_BUS_TRAN_BURST || - pe == PMC_EV_P6_BUS_TRAN_ANY || - pe == PMC_EV_P6_BUS_TRAN_MEM || - pe == PMC_EV_P6_BUS_TRANS_IO || - pe == PMC_EV_P6_BUS_TRANS_P || - pe == PMC_EV_P6_BUS_TRANS_WB || - pe == PMC_EV_P6_EMON_EST_TRANS || - pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || - pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || - pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || - pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || - pe == PMC_EV_P6_EMON_KNI_PREF_MISS || - pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || - pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || - pe == PMC_EV_P6_FP_MMX_TRANS) - && (n > 1)) /* Only one mask keyword is allowed. */ - return (-1); pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } else if (KWMATCH(p, P6_KW_USR)) { + } else if (KWMATCH(p, K8_KW_OS)) { + pmc_config->pm_caps |= PMC_CAP_SYSTEM; + } else if (KWMATCH(p, K8_KW_USR)) { pmc_config->pm_caps |= PMC_CAP_USER; } else return (-1); } - /* post processing */ + /* other post processing */ switch (pe) { - - /* - * The following events default to an evmask of 0 - */ - - /* default => 'self' */ - case PMC_EV_P6_BUS_DRDY_CLOCKS: - case PMC_EV_P6_BUS_LOCK_CLOCKS: - case PMC_EV_P6_BUS_TRAN_BRD: - case PMC_EV_P6_BUS_TRAN_RFO: - case PMC_EV_P6_BUS_TRANS_WB: - case PMC_EV_P6_BUS_TRAN_IFETCH: - case PMC_EV_P6_BUS_TRAN_INVAL: - case PMC_EV_P6_BUS_TRAN_PWR: - case PMC_EV_P6_BUS_TRANS_P: - case PMC_EV_P6_BUS_TRANS_IO: - case PMC_EV_P6_BUS_TRAN_DEF: - case PMC_EV_P6_BUS_TRAN_BURST: - case PMC_EV_P6_BUS_TRAN_ANY: - case PMC_EV_P6_BUS_TRAN_MEM: - - /* default => 'nta' */ - case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: - case PMC_EV_P6_EMON_KNI_PREF_MISS: - - /* default => 'packed and scalar' */ - case PMC_EV_P6_EMON_KNI_INST_RETIRED: - case PMC_EV_P6_EMON_KNI_COMP_INST_RET: - - /* default => 'mmx to fp transitions' */ - case PMC_EV_P6_FP_MMX_TRANS: - - /* default => 'SSE Packed Single' */ - case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: - case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: - - /* default => 'all fused micro-ops' */ - case PMC_EV_P6_EMON_FUSED_UOPS_RET: - - /* default => 'all transitions' */ - case PMC_EV_P6_EMON_EST_TRANS: + case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: + case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: + case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: + case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: + case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: + case PMC_EV_K8_FR_FPU_EXCEPTIONS: + /* XXX only available in rev B and later */ break; - - case PMC_EV_P6_MMX_UOPS_EXEC: - evmask = 0x0F; /* only value allowed */ + case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: + /* XXX only available in rev C and later */ + break; + case PMC_EV_K8_LS_LOCKED_OPERATION: + /* XXX CPU Rev A,B evmask is to be zero */ + if (evmask & (evmask - 1)) /* > 1 bit set */ + return (-1); + if (evmask == 0) { + evmask = 0x01; /* Rev C and later: #instrs */ + pmc_config->pm_caps |= PMC_CAP_QUALIFIER; + } break; - default: - /* - * For all other events, set the default event mask - * to a logical OR of all the allowed event mask bits. - */ - if (evmask == 0 && pmask) { + if (evmask == 0 && pmask != NULL) { for (pm = pmask; pm->pm_name; pm++) evmask |= pm->pm_value; pmc_config->pm_caps |= PMC_CAP_QUALIFIER; } - - break; } if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) - pmc_config->pm_md.pm_ppro.pm_ppro_config |= - P6_EVSEL_TO_UMASK(evmask); + pmc_config->pm_md.pm_amd.pm_amd_config = + AMD_PMC_TO_UNITMASK(evmask); return (0); } #endif #if defined(__i386__) || defined(__amd64__) static int tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { if (pe != PMC_EV_TSC_TSC) return (-1); /* TSC events must be unqualified. */ if (ctrspec && *ctrspec != '\0') return (-1); pmc_config->pm_md.pm_amd.pm_amd_config = 0; pmc_config->pm_caps |= PMC_CAP_READ; return (0); } #endif static struct pmc_event_alias generic_aliases[] = { EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), EV_ALIAS(NULL, NULL) }; static int soft_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { (void)ctrspec; (void)pmc_config; if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) return (-1); pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); return (0); } #if defined(__arm__) #if defined(__XSCALE__) static struct pmc_event_alias xscale_aliases[] = { EV_ALIAS("branches", "BRANCH_RETIRED"), EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), EV_ALIAS("dc-misses", "DC_MISS"), EV_ALIAS("ic-misses", "IC_MISS"), EV_ALIAS("instructions", "INSTR_RETIRED"), EV_ALIAS(NULL, NULL) }; static int xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, struct pmc_op_pmcallocate *pmc_config __unused) { switch (pe) { default: break; } return (0); } #endif static struct pmc_event_alias cortex_a8_aliases[] = { EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), EV_ALIAS("instructions", "INSTR_EXECUTED"), EV_ALIAS(NULL, NULL) }; static struct pmc_event_alias cortex_a9_aliases[] = { EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), EV_ALIAS("instructions", "INSTR_EXECUTED"), EV_ALIAS(NULL, NULL) }; static int armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, struct pmc_op_pmcallocate *pmc_config __unused) { switch (pe) { default: break; } return (0); } #endif #if defined(__aarch64__) static struct pmc_event_alias cortex_a53_aliases[] = { EV_ALIAS(NULL, NULL) }; static struct pmc_event_alias cortex_a57_aliases[] = { EV_ALIAS(NULL, NULL) }; static int arm64_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, struct pmc_op_pmcallocate *pmc_config __unused) { switch (pe) { default: break; } return (0); } #endif #if defined(__mips__) static struct pmc_event_alias mips24k_aliases[] = { EV_ALIAS("instructions", "INSTR_EXECUTED"), EV_ALIAS("branches", "BRANCH_COMPLETED"), EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), EV_ALIAS(NULL, NULL) }; static struct pmc_event_alias mips74k_aliases[] = { EV_ALIAS("instructions", "INSTR_EXECUTED"), EV_ALIAS("branches", "BRANCH_INSNS"), EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCH_INSNS"), EV_ALIAS(NULL, NULL) }; static struct pmc_event_alias octeon_aliases[] = { EV_ALIAS("instructions", "RET"), EV_ALIAS("branches", "BR"), EV_ALIAS("branch-mispredicts", "BRMIS"), EV_ALIAS(NULL, NULL) }; #define MIPS_KW_OS "os" #define MIPS_KW_USR "usr" #define MIPS_KW_ANYTHREAD "anythread" static int mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, struct pmc_op_pmcallocate *pmc_config __unused) { char *p; (void) pe; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); while ((p = strsep(&ctrspec, ",")) != NULL) { if (KWMATCH(p, MIPS_KW_OS)) pmc_config->pm_caps |= PMC_CAP_SYSTEM; else if (KWMATCH(p, MIPS_KW_USR)) pmc_config->pm_caps |= PMC_CAP_USER; else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); else return (-1); } return (0); } #endif /* __mips__ */ #if defined(__powerpc__) static struct pmc_event_alias ppc7450_aliases[] = { EV_ALIAS("instructions", "INSTR_COMPLETED"), EV_ALIAS("branches", "BRANCHES_COMPLETED"), EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), EV_ALIAS(NULL, NULL) }; static struct pmc_event_alias ppc970_aliases[] = { EV_ALIAS("instructions", "INSTR_COMPLETED"), EV_ALIAS("cycles", "CYCLES"), EV_ALIAS(NULL, NULL) }; static struct pmc_event_alias e500_aliases[] = { EV_ALIAS("instructions", "INSTR_COMPLETED"), EV_ALIAS("cycles", "CYCLES"), EV_ALIAS(NULL, NULL) }; #define POWERPC_KW_OS "os" #define POWERPC_KW_USR "usr" #define POWERPC_KW_ANYTHREAD "anythread" static int powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, struct pmc_op_pmcallocate *pmc_config __unused) { char *p; (void) pe; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); while ((p = strsep(&ctrspec, ",")) != NULL) { if (KWMATCH(p, POWERPC_KW_OS)) pmc_config->pm_caps |= PMC_CAP_SYSTEM; else if (KWMATCH(p, POWERPC_KW_USR)) pmc_config->pm_caps |= PMC_CAP_USER; else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); else return (-1); } return (0); } #endif /* __powerpc__ */ /* * Match an event name `name' with its canonical form. * * Matches are case insensitive and spaces, periods, underscores and * hyphen characters are considered to match each other. * * Returns 1 for a match, 0 otherwise. */ static int pmc_match_event_name(const char *name, const char *canonicalname) { int cc, nc; const unsigned char *c, *n; c = (const unsigned char *) canonicalname; n = (const unsigned char *) name; for (; (nc = *n) && (cc = *c); n++, c++) { if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) continue; if (toupper(nc) == toupper(cc)) continue; return (0); } if (*n == '\0' && *c == '\0') return (1); return (0); } /* * Match an event name against all the event named supported by a * PMC class. * * Returns an event descriptor pointer on match or NULL otherwise. */ static const struct pmc_event_descr * pmc_match_event_class(const char *name, const struct pmc_class_descr *pcd) { size_t n; const struct pmc_event_descr *ev; ev = pcd->pm_evc_event_table; for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) if (pmc_match_event_name(name, ev->pm_ev_name)) return (ev); return (NULL); } static int pmc_mdep_is_compatible_class(enum pmc_class pc) { size_t n; for (n = 0; n < pmc_mdep_class_list_size; n++) if (pmc_mdep_class_list[n] == pc) return (1); return (0); } /* * API entry points */ int pmc_allocate(const char *ctrspec, enum pmc_mode mode, uint32_t flags, int cpu, pmc_id_t *pmcid) { size_t n; int retval; char *r, *spec_copy; const char *ctrname; const struct pmc_event_descr *ev; const struct pmc_event_alias *alias; struct pmc_op_pmcallocate pmc_config; const struct pmc_class_descr *pcd; spec_copy = NULL; retval = -1; if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && mode != PMC_MODE_SC && mode != PMC_MODE_TC) { errno = EINVAL; goto out; } bzero(&pmc_config, sizeof(pmc_config)); pmc_config.pm_cpu = cpu; pmc_config.pm_mode = mode; pmc_config.pm_flags = flags; if (PMC_IS_SAMPLING_MODE(mode)) pmc_config.pm_caps |= PMC_CAP_INTERRUPT; /* * Can we pull this straight from the pmu table? */ r = spec_copy = strdup(ctrspec); ctrname = strsep(&r, ","); if (pmc_pmu_pmcallocate(ctrname, &pmc_config) == 0) { if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) { goto out; } retval = 0; *pmcid = pmc_config.pm_pmcid; goto out; } else { free(spec_copy); spec_copy = NULL; } /* replace an event alias with the canonical event specifier */ if (pmc_mdep_event_aliases) for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) if (!strcasecmp(ctrspec, alias->pm_alias)) { spec_copy = strdup(alias->pm_spec); break; } if (spec_copy == NULL) spec_copy = strdup(ctrspec); r = spec_copy; ctrname = strsep(&r, ","); /* * If a explicit class prefix was given by the user, restrict the * search for the event to the specified PMC class. */ ev = NULL; for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { pcd = pmc_class_table[n]; if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && strncasecmp(ctrname, pcd->pm_evc_name, pcd->pm_evc_name_size) == 0) { if ((ev = pmc_match_event_class(ctrname + pcd->pm_evc_name_size, pcd)) == NULL) { errno = EINVAL; goto out; } break; } } /* * Otherwise, search for this event in all compatible PMC * classes. */ for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { pcd = pmc_class_table[n]; if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) ev = pmc_match_event_class(ctrname, pcd); } if (ev == NULL) { errno = EINVAL; goto out; } pmc_config.pm_ev = ev->pm_ev_code; pmc_config.pm_class = pcd->pm_evc_class; if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { errno = EINVAL; goto out; } if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) goto out; *pmcid = pmc_config.pm_pmcid; retval = 0; out: if (spec_copy) free(spec_copy); return (retval); } int pmc_attach(pmc_id_t pmc, pid_t pid) { struct pmc_op_pmcattach pmc_attach_args; pmc_attach_args.pm_pmc = pmc; pmc_attach_args.pm_pid = pid; return (PMC_CALL(PMCATTACH, &pmc_attach_args)); } int pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) { unsigned int i; enum pmc_class cl; cl = PMC_ID_TO_CLASS(pmcid); for (i = 0; i < cpu_info.pm_nclass; i++) if (cpu_info.pm_classes[i].pm_class == cl) { *caps = cpu_info.pm_classes[i].pm_caps; return (0); } errno = EINVAL; return (-1); } int pmc_configure_logfile(int fd) { struct pmc_op_configurelog cla; cla.pm_logfd = fd; if (PMC_CALL(CONFIGURELOG, &cla) < 0) return (-1); return (0); } int pmc_cpuinfo(const struct pmc_cpuinfo **pci) { if (pmc_syscall == -1) { errno = ENXIO; return (-1); } *pci = &cpu_info; return (0); } int pmc_detach(pmc_id_t pmc, pid_t pid) { struct pmc_op_pmcattach pmc_detach_args; pmc_detach_args.pm_pmc = pmc; pmc_detach_args.pm_pid = pid; return (PMC_CALL(PMCDETACH, &pmc_detach_args)); } int pmc_disable(int cpu, int pmc) { struct pmc_op_pmcadmin ssa; ssa.pm_cpu = cpu; ssa.pm_pmc = pmc; ssa.pm_state = PMC_STATE_DISABLED; return (PMC_CALL(PMCADMIN, &ssa)); } int pmc_enable(int cpu, int pmc) { struct pmc_op_pmcadmin ssa; ssa.pm_cpu = cpu; ssa.pm_pmc = pmc; ssa.pm_state = PMC_STATE_FREE; return (PMC_CALL(PMCADMIN, &ssa)); } /* * Return a list of events known to a given PMC class. 'cl' is the * PMC class identifier, 'eventnames' is the returned list of 'const * char *' pointers pointing to the names of the events. 'nevents' is * the number of event name pointers returned. * * The space for 'eventnames' is allocated using malloc(3). The caller * is responsible for freeing this space when done. */ int pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, int *nevents) { int count; const char **names; const struct pmc_event_descr *ev; switch (cl) { case PMC_CLASS_IAF: ev = iaf_event_table; count = PMC_EVENT_TABLE_SIZE(iaf); break; - case PMC_CLASS_IAP: - /* - * Return the most appropriate set of event name - * spellings for the current CPU. - */ - switch (cpu_info.pm_cputype) { - default: - case PMC_CPU_INTEL_ATOM: - ev = atom_event_table; - count = PMC_EVENT_TABLE_SIZE(atom); - break; - case PMC_CPU_INTEL_ATOM_SILVERMONT: - ev = atom_silvermont_event_table; - count = PMC_EVENT_TABLE_SIZE(atom_silvermont); - break; - case PMC_CPU_INTEL_CORE: - ev = core_event_table; - count = PMC_EVENT_TABLE_SIZE(core); - break; - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - ev = core2_event_table; - count = PMC_EVENT_TABLE_SIZE(core2); - break; - case PMC_CPU_INTEL_COREI7: - ev = corei7_event_table; - count = PMC_EVENT_TABLE_SIZE(corei7); - break; - case PMC_CPU_INTEL_NEHALEM_EX: - ev = nehalem_ex_event_table; - count = PMC_EVENT_TABLE_SIZE(nehalem_ex); - break; - case PMC_CPU_INTEL_HASWELL: - ev = haswell_event_table; - count = PMC_EVENT_TABLE_SIZE(haswell); - break; - case PMC_CPU_INTEL_HASWELL_XEON: - ev = haswell_xeon_event_table; - count = PMC_EVENT_TABLE_SIZE(haswell_xeon); - break; - case PMC_CPU_INTEL_BROADWELL: - ev = broadwell_event_table; - count = PMC_EVENT_TABLE_SIZE(broadwell); - break; - case PMC_CPU_INTEL_BROADWELL_XEON: - ev = broadwell_xeon_event_table; - count = PMC_EVENT_TABLE_SIZE(broadwell_xeon); - break; - case PMC_CPU_INTEL_SKYLAKE: - ev = skylake_event_table; - count = PMC_EVENT_TABLE_SIZE(skylake); - break; - case PMC_CPU_INTEL_SKYLAKE_XEON: - ev = skylake_xeon_event_table; - count = PMC_EVENT_TABLE_SIZE(skylake_xeon); - break; - case PMC_CPU_INTEL_IVYBRIDGE: - ev = ivybridge_event_table; - count = PMC_EVENT_TABLE_SIZE(ivybridge); - break; - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - ev = ivybridge_xeon_event_table; - count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon); - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - ev = sandybridge_event_table; - count = PMC_EVENT_TABLE_SIZE(sandybridge); - break; - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - ev = sandybridge_xeon_event_table; - count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); - break; - case PMC_CPU_INTEL_WESTMERE: - ev = westmere_event_table; - count = PMC_EVENT_TABLE_SIZE(westmere); - break; - case PMC_CPU_INTEL_WESTMERE_EX: - ev = westmere_ex_event_table; - count = PMC_EVENT_TABLE_SIZE(westmere_ex); - break; - } - break; - case PMC_CLASS_UCF: - ev = ucf_event_table; - count = PMC_EVENT_TABLE_SIZE(ucf); - break; - case PMC_CLASS_UCP: - /* - * Return the most appropriate set of event name - * spellings for the current CPU. - */ - switch (cpu_info.pm_cputype) { - default: - case PMC_CPU_INTEL_COREI7: - ev = corei7uc_event_table; - count = PMC_EVENT_TABLE_SIZE(corei7uc); - break; - case PMC_CPU_INTEL_HASWELL: - ev = haswelluc_event_table; - count = PMC_EVENT_TABLE_SIZE(haswelluc); - break; - case PMC_CPU_INTEL_BROADWELL: - ev = broadwelluc_event_table; - count = PMC_EVENT_TABLE_SIZE(broadwelluc); - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - ev = sandybridgeuc_event_table; - count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); - break; - case PMC_CPU_INTEL_WESTMERE: - ev = westmereuc_event_table; - count = PMC_EVENT_TABLE_SIZE(westmereuc); - break; - } - break; case PMC_CLASS_TSC: ev = tsc_event_table; count = PMC_EVENT_TABLE_SIZE(tsc); break; - case PMC_CLASS_K7: - ev = k7_event_table; - count = PMC_EVENT_TABLE_SIZE(k7); - break; case PMC_CLASS_K8: ev = k8_event_table; count = PMC_EVENT_TABLE_SIZE(k8); break; - case PMC_CLASS_P4: - ev = p4_event_table; - count = PMC_EVENT_TABLE_SIZE(p4); - break; - case PMC_CLASS_P5: - ev = p5_event_table; - count = PMC_EVENT_TABLE_SIZE(p5); - break; - case PMC_CLASS_P6: - ev = p6_event_table; - count = PMC_EVENT_TABLE_SIZE(p6); - break; case PMC_CLASS_XSCALE: ev = xscale_event_table; count = PMC_EVENT_TABLE_SIZE(xscale); break; case PMC_CLASS_ARMV7: switch (cpu_info.pm_cputype) { default: case PMC_CPU_ARMV7_CORTEX_A8: ev = cortex_a8_event_table; count = PMC_EVENT_TABLE_SIZE(cortex_a8); break; case PMC_CPU_ARMV7_CORTEX_A9: ev = cortex_a9_event_table; count = PMC_EVENT_TABLE_SIZE(cortex_a9); break; } break; case PMC_CLASS_ARMV8: switch (cpu_info.pm_cputype) { default: case PMC_CPU_ARMV8_CORTEX_A53: ev = cortex_a53_event_table; count = PMC_EVENT_TABLE_SIZE(cortex_a53); break; case PMC_CPU_ARMV8_CORTEX_A57: ev = cortex_a57_event_table; count = PMC_EVENT_TABLE_SIZE(cortex_a57); break; } break; case PMC_CLASS_MIPS24K: ev = mips24k_event_table; count = PMC_EVENT_TABLE_SIZE(mips24k); break; case PMC_CLASS_MIPS74K: ev = mips74k_event_table; count = PMC_EVENT_TABLE_SIZE(mips74k); break; case PMC_CLASS_OCTEON: ev = octeon_event_table; count = PMC_EVENT_TABLE_SIZE(octeon); break; case PMC_CLASS_PPC7450: ev = ppc7450_event_table; count = PMC_EVENT_TABLE_SIZE(ppc7450); break; case PMC_CLASS_PPC970: ev = ppc970_event_table; count = PMC_EVENT_TABLE_SIZE(ppc970); break; case PMC_CLASS_E500: ev = e500_event_table; count = PMC_EVENT_TABLE_SIZE(e500); break; case PMC_CLASS_SOFT: ev = soft_event_table; count = soft_event_info.pm_nevent; break; default: errno = EINVAL; return (-1); } if ((names = malloc(count * sizeof(const char *))) == NULL) return (-1); *eventnames = names; *nevents = count; for (;count--; ev++, names++) *names = ev->pm_ev_name; return (0); } int pmc_flush_logfile(void) { return (PMC_CALL(FLUSHLOG,0)); } int pmc_close_logfile(void) { return (PMC_CALL(CLOSELOG,0)); } int pmc_get_driver_stats(struct pmc_driverstats *ds) { struct pmc_op_getdriverstats gms; if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) return (-1); /* copy out fields in the current userland<->library interface */ ds->pm_intr_ignored = gms.pm_intr_ignored; ds->pm_intr_processed = gms.pm_intr_processed; ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; ds->pm_syscalls = gms.pm_syscalls; ds->pm_syscall_errors = gms.pm_syscall_errors; ds->pm_buffer_requests = gms.pm_buffer_requests; ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; ds->pm_log_sweeps = gms.pm_log_sweeps; return (0); } int pmc_get_msr(pmc_id_t pmc, uint32_t *msr) { struct pmc_op_getmsr gm; gm.pm_pmcid = pmc; if (PMC_CALL(PMCGETMSR, &gm) < 0) return (-1); *msr = gm.pm_msr; return (0); } int pmc_init(void) { int error, pmc_mod_id; unsigned int n; uint32_t abi_version; struct module_stat pmc_modstat; struct pmc_op_getcpuinfo op_cpu_info; #if defined(__amd64__) || defined(__i386__) int cpu_has_iaf_counters; unsigned int t; #endif if (pmc_syscall != -1) /* already inited */ return (0); /* retrieve the system call number from the KLD */ if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) return (-1); pmc_modstat.version = sizeof(struct module_stat); if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) return (-1); pmc_syscall = pmc_modstat.data.intval; /* check the kernel module's ABI against our compiled-in version */ abi_version = PMC_VERSION; if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) return (pmc_syscall = -1); /* ignore patch & minor numbers for the comparison */ if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { errno = EPROGMISMATCH; return (pmc_syscall = -1); } bzero(&op_cpu_info, sizeof(op_cpu_info)); if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) return (pmc_syscall = -1); cpu_info.pm_cputype = op_cpu_info.pm_cputype; cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; cpu_info.pm_npmc = op_cpu_info.pm_npmc; cpu_info.pm_nclass = op_cpu_info.pm_nclass; for (n = 0; n < op_cpu_info.pm_nclass; n++) memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n], sizeof(cpu_info.pm_classes[n])); pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * sizeof(struct pmc_class_descr *)); if (pmc_class_table == NULL) return (-1); for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) pmc_class_table[n] = NULL; /* * Get soft events list. */ soft_event_info.pm_class = PMC_CLASS_SOFT; if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) return (pmc_syscall = -1); /* Map soft events to static list. */ for (n = 0; n < soft_event_info.pm_nevent; n++) { soft_event_table[n].pm_ev_name = soft_event_info.pm_events[n].pm_ev_name; soft_event_table[n].pm_ev_code = soft_event_info.pm_events[n].pm_ev_code; } soft_class_table_descr.pm_evc_event_table_size = \ soft_event_info.pm_nevent; soft_class_table_descr.pm_evc_event_table = \ soft_event_table; /* * Fill in the class table. */ n = 0; /* Fill soft events information. */ pmc_class_table[n++] = &soft_class_table_descr; #if defined(__amd64__) || defined(__i386__) if (cpu_info.pm_cputype != PMC_CPU_GENERIC) pmc_class_table[n++] = &tsc_class_table_descr; /* * Check if this CPU has fixed function counters. */ cpu_has_iaf_counters = 0; for (t = 0; t < cpu_info.pm_nclass; t++) if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && cpu_info.pm_classes[t].pm_num > 0) cpu_has_iaf_counters = 1; #endif #define PMC_MDEP_INIT(C) do { \ pmc_mdep_event_aliases = C##_aliases; \ pmc_mdep_class_list = C##_pmc_classes; \ pmc_mdep_class_list_size = \ PMC_TABLE_SIZE(C##_pmc_classes); \ } while (0) #define PMC_MDEP_INIT_INTEL_V2(C) do { \ PMC_MDEP_INIT(C); \ pmc_class_table[n++] = &iaf_class_table_descr; \ if (!cpu_has_iaf_counters) \ pmc_mdep_event_aliases = \ C##_aliases_without_iaf; \ pmc_class_table[n] = &C##_class_table_descr; \ } while (0) /* Configure the event name parser. */ switch (cpu_info.pm_cputype) { -#if defined(__i386__) - case PMC_CPU_AMD_K7: - PMC_MDEP_INIT(k7); - pmc_class_table[n] = &k7_class_table_descr; - break; - case PMC_CPU_INTEL_P5: - PMC_MDEP_INIT(p5); - pmc_class_table[n] = &p5_class_table_descr; - break; - case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ - case PMC_CPU_INTEL_PII: /* similar PMCs. */ - case PMC_CPU_INTEL_PIII: - case PMC_CPU_INTEL_PM: - PMC_MDEP_INIT(p6); - pmc_class_table[n] = &p6_class_table_descr; - break; -#endif #if defined(__amd64__) || defined(__i386__) case PMC_CPU_AMD_K8: PMC_MDEP_INIT(k8); pmc_class_table[n] = &k8_class_table_descr; break; - case PMC_CPU_INTEL_ATOM: - PMC_MDEP_INIT_INTEL_V2(atom); - break; - case PMC_CPU_INTEL_ATOM_SILVERMONT: - PMC_MDEP_INIT_INTEL_V2(atom_silvermont); - break; - case PMC_CPU_INTEL_CORE: - PMC_MDEP_INIT(core); - pmc_class_table[n] = &core_class_table_descr; - break; - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - PMC_MDEP_INIT_INTEL_V2(core2); - break; - case PMC_CPU_INTEL_COREI7: - pmc_class_table[n++] = &ucf_class_table_descr; - pmc_class_table[n++] = &corei7uc_class_table_descr; - PMC_MDEP_INIT_INTEL_V2(corei7); - break; - case PMC_CPU_INTEL_NEHALEM_EX: - PMC_MDEP_INIT_INTEL_V2(nehalem_ex); - break; - case PMC_CPU_INTEL_HASWELL: - pmc_class_table[n++] = &ucf_class_table_descr; - pmc_class_table[n++] = &haswelluc_class_table_descr; - PMC_MDEP_INIT_INTEL_V2(haswell); - break; - case PMC_CPU_INTEL_HASWELL_XEON: - PMC_MDEP_INIT_INTEL_V2(haswell_xeon); - break; - case PMC_CPU_INTEL_BROADWELL: - pmc_class_table[n++] = &ucf_class_table_descr; - pmc_class_table[n++] = &broadwelluc_class_table_descr; - PMC_MDEP_INIT_INTEL_V2(broadwell); - break; - case PMC_CPU_INTEL_BROADWELL_XEON: - PMC_MDEP_INIT_INTEL_V2(broadwell_xeon); - break; - case PMC_CPU_INTEL_SKYLAKE: - PMC_MDEP_INIT_INTEL_V2(skylake); - break; - case PMC_CPU_INTEL_SKYLAKE_XEON: - PMC_MDEP_INIT_INTEL_V2(skylake_xeon); - break; - case PMC_CPU_INTEL_IVYBRIDGE: - PMC_MDEP_INIT_INTEL_V2(ivybridge); - break; - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon); - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - pmc_class_table[n++] = &ucf_class_table_descr; - pmc_class_table[n++] = &sandybridgeuc_class_table_descr; - PMC_MDEP_INIT_INTEL_V2(sandybridge); - break; - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); - break; - case PMC_CPU_INTEL_WESTMERE: - pmc_class_table[n++] = &ucf_class_table_descr; - pmc_class_table[n++] = &westmereuc_class_table_descr; - PMC_MDEP_INIT_INTEL_V2(westmere); - break; - case PMC_CPU_INTEL_WESTMERE_EX: - PMC_MDEP_INIT_INTEL_V2(westmere_ex); - break; - case PMC_CPU_INTEL_PIV: - PMC_MDEP_INIT(p4); - pmc_class_table[n] = &p4_class_table_descr; - break; #endif case PMC_CPU_GENERIC: PMC_MDEP_INIT(generic); break; #if defined(__arm__) #if defined(__XSCALE__) case PMC_CPU_INTEL_XSCALE: PMC_MDEP_INIT(xscale); pmc_class_table[n] = &xscale_class_table_descr; break; #endif case PMC_CPU_ARMV7_CORTEX_A8: PMC_MDEP_INIT(cortex_a8); pmc_class_table[n] = &cortex_a8_class_table_descr; break; case PMC_CPU_ARMV7_CORTEX_A9: PMC_MDEP_INIT(cortex_a9); pmc_class_table[n] = &cortex_a9_class_table_descr; break; #endif #if defined(__aarch64__) case PMC_CPU_ARMV8_CORTEX_A53: PMC_MDEP_INIT(cortex_a53); pmc_class_table[n] = &cortex_a53_class_table_descr; break; case PMC_CPU_ARMV8_CORTEX_A57: PMC_MDEP_INIT(cortex_a57); pmc_class_table[n] = &cortex_a57_class_table_descr; break; #endif #if defined(__mips__) case PMC_CPU_MIPS_24K: PMC_MDEP_INIT(mips24k); pmc_class_table[n] = &mips24k_class_table_descr; break; case PMC_CPU_MIPS_74K: PMC_MDEP_INIT(mips74k); pmc_class_table[n] = &mips74k_class_table_descr; break; case PMC_CPU_MIPS_OCTEON: PMC_MDEP_INIT(octeon); pmc_class_table[n] = &octeon_class_table_descr; break; #endif /* __mips__ */ #if defined(__powerpc__) case PMC_CPU_PPC_7450: PMC_MDEP_INIT(ppc7450); pmc_class_table[n] = &ppc7450_class_table_descr; break; case PMC_CPU_PPC_970: PMC_MDEP_INIT(ppc970); pmc_class_table[n] = &ppc970_class_table_descr; break; case PMC_CPU_PPC_E500: PMC_MDEP_INIT(e500); pmc_class_table[n] = &e500_class_table_descr; break; #endif default: /* * Some kind of CPU this version of the library knows nothing * about. This shouldn't happen since the abi version check * should have caught this. */ errno = ENXIO; return (pmc_syscall = -1); } return (0); } const char * pmc_name_of_capability(enum pmc_caps cap) { int i; /* * 'cap' should have a single bit set and should be in * range. */ if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || cap > PMC_CAP_LAST) { errno = EINVAL; return (NULL); } i = ffs(cap); return (pmc_capability_names[i - 1]); } const char * pmc_name_of_class(enum pmc_class pc) { size_t n; for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++) if (pc == pmc_class_names[n].pm_class) return (pmc_class_names[n].pm_name); errno = EINVAL; return (NULL); } const char * pmc_name_of_cputype(enum pmc_cputype cp) { size_t n; for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) if (cp == pmc_cputype_names[n].pm_cputype) return (pmc_cputype_names[n].pm_name); errno = EINVAL; return (NULL); } const char * pmc_name_of_disposition(enum pmc_disp pd) { if ((int) pd >= PMC_DISP_FIRST && pd <= PMC_DISP_LAST) return (pmc_disposition_names[pd]); errno = EINVAL; return (NULL); } const char * _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) { const struct pmc_event_descr *ev, *evfence; ev = evfence = NULL; - if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { - ev = iaf_event_table; - evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); - } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { - switch (cpu) { - case PMC_CPU_INTEL_ATOM: - ev = atom_event_table; - evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); - break; - case PMC_CPU_INTEL_ATOM_SILVERMONT: - ev = atom_silvermont_event_table; - evfence = atom_silvermont_event_table + - PMC_EVENT_TABLE_SIZE(atom_silvermont); - break; - case PMC_CPU_INTEL_CORE: - ev = core_event_table; - evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); - break; - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - ev = core2_event_table; - evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); - break; - case PMC_CPU_INTEL_COREI7: - ev = corei7_event_table; - evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); - break; - case PMC_CPU_INTEL_NEHALEM_EX: - ev = nehalem_ex_event_table; - evfence = nehalem_ex_event_table + - PMC_EVENT_TABLE_SIZE(nehalem_ex); - break; - case PMC_CPU_INTEL_HASWELL: - ev = haswell_event_table; - evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); - break; - case PMC_CPU_INTEL_HASWELL_XEON: - ev = haswell_xeon_event_table; - evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon); - break; - case PMC_CPU_INTEL_BROADWELL: - ev = broadwell_event_table; - evfence = broadwell_event_table + PMC_EVENT_TABLE_SIZE(broadwell); - break; - case PMC_CPU_INTEL_BROADWELL_XEON: - ev = broadwell_xeon_event_table; - evfence = broadwell_xeon_event_table + PMC_EVENT_TABLE_SIZE(broadwell_xeon); - break; - case PMC_CPU_INTEL_SKYLAKE: - ev = skylake_event_table; - evfence = skylake_event_table + - PMC_EVENT_TABLE_SIZE(skylake); - break; - case PMC_CPU_INTEL_SKYLAKE_XEON: - ev = skylake_xeon_event_table; - evfence = skylake_xeon_event_table + - PMC_EVENT_TABLE_SIZE(skylake_xeon); - break; - case PMC_CPU_INTEL_IVYBRIDGE: - ev = ivybridge_event_table; - evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); - break; - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - ev = ivybridge_xeon_event_table; - evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon); - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - ev = sandybridge_event_table; - evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); - break; - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - ev = sandybridge_xeon_event_table; - evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); - break; - case PMC_CPU_INTEL_WESTMERE: - ev = westmere_event_table; - evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); - break; - case PMC_CPU_INTEL_WESTMERE_EX: - ev = westmere_ex_event_table; - evfence = westmere_ex_event_table + - PMC_EVENT_TABLE_SIZE(westmere_ex); - break; - default: /* Unknown CPU type. */ - break; - } - } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { - ev = ucf_event_table; - evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); - } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { - switch (cpu) { - case PMC_CPU_INTEL_COREI7: - ev = corei7uc_event_table; - evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - ev = sandybridgeuc_event_table; - evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); - break; - case PMC_CPU_INTEL_WESTMERE: - ev = westmereuc_event_table; - evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); - break; - default: /* Unknown CPU type. */ - break; - } - } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { - ev = k7_event_table; - evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); - } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { + if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { ev = k8_event_table; evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); - } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { - ev = p4_event_table; - evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); - } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { - ev = p5_event_table; - evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); - } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { - ev = p6_event_table; - evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { ev = xscale_event_table; evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { switch (cpu) { case PMC_CPU_ARMV7_CORTEX_A8: ev = cortex_a8_event_table; evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8); break; case PMC_CPU_ARMV7_CORTEX_A9: ev = cortex_a9_event_table; evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9); break; default: /* Unknown CPU type. */ break; } } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) { switch (cpu) { case PMC_CPU_ARMV8_CORTEX_A53: ev = cortex_a53_event_table; evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53); break; case PMC_CPU_ARMV8_CORTEX_A57: ev = cortex_a57_event_table; evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57); break; default: /* Unknown CPU type. */ break; } } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { ev = mips24k_event_table; evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); } else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) { ev = mips74k_event_table; evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k); } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { ev = octeon_event_table; evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { ev = ppc7450_event_table; evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { ev = ppc970_event_table; evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) { ev = e500_event_table; evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500); } else if (pe == PMC_EV_TSC_TSC) { ev = tsc_event_table; evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { ev = soft_event_table; evfence = soft_event_table + soft_event_info.pm_nevent; } for (; ev != evfence; ev++) if (pe == ev->pm_ev_code) return (ev->pm_ev_name); return (NULL); } const char * pmc_name_of_event(enum pmc_event pe) { const char *n; if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) return (n); errno = EINVAL; return (NULL); } const char * pmc_name_of_mode(enum pmc_mode pm) { if ((int) pm >= PMC_MODE_FIRST && pm <= PMC_MODE_LAST) return (pmc_mode_names[pm]); errno = EINVAL; return (NULL); } const char * pmc_name_of_state(enum pmc_state ps) { if ((int) ps >= PMC_STATE_FIRST && ps <= PMC_STATE_LAST) return (pmc_state_names[ps]); errno = EINVAL; return (NULL); } int pmc_ncpu(void) { if (pmc_syscall == -1) { errno = ENXIO; return (-1); } return (cpu_info.pm_ncpu); } int pmc_npmc(int cpu) { if (pmc_syscall == -1) { errno = ENXIO; return (-1); } if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { errno = EINVAL; return (-1); } return (cpu_info.pm_npmc); } int pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) { int nbytes, npmc; struct pmc_op_getpmcinfo *pmci; if ((npmc = pmc_npmc(cpu)) < 0) return (-1); nbytes = sizeof(struct pmc_op_getpmcinfo) + npmc * sizeof(struct pmc_info); if ((pmci = calloc(1, nbytes)) == NULL) return (-1); pmci->pm_cpu = cpu; if (PMC_CALL(GETPMCINFO, pmci) < 0) { free(pmci); return (-1); } /* kernel<->library, library<->userland interfaces are identical */ *ppmci = (struct pmc_pmcinfo *) pmci; return (0); } int pmc_read(pmc_id_t pmc, pmc_value_t *value) { struct pmc_op_pmcrw pmc_read_op; pmc_read_op.pm_pmcid = pmc; pmc_read_op.pm_flags = PMC_F_OLDVALUE; pmc_read_op.pm_value = -1; if (PMC_CALL(PMCRW, &pmc_read_op) < 0) return (-1); *value = pmc_read_op.pm_value; return (0); } int pmc_release(pmc_id_t pmc) { struct pmc_op_simple pmc_release_args; pmc_release_args.pm_pmcid = pmc; return (PMC_CALL(PMCRELEASE, &pmc_release_args)); } int pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) { struct pmc_op_pmcrw pmc_rw_op; pmc_rw_op.pm_pmcid = pmc; pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; pmc_rw_op.pm_value = newvalue; if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) return (-1); *oldvaluep = pmc_rw_op.pm_value; return (0); } int pmc_set(pmc_id_t pmc, pmc_value_t value) { struct pmc_op_pmcsetcount sc; sc.pm_pmcid = pmc; sc.pm_count = value; if (PMC_CALL(PMCSETCOUNT, &sc) < 0) return (-1); return (0); } int pmc_start(pmc_id_t pmc) { struct pmc_op_simple pmc_start_args; pmc_start_args.pm_pmcid = pmc; return (PMC_CALL(PMCSTART, &pmc_start_args)); } int pmc_stop(pmc_id_t pmc) { struct pmc_op_simple pmc_stop_args; pmc_stop_args.pm_pmcid = pmc; return (PMC_CALL(PMCSTOP, &pmc_stop_args)); } int pmc_width(pmc_id_t pmcid, uint32_t *width) { unsigned int i; enum pmc_class cl; cl = PMC_ID_TO_CLASS(pmcid); for (i = 0; i < cpu_info.pm_nclass; i++) if (cpu_info.pm_classes[i].pm_class == cl) { *width = cpu_info.pm_classes[i].pm_width; return (0); } errno = EINVAL; return (-1); } int pmc_write(pmc_id_t pmc, pmc_value_t value) { struct pmc_op_pmcrw pmc_write_op; pmc_write_op.pm_pmcid = pmc; pmc_write_op.pm_flags = PMC_F_NEWVALUE; pmc_write_op.pm_value = value; return (PMC_CALL(PMCRW, &pmc_write_op)); } int pmc_writelog(uint32_t userdata) { struct pmc_op_writelog wl; wl.pm_userdata = userdata; return (PMC_CALL(WRITELOG, &wl)); } diff --git a/sys/amd64/include/pmc_mdep.h b/sys/amd64/include/pmc_mdep.h index 58354707cf19..635d880f7f12 100644 --- a/sys/amd64/include/pmc_mdep.h +++ b/sys/amd64/include/pmc_mdep.h @@ -1,143 +1,140 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2003-2008 Joseph Koshy * Copyright (c) 2007 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by A. Joseph Koshy under * sponsorship from the FreeBSD Foundation and Google, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* Machine dependent interfaces */ #ifndef _MACHINE_PMC_MDEP_H #define _MACHINE_PMC_MDEP_H 1 #ifdef _KERNEL struct pmc_mdep; #endif #include #include -#include #include #include /* * Intel processors implementing V2 and later of the Intel performance * measurement architecture have PMCs of the following classes: TSC, * IAF, IAP, UCF and UCP. */ #define PMC_MDEP_CLASS_INDEX_TSC 1 #define PMC_MDEP_CLASS_INDEX_K8 2 #define PMC_MDEP_CLASS_INDEX_P4 2 #define PMC_MDEP_CLASS_INDEX_IAP 2 #define PMC_MDEP_CLASS_INDEX_IAF 3 #define PMC_MDEP_CLASS_INDEX_UCP 4 #define PMC_MDEP_CLASS_INDEX_UCF 5 /* * On the amd64 platform we support the following PMCs. * * TSC The timestamp counter * K8 AMD Athlon64 and Opteron PMCs in 64 bit mode. * PIV Intel P4/HTT and P4/EMT64 * IAP Intel Core/Core2/Atom CPUs in 64 bits mode. * IAF Intel fixed-function PMCs in Core2 and later CPUs. * UCP Intel Uncore programmable PMCs. * UCF Intel Uncore fixed-function PMCs. */ union pmc_md_op_pmcallocate { struct pmc_md_amd_op_pmcallocate pm_amd; struct pmc_md_iaf_op_pmcallocate pm_iaf; struct pmc_md_iap_op_pmcallocate pm_iap; struct pmc_md_ucf_op_pmcallocate pm_ucf; struct pmc_md_ucp_op_pmcallocate pm_ucp; - struct pmc_md_p4_op_pmcallocate pm_p4; uint64_t __pad[4]; }; /* Logging */ #define PMCLOG_READADDR PMCLOG_READ64 #define PMCLOG_EMITADDR PMCLOG_EMIT64 #ifdef _KERNEL union pmc_md_pmc { struct pmc_md_amd_pmc pm_amd; struct pmc_md_iaf_pmc pm_iaf; struct pmc_md_iap_pmc pm_iap; struct pmc_md_ucf_pmc pm_ucf; struct pmc_md_ucp_pmc pm_ucp; - struct pmc_md_p4_pmc pm_p4; }; #define PMC_TRAPFRAME_TO_PC(TF) ((TF)->tf_rip) #define PMC_TRAPFRAME_TO_FP(TF) ((TF)->tf_rbp) #define PMC_TRAPFRAME_TO_USER_SP(TF) ((TF)->tf_rsp) #define PMC_TRAPFRAME_TO_KERNEL_SP(TF) ((TF)->tf_rsp) #define PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(I) \ (((I) & 0xffffffff) == 0xe5894855) /* pushq %rbp; movq %rsp,%rbp */ #define PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(I) \ (((I) & 0x00ffffff) == 0x00e58948) /* movq %rsp,%rbp */ #define PMC_AT_FUNCTION_EPILOGUE_RET(I) \ (((I) & 0xFF) == 0xC3) /* ret */ #define PMC_IN_TRAP_HANDLER(PC) \ ((PC) >= (uintptr_t) start_exceptions && \ (PC) < (uintptr_t) end_exceptions) #define PMC_IN_KERNEL_STACK(S,START,END) \ ((S) >= (START) && (S) < (END)) #define PMC_IN_KERNEL(va) INKERNEL(va) #define PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS) /* Build a fake kernel trapframe from current instruction pointer. */ #define PMC_FAKE_TRAPFRAME(TF) \ do { \ (TF)->tf_cs = 0; (TF)->tf_rflags = 0; \ __asm __volatile("movq %%rbp,%0" : "=r" ((TF)->tf_rbp)); \ __asm __volatile("movq %%rsp,%0" : "=r" ((TF)->tf_rsp)); \ __asm __volatile("call 1f \n\t1: pop %0" : "=r"((TF)->tf_rip)); \ } while (0) /* * Prototypes */ void start_exceptions(void), end_exceptions(void); struct pmc_mdep *pmc_amd_initialize(void); void pmc_amd_finalize(struct pmc_mdep *_md); struct pmc_mdep *pmc_intel_initialize(void); void pmc_intel_finalize(struct pmc_mdep *_md); #endif /* _KERNEL */ #endif /* _MACHINE_PMC_MDEP_H */ diff --git a/sys/conf/files.amd64 b/sys/conf/files.amd64 index 97a1ecef924e..1de5fde27f7b 100644 --- a/sys/conf/files.amd64 +++ b/sys/conf/files.amd64 @@ -1,756 +1,755 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # # cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_i686_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_i686_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-x86-64-freebsd --binary-architecture i386 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_x86_64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_x86_64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-x86-64-freebsd --binary-architecture i386 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # linux32_genassym.o optional compat_linux32 \ dependency "$S/amd64/linux32/linux32_genassym.c" \ compile-with "${CC} ${CFLAGS:N-flto:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "linux32_genassym.o" # linux32_assym.h optional compat_linux32 \ dependency "$S/kern/genassym.sh linux32_genassym.o" \ compile-with "sh $S/kern/genassym.sh linux32_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "linux32_assym.h" # linux32_locore.o optional compat_linux32 \ dependency "linux32_assym.h $S/amd64/linux32/linux32_locore.s" \ compile-with "${CC} -x assembler-with-cpp -DLOCORE -m32 -shared -s -pipe -I. -I$S -Werror -Wall -fPIC -fno-common -nostdinc -nostdlib -Wl,-T$S/amd64/linux32/linux32_vdso.lds.s -Wl,-soname=linux32_vdso.so,--eh-frame-hdr,-warn-common ${.IMPSRC} -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "linux32_locore.o" # linux32_vdso.so optional compat_linux32 \ dependency "linux32_locore.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-x86-64-freebsd --binary-architecture i386 linux32_locore.o ${.TARGET}" \ no-implicit-rule \ clean "linux32_vdso.so" # ia32_genassym.o standard \ dependency "$S/compat/ia32/ia32_genassym.c" \ compile-with "${CC} ${CFLAGS:N-flto:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "ia32_genassym.o" # ia32_assym.h standard \ dependency "$S/kern/genassym.sh ia32_genassym.o" \ compile-with "env NM='${NM}' NMFLAGS='${NMFLAGS}' sh $S/kern/genassym.sh ia32_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "ia32_assym.h" # font.h optional sc_dflt_font \ compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'static u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'static u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'static u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ no-obj no-implicit-rule before-depend \ clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" # atkbdmap.h optional atkbd_dflt_keymap \ compile-with "kbdcontrol -P ${S:S/sys$/share/}/vt/keymaps -P ${S:S/sys$/share/}/syscons/keymaps -L ${ATKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > atkbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "atkbdmap.h" # ukbdmap.h optional ukbd_dflt_keymap \ compile-with "kbdcontrol -P ${S:S/sys$/share/}/vt/keymaps -P ${S:S/sys$/share/}/syscons/keymaps -L ${UKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > ukbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "ukbdmap.h" # hpt27xx_lib.o optional hpt27xx \ dependency "$S/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu" \ compile-with "uudecode < $S/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu" \ no-implicit-rule # hptmvraid.o optional hptmv \ dependency "$S/dev/hptmv/amd64-elf.raid.o.uu" \ compile-with "uudecode < $S/dev/hptmv/amd64-elf.raid.o.uu" \ no-implicit-rule # hptnr_lib.o optional hptnr \ dependency "$S/dev/hptnr/amd64-elf.hptnr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptnr/amd64-elf.hptnr_lib.o.uu" \ no-implicit-rule # hptrr_lib.o optional hptrr \ dependency "$S/dev/hptrr/amd64-elf.hptrr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptrr/amd64-elf.hptrr_lib.o.uu" \ no-implicit-rule # amd64/acpica/acpi_machdep.c optional acpi acpi_wakecode.o optional acpi \ dependency "$S/amd64/acpica/acpi_wakecode.S assym.inc" \ compile-with "${NORMAL_S}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.o" acpi_wakecode.bin optional acpi \ dependency "acpi_wakecode.o" \ compile-with "${OBJCOPY} -S -O binary acpi_wakecode.o ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.bin" acpi_wakecode.h optional acpi \ dependency "acpi_wakecode.bin" \ compile-with "file2c -sx 'static char wakecode[] = {' '};' < acpi_wakecode.bin > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.h" acpi_wakedata.h optional acpi \ dependency "acpi_wakecode.o" \ compile-with '${NM} -n --defined-only acpi_wakecode.o | while read offset dummy what; do echo "#define $${what} 0x$${offset}"; done > ${.TARGET}' \ no-obj no-implicit-rule before-depend \ clean "acpi_wakedata.h" # #amd64/amd64/apic_vector.S standard amd64/amd64/atomic.c standard amd64/amd64/bios.c standard amd64/amd64/bpf_jit_machdep.c optional bpf_jitter amd64/amd64/cpu_switch.S standard amd64/amd64/db_disasm.c optional ddb amd64/amd64/db_interface.c optional ddb amd64/amd64/db_trace.c optional ddb amd64/amd64/efirt_machdep.c optional efirt amd64/amd64/elf_machdep.c standard amd64/amd64/exception.S standard amd64/amd64/fpu.c standard amd64/amd64/gdb_machdep.c optional gdb amd64/amd64/in_cksum.c optional inet | inet6 amd64/amd64/initcpu.c standard amd64/amd64/io.c optional io amd64/amd64/locore.S standard no-obj amd64/amd64/xen-locore.S optional xenhvm amd64/amd64/machdep.c standard amd64/amd64/mem.c optional mem amd64/amd64/minidump_machdep.c standard amd64/amd64/mp_machdep.c optional smp amd64/amd64/mpboot.S optional smp amd64/amd64/pmap.c standard amd64/amd64/prof_machdep.c optional profiling-routine amd64/amd64/ptrace_machdep.c standard amd64/amd64/sigtramp.S standard amd64/amd64/support.S standard amd64/amd64/sys_machdep.c standard amd64/amd64/trap.c standard amd64/amd64/uio_machdep.c standard amd64/amd64/uma_machdep.c standard amd64/amd64/vm_machdep.c standard amd64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 amd64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 amd64/pci/pci_cfgreg.c optional pci cddl/contrib/opensolaris/common/atomic/amd64/opensolaris_atomic.S optional zfs | dtrace compile-with "${ZFS_S}" cddl/dev/dtrace/amd64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/amd64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/x86/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" cddl/dev/dtrace/x86/dis_tables.c optional dtrace_fbt | dtraceall compile-with "${DTRACE_C}" cddl/dev/dtrace/x86/instr_size.c optional dtrace_fbt | dtraceall compile-with "${DTRACE_C}" crypto/aesni/aeskeys_amd64.S optional aesni crypto/aesni/aesni.c optional aesni aesni_ghash.o optional aesni \ dependency "$S/crypto/aesni/aesni_ghash.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -mmmx -msse -msse4 -maes -mpclmul ${.IMPSRC}" \ no-implicit-rule \ clean "aesni_ghash.o" aesni_wrap.o optional aesni \ dependency "$S/crypto/aesni/aesni_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -mmmx -msse -msse4 -maes ${.IMPSRC}" \ no-implicit-rule \ clean "aesni_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | \ ipsec_support | netsmb intel_sha1.o optional aesni \ dependency "$S/crypto/aesni/intel_sha1.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${PROF} -mmmx -msse -msse4 -msha ${.IMPSRC}" \ no-implicit-rule \ clean "intel_sha1.o" intel_sha256.o optional aesni \ dependency "$S/crypto/aesni/intel_sha256.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${PROF} -mmmx -msse -msse4 -msha ${.IMPSRC}" \ no-implicit-rule \ clean "intel_sha256.o" crypto/via/padlock.c optional padlock crypto/via/padlock_cipher.c optional padlock crypto/via/padlock_hash.c optional padlock dev/acpica/acpi_if.m standard dev/acpica/acpi_hpet.c optional acpi dev/acpica/acpi_pci.c optional acpi pci dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pcib_acpi.c optional acpi pci dev/acpica/acpi_pcib_pci.c optional acpi pci dev/acpica/acpi_timer.c optional acpi dev/acpi_support/acpi_wmi_if.m standard dev/agp/agp_amd64.c optional agp dev/agp/agp_i810.c optional agp dev/agp/agp_via.c optional agp dev/amdsbwd/amdsbwd.c optional amdsbwd dev/amdsmn/amdsmn.c optional amdsmn | amdtemp dev/amdtemp/amdtemp.c optional amdtemp dev/arcmsr/arcmsr.c optional arcmsr pci dev/asmc/asmc.c optional asmc isa dev/atkbdc/atkbd.c optional atkbd atkbdc dev/atkbdc/atkbd_atkbdc.c optional atkbd atkbdc dev/atkbdc/atkbdc.c optional atkbdc dev/atkbdc/atkbdc_isa.c optional atkbdc isa dev/atkbdc/atkbdc_subr.c optional atkbdc dev/atkbdc/psm.c optional psm atkbdc dev/bxe/bxe.c optional bxe pci dev/bxe/bxe_stats.c optional bxe pci dev/bxe/bxe_debug.c optional bxe pci dev/bxe/ecore_sp.c optional bxe pci dev/bxe/bxe_elink.c optional bxe pci dev/bxe/57710_init_values.c optional bxe pci dev/bxe/57711_init_values.c optional bxe pci dev/bxe/57712_init_values.c optional bxe pci dev/coretemp/coretemp.c optional coretemp dev/cpuctl/cpuctl.c optional cpuctl dev/dpms/dpms.c optional dpms # There are no systems with isa slots, so all ed isa entries should go.. dev/ed/if_ed_3c503.c optional ed isa ed_3c503 dev/ed/if_ed_isa.c optional ed isa dev/ed/if_ed_wd80x3.c optional ed isa dev/ed/if_ed_hpp.c optional ed isa ed_hpp dev/ed/if_ed_sic.c optional ed isa ed_sic dev/fb/fb.c optional fb | vga dev/fb/s3_pci.c optional s3pci dev/fb/vesa.c optional vga vesa dev/fb/vga.c optional vga dev/ichwd/ichwd.c optional ichwd dev/if_ndis/if_ndis.c optional ndis dev/if_ndis/if_ndis_pccard.c optional ndis pccard dev/if_ndis/if_ndis_pci.c optional ndis cardbus | ndis pci dev/if_ndis/if_ndis_usb.c optional ndis usb dev/imcsmb/imcsmb.c optional imcsmb dev/imcsmb/imcsmb_pci.c optional imcsmb pci dev/intel/spi.c optional intelspi dev/io/iodev.c optional io dev/ioat/ioat.c optional ioat pci dev/ioat/ioat_test.c optional ioat pci dev/ipmi/ipmi.c optional ipmi dev/ipmi/ipmi_acpi.c optional ipmi acpi dev/ipmi/ipmi_isa.c optional ipmi isa dev/ipmi/ipmi_kcs.c optional ipmi dev/ipmi/ipmi_smic.c optional ipmi dev/ipmi/ipmi_smbus.c optional ipmi smbus dev/ipmi/ipmi_smbios.c optional ipmi dev/ipmi/ipmi_ssif.c optional ipmi smbus dev/ipmi/ipmi_pci.c optional ipmi pci dev/ipmi/ipmi_linux.c optional ipmi compat_linux32 dev/ixl/if_ixl.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_pf_main.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_pf_qmgr.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_pf_iov.c optional ixl pci pci_iov \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_pf_i2c.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_iw.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/if_ixlv.c optional ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixlvc.c optional ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/ixl_txrx.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_osdep.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_lan_hmc.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_hmc.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_common.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_nvm.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_adminq.c optional ixl pci | ixlv pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/ixl/i40e_dcb.c optional ixl pci \ compile-with "${NORMAL_C} -I$S/dev/ixl" dev/fdc/fdc.c optional fdc dev/fdc/fdc_acpi.c optional fdc dev/fdc/fdc_isa.c optional fdc isa dev/fdc/fdc_pccard.c optional fdc pccard dev/gpio/bytgpio.c optional bytgpio dev/gpio/chvgpio.c optional chvgpio dev/hpt27xx/hpt27xx_os_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_osm_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_config.c optional hpt27xx dev/hptmv/entry.c optional hptmv dev/hptmv/mv.c optional hptmv dev/hptmv/gui_lib.c optional hptmv dev/hptmv/hptproc.c optional hptmv dev/hptmv/ioctl.c optional hptmv dev/hptnr/hptnr_os_bsd.c optional hptnr dev/hptnr/hptnr_osm_bsd.c optional hptnr dev/hptnr/hptnr_config.c optional hptnr dev/hptrr/hptrr_os_bsd.c optional hptrr dev/hptrr/hptrr_osm_bsd.c optional hptrr dev/hptrr/hptrr_config.c optional hptrr dev/hwpmc/hwpmc_amd.c optional hwpmc dev/hwpmc/hwpmc_intel.c optional hwpmc dev/hwpmc/hwpmc_core.c optional hwpmc dev/hwpmc/hwpmc_uncore.c optional hwpmc -dev/hwpmc/hwpmc_piv.c optional hwpmc dev/hwpmc/hwpmc_tsc.c optional hwpmc dev/hwpmc/hwpmc_x86.c optional hwpmc dev/hyperv/input/hv_kbd.c optional hyperv dev/hyperv/input/hv_kbdc.c optional hyperv dev/hyperv/pcib/vmbus_pcib.c optional hyperv pci dev/hyperv/netvsc/hn_nvs.c optional hyperv dev/hyperv/netvsc/hn_rndis.c optional hyperv dev/hyperv/netvsc/if_hn.c optional hyperv dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c optional hyperv dev/hyperv/utilities/hv_kvp.c optional hyperv dev/hyperv/utilities/hv_snapshot.c optional hyperv dev/hyperv/utilities/vmbus_heartbeat.c optional hyperv dev/hyperv/utilities/vmbus_ic.c optional hyperv dev/hyperv/utilities/vmbus_shutdown.c optional hyperv dev/hyperv/utilities/vmbus_timesync.c optional hyperv dev/hyperv/vmbus/hyperv.c optional hyperv dev/hyperv/vmbus/hyperv_busdma.c optional hyperv dev/hyperv/vmbus/vmbus.c optional hyperv pci dev/hyperv/vmbus/vmbus_br.c optional hyperv dev/hyperv/vmbus/vmbus_chan.c optional hyperv dev/hyperv/vmbus/vmbus_et.c optional hyperv dev/hyperv/vmbus/vmbus_if.m optional hyperv dev/hyperv/vmbus/vmbus_res.c optional hyperv dev/hyperv/vmbus/vmbus_xact.c optional hyperv dev/hyperv/vmbus/amd64/hyperv_machdep.c optional hyperv dev/hyperv/vmbus/amd64/vmbus_vector.S optional hyperv dev/nctgpio/nctgpio.c optional nctgpio dev/nfe/if_nfe.c optional nfe pci dev/ntb/if_ntb/if_ntb.c optional if_ntb dev/ntb/ntb_transport.c optional ntb_transport | if_ntb dev/ntb/ntb.c optional ntb | ntb_transport | if_ntb | ntb_hw_intel | ntb_hw_plx | ntb_hw dev/ntb/ntb_if.m optional ntb | ntb_transport | if_ntb | ntb_hw_intel | ntb_hw_plx | ntb_hw dev/ntb/ntb_hw/ntb_hw_intel.c optional ntb_hw_intel | ntb_hw dev/ntb/ntb_hw/ntb_hw_plx.c optional ntb_hw_plx | ntb_hw dev/nvd/nvd.c optional nvd nvme dev/nvme/nvme.c optional nvme dev/nvme/nvme_ctrlr.c optional nvme dev/nvme/nvme_ctrlr_cmd.c optional nvme dev/nvme/nvme_ns.c optional nvme dev/nvme/nvme_ns_cmd.c optional nvme dev/nvme/nvme_qpair.c optional nvme dev/nvme/nvme_sim.c optional nvme scbus dev/nvme/nvme_sysctl.c optional nvme dev/nvme/nvme_test.c optional nvme dev/nvme/nvme_util.c optional nvme dev/nvram/nvram.c optional nvram isa dev/random/ivy.c optional rdrand_rng dev/random/nehemiah.c optional padlock_rng dev/qlxge/qls_dbg.c optional qlxge pci dev/qlxge/qls_dump.c optional qlxge pci dev/qlxge/qls_hw.c optional qlxge pci dev/qlxge/qls_ioctl.c optional qlxge pci dev/qlxge/qls_isr.c optional qlxge pci dev/qlxge/qls_os.c optional qlxge pci dev/qlxgb/qla_dbg.c optional qlxgb pci dev/qlxgb/qla_hw.c optional qlxgb pci dev/qlxgb/qla_ioctl.c optional qlxgb pci dev/qlxgb/qla_isr.c optional qlxgb pci dev/qlxgb/qla_misc.c optional qlxgb pci dev/qlxgb/qla_os.c optional qlxgb pci dev/qlxgbe/ql_dbg.c optional qlxgbe pci dev/qlxgbe/ql_hw.c optional qlxgbe pci dev/qlxgbe/ql_ioctl.c optional qlxgbe pci dev/qlxgbe/ql_isr.c optional qlxgbe pci dev/qlxgbe/ql_misc.c optional qlxgbe pci dev/qlxgbe/ql_os.c optional qlxgbe pci dev/qlxgbe/ql_reset.c optional qlxgbe pci dev/qlnx/qlnxe/ecore_cxt.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_dcbx.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_dev.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_hw.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_init_fw_funcs.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_init_ops.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_int.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_l2.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_mcp.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_sp_commands.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/ecore_spq.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/qlnx_ioctl.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/qlnx/qlnxe/qlnx_os.c optional qlnxe pci \ compile-with "${LINUXKPI_C}" dev/sfxge/common/ef10_ev.c optional sfxge pci dev/sfxge/common/ef10_filter.c optional sfxge pci dev/sfxge/common/ef10_intr.c optional sfxge pci dev/sfxge/common/ef10_mac.c optional sfxge pci dev/sfxge/common/ef10_mcdi.c optional sfxge pci dev/sfxge/common/ef10_nic.c optional sfxge pci dev/sfxge/common/ef10_nvram.c optional sfxge pci dev/sfxge/common/ef10_phy.c optional sfxge pci dev/sfxge/common/ef10_rx.c optional sfxge pci dev/sfxge/common/ef10_tx.c optional sfxge pci dev/sfxge/common/ef10_vpd.c optional sfxge pci dev/sfxge/common/efx_bootcfg.c optional sfxge pci dev/sfxge/common/efx_crc32.c optional sfxge pci dev/sfxge/common/efx_ev.c optional sfxge pci dev/sfxge/common/efx_filter.c optional sfxge pci dev/sfxge/common/efx_hash.c optional sfxge pci dev/sfxge/common/efx_intr.c optional sfxge pci dev/sfxge/common/efx_lic.c optional sfxge pci dev/sfxge/common/efx_mac.c optional sfxge pci dev/sfxge/common/efx_mcdi.c optional sfxge pci dev/sfxge/common/efx_mon.c optional sfxge pci dev/sfxge/common/efx_nic.c optional sfxge pci dev/sfxge/common/efx_nvram.c optional sfxge pci dev/sfxge/common/efx_phy.c optional sfxge pci dev/sfxge/common/efx_port.c optional sfxge pci dev/sfxge/common/efx_rx.c optional sfxge pci dev/sfxge/common/efx_sram.c optional sfxge pci dev/sfxge/common/efx_tx.c optional sfxge pci dev/sfxge/common/efx_vpd.c optional sfxge pci dev/sfxge/common/hunt_nic.c optional sfxge pci dev/sfxge/common/mcdi_mon.c optional sfxge pci dev/sfxge/common/medford_nic.c optional sfxge pci dev/sfxge/common/siena_mac.c optional sfxge pci dev/sfxge/common/siena_mcdi.c optional sfxge pci dev/sfxge/common/siena_nic.c optional sfxge pci dev/sfxge/common/siena_nvram.c optional sfxge pci dev/sfxge/common/siena_phy.c optional sfxge pci dev/sfxge/common/siena_sram.c optional sfxge pci dev/sfxge/common/siena_vpd.c optional sfxge pci dev/sfxge/sfxge.c optional sfxge pci dev/sfxge/sfxge_dma.c optional sfxge pci dev/sfxge/sfxge_ev.c optional sfxge pci dev/sfxge/sfxge_intr.c optional sfxge pci dev/sfxge/sfxge_mcdi.c optional sfxge pci dev/sfxge/sfxge_nvram.c optional sfxge pci dev/sfxge/sfxge_port.c optional sfxge pci dev/sfxge/sfxge_rx.c optional sfxge pci dev/sfxge/sfxge_tx.c optional sfxge pci dev/sio/sio.c optional sio dev/sio/sio_isa.c optional sio isa dev/sio/sio_pccard.c optional sio pccard dev/sio/sio_pci.c optional sio pci dev/sio/sio_puc.c optional sio puc dev/smartpqi/smartpqi_cam.c optional smartpqi dev/smartpqi/smartpqi_cmd.c optional smartpqi dev/smartpqi/smartpqi_discovery.c optional smartpqi dev/smartpqi/smartpqi_event.c optional smartpqi dev/smartpqi/smartpqi_helper.c optional smartpqi dev/smartpqi/smartpqi_init.c optional smartpqi dev/smartpqi/smartpqi_intr.c optional smartpqi dev/smartpqi/smartpqi_ioctl.c optional smartpqi dev/smartpqi/smartpqi_main.c optional smartpqi dev/smartpqi/smartpqi_mem.c optional smartpqi dev/smartpqi/smartpqi_misc.c optional smartpqi dev/smartpqi/smartpqi_queue.c optional smartpqi dev/smartpqi/smartpqi_request.c optional smartpqi dev/smartpqi/smartpqi_response.c optional smartpqi dev/smartpqi/smartpqi_sis.c optional smartpqi dev/smartpqi/smartpqi_tag.c optional smartpqi dev/speaker/spkr.c optional speaker dev/syscons/apm/apm_saver.c optional apm_saver apm dev/syscons/scterm-teken.c optional sc dev/syscons/scvesactl.c optional sc vga vesa dev/syscons/scvgarndr.c optional sc vga dev/syscons/scvtb.c optional sc dev/tpm/tpm.c optional tpm dev/tpm/tpm_acpi.c optional tpm acpi dev/tpm/tpm_isa.c optional tpm isa dev/uart/uart_cpu_x86.c optional uart dev/viawd/viawd.c optional viawd dev/vmware/vmxnet3/if_vmx.c optional vmx dev/vmware/vmci/vmci.c optional vmci dev/vmware/vmci/vmci_datagram.c optional vmci dev/vmware/vmci/vmci_doorbell.c optional vmci dev/vmware/vmci/vmci_driver.c optional vmci dev/vmware/vmci/vmci_event.c optional vmci dev/vmware/vmci/vmci_hashtable.c optional vmci dev/vmware/vmci/vmci_kernel_if.c optional vmci dev/vmware/vmci/vmci_qpair.c optional vmci dev/vmware/vmci/vmci_queue_pair.c optional vmci dev/vmware/vmci/vmci_resource.c optional vmci dev/wbwd/wbwd.c optional wbwd dev/xen/pci/xen_acpi_pci.c optional xenhvm dev/xen/pci/xen_pci.c optional xenhvm dev/isci/isci.c optional isci dev/isci/isci_controller.c optional isci dev/isci/isci_domain.c optional isci dev/isci/isci_interrupt.c optional isci dev/isci/isci_io_request.c optional isci dev/isci/isci_logger.c optional isci dev/isci/isci_oem_parameters.c optional isci dev/isci/isci_remote_device.c optional isci dev/isci/isci_sysctl.c optional isci dev/isci/isci_task_request.c optional isci dev/isci/isci_timer.c optional isci dev/isci/scil/sati.c optional isci dev/isci/scil/sati_abort_task_set.c optional isci dev/isci/scil/sati_atapi.c optional isci dev/isci/scil/sati_device.c optional isci dev/isci/scil/sati_inquiry.c optional isci dev/isci/scil/sati_log_sense.c optional isci dev/isci/scil/sati_lun_reset.c optional isci dev/isci/scil/sati_mode_pages.c optional isci dev/isci/scil/sati_mode_select.c optional isci dev/isci/scil/sati_mode_sense.c optional isci dev/isci/scil/sati_mode_sense_10.c optional isci dev/isci/scil/sati_mode_sense_6.c optional isci dev/isci/scil/sati_move.c optional isci dev/isci/scil/sati_passthrough.c optional isci dev/isci/scil/sati_read.c optional isci dev/isci/scil/sati_read_buffer.c optional isci dev/isci/scil/sati_read_capacity.c optional isci dev/isci/scil/sati_reassign_blocks.c optional isci dev/isci/scil/sati_report_luns.c optional isci dev/isci/scil/sati_request_sense.c optional isci dev/isci/scil/sati_start_stop_unit.c optional isci dev/isci/scil/sati_synchronize_cache.c optional isci dev/isci/scil/sati_test_unit_ready.c optional isci dev/isci/scil/sati_unmap.c optional isci dev/isci/scil/sati_util.c optional isci dev/isci/scil/sati_verify.c optional isci dev/isci/scil/sati_write.c optional isci dev/isci/scil/sati_write_and_verify.c optional isci dev/isci/scil/sati_write_buffer.c optional isci dev/isci/scil/sati_write_long.c optional isci dev/isci/scil/sci_abstract_list.c optional isci dev/isci/scil/sci_base_controller.c optional isci dev/isci/scil/sci_base_domain.c optional isci dev/isci/scil/sci_base_iterator.c optional isci dev/isci/scil/sci_base_library.c optional isci dev/isci/scil/sci_base_logger.c optional isci dev/isci/scil/sci_base_memory_descriptor_list.c optional isci dev/isci/scil/sci_base_memory_descriptor_list_decorator.c optional isci dev/isci/scil/sci_base_object.c optional isci dev/isci/scil/sci_base_observer.c optional isci dev/isci/scil/sci_base_phy.c optional isci dev/isci/scil/sci_base_port.c optional isci dev/isci/scil/sci_base_remote_device.c optional isci dev/isci/scil/sci_base_request.c optional isci dev/isci/scil/sci_base_state_machine.c optional isci dev/isci/scil/sci_base_state_machine_logger.c optional isci dev/isci/scil/sci_base_state_machine_observer.c optional isci dev/isci/scil/sci_base_subject.c optional isci dev/isci/scil/sci_util.c optional isci dev/isci/scil/scic_sds_controller.c optional isci dev/isci/scil/scic_sds_library.c optional isci dev/isci/scil/scic_sds_pci.c optional isci dev/isci/scil/scic_sds_phy.c optional isci dev/isci/scil/scic_sds_port.c optional isci dev/isci/scil/scic_sds_port_configuration_agent.c optional isci dev/isci/scil/scic_sds_remote_device.c optional isci dev/isci/scil/scic_sds_remote_node_context.c optional isci dev/isci/scil/scic_sds_remote_node_table.c optional isci dev/isci/scil/scic_sds_request.c optional isci dev/isci/scil/scic_sds_sgpio.c optional isci dev/isci/scil/scic_sds_smp_remote_device.c optional isci dev/isci/scil/scic_sds_smp_request.c optional isci dev/isci/scil/scic_sds_ssp_request.c optional isci dev/isci/scil/scic_sds_stp_packet_request.c optional isci dev/isci/scil/scic_sds_stp_remote_device.c optional isci dev/isci/scil/scic_sds_stp_request.c optional isci dev/isci/scil/scic_sds_unsolicited_frame_control.c optional isci dev/isci/scil/scif_sas_controller.c optional isci dev/isci/scil/scif_sas_controller_state_handlers.c optional isci dev/isci/scil/scif_sas_controller_states.c optional isci dev/isci/scil/scif_sas_domain.c optional isci dev/isci/scil/scif_sas_domain_state_handlers.c optional isci dev/isci/scil/scif_sas_domain_states.c optional isci dev/isci/scil/scif_sas_high_priority_request_queue.c optional isci dev/isci/scil/scif_sas_internal_io_request.c optional isci dev/isci/scil/scif_sas_io_request.c optional isci dev/isci/scil/scif_sas_io_request_state_handlers.c optional isci dev/isci/scil/scif_sas_io_request_states.c optional isci dev/isci/scil/scif_sas_library.c optional isci dev/isci/scil/scif_sas_remote_device.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substates.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substates.c optional isci dev/isci/scil/scif_sas_remote_device_state_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_states.c optional isci dev/isci/scil/scif_sas_request.c optional isci dev/isci/scil/scif_sas_smp_activity_clear_affiliation.c optional isci dev/isci/scil/scif_sas_smp_io_request.c optional isci dev/isci/scil/scif_sas_smp_phy.c optional isci dev/isci/scil/scif_sas_smp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_io_request.c optional isci dev/isci/scil/scif_sas_stp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_task_request.c optional isci dev/isci/scil/scif_sas_task_request.c optional isci dev/isci/scil/scif_sas_task_request_state_handlers.c optional isci dev/isci/scil/scif_sas_task_request_states.c optional isci dev/isci/scil/scif_sas_timer.c optional isci isa/syscons_isa.c optional sc isa/vga_isa.c optional vga kern/kern_clocksource.c standard kern/link_elf_obj.c standard libkern/x86/crc32_sse42.c standard # # IA32 binary support # #amd64/ia32/ia32_exception.S optional compat_freebsd32 amd64/ia32/ia32_reg.c optional compat_freebsd32 amd64/ia32/ia32_signal.c optional compat_freebsd32 amd64/ia32/ia32_sigtramp.S optional compat_freebsd32 amd64/ia32/ia32_syscall.c optional compat_freebsd32 amd64/ia32/ia32_misc.c optional compat_freebsd32 compat/ia32/ia32_sysvec.c optional compat_freebsd32 compat/linprocfs/linprocfs.c optional linprocfs compat/linsysfs/linsysfs.c optional linsysfs # # Linux/i386 binary support # amd64/linux32/linux32_dummy.c optional compat_linux32 amd64/linux32/linux32_machdep.c optional compat_linux32 amd64/linux32/linux32_support.s optional compat_linux32 \ dependency "linux32_assym.h" amd64/linux32/linux32_sysent.c optional compat_linux32 amd64/linux32/linux32_sysvec.c optional compat_linux32 compat/linux/linux_emul.c optional compat_linux32 compat/linux/linux_errno.c optional compat_linux32 compat/linux/linux_file.c optional compat_linux32 compat/linux/linux_fork.c optional compat_linux32 compat/linux/linux_futex.c optional compat_linux32 compat/linux/linux_getcwd.c optional compat_linux32 compat/linux/linux_ioctl.c optional compat_linux32 compat/linux/linux_ipc.c optional compat_linux32 compat/linux/linux_mib.c optional compat_linux32 compat/linux/linux_misc.c optional compat_linux32 compat/linux/linux_mmap.c optional compat_linux32 compat/linux/linux_signal.c optional compat_linux32 compat/linux/linux_socket.c optional compat_linux32 compat/linux/linux_stats.c optional compat_linux32 compat/linux/linux_sysctl.c optional compat_linux32 compat/linux/linux_time.c optional compat_linux32 compat/linux/linux_timer.c optional compat_linux32 compat/linux/linux_uid16.c optional compat_linux32 compat/linux/linux_util.c optional compat_linux32 compat/linux/linux_vdso.c optional compat_linux32 compat/linux/linux_common.c optional compat_linux32 compat/linux/linux_event.c optional compat_linux32 compat/linux/linux.c optional compat_linux32 dev/amr/amr_linux.c optional compat_linux32 amr dev/mfi/mfi_linux.c optional compat_linux32 mfi # # Windows NDIS driver support # compat/ndis/kern_ndis.c optional ndisapi pci compat/ndis/kern_windrv.c optional ndisapi pci compat/ndis/subr_hal.c optional ndisapi pci compat/ndis/subr_ndis.c optional ndisapi pci compat/ndis/subr_ntoskrnl.c optional ndisapi pci compat/ndis/subr_pe.c optional ndisapi pci compat/ndis/subr_usbd.c optional ndisapi pci compat/ndis/winx64_wrap.S optional ndisapi pci # # x86 real mode BIOS emulator, required by dpms/pci/vesa # compat/x86bios/x86bios.c optional x86bios | dpms | pci | vesa contrib/x86emu/x86emu.c optional x86bios | dpms | pci | vesa # # bvm console # dev/bvm/bvm_console.c optional bvmconsole dev/bvm/bvm_dbg.c optional bvmdebug # # x86 shared code between IA32 and AMD64 architectures # x86/acpica/OsdEnvironment.c optional acpi x86/acpica/acpi_apm.c optional acpi x86/acpica/acpi_wakeup.c optional acpi x86/acpica/madt.c optional acpi x86/acpica/srat.c optional acpi x86/bios/smbios.c optional smbios x86/bios/vpd.c optional vpd x86/cpufreq/powernow.c optional cpufreq x86/cpufreq/est.c optional cpufreq x86/cpufreq/hwpstate.c optional cpufreq x86/cpufreq/p4tcc.c optional cpufreq x86/iommu/busdma_dmar.c optional acpi acpi_dmar pci x86/iommu/intel_ctx.c optional acpi acpi_dmar pci x86/iommu/intel_drv.c optional acpi acpi_dmar pci x86/iommu/intel_fault.c optional acpi acpi_dmar pci x86/iommu/intel_gas.c optional acpi acpi_dmar pci x86/iommu/intel_idpgtbl.c optional acpi acpi_dmar pci x86/iommu/intel_intrmap.c optional acpi acpi_dmar pci x86/iommu/intel_qi.c optional acpi acpi_dmar pci x86/iommu/intel_quirks.c optional acpi acpi_dmar pci x86/iommu/intel_utils.c optional acpi acpi_dmar pci x86/isa/atpic.c optional atpic isa x86/isa/atrtc.c standard x86/isa/clock.c standard x86/isa/elcr.c optional atpic isa | mptable x86/isa/isa.c standard x86/isa/isa_dma.c standard x86/isa/nmi.c standard x86/isa/orm.c optional isa x86/pci/pci_bus.c optional pci x86/pci/qpi.c optional pci x86/x86/autoconf.c standard x86/x86/bus_machdep.c standard x86/x86/busdma_bounce.c standard x86/x86/busdma_machdep.c standard x86/x86/cpu_machdep.c standard x86/x86/dump_machdep.c standard x86/x86/fdt_machdep.c optional fdt x86/x86/identcpu.c standard x86/x86/intr_machdep.c standard x86/x86/io_apic.c standard x86/x86/legacy.c standard x86/x86/local_apic.c standard x86/x86/mca.c standard x86/x86/x86_mem.c optional mem x86/x86/mptable.c optional mptable x86/x86/mptable_pci.c optional mptable pci x86/x86/mp_x86.c optional smp x86/x86/mp_watchdog.c optional mp_watchdog smp x86/x86/msi.c optional pci x86/x86/nexus.c standard x86/x86/pvclock.c standard x86/x86/stack_machdep.c optional ddb | stack x86/x86/tsc.c standard x86/x86/delay.c standard x86/xen/hvm.c optional xenhvm x86/xen/xen_intr.c optional xenhvm x86/xen/pv.c optional xenhvm x86/xen/pvcpu_enum.c optional xenhvm x86/xen/xen_apic.c optional xenhvm x86/xen/xenpv.c optional xenhvm x86/xen/xen_nexus.c optional xenhvm x86/xen/xen_msi.c optional xenhvm x86/xen/xen_pci_bus.c optional xenhvm diff --git a/sys/conf/files.i386 b/sys/conf/files.i386 index e06c4f6fb57c..513c35363cff 100644 --- a/sys/conf/files.i386 +++ b/sys/conf/files.i386 @@ -1,636 +1,633 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_i686.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_i686.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf32-i386-freebsd --binary-architecture i386 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # linux_genassym.o optional compat_linux \ dependency "$S/i386/linux/linux_genassym.c" \ compile-with "${CC} ${CFLAGS:N-flto:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "linux_genassym.o" # linux_assym.h optional compat_linux \ dependency "$S/kern/genassym.sh linux_genassym.o" \ compile-with "sh $S/kern/genassym.sh linux_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "linux_assym.h" # linux_locore.o optional compat_linux \ dependency "linux_assym.h $S/i386/linux/linux_locore.s" \ compile-with "${CC} -x assembler-with-cpp -DLOCORE -shared -s -pipe -I. -I$S -Werror -Wall -fPIC -fno-common -nostdinc -nostdlib -Wl,-T$S/i386/linux/linux_vdso.lds.s -Wl,-soname=linux_vdso.so,--eh-frame-hdr,-warn-common ${.IMPSRC} -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "linux_locore.o" # linux_vdso.so optional compat_linux \ dependency "linux_locore.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf32-i386-freebsd --binary-architecture i386 linux_locore.o ${.TARGET}" \ no-implicit-rule \ clean "linux_vdso.so" # font.h optional sc_dflt_font \ compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'static u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'static u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'static u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ no-obj no-implicit-rule before-depend \ clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" # atkbdmap.h optional atkbd_dflt_keymap \ compile-with "kbdcontrol -P ${S:S/sys$/share/}/vt/keymaps -P ${S:S/sys$/share/}/syscons/keymaps -L ${ATKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > atkbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "atkbdmap.h" # ukbdmap.h optional ukbd_dflt_keymap \ compile-with "kbdcontrol -P ${S:S/sys$/share/}/vt/keymaps -P ${S:S/sys$/share/}/syscons/keymaps -L ${UKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > ukbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "ukbdmap.h" # hpt27xx_lib.o optional hpt27xx \ dependency "$S/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu" \ compile-with "uudecode < $S/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu" \ no-implicit-rule # hptmvraid.o optional hptmv \ dependency "$S/dev/hptmv/i386-elf.raid.o.uu" \ compile-with "uudecode < $S/dev/hptmv/i386-elf.raid.o.uu" \ no-implicit-rule # hptnr_lib.o optional hptnr \ dependency "$S/dev/hptnr/i386-elf.hptnr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptnr/i386-elf.hptnr_lib.o.uu" \ no-implicit-rule # hptrr_lib.o optional hptrr \ dependency "$S/dev/hptrr/i386-elf.hptrr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptrr/i386-elf.hptrr_lib.o.uu" \ no-implicit-rule # cddl/contrib/opensolaris/common/atomic/i386/opensolaris_atomic.S optional zfs | dtrace compile-with "${ZFS_S}" cddl/dev/dtrace/i386/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/i386/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/x86/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" cddl/dev/dtrace/x86/dis_tables.c optional dtrace_fbt | dtraceall compile-with "${DTRACE_C}" cddl/dev/dtrace/x86/instr_size.c optional dtrace_fbt | dtraceall compile-with "${DTRACE_C}" compat/linprocfs/linprocfs.c optional linprocfs compat/linsysfs/linsysfs.c optional linsysfs compat/linux/linux_event.c optional compat_linux compat/linux/linux_emul.c optional compat_linux compat/linux/linux_errno.c optional compat_linux compat/linux/linux_file.c optional compat_linux compat/linux/linux_fork.c optional compat_linux compat/linux/linux_futex.c optional compat_linux compat/linux/linux_getcwd.c optional compat_linux compat/linux/linux_ioctl.c optional compat_linux compat/linux/linux_ipc.c optional compat_linux compat/linux/linux_mib.c optional compat_linux compat/linux/linux_misc.c optional compat_linux compat/linux/linux_mmap.c optional compat_linux compat/linux/linux_signal.c optional compat_linux compat/linux/linux_socket.c optional compat_linux compat/linux/linux_stats.c optional compat_linux compat/linux/linux_sysctl.c optional compat_linux compat/linux/linux_time.c optional compat_linux compat/linux/linux_timer.c optional compat_linux compat/linux/linux_uid16.c optional compat_linux compat/linux/linux_util.c optional compat_linux compat/linux/linux_vdso.c optional compat_linux compat/linux/linux.c optional compat_linux compat/ndis/kern_ndis.c optional ndisapi pci compat/ndis/kern_windrv.c optional ndisapi pci compat/ndis/subr_hal.c optional ndisapi pci compat/ndis/subr_ndis.c optional ndisapi pci compat/ndis/subr_ntoskrnl.c optional ndisapi pci compat/ndis/subr_pe.c optional ndisapi pci compat/ndis/subr_usbd.c optional ndisapi pci compat/ndis/winx32_wrap.S optional ndisapi pci bf_enc.o optional crypto | ipsec | ipsec_support \ dependency "$S/crypto/blowfish/arch/i386/bf_enc.S $S/crypto/blowfish/arch/i386/bf_enc_586.S $S/crypto/blowfish/arch/i386/bf_enc_686.S" \ compile-with "${CC} -c -I$S/crypto/blowfish/arch/i386 ${ASM_CFLAGS} ${WERROR} ${.IMPSRC}" \ no-implicit-rule crypto/aesni/aeskeys_i386.S optional aesni crypto/aesni/aesni.c optional aesni aesni_ghash.o optional aesni \ dependency "$S/crypto/aesni/aesni_ghash.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -mmmx -msse -msse4 -maes -mpclmul ${.IMPSRC}" \ no-implicit-rule \ clean "aesni_ghash.o" aesni_wrap.o optional aesni \ dependency "$S/crypto/aesni/aesni_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -mmmx -msse -msse4 -maes ${.IMPSRC}" \ no-implicit-rule \ clean "aesni_wrap.o" crypto/des/arch/i386/des_enc.S optional crypto | ipsec | ipsec_support | netsmb intel_sha1.o optional aesni \ dependency "$S/crypto/aesni/intel_sha1.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${PROF} -mmmx -msse -msse4 -msha ${.IMPSRC}" \ no-implicit-rule \ clean "intel_sha1.o" intel_sha256.o optional aesni \ dependency "$S/crypto/aesni/intel_sha256.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${PROF} -mmmx -msse -msse4 -msha ${.IMPSRC}" \ no-implicit-rule \ clean "intel_sha256.o" crypto/via/padlock.c optional padlock crypto/via/padlock_cipher.c optional padlock crypto/via/padlock_hash.c optional padlock dev/acpica/acpi_pci.c optional acpi pci dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pcib_acpi.c optional acpi pci dev/acpica/acpi_pcib_pci.c optional acpi pci dev/advansys/adv_isa.c optional adv isa dev/agp/agp_ali.c optional agp dev/agp/agp_amd.c optional agp dev/agp/agp_amd64.c optional agp dev/agp/agp_ati.c optional agp dev/agp/agp_i810.c optional agp dev/agp/agp_intel.c optional agp dev/agp/agp_nvidia.c optional agp dev/agp/agp_sis.c optional agp dev/agp/agp_via.c optional agp dev/aic/aic_isa.c optional aic isa dev/amdsbwd/amdsbwd.c optional amdsbwd dev/amdsmn/amdsmn.c optional amdsmn | amdtemp dev/amdtemp/amdtemp.c optional amdtemp dev/arcmsr/arcmsr.c optional arcmsr pci dev/asmc/asmc.c optional asmc isa dev/atkbdc/atkbd.c optional atkbd atkbdc dev/atkbdc/atkbd_atkbdc.c optional atkbd atkbdc dev/atkbdc/atkbdc.c optional atkbdc dev/atkbdc/atkbdc_isa.c optional atkbdc isa dev/atkbdc/atkbdc_subr.c optional atkbdc dev/atkbdc/psm.c optional psm atkbdc dev/bxe/bxe.c optional bxe pci dev/bxe/bxe_stats.c optional bxe pci dev/bxe/bxe_debug.c optional bxe pci dev/bxe/ecore_sp.c optional bxe pci dev/bxe/bxe_elink.c optional bxe pci dev/bxe/57710_init_values.c optional bxe pci dev/bxe/57711_init_values.c optional bxe pci dev/bxe/57712_init_values.c optional bxe pci dev/ce/ceddk.c optional ce dev/ce/if_ce.c optional ce dev/ce/tau32-ddk.c optional ce \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/coretemp/coretemp.c optional coretemp dev/cp/cpddk.c optional cp dev/cp/if_cp.c optional cp dev/cpuctl/cpuctl.c optional cpuctl dev/ctau/ctau.c optional ctau dev/ctau/ctddk.c optional ctau dev/ctau/if_ct.c optional ctau dev/cx/csigma.c optional cx dev/cx/cxddk.c optional cx dev/cx/if_cx.c optional cx dev/dpms/dpms.c optional dpms dev/ed/if_ed_3c503.c optional ed isa ed_3c503 dev/ed/if_ed_isa.c optional ed isa dev/ed/if_ed_wd80x3.c optional ed isa dev/ed/if_ed_hpp.c optional ed isa ed_hpp dev/ed/if_ed_sic.c optional ed isa ed_sic dev/ep/elink.c optional ep dev/fb/fb.c optional fb | vga dev/fb/s3_pci.c optional s3pci dev/fb/vesa.c optional vga vesa dev/fb/vga.c optional vga dev/fdc/fdc.c optional fdc dev/fdc/fdc_acpi.c optional fdc dev/fdc/fdc_isa.c optional fdc isa dev/fdc/fdc_pccard.c optional fdc pccard dev/fe/if_fe_isa.c optional fe isa dev/glxiic/glxiic.c optional glxiic dev/glxsb/glxsb.c optional glxsb dev/glxsb/glxsb_hash.c optional glxsb dev/gpio/bytgpio.c optional bytgpio dev/gpio/chvgpio.c optional chvgpio dev/hpt27xx/hpt27xx_os_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_osm_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_config.c optional hpt27xx dev/hptmv/entry.c optional hptmv dev/hptmv/mv.c optional hptmv dev/hptmv/gui_lib.c optional hptmv dev/hptmv/hptproc.c optional hptmv dev/hptmv/ioctl.c optional hptmv dev/hptnr/hptnr_os_bsd.c optional hptnr dev/hptnr/hptnr_osm_bsd.c optional hptnr dev/hptnr/hptnr_config.c optional hptnr dev/hptrr/hptrr_os_bsd.c optional hptrr dev/hptrr/hptrr_osm_bsd.c optional hptrr dev/hptrr/hptrr_config.c optional hptrr dev/hwpmc/hwpmc_amd.c optional hwpmc dev/hwpmc/hwpmc_intel.c optional hwpmc dev/hwpmc/hwpmc_core.c optional hwpmc dev/hwpmc/hwpmc_uncore.c optional hwpmc -dev/hwpmc/hwpmc_pentium.c optional hwpmc -dev/hwpmc/hwpmc_piv.c optional hwpmc -dev/hwpmc/hwpmc_ppro.c optional hwpmc dev/hwpmc/hwpmc_tsc.c optional hwpmc dev/hwpmc/hwpmc_x86.c optional hwpmc dev/hyperv/pcib/vmbus_pcib.c optional hyperv pci dev/hyperv/netvsc/hn_nvs.c optional hyperv dev/hyperv/netvsc/hn_rndis.c optional hyperv dev/hyperv/netvsc/if_hn.c optional hyperv dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c optional hyperv dev/hyperv/utilities/hv_kvp.c optional hyperv dev/hyperv/utilities/hv_snapshot.c optional hyperv dev/hyperv/utilities/vmbus_heartbeat.c optional hyperv dev/hyperv/utilities/vmbus_ic.c optional hyperv dev/hyperv/utilities/vmbus_shutdown.c optional hyperv dev/hyperv/utilities/vmbus_timesync.c optional hyperv dev/hyperv/vmbus/hyperv.c optional hyperv dev/hyperv/vmbus/hyperv_busdma.c optional hyperv dev/hyperv/vmbus/vmbus.c optional hyperv pci dev/hyperv/vmbus/vmbus_br.c optional hyperv dev/hyperv/vmbus/vmbus_chan.c optional hyperv dev/hyperv/vmbus/vmbus_et.c optional hyperv dev/hyperv/vmbus/vmbus_if.m optional hyperv dev/hyperv/vmbus/vmbus_res.c optional hyperv dev/hyperv/vmbus/vmbus_xact.c optional hyperv dev/hyperv/vmbus/i386/hyperv_machdep.c optional hyperv dev/hyperv/vmbus/i386/vmbus_vector.S optional hyperv dev/ichwd/ichwd.c optional ichwd dev/if_ndis/if_ndis.c optional ndis dev/if_ndis/if_ndis_pccard.c optional ndis pccard dev/if_ndis/if_ndis_pci.c optional ndis cardbus | ndis pci dev/if_ndis/if_ndis_usb.c optional ndis usb dev/imcsmb/imcsmb.c optional imcsmb dev/imcsmb/imcsmb_pci.c optional imcsmb pci dev/intel/spi.c optional intelspi dev/io/iodev.c optional io dev/ipmi/ipmi.c optional ipmi dev/ipmi/ipmi_acpi.c optional ipmi acpi dev/ipmi/ipmi_isa.c optional ipmi isa dev/ipmi/ipmi_kcs.c optional ipmi dev/ipmi/ipmi_smic.c optional ipmi dev/ipmi/ipmi_smbus.c optional ipmi smbus dev/ipmi/ipmi_smbios.c optional ipmi dev/ipmi/ipmi_ssif.c optional ipmi smbus dev/ipmi/ipmi_pci.c optional ipmi pci dev/ipmi/ipmi_linux.c optional ipmi compat_linux dev/le/if_le_isa.c optional le isa dev/mse/mse.c optional mse dev/mse/mse_isa.c optional mse isa dev/nctgpio/nctgpio.c optional nctgpio dev/nfe/if_nfe.c optional nfe pci dev/ntb/if_ntb/if_ntb.c optional if_ntb dev/ntb/ntb_transport.c optional ntb_transport | if_ntb dev/ntb/ntb.c optional ntb | ntb_transport | if_ntb | ntb_hw_intel | ntb_hw_plx | ntb_hw dev/ntb/ntb_if.m optional ntb | ntb_transport | if_ntb | ntb_hw_intel | ntb_hw_plx | ntb_hw dev/ntb/ntb_hw/ntb_hw_intel.c optional ntb_hw_intel | ntb_hw dev/ntb/ntb_hw/ntb_hw_plx.c optional ntb_hw_plx | ntb_hw dev/nvd/nvd.c optional nvd nvme dev/nvme/nvme.c optional nvme dev/nvme/nvme_ctrlr.c optional nvme dev/nvme/nvme_ctrlr_cmd.c optional nvme dev/nvme/nvme_ns.c optional nvme dev/nvme/nvme_ns_cmd.c optional nvme dev/nvme/nvme_qpair.c optional nvme dev/nvme/nvme_sysctl.c optional nvme dev/nvme/nvme_test.c optional nvme dev/nvme/nvme_util.c optional nvme dev/nvram/nvram.c optional nvram isa dev/ofw/ofwpci.c optional fdt pci dev/pcf/pcf_isa.c optional pcf dev/random/ivy.c optional rdrand_rng dev/random/nehemiah.c optional padlock_rng dev/sbni/if_sbni.c optional sbni dev/sbni/if_sbni_isa.c optional sbni isa dev/sbni/if_sbni_pci.c optional sbni pci dev/sio/sio.c optional sio dev/sio/sio_isa.c optional sio isa dev/sio/sio_pccard.c optional sio pccard dev/sio/sio_pci.c optional sio pci dev/sio/sio_puc.c optional sio puc dev/speaker/spkr.c optional speaker dev/syscons/apm/apm_saver.c optional apm_saver apm dev/syscons/scterm-teken.c optional sc dev/syscons/scvesactl.c optional sc vga vesa dev/syscons/scvgarndr.c optional sc vga dev/syscons/scvtb.c optional sc dev/tpm/tpm.c optional tpm dev/tpm/tpm_acpi.c optional tpm acpi dev/tpm/tpm_isa.c optional tpm isa dev/uart/uart_cpu_x86.c optional uart dev/viawd/viawd.c optional viawd dev/vmware/vmxnet3/if_vmx.c optional vmx dev/vmware/vmci/vmci.c optional vmci dev/vmware/vmci/vmci_datagram.c optional vmci dev/vmware/vmci/vmci_doorbell.c optional vmci dev/vmware/vmci/vmci_driver.c optional vmci dev/vmware/vmci/vmci_event.c optional vmci dev/vmware/vmci/vmci_hashtable.c optional vmci dev/vmware/vmci/vmci_kernel_if.c optional vmci dev/vmware/vmci/vmci_qpair.c optional vmci dev/vmware/vmci/vmci_queue_pair.c optional vmci dev/vmware/vmci/vmci_resource.c optional vmci dev/acpica/acpi_if.m standard dev/acpica/acpi_hpet.c optional acpi dev/acpica/acpi_timer.c optional acpi dev/acpi_support/acpi_wmi_if.m standard dev/wbwd/wbwd.c optional wbwd dev/isci/isci.c optional isci dev/isci/isci_controller.c optional isci dev/isci/isci_domain.c optional isci dev/isci/isci_interrupt.c optional isci dev/isci/isci_io_request.c optional isci dev/isci/isci_logger.c optional isci dev/isci/isci_oem_parameters.c optional isci dev/isci/isci_remote_device.c optional isci dev/isci/isci_sysctl.c optional isci dev/isci/isci_task_request.c optional isci dev/isci/isci_timer.c optional isci dev/isci/scil/sati.c optional isci dev/isci/scil/sati_abort_task_set.c optional isci dev/isci/scil/sati_atapi.c optional isci dev/isci/scil/sati_device.c optional isci dev/isci/scil/sati_inquiry.c optional isci dev/isci/scil/sati_log_sense.c optional isci dev/isci/scil/sati_lun_reset.c optional isci dev/isci/scil/sati_mode_pages.c optional isci dev/isci/scil/sati_mode_select.c optional isci dev/isci/scil/sati_mode_sense.c optional isci dev/isci/scil/sati_mode_sense_10.c optional isci dev/isci/scil/sati_mode_sense_6.c optional isci dev/isci/scil/sati_move.c optional isci dev/isci/scil/sati_passthrough.c optional isci dev/isci/scil/sati_read.c optional isci dev/isci/scil/sati_read_buffer.c optional isci dev/isci/scil/sati_read_capacity.c optional isci dev/isci/scil/sati_reassign_blocks.c optional isci dev/isci/scil/sati_report_luns.c optional isci dev/isci/scil/sati_request_sense.c optional isci dev/isci/scil/sati_start_stop_unit.c optional isci dev/isci/scil/sati_synchronize_cache.c optional isci dev/isci/scil/sati_test_unit_ready.c optional isci dev/isci/scil/sati_unmap.c optional isci dev/isci/scil/sati_util.c optional isci dev/isci/scil/sati_verify.c optional isci dev/isci/scil/sati_write.c optional isci dev/isci/scil/sati_write_and_verify.c optional isci dev/isci/scil/sati_write_buffer.c optional isci dev/isci/scil/sati_write_long.c optional isci dev/isci/scil/sci_abstract_list.c optional isci dev/isci/scil/sci_base_controller.c optional isci dev/isci/scil/sci_base_domain.c optional isci dev/isci/scil/sci_base_iterator.c optional isci dev/isci/scil/sci_base_library.c optional isci dev/isci/scil/sci_base_logger.c optional isci dev/isci/scil/sci_base_memory_descriptor_list.c optional isci dev/isci/scil/sci_base_memory_descriptor_list_decorator.c optional isci dev/isci/scil/sci_base_object.c optional isci dev/isci/scil/sci_base_observer.c optional isci dev/isci/scil/sci_base_phy.c optional isci dev/isci/scil/sci_base_port.c optional isci dev/isci/scil/sci_base_remote_device.c optional isci dev/isci/scil/sci_base_request.c optional isci dev/isci/scil/sci_base_state_machine.c optional isci dev/isci/scil/sci_base_state_machine_logger.c optional isci dev/isci/scil/sci_base_state_machine_observer.c optional isci dev/isci/scil/sci_base_subject.c optional isci dev/isci/scil/sci_util.c optional isci dev/isci/scil/scic_sds_controller.c optional isci dev/isci/scil/scic_sds_library.c optional isci dev/isci/scil/scic_sds_pci.c optional isci dev/isci/scil/scic_sds_phy.c optional isci dev/isci/scil/scic_sds_port.c optional isci dev/isci/scil/scic_sds_port_configuration_agent.c optional isci dev/isci/scil/scic_sds_remote_device.c optional isci dev/isci/scil/scic_sds_remote_node_context.c optional isci dev/isci/scil/scic_sds_remote_node_table.c optional isci dev/isci/scil/scic_sds_request.c optional isci dev/isci/scil/scic_sds_sgpio.c optional isci dev/isci/scil/scic_sds_smp_remote_device.c optional isci dev/isci/scil/scic_sds_smp_request.c optional isci dev/isci/scil/scic_sds_ssp_request.c optional isci dev/isci/scil/scic_sds_stp_packet_request.c optional isci dev/isci/scil/scic_sds_stp_remote_device.c optional isci dev/isci/scil/scic_sds_stp_request.c optional isci dev/isci/scil/scic_sds_unsolicited_frame_control.c optional isci dev/isci/scil/scif_sas_controller.c optional isci dev/isci/scil/scif_sas_controller_state_handlers.c optional isci dev/isci/scil/scif_sas_controller_states.c optional isci dev/isci/scil/scif_sas_domain.c optional isci dev/isci/scil/scif_sas_domain_state_handlers.c optional isci dev/isci/scil/scif_sas_domain_states.c optional isci dev/isci/scil/scif_sas_high_priority_request_queue.c optional isci dev/isci/scil/scif_sas_internal_io_request.c optional isci dev/isci/scil/scif_sas_io_request.c optional isci dev/isci/scil/scif_sas_io_request_state_handlers.c optional isci dev/isci/scil/scif_sas_io_request_states.c optional isci dev/isci/scil/scif_sas_library.c optional isci dev/isci/scil/scif_sas_remote_device.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substates.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substates.c optional isci dev/isci/scil/scif_sas_remote_device_state_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_states.c optional isci dev/isci/scil/scif_sas_request.c optional isci dev/isci/scil/scif_sas_smp_activity_clear_affiliation.c optional isci dev/isci/scil/scif_sas_smp_io_request.c optional isci dev/isci/scil/scif_sas_smp_phy.c optional isci dev/isci/scil/scif_sas_smp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_io_request.c optional isci dev/isci/scil/scif_sas_stp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_task_request.c optional isci dev/isci/scil/scif_sas_task_request.c optional isci dev/isci/scil/scif_sas_task_request_state_handlers.c optional isci dev/isci/scil/scif_sas_task_request_states.c optional isci dev/isci/scil/scif_sas_timer.c optional isci i386/acpica/acpi_machdep.c optional acpi acpi_wakecode.o optional acpi \ dependency "$S/i386/acpica/acpi_wakecode.S assym.inc" \ compile-with "${NORMAL_S}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.o" acpi_wakecode.bin optional acpi \ dependency "acpi_wakecode.o" \ compile-with "${OBJCOPY} -S -O binary acpi_wakecode.o ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.bin" acpi_wakecode.h optional acpi \ dependency "acpi_wakecode.bin" \ compile-with "file2c -sx 'static char wakecode[] = {' '};' < acpi_wakecode.bin > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.h" acpi_wakedata.h optional acpi \ dependency "acpi_wakecode.o" \ compile-with '${NM} -n --defined-only acpi_wakecode.o | while read offset dummy what; do echo "#define $${what} 0x$${offset}"; done > ${.TARGET}' \ no-obj no-implicit-rule before-depend \ clean "acpi_wakedata.h" # i386/bios/apm.c optional apm i386/bios/smapi.c optional smapi i386/bios/smapi_bios.S optional smapi i386/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 #i386/i386/apic_vector.s optional apic i386/i386/atomic.c standard \ compile-with "${CC} -c ${CFLAGS} ${DEFINED_PROF:S/^$/-fomit-frame-pointer/} ${.IMPSRC}" i386/i386/bios.c standard i386/i386/bioscall.s standard i386/i386/bpf_jit_machdep.c optional bpf_jitter i386/i386/copyout.c standard i386/i386/db_disasm.c optional ddb i386/i386/db_interface.c optional ddb i386/i386/db_trace.c optional ddb i386/i386/elan-mmcr.c optional cpu_elan | cpu_soekris i386/i386/elf_machdep.c standard i386/i386/exception.s standard i386/i386/gdb_machdep.c optional gdb i386/i386/geode.c optional cpu_geode i386/i386/in_cksum.c optional inet | inet6 i386/i386/initcpu.c standard i386/i386/io.c optional io i386/i386/k6_mem.c optional mem i386/i386/locore.s standard no-obj i386/i386/longrun.c optional cpu_enable_longrun i386/i386/machdep.c standard i386/i386/mem.c optional mem i386/i386/minidump_machdep.c standard i386/i386/mp_clock.c optional smp i386/i386/mp_machdep.c optional smp i386/i386/mpboot.s optional smp i386/i386/npx.c standard i386/i386/perfmon.c optional perfmon i386/i386/pmap.c standard i386/i386/prof_machdep.c optional profiling-routine i386/i386/ptrace_machdep.c standard i386/i386/sigtramp.s standard i386/i386/support.s standard i386/i386/swtch.s standard i386/i386/sys_machdep.c standard i386/i386/trap.c standard i386/i386/uio_machdep.c standard i386/i386/vm86.c standard i386/i386/vm_machdep.c standard i386/ibcs2/ibcs2_errno.c optional ibcs2 i386/ibcs2/ibcs2_fcntl.c optional ibcs2 i386/ibcs2/ibcs2_ioctl.c optional ibcs2 i386/ibcs2/ibcs2_ipc.c optional ibcs2 i386/ibcs2/ibcs2_isc.c optional ibcs2 i386/ibcs2/ibcs2_isc_sysent.c optional ibcs2 i386/ibcs2/ibcs2_misc.c optional ibcs2 i386/ibcs2/ibcs2_msg.c optional ibcs2 i386/ibcs2/ibcs2_other.c optional ibcs2 i386/ibcs2/ibcs2_signal.c optional ibcs2 i386/ibcs2/ibcs2_socksys.c optional ibcs2 i386/ibcs2/ibcs2_stat.c optional ibcs2 i386/ibcs2/ibcs2_sysent.c optional ibcs2 i386/ibcs2/ibcs2_sysi86.c optional ibcs2 i386/ibcs2/ibcs2_sysvec.c optional ibcs2 i386/ibcs2/ibcs2_util.c optional ibcs2 i386/ibcs2/ibcs2_xenix.c optional ibcs2 i386/ibcs2/ibcs2_xenix_sysent.c optional ibcs2 i386/ibcs2/imgact_coff.c optional ibcs2 i386/linux/imgact_linux.c optional compat_linux i386/linux/linux_copyout.c optional compat_linux i386/linux/linux_dummy.c optional compat_linux i386/linux/linux_machdep.c optional compat_linux i386/linux/linux_ptrace.c optional compat_linux i386/linux/linux_sysent.c optional compat_linux i386/linux/linux_sysvec.c optional compat_linux i386/pci/pci_cfgreg.c optional pci i386/pci/pci_pir.c optional pci isa/syscons_isa.c optional sc isa/vga_isa.c optional vga kern/kern_clocksource.c standard kern/imgact_aout.c optional compat_aout kern/imgact_gzip.c optional gzip kern/subr_sfbuf.c standard libkern/divdi3.c standard libkern/ffsll.c standard libkern/flsll.c standard libkern/memset.c standard libkern/moddi3.c standard libkern/qdivrem.c standard libkern/ucmpdi2.c standard libkern/udivdi3.c standard libkern/umoddi3.c standard libkern/x86/crc32_sse42.c standard # # x86 real mode BIOS support, required by dpms/pci/vesa # compat/x86bios/x86bios.c optional x86bios | dpms | pci | vesa # # bvm console # dev/bvm/bvm_console.c optional bvmconsole dev/bvm/bvm_dbg.c optional bvmdebug # # x86 shared code between IA32 and AMD64 architectures # x86/acpica/OsdEnvironment.c optional acpi x86/acpica/acpi_apm.c optional acpi x86/acpica/acpi_wakeup.c optional acpi x86/acpica/madt.c optional acpi apic x86/acpica/srat.c optional acpi x86/bios/smbios.c optional smbios x86/bios/vpd.c optional vpd x86/cpufreq/est.c optional cpufreq x86/cpufreq/hwpstate.c optional cpufreq x86/cpufreq/p4tcc.c optional cpufreq x86/cpufreq/powernow.c optional cpufreq x86/cpufreq/smist.c optional cpufreq x86/iommu/busdma_dmar.c optional acpi acpi_dmar pci x86/iommu/intel_ctx.c optional acpi acpi_dmar pci x86/iommu/intel_drv.c optional acpi acpi_dmar pci x86/iommu/intel_fault.c optional acpi acpi_dmar pci x86/iommu/intel_gas.c optional acpi acpi_dmar pci x86/iommu/intel_idpgtbl.c optional acpi acpi_dmar pci x86/iommu/intel_intrmap.c optional acpi acpi_dmar pci x86/iommu/intel_qi.c optional acpi acpi_dmar pci x86/iommu/intel_quirks.c optional acpi acpi_dmar pci x86/iommu/intel_utils.c optional acpi acpi_dmar pci x86/isa/atpic.c optional atpic x86/isa/atrtc.c standard x86/isa/clock.c standard x86/isa/elcr.c optional atpic | apic x86/isa/isa.c optional isa x86/isa/isa_dma.c optional isa x86/isa/nmi.c standard x86/isa/orm.c optional isa x86/pci/pci_bus.c optional pci x86/pci/qpi.c optional pci x86/x86/autoconf.c standard x86/x86/bus_machdep.c standard x86/x86/busdma_bounce.c standard x86/x86/busdma_machdep.c standard x86/x86/cpu_machdep.c standard x86/x86/dump_machdep.c standard x86/x86/fdt_machdep.c optional fdt x86/x86/identcpu.c standard x86/x86/intr_machdep.c standard x86/x86/io_apic.c optional apic x86/x86/legacy.c standard x86/x86/local_apic.c optional apic x86/x86/mca.c standard x86/x86/x86_mem.c optional mem x86/x86/mptable.c optional apic x86/x86/mptable_pci.c optional apic pci x86/x86/mp_x86.c optional smp x86/x86/mp_watchdog.c optional mp_watchdog smp x86/x86/msi.c optional apic pci x86/x86/nexus.c standard x86/x86/stack_machdep.c optional ddb | stack x86/x86/tsc.c standard x86/x86/pvclock.c standard x86/x86/delay.c standard x86/xen/hvm.c optional xenhvm x86/xen/xen_intr.c optional xenhvm x86/xen/xen_apic.c optional xenhvm x86/xen/xenpv.c optional xenhvm x86/xen/xen_nexus.c optional xenhvm x86/xen/xen_msi.c optional xenhvm diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c index ff7d7a3ffae9..cf2e17955a15 100644 --- a/sys/dev/hwpmc/hwpmc_core.c +++ b/sys/dev/hwpmc/hwpmc_core.c @@ -1,1323 +1,1322 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2008 Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Intel Core PMCs. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #if (__FreeBSD_version >= 1100000) #include #else #include #endif #include #include #include #include #define CORE_CPUID_REQUEST 0xA #define CORE_CPUID_REQUEST_SIZE 0x4 #define CORE_CPUID_EAX 0x0 #define CORE_CPUID_EBX 0x1 #define CORE_CPUID_ECX 0x2 #define CORE_CPUID_EDX 0x3 #define IAF_PMC_CAPS \ (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ PMC_CAP_USER | PMC_CAP_SYSTEM) #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) #define EV_IS_NOTARCH 0 #define EV_IS_ARCH_SUPP 1 #define EV_IS_ARCH_NOTSUPP -1 /* * "Architectural" events defined by Intel. The values of these * symbols correspond to positions in the bitmask returned by * the CPUID.0AH instruction. */ enum core_arch_events { CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, CORE_AE_BRANCH_MISSES_RETIRED = 6, CORE_AE_INSTRUCTION_RETIRED = 1, CORE_AE_LLC_MISSES = 4, CORE_AE_LLC_REFERENCE = 3, CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, CORE_AE_UNHALTED_CORE_CYCLES = 0 }; static enum pmc_cputype core_cputype; struct core_cpu { volatile uint32_t pc_resync; volatile uint32_t pc_iafctrl; /* Fixed function control. */ volatile uint64_t pc_globalctrl; /* Global control register. */ struct pmc_hw pc_corepmcs[]; }; static struct core_cpu **core_pcpu; static uint32_t core_architectural_events; static uint64_t core_pmcmask; static int core_iaf_ri; /* relative index of fixed counters */ static int core_iaf_width; static int core_iaf_npmc; static int core_iap_width; static int core_iap_npmc; static int core_iap_wroffset; static int core_pcpu_noop(struct pmc_mdep *md, int cpu) { (void) md; (void) cpu; return (0); } static int core_pcpu_init(struct pmc_mdep *md, int cpu) { struct pmc_cpu *pc; struct core_cpu *cc; struct pmc_hw *phw; int core_ri, n, npmc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu); core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; if (core_cputype != PMC_CPU_INTEL_CORE) npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), M_PMC, M_WAITOK | M_ZERO); core_pcpu[cpu] = cc; pc = pmc_pcpu[cpu]; KASSERT(pc != NULL && cc != NULL, ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n + core_ri); phw->phw_pmc = NULL; pc->pc_hwpmcs[n + core_ri] = phw; } return (0); } static int core_pcpu_fini(struct pmc_mdep *md, int cpu) { int core_ri, n, npmc; struct pmc_cpu *pc; struct core_cpu *cc; uint64_t msr = 0; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); if ((cc = core_pcpu[cpu]) == NULL) return (0); core_pcpu[cpu] = NULL; pc = pmc_pcpu[cpu]; KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, cpu)); npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; for (n = 0; n < npmc; n++) { msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; wrmsr(IAP_EVSEL0 + n, msr); } if (core_cputype != PMC_CPU_INTEL_CORE) { msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr); npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; } for (n = 0; n < npmc; n++) pc->pc_hwpmcs[n + core_ri] = NULL; free(cc, M_PMC); return (0); } /* * Fixed function counters. */ static pmc_value_t iaf_perfctr_value_to_reload_count(pmc_value_t v) { /* If the PMC has overflowed, return a reload count of zero. */ if ((v & (1ULL << (core_iaf_width - 1))) == 0) return (0); v &= (1ULL << core_iaf_width) - 1; return (1ULL << core_iaf_width) - v; } static pmc_value_t iaf_reload_count_to_perfctr_value(pmc_value_t rlc) { return (1ULL << core_iaf_width) - rlc; } static int iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, const struct pmc_op_pmcallocate *a) { enum pmc_event ev; uint32_t caps, flags, validflags; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); if (ri < 0 || ri > core_iaf_npmc) return (EINVAL); caps = a->pm_caps; if (a->pm_class != PMC_CLASS_IAF || (caps & IAF_PMC_CAPS) != caps) return (EINVAL); ev = pm->pm_event; - if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) - return (EINVAL); + if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) return (EINVAL); if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) return (EINVAL); if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) return (EINVAL); flags = a->pm_md.pm_iaf.pm_iaf_flags; validflags = IAF_MASK; if (caps & PMC_CAP_INTERRUPT) flags |= IAF_PMI; if (caps & PMC_CAP_SYSTEM) flags |= IAF_OS; if (caps & PMC_CAP_USER) flags |= IAF_USR; if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) flags |= (IAF_OS | IAF_USR); pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx", (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); return (0); } static int iaf_config_pmc(int cpu, int ri, struct pmc *pm) { KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, cpu)); core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; return (0); } static int iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) { int error; struct pmc_hw *phw; char iaf_name[PMC_NAME_MAX]; phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, NULL)) != 0) return (error); pi->pm_class = PMC_CLASS_IAF; if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { pi->pm_enabled = TRUE; *ppmc = phw->phw_pmc; } else { pi->pm_enabled = FALSE; *ppmc = NULL; } return (0); } static int iaf_get_config(int cpu, int ri, struct pmc **ppm) { *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; return (0); } static int iaf_get_msr(int ri, uint32_t *msr) { KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[iaf,%d] ri %d out of range", __LINE__, ri)); *msr = IAF_RI_TO_MSR(ri); return (0); } static int iaf_read_pmc(int cpu, int ri, pmc_value_t *v) { struct pmc *pm; pmc_value_t tmp; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, ri, ri + core_iaf_ri)); tmp = rdpmc(IAF_RI_TO_MSR(ri)); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) *v = iaf_perfctr_value_to_reload_count(tmp); else *v = tmp & ((1ULL << core_iaf_width) - 1); PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, IAF_RI_TO_MSR(ri), *v); return (0); } static int iaf_release_pmc(int cpu, int ri, struct pmc *pmc) { PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); return (0); } static int iaf_start_pmc(int cpu, int ri) { struct pmc *pm; struct core_cpu *iafc; uint64_t msr = 0; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); iafc = core_pcpu[cpu]; pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); do { iafc->pc_resync = 0; iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & IAF_GLOBAL_CTRL_MASK)); } while (iafc->pc_resync != 0); PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); return (0); } static int iaf_stop_pmc(int cpu, int ri) { uint32_t fc; struct core_cpu *iafc; uint64_t msr = 0; PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); iafc = core_pcpu[cpu]; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); fc = (IAF_MASK << (ri * 4)); iafc->pc_iafctrl &= ~fc; PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); do { iafc->pc_resync = 0; iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & IAF_GLOBAL_CTRL_MASK)); } while (iafc->pc_resync != 0); PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); return (0); } static int iaf_write_pmc(int cpu, int ri, pmc_value_t v) { struct core_cpu *cc; struct pmc *pm; uint64_t msr; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) v = iaf_reload_count_to_perfctr_value(v); /* Turn off fixed counters */ msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr); wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); /* Turn on fixed counters */ msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, (uintmax_t) rdmsr(IAF_CTRL), (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); return (0); } static void iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) { struct pmc_classdep *pcd; KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); PMCDBG0(MDP,INI,1, "iaf-initialize"); pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; pcd->pcd_caps = IAF_PMC_CAPS; pcd->pcd_class = PMC_CLASS_IAF; pcd->pcd_num = npmc; pcd->pcd_ri = md->pmd_npmc; pcd->pcd_width = pmcwidth; pcd->pcd_allocate_pmc = iaf_allocate_pmc; pcd->pcd_config_pmc = iaf_config_pmc; pcd->pcd_describe = iaf_describe; pcd->pcd_get_config = iaf_get_config; pcd->pcd_get_msr = iaf_get_msr; pcd->pcd_pcpu_fini = core_pcpu_noop; pcd->pcd_pcpu_init = core_pcpu_noop; pcd->pcd_read_pmc = iaf_read_pmc; pcd->pcd_release_pmc = iaf_release_pmc; pcd->pcd_start_pmc = iaf_start_pmc; pcd->pcd_stop_pmc = iaf_stop_pmc; pcd->pcd_write_pmc = iaf_write_pmc; md->pmd_npmc += npmc; } /* * Intel programmable PMCs. */ /* Sub fields of UMASK that this event supports. */ #define IAP_M_CORE (1 << 0) /* Core specificity */ #define IAP_M_AGENT (1 << 1) /* Agent specificity */ #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ #define IAP_M_MESI (1 << 3) /* MESI */ #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ #define IAP_M_TRANSITION (1 << 6) /* Transition */ #define IAP_F_CORE (0x3 << 14) /* Core specificity */ #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ #define IAP_F_MESI (0xF << 8) /* MESI */ #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ #define IAP_PREFETCH_RESERVED (0x2 << 12) #define IAP_CORE_THIS (0x1 << 14) #define IAP_CORE_ALL (0x3 << 14) #define IAP_F_CMASK 0xFF000000 static pmc_value_t iap_perfctr_value_to_reload_count(pmc_value_t v) { /* If the PMC has overflowed, return a reload count of zero. */ if ((v & (1ULL << (core_iap_width - 1))) == 0) return (0); v &= (1ULL << core_iap_width) - 1; return (1ULL << core_iap_width) - v; } static pmc_value_t iap_reload_count_to_perfctr_value(pmc_value_t rlc) { return (1ULL << core_iap_width) - rlc; } static int iap_pmc_has_overflowed(int ri) { uint64_t v; /* * We treat a Core (i.e., Intel architecture v1) PMC as has * having overflowed if its MSB is zero. */ v = rdpmc(ri); return ((v & (1ULL << (core_iap_width - 1))) == 0); } static int iap_event_corei7_ok_on_counter(uint8_t evsel, int ri) { uint32_t mask; switch (evsel) { /* * Events valid only on counter 0, 1. */ case 0x40: case 0x41: case 0x42: case 0x43: case 0x51: case 0x63: mask = 0x3; break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_event_westmere_ok_on_counter(uint8_t evsel, int ri) { uint32_t mask; switch (evsel) { /* * Events valid only on counter 0. */ case 0x60: case 0xB3: mask = 0x1; break; /* * Events valid only on counter 0, 1. */ case 0x4C: case 0x4E: case 0x51: case 0x63: mask = 0x3; break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_event_sb_sbx_ib_ibx_ok_on_counter(uint8_t evsel, int ri) { uint32_t mask; switch (evsel) { /* Events valid only on counter 0. */ case 0xB7: mask = 0x1; break; /* Events valid only on counter 1. */ case 0xC0: mask = 0x2; break; /* Events valid only on counter 2. */ case 0x48: case 0xA2: case 0xA3: mask = 0x4; break; /* Events valid only on counter 3. */ case 0xBB: case 0xCD: mask = 0x8; break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_event_ok_on_counter(uint8_t evsel, int ri) { uint32_t mask; switch (evsel) { /* * Events valid only on counter 0. */ case 0x10: case 0x14: case 0x18: case 0xB3: case 0xC1: case 0xCB: mask = (1 << 0); break; /* * Events valid only on counter 1. */ case 0x11: case 0x12: case 0x13: mask = (1 << 1); break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_allocate_pmc(int cpu, int ri, struct pmc *pm, const struct pmc_op_pmcallocate *a) { enum pmc_event map; uint8_t ev; uint32_t caps; const struct pmc_md_iap_op_pmcallocate *iap; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index value %d", __LINE__, ri)); /* check requested capabilities */ caps = a->pm_caps; if ((IAP_PMC_CAPS & caps) != caps) return (EPERM); map = 0; /* XXX: silent GCC warning */ iap = &a->pm_md.pm_iap; ev = IAP_EVSEL_GET(iap->pm_iap_config); switch (core_cputype) { case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_NEHALEM_EX: if (iap_event_corei7_ok_on_counter(ev, ri) == 0) return (EINVAL); break; case PMC_CPU_INTEL_SKYLAKE: case PMC_CPU_INTEL_SKYLAKE_XEON: case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_BROADWELL_XEON: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_IVYBRIDGE_XEON: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL_XEON: if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) return (EINVAL); break; case PMC_CPU_INTEL_WESTMERE: case PMC_CPU_INTEL_WESTMERE_EX: if (iap_event_westmere_ok_on_counter(ev, ri) == 0) return (EINVAL); break; default: if (iap_event_ok_on_counter(ev, ri) == 0) return (EINVAL); } pm->pm_md.pm_iap.pm_iap_evsel = iap->pm_iap_config; return (0); } static int iap_config_pmc(int cpu, int ri, struct pmc *pm) { KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, cpu)); core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; return (0); } static int iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) { int error; struct pmc_hw *phw; char iap_name[PMC_NAME_MAX]; phw = &core_pcpu[cpu]->pc_corepmcs[ri]; (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, NULL)) != 0) return (error); pi->pm_class = PMC_CLASS_IAP; if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { pi->pm_enabled = TRUE; *ppmc = phw->phw_pmc; } else { pi->pm_enabled = FALSE; *ppmc = NULL; } return (0); } static int iap_get_config(int cpu, int ri, struct pmc **ppm) { *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; return (0); } static int iap_get_msr(int ri, uint32_t *msr) { KASSERT(ri >= 0 && ri < core_iap_npmc, ("[iap,%d] ri %d out of range", __LINE__, ri)); *msr = ri; return (0); } static int iap_read_pmc(int cpu, int ri, pmc_value_t *v) { struct pmc *pm; pmc_value_t tmp; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); tmp = rdpmc(ri); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) *v = iap_perfctr_value_to_reload_count(tmp); else *v = tmp & ((1ULL << core_iap_width) - 1); PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, IAP_PMC0 + ri, *v); return (0); } static int iap_release_pmc(int cpu, int ri, struct pmc *pm) { (void) pm; PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); return (0); } static int iap_start_pmc(int cpu, int ri) { struct pmc *pm; uint32_t evsel; struct core_cpu *cc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] starting cpu%d,ri%d with no pmc configured", __LINE__, cpu, ri)); PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); evsel = pm->pm_md.pm_iap.pm_iap_evsel; PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", cpu, ri, IAP_EVSEL0 + ri, evsel); /* Event specific configuration. */ switch (IAP_EVSEL_GET(evsel)) { case 0xB7: wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); break; case 0xBB: wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); break; default: break; } wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); if (core_cputype == PMC_CPU_INTEL_CORE) return (0); do { cc->pc_resync = 0; cc->pc_globalctrl |= (1ULL << ri); wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); } while (cc->pc_resync != 0); return (0); } static int iap_stop_pmc(int cpu, int ri) { struct pmc *pm; struct core_cpu *cc; uint64_t msr; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, cpu, ri)); PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ if (core_cputype == PMC_CPU_INTEL_CORE) return (0); msr = 0; do { cc->pc_resync = 0; cc->pc_globalctrl &= ~(1ULL << ri); msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); } while (cc->pc_resync != 0); return (0); } static int iap_write_pmc(int cpu, int ri, pmc_value_t v) { struct pmc *pm; struct core_cpu *cc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, cpu, ri)); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) v = iap_reload_count_to_perfctr_value(v); v &= (1ULL << core_iap_width) - 1; PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, IAP_PMC0 + ri, v); /* * Write the new value to the counter (or it's alias). The * counter will be in a stopped state when the pcd_write() * entry point is called. */ wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); return (0); } static void iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, int flags) { struct pmc_classdep *pcd; KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); PMCDBG0(MDP,INI,1, "iap-initialize"); /* Remember the set of architectural events supported. */ core_architectural_events = ~flags; pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; pcd->pcd_caps = IAP_PMC_CAPS; pcd->pcd_class = PMC_CLASS_IAP; pcd->pcd_num = npmc; pcd->pcd_ri = md->pmd_npmc; pcd->pcd_width = pmcwidth; pcd->pcd_allocate_pmc = iap_allocate_pmc; pcd->pcd_config_pmc = iap_config_pmc; pcd->pcd_describe = iap_describe; pcd->pcd_get_config = iap_get_config; pcd->pcd_get_msr = iap_get_msr; pcd->pcd_pcpu_fini = core_pcpu_fini; pcd->pcd_pcpu_init = core_pcpu_init; pcd->pcd_read_pmc = iap_read_pmc; pcd->pcd_release_pmc = iap_release_pmc; pcd->pcd_start_pmc = iap_start_pmc; pcd->pcd_stop_pmc = iap_stop_pmc; pcd->pcd_write_pmc = iap_write_pmc; md->pmd_npmc += npmc; } static int core_intr(int cpu, struct trapframe *tf) { pmc_value_t v; struct pmc *pm; struct core_cpu *cc; int error, found_interrupt, ri; uint64_t msr; PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, TRAPF_USERMODE(tf)); found_interrupt = 0; cc = core_pcpu[cpu]; for (ri = 0; ri < core_iap_npmc; ri++) { if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) continue; if (!iap_pmc_has_overflowed(ri)) continue; found_interrupt = 1; if (pm->pm_state != PMC_STATE_RUNNING) continue; error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, TRAPF_USERMODE(tf)); v = pm->pm_sc.pm_reloadcount; v = iap_reload_count_to_perfctr_value(v); /* * Stop the counter, reload it but only restart it if * the PMC is not stalled. */ msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; wrmsr(IAP_EVSEL0 + ri, msr); wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); if (error) continue; wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | IAP_EN)); } if (found_interrupt) lapic_reenable_pmc(); if (found_interrupt) counter_u64_add(pmc_stats.pm_intr_processed, 1); else counter_u64_add(pmc_stats.pm_intr_ignored, 1); return (found_interrupt); } static int core2_intr(int cpu, struct trapframe *tf) { int error, found_interrupt, n; uint64_t flag, intrstatus, intrenable, msr; struct pmc *pm; struct core_cpu *cc; pmc_value_t v; PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, TRAPF_USERMODE(tf)); /* * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which * PMCs have a pending PMI interrupt. We take a 'snapshot' of * the current set of interrupting PMCs and process these * after stopping them. */ intrstatus = rdmsr(IA_GLOBAL_STATUS); intrenable = intrstatus & core_pmcmask; PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, (uintmax_t) intrstatus); found_interrupt = 0; cc = core_pcpu[cpu]; KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); cc->pc_globalctrl &= ~intrenable; cc->pc_resync = 1; /* MSRs now potentially out of sync. */ /* * Stop PMCs and clear overflow status bits. */ msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, msr); wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | IA_GLOBAL_STATUS_FLAG_OVFBUF | IA_GLOBAL_STATUS_FLAG_CONDCHG); /* * Look for interrupts from fixed function PMCs. */ for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; n++, flag <<= 1) { if ((intrstatus & flag) == 0) continue; found_interrupt = 1; pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) continue; error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, TRAPF_USERMODE(tf)); if (error) intrenable &= ~flag; v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); /* Reload sampling count. */ wrmsr(IAF_CTR0 + n, v); PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); } /* * Process interrupts from the programmable counters. */ for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { if ((intrstatus & flag) == 0) continue; found_interrupt = 1; pm = cc->pc_corepmcs[n].phw_pmc; if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) continue; error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, TRAPF_USERMODE(tf)); if (error) intrenable &= ~flag; v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, (uintmax_t) v); /* Reload sampling count. */ wrmsr(core_iap_wroffset + IAP_PMC0 + n, v); } /* * Reenable all non-stalled PMCs. */ PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, (uintmax_t) intrenable); cc->pc_globalctrl |= intrenable; wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), (uintmax_t) rdmsr(IA_GLOBAL_CTRL), (uintmax_t) rdmsr(IA_GLOBAL_STATUS), (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); if (found_interrupt) lapic_reenable_pmc(); if (found_interrupt) counter_u64_add(pmc_stats.pm_intr_processed, 1); else counter_u64_add(pmc_stats.pm_intr_ignored, 1); return (found_interrupt); } int pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) { int cpuid[CORE_CPUID_REQUEST_SIZE]; int ipa_version, flags, nflags; do_cpuid(CORE_CPUID_REQUEST, cpuid); ipa_version = (version_override > 0) ? version_override : cpuid[CORE_CPUID_EAX] & 0xFF; core_cputype = md->pmd_cputype; PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", core_cputype, maxcpu, ipa_version); if (ipa_version < 1 || ipa_version > 4 || (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { /* Unknown PMC architecture. */ printf("hwpc_core: unknown PMC architecture: %d\n", ipa_version); return (EPROGMISMATCH); } core_iap_wroffset = 0; if (cpu_feature2 & CPUID2_PDCM) { if (rdmsr(IA32_PERF_CAPABILITIES) & PERFCAP_FW_WRITE) { PMCDBG0(MDP, INI, 1, "core-init full-width write supported"); core_iap_wroffset = IAP_A_PMC0 - IAP_PMC0; } else PMCDBG0(MDP, INI, 1, "core-init full-width write NOT supported"); } else PMCDBG0(MDP, INI, 1, "core-init pdcm not supported"); core_pmcmask = 0; /* * Initialize programmable counters. */ core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; core_pmcmask |= ((1ULL << core_iap_npmc) - 1); nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); /* * Initialize fixed function counters, if present. */ if (core_cputype != PMC_CPU_INTEL_CORE) { core_iaf_ri = core_iap_npmc; core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; } PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, core_iaf_ri); core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, M_ZERO | M_WAITOK); /* * Choose the appropriate interrupt handler. */ if (ipa_version == 1) md->pmd_intr = core_intr; else md->pmd_intr = core2_intr; md->pmd_pcpu_fini = NULL; md->pmd_pcpu_init = NULL; return (0); } void pmc_core_finalize(struct pmc_mdep *md) { PMCDBG0(MDP,INI,1, "core-finalize"); free(core_pcpu, M_PMC); core_pcpu = NULL; } diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c index 5b289f5210b4..d54c8761bec5 100644 --- a/sys/dev/hwpmc/hwpmc_intel.c +++ b/sys/dev/hwpmc/hwpmc_intel.c @@ -1,410 +1,329 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2008 Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Common code for handling Intel CPUs. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include static int intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) { (void) pc; PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); /* allow the RDPMC instruction if needed */ if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) load_cr4(rcr4() | CR4_PCE); PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); return 0; } static int intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) { (void) pc; (void) pp; /* can be NULL */ PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, (uintmax_t) rcr4()); /* always turn off the RDPMC instruction */ load_cr4(rcr4() & ~CR4_PCE); return 0; } struct pmc_mdep * pmc_intel_initialize(void) { struct pmc_mdep *pmc_mdep; enum pmc_cputype cputype; int error, model, nclasses, ncpus, stepping, verov; KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, ("[intel,%d] Initializing non-intel processor", __LINE__)); PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); cputype = -1; nclasses = 2; error = 0; verov = 0; model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); stepping = cpu_id & 0xF; snprintf(pmc_cpuid, sizeof(pmc_cpuid), "GenuineIntel-%d-%02X", (cpu_id & 0xF00) >> 8, model); switch (cpu_id & 0xF00) { -#if defined(__i386__) - case 0x500: /* Pentium family processors */ - cputype = PMC_CPU_INTEL_P5; - break; -#endif case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ switch (model) { -#if defined(__i386__) - case 0x1: - cputype = PMC_CPU_INTEL_P6; - break; - case 0x3: case 0x5: - cputype = PMC_CPU_INTEL_PII; - break; - case 0x6: case 0x16: - cputype = PMC_CPU_INTEL_CL; - break; - case 0x7: case 0x8: case 0xA: case 0xB: - cputype = PMC_CPU_INTEL_PIII; - break; - case 0x9: case 0xD: - cputype = PMC_CPU_INTEL_PM; - break; -#endif case 0xE: cputype = PMC_CPU_INTEL_CORE; break; case 0xF: /* Per Intel document 315338-020. */ if (stepping == 0x7) { cputype = PMC_CPU_INTEL_CORE; verov = 1; } else { cputype = PMC_CPU_INTEL_CORE2; nclasses = 3; } break; case 0x17: cputype = PMC_CPU_INTEL_CORE2EXTREME; nclasses = 3; break; case 0x1C: /* Per Intel document 320047-002. */ cputype = PMC_CPU_INTEL_ATOM; nclasses = 3; break; case 0x1A: case 0x1E: /* * Per Intel document 253669-032 9/2009, * pages A-2 and A-57 */ case 0x1F: /* * Per Intel document 253669-032 9/2009, * pages A-2 and A-57 */ cputype = PMC_CPU_INTEL_COREI7; nclasses = 5; break; case 0x2E: cputype = PMC_CPU_INTEL_NEHALEM_EX; nclasses = 3; break; case 0x25: /* Per Intel document 253669-033US 12/2009. */ case 0x2C: /* Per Intel document 253669-033US 12/2009. */ cputype = PMC_CPU_INTEL_WESTMERE; nclasses = 5; break; case 0x2F: /* Westmere-EX, seen in wild */ cputype = PMC_CPU_INTEL_WESTMERE_EX; nclasses = 3; break; case 0x2A: /* Per Intel document 253669-039US 05/2011. */ cputype = PMC_CPU_INTEL_SANDYBRIDGE; nclasses = 5; break; case 0x2D: /* Per Intel document 253669-044US 08/2012. */ cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON; nclasses = 3; break; case 0x3A: /* Per Intel document 253669-043US 05/2012. */ cputype = PMC_CPU_INTEL_IVYBRIDGE; nclasses = 3; break; case 0x3E: /* Per Intel document 325462-045US 01/2013. */ cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; nclasses = 3; break; /* Skylake */ case 0x4e: case 0x5e: /* Kabylake */ case 0x8E: /* Per Intel document 325462-063US July 2017. */ case 0x9E: /* Per Intel document 325462-063US July 2017. */ cputype = PMC_CPU_INTEL_SKYLAKE; nclasses = 3; break; case 0x55: /* SDM rev 63 */ cputype = PMC_CPU_INTEL_SKYLAKE_XEON; nclasses = 3; break; case 0x3D: case 0x47: cputype = PMC_CPU_INTEL_BROADWELL; nclasses = 3; break; case 0x4f: case 0x56: cputype = PMC_CPU_INTEL_BROADWELL_XEON; nclasses = 3; break; case 0x3F: /* Per Intel document 325462-045US 09/2014. */ case 0x46: /* Per Intel document 325462-045US 09/2014. */ /* Should 46 be XEON. probably its own? */ cputype = PMC_CPU_INTEL_HASWELL_XEON; nclasses = 3; break; case 0x3C: /* Per Intel document 325462-045US 01/2013. */ case 0x45: /* Per Intel document 325462-045US 09/2014. */ cputype = PMC_CPU_INTEL_HASWELL; nclasses = 5; break; case 0x4D: /* Per Intel document 330061-001 01/2014. */ cputype = PMC_CPU_INTEL_ATOM_SILVERMONT; nclasses = 3; break; } break; -#if defined(__i386__) || defined(__amd64__) - case 0xF00: /* P4 */ - if (model >= 0 && model <= 6) /* known models */ - cputype = PMC_CPU_INTEL_PIV; - break; } -#endif + if ((int) cputype == -1) { printf("pmc: Unknown Intel CPU.\n"); return (NULL); } /* Allocate base class and initialize machine dependent struct */ pmc_mdep = pmc_mdep_alloc(nclasses); pmc_mdep->pmd_cputype = cputype; pmc_mdep->pmd_switch_in = intel_switch_in; pmc_mdep->pmd_switch_out = intel_switch_out; ncpus = pmc_cpu_max(); error = pmc_tsc_initialize(pmc_mdep, ncpus); if (error) goto error; switch (cputype) { -#if defined(__i386__) || defined(__amd64__) /* * Intel Core, Core 2 and Atom processors. */ case PMC_CPU_INTEL_ATOM: case PMC_CPU_INTEL_ATOM_SILVERMONT: case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_BROADWELL_XEON: case PMC_CPU_INTEL_SKYLAKE_XEON: case PMC_CPU_INTEL_SKYLAKE: case PMC_CPU_INTEL_CORE: case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_NEHALEM_EX: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: case PMC_CPU_INTEL_WESTMERE_EX: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE_XEON: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL_XEON: error = pmc_core_initialize(pmc_mdep, ncpus, verov); break; - /* - * Intel Pentium 4 Processors, and P4/EMT64 processors. - */ - - case PMC_CPU_INTEL_PIV: - error = pmc_p4_initialize(pmc_mdep, ncpus); - break; -#endif - -#if defined(__i386__) - /* - * P6 Family Processors - */ - - case PMC_CPU_INTEL_P6: - case PMC_CPU_INTEL_CL: - case PMC_CPU_INTEL_PII: - case PMC_CPU_INTEL_PIII: - case PMC_CPU_INTEL_PM: - error = pmc_p6_initialize(pmc_mdep, ncpus); - break; - - /* - * Intel Pentium PMCs. - */ - - case PMC_CPU_INTEL_P5: - error = pmc_p5_initialize(pmc_mdep, ncpus); - break; -#endif - default: KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); } if (error) { pmc_tsc_finalize(pmc_mdep); goto error; } /* * Init the uncore class. */ -#if defined(__i386__) || defined(__amd64__) switch (cputype) { /* * Intel Corei7 and Westmere processors. */ case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: case PMC_CPU_INTEL_BROADWELL: error = pmc_uncore_initialize(pmc_mdep, ncpus); break; default: break; } -#endif error: if (error) { pmc_mdep_free(pmc_mdep); pmc_mdep = NULL; } return (pmc_mdep); } void pmc_intel_finalize(struct pmc_mdep *md) { pmc_tsc_finalize(md); switch (md->pmd_cputype) { -#if defined(__i386__) || defined(__amd64__) case PMC_CPU_INTEL_ATOM: case PMC_CPU_INTEL_ATOM_SILVERMONT: case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_BROADWELL_XEON: case PMC_CPU_INTEL_SKYLAKE_XEON: case PMC_CPU_INTEL_SKYLAKE: case PMC_CPU_INTEL_CORE: case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_NEHALEM_EX: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL_XEON: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: case PMC_CPU_INTEL_WESTMERE_EX: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE_XEON: pmc_core_finalize(md); break; - - case PMC_CPU_INTEL_PIV: - pmc_p4_finalize(md); - break; -#endif -#if defined(__i386__) - case PMC_CPU_INTEL_P6: - case PMC_CPU_INTEL_CL: - case PMC_CPU_INTEL_PII: - case PMC_CPU_INTEL_PIII: - case PMC_CPU_INTEL_PM: - pmc_p6_finalize(md); - break; - case PMC_CPU_INTEL_P5: - pmc_p5_finalize(md); - break; -#endif default: KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); } /* * Uncore. */ -#if defined(__i386__) || defined(__amd64__) switch (md->pmd_cputype) { case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: pmc_uncore_finalize(md); break; default: break; } -#endif } diff --git a/sys/dev/hwpmc/hwpmc_pentium.c b/sys/dev/hwpmc/hwpmc_pentium.c deleted file mode 100644 index 8da9d316718a..000000000000 --- a/sys/dev/hwpmc/hwpmc_pentium.c +++ /dev/null @@ -1,59 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003-2005 Joseph Koshy - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/* - * Intel Pentium PMCs - */ - -int -pmc_p5_initialize(struct pmc_mdep *pmc_mdep, int ncpus) -{ - (void) pmc_mdep; (void) ncpus; - return (ENOSYS); /* nothing here yet */ -} - -void -pmc_p5_finalize(struct pmc_mdep *pmc_mdep) -{ - (void) pmc_mdep; -} diff --git a/sys/dev/hwpmc/hwpmc_pentium.h b/sys/dev/hwpmc/hwpmc_pentium.h deleted file mode 100644 index c27c108a47a3..000000000000 --- a/sys/dev/hwpmc/hwpmc_pentium.h +++ /dev/null @@ -1,75 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2005, Joseph Koshy - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/* Machine dependent interfaces */ - -#ifndef _DEV_HWPMC_PENTIUM_H_ -#define _DEV_HWPMC_PENTIUM_H_ 1 - -/* Intel Pentium PMCs */ - -#define PENTIUM_NPMCS 2 -#define PENTIUM_CESR_PC1 (1 << 25) -#define PENTIUM_CESR_CC1_MASK 0x01C00000 -#define PENTIUM_CESR_TO_CC1(C) (((C) & 0x07) << 22) -#define PENTIUM_CESR_ES1_MASK 0x003F0000 -#define PENTIUM_CESR_TO_ES1(E) (((E) & 0x3F) << 16) -#define PENTIUM_CESR_PC0 (1 << 9) -#define PENTIUM_CESR_CC0_MASK 0x000001C0 -#define PENTIUM_CESR_TO_CC0(C) (((C) & 0x07) << 6) -#define PENTIUM_CESR_ES0_MASK 0x0000003F -#define PENTIUM_CESR_TO_ES0(E) ((E) & 0x3F) -#define PENTIUM_CESR_RESERVED 0xFC00FC00 - -#define PENTIUM_MSR_CESR 0x11 -#define PENTIUM_MSR_CTR0 0x12 -#define PENTIUM_MSR_CTR1 0x13 - -struct pmc_md_pentium_op_pmcallocate { - uint32_t pm_pentium_config; -}; - -#ifdef _KERNEL - -/* MD extension for 'struct pmc' */ -struct pmc_md_pentium_pmc { - uint32_t pm_pentium_cesr; -}; - - -/* - * Prototypes - */ - -int pmc_p5_initialize(struct pmc_mdep *_md, int _ncpus); -void pmc_p5_finalize(struct pmc_mdep *_md); - -#endif /* _KERNEL */ -#endif /* _DEV_HWPMC_PENTIUM_H_ */ diff --git a/sys/dev/hwpmc/hwpmc_piv.c b/sys/dev/hwpmc/hwpmc_piv.c deleted file mode 100644 index 9e4b7b5894a7..000000000000 --- a/sys/dev/hwpmc/hwpmc_piv.c +++ /dev/null @@ -1,1702 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003-2007 Joseph Koshy - * Copyright (c) 2007 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by A. Joseph Koshy under - * sponsorship from the FreeBSD Foundation and Google, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if (__FreeBSD_version >= 1100000) -#include -#else -#include -#endif -#include -#include -#include -#include -#include - -/* - * PENTIUM 4 SUPPORT - * - * The P4 has 18 PMCs, divided into 4 groups with 4,4,4 and 6 PMCs - * respectively. Each PMC comprises of two model specific registers: - * a counter configuration control register (CCCR) and a counter - * register that holds the actual event counts. - * - * Configuring an event requires the use of one of 45 event selection - * control registers (ESCR). Events are associated with specific - * ESCRs. Each PMC group has a set of ESCRs it can use. - * - * - The BPU counter group (4 PMCs) can use the 16 ESCRs: - * BPU_ESCR{0,1}, IS_ESCR{0,1}, MOB_ESCR{0,1}, ITLB_ESCR{0,1}, - * PMH_ESCR{0,1}, IX_ESCR{0,1}, FSB_ESCR{0,}, BSU_ESCR{0,1}. - * - * - The MS counter group (4 PMCs) can use the 6 ESCRs: MS_ESCR{0,1}, - * TC_ESCR{0,1}, TBPU_ESCR{0,1}. - * - * - The FLAME counter group (4 PMCs) can use the 10 ESCRs: - * FLAME_ESCR{0,1}, FIRM_ESCR{0,1}, SAAT_ESCR{0,1}, U2L_ESCR{0,1}, - * DAC_ESCR{0,1}. - * - * - The IQ counter group (6 PMCs) can use the 13 ESCRs: IQ_ESCR{0,1}, - * ALF_ESCR{0,1}, RAT_ESCR{0,1}, SSU_ESCR0, CRU_ESCR{0,1,2,3,4,5}. - * - * Even-numbered ESCRs can be used with counters 0, 1 and 4 (if - * present) of a counter group. Odd-numbers ESCRs can be used with - * counters 2, 3 and 5 (if present) of a counter group. The - * 'p4_escrs[]' table describes these restrictions in a form that - * function 'p4_allocate()' uses for making allocation decisions. - * - * SYSTEM-MODE AND THREAD-MODE ALLOCATION - * - * In addition to remembering the state of PMC rows - * ('FREE','STANDALONE', or 'THREAD'), we similar need to track the - * state of ESCR rows. If an ESCR is allocated to a system-mode PMC - * on a CPU we cannot allocate this to a thread-mode PMC. On a - * multi-cpu (multiple physical CPUs) system, ESCR allocation on each - * CPU is tracked by the pc_escrs[] array. - * - * Each system-mode PMC that is using an ESCR records its row-index in - * the appropriate entry and system-mode allocation attempts check - * that an ESCR is available using this array. Process-mode PMCs do - * not use the pc_escrs[] array, since ESCR row itself would have been - * marked as in 'THREAD' mode. - * - * HYPERTHREADING SUPPORT - * - * When HTT is enabled, the FreeBSD kernel treats the two 'logical' - * cpus as independent CPUs and can schedule kernel threads on them - * independently. However, the two logical CPUs share the same set of - * PMC resources. We need to ensure that: - * - PMCs that use the PMC_F_DESCENDANTS semantics are handled correctly, - * and, - * - Threads of multi-threaded processes that get scheduled on the same - * physical CPU are handled correctly. - * - * HTT Detection - * - * Not all HTT capable systems will have HTT enabled. We detect the - * presence of HTT by detecting if 'p4_init()' was called for a secondary - * CPU in a HTT pair. - * - * Note that hwpmc(4) cannot currently deal with a change in HTT status once - * loaded. - * - * Handling HTT READ / WRITE / START / STOP - * - * PMC resources are shared across the CPUs in an HTT pair. We - * designate the lower numbered CPU in a HTT pair as the 'primary' - * CPU. In each primary CPU's state we keep track of a 'runcount' - * which reflects the number of PMC-using processes that have been - * scheduled on its secondary CPU. Process-mode PMC operations will - * actually 'start' or 'stop' hardware only if these are the first or - * last processes respectively to use the hardware. PMC values - * written by a 'write' operation are saved and are transferred to - * hardware at PMC 'start' time if the runcount is 0. If the runcount - * is greater than 0 at the time of a 'start' operation, we keep track - * of the actual hardware value at the time of the 'start' operation - * and use this to adjust the final readings at PMC 'stop' or 'read' - * time. - * - * Execution sequences: - * - * Case 1: CPUx +...- (no overlap) - * CPUy +...- - * RC 0 1 0 1 0 - * - * Case 2: CPUx +........- (partial overlap) - * CPUy +........- - * RC 0 1 2 1 0 - * - * Case 3: CPUx +..............- (fully overlapped) - * CPUy +.....- - * RC 0 1 2 1 0 - * - * Key: - * 'CPU[xy]' : one of the two logical processors on a HTT CPU. - * 'RC' : run count (#threads per physical core). - * '+' : point in time when a thread is put on a CPU. - * '-' : point in time where a thread is taken off a CPU. - * - * Handling HTT CONFIG - * - * Different processes attached to the same PMC may get scheduled on - * the two logical processors in the package. We keep track of config - * and de-config operations using the CFGFLAGS fields of the per-physical - * cpu state. - */ - -#define P4_PMCS() \ - P4_PMC(BPU_COUNTER0) \ - P4_PMC(BPU_COUNTER1) \ - P4_PMC(BPU_COUNTER2) \ - P4_PMC(BPU_COUNTER3) \ - P4_PMC(MS_COUNTER0) \ - P4_PMC(MS_COUNTER1) \ - P4_PMC(MS_COUNTER2) \ - P4_PMC(MS_COUNTER3) \ - P4_PMC(FLAME_COUNTER0) \ - P4_PMC(FLAME_COUNTER1) \ - P4_PMC(FLAME_COUNTER2) \ - P4_PMC(FLAME_COUNTER3) \ - P4_PMC(IQ_COUNTER0) \ - P4_PMC(IQ_COUNTER1) \ - P4_PMC(IQ_COUNTER2) \ - P4_PMC(IQ_COUNTER3) \ - P4_PMC(IQ_COUNTER4) \ - P4_PMC(IQ_COUNTER5) \ - P4_PMC(NONE) - -enum pmc_p4pmc { -#undef P4_PMC -#define P4_PMC(N) P4_PMC_##N , - P4_PMCS() -}; - -/* - * P4 ESCR descriptors - */ - -#define P4_ESCRS() \ - P4_ESCR(BSU_ESCR0, 0x3A0, BPU_COUNTER0, BPU_COUNTER1, NONE) \ - P4_ESCR(BSU_ESCR1, 0x3A1, BPU_COUNTER2, BPU_COUNTER3, NONE) \ - P4_ESCR(FSB_ESCR0, 0x3A2, BPU_COUNTER0, BPU_COUNTER1, NONE) \ - P4_ESCR(FSB_ESCR1, 0x3A3, BPU_COUNTER2, BPU_COUNTER3, NONE) \ - P4_ESCR(FIRM_ESCR0, 0x3A4, FLAME_COUNTER0, FLAME_COUNTER1, NONE) \ - P4_ESCR(FIRM_ESCR1, 0x3A5, FLAME_COUNTER2, FLAME_COUNTER3, NONE) \ - P4_ESCR(FLAME_ESCR0, 0x3A6, FLAME_COUNTER0, FLAME_COUNTER1, NONE) \ - P4_ESCR(FLAME_ESCR1, 0x3A7, FLAME_COUNTER2, FLAME_COUNTER3, NONE) \ - P4_ESCR(DAC_ESCR0, 0x3A8, FLAME_COUNTER0, FLAME_COUNTER1, NONE) \ - P4_ESCR(DAC_ESCR1, 0x3A9, FLAME_COUNTER2, FLAME_COUNTER3, NONE) \ - P4_ESCR(MOB_ESCR0, 0x3AA, BPU_COUNTER0, BPU_COUNTER1, NONE) \ - P4_ESCR(MOB_ESCR1, 0x3AB, BPU_COUNTER2, BPU_COUNTER3, NONE) \ - P4_ESCR(PMH_ESCR0, 0x3AC, BPU_COUNTER0, BPU_COUNTER1, NONE) \ - P4_ESCR(PMH_ESCR1, 0x3AD, BPU_COUNTER2, BPU_COUNTER3, NONE) \ - P4_ESCR(SAAT_ESCR0, 0x3AE, FLAME_COUNTER0, FLAME_COUNTER1, NONE) \ - P4_ESCR(SAAT_ESCR1, 0x3AF, FLAME_COUNTER2, FLAME_COUNTER3, NONE) \ - P4_ESCR(U2L_ESCR0, 0x3B0, FLAME_COUNTER0, FLAME_COUNTER1, NONE) \ - P4_ESCR(U2L_ESCR1, 0x3B1, FLAME_COUNTER2, FLAME_COUNTER3, NONE) \ - P4_ESCR(BPU_ESCR0, 0x3B2, BPU_COUNTER0, BPU_COUNTER1, NONE) \ - P4_ESCR(BPU_ESCR1, 0x3B3, BPU_COUNTER2, BPU_COUNTER3, NONE) \ - P4_ESCR(IS_ESCR0, 0x3B4, BPU_COUNTER0, BPU_COUNTER1, NONE) \ - P4_ESCR(IS_ESCR1, 0x3B5, BPU_COUNTER2, BPU_COUNTER3, NONE) \ - P4_ESCR(ITLB_ESCR0, 0x3B6, BPU_COUNTER0, BPU_COUNTER1, NONE) \ - P4_ESCR(ITLB_ESCR1, 0x3B7, BPU_COUNTER2, BPU_COUNTER3, NONE) \ - P4_ESCR(CRU_ESCR0, 0x3B8, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4) \ - P4_ESCR(CRU_ESCR1, 0x3B9, IQ_COUNTER2, IQ_COUNTER3, IQ_COUNTER5) \ - P4_ESCR(IQ_ESCR0, 0x3BA, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4) \ - P4_ESCR(IQ_ESCR1, 0x3BB, IQ_COUNTER1, IQ_COUNTER3, IQ_COUNTER5) \ - P4_ESCR(RAT_ESCR0, 0x3BC, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4) \ - P4_ESCR(RAT_ESCR1, 0x3BD, IQ_COUNTER2, IQ_COUNTER3, IQ_COUNTER5) \ - P4_ESCR(SSU_ESCR0, 0x3BE, IQ_COUNTER0, IQ_COUNTER2, IQ_COUNTER4) \ - P4_ESCR(MS_ESCR0, 0x3C0, MS_COUNTER0, MS_COUNTER1, NONE) \ - P4_ESCR(MS_ESCR1, 0x3C1, MS_COUNTER2, MS_COUNTER3, NONE) \ - P4_ESCR(TBPU_ESCR0, 0x3C2, MS_COUNTER0, MS_COUNTER1, NONE) \ - P4_ESCR(TBPU_ESCR1, 0x3C3, MS_COUNTER2, MS_COUNTER3, NONE) \ - P4_ESCR(TC_ESCR0, 0x3C4, MS_COUNTER0, MS_COUNTER1, NONE) \ - P4_ESCR(TC_ESCR1, 0x3C5, MS_COUNTER2, MS_COUNTER3, NONE) \ - P4_ESCR(IX_ESCR0, 0x3C8, BPU_COUNTER0, BPU_COUNTER1, NONE) \ - P4_ESCR(IX_ESCR1, 0x3C9, BPU_COUNTER2, BPU_COUNTER3, NONE) \ - P4_ESCR(ALF_ESCR0, 0x3CA, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4) \ - P4_ESCR(ALF_ESCR1, 0x3CB, IQ_COUNTER2, IQ_COUNTER3, IQ_COUNTER5) \ - P4_ESCR(CRU_ESCR2, 0x3CC, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4) \ - P4_ESCR(CRU_ESCR3, 0x3CD, IQ_COUNTER2, IQ_COUNTER3, IQ_COUNTER5) \ - P4_ESCR(CRU_ESCR4, 0x3E0, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4) \ - P4_ESCR(CRU_ESCR5, 0x3E1, IQ_COUNTER2, IQ_COUNTER3, IQ_COUNTER5) \ - P4_ESCR(NONE, ~0, NONE, NONE, NONE) - -enum pmc_p4escr { -#define P4_ESCR(N, MSR, P1, P2, P3) P4_ESCR_##N , - P4_ESCRS() -#undef P4_ESCR -}; - -struct pmc_p4escr_descr { - const char pm_escrname[PMC_NAME_MAX]; - u_short pm_escr_msr; - const enum pmc_p4pmc pm_pmcs[P4_MAX_PMC_PER_ESCR]; -}; - -static struct pmc_p4escr_descr p4_escrs[] = -{ -#define P4_ESCR(N, MSR, P1, P2, P3) \ - { \ - .pm_escrname = #N, \ - .pm_escr_msr = (MSR), \ - .pm_pmcs = \ - { \ - P4_PMC_##P1, \ - P4_PMC_##P2, \ - P4_PMC_##P3 \ - } \ - } , - - P4_ESCRS() - -#undef P4_ESCR -}; - -/* - * P4 Event descriptor - */ - -struct p4_event_descr { - const enum pmc_event pm_event; - const uint32_t pm_escr_eventselect; - const uint32_t pm_cccr_select; - const char pm_is_ti_event; - enum pmc_p4escr pm_escrs[P4_MAX_ESCR_PER_EVENT]; -}; - -static struct p4_event_descr p4_events[] = { - -#define P4_EVDESCR(NAME, ESCREVENTSEL, CCCRSEL, TI_EVENT, ESCR0, ESCR1) \ - { \ - .pm_event = PMC_EV_P4_##NAME, \ - .pm_escr_eventselect = (ESCREVENTSEL), \ - .pm_cccr_select = (CCCRSEL), \ - .pm_is_ti_event = (TI_EVENT), \ - .pm_escrs = \ - { \ - P4_ESCR_##ESCR0, \ - P4_ESCR_##ESCR1 \ - } \ - } - -P4_EVDESCR(TC_DELIVER_MODE, 0x01, 0x01, TRUE, TC_ESCR0, TC_ESCR1), -P4_EVDESCR(BPU_FETCH_REQUEST, 0x03, 0x00, FALSE, BPU_ESCR0, BPU_ESCR1), -P4_EVDESCR(ITLB_REFERENCE, 0x18, 0x03, FALSE, ITLB_ESCR0, ITLB_ESCR1), -P4_EVDESCR(MEMORY_CANCEL, 0x02, 0x05, FALSE, DAC_ESCR0, DAC_ESCR1), -P4_EVDESCR(MEMORY_COMPLETE, 0x08, 0x02, FALSE, SAAT_ESCR0, SAAT_ESCR1), -P4_EVDESCR(LOAD_PORT_REPLAY, 0x04, 0x02, FALSE, SAAT_ESCR0, SAAT_ESCR1), -P4_EVDESCR(STORE_PORT_REPLAY, 0x05, 0x02, FALSE, SAAT_ESCR0, SAAT_ESCR1), -P4_EVDESCR(MOB_LOAD_REPLAY, 0x03, 0x02, FALSE, MOB_ESCR0, MOB_ESCR1), -P4_EVDESCR(PAGE_WALK_TYPE, 0x01, 0x04, TRUE, PMH_ESCR0, PMH_ESCR1), -P4_EVDESCR(BSQ_CACHE_REFERENCE, 0x0C, 0x07, FALSE, BSU_ESCR0, BSU_ESCR1), -P4_EVDESCR(IOQ_ALLOCATION, 0x03, 0x06, FALSE, FSB_ESCR0, FSB_ESCR1), -P4_EVDESCR(IOQ_ACTIVE_ENTRIES, 0x1A, 0x06, FALSE, FSB_ESCR1, NONE), -P4_EVDESCR(FSB_DATA_ACTIVITY, 0x17, 0x06, TRUE, FSB_ESCR0, FSB_ESCR1), -P4_EVDESCR(BSQ_ALLOCATION, 0x05, 0x07, FALSE, BSU_ESCR0, NONE), -P4_EVDESCR(BSQ_ACTIVE_ENTRIES, 0x06, 0x07, FALSE, BSU_ESCR1, NONE), - /* BSQ_ACTIVE_ENTRIES inherits CPU specificity from BSQ_ALLOCATION */ -P4_EVDESCR(SSE_INPUT_ASSIST, 0x34, 0x01, TRUE, FIRM_ESCR0, FIRM_ESCR1), -P4_EVDESCR(PACKED_SP_UOP, 0x08, 0x01, TRUE, FIRM_ESCR0, FIRM_ESCR1), -P4_EVDESCR(PACKED_DP_UOP, 0x0C, 0x01, TRUE, FIRM_ESCR0, FIRM_ESCR1), -P4_EVDESCR(SCALAR_SP_UOP, 0x0A, 0x01, TRUE, FIRM_ESCR0, FIRM_ESCR1), -P4_EVDESCR(SCALAR_DP_UOP, 0x0E, 0x01, TRUE, FIRM_ESCR0, FIRM_ESCR1), -P4_EVDESCR(64BIT_MMX_UOP, 0x02, 0x01, TRUE, FIRM_ESCR0, FIRM_ESCR1), -P4_EVDESCR(128BIT_MMX_UOP, 0x1A, 0x01, TRUE, FIRM_ESCR0, FIRM_ESCR1), -P4_EVDESCR(X87_FP_UOP, 0x04, 0x01, TRUE, FIRM_ESCR0, FIRM_ESCR1), -P4_EVDESCR(X87_SIMD_MOVES_UOP, 0x2E, 0x01, TRUE, FIRM_ESCR0, FIRM_ESCR1), -P4_EVDESCR(GLOBAL_POWER_EVENTS, 0x13, 0x06, FALSE, FSB_ESCR0, FSB_ESCR1), -P4_EVDESCR(TC_MS_XFER, 0x05, 0x00, FALSE, MS_ESCR0, MS_ESCR1), -P4_EVDESCR(UOP_QUEUE_WRITES, 0x09, 0x00, FALSE, MS_ESCR0, MS_ESCR1), -P4_EVDESCR(RETIRED_MISPRED_BRANCH_TYPE, - 0x05, 0x02, FALSE, TBPU_ESCR0, TBPU_ESCR1), -P4_EVDESCR(RETIRED_BRANCH_TYPE, 0x04, 0x02, FALSE, TBPU_ESCR0, TBPU_ESCR1), -P4_EVDESCR(RESOURCE_STALL, 0x01, 0x01, FALSE, ALF_ESCR0, ALF_ESCR1), -P4_EVDESCR(WC_BUFFER, 0x05, 0x05, TRUE, DAC_ESCR0, DAC_ESCR1), -P4_EVDESCR(B2B_CYCLES, 0x16, 0x03, TRUE, FSB_ESCR0, FSB_ESCR1), -P4_EVDESCR(BNR, 0x08, 0x03, TRUE, FSB_ESCR0, FSB_ESCR1), -P4_EVDESCR(SNOOP, 0x06, 0x03, TRUE, FSB_ESCR0, FSB_ESCR1), -P4_EVDESCR(RESPONSE, 0x04, 0x03, TRUE, FSB_ESCR0, FSB_ESCR1), -P4_EVDESCR(FRONT_END_EVENT, 0x08, 0x05, FALSE, CRU_ESCR2, CRU_ESCR3), -P4_EVDESCR(EXECUTION_EVENT, 0x0C, 0x05, FALSE, CRU_ESCR2, CRU_ESCR3), -P4_EVDESCR(REPLAY_EVENT, 0x09, 0x05, FALSE, CRU_ESCR2, CRU_ESCR3), -P4_EVDESCR(INSTR_RETIRED, 0x02, 0x04, FALSE, CRU_ESCR0, CRU_ESCR1), -P4_EVDESCR(UOPS_RETIRED, 0x01, 0x04, FALSE, CRU_ESCR0, CRU_ESCR1), -P4_EVDESCR(UOP_TYPE, 0x02, 0x02, FALSE, RAT_ESCR0, RAT_ESCR1), -P4_EVDESCR(BRANCH_RETIRED, 0x06, 0x05, FALSE, CRU_ESCR2, CRU_ESCR3), -P4_EVDESCR(MISPRED_BRANCH_RETIRED, 0x03, 0x04, FALSE, CRU_ESCR0, CRU_ESCR1), -P4_EVDESCR(X87_ASSIST, 0x03, 0x05, FALSE, CRU_ESCR2, CRU_ESCR3), -P4_EVDESCR(MACHINE_CLEAR, 0x02, 0x05, FALSE, CRU_ESCR2, CRU_ESCR3) - -#undef P4_EVDESCR -}; - -#define P4_EVENT_IS_TI(E) ((E)->pm_is_ti_event == TRUE) - -#define P4_NEVENTS (PMC_EV_P4_LAST - PMC_EV_P4_FIRST + 1) - -/* - * P4 PMC descriptors - */ - -struct p4pmc_descr { - struct pmc_descr pm_descr; /* common information */ - enum pmc_p4pmc pm_pmcnum; /* PMC number */ - uint32_t pm_pmc_msr; /* PERFCTR MSR address */ - uint32_t pm_cccr_msr; /* CCCR MSR address */ -}; - -static struct p4pmc_descr p4_pmcdesc[P4_NPMCS] = { -#define P4_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ - PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ - PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE | \ - PMC_CAP_TAGGING | PMC_CAP_CASCADE) - -#define P4_PMCDESCR(N, PMC, CCCR) \ - { \ - .pm_descr = \ - { \ - .pd_name = #N, \ - .pd_class = PMC_CLASS_P4, \ - .pd_caps = P4_PMC_CAPS, \ - .pd_width = 40 \ - }, \ - .pm_pmcnum = P4_PMC_##N, \ - .pm_cccr_msr = (CCCR), \ - .pm_pmc_msr = (PMC) \ - } - - P4_PMCDESCR(BPU_COUNTER0, 0x300, 0x360), - P4_PMCDESCR(BPU_COUNTER1, 0x301, 0x361), - P4_PMCDESCR(BPU_COUNTER2, 0x302, 0x362), - P4_PMCDESCR(BPU_COUNTER3, 0x303, 0x363), - P4_PMCDESCR(MS_COUNTER0, 0x304, 0x364), - P4_PMCDESCR(MS_COUNTER1, 0x305, 0x365), - P4_PMCDESCR(MS_COUNTER2, 0x306, 0x366), - P4_PMCDESCR(MS_COUNTER3, 0x307, 0x367), - P4_PMCDESCR(FLAME_COUNTER0, 0x308, 0x368), - P4_PMCDESCR(FLAME_COUNTER1, 0x309, 0x369), - P4_PMCDESCR(FLAME_COUNTER2, 0x30A, 0x36A), - P4_PMCDESCR(FLAME_COUNTER3, 0x30B, 0x36B), - P4_PMCDESCR(IQ_COUNTER0, 0x30C, 0x36C), - P4_PMCDESCR(IQ_COUNTER1, 0x30D, 0x36D), - P4_PMCDESCR(IQ_COUNTER2, 0x30E, 0x36E), - P4_PMCDESCR(IQ_COUNTER3, 0x30F, 0x36F), - P4_PMCDESCR(IQ_COUNTER4, 0x310, 0x370), - P4_PMCDESCR(IQ_COUNTER5, 0x311, 0x371), - -#undef P4_PMCDESCR -}; - -/* HTT support */ -#define P4_NHTT 2 /* logical processors/chip */ - -static int p4_system_has_htt; - -/* - * Per-CPU data structure for P4 class CPUs - * - * [19 struct pmc_hw structures] - * [45 ESCRs status bytes] - * [per-cpu spin mutex] - * [19 flag fields for holding config flags and a runcount] - * [19*2 hw value fields] (Thread mode PMC support) - * or - * [19*2 EIP values] (Sampling mode PMCs) - * [19*2 pmc value fields] (Thread mode PMC support)) - */ - -struct p4_cpu { - struct pmc_hw pc_p4pmcs[P4_NPMCS]; - char pc_escrs[P4_NESCR]; - struct mtx pc_mtx; /* spin lock */ - uint32_t pc_intrflag; /* NMI handler flags */ - unsigned int pc_intrlock; /* NMI handler spin lock */ - unsigned char pc_flags[P4_NPMCS]; /* 4 bits each: {cfg,run}count */ - union { - pmc_value_t pc_hw[P4_NPMCS * P4_NHTT]; - uintptr_t pc_ip[P4_NPMCS * P4_NHTT]; - } pc_si; - pmc_value_t pc_pmc_values[P4_NPMCS * P4_NHTT]; -}; - -static struct p4_cpu **p4_pcpu; - -#define P4_PCPU_PMC_VALUE(PC,RI,CPU) (PC)->pc_pmc_values[(RI)*((CPU) & 1)] -#define P4_PCPU_HW_VALUE(PC,RI,CPU) (PC)->pc_si.pc_hw[(RI)*((CPU) & 1)] -#define P4_PCPU_SAVED_IP(PC,RI,CPU) (PC)->pc_si.pc_ip[(RI)*((CPU) & 1)] - -#define P4_PCPU_GET_FLAGS(PC,RI,MASK) ((PC)->pc_flags[(RI)] & (MASK)) -#define P4_PCPU_SET_FLAGS(PC,RI,MASK,VAL) do { \ - char _tmp; \ - _tmp = (PC)->pc_flags[(RI)]; \ - _tmp &= ~(MASK); \ - _tmp |= (VAL) & (MASK); \ - (PC)->pc_flags[(RI)] = _tmp; \ -} while (0) - -#define P4_PCPU_GET_RUNCOUNT(PC,RI) P4_PCPU_GET_FLAGS(PC,RI,0x0F) -#define P4_PCPU_SET_RUNCOUNT(PC,RI,V) P4_PCPU_SET_FLAGS(PC,RI,0x0F,V) - -#define P4_PCPU_GET_CFGFLAGS(PC,RI) (P4_PCPU_GET_FLAGS(PC,RI,0xF0) >> 4) -#define P4_PCPU_SET_CFGFLAGS(PC,RI,C) P4_PCPU_SET_FLAGS(PC,RI,0xF0,((C) <<4)) - -#define P4_CPU_TO_FLAG(C) (P4_CPU_IS_HTT_SECONDARY(cpu) ? 0x2 : 0x1) - -#define P4_PCPU_GET_INTRFLAG(PC,I) ((PC)->pc_intrflag & (1 << (I))) -#define P4_PCPU_SET_INTRFLAG(PC,I,V) do { \ - uint32_t __mask; \ - __mask = 1 << (I); \ - if ((V)) \ - (PC)->pc_intrflag |= __mask; \ - else \ - (PC)->pc_intrflag &= ~__mask; \ - } while (0) - -/* - * A minimal spin lock implementation for use inside the NMI handler. - * - * We don't want to use a regular spin lock here, because curthread - * may not be consistent at the time the handler is invoked. - */ -#define P4_PCPU_ACQ_INTR_SPINLOCK(PC) do { \ - while (!atomic_cmpset_acq_int(&pc->pc_intrlock, 0, 1)) \ - ia32_pause(); \ - } while (0) -#define P4_PCPU_REL_INTR_SPINLOCK(PC) \ - atomic_store_rel_int(&pc->pc_intrlock, 0); - -/* ESCR row disposition */ -static int p4_escrdisp[P4_NESCR]; - -#define P4_ESCR_ROW_DISP_IS_THREAD(E) (p4_escrdisp[(E)] > 0) -#define P4_ESCR_ROW_DISP_IS_STANDALONE(E) (p4_escrdisp[(E)] < 0) -#define P4_ESCR_ROW_DISP_IS_FREE(E) (p4_escrdisp[(E)] == 0) - -#define P4_ESCR_MARK_ROW_STANDALONE(E) do { \ - KASSERT(p4_escrdisp[(E)] <= 0, ("[p4,%d] row disposition error",\ - __LINE__)); \ - atomic_add_int(&p4_escrdisp[(E)], -1); \ - KASSERT(p4_escrdisp[(E)] >= (-pmc_cpu_max_active()), \ - ("[p4,%d] row disposition error", __LINE__)); \ -} while (0) - -#define P4_ESCR_UNMARK_ROW_STANDALONE(E) do { \ - atomic_add_int(&p4_escrdisp[(E)], 1); \ - KASSERT(p4_escrdisp[(E)] <= 0, ("[p4,%d] row disposition error",\ - __LINE__)); \ -} while (0) - -#define P4_ESCR_MARK_ROW_THREAD(E) do { \ - KASSERT(p4_escrdisp[(E)] >= 0, ("[p4,%d] row disposition error", \ - __LINE__)); \ - atomic_add_int(&p4_escrdisp[(E)], 1); \ -} while (0) - -#define P4_ESCR_UNMARK_ROW_THREAD(E) do { \ - atomic_add_int(&p4_escrdisp[(E)], -1); \ - KASSERT(p4_escrdisp[(E)] >= 0, ("[p4,%d] row disposition error", \ - __LINE__)); \ -} while (0) - -#define P4_PMC_IS_STOPPED(cccr) ((rdmsr(cccr) & P4_CCCR_ENABLE) == 0) - -#define P4_CPU_IS_HTT_SECONDARY(cpu) \ - (p4_system_has_htt ? ((cpu) & 1) : 0) -#define P4_TO_HTT_PRIMARY(cpu) \ - (p4_system_has_htt ? ((cpu) & ~1) : (cpu)) - -#define P4_CCCR_Tx_MASK (~(P4_CCCR_OVF_PMI_T0|P4_CCCR_OVF_PMI_T1| \ - P4_CCCR_ENABLE|P4_CCCR_OVF)) -#define P4_ESCR_Tx_MASK (~(P4_ESCR_T0_OS|P4_ESCR_T0_USR|P4_ESCR_T1_OS| \ - P4_ESCR_T1_USR)) - -/* - * support routines - */ - -static struct p4_event_descr * -p4_find_event(enum pmc_event ev) -{ - int n; - - for (n = 0; n < P4_NEVENTS; n++) - if (p4_events[n].pm_event == ev) - break; - if (n == P4_NEVENTS) - return (NULL); - return (&p4_events[n]); -} - -/* - * Initialize per-cpu state - */ - -static int -p4_pcpu_init(struct pmc_mdep *md, int cpu) -{ - char *pescr; - int n, first_ri, phycpu; - struct pmc_hw *phw; - struct p4_cpu *p4c; - struct pmc_cpu *pc, *plc; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p4,%d] insane cpu number %d", __LINE__, cpu)); - - PMCDBG2(MDP,INI,0, "p4-init cpu=%d is-primary=%d", cpu, - pmc_cpu_is_primary(cpu) != 0); - - first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P4].pcd_ri; - - /* - * The two CPUs in an HT pair share their per-cpu state. - * - * For HT capable CPUs, we assume that the two logical - * processors in the HT pair get two consecutive CPU ids - * starting with an even id #. - * - * The primary CPU (the even numbered CPU of the pair) would - * have been initialized prior to the initialization for the - * secondary. - */ - - if (!pmc_cpu_is_primary(cpu) && (cpu & 1)) { - - p4_system_has_htt = 1; - - phycpu = P4_TO_HTT_PRIMARY(cpu); - pc = pmc_pcpu[phycpu]; - plc = pmc_pcpu[cpu]; - - KASSERT(plc != pc, ("[p4,%d] per-cpu config error", __LINE__)); - - PMCDBG3(MDP,INI,1, "p4-init cpu=%d phycpu=%d pc=%p", cpu, - phycpu, pc); - KASSERT(pc, ("[p4,%d] Null Per-Cpu state cpu=%d phycpu=%d", - __LINE__, cpu, phycpu)); - - /* PMCs are shared with the physical CPU. */ - for (n = 0; n < P4_NPMCS; n++) - plc->pc_hwpmcs[n + first_ri] = - pc->pc_hwpmcs[n + first_ri]; - - return (0); - } - - p4c = malloc(sizeof(struct p4_cpu), M_PMC, M_WAITOK|M_ZERO); - - pc = pmc_pcpu[cpu]; - - KASSERT(pc != NULL, ("[p4,%d] cpu %d null per-cpu", __LINE__, cpu)); - - p4_pcpu[cpu] = p4c; - phw = p4c->pc_p4pmcs; - - for (n = 0; n < P4_NPMCS; n++, phw++) { - phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | - PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n); - phw->phw_pmc = NULL; - pc->pc_hwpmcs[n + first_ri] = phw; - } - - pescr = p4c->pc_escrs; - for (n = 0; n < P4_NESCR; n++) - *pescr++ = P4_INVALID_PMC_INDEX; - - mtx_init(&p4c->pc_mtx, "p4-pcpu", "pmc-leaf", MTX_SPIN); - - return (0); -} - -/* - * Destroy per-cpu state. - */ - -static int -p4_pcpu_fini(struct pmc_mdep *md, int cpu) -{ - int first_ri, i; - struct p4_cpu *p4c; - struct pmc_cpu *pc; - - PMCDBG1(MDP,INI,0, "p4-cleanup cpu=%d", cpu); - - pc = pmc_pcpu[cpu]; - first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P4].pcd_ri; - - for (i = 0; i < P4_NPMCS; i++) - pc->pc_hwpmcs[i + first_ri] = NULL; - - if (!pmc_cpu_is_primary(cpu) && (cpu & 1)) - return (0); - - p4c = p4_pcpu[cpu]; - - KASSERT(p4c != NULL, ("[p4,%d] NULL pcpu", __LINE__)); - - /* Turn off all PMCs on this CPU */ - for (i = 0; i < P4_NPMCS - 1; i++) - wrmsr(P4_CCCR_MSR_FIRST + i, - rdmsr(P4_CCCR_MSR_FIRST + i) & ~P4_CCCR_ENABLE); - - mtx_destroy(&p4c->pc_mtx); - - free(p4c, M_PMC); - - p4_pcpu[cpu] = NULL; - - return (0); -} - -/* - * Read a PMC - */ - -static int -p4_read_pmc(int cpu, int ri, pmc_value_t *v) -{ - struct pmc *pm; - pmc_value_t tmp; - struct p4_cpu *pc; - enum pmc_mode mode; - struct p4pmc_descr *pd; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p4,%d] illegal CPU value %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P4_NPMCS, - ("[p4,%d] illegal row-index %d", __LINE__, ri)); - - pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)]; - pm = pc->pc_p4pmcs[ri].phw_pmc; - pd = &p4_pmcdesc[ri]; - - KASSERT(pm != NULL, - ("[p4,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__, cpu, ri)); - - KASSERT(pd->pm_descr.pd_class == PMC_TO_CLASS(pm), - ("[p4,%d] class mismatch pd %d != id class %d", __LINE__, - pd->pm_descr.pd_class, PMC_TO_CLASS(pm))); - - mode = PMC_TO_MODE(pm); - - PMCDBG3(MDP,REA,1, "p4-read cpu=%d ri=%d mode=%d", cpu, ri, mode); - - KASSERT(pd->pm_descr.pd_class == PMC_CLASS_P4, - ("[p4,%d] unknown PMC class %d", __LINE__, pd->pm_descr.pd_class)); - - tmp = rdmsr(p4_pmcdesc[ri].pm_pmc_msr); - - if (PMC_IS_VIRTUAL_MODE(mode)) { - if (tmp < P4_PCPU_HW_VALUE(pc,ri,cpu)) /* 40 bit overflow */ - tmp += (P4_PERFCTR_MASK + 1) - - P4_PCPU_HW_VALUE(pc,ri,cpu); - else - tmp -= P4_PCPU_HW_VALUE(pc,ri,cpu); - tmp += P4_PCPU_PMC_VALUE(pc,ri,cpu); - } - - if (PMC_IS_SAMPLING_MODE(mode)) /* undo transformation */ - *v = P4_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); - else - *v = tmp; - - PMCDBG1(MDP,REA,2, "p4-read -> %jx", *v); - - return (0); -} - -/* - * Write a PMC - */ - -static int -p4_write_pmc(int cpu, int ri, pmc_value_t v) -{ - enum pmc_mode mode; - struct pmc *pm; - struct p4_cpu *pc; - const struct pmc_hw *phw; - const struct p4pmc_descr *pd; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P4_NPMCS, - ("[amd,%d] illegal row-index %d", __LINE__, ri)); - - pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)]; - phw = &pc->pc_p4pmcs[ri]; - pm = phw->phw_pmc; - pd = &p4_pmcdesc[ri]; - - KASSERT(pm != NULL, - ("[p4,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__, - cpu, ri)); - - mode = PMC_TO_MODE(pm); - - PMCDBG4(MDP,WRI,1, "p4-write cpu=%d ri=%d mode=%d v=%jx", cpu, ri, - mode, v); - - /* - * write the PMC value to the register/saved value: for - * sampling mode PMCs, the value to be programmed into the PMC - * counter is -(C+1) where 'C' is the requested sample rate. - */ - if (PMC_IS_SAMPLING_MODE(mode)) - v = P4_RELOAD_COUNT_TO_PERFCTR_VALUE(v); - - if (PMC_IS_SYSTEM_MODE(mode)) - wrmsr(pd->pm_pmc_msr, v); - else - P4_PCPU_PMC_VALUE(pc,ri,cpu) = v; - - return (0); -} - -/* - * Configure a PMC 'pm' on the given CPU and row-index. - * - * 'pm' may be NULL to indicate de-configuration. - * - * On HTT systems, a PMC may get configured twice, once for each - * "logical" CPU. We track this using the CFGFLAGS field of the - * per-cpu state; this field is a bit mask with one bit each for - * logical CPUs 0 & 1. - */ - -static int -p4_config_pmc(int cpu, int ri, struct pmc *pm) -{ - struct pmc_hw *phw; - struct p4_cpu *pc; - int cfgflags, cpuflag; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p4,%d] illegal CPU %d", __LINE__, cpu)); - - KASSERT(ri >= 0 && ri < P4_NPMCS, - ("[p4,%d] illegal row-index %d", __LINE__, ri)); - - PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); - - pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)]; - phw = &pc->pc_p4pmcs[ri]; - - KASSERT(pm == NULL || phw->phw_pmc == NULL || - (p4_system_has_htt && phw->phw_pmc == pm), - ("[p4,%d] hwpmc not unconfigured before re-config", __LINE__)); - - mtx_lock_spin(&pc->pc_mtx); - cfgflags = P4_PCPU_GET_CFGFLAGS(pc,ri); - - KASSERT((cfgflags & ~0x3) == 0, - ("[p4,%d] illegal cfgflags cfg=%#x on cpu=%d ri=%d", __LINE__, - cfgflags, cpu, ri)); - - KASSERT(cfgflags == 0 || phw->phw_pmc, - ("[p4,%d] cpu=%d ri=%d pmc configured with zero cfg count", - __LINE__, cpu, ri)); - - cpuflag = P4_CPU_TO_FLAG(cpu); - - if (pm) { /* config */ - if (cfgflags == 0) - phw->phw_pmc = pm; - - KASSERT(phw->phw_pmc == pm, - ("[p4,%d] cpu=%d ri=%d config %p != hw %p", - __LINE__, cpu, ri, pm, phw->phw_pmc)); - - cfgflags |= cpuflag; - } else { /* unconfig */ - cfgflags &= ~cpuflag; - - if (cfgflags == 0) - phw->phw_pmc = NULL; - } - - KASSERT((cfgflags & ~0x3) == 0, - ("[p4,%d] illegal runcount cfg=%#x on cpu=%d ri=%d", __LINE__, - cfgflags, cpu, ri)); - - P4_PCPU_SET_CFGFLAGS(pc,ri,cfgflags); - - mtx_unlock_spin(&pc->pc_mtx); - - return (0); -} - -/* - * Retrieve a configured PMC pointer from hardware state. - */ - -static int -p4_get_config(int cpu, int ri, struct pmc **ppm) -{ - int cfgflags; - struct p4_cpu *pc; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p4,%d] illegal CPU %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P4_NPMCS, - ("[p4,%d] illegal row-index %d", __LINE__, ri)); - - pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)]; - - mtx_lock_spin(&pc->pc_mtx); - cfgflags = P4_PCPU_GET_CFGFLAGS(pc,ri); - mtx_unlock_spin(&pc->pc_mtx); - - if (cfgflags & P4_CPU_TO_FLAG(cpu)) - *ppm = pc->pc_p4pmcs[ri].phw_pmc; /* PMC config'ed on this CPU */ - else - *ppm = NULL; - - return 0; -} - -/* - * Allocate a PMC. - * - * The allocation strategy differs between HTT and non-HTT systems. - * - * The non-HTT case: - * - Given the desired event and the PMC row-index, lookup the - * list of valid ESCRs for the event. - * - For each valid ESCR: - * - Check if the ESCR is free and the ESCR row is in a compatible - * mode (i.e., system or process)) - * - Check if the ESCR is usable with a P4 PMC at the desired row-index. - * If everything matches, we determine the appropriate bit values for the - * ESCR and CCCR registers. - * - * The HTT case: - * - * - Process mode PMCs require special care. The FreeBSD scheduler could - * schedule any two processes on the same physical CPU. We need to ensure - * that a given PMC row-index is never allocated to two different - * PMCs owned by different user-processes. - * This is ensured by always allocating a PMC from a 'FREE' PMC row - * if the system has HTT active. - * - A similar check needs to be done for ESCRs; we do not want two PMCs - * using the same ESCR to be scheduled at the same time. Thus ESCR - * allocation is also restricted to FREE rows if the system has HTT - * enabled. - * - Thirdly, some events are 'thread-independent' terminology, i.e., - * the PMC hardware cannot distinguish between events caused by - * different logical CPUs. This makes it impossible to assign events - * to a given thread of execution. If the system has HTT enabled, - * these events are not allowed for process-mode PMCs. - */ - -static int -p4_allocate_pmc(int cpu, int ri, struct pmc *pm, - const struct pmc_op_pmcallocate *a) -{ - int found, n, m; - uint32_t caps, cccrvalue, escrvalue, tflags; - enum pmc_p4escr escr; - struct p4_cpu *pc; - struct p4_event_descr *pevent; - const struct p4pmc_descr *pd; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p4,%d] illegal CPU %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P4_NPMCS, - ("[p4,%d] illegal row-index value %d", __LINE__, ri)); - - pd = &p4_pmcdesc[ri]; - - PMCDBG4(MDP,ALL,1, "p4-allocate ri=%d class=%d pmccaps=0x%x " - "reqcaps=0x%x", ri, pd->pm_descr.pd_class, pd->pm_descr.pd_caps, - pm->pm_caps); - - /* check class */ - if (pd->pm_descr.pd_class != a->pm_class) - return (EINVAL); - - /* check requested capabilities */ - caps = a->pm_caps; - if ((pd->pm_descr.pd_caps & caps) != caps) - return (EPERM); - - /* - * If the system has HTT enabled, and the desired allocation - * mode is process-private, and the PMC row disposition is not - * FREE (0), decline the allocation. - */ - - if (p4_system_has_htt && - PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm)) && - pmc_getrowdisp(ri) != 0) - return (EBUSY); - - KASSERT(pd->pm_descr.pd_class == PMC_CLASS_P4, - ("[p4,%d] unknown PMC class %d", __LINE__, - pd->pm_descr.pd_class)); - - if (pm->pm_event < PMC_EV_P4_FIRST || - pm->pm_event > PMC_EV_P4_LAST) - return (EINVAL); - - if ((pevent = p4_find_event(pm->pm_event)) == NULL) - return (ESRCH); - - PMCDBG4(MDP,ALL,2, "pevent={ev=%d,escrsel=0x%x,cccrsel=0x%x,isti=%d}", - pevent->pm_event, pevent->pm_escr_eventselect, - pevent->pm_cccr_select, pevent->pm_is_ti_event); - - /* - * Some PMC events are 'thread independent'and therefore - * cannot be used for process-private modes if HTT is being - * used. - */ - - if (P4_EVENT_IS_TI(pevent) && - PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm)) && - p4_system_has_htt) - return (EINVAL); - - pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)]; - - found = 0; - - /* look for a suitable ESCR for this event */ - for (n = 0; n < P4_MAX_ESCR_PER_EVENT && !found; n++) { - if ((escr = pevent->pm_escrs[n]) == P4_ESCR_NONE) - break; /* out of ESCRs */ - /* - * Check ESCR row disposition. - * - * If the request is for a system-mode PMC, then the - * ESCR row should not be in process-virtual mode, and - * should also be free on the current CPU. - */ - - if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) { - if (P4_ESCR_ROW_DISP_IS_THREAD(escr) || - pc->pc_escrs[escr] != P4_INVALID_PMC_INDEX) - continue; - } - - /* - * If the request is for a process-virtual PMC, and if - * HTT is not enabled, we can use an ESCR row that is - * either FREE or already in process mode. - * - * If HTT is enabled, then we need to ensure that a - * given ESCR is never allocated to two PMCS that - * could run simultaneously on the two logical CPUs of - * a CPU package. We ensure this be only allocating - * ESCRs from rows marked as 'FREE'. - */ - - if (PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm))) { - if (p4_system_has_htt) { - if (!P4_ESCR_ROW_DISP_IS_FREE(escr)) - continue; - } else - if (P4_ESCR_ROW_DISP_IS_STANDALONE(escr)) - continue; - } - - /* - * We found a suitable ESCR for this event. Now check if - * this escr can work with the PMC at row-index 'ri'. - */ - - for (m = 0; m < P4_MAX_PMC_PER_ESCR; m++) - if (p4_escrs[escr].pm_pmcs[m] == pd->pm_pmcnum) { - found = 1; - break; - } - } - - if (found == 0) - return (ESRCH); - - KASSERT((int) escr >= 0 && escr < P4_NESCR, - ("[p4,%d] illegal ESCR value %d", __LINE__, escr)); - - /* mark ESCR row mode */ - if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) { - pc->pc_escrs[escr] = ri; /* mark ESCR as in use on this cpu */ - P4_ESCR_MARK_ROW_STANDALONE(escr); - } else { - KASSERT(pc->pc_escrs[escr] == P4_INVALID_PMC_INDEX, - ("[p4,%d] escr[%d] already in use", __LINE__, escr)); - P4_ESCR_MARK_ROW_THREAD(escr); - } - - pm->pm_md.pm_p4.pm_p4_escrmsr = p4_escrs[escr].pm_escr_msr; - pm->pm_md.pm_p4.pm_p4_escr = escr; - - cccrvalue = P4_CCCR_TO_ESCR_SELECT(pevent->pm_cccr_select); - escrvalue = P4_ESCR_TO_EVENT_SELECT(pevent->pm_escr_eventselect); - - /* CCCR fields */ - if (caps & PMC_CAP_THRESHOLD) - cccrvalue |= (a->pm_md.pm_p4.pm_p4_cccrconfig & - P4_CCCR_THRESHOLD_MASK) | P4_CCCR_COMPARE; - - if (caps & PMC_CAP_EDGE) - cccrvalue |= P4_CCCR_EDGE; - - if (caps & PMC_CAP_INVERT) - cccrvalue |= P4_CCCR_COMPLEMENT; - - if (p4_system_has_htt) - cccrvalue |= a->pm_md.pm_p4.pm_p4_cccrconfig & - P4_CCCR_ACTIVE_THREAD_MASK; - else /* no HTT; thread field should be '11b' */ - cccrvalue |= P4_CCCR_TO_ACTIVE_THREAD(0x3); - - if (caps & PMC_CAP_CASCADE) - cccrvalue |= P4_CCCR_CASCADE; - - /* On HTT systems the PMI T0 field may get moved to T1 at pmc start */ - if (caps & PMC_CAP_INTERRUPT) - cccrvalue |= P4_CCCR_OVF_PMI_T0; - - /* ESCR fields */ - if (caps & PMC_CAP_QUALIFIER) - escrvalue |= a->pm_md.pm_p4.pm_p4_escrconfig & - P4_ESCR_EVENT_MASK_MASK; - if (caps & PMC_CAP_TAGGING) - escrvalue |= (a->pm_md.pm_p4.pm_p4_escrconfig & - P4_ESCR_TAG_VALUE_MASK) | P4_ESCR_TAG_ENABLE; - if (caps & PMC_CAP_QUALIFIER) - escrvalue |= (a->pm_md.pm_p4.pm_p4_escrconfig & - P4_ESCR_EVENT_MASK_MASK); - - /* HTT: T0_{OS,USR} bits may get moved to T1 at pmc start */ - tflags = 0; - if (caps & PMC_CAP_SYSTEM) - tflags |= P4_ESCR_T0_OS; - if (caps & PMC_CAP_USER) - tflags |= P4_ESCR_T0_USR; - if (tflags == 0) - tflags = (P4_ESCR_T0_OS|P4_ESCR_T0_USR); - escrvalue |= tflags; - - pm->pm_md.pm_p4.pm_p4_cccrvalue = cccrvalue; - pm->pm_md.pm_p4.pm_p4_escrvalue = escrvalue; - - PMCDBG5(MDP,ALL,2, "p4-allocate cccrsel=0x%x cccrval=0x%x " - "escr=%d escrmsr=0x%x escrval=0x%x", pevent->pm_cccr_select, - cccrvalue, escr, pm->pm_md.pm_p4.pm_p4_escrmsr, escrvalue); - - return (0); -} - -/* - * release a PMC. - */ - -static int -p4_release_pmc(int cpu, int ri, struct pmc *pm) -{ - enum pmc_p4escr escr; - struct p4_cpu *pc; - - KASSERT(ri >= 0 && ri < P4_NPMCS, - ("[p4,%d] illegal row-index %d", __LINE__, ri)); - - escr = pm->pm_md.pm_p4.pm_p4_escr; - - PMCDBG3(MDP,REL,1, "p4-release cpu=%d ri=%d escr=%d", cpu, ri, escr); - - if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) { - pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)]; - - KASSERT(pc->pc_p4pmcs[ri].phw_pmc == NULL, - ("[p4,%d] releasing configured PMC ri=%d", __LINE__, ri)); - - P4_ESCR_UNMARK_ROW_STANDALONE(escr); - KASSERT(pc->pc_escrs[escr] == ri, - ("[p4,%d] escr[%d] not allocated to ri %d", __LINE__, - escr, ri)); - pc->pc_escrs[escr] = P4_INVALID_PMC_INDEX; /* mark as free */ - } else - P4_ESCR_UNMARK_ROW_THREAD(escr); - - return (0); -} - -/* - * Start a PMC - */ - -static int -p4_start_pmc(int cpu, int ri) -{ - int rc; - struct pmc *pm; - struct p4_cpu *pc; - struct p4pmc_descr *pd; - uint32_t cccrvalue, cccrtbits, escrvalue, escrmsr, escrtbits; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p4,%d] illegal CPU value %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P4_NPMCS, - ("[p4,%d] illegal row-index %d", __LINE__, ri)); - - pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)]; - pm = pc->pc_p4pmcs[ri].phw_pmc; - pd = &p4_pmcdesc[ri]; - - KASSERT(pm != NULL, - ("[p4,%d] starting cpu%d,pmc%d with null pmc", __LINE__, cpu, ri)); - - PMCDBG2(MDP,STA,1, "p4-start cpu=%d ri=%d", cpu, ri); - - KASSERT(pd->pm_descr.pd_class == PMC_CLASS_P4, - ("[p4,%d] wrong PMC class %d", __LINE__, - pd->pm_descr.pd_class)); - - /* retrieve the desired CCCR/ESCR values from the PMC */ - cccrvalue = pm->pm_md.pm_p4.pm_p4_cccrvalue; - escrvalue = pm->pm_md.pm_p4.pm_p4_escrvalue; - escrmsr = pm->pm_md.pm_p4.pm_p4_escrmsr; - - /* extract and zero the logical processor selection bits */ - cccrtbits = cccrvalue & P4_CCCR_OVF_PMI_T0; - escrtbits = escrvalue & (P4_ESCR_T0_OS|P4_ESCR_T0_USR); - cccrvalue &= ~P4_CCCR_OVF_PMI_T0; - escrvalue &= ~(P4_ESCR_T0_OS|P4_ESCR_T0_USR); - - if (P4_CPU_IS_HTT_SECONDARY(cpu)) { /* shift T0 bits to T1 position */ - cccrtbits <<= 1; - escrtbits >>= 2; - } - - /* start system mode PMCs directly */ - if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) { - wrmsr(escrmsr, escrvalue | escrtbits); - wrmsr(pd->pm_cccr_msr, cccrvalue | cccrtbits | P4_CCCR_ENABLE); - return 0; - } - - /* - * Thread mode PMCs - * - * On HTT machines, the same PMC could be scheduled on the - * same physical CPU twice (once for each logical CPU), for - * example, if two threads of a multi-threaded process get - * scheduled on the same CPU. - * - */ - - mtx_lock_spin(&pc->pc_mtx); - - rc = P4_PCPU_GET_RUNCOUNT(pc,ri); - KASSERT(rc == 0 || rc == 1, - ("[p4,%d] illegal runcount cpu=%d ri=%d rc=%d", __LINE__, cpu, ri, - rc)); - - if (rc == 0) { /* 1st CPU and the non-HTT case */ - - KASSERT(P4_PMC_IS_STOPPED(pd->pm_cccr_msr), - ("[p4,%d] cpu=%d ri=%d cccr=0x%x not stopped", __LINE__, - cpu, ri, pd->pm_cccr_msr)); - - /* write out the low 40 bits of the saved value to hardware */ - wrmsr(pd->pm_pmc_msr, - P4_PCPU_PMC_VALUE(pc,ri,cpu) & P4_PERFCTR_MASK); - - } else if (rc == 1) { /* 2nd CPU */ - - /* - * Stop the PMC and retrieve the CCCR and ESCR values - * from their MSRs, and turn on the additional T[0/1] - * bits for the 2nd CPU. - */ - - cccrvalue = rdmsr(pd->pm_cccr_msr); - wrmsr(pd->pm_cccr_msr, cccrvalue & ~P4_CCCR_ENABLE); - - /* check that the configuration bits read back match the PMC */ - KASSERT((cccrvalue & P4_CCCR_Tx_MASK) == - (pm->pm_md.pm_p4.pm_p4_cccrvalue & P4_CCCR_Tx_MASK), - ("[p4,%d] Extra CCCR bits cpu=%d rc=%d ri=%d " - "cccr=0x%x PMC=0x%x", __LINE__, cpu, rc, ri, - cccrvalue & P4_CCCR_Tx_MASK, - pm->pm_md.pm_p4.pm_p4_cccrvalue & P4_CCCR_Tx_MASK)); - KASSERT(cccrvalue & P4_CCCR_ENABLE, - ("[p4,%d] 2nd cpu rc=%d cpu=%d ri=%d not running", - __LINE__, rc, cpu, ri)); - KASSERT((cccrvalue & cccrtbits) == 0, - ("[p4,%d] CCCR T0/T1 mismatch rc=%d cpu=%d ri=%d" - "cccrvalue=0x%x tbits=0x%x", __LINE__, rc, cpu, ri, - cccrvalue, cccrtbits)); - - escrvalue = rdmsr(escrmsr); - - KASSERT((escrvalue & P4_ESCR_Tx_MASK) == - (pm->pm_md.pm_p4.pm_p4_escrvalue & P4_ESCR_Tx_MASK), - ("[p4,%d] Extra ESCR bits cpu=%d rc=%d ri=%d " - "escr=0x%x pm=0x%x", __LINE__, cpu, rc, ri, - escrvalue & P4_ESCR_Tx_MASK, - pm->pm_md.pm_p4.pm_p4_escrvalue & P4_ESCR_Tx_MASK)); - KASSERT((escrvalue & escrtbits) == 0, - ("[p4,%d] ESCR T0/T1 mismatch rc=%d cpu=%d ri=%d " - "escrmsr=0x%x escrvalue=0x%x tbits=0x%x", __LINE__, - rc, cpu, ri, escrmsr, escrvalue, escrtbits)); - } - - /* Enable the correct bits for this CPU. */ - escrvalue |= escrtbits; - cccrvalue |= cccrtbits | P4_CCCR_ENABLE; - - /* Save HW value at the time of starting hardware */ - P4_PCPU_HW_VALUE(pc,ri,cpu) = rdmsr(pd->pm_pmc_msr); - - /* Program the ESCR and CCCR and start the PMC */ - wrmsr(escrmsr, escrvalue); - wrmsr(pd->pm_cccr_msr, cccrvalue); - - ++rc; - P4_PCPU_SET_RUNCOUNT(pc,ri,rc); - - mtx_unlock_spin(&pc->pc_mtx); - - PMCDBG6(MDP,STA,2,"p4-start cpu=%d rc=%d ri=%d escr=%d " - "escrmsr=0x%x escrvalue=0x%x", cpu, rc, - ri, pm->pm_md.pm_p4.pm_p4_escr, escrmsr, escrvalue); - PMCDBG2(MDP,STA,2,"cccr_config=0x%x v=%jx", - cccrvalue, P4_PCPU_HW_VALUE(pc,ri,cpu)); - - return (0); -} - -/* - * Stop a PMC. - */ - -static int -p4_stop_pmc(int cpu, int ri) -{ - int rc; - uint32_t cccrvalue, cccrtbits, escrvalue, escrmsr, escrtbits; - struct pmc *pm; - struct p4_cpu *pc; - struct p4pmc_descr *pd; - pmc_value_t tmp; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p4,%d] illegal CPU value %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P4_NPMCS, - ("[p4,%d] illegal row index %d", __LINE__, ri)); - - pd = &p4_pmcdesc[ri]; - pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)]; - pm = pc->pc_p4pmcs[ri].phw_pmc; - - KASSERT(pm != NULL, - ("[p4,%d] null pmc for cpu%d, ri%d", __LINE__, cpu, ri)); - - PMCDBG2(MDP,STO,1, "p4-stop cpu=%d ri=%d", cpu, ri); - - if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) { - wrmsr(pd->pm_cccr_msr, - pm->pm_md.pm_p4.pm_p4_cccrvalue & ~P4_CCCR_ENABLE); - return (0); - } - - /* - * Thread mode PMCs. - * - * On HTT machines, this PMC may be in use by two threads - * running on two logical CPUS. Thus we look at the - * 'runcount' field and only turn off the appropriate TO/T1 - * bits (and keep the PMC running) if two logical CPUs were - * using the PMC. - * - */ - - /* bits to mask */ - cccrtbits = P4_CCCR_OVF_PMI_T0; - escrtbits = P4_ESCR_T0_OS | P4_ESCR_T0_USR; - if (P4_CPU_IS_HTT_SECONDARY(cpu)) { - cccrtbits <<= 1; - escrtbits >>= 2; - } - - mtx_lock_spin(&pc->pc_mtx); - - rc = P4_PCPU_GET_RUNCOUNT(pc,ri); - - KASSERT(rc == 2 || rc == 1, - ("[p4,%d] illegal runcount cpu=%d ri=%d rc=%d", __LINE__, cpu, ri, - rc)); - - --rc; - - P4_PCPU_SET_RUNCOUNT(pc,ri,rc); - - /* Stop this PMC */ - cccrvalue = rdmsr(pd->pm_cccr_msr); - wrmsr(pd->pm_cccr_msr, cccrvalue & ~P4_CCCR_ENABLE); - - escrmsr = pm->pm_md.pm_p4.pm_p4_escrmsr; - escrvalue = rdmsr(escrmsr); - - /* The current CPU should be running on this PMC */ - KASSERT(escrvalue & escrtbits, - ("[p4,%d] ESCR T0/T1 mismatch cpu=%d rc=%d ri=%d escrmsr=0x%x " - "escrvalue=0x%x tbits=0x%x", __LINE__, cpu, rc, ri, escrmsr, - escrvalue, escrtbits)); - KASSERT(PMC_IS_COUNTING_MODE(PMC_TO_MODE(pm)) || - (cccrvalue & cccrtbits), - ("[p4,%d] CCCR T0/T1 mismatch cpu=%d ri=%d cccrvalue=0x%x " - "tbits=0x%x", __LINE__, cpu, ri, cccrvalue, cccrtbits)); - - /* get the current hardware reading */ - tmp = rdmsr(pd->pm_pmc_msr); - - if (rc == 1) { /* need to keep the PMC running */ - escrvalue &= ~escrtbits; - cccrvalue &= ~cccrtbits; - wrmsr(escrmsr, escrvalue); - wrmsr(pd->pm_cccr_msr, cccrvalue); - } - - mtx_unlock_spin(&pc->pc_mtx); - - PMCDBG5(MDP,STO,2, "p4-stop cpu=%d rc=%d ri=%d escrmsr=0x%x " - "escrval=0x%x", cpu, rc, ri, escrmsr, escrvalue); - PMCDBG2(MDP,STO,2, "cccrval=0x%x v=%jx", cccrvalue, tmp); - - if (tmp < P4_PCPU_HW_VALUE(pc,ri,cpu)) /* 40 bit counter overflow */ - tmp += (P4_PERFCTR_MASK + 1) - P4_PCPU_HW_VALUE(pc,ri,cpu); - else - tmp -= P4_PCPU_HW_VALUE(pc,ri,cpu); - - P4_PCPU_PMC_VALUE(pc,ri,cpu) += tmp; - - return 0; -} - -/* - * Handle an interrupt. - * - * The hardware sets the CCCR_OVF whenever a counter overflow occurs, - * so the handler examines all the 18 CCCR registers, processing the - * counters that have overflowed. - * - * On HTT machines, the CCCR register is shared and will interrupt - * both logical processors if so configured. Thus multiple logical - * CPUs could enter the NMI service routine at the same time. These - * will get serialized using a per-cpu spinlock dedicated for use in - * the NMI handler. - */ - -static int -p4_intr(int cpu, struct trapframe *tf) -{ - uint32_t cccrval, ovf_mask, ovf_partner; - int did_interrupt, error, ri; - struct p4_cpu *pc; - struct pmc *pm; - pmc_value_t v; - - PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, - TRAPF_USERMODE(tf)); - - pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)]; - - ovf_mask = P4_CPU_IS_HTT_SECONDARY(cpu) ? - P4_CCCR_OVF_PMI_T1 : P4_CCCR_OVF_PMI_T0; - ovf_mask |= P4_CCCR_OVF; - if (p4_system_has_htt) - ovf_partner = P4_CPU_IS_HTT_SECONDARY(cpu) ? - P4_CCCR_OVF_PMI_T0 : P4_CCCR_OVF_PMI_T1; - else - ovf_partner = 0; - did_interrupt = 0; - - if (p4_system_has_htt) - P4_PCPU_ACQ_INTR_SPINLOCK(pc); - - /* - * Loop through all CCCRs, looking for ones that have - * interrupted this CPU. - */ - for (ri = 0; ri < P4_NPMCS; ri++) { - - /* - * Check if our partner logical CPU has already marked - * this PMC has having interrupted it. If so, reset - * the flag and process the interrupt, but leave the - * hardware alone. - */ - if (p4_system_has_htt && P4_PCPU_GET_INTRFLAG(pc,ri)) { - P4_PCPU_SET_INTRFLAG(pc,ri,0); - did_interrupt = 1; - - /* - * Ignore de-configured or stopped PMCs. - * Ignore PMCs not in sampling mode. - */ - pm = pc->pc_p4pmcs[ri].phw_pmc; - if (pm == NULL || - pm->pm_state != PMC_STATE_RUNNING || - !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { - continue; - } - (void) pmc_process_interrupt(cpu, PMC_HR, pm, tf, - TRAPF_USERMODE(tf)); - continue; - } - - /* - * Fresh interrupt. Look for the CCCR_OVF bit - * and the OVF_Tx bit for this logical - * processor being set. - */ - cccrval = rdmsr(P4_CCCR_MSR_FIRST + ri); - - if ((cccrval & ovf_mask) != ovf_mask) - continue; - - /* - * If the other logical CPU would also have been - * interrupted due to the PMC being shared, record - * this fact in the per-cpu saved interrupt flag - * bitmask. - */ - if (p4_system_has_htt && (cccrval & ovf_partner)) - P4_PCPU_SET_INTRFLAG(pc, ri, 1); - - v = rdmsr(P4_PERFCTR_MSR_FIRST + ri); - - PMCDBG2(MDP,INT, 2, "ri=%d v=%jx", ri, v); - - /* Stop the counter, and reset the overflow bit */ - cccrval &= ~(P4_CCCR_OVF | P4_CCCR_ENABLE); - wrmsr(P4_CCCR_MSR_FIRST + ri, cccrval); - - did_interrupt = 1; - - /* - * Ignore de-configured or stopped PMCs. Ignore PMCs - * not in sampling mode. - */ - pm = pc->pc_p4pmcs[ri].phw_pmc; - - if (pm == NULL || - pm->pm_state != PMC_STATE_RUNNING || - !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { - continue; - } - - /* - * Process the interrupt. Re-enable the PMC if - * processing was successful. - */ - error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, - TRAPF_USERMODE(tf)); - - /* - * Only the first processor executing the NMI handler - * in a HTT pair will restart a PMC, and that too - * only if there were no errors. - */ - v = P4_RELOAD_COUNT_TO_PERFCTR_VALUE( - pm->pm_sc.pm_reloadcount); - wrmsr(P4_PERFCTR_MSR_FIRST + ri, v); - if (error == 0) - wrmsr(P4_CCCR_MSR_FIRST + ri, - cccrval | P4_CCCR_ENABLE); - } - - /* allow the other CPU to proceed */ - if (p4_system_has_htt) - P4_PCPU_REL_INTR_SPINLOCK(pc); - - /* - * On Intel P4 CPUs, the PMC 'pcint' entry in the LAPIC gets - * masked when a PMC interrupts the CPU. We need to unmask - * the interrupt source explicitly. - */ - - if (did_interrupt) - lapic_reenable_pmc(); - - if (did_interrupt) - counter_u64_add(pmc_stats.pm_intr_processed, 1); - else - counter_u64_add(pmc_stats.pm_intr_ignored, 1); - - return (did_interrupt); -} - -/* - * Describe a CPU's PMC state. - */ - -static int -p4_describe(int cpu, int ri, struct pmc_info *pi, - struct pmc **ppmc) -{ - int error; - size_t copied; - const struct p4pmc_descr *pd; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p4,%d] illegal CPU %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P4_NPMCS, - ("[p4,%d] row-index %d out of range", __LINE__, ri)); - - PMCDBG2(MDP,OPS,1,"p4-describe cpu=%d ri=%d", cpu, ri); - - if (P4_CPU_IS_HTT_SECONDARY(cpu)) - return (EINVAL); - - pd = &p4_pmcdesc[ri]; - - if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name, - PMC_NAME_MAX, &copied)) != 0) - return (error); - - pi->pm_class = pd->pm_descr.pd_class; - - if (p4_pcpu[cpu]->pc_p4pmcs[ri].phw_state & PMC_PHW_FLAG_IS_ENABLED) { - pi->pm_enabled = TRUE; - *ppmc = p4_pcpu[cpu]->pc_p4pmcs[ri].phw_pmc; - } else { - pi->pm_enabled = FALSE; - *ppmc = NULL; - } - - return (0); -} - -/* - * Get MSR# for use with RDPMC. - */ - -static int -p4_get_msr(int ri, uint32_t *msr) -{ - KASSERT(ri >= 0 && ri < P4_NPMCS, - ("[p4,%d] ri %d out of range", __LINE__, ri)); - - *msr = p4_pmcdesc[ri].pm_pmc_msr - P4_PERFCTR_MSR_FIRST; - - PMCDBG2(MDP,OPS, 1, "ri=%d getmsr=0x%x", ri, *msr); - - return 0; -} - - -int -pmc_p4_initialize(struct pmc_mdep *md, int ncpus) -{ - struct pmc_classdep *pcd; - struct p4_event_descr *pe; - - KASSERT(md != NULL, ("[p4,%d] md is NULL", __LINE__)); - KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, - ("[p4,%d] Initializing non-intel processor", __LINE__)); - - PMCDBG0(MDP,INI,1, "p4-initialize"); - - /* Allocate space for pointers to per-cpu descriptors. */ - p4_pcpu = malloc(sizeof(*p4_pcpu) * ncpus, M_PMC, M_ZERO | M_WAITOK); - - /* Fill in the class dependent descriptor. */ - pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P4]; - - switch (md->pmd_cputype) { - case PMC_CPU_INTEL_PIV: - - pcd->pcd_caps = P4_PMC_CAPS; - pcd->pcd_class = PMC_CLASS_P4; - pcd->pcd_num = P4_NPMCS; - pcd->pcd_ri = md->pmd_npmc; - pcd->pcd_width = 40; - - pcd->pcd_allocate_pmc = p4_allocate_pmc; - pcd->pcd_config_pmc = p4_config_pmc; - pcd->pcd_describe = p4_describe; - pcd->pcd_get_config = p4_get_config; - pcd->pcd_get_msr = p4_get_msr; - pcd->pcd_pcpu_fini = p4_pcpu_fini; - pcd->pcd_pcpu_init = p4_pcpu_init; - pcd->pcd_read_pmc = p4_read_pmc; - pcd->pcd_release_pmc = p4_release_pmc; - pcd->pcd_start_pmc = p4_start_pmc; - pcd->pcd_stop_pmc = p4_stop_pmc; - pcd->pcd_write_pmc = p4_write_pmc; - - md->pmd_pcpu_fini = NULL; - md->pmd_pcpu_init = NULL; - md->pmd_intr = p4_intr; - md->pmd_npmc += P4_NPMCS; - - /* model specific configuration */ - if ((cpu_id & 0xFFF) < 0xF27) { - - /* - * On P4 and Xeon with CPUID < (Family 15, - * Model 2, Stepping 7), only one ESCR is - * available for the IOQ_ALLOCATION event. - */ - - pe = p4_find_event(PMC_EV_P4_IOQ_ALLOCATION); - pe->pm_escrs[1] = P4_ESCR_NONE; - } - - break; - - default: - KASSERT(0,("[p4,%d] Unknown CPU type", __LINE__)); - return ENOSYS; - } - - return (0); -} - -void -pmc_p4_finalize(struct pmc_mdep *md) -{ -#if defined(INVARIANTS) - int i, ncpus; -#endif - - KASSERT(p4_pcpu != NULL, - ("[p4,%d] NULL p4_pcpu", __LINE__)); - -#if defined(INVARIANTS) - ncpus = pmc_cpu_max(); - for (i = 0; i < ncpus; i++) - KASSERT(p4_pcpu[i] == NULL, ("[p4,%d] non-null pcpu %d", - __LINE__, i)); -#endif - - free(p4_pcpu, M_PMC); - p4_pcpu = NULL; -} diff --git a/sys/dev/hwpmc/hwpmc_piv.h b/sys/dev/hwpmc/hwpmc_piv.h deleted file mode 100644 index 14e5ed4a6f4c..000000000000 --- a/sys/dev/hwpmc/hwpmc_piv.h +++ /dev/null @@ -1,127 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2005, Joseph Koshy - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/* Machine dependent interfaces */ - -#ifndef _DEV_HWPMC_PIV_H_ -#define _DEV_HWPMC_PIV_H_ 1 - -/* Intel P4 PMCs */ - -#define P4_NPMCS 18 -#define P4_NESCR 45 -#define P4_INVALID_PMC_INDEX -1 -#define P4_MAX_ESCR_PER_EVENT 2 -#define P4_MAX_PMC_PER_ESCR 3 - -#define P4_CCCR_OVF (1U << 31) -#define P4_CCCR_CASCADE (1 << 30) -#define P4_CCCR_OVF_PMI_T1 (1 << 27) -#define P4_CCCR_OVF_PMI_T0 (1 << 26) -#define P4_CCCR_FORCE_OVF (1 << 25) -#define P4_CCCR_EDGE (1 << 24) -#define P4_CCCR_THRESHOLD_SHIFT 20 -#define P4_CCCR_THRESHOLD_MASK 0x00F00000 -#define P4_CCCR_TO_THRESHOLD(C) (((C) << P4_CCCR_THRESHOLD_SHIFT) & \ - P4_CCCR_THRESHOLD_MASK) -#define P4_CCCR_COMPLEMENT (1 << 19) -#define P4_CCCR_COMPARE (1 << 18) -#define P4_CCCR_ACTIVE_THREAD_SHIFT 16 -#define P4_CCCR_ACTIVE_THREAD_MASK 0x00030000 -#define P4_CCCR_TO_ACTIVE_THREAD(T) (((T) << P4_CCCR_ACTIVE_THREAD_SHIFT) & \ - P4_CCCR_ACTIVE_THREAD_MASK) -#define P4_CCCR_ESCR_SELECT_SHIFT 13 -#define P4_CCCR_ESCR_SELECT_MASK 0x0000E000 -#define P4_CCCR_TO_ESCR_SELECT(E) (((E) << P4_CCCR_ESCR_SELECT_SHIFT) & \ - P4_CCCR_ESCR_SELECT_MASK) -#define P4_CCCR_ENABLE (1 << 12) -#define P4_CCCR_VALID_BITS (P4_CCCR_OVF | P4_CCCR_CASCADE | \ - P4_CCCR_OVF_PMI_T1 | P4_CCCR_OVF_PMI_T0 | P4_CCCR_FORCE_OVF | \ - P4_CCCR_EDGE | P4_CCCR_THRESHOLD_MASK | P4_CCCR_COMPLEMENT | \ - P4_CCCR_COMPARE | P4_CCCR_ESCR_SELECT_MASK | P4_CCCR_ENABLE) - -#define P4_ESCR_EVENT_SELECT_SHIFT 25 -#define P4_ESCR_EVENT_SELECT_MASK 0x7E000000 -#define P4_ESCR_TO_EVENT_SELECT(E) (((E) << P4_ESCR_EVENT_SELECT_SHIFT) & \ - P4_ESCR_EVENT_SELECT_MASK) -#define P4_ESCR_EVENT_MASK_SHIFT 9 -#define P4_ESCR_EVENT_MASK_MASK 0x01FFFE00 -#define P4_ESCR_TO_EVENT_MASK(M) (((M) << P4_ESCR_EVENT_MASK_SHIFT) & \ - P4_ESCR_EVENT_MASK_MASK) -#define P4_ESCR_TAG_VALUE_SHIFT 5 -#define P4_ESCR_TAG_VALUE_MASK 0x000001E0 -#define P4_ESCR_TO_TAG_VALUE(T) (((T) << P4_ESCR_TAG_VALUE_SHIFT) & \ - P4_ESCR_TAG_VALUE_MASK) -#define P4_ESCR_TAG_ENABLE 0x00000010 -#define P4_ESCR_T0_OS 0x00000008 -#define P4_ESCR_T0_USR 0x00000004 -#define P4_ESCR_T1_OS 0x00000002 -#define P4_ESCR_T1_USR 0x00000001 -#define P4_ESCR_OS P4_ESCR_T0_OS -#define P4_ESCR_USR P4_ESCR_T0_USR -#define P4_ESCR_VALID_BITS (P4_ESCR_EVENT_SELECT_MASK | \ - P4_ESCR_EVENT_MASK_MASK | P4_ESCR_TAG_VALUE_MASK | \ - P4_ESCR_TAG_ENABLE | P4_ESCR_T0_OS | P4_ESCR_T0_USR | P4_ESCR_T1_OS \ - P4_ESCR_T1_USR) - -#define P4_PERFCTR_MASK 0xFFFFFFFFFFLL /* 40 bits */ -#define P4_PERFCTR_OVERFLOWED(PMC) ((rdpmc(PMC) & (1LL << 39)) == 0) - -#define P4_CCCR_MSR_FIRST 0x360 /* MSR_BPU_CCCR0 */ -#define P4_PERFCTR_MSR_FIRST 0x300 /* MSR_BPU_COUNTER0 */ - -#define P4_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (1 - (V)) -#define P4_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (1 - (P)) - -struct pmc_md_p4_op_pmcallocate { - uint32_t pm_p4_cccrconfig; - uint32_t pm_p4_escrconfig; -}; - -#ifdef _KERNEL - -/* MD extension for 'struct pmc' */ -struct pmc_md_p4_pmc { - uint32_t pm_p4_cccrvalue; - uint32_t pm_p4_escrvalue; - uint32_t pm_p4_escr; - uint32_t pm_p4_escrmsr; -}; - - -/* - * Prototypes - */ - -int pmc_p4_initialize(struct pmc_mdep *_md, int _ncpus); -void pmc_p4_finalize(struct pmc_mdep *md); - -#endif /* _KERNEL */ -#endif /* _DEV_HWPMC_PIV_H_ */ diff --git a/sys/dev/hwpmc/hwpmc_ppro.c b/sys/dev/hwpmc/hwpmc_ppro.c deleted file mode 100644 index 47fc70c04451..000000000000 --- a/sys/dev/hwpmc/hwpmc_ppro.c +++ /dev/null @@ -1,870 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003-2005,2008 Joseph Koshy - * Copyright (c) 2007 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by A. Joseph Koshy under - * sponsorship from the FreeBSD Foundation and Google, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * PENTIUM PRO SUPPORT - * - * Quirks: - * - * - Both PMCs are enabled by a single bit P6_EVSEL_EN in performance - * counter '0'. This bit needs to be '1' if any of the two - * performance counters are in use. Perf counters can also be - * switched off by writing zeros to their EVSEL register. - * - * - While the width of these counters is 40 bits, we do not appear to - * have a way of writing 40 bits to the counter MSRs. A WRMSR - * instruction will sign extend bit 31 of the value being written to - * the perf counter -- a value of 0x80000000 written to an perf - * counter register will be sign extended to 0xFF80000000. - * - * This quirk primarily affects thread-mode PMCs in counting mode, as - * these PMCs read and write PMC registers at every context switch. - */ - -struct p6pmc_descr { - struct pmc_descr pm_descr; /* common information */ - uint32_t pm_pmc_msr; - uint32_t pm_evsel_msr; -}; - -static struct p6pmc_descr p6_pmcdesc[P6_NPMCS] = { - -#define P6_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ - PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ - PMC_CAP_INVERT | PMC_CAP_QUALIFIER) - - /* PMC 0 */ - { - .pm_descr = - { - .pd_name ="P6-0", - .pd_class = PMC_CLASS_P6, - .pd_caps = P6_PMC_CAPS, - .pd_width = 40 - }, - .pm_pmc_msr = P6_MSR_PERFCTR0, - .pm_evsel_msr = P6_MSR_EVSEL0 - }, - - /* PMC 1 */ - { - .pm_descr = - { - .pd_name ="P6-1", - .pd_class = PMC_CLASS_P6, - .pd_caps = P6_PMC_CAPS, - .pd_width = 40 - }, - .pm_pmc_msr = P6_MSR_PERFCTR1, - .pm_evsel_msr = P6_MSR_EVSEL1 - } -}; - -static enum pmc_cputype p6_cputype; - -/* - * P6 Event descriptor - * - * The 'pm_flags' field has the following structure: - * - The upper 4 bits are used to track which counter an event is valid on. - * - The lower bits form a bitmask of flags indicating support for the event - * on a given CPU. - */ - -struct p6_event_descr { - const enum pmc_event pm_event; - uint32_t pm_evsel; - uint32_t pm_flags; - uint32_t pm_unitmask; -}; - -#define P6F_CTR(C) (1 << (28 + (C))) -#define P6F_CTR0 P6F_CTR(0) -#define P6F_CTR1 P6F_CTR(1) -#define P6F(CPU) (1 << ((CPU) - PMC_CPU_INTEL_P6)) -#define _P6F(C) P6F(PMC_CPU_INTEL_##C) -#define P6F_P6 _P6F(P6) -#define P6F_CL _P6F(CL) -#define P6F_PII _P6F(PII) -#define P6F_PIII _P6F(PIII) -#define P6F_PM _P6F(PM) -#define P6F_ALL_CPUS (P6F_P6 | P6F_PII | P6F_CL | P6F_PIII | P6F_PM) -#define P6F_ALL_CTRS (P6F_CTR0 | P6F_CTR1) -#define P6F_ALL (P6F_ALL_CPUS | P6F_ALL_CTRS) - -#define P6_EVENT_VALID_FOR_CPU(P,CPU) ((P)->pm_flags & P6F(CPU)) -#define P6_EVENT_VALID_FOR_CTR(P,CTR) ((P)->pm_flags & P6F_CTR(CTR)) - -static const struct p6_event_descr p6_events[] = { - -#define P6_EVDESCR(NAME, EVSEL, FLAGS, UMASK) \ - { \ - .pm_event = PMC_EV_P6_##NAME, \ - .pm_evsel = (EVSEL), \ - .pm_flags = (FLAGS), \ - .pm_unitmask = (UMASK) \ - } - -P6_EVDESCR(DATA_MEM_REFS, 0x43, P6F_ALL, 0x00), -P6_EVDESCR(DCU_LINES_IN, 0x45, P6F_ALL, 0x00), -P6_EVDESCR(DCU_M_LINES_IN, 0x46, P6F_ALL, 0x00), -P6_EVDESCR(DCU_M_LINES_OUT, 0x47, P6F_ALL, 0x00), -P6_EVDESCR(DCU_MISS_OUTSTANDING, 0x47, P6F_ALL, 0x00), -P6_EVDESCR(IFU_FETCH, 0x80, P6F_ALL, 0x00), -P6_EVDESCR(IFU_FETCH_MISS, 0x81, P6F_ALL, 0x00), -P6_EVDESCR(ITLB_MISS, 0x85, P6F_ALL, 0x00), -P6_EVDESCR(IFU_MEM_STALL, 0x86, P6F_ALL, 0x00), -P6_EVDESCR(ILD_STALL, 0x87, P6F_ALL, 0x00), -P6_EVDESCR(L2_IFETCH, 0x28, P6F_ALL, 0x0F), -P6_EVDESCR(L2_LD, 0x29, P6F_ALL, 0x0F), -P6_EVDESCR(L2_ST, 0x2A, P6F_ALL, 0x0F), -P6_EVDESCR(L2_LINES_IN, 0x24, P6F_ALL, 0x0F), -P6_EVDESCR(L2_LINES_OUT, 0x26, P6F_ALL, 0x0F), -P6_EVDESCR(L2_M_LINES_INM, 0x25, P6F_ALL, 0x00), -P6_EVDESCR(L2_M_LINES_OUTM, 0x27, P6F_ALL, 0x0F), -P6_EVDESCR(L2_RQSTS, 0x2E, P6F_ALL, 0x0F), -P6_EVDESCR(L2_ADS, 0x21, P6F_ALL, 0x00), -P6_EVDESCR(L2_DBUS_BUSY, 0x22, P6F_ALL, 0x00), -P6_EVDESCR(L2_DBUS_BUSY_RD, 0x23, P6F_ALL, 0x00), -P6_EVDESCR(BUS_DRDY_CLOCKS, 0x62, P6F_ALL, 0x20), -P6_EVDESCR(BUS_LOCK_CLOCKS, 0x63, P6F_ALL, 0x20), -P6_EVDESCR(BUS_REQ_OUTSTANDING, 0x60, P6F_ALL, 0x00), -P6_EVDESCR(BUS_TRAN_BRD, 0x65, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRAN_RFO, 0x66, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRANS_WB, 0x67, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRAN_IFETCH, 0x68, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRAN_INVAL, 0x69, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRAN_PWR, 0x6A, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRANS_P, 0x6B, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRANS_IO, 0x6C, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRAN_DEF, 0x6D, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRAN_BURST, 0x6E, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRAN_ANY, 0x70, P6F_ALL, 0x20), -P6_EVDESCR(BUS_TRAN_MEM, 0x6F, P6F_ALL, 0x20), -P6_EVDESCR(BUS_DATA_RCV, 0x64, P6F_ALL, 0x00), -P6_EVDESCR(BUS_BNR_DRV, 0x61, P6F_ALL, 0x00), -P6_EVDESCR(BUS_HIT_DRV, 0x7A, P6F_ALL, 0x00), -P6_EVDESCR(BUS_HITM_DRV, 0x7B, P6F_ALL, 0x00), -P6_EVDESCR(BUS_SNOOP_STALL, 0x7E, P6F_ALL, 0x00), -P6_EVDESCR(FLOPS, 0xC1, P6F_ALL_CPUS | P6F_CTR0, 0x00), -P6_EVDESCR(FP_COMPS_OPS_EXE, 0x10, P6F_ALL_CPUS | P6F_CTR0, 0x00), -P6_EVDESCR(FP_ASSIST, 0x11, P6F_ALL_CPUS | P6F_CTR1, 0x00), -P6_EVDESCR(MUL, 0x12, P6F_ALL_CPUS | P6F_CTR1, 0x00), -P6_EVDESCR(DIV, 0x13, P6F_ALL_CPUS | P6F_CTR1, 0x00), -P6_EVDESCR(CYCLES_DIV_BUSY, 0x14, P6F_ALL_CPUS | P6F_CTR0, 0x00), -P6_EVDESCR(LD_BLOCKS, 0x03, P6F_ALL, 0x00), -P6_EVDESCR(SB_DRAINS, 0x04, P6F_ALL, 0x00), -P6_EVDESCR(MISALIGN_MEM_REF, 0x05, P6F_ALL, 0x00), -P6_EVDESCR(EMON_KNI_PREF_DISPATCHED, 0x07, P6F_PIII | P6F_ALL_CTRS, 0x03), -P6_EVDESCR(EMON_KNI_PREF_MISS, 0x4B, P6F_PIII | P6F_ALL_CTRS, 0x03), -P6_EVDESCR(INST_RETIRED, 0xC0, P6F_ALL, 0x00), -P6_EVDESCR(UOPS_RETIRED, 0xC2, P6F_ALL, 0x00), -P6_EVDESCR(INST_DECODED, 0xD0, P6F_ALL, 0x00), -P6_EVDESCR(EMON_KNI_INST_RETIRED, 0xD8, P6F_PIII | P6F_ALL_CTRS, 0x01), -P6_EVDESCR(EMON_KNI_COMP_INST_RET, 0xD9, P6F_PIII | P6F_ALL_CTRS, 0x01), -P6_EVDESCR(HW_INT_RX, 0xC8, P6F_ALL, 0x00), -P6_EVDESCR(CYCLES_INT_MASKED, 0xC6, P6F_ALL, 0x00), -P6_EVDESCR(CYCLES_INT_PENDING_AND_MASKED, 0xC7, P6F_ALL, 0x00), -P6_EVDESCR(BR_INST_RETIRED, 0xC4, P6F_ALL, 0x00), -P6_EVDESCR(BR_MISS_PRED_RETIRED, 0xC5, P6F_ALL, 0x00), -P6_EVDESCR(BR_TAKEN_RETIRED, 0xC9, P6F_ALL, 0x00), -P6_EVDESCR(BR_MISS_PRED_TAKEN_RET, 0xCA, P6F_ALL, 0x00), -P6_EVDESCR(BR_INST_DECODED, 0xE0, P6F_ALL, 0x00), -P6_EVDESCR(BTB_MISSES, 0xE2, P6F_ALL, 0x00), -P6_EVDESCR(BR_BOGUS, 0xE4, P6F_ALL, 0x00), -P6_EVDESCR(BACLEARS, 0xE6, P6F_ALL, 0x00), -P6_EVDESCR(RESOURCE_STALLS, 0xA2, P6F_ALL, 0x00), -P6_EVDESCR(PARTIAL_RAT_STALLS, 0xD2, P6F_ALL, 0x00), -P6_EVDESCR(SEGMENT_REG_LOADS, 0x06, P6F_ALL, 0x00), -P6_EVDESCR(CPU_CLK_UNHALTED, 0x79, P6F_ALL, 0x00), -P6_EVDESCR(MMX_INSTR_EXEC, 0xB0, - P6F_ALL_CTRS | P6F_CL | P6F_PII, 0x00), -P6_EVDESCR(MMX_SAT_INSTR_EXEC, 0xB1, - P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x00), -P6_EVDESCR(MMX_UOPS_EXEC, 0xB2, - P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x0F), -P6_EVDESCR(MMX_INSTR_TYPE_EXEC, 0xB3, - P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x3F), -P6_EVDESCR(FP_MMX_TRANS, 0xCC, - P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x01), -P6_EVDESCR(MMX_ASSIST, 0xCD, - P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x00), -P6_EVDESCR(MMX_INSTR_RET, 0xCE, P6F_ALL_CTRS | P6F_PII, 0x00), -P6_EVDESCR(SEG_RENAME_STALLS, 0xD4, - P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x0F), -P6_EVDESCR(SEG_REG_RENAMES, 0xD5, - P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x0F), -P6_EVDESCR(RET_SEG_RENAMES, 0xD6, - P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x00), -P6_EVDESCR(EMON_EST_TRANS, 0x58, P6F_ALL_CTRS | P6F_PM, 0x02), -P6_EVDESCR(EMON_THERMAL_TRIP, 0x59, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_INST_EXEC, 0x88, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_MISSP_EXEC, 0x89, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_BAC_MISSP_EXEC, 0x8A, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_CND_EXEC, 0x8B, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_CND_MISSP_EXEC, 0x8C, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_IND_EXEC, 0x8D, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_IND_MISSP_EXEC, 0x8E, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_RET_EXEC, 0x8F, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_RET_MISSP_EXEC, 0x90, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_RET_BAC_MISSP_EXEC, 0x91, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_CALL_EXEC, 0x92, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_CALL_MISSP_EXEC, 0x93, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(BR_IND_CALL_EXEC, 0x94, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(EMON_SIMD_INSTR_RETIRED, 0xCE, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(EMON_SYNCH_UOPS, 0xD3, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(EMON_ESP_UOPS, 0xD7, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(EMON_FUSED_UOPS_RET, 0xDA, P6F_ALL_CTRS | P6F_PM, 0x03), -P6_EVDESCR(EMON_UNFUSION, 0xDB, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(EMON_PREF_RQSTS_UP, 0xF0, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(EMON_PREF_RQSTS_DN, 0xD8, P6F_ALL_CTRS | P6F_PM, 0x00), -P6_EVDESCR(EMON_SSE_SSE2_INST_RETIRED, 0xD8, P6F_ALL_CTRS | P6F_PM, 0x03), -P6_EVDESCR(EMON_SSE_SSE2_COMP_INST_RETIRED, 0xD9, P6F_ALL_CTRS | P6F_PM, 0x03) - -#undef P6_EVDESCR -}; - -#define P6_NEVENTS (PMC_EV_P6_LAST - PMC_EV_P6_FIRST + 1) - -static const struct p6_event_descr * -p6_find_event(enum pmc_event ev) -{ - int n; - - for (n = 0; n < P6_NEVENTS; n++) - if (p6_events[n].pm_event == ev) - break; - if (n == P6_NEVENTS) - return NULL; - return &p6_events[n]; -} - -/* - * Per-CPU data structure for P6 class CPUs - * - * [common stuff] - * [flags for maintaining PMC start/stop state] - * [3 struct pmc_hw pointers] - * [3 struct pmc_hw structures] - */ - -struct p6_cpu { - struct pmc_hw pc_p6pmcs[P6_NPMCS]; - uint32_t pc_state; -}; - -static struct p6_cpu **p6_pcpu; - -/* - * If CTR1 is active, we need to keep the 'EN' bit if CTR0 set, - * with the rest of CTR0 being zero'ed out. - */ -#define P6_SYNC_CTR_STATE(PC) do { \ - uint32_t _config, _enable; \ - _enable = 0; \ - if ((PC)->pc_state & 0x02) \ - _enable |= P6_EVSEL_EN; \ - if ((PC)->pc_state & 0x01) \ - _config = rdmsr(P6_MSR_EVSEL0) | \ - P6_EVSEL_EN; \ - else \ - _config = 0; \ - wrmsr(P6_MSR_EVSEL0, _config | _enable); \ - } while (0) - -#define P6_MARK_STARTED(PC,RI) do { \ - (PC)->pc_state |= (1 << ((RI)-1)); \ - } while (0) - -#define P6_MARK_STOPPED(PC,RI) do { \ - (PC)->pc_state &= ~(1<< ((RI)-1)); \ - } while (0) - -static int -p6_pcpu_init(struct pmc_mdep *md, int cpu) -{ - int first_ri, n; - struct p6_cpu *p6c; - struct pmc_cpu *pc; - struct pmc_hw *phw; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] bad cpu %d", __LINE__, cpu)); - - PMCDBG1(MDP,INI,0,"p6-init cpu=%d", cpu); - - p6c = malloc(sizeof (struct p6_cpu), M_PMC, M_WAITOK|M_ZERO); - pc = pmc_pcpu[cpu]; - - KASSERT(pc != NULL, ("[p6,%d] cpu %d null per-cpu", __LINE__, cpu)); - - phw = p6c->pc_p6pmcs; - p6_pcpu[cpu] = p6c; - - first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P6].pcd_ri; - - for (n = 0; n < P6_NPMCS; n++, phw++) { - phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | - PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n); - phw->phw_pmc = NULL; - pc->pc_hwpmcs[n + first_ri] = phw; - } - - return (0); -} - -static int -p6_pcpu_fini(struct pmc_mdep *md, int cpu) -{ - int first_ri, n; - struct p6_cpu *p6c; - struct pmc_cpu *pc; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] bad cpu %d", __LINE__, cpu)); - - PMCDBG1(MDP,INI,0,"p6-cleanup cpu=%d", cpu); - - p6c = p6_pcpu[cpu]; - p6_pcpu[cpu] = NULL; - - KASSERT(p6c != NULL, ("[p6,%d] null pcpu", __LINE__)); - - free(p6c, M_PMC); - - first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P6].pcd_ri; - pc = pmc_pcpu[cpu]; - for (n = 0; n < P6_NPMCS; n++) - pc->pc_hwpmcs[n + first_ri] = NULL; - - return (0); -} - -static int -p6_read_pmc(int cpu, int ri, pmc_value_t *v) -{ - struct pmc *pm; - struct p6pmc_descr *pd; - pmc_value_t tmp; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] illegal cpu value %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P6_NPMCS, - ("[p6,%d] illegal row-index %d", __LINE__, ri)); - - pm = p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc; - pd = &p6_pmcdesc[ri]; - - KASSERT(pm, - ("[p6,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); - - tmp = rdmsr(pd->pm_pmc_msr) & P6_PERFCTR_READ_MASK; - if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) - *v = P6_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); - else - *v = tmp; - - PMCDBG4(MDP,REA,1, "p6-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, - pd->pm_pmc_msr, *v); - - return (0); -} - -static int -p6_write_pmc(int cpu, int ri, pmc_value_t v) -{ - struct pmc *pm; - struct p6pmc_descr *pd; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] illegal cpu value %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P6_NPMCS, - ("[p6,%d] illegal row-index %d", __LINE__, ri)); - - pm = p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc; - pd = &p6_pmcdesc[ri]; - - KASSERT(pm, - ("[p6,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); - - PMCDBG4(MDP,WRI,1, "p6-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, - pd->pm_pmc_msr, v); - - if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) - v = P6_RELOAD_COUNT_TO_PERFCTR_VALUE(v); - - wrmsr(pd->pm_pmc_msr, v & P6_PERFCTR_WRITE_MASK); - - return (0); -} - -static int -p6_config_pmc(int cpu, int ri, struct pmc *pm) -{ - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] illegal CPU %d", __LINE__, cpu)); - - KASSERT(ri >= 0 && ri < P6_NPMCS, - ("[p6,%d] illegal row-index %d", __LINE__, ri)); - - PMCDBG3(MDP,CFG,1, "p6-config cpu=%d ri=%d pm=%p", cpu, ri, pm); - - KASSERT(p6_pcpu[cpu] != NULL, ("[p6,%d] null per-cpu %d", __LINE__, - cpu)); - - p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc = pm; - - return (0); -} - -/* - * Retrieve a configured PMC pointer from hardware state. - */ - -static int -p6_get_config(int cpu, int ri, struct pmc **ppm) -{ - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] illegal CPU %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P6_NPMCS, - ("[p6,%d] illegal row-index %d", __LINE__, ri)); - - *ppm = p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc; - - return (0); -} - - -/* - * A pmc may be allocated to a given row index if: - * - the event is valid for this CPU - * - the event is valid for this counter index - */ - -static int -p6_allocate_pmc(int cpu, int ri, struct pmc *pm, - const struct pmc_op_pmcallocate *a) -{ - uint32_t allowed_unitmask, caps, config, unitmask; - const struct p6pmc_descr *pd; - const struct p6_event_descr *pevent; - enum pmc_event ev; - - (void) cpu; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] illegal CPU %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P6_NPMCS, - ("[p6,%d] illegal row-index value %d", __LINE__, ri)); - - pd = &p6_pmcdesc[ri]; - - PMCDBG4(MDP,ALL,1, "p6-allocate ri=%d class=%d pmccaps=0x%x " - "reqcaps=0x%x", ri, pd->pm_descr.pd_class, pd->pm_descr.pd_caps, - pm->pm_caps); - - /* check class */ - if (pd->pm_descr.pd_class != a->pm_class) - return (EINVAL); - - /* check requested capabilities */ - caps = a->pm_caps; - if ((pd->pm_descr.pd_caps & caps) != caps) - return (EPERM); - - ev = pm->pm_event; - - if (ev < PMC_EV_P6_FIRST || ev > PMC_EV_P6_LAST) - return (EINVAL); - - if ((pevent = p6_find_event(ev)) == NULL) - return (ESRCH); - - if (!P6_EVENT_VALID_FOR_CPU(pevent, p6_cputype) || - !P6_EVENT_VALID_FOR_CTR(pevent, (ri-1))) - return (EINVAL); - - /* For certain events, Pentium M differs from the stock P6 */ - allowed_unitmask = 0; - if (p6_cputype == PMC_CPU_INTEL_PM) { - if (ev == PMC_EV_P6_L2_LD || ev == PMC_EV_P6_L2_LINES_IN || - ev == PMC_EV_P6_L2_LINES_OUT) - allowed_unitmask = P6_EVSEL_TO_UMASK(0x3F); - else if (ev == PMC_EV_P6_L2_M_LINES_OUTM) - allowed_unitmask = P6_EVSEL_TO_UMASK(0x30); - } else - allowed_unitmask = P6_EVSEL_TO_UMASK(pevent->pm_unitmask); - - unitmask = a->pm_md.pm_ppro.pm_ppro_config & P6_EVSEL_UMASK_MASK; - if (unitmask & ~allowed_unitmask) /* disallow reserved bits */ - return (EINVAL); - - if (ev == PMC_EV_P6_MMX_UOPS_EXEC) /* hardcoded mask */ - unitmask = P6_EVSEL_TO_UMASK(0x0F); - - config = 0; - - config |= P6_EVSEL_EVENT_SELECT(pevent->pm_evsel); - - if (unitmask & (caps & PMC_CAP_QUALIFIER)) - config |= unitmask; - - if (caps & PMC_CAP_THRESHOLD) - config |= a->pm_md.pm_ppro.pm_ppro_config & - P6_EVSEL_CMASK_MASK; - - /* set at least one of the 'usr' or 'os' caps */ - if (caps & PMC_CAP_USER) - config |= P6_EVSEL_USR; - if (caps & PMC_CAP_SYSTEM) - config |= P6_EVSEL_OS; - if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0) - config |= (P6_EVSEL_USR|P6_EVSEL_OS); - - if (caps & PMC_CAP_EDGE) - config |= P6_EVSEL_E; - if (caps & PMC_CAP_INVERT) - config |= P6_EVSEL_INV; - if (caps & PMC_CAP_INTERRUPT) - config |= P6_EVSEL_INT; - - pm->pm_md.pm_ppro.pm_ppro_evsel = config; - - PMCDBG1(MDP,ALL,2, "p6-allocate config=0x%x", config); - - return (0); -} - -static int -p6_release_pmc(int cpu, int ri, struct pmc *pm) -{ - (void) pm; - - PMCDBG3(MDP,REL,1, "p6-release cpu=%d ri=%d pm=%p", cpu, ri, pm); - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] illegal CPU value %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P6_NPMCS, - ("[p6,%d] illegal row-index %d", __LINE__, ri)); - - KASSERT(p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc == NULL, - ("[p6,%d] PHW pmc non-NULL", __LINE__)); - - return (0); -} - -static int -p6_start_pmc(int cpu, int ri) -{ - uint32_t config; - struct pmc *pm; - struct p6_cpu *pc; - const struct p6pmc_descr *pd; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] illegal CPU value %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P6_NPMCS, - ("[p6,%d] illegal row-index %d", __LINE__, ri)); - - pc = p6_pcpu[cpu]; - pm = pc->pc_p6pmcs[ri].phw_pmc; - pd = &p6_pmcdesc[ri]; - - KASSERT(pm, - ("[p6,%d] starting cpu%d,ri%d with no pmc configured", - __LINE__, cpu, ri)); - - PMCDBG2(MDP,STA,1, "p6-start cpu=%d ri=%d", cpu, ri); - - config = pm->pm_md.pm_ppro.pm_ppro_evsel; - - PMCDBG4(MDP,STA,2, "p6-start/2 cpu=%d ri=%d evselmsr=0x%x config=0x%x", - cpu, ri, pd->pm_evsel_msr, config); - - P6_MARK_STARTED(pc, ri); - wrmsr(pd->pm_evsel_msr, config); - - P6_SYNC_CTR_STATE(pc); - - return (0); -} - -static int -p6_stop_pmc(int cpu, int ri) -{ - struct pmc *pm; - struct p6_cpu *pc; - struct p6pmc_descr *pd; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] illegal cpu value %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P6_NPMCS, - ("[p6,%d] illegal row index %d", __LINE__, ri)); - - pc = p6_pcpu[cpu]; - pm = pc->pc_p6pmcs[ri].phw_pmc; - pd = &p6_pmcdesc[ri]; - - KASSERT(pm, - ("[p6,%d] cpu%d ri%d no configured PMC to stop", __LINE__, - cpu, ri)); - - PMCDBG2(MDP,STO,1, "p6-stop cpu=%d ri=%d", cpu, ri); - - wrmsr(pd->pm_evsel_msr, 0); /* stop hw */ - P6_MARK_STOPPED(pc, ri); /* update software state */ - - P6_SYNC_CTR_STATE(pc); /* restart CTR1 if need be */ - - PMCDBG2(MDP,STO,2, "p6-stop/2 cpu=%d ri=%d", cpu, ri); - - return (0); -} - -static int -p6_intr(int cpu, struct trapframe *tf) -{ - int error, retval, ri; - uint32_t perf0cfg; - struct pmc *pm; - struct p6_cpu *pc; - pmc_value_t v; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] CPU %d out of range", __LINE__, cpu)); - - retval = 0; - pc = p6_pcpu[cpu]; - - /* stop both PMCs */ - perf0cfg = rdmsr(P6_MSR_EVSEL0); - wrmsr(P6_MSR_EVSEL0, perf0cfg & ~P6_EVSEL_EN); - - for (ri = 0; ri < P6_NPMCS; ri++) { - - if ((pm = pc->pc_p6pmcs[ri].phw_pmc) == NULL || - !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { - continue; - } - - if (!P6_PMC_HAS_OVERFLOWED(ri)) - continue; - - retval = 1; - - if (pm->pm_state != PMC_STATE_RUNNING) - continue; - - error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, - TRAPF_USERMODE(tf)); - if (error) - P6_MARK_STOPPED(pc,ri); - - /* reload sampling count */ - v = pm->pm_sc.pm_reloadcount; - wrmsr(P6_MSR_PERFCTR0 + ri, - P6_RELOAD_COUNT_TO_PERFCTR_VALUE(v)); - - } - - /* - * On P6 processors, the LAPIC needs to have its PMC interrupt - * unmasked after a PMC interrupt. - */ - if (retval) - lapic_reenable_pmc(); - - if (retval) - counter_u64_add(pmc_stats.pm_intr_processed, 1); - else - counter_u64_add(pmc_stats.pm_intr_ignored, 1); - - /* restart counters that can be restarted */ - P6_SYNC_CTR_STATE(pc); - - return (retval); -} - -static int -p6_describe(int cpu, int ri, struct pmc_info *pi, - struct pmc **ppmc) -{ - int error; - size_t copied; - struct pmc_hw *phw; - struct p6pmc_descr *pd; - - KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), - ("[p6,%d] illegal CPU %d", __LINE__, cpu)); - KASSERT(ri >= 0 && ri < P6_NPMCS, - ("[p6,%d] row-index %d out of range", __LINE__, ri)); - - phw = pmc_pcpu[cpu]->pc_hwpmcs[ri]; - pd = &p6_pmcdesc[ri]; - - KASSERT(phw == &p6_pcpu[cpu]->pc_p6pmcs[ri], - ("[p6,%d] phw mismatch", __LINE__)); - - if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name, - PMC_NAME_MAX, &copied)) != 0) - return (error); - - pi->pm_class = pd->pm_descr.pd_class; - - if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { - pi->pm_enabled = TRUE; - *ppmc = phw->phw_pmc; - } else { - pi->pm_enabled = FALSE; - *ppmc = NULL; - } - - return (0); -} - -static int -p6_get_msr(int ri, uint32_t *msr) -{ - KASSERT(ri >= 0 && ri < P6_NPMCS, - ("[p6,%d ri %d out of range", __LINE__, ri)); - - *msr = p6_pmcdesc[ri].pm_pmc_msr - P6_MSR_PERFCTR0; - - return (0); -} - -int -pmc_p6_initialize(struct pmc_mdep *md, int ncpus) -{ - struct pmc_classdep *pcd; - - KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, - ("[p6,%d] Initializing non-intel processor", __LINE__)); - - PMCDBG0(MDP,INI,1, "p6-initialize"); - - /* Allocate space for pointers to per-cpu descriptors. */ - p6_pcpu = malloc(sizeof(struct p6_cpu **) * ncpus, M_PMC, - M_ZERO|M_WAITOK); - - /* Fill in the class dependent descriptor. */ - pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P6]; - - switch (md->pmd_cputype) { - - /* - * P6 Family Processors - */ - case PMC_CPU_INTEL_P6: - case PMC_CPU_INTEL_CL: - case PMC_CPU_INTEL_PII: - case PMC_CPU_INTEL_PIII: - case PMC_CPU_INTEL_PM: - - p6_cputype = md->pmd_cputype; - - pcd->pcd_caps = P6_PMC_CAPS; - pcd->pcd_class = PMC_CLASS_P6; - pcd->pcd_num = P6_NPMCS; - pcd->pcd_ri = md->pmd_npmc; - pcd->pcd_width = 40; - - pcd->pcd_allocate_pmc = p6_allocate_pmc; - pcd->pcd_config_pmc = p6_config_pmc; - pcd->pcd_describe = p6_describe; - pcd->pcd_get_config = p6_get_config; - pcd->pcd_get_msr = p6_get_msr; - pcd->pcd_pcpu_fini = p6_pcpu_fini; - pcd->pcd_pcpu_init = p6_pcpu_init; - pcd->pcd_read_pmc = p6_read_pmc; - pcd->pcd_release_pmc = p6_release_pmc; - pcd->pcd_start_pmc = p6_start_pmc; - pcd->pcd_stop_pmc = p6_stop_pmc; - pcd->pcd_write_pmc = p6_write_pmc; - - md->pmd_pcpu_fini = NULL; - md->pmd_pcpu_init = NULL; - md->pmd_intr = p6_intr; - - md->pmd_npmc += P6_NPMCS; - - break; - - default: - KASSERT(0,("[p6,%d] Unknown CPU type", __LINE__)); - return ENOSYS; - } - - return (0); -} - -void -pmc_p6_finalize(struct pmc_mdep *md) -{ -#if defined(INVARIANTS) - int i, ncpus; -#endif - - KASSERT(p6_pcpu != NULL, ("[p6,%d] NULL p6_pcpu", __LINE__)); - -#if defined(INVARIANTS) - ncpus = pmc_cpu_max(); - for (i = 0; i < ncpus; i++) - KASSERT(p6_pcpu[i] == NULL, ("[p6,%d] non-null pcpu %d", - __LINE__, i)); -#endif - - free(p6_pcpu, M_PMC); - p6_pcpu = NULL; -} diff --git a/sys/dev/hwpmc/hwpmc_ppro.h b/sys/dev/hwpmc/hwpmc_ppro.h deleted file mode 100644 index 55238704809a..000000000000 --- a/sys/dev/hwpmc/hwpmc_ppro.h +++ /dev/null @@ -1,86 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2005, Joseph Koshy - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/* Machine dependent interfaces */ - -#ifndef _DEV_HWPMC_PPRO_H_ -#define _DEV_HWPMC_PPRO_H_ - -/* Intel PPro, Celeron, P-II, P-III, Pentium-M PMCS */ - -#define P6_NPMCS 2 /* 2 PMCs */ - -#define P6_EVSEL_CMASK_MASK 0xFF000000 -#define P6_EVSEL_TO_CMASK(C) (((C) & 0xFF) << 24) -#define P6_EVSEL_INV (1 << 23) -#define P6_EVSEL_EN (1 << 22) -#define P6_EVSEL_INT (1 << 20) -#define P6_EVSEL_PC (1 << 19) -#define P6_EVSEL_E (1 << 18) -#define P6_EVSEL_OS (1 << 17) -#define P6_EVSEL_USR (1 << 16) -#define P6_EVSEL_UMASK_MASK 0x0000FF00 -#define P6_EVSEL_TO_UMASK(U) (((U) & 0xFF) << 8) -#define P6_EVSEL_EVENT_SELECT(ES) ((ES) & 0xFF) -#define P6_EVSEL_RESERVED (1 << 21) - -#define P6_MSR_EVSEL0 0x0186 -#define P6_MSR_EVSEL1 0x0187 -#define P6_MSR_PERFCTR0 0x00C1 -#define P6_MSR_PERFCTR1 0x00C2 - -#define P6_PERFCTR_READ_MASK 0xFFFFFFFFFFLL /* 40 bits */ -#define P6_PERFCTR_WRITE_MASK 0xFFFFFFFFU /* 32 bits */ - -#define P6_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R)) -#define P6_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) - -#define P6_PMC_HAS_OVERFLOWED(P) ((rdpmc(P) & (1LL << 39)) == 0) - -struct pmc_md_ppro_op_pmcallocate { - uint32_t pm_ppro_config; -}; - -#ifdef _KERNEL - -/* MD extension for 'struct pmc' */ -struct pmc_md_ppro_pmc { - uint32_t pm_ppro_evsel; -}; - -/* - * Prototypes - */ - -int pmc_p6_initialize(struct pmc_mdep *_md, int _ncpus); -void pmc_p6_finalize(struct pmc_mdep *_md); - -#endif /* _KERNEL */ -#endif /* _DEV_HWPMC_PPRO_H_ */ diff --git a/sys/dev/hwpmc/hwpmc_uncore.c b/sys/dev/hwpmc/hwpmc_uncore.c index 50f5e988c643..594367c3542a 100644 --- a/sys/dev/hwpmc/hwpmc_uncore.c +++ b/sys/dev/hwpmc/hwpmc_uncore.c @@ -1,1232 +1,861 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2010 Fabien Thomas * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Intel Uncore PMCs. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #if (__FreeBSD_version >= 1100000) #include #else #include #endif #include #include #include #define UCF_PMC_CAPS \ (PMC_CAP_READ | PMC_CAP_WRITE) #define UCP_PMC_CAPS \ (PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) #define SELECTSEL(x) \ (((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \ UCP_CB0_EVSEL0 : UCP_EVSEL0) #define SELECTOFF(x) \ (((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \ UCF_OFFSET_SB : UCF_OFFSET) static enum pmc_cputype uncore_cputype; struct uncore_cpu { volatile uint32_t pc_resync; volatile uint32_t pc_ucfctrl; /* Fixed function control. */ volatile uint64_t pc_globalctrl; /* Global control register. */ struct pmc_hw pc_uncorepmcs[]; }; static struct uncore_cpu **uncore_pcpu; static uint64_t uncore_pmcmask; static int uncore_ucf_ri; /* relative index of fixed counters */ static int uncore_ucf_width; static int uncore_ucf_npmc; static int uncore_ucp_width; static int uncore_ucp_npmc; static int uncore_pcpu_noop(struct pmc_mdep *md, int cpu) { (void) md; (void) cpu; return (0); } static int uncore_pcpu_init(struct pmc_mdep *md, int cpu) { struct pmc_cpu *pc; struct uncore_cpu *cc; struct pmc_hw *phw; int uncore_ri, n, npmc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[ucf,%d] insane cpu number %d", __LINE__, cpu)); PMCDBG1(MDP,INI,1,"uncore-init cpu=%d", cpu); uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri; npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num; npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num; cc = malloc(sizeof(struct uncore_cpu) + npmc * sizeof(struct pmc_hw), M_PMC, M_WAITOK | M_ZERO); uncore_pcpu[cpu] = cc; pc = pmc_pcpu[cpu]; KASSERT(pc != NULL && cc != NULL, ("[uncore,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); for (n = 0, phw = cc->pc_uncorepmcs; n < npmc; n++, phw++) { phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n + uncore_ri); phw->phw_pmc = NULL; pc->pc_hwpmcs[n + uncore_ri] = phw; } return (0); } static int uncore_pcpu_fini(struct pmc_mdep *md, int cpu) { int uncore_ri, n, npmc; struct pmc_cpu *pc; struct uncore_cpu *cc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] insane cpu number (%d)", __LINE__, cpu)); PMCDBG1(MDP,INI,1,"uncore-pcpu-fini cpu=%d", cpu); if ((cc = uncore_pcpu[cpu]) == NULL) return (0); uncore_pcpu[cpu] = NULL; pc = pmc_pcpu[cpu]; KASSERT(pc != NULL, ("[uncore,%d] NULL per-cpu %d state", __LINE__, cpu)); npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num; uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri; for (n = 0; n < npmc; n++) wrmsr(SELECTSEL(uncore_cputype) + n, 0); wrmsr(UCF_CTRL, 0); npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num; for (n = 0; n < npmc; n++) pc->pc_hwpmcs[n + uncore_ri] = NULL; free(cc, M_PMC); return (0); } /* * Fixed function counters. */ static pmc_value_t ucf_perfctr_value_to_reload_count(pmc_value_t v) { v &= (1ULL << uncore_ucf_width) - 1; return (1ULL << uncore_ucf_width) - v; } static pmc_value_t ucf_reload_count_to_perfctr_value(pmc_value_t rlc) { return (1ULL << uncore_ucf_width) - rlc; } static int ucf_allocate_pmc(int cpu, int ri, struct pmc *pm, const struct pmc_op_pmcallocate *a) { enum pmc_event ev; uint32_t caps, flags; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); PMCDBG2(MDP,ALL,1, "ucf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); if (ri < 0 || ri > uncore_ucf_npmc) return (EINVAL); caps = a->pm_caps; if (a->pm_class != PMC_CLASS_UCF || (caps & UCF_PMC_CAPS) != caps) return (EINVAL); ev = pm->pm_event; - if (ev < PMC_EV_UCF_FIRST || ev > PMC_EV_UCF_LAST) - return (EINVAL); - flags = UCF_EN; pm->pm_md.pm_ucf.pm_ucf_ctrl = (flags << (ri * 4)); PMCDBG1(MDP,ALL,2, "ucf-allocate config=0x%jx", (uintmax_t) pm->pm_md.pm_ucf.pm_ucf_ctrl); return (0); } static int ucf_config_pmc(int cpu, int ri, struct pmc *pm) { KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucf_npmc, ("[uncore,%d] illegal row-index %d", __LINE__, ri)); PMCDBG3(MDP,CFG,1, "ucf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__, cpu)); uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc = pm; return (0); } static int ucf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) { int error; struct pmc_hw *phw; char ucf_name[PMC_NAME_MAX]; phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri]; (void) snprintf(ucf_name, sizeof(ucf_name), "UCF-%d", ri); if ((error = copystr(ucf_name, pi->pm_name, PMC_NAME_MAX, NULL)) != 0) return (error); pi->pm_class = PMC_CLASS_UCF; if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { pi->pm_enabled = TRUE; *ppmc = phw->phw_pmc; } else { pi->pm_enabled = FALSE; *ppmc = NULL; } return (0); } static int ucf_get_config(int cpu, int ri, struct pmc **ppm) { *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; return (0); } static int ucf_read_pmc(int cpu, int ri, pmc_value_t *v) { struct pmc *pm; pmc_value_t tmp; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucf_npmc, ("[uncore,%d] illegal row-index %d", __LINE__, ri)); pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; KASSERT(pm, ("[uncore,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, ri, ri + uncore_ucf_ri)); tmp = rdmsr(UCF_CTR0 + ri); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) *v = ucf_perfctr_value_to_reload_count(tmp); else *v = tmp; PMCDBG3(MDP,REA,1, "ucf-read cpu=%d ri=%d -> v=%jx", cpu, ri, *v); return (0); } static int ucf_release_pmc(int cpu, int ri, struct pmc *pmc) { PMCDBG3(MDP,REL,1, "ucf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucf_npmc, ("[uncore,%d] illegal row-index %d", __LINE__, ri)); KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc == NULL, ("[uncore,%d] PHW pmc non-NULL", __LINE__)); return (0); } static int ucf_start_pmc(int cpu, int ri) { struct pmc *pm; struct uncore_cpu *ucfc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucf_npmc, ("[uncore,%d] illegal row-index %d", __LINE__, ri)); PMCDBG2(MDP,STA,1,"ucf-start cpu=%d ri=%d", cpu, ri); ucfc = uncore_pcpu[cpu]; pm = ucfc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; ucfc->pc_ucfctrl |= pm->pm_md.pm_ucf.pm_ucf_ctrl; wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); do { ucfc->pc_resync = 0; ucfc->pc_globalctrl |= (1ULL << (ri + SELECTOFF(uncore_cputype))); wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); } while (ucfc->pc_resync != 0); PMCDBG4(MDP,STA,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)", ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); return (0); } static int ucf_stop_pmc(int cpu, int ri) { uint32_t fc; struct uncore_cpu *ucfc; PMCDBG2(MDP,STO,1,"ucf-stop cpu=%d ri=%d", cpu, ri); ucfc = uncore_pcpu[cpu]; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucf_npmc, ("[uncore,%d] illegal row-index %d", __LINE__, ri)); fc = (UCF_MASK << (ri * 4)); ucfc->pc_ucfctrl &= ~fc; PMCDBG1(MDP,STO,1,"ucf-stop ucfctrl=%x", ucfc->pc_ucfctrl); wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); do { ucfc->pc_resync = 0; ucfc->pc_globalctrl &= ~(1ULL << (ri + SELECTOFF(uncore_cputype))); wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); } while (ucfc->pc_resync != 0); PMCDBG4(MDP,STO,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)", ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); return (0); } static int ucf_write_pmc(int cpu, int ri, pmc_value_t v) { struct uncore_cpu *cc; struct pmc *pm; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucf_npmc, ("[uncore,%d] illegal row-index %d", __LINE__, ri)); cc = uncore_pcpu[cpu]; pm = cc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; KASSERT(pm, ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) v = ucf_reload_count_to_perfctr_value(v); wrmsr(UCF_CTRL, 0); /* Turn off fixed counters */ wrmsr(UCF_CTR0 + ri, v); wrmsr(UCF_CTRL, cc->pc_ucfctrl); PMCDBG4(MDP,WRI,1, "ucf-write cpu=%d ri=%d v=%jx ucfctrl=%jx ", cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL)); return (0); } static void ucf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) { struct pmc_classdep *pcd; KASSERT(md != NULL, ("[ucf,%d] md is NULL", __LINE__)); PMCDBG0(MDP,INI,1, "ucf-initialize"); pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF]; pcd->pcd_caps = UCF_PMC_CAPS; pcd->pcd_class = PMC_CLASS_UCF; pcd->pcd_num = npmc; pcd->pcd_ri = md->pmd_npmc; pcd->pcd_width = pmcwidth; pcd->pcd_allocate_pmc = ucf_allocate_pmc; pcd->pcd_config_pmc = ucf_config_pmc; pcd->pcd_describe = ucf_describe; pcd->pcd_get_config = ucf_get_config; pcd->pcd_get_msr = NULL; pcd->pcd_pcpu_fini = uncore_pcpu_noop; pcd->pcd_pcpu_init = uncore_pcpu_noop; pcd->pcd_read_pmc = ucf_read_pmc; pcd->pcd_release_pmc = ucf_release_pmc; pcd->pcd_start_pmc = ucf_start_pmc; pcd->pcd_stop_pmc = ucf_stop_pmc; pcd->pcd_write_pmc = ucf_write_pmc; md->pmd_npmc += npmc; } /* * Intel programmable PMCs. */ /* * Event descriptor tables. * * For each event id, we track: * * 1. The CPUs that the event is valid for. * * 2. If the event uses a fixed UMASK, the value of the umask field. * If the event doesn't use a fixed UMASK, a mask of legal bits * to check against. */ struct ucp_event_descr { enum pmc_event ucp_ev; unsigned char ucp_evcode; unsigned char ucp_umask; unsigned char ucp_flags; }; #define UCP_F_I7 (1 << 0) /* CPU: Core i7 */ #define UCP_F_WM (1 << 1) /* CPU: Westmere */ #define UCP_F_SB (1 << 2) /* CPU: Sandy Bridge */ #define UCP_F_HW (1 << 3) /* CPU: Haswell */ #define UCP_F_FM (1 << 4) /* Fixed mask */ #define UCP_F_ALLCPUS \ (UCP_F_I7 | UCP_F_WM) #define UCP_F_CMASK 0xFF000000 -static struct ucp_event_descr ucp_events[] = { -#undef UCPDESCR -#define UCPDESCR(N,EV,UM,FLAGS) { \ - .ucp_ev = PMC_EV_UCP_EVENT_##N, \ - .ucp_evcode = (EV), \ - .ucp_umask = (UM), \ - .ucp_flags = (FLAGS) \ - } - - UCPDESCR(00H_01H, 0x00, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(00H_02H, 0x00, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(00H_04H, 0x00, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(01H_01H, 0x01, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(01H_02H, 0x01, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(01H_04H, 0x01, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(02H_01H, 0x02, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(03H_01H, 0x03, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(03H_02H, 0x03, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(03H_04H, 0x03, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(03H_08H, 0x03, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(03H_10H, 0x03, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(03H_20H, 0x03, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(03H_40H, 0x03, 0x40, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(04H_01H, 0x04, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(04H_02H, 0x04, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(04H_04H, 0x04, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(04H_08H, 0x04, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(04H_10H, 0x04, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(05H_01H, 0x05, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(05H_02H, 0x05, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(05H_04H, 0x05, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(06H_01H, 0x06, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(06H_02H, 0x06, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(06H_04H, 0x06, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(06H_08H, 0x06, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(06H_10H, 0x06, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(06H_20H, 0x06, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(07H_01H, 0x07, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(07H_02H, 0x07, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(07H_04H, 0x07, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(07H_08H, 0x07, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(07H_10H, 0x07, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(07H_20H, 0x07, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(07H_24H, 0x07, 0x24, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(08H_01H, 0x08, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(08H_02H, 0x08, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(08H_04H, 0x08, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(08H_03H, 0x08, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(09H_01H, 0x09, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(09H_02H, 0x09, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(09H_04H, 0x09, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(09H_03H, 0x09, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(0AH_01H, 0x0A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(0AH_02H, 0x0A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(0AH_04H, 0x0A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(0AH_08H, 0x0A, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(0AH_0FH, 0x0A, 0x0F, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(0BH_01H, 0x0B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(0BH_02H, 0x0B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(0BH_04H, 0x0B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(0BH_08H, 0x0B, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(0BH_10H, 0x0B, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(0BH_1FH, 0x0B, 0x1F, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(0CH_01H, 0x0C, 0x01, UCP_F_FM | UCP_F_WM), - UCPDESCR(0CH_02H, 0x0C, 0x02, UCP_F_FM | UCP_F_WM), - UCPDESCR(0CH_04H_E, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), - UCPDESCR(0CH_04H_F, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), - UCPDESCR(0CH_04H_M, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), - UCPDESCR(0CH_04H_S, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), - UCPDESCR(0CH_08H_E, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), - UCPDESCR(0CH_08H_F, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), - UCPDESCR(0CH_08H_M, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), - UCPDESCR(0CH_08H_S, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), - - UCPDESCR(20H_01H, 0x20, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(20H_02H, 0x20, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(20H_04H, 0x20, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(20H_08H, 0x20, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(20H_10H, 0x20, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(20H_20H, 0x20, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(21H_01H, 0x21, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(21H_02H, 0x21, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(21H_04H, 0x21, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(22H_01H, 0x22, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM | - UCP_F_SB | UCP_F_HW), - UCPDESCR(22H_02H, 0x22, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM | - UCP_F_SB | UCP_F_HW), - UCPDESCR(22H_04H, 0x22, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM | - UCP_F_SB | UCP_F_HW), - UCPDESCR(22H_08H, 0x22, 0x08, UCP_F_FM | UCP_F_SB | UCP_F_HW), - UCPDESCR(22H_10H, 0x22, 0x10, UCP_F_FM | UCP_F_HW), - UCPDESCR(22H_20H, 0x22, 0x20, UCP_F_FM | UCP_F_SB | UCP_F_HW), - UCPDESCR(22H_40H, 0x22, 0x40, UCP_F_FM | UCP_F_SB | UCP_F_HW), - UCPDESCR(22H_80H, 0x22, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW), - - UCPDESCR(23H_01H, 0x23, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(23H_02H, 0x23, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(23H_04H, 0x23, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(24H_02H, 0x24, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(24H_04H, 0x24, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(25H_01H, 0x25, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(25H_02H, 0x25, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(25H_04H, 0x25, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(26H_01H, 0x26, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(27H_01H, 0x27, 0x01, UCP_F_FM | UCP_F_I7), - UCPDESCR(27H_02H, 0x27, 0x02, UCP_F_FM | UCP_F_I7), - UCPDESCR(27H_04H, 0x27, 0x04, UCP_F_FM | UCP_F_I7), - UCPDESCR(27H_08H, 0x27, 0x08, UCP_F_FM | UCP_F_I7), - UCPDESCR(27H_10H, 0x27, 0x10, UCP_F_FM | UCP_F_I7), - UCPDESCR(27H_20H, 0x27, 0x20, UCP_F_FM | UCP_F_I7), - - UCPDESCR(28H_01H, 0x28, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(28H_02H, 0x28, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(28H_04H, 0x28, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(28H_08H, 0x28, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(28H_10H, 0x28, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(28H_20H, 0x28, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(29H_01H, 0x29, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(29H_02H, 0x29, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(29H_04H, 0x29, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(29H_08H, 0x29, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(29H_10H, 0x29, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(29H_20H, 0x29, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(2AH_01H, 0x2A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2AH_02H, 0x2A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2AH_04H, 0x2A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2AH_07H, 0x2A, 0x07, UCP_F_FM | UCP_F_WM), - - UCPDESCR(2BH_01H, 0x2B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2BH_02H, 0x2B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2BH_04H, 0x2B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2BH_07H, 0x2B, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(2CH_01H, 0x2C, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2CH_02H, 0x2C, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2CH_04H, 0x2C, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2CH_07H, 0x2C, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(2DH_01H, 0x2D, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2DH_02H, 0x2D, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2DH_04H, 0x2D, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2DH_07H, 0x2D, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(2EH_01H, 0x2E, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2EH_02H, 0x2E, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2EH_04H, 0x2E, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2EH_07H, 0x2E, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(2FH_01H, 0x2F, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2FH_02H, 0x2F, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2FH_04H, 0x2F, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2FH_07H, 0x2F, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2FH_08H, 0x2F, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2FH_10H, 0x2F, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2FH_20H, 0x2F, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(2FH_38H, 0x2F, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(30H_01H, 0x30, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(30H_02H, 0x30, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(30H_04H, 0x30, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(30H_07H, 0x30, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(31H_01H, 0x31, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(31H_02H, 0x31, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(31H_04H, 0x31, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(31H_07H, 0x31, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(32H_01H, 0x32, 0x01, UCP_F_FM | UCP_F_WM), - UCPDESCR(32H_02H, 0x32, 0x02, UCP_F_FM | UCP_F_WM), - UCPDESCR(32H_04H, 0x32, 0x04, UCP_F_FM | UCP_F_WM), - UCPDESCR(32H_07H, 0x32, 0x07, UCP_F_FM | UCP_F_WM), - - UCPDESCR(33H_01H, 0x33, 0x01, UCP_F_FM | UCP_F_WM), - UCPDESCR(33H_02H, 0x33, 0x02, UCP_F_FM | UCP_F_WM), - UCPDESCR(33H_04H, 0x33, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(33H_07H, 0x33, 0x07, UCP_F_FM | UCP_F_WM), - - UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | - UCP_F_HW), - UCPDESCR(34H_02H, 0x34, 0x02, UCP_F_FM | UCP_F_WM | UCP_F_SB), - UCPDESCR(34H_04H, 0x34, 0x04, UCP_F_FM | UCP_F_WM | UCP_F_SB), - UCPDESCR(34H_06H, 0x34, 0x06, UCP_F_FM | UCP_F_HW), - UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM | UCP_F_SB | - UCP_F_HW), - UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM | UCP_F_SB | - UCP_F_HW), - UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM | UCP_F_SB | - UCP_F_HW), - UCPDESCR(34H_40H, 0x34, 0x40, UCP_F_FM | UCP_F_SB | UCP_F_HW), - UCPDESCR(34H_80H, 0x34, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW), - - UCPDESCR(35H_01H, 0x35, 0x01, UCP_F_FM | UCP_F_WM), - UCPDESCR(35H_02H, 0x35, 0x02, UCP_F_FM | UCP_F_WM), - UCPDESCR(35H_04H, 0x35, 0x04, UCP_F_FM | UCP_F_WM), - - UCPDESCR(40H_01H, 0x40, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(40H_02H, 0x40, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(40H_04H, 0x40, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(40H_08H, 0x40, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(40H_10H, 0x40, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(40H_20H, 0x40, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(40H_07H, 0x40, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(40H_38H, 0x40, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(41H_01H, 0x41, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(41H_02H, 0x41, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(41H_04H, 0x41, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(41H_08H, 0x41, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(41H_10H, 0x41, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(41H_20H, 0x41, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(41H_07H, 0x41, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(41H_38H, 0x41, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(42H_01H, 0x42, 0x01, UCP_F_FM | UCP_F_WM), - UCPDESCR(42H_02H, 0x42, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(42H_04H, 0x42, 0x04, UCP_F_FM | UCP_F_WM), - UCPDESCR(42H_08H, 0x42, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(43H_01H, 0x43, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(43H_02H, 0x43, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(60H_01H, 0x60, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(60H_02H, 0x60, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(60H_04H, 0x60, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(61H_01H, 0x61, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(61H_02H, 0x61, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(61H_04H, 0x61, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(62H_01H, 0x62, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(62H_02H, 0x62, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(62H_04H, 0x62, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(63H_01H, 0x63, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(63H_02H, 0x63, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(63H_04H, 0x63, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(63H_08H, 0x63, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(63H_10H, 0x63, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(63H_20H, 0x63, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(64H_01H, 0x64, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(64H_02H, 0x64, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(64H_04H, 0x64, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(64H_08H, 0x64, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(64H_10H, 0x64, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(64H_20H, 0x64, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(65H_01H, 0x65, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(65H_02H, 0x65, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(65H_04H, 0x65, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(66H_01H, 0x66, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(66H_02H, 0x66, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - UCPDESCR(66H_04H, 0x66, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), - - UCPDESCR(67H_01H, 0x67, 0x01, UCP_F_FM | UCP_F_WM), - - UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | - UCP_F_HW), - UCPDESCR(80H_02H, 0x80, 0x02, UCP_F_FM | UCP_F_WM), - UCPDESCR(80H_04H, 0x80, 0x04, UCP_F_FM | UCP_F_WM), - UCPDESCR(80H_08H, 0x80, 0x08, UCP_F_FM | UCP_F_WM), - - UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | - UCP_F_HW), - UCPDESCR(81H_02H, 0x81, 0x02, UCP_F_FM | UCP_F_WM), - UCPDESCR(81H_04H, 0x81, 0x04, UCP_F_FM | UCP_F_WM), - UCPDESCR(81H_08H, 0x81, 0x08, UCP_F_FM | UCP_F_WM), - UCPDESCR(81H_20H, 0x81, 0x20, UCP_F_FM | UCP_F_SB | UCP_F_HW), - UCPDESCR(81H_80H, 0x81, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW), - - UCPDESCR(82H_01H, 0x82, 0x01, UCP_F_FM | UCP_F_WM), - - UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | - UCP_F_HW), - UCPDESCR(83H_02H, 0x83, 0x02, UCP_F_FM | UCP_F_WM), - UCPDESCR(83H_04H, 0x83, 0x04, UCP_F_FM | UCP_F_WM), - UCPDESCR(83H_08H, 0x83, 0x08, UCP_F_FM | UCP_F_WM), - - UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | - UCP_F_HW), - UCPDESCR(84H_02H, 0x84, 0x02, UCP_F_FM | UCP_F_WM), - UCPDESCR(84H_04H, 0x84, 0x04, UCP_F_FM | UCP_F_WM), - UCPDESCR(84H_08H, 0x84, 0x08, UCP_F_FM | UCP_F_WM), - UCPDESCR(85H_02H, 0x85, 0x02, UCP_F_FM | UCP_F_WM), - UCPDESCR(86H_01H, 0x86, 0x01, UCP_F_FM | UCP_F_WM) -}; - static pmc_value_t ucp_perfctr_value_to_reload_count(pmc_value_t v) { v &= (1ULL << uncore_ucp_width) - 1; return (1ULL << uncore_ucp_width) - v; } static pmc_value_t ucp_reload_count_to_perfctr_value(pmc_value_t rlc) { return (1ULL << uncore_ucp_width) - rlc; } /* * Counter specific event information for Sandybridge and Haswell */ static int -ucp_event_sb_hw_ok_on_counter(enum pmc_event pe, int ri) +ucp_event_sb_hw_ok_on_counter(uint8_t ev, int ri) { uint32_t mask; - switch (pe) { + switch (ev) { /* * Events valid only on counter 0. */ - case PMC_EV_UCP_EVENT_80H_01H: - case PMC_EV_UCP_EVENT_83H_01H: + case 0x80: + case 0x83: mask = (1 << 0); break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int ucp_allocate_pmc(int cpu, int ri, struct pmc *pm, const struct pmc_op_pmcallocate *a) { - int n; - enum pmc_event ev; - struct ucp_event_descr *ie; - uint32_t caps, config, cpuflag, evsel; + uint8_t ev; + uint32_t caps; + const struct pmc_md_ucp_op_pmcallocate *ucp; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucp_npmc, ("[uncore,%d] illegal row-index value %d", __LINE__, ri)); /* check requested capabilities */ caps = a->pm_caps; if ((UCP_PMC_CAPS & caps) != caps) return (EPERM); - ev = pm->pm_event; - + ucp = &a->pm_md.pm_ucp; + ev = UCP_EVSEL(ucp->pm_ucp_config); switch (uncore_cputype) { case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_SANDYBRIDGE: if (ucp_event_sb_hw_ok_on_counter(ev, ri) == 0) return (EINVAL); break; default: break; } - - /* - * Look for an event descriptor with matching CPU and event id - * fields. - */ - - switch (uncore_cputype) { - case PMC_CPU_INTEL_COREI7: - cpuflag = UCP_F_I7; - break; - case PMC_CPU_INTEL_HASWELL: - cpuflag = UCP_F_HW; - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - cpuflag = UCP_F_SB; - break; - case PMC_CPU_INTEL_WESTMERE: - cpuflag = UCP_F_WM; - break; - default: - return (EINVAL); - } - - for (n = 0, ie = ucp_events; n < nitems(ucp_events); n++, ie++) - if (ie->ucp_ev == ev && ie->ucp_flags & cpuflag) - break; - - if (n == nitems(ucp_events)) - return (EINVAL); - - /* - * A matching event descriptor has been found, so start - * assembling the contents of the event select register. - */ - evsel = ie->ucp_evcode | UCP_EN; - - config = a->pm_md.pm_ucp.pm_ucp_config & ~UCP_F_CMASK; - - /* - * If the event uses a fixed umask value, reject any umask - * bits set by the user. - */ - if (ie->ucp_flags & UCP_F_FM) { - - if (UCP_UMASK(config) != 0) - return (EINVAL); - - evsel |= (ie->ucp_umask << 8); - - } else - return (EINVAL); - - if (caps & PMC_CAP_THRESHOLD) - evsel |= (a->pm_md.pm_ucp.pm_ucp_config & UCP_F_CMASK); - if (caps & PMC_CAP_EDGE) - evsel |= UCP_EDGE; - if (caps & PMC_CAP_INVERT) - evsel |= UCP_INV; - - pm->pm_md.pm_ucp.pm_ucp_evsel = evsel; + pm->pm_md.pm_ucp.pm_ucp_evsel = ucp->pm_ucp_config | UCP_EN; return (0); } static int ucp_config_pmc(int cpu, int ri, struct pmc *pm) { KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucp_npmc, ("[uncore,%d] illegal row-index %d", __LINE__, ri)); PMCDBG3(MDP,CFG,1, "ucp-config cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__, cpu)); uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc = pm; return (0); } static int ucp_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) { int error; struct pmc_hw *phw; char ucp_name[PMC_NAME_MAX]; phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri]; (void) snprintf(ucp_name, sizeof(ucp_name), "UCP-%d", ri); if ((error = copystr(ucp_name, pi->pm_name, PMC_NAME_MAX, NULL)) != 0) return (error); pi->pm_class = PMC_CLASS_UCP; if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { pi->pm_enabled = TRUE; *ppmc = phw->phw_pmc; } else { pi->pm_enabled = FALSE; *ppmc = NULL; } return (0); } static int ucp_get_config(int cpu, int ri, struct pmc **ppm) { *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc; return (0); } static int ucp_read_pmc(int cpu, int ri, pmc_value_t *v) { struct pmc *pm; pmc_value_t tmp; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucp_npmc, ("[uncore,%d] illegal row-index %d", __LINE__, ri)); pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc; KASSERT(pm, ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); tmp = rdmsr(UCP_PMC0 + ri); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) *v = ucp_perfctr_value_to_reload_count(tmp); else *v = tmp; PMCDBG4(MDP,REA,1, "ucp-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, ri, *v); return (0); } static int ucp_release_pmc(int cpu, int ri, struct pmc *pm) { (void) pm; PMCDBG3(MDP,REL,1, "ucp-release cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucp_npmc, ("[uncore,%d] illegal row-index %d", __LINE__, ri)); KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc == NULL, ("[uncore,%d] PHW pmc non-NULL", __LINE__)); return (0); } static int ucp_start_pmc(int cpu, int ri) { struct pmc *pm; uint32_t evsel; struct uncore_cpu *cc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucp_npmc, ("[uncore,%d] illegal row-index %d", __LINE__, ri)); cc = uncore_pcpu[cpu]; pm = cc->pc_uncorepmcs[ri].phw_pmc; KASSERT(pm, ("[uncore,%d] starting cpu%d,ri%d with no pmc configured", __LINE__, cpu, ri)); PMCDBG2(MDP,STA,1, "ucp-start cpu=%d ri=%d", cpu, ri); evsel = pm->pm_md.pm_ucp.pm_ucp_evsel; PMCDBG4(MDP,STA,2, "ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", cpu, ri, SELECTSEL(uncore_cputype) + ri, evsel); /* Event specific configuration. */ switch (pm->pm_event) { case PMC_EV_UCP_EVENT_0CH_04H_E: case PMC_EV_UCP_EVENT_0CH_08H_E: wrmsr(MSR_GQ_SNOOP_MESF,0x2); break; case PMC_EV_UCP_EVENT_0CH_04H_F: case PMC_EV_UCP_EVENT_0CH_08H_F: wrmsr(MSR_GQ_SNOOP_MESF,0x8); break; case PMC_EV_UCP_EVENT_0CH_04H_M: case PMC_EV_UCP_EVENT_0CH_08H_M: wrmsr(MSR_GQ_SNOOP_MESF,0x1); break; case PMC_EV_UCP_EVENT_0CH_04H_S: case PMC_EV_UCP_EVENT_0CH_08H_S: wrmsr(MSR_GQ_SNOOP_MESF,0x4); break; default: break; } - wrmsr(SELECTSEL(uncore_cputype) + ri, evsel); do { cc->pc_resync = 0; cc->pc_globalctrl |= (1ULL << ri); wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl); } while (cc->pc_resync != 0); return (0); } static int ucp_stop_pmc(int cpu, int ri) { struct pmc *pm; struct uncore_cpu *cc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucp_npmc, ("[uncore,%d] illegal row index %d", __LINE__, ri)); cc = uncore_pcpu[cpu]; pm = cc->pc_uncorepmcs[ri].phw_pmc; KASSERT(pm, ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__, cpu, ri)); PMCDBG2(MDP,STO,1, "ucp-stop cpu=%d ri=%d", cpu, ri); /* stop hw. */ wrmsr(SELECTSEL(uncore_cputype) + ri, 0); do { cc->pc_resync = 0; cc->pc_globalctrl &= ~(1ULL << ri); wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl); } while (cc->pc_resync != 0); return (0); } static int ucp_write_pmc(int cpu, int ri, pmc_value_t v) { struct pmc *pm; struct uncore_cpu *cc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < uncore_ucp_npmc, ("[uncore,%d] illegal row index %d", __LINE__, ri)); cc = uncore_pcpu[cpu]; pm = cc->pc_uncorepmcs[ri].phw_pmc; KASSERT(pm, ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__, cpu, ri)); PMCDBG4(MDP,WRI,1, "ucp-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, UCP_PMC0 + ri, v); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) v = ucp_reload_count_to_perfctr_value(v); /* * Write the new value to the counter. The counter will be in * a stopped state when the pcd_write() entry point is called. */ wrmsr(UCP_PMC0 + ri, v); return (0); } static void ucp_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) { struct pmc_classdep *pcd; KASSERT(md != NULL, ("[ucp,%d] md is NULL", __LINE__)); PMCDBG0(MDP,INI,1, "ucp-initialize"); pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP]; pcd->pcd_caps = UCP_PMC_CAPS; pcd->pcd_class = PMC_CLASS_UCP; pcd->pcd_num = npmc; pcd->pcd_ri = md->pmd_npmc; pcd->pcd_width = pmcwidth; pcd->pcd_allocate_pmc = ucp_allocate_pmc; pcd->pcd_config_pmc = ucp_config_pmc; pcd->pcd_describe = ucp_describe; pcd->pcd_get_config = ucp_get_config; pcd->pcd_get_msr = NULL; pcd->pcd_pcpu_fini = uncore_pcpu_fini; pcd->pcd_pcpu_init = uncore_pcpu_init; pcd->pcd_read_pmc = ucp_read_pmc; pcd->pcd_release_pmc = ucp_release_pmc; pcd->pcd_start_pmc = ucp_start_pmc; pcd->pcd_stop_pmc = ucp_stop_pmc; pcd->pcd_write_pmc = ucp_write_pmc; md->pmd_npmc += npmc; } int pmc_uncore_initialize(struct pmc_mdep *md, int maxcpu) { uncore_cputype = md->pmd_cputype; uncore_pmcmask = 0; /* * Initialize programmable counters. */ uncore_ucp_npmc = 8; uncore_ucp_width = 48; uncore_pmcmask |= ((1ULL << uncore_ucp_npmc) - 1); ucp_initialize(md, maxcpu, uncore_ucp_npmc, uncore_ucp_width); /* * Initialize fixed function counters, if present. */ uncore_ucf_ri = uncore_ucp_npmc; uncore_ucf_npmc = 1; uncore_ucf_width = 48; ucf_initialize(md, maxcpu, uncore_ucf_npmc, uncore_ucf_width); uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << SELECTOFF(uncore_cputype); PMCDBG2(MDP,INI,1,"uncore-init pmcmask=0x%jx ucfri=%d", uncore_pmcmask, uncore_ucf_ri); uncore_pcpu = malloc(sizeof(*uncore_pcpu) * maxcpu, M_PMC, M_ZERO | M_WAITOK); return (0); } void pmc_uncore_finalize(struct pmc_mdep *md) { PMCDBG0(MDP,INI,1, "uncore-finalize"); free(uncore_pcpu, M_PMC); uncore_pcpu = NULL; } diff --git a/sys/dev/hwpmc/hwpmc_uncore.h b/sys/dev/hwpmc/hwpmc_uncore.h index 64bf650dd5bc..ac1623e7737e 100644 --- a/sys/dev/hwpmc/hwpmc_uncore.h +++ b/sys/dev/hwpmc/hwpmc_uncore.h @@ -1,128 +1,127 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2010 Fabien Thomas * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV_HWPMC_UNCORE_H_ #define _DEV_HWPMC_UNCORE_H_ 1 /* * Fixed-function PMCs. */ struct pmc_md_ucf_op_pmcallocate { uint16_t pm_ucf_flags; /* additional flags */ }; #define UCF_EN 0x1 #define UCF_PMI 0x4 /* * Programmable PMCs. */ struct pmc_md_ucp_op_pmcallocate { uint32_t pm_ucp_config; }; #define UCP_EVSEL(C) ((C) & 0xFF) #define UCP_UMASK(C) ((C) & 0xFF00) #define UCP_CTRR (1 << 17) #define UCP_EDGE (1 << 18) #define UCP_INT (1 << 20) #define UCP_EN (1 << 22) #define UCP_INV (1 << 23) #define UCP_CMASK(C) (((C) & 0xFF) << 24) - #ifdef _KERNEL #define DCTL_FLAG_UNC_PMI (1ULL << 13) /* * Fixed-function counters. */ #define UCF_MASK 0xF #define UCF_CTR0 0x394 #define UCF_OFFSET 32 #define UCF_OFFSET_SB 29 #define UCF_CTRL 0x395 /* * Programmable counters. */ #define UCP_PMC0 0x3B0 #define UCP_EVSEL0 0x3C0 #define UCP_OPCODE_MATCH 0x396 #define UCP_CB0_EVSEL0 0x700 /* * Simplified programming interface in Intel Performance Architecture * v2 and later. */ #define UC_GLOBAL_STATUS 0x392 #define UC_GLOBAL_CTRL 0x391 #define UC_GLOBAL_OVF_CTRL 0x393 #define UC_GLOBAL_STATUS_FLAG_CLRCHG (1ULL << 63) #define UC_GLOBAL_STATUS_FLAG_OVFPMI (1ULL << 61) #define UC_GLOBAL_CTRL_FLAG_FRZ (1ULL << 63) #define UC_GLOBAL_CTRL_FLAG_ENPMICORE0 (1ULL << 48) /* * Model specific registers. */ #define MSR_GQ_SNOOP_MESF 0x301 struct pmc_md_ucf_pmc { uint64_t pm_ucf_ctrl; }; struct pmc_md_ucp_pmc { uint32_t pm_ucp_evsel; }; /* * Prototypes. */ int pmc_uncore_initialize(struct pmc_mdep *_md, int _maxcpu); void pmc_uncore_finalize(struct pmc_mdep *_md); int pmc_ucf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width); void pmc_ucf_finalize(struct pmc_mdep *_md); int pmc_ucp_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width, int _flags); void pmc_ucp_finalize(struct pmc_mdep *_md); #endif /* _KERNEL */ #endif /* _DEV_HWPMC_UNCORE_H */ diff --git a/sys/dev/hwpmc/pmc_events.h b/sys/dev/hwpmc/pmc_events.h index 213d311cf472..99aca46fa5f5 100644 --- a/sys/dev/hwpmc/pmc_events.h +++ b/sys/dev/hwpmc/pmc_events.h @@ -1,7205 +1,1817 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2005 Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV_HWPMC_PMC_EVENTS_H_ #define _DEV_HWPMC_PMC_EVENTS_H_ /* * Note: Documentation on adding events can be found both in * the source tree at src/share/doc/papers/hwpmc/hwpmc.ms * as well as on-line at: * * http://wiki.freebsd.org/PmcTools/PmcHardwareHowTo * * Please refer to those resources before you attempt to modify * this file or the hwpmc driver/subsystem. */ /* * PMC event codes. * * __PMC_EV(CLASS, SYMBOLIC-NAME) * */ +/* timestamp counters. */ +#define __PMC_EV_TSC() \ + __PMC_EV(TSC, TSC) + +#define PMC_EV_TSC_FIRST PMC_EV_TSC_TSC +#define PMC_EV_TSC_LAST PMC_EV_TSC_TSC + +/* + * Software events are dynamically defined. + */ + +#define PMC_EV_DYN_COUNT 0x1000 + +#define PMC_EV_SOFT_FIRST 0x20000 +#define PMC_EV_SOFT_LAST (PMC_EV_SOFT_FIRST + PMC_EV_DYN_COUNT - 1) /* * AMD K7 Events, from "The AMD Athlon(tm) Processor x86 Code * Optimization Guide" [Doc#22007K, Feb 2002] */ #define __PMC_EV_K7() \ __PMC_EV(K7, DC_ACCESSES) \ __PMC_EV(K7, DC_MISSES) \ __PMC_EV(K7, DC_REFILLS_FROM_L2) \ __PMC_EV(K7, DC_REFILLS_FROM_SYSTEM) \ __PMC_EV(K7, DC_WRITEBACKS) \ __PMC_EV(K7, L1_DTLB_MISS_AND_L2_DTLB_HITS) \ __PMC_EV(K7, L1_AND_L2_DTLB_MISSES) \ __PMC_EV(K7, MISALIGNED_REFERENCES) \ __PMC_EV(K7, IC_FETCHES) \ __PMC_EV(K7, IC_MISSES) \ __PMC_EV(K7, L1_ITLB_MISSES) \ __PMC_EV(K7, L1_L2_ITLB_MISSES) \ __PMC_EV(K7, RETIRED_INSTRUCTIONS) \ __PMC_EV(K7, RETIRED_OPS) \ __PMC_EV(K7, RETIRED_BRANCHES) \ __PMC_EV(K7, RETIRED_BRANCHES_MISPREDICTED) \ __PMC_EV(K7, RETIRED_TAKEN_BRANCHES) \ __PMC_EV(K7, RETIRED_TAKEN_BRANCHES_MISPREDICTED) \ __PMC_EV(K7, RETIRED_FAR_CONTROL_TRANSFERS) \ __PMC_EV(K7, RETIRED_RESYNC_BRANCHES) \ __PMC_EV(K7, INTERRUPTS_MASKED_CYCLES) \ __PMC_EV(K7, INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \ __PMC_EV(K7, HARDWARE_INTERRUPTS) #define PMC_EV_K7_FIRST PMC_EV_K7_DC_ACCESSES #define PMC_EV_K7_LAST PMC_EV_K7_HARDWARE_INTERRUPTS - -/* - * Intel P4 Events, from "IA-32 Intel(r) Architecture Software - * Developer's Manual, Volume 3: System Programming Guide" [245472-012] - */ - -#define __PMC_EV_P4() \ -__PMC_EV(P4, TC_DELIVER_MODE) \ -__PMC_EV(P4, BPU_FETCH_REQUEST) \ -__PMC_EV(P4, ITLB_REFERENCE) \ -__PMC_EV(P4, MEMORY_CANCEL) \ -__PMC_EV(P4, MEMORY_COMPLETE) \ -__PMC_EV(P4, LOAD_PORT_REPLAY) \ -__PMC_EV(P4, STORE_PORT_REPLAY) \ -__PMC_EV(P4, MOB_LOAD_REPLAY) \ -__PMC_EV(P4, PAGE_WALK_TYPE) \ -__PMC_EV(P4, BSQ_CACHE_REFERENCE) \ -__PMC_EV(P4, IOQ_ALLOCATION) \ -__PMC_EV(P4, IOQ_ACTIVE_ENTRIES) \ -__PMC_EV(P4, FSB_DATA_ACTIVITY) \ -__PMC_EV(P4, BSQ_ALLOCATION) \ -__PMC_EV(P4, BSQ_ACTIVE_ENTRIES) \ -__PMC_EV(P4, SSE_INPUT_ASSIST) \ -__PMC_EV(P4, PACKED_SP_UOP) \ -__PMC_EV(P4, PACKED_DP_UOP) \ -__PMC_EV(P4, SCALAR_SP_UOP) \ -__PMC_EV(P4, SCALAR_DP_UOP) \ -__PMC_EV(P4, 64BIT_MMX_UOP) \ -__PMC_EV(P4, 128BIT_MMX_UOP) \ -__PMC_EV(P4, X87_FP_UOP) \ -__PMC_EV(P4, X87_SIMD_MOVES_UOP) \ -__PMC_EV(P4, GLOBAL_POWER_EVENTS) \ -__PMC_EV(P4, TC_MS_XFER) \ -__PMC_EV(P4, UOP_QUEUE_WRITES) \ -__PMC_EV(P4, RETIRED_MISPRED_BRANCH_TYPE) \ -__PMC_EV(P4, RETIRED_BRANCH_TYPE) \ -__PMC_EV(P4, RESOURCE_STALL) \ -__PMC_EV(P4, WC_BUFFER) \ -__PMC_EV(P4, B2B_CYCLES) \ -__PMC_EV(P4, BNR) \ -__PMC_EV(P4, SNOOP) \ -__PMC_EV(P4, RESPONSE) \ -__PMC_EV(P4, FRONT_END_EVENT) \ -__PMC_EV(P4, EXECUTION_EVENT) \ -__PMC_EV(P4, REPLAY_EVENT) \ -__PMC_EV(P4, INSTR_RETIRED) \ -__PMC_EV(P4, UOPS_RETIRED) \ -__PMC_EV(P4, UOP_TYPE) \ -__PMC_EV(P4, BRANCH_RETIRED) \ -__PMC_EV(P4, MISPRED_BRANCH_RETIRED) \ -__PMC_EV(P4, X87_ASSIST) \ -__PMC_EV(P4, MACHINE_CLEAR) - -#define PMC_EV_P4_FIRST PMC_EV_P4_TC_DELIVER_MODE -#define PMC_EV_P4_LAST PMC_EV_P4_MACHINE_CLEAR - -/* Intel Pentium Pro, P-II, P-III and Pentium-M style events */ - -#define __PMC_EV_P6() \ -__PMC_EV(P6, DATA_MEM_REFS) \ -__PMC_EV(P6, DCU_LINES_IN) \ -__PMC_EV(P6, DCU_M_LINES_IN) \ -__PMC_EV(P6, DCU_M_LINES_OUT) \ -__PMC_EV(P6, DCU_MISS_OUTSTANDING) \ -__PMC_EV(P6, IFU_FETCH) \ -__PMC_EV(P6, IFU_FETCH_MISS) \ -__PMC_EV(P6, ITLB_MISS) \ -__PMC_EV(P6, IFU_MEM_STALL) \ -__PMC_EV(P6, ILD_STALL) \ -__PMC_EV(P6, L2_IFETCH) \ -__PMC_EV(P6, L2_LD) \ -__PMC_EV(P6, L2_ST) \ -__PMC_EV(P6, L2_LINES_IN) \ -__PMC_EV(P6, L2_LINES_OUT) \ -__PMC_EV(P6, L2_M_LINES_INM) \ -__PMC_EV(P6, L2_M_LINES_OUTM) \ -__PMC_EV(P6, L2_RQSTS) \ -__PMC_EV(P6, L2_ADS) \ -__PMC_EV(P6, L2_DBUS_BUSY) \ -__PMC_EV(P6, L2_DBUS_BUSY_RD) \ -__PMC_EV(P6, BUS_DRDY_CLOCKS) \ -__PMC_EV(P6, BUS_LOCK_CLOCKS) \ -__PMC_EV(P6, BUS_REQ_OUTSTANDING) \ -__PMC_EV(P6, BUS_TRAN_BRD) \ -__PMC_EV(P6, BUS_TRAN_RFO) \ -__PMC_EV(P6, BUS_TRANS_WB) \ -__PMC_EV(P6, BUS_TRAN_IFETCH) \ -__PMC_EV(P6, BUS_TRAN_INVAL) \ -__PMC_EV(P6, BUS_TRAN_PWR) \ -__PMC_EV(P6, BUS_TRANS_P) \ -__PMC_EV(P6, BUS_TRANS_IO) \ -__PMC_EV(P6, BUS_TRAN_DEF) \ -__PMC_EV(P6, BUS_TRAN_BURST) \ -__PMC_EV(P6, BUS_TRAN_ANY) \ -__PMC_EV(P6, BUS_TRAN_MEM) \ -__PMC_EV(P6, BUS_DATA_RCV) \ -__PMC_EV(P6, BUS_BNR_DRV) \ -__PMC_EV(P6, BUS_HIT_DRV) \ -__PMC_EV(P6, BUS_HITM_DRV) \ -__PMC_EV(P6, BUS_SNOOP_STALL) \ -__PMC_EV(P6, FLOPS) \ -__PMC_EV(P6, FP_COMPS_OPS_EXE) \ -__PMC_EV(P6, FP_ASSIST) \ -__PMC_EV(P6, MUL) \ -__PMC_EV(P6, DIV) \ -__PMC_EV(P6, CYCLES_DIV_BUSY) \ -__PMC_EV(P6, LD_BLOCKS) \ -__PMC_EV(P6, SB_DRAINS) \ -__PMC_EV(P6, MISALIGN_MEM_REF) \ -__PMC_EV(P6, EMON_KNI_PREF_DISPATCHED) \ -__PMC_EV(P6, EMON_KNI_PREF_MISS) \ -__PMC_EV(P6, INST_RETIRED) \ -__PMC_EV(P6, UOPS_RETIRED) \ -__PMC_EV(P6, INST_DECODED) \ -__PMC_EV(P6, EMON_KNI_INST_RETIRED) \ -__PMC_EV(P6, EMON_KNI_COMP_INST_RET) \ -__PMC_EV(P6, HW_INT_RX) \ -__PMC_EV(P6, CYCLES_INT_MASKED) \ -__PMC_EV(P6, CYCLES_INT_PENDING_AND_MASKED) \ -__PMC_EV(P6, BR_INST_RETIRED) \ -__PMC_EV(P6, BR_MISS_PRED_RETIRED) \ -__PMC_EV(P6, BR_TAKEN_RETIRED) \ -__PMC_EV(P6, BR_MISS_PRED_TAKEN_RET) \ -__PMC_EV(P6, BR_INST_DECODED) \ -__PMC_EV(P6, BTB_MISSES) \ -__PMC_EV(P6, BR_BOGUS) \ -__PMC_EV(P6, BACLEARS) \ -__PMC_EV(P6, RESOURCE_STALLS) \ -__PMC_EV(P6, PARTIAL_RAT_STALLS) \ -__PMC_EV(P6, SEGMENT_REG_LOADS) \ -__PMC_EV(P6, CPU_CLK_UNHALTED) \ -__PMC_EV(P6, MMX_INSTR_EXEC) \ -__PMC_EV(P6, MMX_SAT_INSTR_EXEC) \ -__PMC_EV(P6, MMX_UOPS_EXEC) \ -__PMC_EV(P6, MMX_INSTR_TYPE_EXEC) \ -__PMC_EV(P6, FP_MMX_TRANS) \ -__PMC_EV(P6, MMX_ASSIST) \ -__PMC_EV(P6, MMX_INSTR_RET) \ -__PMC_EV(P6, SEG_RENAME_STALLS) \ -__PMC_EV(P6, SEG_REG_RENAMES) \ -__PMC_EV(P6, RET_SEG_RENAMES) \ -__PMC_EV(P6, EMON_EST_TRANS) \ -__PMC_EV(P6, EMON_THERMAL_TRIP) \ -__PMC_EV(P6, BR_INST_EXEC) \ -__PMC_EV(P6, BR_MISSP_EXEC) \ -__PMC_EV(P6, BR_BAC_MISSP_EXEC) \ -__PMC_EV(P6, BR_CND_EXEC) \ -__PMC_EV(P6, BR_CND_MISSP_EXEC) \ -__PMC_EV(P6, BR_IND_EXEC) \ -__PMC_EV(P6, BR_IND_MISSP_EXEC) \ -__PMC_EV(P6, BR_RET_EXEC) \ -__PMC_EV(P6, BR_RET_MISSP_EXEC) \ -__PMC_EV(P6, BR_RET_BAC_MISSP_EXEC) \ -__PMC_EV(P6, BR_CALL_EXEC) \ -__PMC_EV(P6, BR_CALL_MISSP_EXEC) \ -__PMC_EV(P6, BR_IND_CALL_EXEC) \ -__PMC_EV(P6, EMON_SIMD_INSTR_RETIRED) \ -__PMC_EV(P6, EMON_SYNCH_UOPS) \ -__PMC_EV(P6, EMON_ESP_UOPS) \ -__PMC_EV(P6, EMON_FUSED_UOPS_RET) \ -__PMC_EV(P6, EMON_UNFUSION) \ -__PMC_EV(P6, EMON_PREF_RQSTS_UP) \ -__PMC_EV(P6, EMON_PREF_RQSTS_DN) \ -__PMC_EV(P6, EMON_SSE_SSE2_INST_RETIRED) \ -__PMC_EV(P6, EMON_SSE_SSE2_COMP_INST_RETIRED) - - -#define PMC_EV_P6_FIRST PMC_EV_P6_DATA_MEM_REFS -#define PMC_EV_P6_LAST PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED - /* AMD K8 PMCs */ #define __PMC_EV_K8() \ __PMC_EV(K8, FP_DISPATCHED_FPU_OPS) \ __PMC_EV(K8, FP_CYCLES_WITH_NO_FPU_OPS_RETIRED) \ __PMC_EV(K8, FP_DISPATCHED_FPU_FAST_FLAG_OPS) \ __PMC_EV(K8, LS_SEGMENT_REGISTER_LOAD) \ __PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE) \ __PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP) \ __PMC_EV(K8, LS_BUFFER2_FULL) \ __PMC_EV(K8, LS_LOCKED_OPERATION) \ __PMC_EV(K8, LS_MICROARCHITECTURAL_LATE_CANCEL) \ __PMC_EV(K8, LS_RETIRED_CFLUSH_INSTRUCTIONS) \ __PMC_EV(K8, LS_RETIRED_CPUID_INSTRUCTIONS) \ __PMC_EV(K8, DC_ACCESS) \ __PMC_EV(K8, DC_MISS) \ __PMC_EV(K8, DC_REFILL_FROM_L2) \ __PMC_EV(K8, DC_REFILL_FROM_SYSTEM) \ __PMC_EV(K8, DC_COPYBACK) \ __PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_HIT) \ __PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_MISS) \ __PMC_EV(K8, DC_MISALIGNED_DATA_REFERENCE) \ __PMC_EV(K8, DC_MICROARCHITECTURAL_LATE_CANCEL) \ __PMC_EV(K8, DC_MICROARCHITECTURAL_EARLY_CANCEL) \ __PMC_EV(K8, DC_ONE_BIT_ECC_ERROR) \ __PMC_EV(K8, DC_DISPATCHED_PREFETCH_INSTRUCTIONS) \ __PMC_EV(K8, DC_DCACHE_ACCESSES_BY_LOCKS) \ __PMC_EV(K8, BU_CPU_CLK_UNHALTED) \ __PMC_EV(K8, BU_INTERNAL_L2_REQUEST) \ __PMC_EV(K8, BU_FILL_REQUEST_L2_MISS) \ __PMC_EV(K8, BU_FILL_INTO_L2) \ __PMC_EV(K8, IC_FETCH) \ __PMC_EV(K8, IC_MISS) \ __PMC_EV(K8, IC_REFILL_FROM_L2) \ __PMC_EV(K8, IC_REFILL_FROM_SYSTEM) \ __PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_HIT) \ __PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_MISS) \ __PMC_EV(K8, IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP) \ __PMC_EV(K8, IC_INSTRUCTION_FETCH_STALL) \ __PMC_EV(K8, IC_RETURN_STACK_HIT) \ __PMC_EV(K8, IC_RETURN_STACK_OVERFLOW) \ __PMC_EV(K8, FR_RETIRED_X86_INSTRUCTIONS) \ __PMC_EV(K8, FR_RETIRED_UOPS) \ __PMC_EV(K8, FR_RETIRED_BRANCHES) \ __PMC_EV(K8, FR_RETIRED_BRANCHES_MISPREDICTED) \ __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES) \ __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED) \ __PMC_EV(K8, FR_RETIRED_FAR_CONTROL_TRANSFERS) \ __PMC_EV(K8, FR_RETIRED_RESYNCS) \ __PMC_EV(K8, FR_RETIRED_NEAR_RETURNS) \ __PMC_EV(K8, FR_RETIRED_NEAR_RETURNS_MISPREDICTED) \ __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE) \ __PMC_EV(K8, FR_RETIRED_FPU_INSTRUCTIONS) \ __PMC_EV(K8, FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS) \ __PMC_EV(K8, FR_INTERRUPTS_MASKED_CYCLES) \ __PMC_EV(K8, FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \ __PMC_EV(K8, FR_TAKEN_HARDWARE_INTERRUPTS) \ __PMC_EV(K8, FR_DECODER_EMPTY) \ __PMC_EV(K8, FR_DISPATCH_STALLS) \ __PMC_EV(K8, FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE) \ __PMC_EV(K8, FR_DISPATCH_STALL_FOR_SERIALIZATION) \ __PMC_EV(K8, FR_DISPATCH_STALL_FOR_SEGMENT_LOAD) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FPU_IS_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_LS_IS_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING) \ __PMC_EV(K8, FR_FPU_EXCEPTIONS) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR0) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR1) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR2) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR3) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_TURNAROUND) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_BYPASS_SATURATION) \ __PMC_EV(K8, NB_SIZED_COMMANDS) \ __PMC_EV(K8, NB_PROBE_RESULT) \ __PMC_EV(K8, NB_HT_BUS0_BANDWIDTH) \ __PMC_EV(K8, NB_HT_BUS1_BANDWIDTH) \ __PMC_EV(K8, NB_HT_BUS2_BANDWIDTH) #define PMC_EV_K8_FIRST PMC_EV_K8_FP_DISPATCHED_FPU_OPS #define PMC_EV_K8_LAST PMC_EV_K8_NB_HT_BUS2_BANDWIDTH - -/* - * Intel Pentium and Pentium MMX events, from the "Intel 64 and IA-32 - * Architectures Software Developer's Manual, Volume 3B: System Programming - * Guide, Part 2, August 2007". - */ -#define __PMC_EV_P5() \ -__PMC_EV(P5, DATA_READ) \ -__PMC_EV(P5, DATA_WRITE) \ -__PMC_EV(P5, DATA_TLB_MISS) \ -__PMC_EV(P5, DATA_READ_MISS) \ -__PMC_EV(P5, DATA_WRITE_MISS) \ -__PMC_EV(P5, WRITE_HIT_TO_M_OR_E_STATE_LINES) \ -__PMC_EV(P5, DATA_CACHE_LINES_WRITTEN_BACK) \ -__PMC_EV(P5, EXTERNAL_SNOOPS) \ -__PMC_EV(P5, EXTERNAL_DATA_CACHE_SNOOP_HITS) \ -__PMC_EV(P5, MEMORY_ACCESSES_IN_BOTH_PIPES) \ -__PMC_EV(P5, BANK_CONFLICTS) \ -__PMC_EV(P5, MISALIGNED_DATA_OR_IO_REFERENCES) \ -__PMC_EV(P5, CODE_READ) \ -__PMC_EV(P5, CODE_TLB_MISS) \ -__PMC_EV(P5, CODE_CACHE_MISS) \ -__PMC_EV(P5, ANY_SEGMENT_REGISTER_LOADED) \ -__PMC_EV(P5, BRANCHES) \ -__PMC_EV(P5, BTB_HITS) \ -__PMC_EV(P5, TAKEN_BRANCH_OR_BTB_HIT) \ -__PMC_EV(P5, PIPELINE_FLUSHES) \ -__PMC_EV(P5, INSTRUCTIONS_EXECUTED) \ -__PMC_EV(P5, INSTRUCTIONS_EXECUTED_V_PIPE) \ -__PMC_EV(P5, BUS_CYCLE_DURATION) \ -__PMC_EV(P5, WRITE_BUFFER_FULL_STALL_DURATION) \ -__PMC_EV(P5, WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION) \ -__PMC_EV(P5, STALL_ON_WRITE_TO_AN_E_OR_M_STATE_LINE) \ -__PMC_EV(P5, LOCKED_BUS_CYCLE) \ -__PMC_EV(P5, IO_READ_OR_WRITE_CYCLE) \ -__PMC_EV(P5, NONCACHEABLE_MEMORY_READS) \ -__PMC_EV(P5, PIPELINE_AGI_STALLS) \ -__PMC_EV(P5, FLOPS) \ -__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR0_REGISTER) \ -__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR1_REGISTER) \ -__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR2_REGISTER) \ -__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR3_REGISTER) \ -__PMC_EV(P5, HARDWARE_INTERRUPTS) \ -__PMC_EV(P5, DATA_READ_OR_WRITE) \ -__PMC_EV(P5, DATA_READ_MISS_OR_WRITE_MISS) \ -__PMC_EV(P5, BUS_OWNERSHIP_LATENCY) \ -__PMC_EV(P5, BUS_OWNERSHIP_TRANSFERS) \ -__PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_U_PIPE) \ -__PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_V_PIPE) \ -__PMC_EV(P5, CACHE_M_LINE_SHARING) \ -__PMC_EV(P5, CACHE_LINE_SHARING) \ -__PMC_EV(P5, EMMS_INSTRUCTIONS_EXECUTED) \ -__PMC_EV(P5, TRANSITIONS_BETWEEN_MMX_AND_FP_INSTRUCTIONS) \ -__PMC_EV(P5, BUS_UTILIZATION_DUE_TO_PROCESSOR_ACTIVITY) \ -__PMC_EV(P5, WRITES_TO_NONCACHEABLE_MEMORY) \ -__PMC_EV(P5, SATURATING_MMX_INSTRUCTIONS_EXECUTED) \ -__PMC_EV(P5, SATURATIONS_PERFORMED) \ -__PMC_EV(P5, NUMBER_OF_CYCLES_NOT_IN_HALT_STATE) \ -__PMC_EV(P5, DATA_CACHE_TLB_MISS_STALL_DURATION) \ -__PMC_EV(P5, MMX_INSTRUCTION_DATA_READS) \ -__PMC_EV(P5, MMX_INSTRUCTION_DATA_READ_MISSES) \ -__PMC_EV(P5, FLOATING_POINT_STALLS_DURATION) \ -__PMC_EV(P5, TAKEN_BRANCHES) \ -__PMC_EV(P5, D1_STARVATION_AND_FIFO_IS_EMPTY) \ -__PMC_EV(P5, D1_STARVATION_AND_ONLY_ONE_INSTRUCTION_IN_FIFO) \ -__PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITES) \ -__PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITE_MISSES) \ -__PMC_EV(P5, PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS) \ -__PMC_EV(P5, \ - PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS_RESOLVED_IN_WB_STAGE) \ -__PMC_EV(P5, MISALIGNED_DATA_MEMORY_REFERENCE_ON_MMX_INSTRUCTIONS) \ -__PMC_EV(P5, PIPELINE_STALL_FOR_MMX_INSTRUCTION_DATA_MEMORY_READS) \ -__PMC_EV(P5, MISPREDICTED_OR_UNPREDICTED_RETURNS) \ -__PMC_EV(P5, PREDICTED_RETURNS) \ -__PMC_EV(P5, MMX_MULTIPLY_UNIT_INTERLOCK) \ -__PMC_EV(P5, MOVD_MOVQ_STORE_STALL_DUE_TO_PREVIOUS_MMX_OPERATION) \ -__PMC_EV(P5, RETURNS) \ -__PMC_EV(P5, BTB_FALSE_ENTRIES) \ -__PMC_EV(P5, BTB_MISS_PREDICTION_ON_NOT_TAKEN_BRANCH) \ -__PMC_EV(P5, \ - FULL_WRITE_BUFFER_STALL_DURATION_WHILE_EXECUTING_MMX_INSTRUCTIONS) \ -__PMC_EV(P5, STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE) - -#define PMC_EV_P5_FIRST PMC_EV_P5_DATA_READ -#define PMC_EV_P5_LAST \ - PMC_EV_P5_STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE - /* * Events supported by Intel architectural fixed function counters, * from the "Intel 64 and IA-32 Architectures Software Developer's * Manual Volume 3B: System Programming Guide, Part 2", July 2008. */ #define __PMC_EV_IAF() \ __PMC_EV(IAF, INSTR_RETIRED_ANY) \ __PMC_EV(IAF, CPU_CLK_UNHALTED_CORE) \ __PMC_EV(IAF, CPU_CLK_UNHALTED_REF) #define PMC_EV_IAF_FIRST PMC_EV_IAF_INSTR_RETIRED_ANY #define PMC_EV_IAF_LAST PMC_EV_IAF_CPU_CLK_UNHALTED_REF #define __PMC_EV_ALIAS_IAF() \ __PMC_EV_ALIAS("instruction-retired", IAF_INSTR_RETIRED_ANY) \ __PMC_EV_ALIAS("unhalted-core-cycles", IAF_CPU_CLK_UNHALTED_CORE) \ __PMC_EV_ALIAS("unhalted-reference-cycles", IAF_CPU_CLK_UNHALTED_REF) -/* - * Events supported by programmable function counters present in - * Intel Atom, Core and Core2 CPUs, from the "Intel 64 and IA-32 - * Architectures Software Developer's Manual Volume 3B: System Programming - * Guide, Part 2", July 2008. - * - * These PMCs select events with a combination of an event code and - * unit mask. Quirks that need to be taken care of include: - * - The set of (event code, umask) combinations supported by a processor - * varies according to the processor model. - * - A given (event code, umask) combination need not measure the same - * hardware event in all processor models. - * - Event names in vendor documentation for an (event code, umask) pair - * may vary according to the CPU model. - * - Identically named events can map to different (event code, umask) - * pairs on different CPUs. - * - New (event code, umask) combinations continue to be added as CPUs - * evolve. The interface between hwpmc(4) and libpmc(3) needs to be - * robust with respect to ABI changes. - * - * The IAP_EVENT_* symbols below define the ABI between userland and kernel. - * New (event code, * umask) combinations used in new CPUs would be added - * to the end of the list. Vendor names for events are mapped to IAP_EVENT_* - * symbols using aliases. The final disambiguation of semantics based on - * the CPU model happens inside hwpmc(4). - */ -#define __PMC_EV_IAP() \ -__PMC_EV(IAP, ARCH_BR_INS_RET) \ -__PMC_EV(IAP, ARCH_BR_MIS_RET) \ -__PMC_EV(IAP, ARCH_INS_RET) \ -__PMC_EV(IAP, ARCH_LLC_MIS) \ -__PMC_EV(IAP, ARCH_LLC_REF) \ -__PMC_EV(IAP, ARCH_UNH_REF_CYC) \ -__PMC_EV(IAP, ARCH_UNH_COR_CYC) \ -__PMC_EV(IAP, EVENT_02H_01H) \ -__PMC_EV(IAP, EVENT_02H_81H) \ -__PMC_EV(IAP, EVENT_03H_00H) \ -__PMC_EV(IAP, EVENT_03H_01H) \ -__PMC_EV(IAP, EVENT_03H_02H) \ -__PMC_EV(IAP, EVENT_03H_04H) \ -__PMC_EV(IAP, EVENT_03H_08H) \ -__PMC_EV(IAP, EVENT_03H_10H) \ -__PMC_EV(IAP, EVENT_03H_20H) \ -__PMC_EV(IAP, EVENT_03H_40H) \ -__PMC_EV(IAP, EVENT_03H_80H) \ -__PMC_EV(IAP, EVENT_04H_00H) \ -__PMC_EV(IAP, EVENT_04H_01H) \ -__PMC_EV(IAP, EVENT_04H_02H) \ -__PMC_EV(IAP, EVENT_04H_04H) \ -__PMC_EV(IAP, EVENT_04H_07H) \ -__PMC_EV(IAP, EVENT_04H_08H) \ -__PMC_EV(IAP, EVENT_04H_10H) \ -__PMC_EV(IAP, EVENT_04H_20H) \ -__PMC_EV(IAP, EVENT_04H_40H) \ -__PMC_EV(IAP, EVENT_04H_80H) \ -__PMC_EV(IAP, EVENT_05H_00H) \ -__PMC_EV(IAP, EVENT_05H_01H) \ -__PMC_EV(IAP, EVENT_05H_02H) \ -__PMC_EV(IAP, EVENT_05H_03H) \ -__PMC_EV(IAP, EVENT_06H_00H) \ -__PMC_EV(IAP, EVENT_06H_01H) \ -__PMC_EV(IAP, EVENT_06H_02H) \ -__PMC_EV(IAP, EVENT_06H_04H) \ -__PMC_EV(IAP, EVENT_06H_08H) \ -__PMC_EV(IAP, EVENT_06H_0FH) \ -__PMC_EV(IAP, EVENT_07H_00H) \ -__PMC_EV(IAP, EVENT_07H_01H) \ -__PMC_EV(IAP, EVENT_07H_02H) \ -__PMC_EV(IAP, EVENT_07H_03H) \ -__PMC_EV(IAP, EVENT_07H_06H) \ -__PMC_EV(IAP, EVENT_07H_08H) \ -__PMC_EV(IAP, EVENT_08H_01H) \ -__PMC_EV(IAP, EVENT_08H_02H) \ -__PMC_EV(IAP, EVENT_08H_04H) \ -__PMC_EV(IAP, EVENT_08H_05H) \ -__PMC_EV(IAP, EVENT_08H_06H) \ -__PMC_EV(IAP, EVENT_08H_07H) \ -__PMC_EV(IAP, EVENT_08H_08H) \ -__PMC_EV(IAP, EVENT_08H_09H) \ -__PMC_EV(IAP, EVENT_08H_0EH) \ -__PMC_EV(IAP, EVENT_08H_10H) \ -__PMC_EV(IAP, EVENT_08H_20H) \ -__PMC_EV(IAP, EVENT_08H_40H) \ -__PMC_EV(IAP, EVENT_08H_60H) \ -__PMC_EV(IAP, EVENT_08H_80H) \ -__PMC_EV(IAP, EVENT_08H_81H) \ -__PMC_EV(IAP, EVENT_08H_82H) \ -__PMC_EV(IAP, EVENT_08H_84H) \ -__PMC_EV(IAP, EVENT_08H_88H) \ -__PMC_EV(IAP, EVENT_09H_01H) \ -__PMC_EV(IAP, EVENT_09H_02H) \ -__PMC_EV(IAP, EVENT_09H_04H) \ -__PMC_EV(IAP, EVENT_09H_08H) \ -__PMC_EV(IAP, EVENT_0BH_01H) \ -__PMC_EV(IAP, EVENT_0BH_02H) \ -__PMC_EV(IAP, EVENT_0BH_10H) \ -__PMC_EV(IAP, EVENT_0CH_01H) \ -__PMC_EV(IAP, EVENT_0CH_02H) \ -__PMC_EV(IAP, EVENT_0CH_03H) \ -__PMC_EV(IAP, EVENT_0DH_01H) \ -__PMC_EV(IAP, EVENT_0DH_03H) \ -__PMC_EV(IAP, EVENT_0DH_40H) \ -__PMC_EV(IAP, EVENT_0DH_80H) \ -__PMC_EV(IAP, EVENT_0EH_01H) \ -__PMC_EV(IAP, EVENT_0EH_02H) \ -__PMC_EV(IAP, EVENT_0EH_10H) \ -__PMC_EV(IAP, EVENT_0EH_20H) \ -__PMC_EV(IAP, EVENT_0EH_40H) \ -__PMC_EV(IAP, EVENT_0FH_01H) \ -__PMC_EV(IAP, EVENT_0FH_02H) \ -__PMC_EV(IAP, EVENT_0FH_08H) \ -__PMC_EV(IAP, EVENT_0FH_10H) \ -__PMC_EV(IAP, EVENT_0FH_20H) \ -__PMC_EV(IAP, EVENT_0FH_80H) \ -__PMC_EV(IAP, EVENT_10H_00H) \ -__PMC_EV(IAP, EVENT_10H_01H) \ -__PMC_EV(IAP, EVENT_10H_02H) \ -__PMC_EV(IAP, EVENT_10H_04H) \ -__PMC_EV(IAP, EVENT_10H_08H) \ -__PMC_EV(IAP, EVENT_10H_10H) \ -__PMC_EV(IAP, EVENT_10H_20H) \ -__PMC_EV(IAP, EVENT_10H_40H) \ -__PMC_EV(IAP, EVENT_10H_80H) \ -__PMC_EV(IAP, EVENT_10H_81H) \ -__PMC_EV(IAP, EVENT_11H_00H) \ -__PMC_EV(IAP, EVENT_11H_01H) \ -__PMC_EV(IAP, EVENT_11H_02H) \ -__PMC_EV(IAP, EVENT_11H_81H) \ -__PMC_EV(IAP, EVENT_12H_00H) \ -__PMC_EV(IAP, EVENT_12H_01H) \ -__PMC_EV(IAP, EVENT_12H_02H) \ -__PMC_EV(IAP, EVENT_12H_04H) \ -__PMC_EV(IAP, EVENT_12H_08H) \ -__PMC_EV(IAP, EVENT_12H_10H) \ -__PMC_EV(IAP, EVENT_12H_20H) \ -__PMC_EV(IAP, EVENT_12H_40H) \ -__PMC_EV(IAP, EVENT_12H_81H) \ -__PMC_EV(IAP, EVENT_13H_00H) \ -__PMC_EV(IAP, EVENT_13H_01H) \ -__PMC_EV(IAP, EVENT_13H_02H) \ -__PMC_EV(IAP, EVENT_13H_04H) \ -__PMC_EV(IAP, EVENT_13H_07H) \ -__PMC_EV(IAP, EVENT_13H_81H) \ -__PMC_EV(IAP, EVENT_14H_00H) \ -__PMC_EV(IAP, EVENT_14H_01H) \ -__PMC_EV(IAP, EVENT_14H_02H) \ -__PMC_EV(IAP, EVENT_17H_01H) \ -__PMC_EV(IAP, EVENT_18H_00H) \ -__PMC_EV(IAP, EVENT_18H_01H) \ -__PMC_EV(IAP, EVENT_19H_00H) \ -__PMC_EV(IAP, EVENT_19H_01H) \ -__PMC_EV(IAP, EVENT_19H_02H) \ -__PMC_EV(IAP, EVENT_1DH_01H) \ -__PMC_EV(IAP, EVENT_1DH_02H) \ -__PMC_EV(IAP, EVENT_1DH_04H) \ -__PMC_EV(IAP, EVENT_1EH_01H) \ -__PMC_EV(IAP, EVENT_20H_01H) \ -__PMC_EV(IAP, EVENT_21H) \ -__PMC_EV(IAP, EVENT_22H) \ -__PMC_EV(IAP, EVENT_22H_01H) \ -__PMC_EV(IAP, EVENT_22H_02H) \ -__PMC_EV(IAP, EVENT_22H_04H) \ -__PMC_EV(IAP, EVENT_22H_08H) \ -__PMC_EV(IAP, EVENT_22H_10H) \ -__PMC_EV(IAP, EVENT_22H_20H) \ -__PMC_EV(IAP, EVENT_22H_40H) \ -__PMC_EV(IAP, EVENT_22H_80H) \ -__PMC_EV(IAP, EVENT_23H) \ -__PMC_EV(IAP, EVENT_24H) \ -__PMC_EV(IAP, EVENT_24H_01H) \ -__PMC_EV(IAP, EVENT_24H_02H) \ -__PMC_EV(IAP, EVENT_24H_03H) \ -__PMC_EV(IAP, EVENT_24H_04H) \ -__PMC_EV(IAP, EVENT_24H_08H) \ -__PMC_EV(IAP, EVENT_24H_0CH) \ -__PMC_EV(IAP, EVENT_24H_10H) \ -__PMC_EV(IAP, EVENT_24H_20H) \ -__PMC_EV(IAP, EVENT_24H_21H) \ -__PMC_EV(IAP, EVENT_24H_22H) \ -__PMC_EV(IAP, EVENT_24H_24H) \ -__PMC_EV(IAP, EVENT_24H_27H) \ -__PMC_EV(IAP, EVENT_24H_30H) \ -__PMC_EV(IAP, EVENT_24H_38H) \ -__PMC_EV(IAP, EVENT_24H_3FH) \ -__PMC_EV(IAP, EVENT_24H_40H) \ -__PMC_EV(IAP, EVENT_24H_41H) \ -__PMC_EV(IAP, EVENT_24H_42H) \ -__PMC_EV(IAP, EVENT_24H_44H) \ -__PMC_EV(IAP, EVENT_24H_50H) \ -__PMC_EV(IAP, EVENT_24H_80H) \ -__PMC_EV(IAP, EVENT_24H_AAH) \ -__PMC_EV(IAP, EVENT_24H_BFH) \ -__PMC_EV(IAP, EVENT_24H_C0H) \ -__PMC_EV(IAP, EVENT_24H_D8H) \ -__PMC_EV(IAP, EVENT_24H_E1H) \ -__PMC_EV(IAP, EVENT_24H_E2H) \ -__PMC_EV(IAP, EVENT_24H_E4H) \ -__PMC_EV(IAP, EVENT_24H_E7H) \ -__PMC_EV(IAP, EVENT_24H_EFH) \ -__PMC_EV(IAP, EVENT_24H_F7H) \ -__PMC_EV(IAP, EVENT_24H_F8H) \ -__PMC_EV(IAP, EVENT_24H_FFH) \ -__PMC_EV(IAP, EVENT_25H) \ -__PMC_EV(IAP, EVENT_26H) \ -__PMC_EV(IAP, EVENT_26H_01H) \ -__PMC_EV(IAP, EVENT_26H_02H) \ -__PMC_EV(IAP, EVENT_26H_04H) \ -__PMC_EV(IAP, EVENT_26H_08H) \ -__PMC_EV(IAP, EVENT_26H_0FH) \ -__PMC_EV(IAP, EVENT_26H_10H) \ -__PMC_EV(IAP, EVENT_26H_20H) \ -__PMC_EV(IAP, EVENT_26H_40H) \ -__PMC_EV(IAP, EVENT_26H_80H) \ -__PMC_EV(IAP, EVENT_26H_F0H) \ -__PMC_EV(IAP, EVENT_26H_FFH) \ -__PMC_EV(IAP, EVENT_27H) \ -__PMC_EV(IAP, EVENT_27H_01H) \ -__PMC_EV(IAP, EVENT_27H_02H) \ -__PMC_EV(IAP, EVENT_27H_04H) \ -__PMC_EV(IAP, EVENT_27H_08H) \ -__PMC_EV(IAP, EVENT_27H_0EH) \ -__PMC_EV(IAP, EVENT_27H_0FH) \ -__PMC_EV(IAP, EVENT_27H_10H) \ -__PMC_EV(IAP, EVENT_27H_20H) \ -__PMC_EV(IAP, EVENT_27H_40H) \ -__PMC_EV(IAP, EVENT_27H_50H) \ -__PMC_EV(IAP, EVENT_27H_80H) \ -__PMC_EV(IAP, EVENT_27H_E0H) \ -__PMC_EV(IAP, EVENT_27H_F0H) \ -__PMC_EV(IAP, EVENT_28H) \ -__PMC_EV(IAP, EVENT_28H_01H) \ -__PMC_EV(IAP, EVENT_28H_02H) \ -__PMC_EV(IAP, EVENT_28H_04H) \ -__PMC_EV(IAP, EVENT_28H_07H) \ -__PMC_EV(IAP, EVENT_28H_08H) \ -__PMC_EV(IAP, EVENT_28H_0FH) \ -__PMC_EV(IAP, EVENT_28H_18H) \ -__PMC_EV(IAP, EVENT_28H_20H) \ -__PMC_EV(IAP, EVENT_28H_40H) \ -__PMC_EV(IAP, EVENT_29H) \ -__PMC_EV(IAP, EVENT_2AH) \ -__PMC_EV(IAP, EVENT_2BH) \ -__PMC_EV(IAP, EVENT_2EH) \ -__PMC_EV(IAP, EVENT_2EH_01H) \ -__PMC_EV(IAP, EVENT_2EH_02H) \ -__PMC_EV(IAP, EVENT_2EH_41H) \ -__PMC_EV(IAP, EVENT_2EH_4FH) \ -__PMC_EV(IAP, EVENT_30H) \ -__PMC_EV(IAP, EVENT_30H_00H) \ -__PMC_EV(IAP, EVENT_31H_00H) \ -__PMC_EV(IAP, EVENT_32H) \ -__PMC_EV(IAP, EVENT_3AH) \ -__PMC_EV(IAP, EVENT_3AH_00H) \ -__PMC_EV(IAP, EVENT_3BH_C0H) \ -__PMC_EV(IAP, EVENT_3CH_00H) \ -__PMC_EV(IAP, EVENT_3CH_01H) \ -__PMC_EV(IAP, EVENT_3CH_02H) \ -__PMC_EV(IAP, EVENT_3DH_01H) \ -__PMC_EV(IAP, EVENT_40H) \ -__PMC_EV(IAP, EVENT_40H_01H) \ -__PMC_EV(IAP, EVENT_40H_02H) \ -__PMC_EV(IAP, EVENT_40H_04H) \ -__PMC_EV(IAP, EVENT_40H_08H) \ -__PMC_EV(IAP, EVENT_40H_0FH) \ -__PMC_EV(IAP, EVENT_40H_21H) \ -__PMC_EV(IAP, EVENT_41H) \ -__PMC_EV(IAP, EVENT_41H_01H) \ -__PMC_EV(IAP, EVENT_41H_02H) \ -__PMC_EV(IAP, EVENT_41H_04H) \ -__PMC_EV(IAP, EVENT_41H_08H) \ -__PMC_EV(IAP, EVENT_41H_0FH) \ -__PMC_EV(IAP, EVENT_41H_22H) \ -__PMC_EV(IAP, EVENT_42H) \ -__PMC_EV(IAP, EVENT_42H_01H) \ -__PMC_EV(IAP, EVENT_42H_02H) \ -__PMC_EV(IAP, EVENT_42H_04H) \ -__PMC_EV(IAP, EVENT_42H_08H) \ -__PMC_EV(IAP, EVENT_42H_10H) \ -__PMC_EV(IAP, EVENT_43H_01H) \ -__PMC_EV(IAP, EVENT_43H_02H) \ -__PMC_EV(IAP, EVENT_44H_02H) \ -__PMC_EV(IAP, EVENT_45H_0FH) \ -__PMC_EV(IAP, EVENT_46H_00H) \ -__PMC_EV(IAP, EVENT_47H_00H) \ -__PMC_EV(IAP, EVENT_48H_00H) \ -__PMC_EV(IAP, EVENT_48H_01H) \ -__PMC_EV(IAP, EVENT_48H_02H) \ -__PMC_EV(IAP, EVENT_49H_00H) \ -__PMC_EV(IAP, EVENT_49H_01H) \ -__PMC_EV(IAP, EVENT_49H_02H) \ -__PMC_EV(IAP, EVENT_49H_04H) \ -__PMC_EV(IAP, EVENT_49H_08H) \ -__PMC_EV(IAP, EVENT_49H_0EH) \ -__PMC_EV(IAP, EVENT_49H_10H) \ -__PMC_EV(IAP, EVENT_49H_20H) \ -__PMC_EV(IAP, EVENT_49H_40H) \ -__PMC_EV(IAP, EVENT_49H_60H) \ -__PMC_EV(IAP, EVENT_49H_80H) \ -__PMC_EV(IAP, EVENT_4BH_00H) \ -__PMC_EV(IAP, EVENT_4BH_01H) \ -__PMC_EV(IAP, EVENT_4BH_02H) \ -__PMC_EV(IAP, EVENT_4BH_03H) \ -__PMC_EV(IAP, EVENT_4BH_08H) \ -__PMC_EV(IAP, EVENT_4CH_00H) \ -__PMC_EV(IAP, EVENT_4CH_01H) \ -__PMC_EV(IAP, EVENT_4CH_02H) \ -__PMC_EV(IAP, EVENT_4DH_01H) \ -__PMC_EV(IAP, EVENT_4EH_01H) \ -__PMC_EV(IAP, EVENT_4EH_02H) \ -__PMC_EV(IAP, EVENT_4EH_04H) \ -__PMC_EV(IAP, EVENT_4EH_10H) \ -__PMC_EV(IAP, EVENT_4FH_00H) \ -__PMC_EV(IAP, EVENT_4FH_02H) \ -__PMC_EV(IAP, EVENT_4FH_04H) \ -__PMC_EV(IAP, EVENT_4FH_08H) \ -__PMC_EV(IAP, EVENT_4FH_10H) \ -__PMC_EV(IAP, EVENT_51H_01H) \ -__PMC_EV(IAP, EVENT_51H_02H) \ -__PMC_EV(IAP, EVENT_51H_04H) \ -__PMC_EV(IAP, EVENT_51H_08H) \ -__PMC_EV(IAP, EVENT_52H_01H) \ -__PMC_EV(IAP, EVENT_53H_01H) \ -__PMC_EV(IAP, EVENT_54H_01H) \ -__PMC_EV(IAP, EVENT_54H_02H) \ -__PMC_EV(IAP, EVENT_54H_04H) \ -__PMC_EV(IAP, EVENT_54H_08H) \ -__PMC_EV(IAP, EVENT_54H_10H) \ -__PMC_EV(IAP, EVENT_54H_20H) \ -__PMC_EV(IAP, EVENT_54H_40H) \ -__PMC_EV(IAP, EVENT_58H_01H) \ -__PMC_EV(IAP, EVENT_58H_02H) \ -__PMC_EV(IAP, EVENT_58H_04H) \ -__PMC_EV(IAP, EVENT_58H_08H) \ -__PMC_EV(IAP, EVENT_59H_20H) \ -__PMC_EV(IAP, EVENT_59H_40H) \ -__PMC_EV(IAP, EVENT_59H_80H) \ -__PMC_EV(IAP, EVENT_5BH_0CH) \ -__PMC_EV(IAP, EVENT_5BH_0FH) \ -__PMC_EV(IAP, EVENT_5BH_40H) \ -__PMC_EV(IAP, EVENT_5BH_4FH) \ -__PMC_EV(IAP, EVENT_5CH_01H) \ -__PMC_EV(IAP, EVENT_5CH_02H) \ -__PMC_EV(IAP, EVENT_5DH_01H) \ -__PMC_EV(IAP, EVENT_5DH_02H) \ -__PMC_EV(IAP, EVENT_5DH_04H) \ -__PMC_EV(IAP, EVENT_5DH_08H) \ -__PMC_EV(IAP, EVENT_5DH_10H) \ -__PMC_EV(IAP, EVENT_5EH_01H) \ -__PMC_EV(IAP, EVENT_5FH_01H) \ -__PMC_EV(IAP, EVENT_5FH_04H) \ -__PMC_EV(IAP, EVENT_60H) \ -__PMC_EV(IAP, EVENT_60H_01H) \ -__PMC_EV(IAP, EVENT_60H_02H) \ -__PMC_EV(IAP, EVENT_60H_04H) \ -__PMC_EV(IAP, EVENT_60H_08H) \ -__PMC_EV(IAP, EVENT_60H_10H) \ -__PMC_EV(IAP, EVENT_61H) \ -__PMC_EV(IAP, EVENT_61H_00H) \ -__PMC_EV(IAP, EVENT_62H) \ -__PMC_EV(IAP, EVENT_62H_00H) \ -__PMC_EV(IAP, EVENT_63H) \ -__PMC_EV(IAP, EVENT_63H_01H) \ -__PMC_EV(IAP, EVENT_63H_02H) \ -__PMC_EV(IAP, EVENT_64H) \ -__PMC_EV(IAP, EVENT_64H_40H) \ -__PMC_EV(IAP, EVENT_65H) \ -__PMC_EV(IAP, EVENT_66H) \ -__PMC_EV(IAP, EVENT_67H) \ -__PMC_EV(IAP, EVENT_68H) \ -__PMC_EV(IAP, EVENT_69H) \ -__PMC_EV(IAP, EVENT_6AH) \ -__PMC_EV(IAP, EVENT_6BH) \ -__PMC_EV(IAP, EVENT_6CH) \ -__PMC_EV(IAP, EVENT_6CH_01H) \ -__PMC_EV(IAP, EVENT_6DH) \ -__PMC_EV(IAP, EVENT_6EH) \ -__PMC_EV(IAP, EVENT_6FH) \ -__PMC_EV(IAP, EVENT_70H) \ -__PMC_EV(IAP, EVENT_77H) \ -__PMC_EV(IAP, EVENT_78H) \ -__PMC_EV(IAP, EVENT_79H_02H) \ -__PMC_EV(IAP, EVENT_79H_04H) \ -__PMC_EV(IAP, EVENT_79H_08H) \ -__PMC_EV(IAP, EVENT_79H_10H) \ -__PMC_EV(IAP, EVENT_79H_18H) \ -__PMC_EV(IAP, EVENT_79H_20H) \ -__PMC_EV(IAP, EVENT_79H_24H) \ -__PMC_EV(IAP, EVENT_79H_30H) \ -__PMC_EV(IAP, EVENT_79H_3CH) \ -__PMC_EV(IAP, EVENT_7AH) \ -__PMC_EV(IAP, EVENT_7BH) \ -__PMC_EV(IAP, EVENT_7DH) \ -__PMC_EV(IAP, EVENT_7EH) \ -__PMC_EV(IAP, EVENT_7EH_00H) \ -__PMC_EV(IAP, EVENT_7FH) \ -__PMC_EV(IAP, EVENT_80H_00H) \ -__PMC_EV(IAP, EVENT_80H_01H) \ -__PMC_EV(IAP, EVENT_80H_02H) \ -__PMC_EV(IAP, EVENT_80H_03H) \ -__PMC_EV(IAP, EVENT_80H_04H) \ -__PMC_EV(IAP, EVENT_80H_10H) \ -__PMC_EV(IAP, EVENT_81H_00H) \ -__PMC_EV(IAP, EVENT_81H_01H) \ -__PMC_EV(IAP, EVENT_81H_02H) \ -__PMC_EV(IAP, EVENT_82H_01H) \ -__PMC_EV(IAP, EVENT_82H_02H) \ -__PMC_EV(IAP, EVENT_82H_04H) \ -__PMC_EV(IAP, EVENT_82H_10H) \ -__PMC_EV(IAP, EVENT_82H_12H) \ -__PMC_EV(IAP, EVENT_82H_40H) \ -__PMC_EV(IAP, EVENT_83H_01H) \ -__PMC_EV(IAP, EVENT_83H_02H) \ -__PMC_EV(IAP, EVENT_83H_04H) \ -__PMC_EV(IAP, EVENT_85H_00H) \ -__PMC_EV(IAP, EVENT_85H_01H) \ -__PMC_EV(IAP, EVENT_85H_02H) \ -__PMC_EV(IAP, EVENT_85H_04H) \ -__PMC_EV(IAP, EVENT_85H_08H) \ -__PMC_EV(IAP, EVENT_85H_0EH) \ -__PMC_EV(IAP, EVENT_85H_10H) \ -__PMC_EV(IAP, EVENT_85H_20H) \ -__PMC_EV(IAP, EVENT_85H_40H) \ -__PMC_EV(IAP, EVENT_85H_60H) \ -__PMC_EV(IAP, EVENT_85H_80H) \ -__PMC_EV(IAP, EVENT_86H_00H) \ -__PMC_EV(IAP, EVENT_87H_00H) \ -__PMC_EV(IAP, EVENT_87H_01H) \ -__PMC_EV(IAP, EVENT_87H_02H) \ -__PMC_EV(IAP, EVENT_87H_04H) \ -__PMC_EV(IAP, EVENT_87H_08H) \ -__PMC_EV(IAP, EVENT_87H_0FH) \ -__PMC_EV(IAP, EVENT_88H_00H) \ -__PMC_EV(IAP, EVENT_88H_01H) \ -__PMC_EV(IAP, EVENT_88H_02H) \ -__PMC_EV(IAP, EVENT_88H_04H) \ -__PMC_EV(IAP, EVENT_88H_07H) \ -__PMC_EV(IAP, EVENT_88H_08H) \ -__PMC_EV(IAP, EVENT_88H_10H) \ -__PMC_EV(IAP, EVENT_88H_20H) \ -__PMC_EV(IAP, EVENT_88H_30H) \ -__PMC_EV(IAP, EVENT_88H_40H) \ -__PMC_EV(IAP, EVENT_88H_41H) \ -__PMC_EV(IAP, EVENT_88H_80H) \ -__PMC_EV(IAP, EVENT_88H_81H) \ -__PMC_EV(IAP, EVENT_88H_82H) \ -__PMC_EV(IAP, EVENT_88H_84H) \ -__PMC_EV(IAP, EVENT_88H_88H) \ -__PMC_EV(IAP, EVENT_88H_90H) \ -__PMC_EV(IAP, EVENT_88H_A0H) \ -__PMC_EV(IAP, EVENT_88H_7FH) \ -__PMC_EV(IAP, EVENT_88H_FFH) \ -__PMC_EV(IAP, EVENT_89H_00H) \ -__PMC_EV(IAP, EVENT_89H_01H) \ -__PMC_EV(IAP, EVENT_89H_02H) \ -__PMC_EV(IAP, EVENT_89H_04H) \ -__PMC_EV(IAP, EVENT_89H_07H) \ -__PMC_EV(IAP, EVENT_89H_08H) \ -__PMC_EV(IAP, EVENT_89H_10H) \ -__PMC_EV(IAP, EVENT_89H_20H) \ -__PMC_EV(IAP, EVENT_89H_30H) \ -__PMC_EV(IAP, EVENT_89H_40H) \ -__PMC_EV(IAP, EVENT_89H_41H) \ -__PMC_EV(IAP, EVENT_89H_80H) \ -__PMC_EV(IAP, EVENT_89H_81H) \ -__PMC_EV(IAP, EVENT_89H_82H) \ -__PMC_EV(IAP, EVENT_89H_84H) \ -__PMC_EV(IAP, EVENT_89H_88H) \ -__PMC_EV(IAP, EVENT_89H_90H) \ -__PMC_EV(IAP, EVENT_89H_A0H) \ -__PMC_EV(IAP, EVENT_89H_7FH) \ -__PMC_EV(IAP, EVENT_89H_FFH) \ -__PMC_EV(IAP, EVENT_8AH_00H) \ -__PMC_EV(IAP, EVENT_8BH_00H) \ -__PMC_EV(IAP, EVENT_8CH_00H) \ -__PMC_EV(IAP, EVENT_8DH_00H) \ -__PMC_EV(IAP, EVENT_8EH_00H) \ -__PMC_EV(IAP, EVENT_8FH_00H) \ -__PMC_EV(IAP, EVENT_90H_00H) \ -__PMC_EV(IAP, EVENT_91H_00H) \ -__PMC_EV(IAP, EVENT_92H_00H) \ -__PMC_EV(IAP, EVENT_93H_00H) \ -__PMC_EV(IAP, EVENT_94H_00H) \ -__PMC_EV(IAP, EVENT_97H_00H) \ -__PMC_EV(IAP, EVENT_98H_00H) \ -__PMC_EV(IAP, EVENT_9CH_01H) \ -__PMC_EV(IAP, EVENT_A0H_00H) \ -__PMC_EV(IAP, EVENT_A1H_01H) \ -__PMC_EV(IAP, EVENT_A1H_02H) \ -__PMC_EV(IAP, EVENT_A1H_04H) \ -__PMC_EV(IAP, EVENT_A1H_08H) \ -__PMC_EV(IAP, EVENT_A1H_0CH) \ -__PMC_EV(IAP, EVENT_A1H_10H) \ -__PMC_EV(IAP, EVENT_A1H_20H) \ -__PMC_EV(IAP, EVENT_A1H_30H) \ -__PMC_EV(IAP, EVENT_A1H_40H) \ -__PMC_EV(IAP, EVENT_A1H_80H) \ -__PMC_EV(IAP, EVENT_A2H_00H) \ -__PMC_EV(IAP, EVENT_A2H_01H) \ -__PMC_EV(IAP, EVENT_A2H_02H) \ -__PMC_EV(IAP, EVENT_A2H_04H) \ -__PMC_EV(IAP, EVENT_A2H_08H) \ -__PMC_EV(IAP, EVENT_A2H_10H) \ -__PMC_EV(IAP, EVENT_A2H_20H) \ -__PMC_EV(IAP, EVENT_A2H_40H) \ -__PMC_EV(IAP, EVENT_A2H_80H) \ -__PMC_EV(IAP, EVENT_A3H_01H) \ -__PMC_EV(IAP, EVENT_A3H_02H) \ -__PMC_EV(IAP, EVENT_A3H_04H) \ -__PMC_EV(IAP, EVENT_A3H_05H) \ -__PMC_EV(IAP, EVENT_A3H_06H) \ -__PMC_EV(IAP, EVENT_A3H_08H) \ -__PMC_EV(IAP, EVENT_A3H_0CH) \ -__PMC_EV(IAP, EVENT_A3H_10H) \ -__PMC_EV(IAP, EVENT_A3H_14H) \ -__PMC_EV(IAP, EVENT_A6H_01H) \ -__PMC_EV(IAP, EVENT_A6H_02H) \ -__PMC_EV(IAP, EVENT_A6H_04H) \ -__PMC_EV(IAP, EVENT_A6H_08H) \ -__PMC_EV(IAP, EVENT_A6H_10H) \ -__PMC_EV(IAP, EVENT_A6H_40H) \ -__PMC_EV(IAP, EVENT_A7H_01H) \ -__PMC_EV(IAP, EVENT_A8H_01H) \ -__PMC_EV(IAP, EVENT_A8H_02H) \ -__PMC_EV(IAP, EVENT_AAH_01H) \ -__PMC_EV(IAP, EVENT_AAH_02H) \ -__PMC_EV(IAP, EVENT_AAH_03H) \ -__PMC_EV(IAP, EVENT_AAH_08H) \ -__PMC_EV(IAP, EVENT_ABH_01H) \ -__PMC_EV(IAP, EVENT_ABH_02H) \ -__PMC_EV(IAP, EVENT_ACH_02H) \ -__PMC_EV(IAP, EVENT_ACH_08H) \ -__PMC_EV(IAP, EVENT_ACH_0AH) \ -__PMC_EV(IAP, EVENT_AEH_01H) \ -__PMC_EV(IAP, EVENT_B0H_00H) \ -__PMC_EV(IAP, EVENT_B0H_01H) \ -__PMC_EV(IAP, EVENT_B0H_02H) \ -__PMC_EV(IAP, EVENT_B0H_04H) \ -__PMC_EV(IAP, EVENT_B0H_08H) \ -__PMC_EV(IAP, EVENT_B0H_10H) \ -__PMC_EV(IAP, EVENT_B0H_20H) \ -__PMC_EV(IAP, EVENT_B0H_40H) \ -__PMC_EV(IAP, EVENT_B0H_80H) \ -__PMC_EV(IAP, EVENT_B1H_00H) \ -__PMC_EV(IAP, EVENT_B1H_01H) \ -__PMC_EV(IAP, EVENT_B1H_02H) \ -__PMC_EV(IAP, EVENT_B1H_04H) \ -__PMC_EV(IAP, EVENT_B1H_08H) \ -__PMC_EV(IAP, EVENT_B1H_10H) \ -__PMC_EV(IAP, EVENT_B1H_1FH) \ -__PMC_EV(IAP, EVENT_B1H_20H) \ -__PMC_EV(IAP, EVENT_B1H_3FH) \ -__PMC_EV(IAP, EVENT_B1H_40H) \ -__PMC_EV(IAP, EVENT_B1H_80H) \ -__PMC_EV(IAP, EVENT_B2H_01H) \ -__PMC_EV(IAP, EVENT_B3H_01H) \ -__PMC_EV(IAP, EVENT_B3H_02H) \ -__PMC_EV(IAP, EVENT_B3H_04H) \ -__PMC_EV(IAP, EVENT_B3H_08H) \ -__PMC_EV(IAP, EVENT_B3H_10H) \ -__PMC_EV(IAP, EVENT_B3H_20H) \ -__PMC_EV(IAP, EVENT_B3H_81H) \ -__PMC_EV(IAP, EVENT_B3H_82H) \ -__PMC_EV(IAP, EVENT_B3H_84H) \ -__PMC_EV(IAP, EVENT_B3H_88H) \ -__PMC_EV(IAP, EVENT_B3H_90H) \ -__PMC_EV(IAP, EVENT_B3H_A0H) \ -__PMC_EV(IAP, EVENT_B4H_01H) \ -__PMC_EV(IAP, EVENT_B4H_02H) \ -__PMC_EV(IAP, EVENT_B4H_04H) \ -__PMC_EV(IAP, EVENT_B6H_01H) \ -__PMC_EV(IAP, EVENT_B6H_04H) \ -__PMC_EV(IAP, EVENT_B7H_01H) \ -__PMC_EV(IAP, EVENT_B7H_02H) \ -__PMC_EV(IAP, EVENT_B8H_01H) \ -__PMC_EV(IAP, EVENT_B8H_02H) \ -__PMC_EV(IAP, EVENT_B8H_04H) \ -__PMC_EV(IAP, EVENT_BAH_01H) \ -__PMC_EV(IAP, EVENT_BAH_02H) \ -__PMC_EV(IAP, EVENT_BBH_01H) \ -__PMC_EV(IAP, EVENT_BCH_11H) \ -__PMC_EV(IAP, EVENT_BCH_12H) \ -__PMC_EV(IAP, EVENT_BCH_14H) \ -__PMC_EV(IAP, EVENT_BCH_18H) \ -__PMC_EV(IAP, EVENT_BCH_21H) \ -__PMC_EV(IAP, EVENT_BCH_22H) \ -__PMC_EV(IAP, EVENT_BCH_24H) \ -__PMC_EV(IAP, EVENT_BCH_28H) \ -__PMC_EV(IAP, EVENT_BDH_01H) \ -__PMC_EV(IAP, EVENT_BDH_20H) \ -__PMC_EV(IAP, EVENT_BFH_05H) \ -__PMC_EV(IAP, EVENT_C0H_00H) \ -__PMC_EV(IAP, EVENT_C0H_01H) \ -__PMC_EV(IAP, EVENT_C0H_02H) \ -__PMC_EV(IAP, EVENT_C0H_04H) \ -__PMC_EV(IAP, EVENT_C0H_08H) \ -__PMC_EV(IAP, EVENT_C1H_00H) \ -__PMC_EV(IAP, EVENT_C1H_01H) \ -__PMC_EV(IAP, EVENT_C1H_02H) \ -__PMC_EV(IAP, EVENT_C1H_08H) \ -__PMC_EV(IAP, EVENT_C1H_10H) \ -__PMC_EV(IAP, EVENT_C1H_20H) \ -__PMC_EV(IAP, EVENT_C1H_3FH) \ -__PMC_EV(IAP, EVENT_C1H_40H) \ -__PMC_EV(IAP, EVENT_C1H_80H) \ -__PMC_EV(IAP, EVENT_C1H_FEH) \ -__PMC_EV(IAP, EVENT_C2H_00H) \ -__PMC_EV(IAP, EVENT_C2H_01H) \ -__PMC_EV(IAP, EVENT_C2H_02H) \ -__PMC_EV(IAP, EVENT_C2H_04H) \ -__PMC_EV(IAP, EVENT_C2H_07H) \ -__PMC_EV(IAP, EVENT_C2H_08H) \ -__PMC_EV(IAP, EVENT_C2H_0FH) \ -__PMC_EV(IAP, EVENT_C2H_10H) \ -__PMC_EV(IAP, EVENT_C3H_00H) \ -__PMC_EV(IAP, EVENT_C3H_01H) \ -__PMC_EV(IAP, EVENT_C3H_02H) \ -__PMC_EV(IAP, EVENT_C3H_04H) \ -__PMC_EV(IAP, EVENT_C3H_08H) \ -__PMC_EV(IAP, EVENT_C3H_10H) \ -__PMC_EV(IAP, EVENT_C3H_20H) \ -__PMC_EV(IAP, EVENT_C4H_00H) \ -__PMC_EV(IAP, EVENT_C4H_01H) \ -__PMC_EV(IAP, EVENT_C4H_02H) \ -__PMC_EV(IAP, EVENT_C4H_04H) \ -__PMC_EV(IAP, EVENT_C4H_08H) \ -__PMC_EV(IAP, EVENT_C4H_0CH) \ -__PMC_EV(IAP, EVENT_C4H_0FH) \ -__PMC_EV(IAP, EVENT_C4H_10H) \ -__PMC_EV(IAP, EVENT_C4H_20H) \ -__PMC_EV(IAP, EVENT_C4H_40H) \ -__PMC_EV(IAP, EVENT_C4H_7EH) \ -__PMC_EV(IAP, EVENT_C4H_BFH) \ -__PMC_EV(IAP, EVENT_C4H_EBH) \ -__PMC_EV(IAP, EVENT_C4H_F7H) \ -__PMC_EV(IAP, EVENT_C4H_F9H) \ -__PMC_EV(IAP, EVENT_C4H_FBH) \ -__PMC_EV(IAP, EVENT_C4H_FDH) \ -__PMC_EV(IAP, EVENT_C4H_FEH) \ -__PMC_EV(IAP, EVENT_C5H_00H) \ -__PMC_EV(IAP, EVENT_C5H_01H) \ -__PMC_EV(IAP, EVENT_C5H_02H) \ -__PMC_EV(IAP, EVENT_C5H_04H) \ -__PMC_EV(IAP, EVENT_C5H_10H) \ -__PMC_EV(IAP, EVENT_C5H_20H) \ -__PMC_EV(IAP, EVENT_C5H_7EH) \ -__PMC_EV(IAP, EVENT_C5H_BFH) \ -__PMC_EV(IAP, EVENT_C5H_EBH) \ -__PMC_EV(IAP, EVENT_C5H_F7H) \ -__PMC_EV(IAP, EVENT_C5H_F9H) \ -__PMC_EV(IAP, EVENT_C5H_FBH) \ -__PMC_EV(IAP, EVENT_C5H_FDH) \ -__PMC_EV(IAP, EVENT_C5H_FEH) \ -__PMC_EV(IAP, EVENT_C6H_00H) \ -__PMC_EV(IAP, EVENT_C6H_01H) \ -__PMC_EV(IAP, EVENT_C6H_02H) \ -__PMC_EV(IAP, EVENT_C7H_00H) \ -__PMC_EV(IAP, EVENT_C7H_01H) \ -__PMC_EV(IAP, EVENT_C7H_02H) \ -__PMC_EV(IAP, EVENT_C7H_04H) \ -__PMC_EV(IAP, EVENT_C7H_08H) \ -__PMC_EV(IAP, EVENT_C7H_10H) \ -__PMC_EV(IAP, EVENT_C7H_1FH) \ -__PMC_EV(IAP, EVENT_C7H_20H) \ -__PMC_EV(IAP, EVENT_C7H_40H) \ -__PMC_EV(IAP, EVENT_C7H_80H) \ -__PMC_EV(IAP, EVENT_C8H_00H) \ -__PMC_EV(IAP, EVENT_C8H_01H) \ -__PMC_EV(IAP, EVENT_C8H_02H) \ -__PMC_EV(IAP, EVENT_C8H_04H) \ -__PMC_EV(IAP, EVENT_C8H_08H) \ -__PMC_EV(IAP, EVENT_C8H_10H) \ -__PMC_EV(IAP, EVENT_C8H_20H) \ -__PMC_EV(IAP, EVENT_C8H_40H) \ -__PMC_EV(IAP, EVENT_C8H_80H) \ -__PMC_EV(IAP, EVENT_C9H_00H) \ -__PMC_EV(IAP, EVENT_C9H_01H) \ -__PMC_EV(IAP, EVENT_C9H_02H) \ -__PMC_EV(IAP, EVENT_C9H_04H) \ -__PMC_EV(IAP, EVENT_C9H_08H) \ -__PMC_EV(IAP, EVENT_C9H_10H) \ -__PMC_EV(IAP, EVENT_C9H_20H) \ -__PMC_EV(IAP, EVENT_C9H_40H) \ -__PMC_EV(IAP, EVENT_C9H_80H) \ -__PMC_EV(IAP, EVENT_CAH_00H) \ -__PMC_EV(IAP, EVENT_CAH_01H) \ -__PMC_EV(IAP, EVENT_CAH_02H) \ -__PMC_EV(IAP, EVENT_CAH_04H) \ -__PMC_EV(IAP, EVENT_CAH_08H) \ -__PMC_EV(IAP, EVENT_CAH_10H) \ -__PMC_EV(IAP, EVENT_CAH_20H) \ -__PMC_EV(IAP, EVENT_CAH_1EH) \ -__PMC_EV(IAP, EVENT_CAH_3FH) \ -__PMC_EV(IAP, EVENT_CAH_50H) \ -__PMC_EV(IAP, EVENT_CBH_01H) \ -__PMC_EV(IAP, EVENT_CBH_02H) \ -__PMC_EV(IAP, EVENT_CBH_04H) \ -__PMC_EV(IAP, EVENT_CBH_08H) \ -__PMC_EV(IAP, EVENT_CBH_10H) \ -__PMC_EV(IAP, EVENT_CBH_1FH) \ -__PMC_EV(IAP, EVENT_CBH_40H) \ -__PMC_EV(IAP, EVENT_CBH_80H) \ -__PMC_EV(IAP, EVENT_CCH_00H) \ -__PMC_EV(IAP, EVENT_CCH_01H) \ -__PMC_EV(IAP, EVENT_CCH_02H) \ -__PMC_EV(IAP, EVENT_CCH_03H) \ -__PMC_EV(IAP, EVENT_CCH_20H) \ -__PMC_EV(IAP, EVENT_CDH_00H) \ -__PMC_EV(IAP, EVENT_CDH_01H) \ -__PMC_EV(IAP, EVENT_CDH_02H) \ -__PMC_EV(IAP, EVENT_CEH_00H) \ -__PMC_EV(IAP, EVENT_CFH_00H) \ -__PMC_EV(IAP, EVENT_D0H_00H) \ -__PMC_EV(IAP, EVENT_D0H_01H) \ -__PMC_EV(IAP, EVENT_D0H_02H) \ -__PMC_EV(IAP, EVENT_D0H_10H) \ -__PMC_EV(IAP, EVENT_D0H_11H) \ -__PMC_EV(IAP, EVENT_D0H_12H) \ -__PMC_EV(IAP, EVENT_D0H_20H) \ -__PMC_EV(IAP, EVENT_D0H_21H) \ -__PMC_EV(IAP, EVENT_D0H_40H) \ -__PMC_EV(IAP, EVENT_D0H_41H) \ -__PMC_EV(IAP, EVENT_D0H_42H) \ -__PMC_EV(IAP, EVENT_D0H_80H) \ -__PMC_EV(IAP, EVENT_D0H_81H) \ -__PMC_EV(IAP, EVENT_D0H_82H) \ -__PMC_EV(IAP, EVENT_D1H_01H) \ -__PMC_EV(IAP, EVENT_D1H_02H) \ -__PMC_EV(IAP, EVENT_D1H_04H) \ -__PMC_EV(IAP, EVENT_D1H_08H) \ -__PMC_EV(IAP, EVENT_D1H_10H) \ -__PMC_EV(IAP, EVENT_D1H_20H) \ -__PMC_EV(IAP, EVENT_D1H_40H) \ -__PMC_EV(IAP, EVENT_D2H_01H) \ -__PMC_EV(IAP, EVENT_D2H_02H) \ -__PMC_EV(IAP, EVENT_D2H_04H) \ -__PMC_EV(IAP, EVENT_D2H_08H) \ -__PMC_EV(IAP, EVENT_D2H_0FH) \ -__PMC_EV(IAP, EVENT_D2H_10H) \ -__PMC_EV(IAP, EVENT_D3H_01H) \ -__PMC_EV(IAP, EVENT_D3H_02H) \ -__PMC_EV(IAP, EVENT_D3H_03H) \ -__PMC_EV(IAP, EVENT_D3H_04H) \ -__PMC_EV(IAP, EVENT_D3H_08H) \ -__PMC_EV(IAP, EVENT_D3H_0CH) \ -__PMC_EV(IAP, EVENT_D3H_10H) \ -__PMC_EV(IAP, EVENT_D3H_20H) \ -__PMC_EV(IAP, EVENT_D4H_01H) \ -__PMC_EV(IAP, EVENT_D4H_02H) \ -__PMC_EV(IAP, EVENT_D4H_04H) \ -__PMC_EV(IAP, EVENT_D4H_08H) \ -__PMC_EV(IAP, EVENT_D4H_0FH) \ -__PMC_EV(IAP, EVENT_D5H_01H) \ -__PMC_EV(IAP, EVENT_D5H_02H) \ -__PMC_EV(IAP, EVENT_D5H_04H) \ -__PMC_EV(IAP, EVENT_D5H_08H) \ -__PMC_EV(IAP, EVENT_D5H_0FH) \ -__PMC_EV(IAP, EVENT_D7H_00H) \ -__PMC_EV(IAP, EVENT_D8H_00H) \ -__PMC_EV(IAP, EVENT_D8H_01H) \ -__PMC_EV(IAP, EVENT_D8H_02H) \ -__PMC_EV(IAP, EVENT_D8H_03H) \ -__PMC_EV(IAP, EVENT_D8H_04H) \ -__PMC_EV(IAP, EVENT_D9H_00H) \ -__PMC_EV(IAP, EVENT_D9H_01H) \ -__PMC_EV(IAP, EVENT_D9H_02H) \ -__PMC_EV(IAP, EVENT_D9H_03H) \ -__PMC_EV(IAP, EVENT_DAH_00H) \ -__PMC_EV(IAP, EVENT_DAH_01H) \ -__PMC_EV(IAP, EVENT_DAH_02H) \ -__PMC_EV(IAP, EVENT_DBH_00H) \ -__PMC_EV(IAP, EVENT_DBH_01H) \ -__PMC_EV(IAP, EVENT_DCH_01H) \ -__PMC_EV(IAP, EVENT_DCH_02H) \ -__PMC_EV(IAP, EVENT_DCH_04H) \ -__PMC_EV(IAP, EVENT_DCH_08H) \ -__PMC_EV(IAP, EVENT_DCH_10H) \ -__PMC_EV(IAP, EVENT_DCH_1FH) \ -__PMC_EV(IAP, EVENT_E0H_00H) \ -__PMC_EV(IAP, EVENT_E0H_01H) \ -__PMC_EV(IAP, EVENT_E2H_00H) \ -__PMC_EV(IAP, EVENT_E4H_00H) \ -__PMC_EV(IAP, EVENT_E4H_01H) \ -__PMC_EV(IAP, EVENT_E5H_01H) \ -__PMC_EV(IAP, EVENT_E6H_00H) \ -__PMC_EV(IAP, EVENT_E6H_01H) \ -__PMC_EV(IAP, EVENT_E6H_02H) \ -__PMC_EV(IAP, EVENT_E6H_08H) \ -__PMC_EV(IAP, EVENT_E6H_10H) \ -__PMC_EV(IAP, EVENT_E6H_1FH) \ -__PMC_EV(IAP, EVENT_E7H_01H) \ -__PMC_EV(IAP, EVENT_E8H_01H) \ -__PMC_EV(IAP, EVENT_E8H_02H) \ -__PMC_EV(IAP, EVENT_E8H_03H) \ -__PMC_EV(IAP, EVENT_ECH_01H) \ -__PMC_EV(IAP, EVENT_F0H_00H) \ -__PMC_EV(IAP, EVENT_F0H_01H) \ -__PMC_EV(IAP, EVENT_F0H_02H) \ -__PMC_EV(IAP, EVENT_F0H_04H) \ -__PMC_EV(IAP, EVENT_F0H_08H) \ -__PMC_EV(IAP, EVENT_F0H_10H) \ -__PMC_EV(IAP, EVENT_F0H_20H) \ -__PMC_EV(IAP, EVENT_F0H_40H) \ -__PMC_EV(IAP, EVENT_F0H_80H) \ -__PMC_EV(IAP, EVENT_F1H_01H) \ -__PMC_EV(IAP, EVENT_F1H_02H) \ -__PMC_EV(IAP, EVENT_F1H_04H) \ -__PMC_EV(IAP, EVENT_F1H_07H) \ -__PMC_EV(IAP, EVENT_F1H_1FH) \ -__PMC_EV(IAP, EVENT_F2H_01H) \ -__PMC_EV(IAP, EVENT_F2H_02H) \ -__PMC_EV(IAP, EVENT_F2H_04H) \ -__PMC_EV(IAP, EVENT_F2H_05H) \ -__PMC_EV(IAP, EVENT_F2H_06H) \ -__PMC_EV(IAP, EVENT_F2H_08H) \ -__PMC_EV(IAP, EVENT_F2H_0AH) \ -__PMC_EV(IAP, EVENT_F2H_0FH) \ -__PMC_EV(IAP, EVENT_F3H_01H) \ -__PMC_EV(IAP, EVENT_F3H_02H) \ -__PMC_EV(IAP, EVENT_F3H_04H) \ -__PMC_EV(IAP, EVENT_F3H_08H) \ -__PMC_EV(IAP, EVENT_F3H_10H) \ -__PMC_EV(IAP, EVENT_F3H_20H) \ -__PMC_EV(IAP, EVENT_F4H_01H) \ -__PMC_EV(IAP, EVENT_F4H_02H) \ -__PMC_EV(IAP, EVENT_F4H_04H) \ -__PMC_EV(IAP, EVENT_F4H_08H) \ -__PMC_EV(IAP, EVENT_F4H_10H) \ -__PMC_EV(IAP, EVENT_F6H_01H) \ -__PMC_EV(IAP, EVENT_F7H_01H) \ -__PMC_EV(IAP, EVENT_F7H_02H) \ -__PMC_EV(IAP, EVENT_F7H_04H) \ -__PMC_EV(IAP, EVENT_F8H_00H) \ -__PMC_EV(IAP, EVENT_F8H_01H) \ -__PMC_EV(IAP, EVENT_FDH_01H) \ -__PMC_EV(IAP, EVENT_FDH_02H) \ -__PMC_EV(IAP, EVENT_FDH_04H) \ -__PMC_EV(IAP, EVENT_FDH_08H) \ -__PMC_EV(IAP, EVENT_FDH_10H) \ -__PMC_EV(IAP, EVENT_FDH_20H) \ -__PMC_EV(IAP, EVENT_FDH_40H) \ -__PMC_EV(IAP, EVENT_FEH_02H) \ -__PMC_EV(IAP, EVENT_FEH_04H) #define PMC_EV_IAP_FIRST PMC_EV_IAP_ARCH_BR_INS_RET #define PMC_EV_IAP_LAST PMC_EV_IAP_EVENT_FDH_40H /* * Map "architectural" event names to event ids. */ #define __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("branch-instruction-retired", IAP_ARCH_BR_INS_RET) \ __PMC_EV_ALIAS("branch-misses-retired", IAP_ARCH_BR_MIS_RET) \ __PMC_EV_ALIAS("instruction-retired", IAP_ARCH_INS_RET) \ __PMC_EV_ALIAS("llc-misses", IAP_ARCH_LLC_MIS) \ __PMC_EV_ALIAS("llc-reference", IAP_ARCH_LLC_REF) \ __PMC_EV_ALIAS("unhalted-reference-cycles", IAP_ARCH_UNH_REF_CYC) \ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC) -/* - * Aliases for Atom PMCs. - */ -#define __PMC_EV_ALIAS_ATOM() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("BACLEARS", IAP_EVENT_E6H_01H) \ -__PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_00H) \ -__PMC_EV_ALIAS("BR_BAC_MISSP_EXEC", IAP_EVENT_8AH_00H) \ -__PMC_EV_ALIAS("BR_CALL_EXEC", IAP_EVENT_92H_00H) \ -__PMC_EV_ALIAS("BR_CALL_MISSP_EXEC", IAP_EVENT_93H_00H) \ -__PMC_EV_ALIAS("BR_CND_EXEC", IAP_EVENT_8BH_00H) \ -__PMC_EV_ALIAS("BR_CND_MISSP_EXEC", IAP_EVENT_8CH_00H) \ -__PMC_EV_ALIAS("BR_IND_CALL_EXEC", IAP_EVENT_94H_00H) \ -__PMC_EV_ALIAS("BR_IND_EXEC", IAP_EVENT_8DH_00H) \ -__PMC_EV_ALIAS("BR_IND_MISSP_EXEC", IAP_EVENT_8EH_00H) \ -__PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC", IAP_EVENT_88H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ANY", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ANY1", IAP_EVENT_C4H_0FH) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_NOT_TAKEN", \ - IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_TAKEN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_NOT_TAKEN", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_TAKEN", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN", IAP_EVENT_C4H_0CH) \ -__PMC_EV_ALIAS("BR_MISSP_EXEC", IAP_EVENT_89H_00H) \ -__PMC_EV_ALIAS("BR_RET_BAC_MISSP_EXEC", IAP_EVENT_91H_00H) \ -__PMC_EV_ALIAS("BR_RET_EXEC", IAP_EVENT_8FH_00H) \ -__PMC_EV_ALIAS("BR_RET_MISSP_EXEC", IAP_EVENT_90H_00H) \ -__PMC_EV_ALIAS("BR_TKN_BUBBLE_1", IAP_EVENT_97H_00H) \ -__PMC_EV_ALIAS("BR_TKN_BUBBLE_2", IAP_EVENT_98H_00H) \ -__PMC_EV_ALIAS("BUSQ_EMPTY", IAP_EVENT_7DH) \ -__PMC_EV_ALIAS("BUS_BNR_DRV", IAP_EVENT_61H) \ -__PMC_EV_ALIAS("BUS_DATA_RCV", IAP_EVENT_64H) \ -__PMC_EV_ALIAS("BUS_DRDY_CLOCKS", IAP_EVENT_62H) \ -__PMC_EV_ALIAS("BUS_HITM_DRV", IAP_EVENT_7BH) \ -__PMC_EV_ALIAS("BUS_HIT_DRV", IAP_EVENT_7AH) \ -__PMC_EV_ALIAS("BUS_IO_WAIT", IAP_EVENT_7FH) \ -__PMC_EV_ALIAS("BUS_LOCK_CLOCKS", IAP_EVENT_63H) \ -__PMC_EV_ALIAS("BUS_REQUEST_OUTSTANDING", IAP_EVENT_60H) \ -__PMC_EV_ALIAS("BUS_TRANS_ANY", IAP_EVENT_70H) \ -__PMC_EV_ALIAS("BUS_TRANS_BRD", IAP_EVENT_65H) \ -__PMC_EV_ALIAS("BUS_TRANS_BURST", IAP_EVENT_6EH) \ -__PMC_EV_ALIAS("BUS_TRANS_DEF", IAP_EVENT_6DH) \ -__PMC_EV_ALIAS("BUS_TRANS_IFETCH", IAP_EVENT_68H) \ -__PMC_EV_ALIAS("BUS_TRANS_INVAL", IAP_EVENT_69H) \ -__PMC_EV_ALIAS("BUS_TRANS_IO", IAP_EVENT_6CH) \ -__PMC_EV_ALIAS("BUS_TRANS_MEM", IAP_EVENT_6FH) \ -__PMC_EV_ALIAS("BUS_TRANS_P", IAP_EVENT_6BH) \ -__PMC_EV_ALIAS("BUS_TRANS_PWR", IAP_EVENT_6AH) \ -__PMC_EV_ALIAS("BUS_TRANS_RFO", IAP_EVENT_66H) \ -__PMC_EV_ALIAS("BUS_TRANS_WB", IAP_EVENT_67H) \ -__PMC_EV_ALIAS("CMP_SNOOP", IAP_EVENT_78H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.BUS", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.NO_OTHER", IAP_EVENT_3CH_02H) \ -__PMC_EV_ALIAS("CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \ -__PMC_EV_ALIAS("CYCLES_INT_MASKED.CYCLES_INT_MASKED", \ - IAP_EVENT_C6H_01H) \ -__PMC_EV_ALIAS("CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", \ - IAP_EVENT_C6H_02H) \ -__PMC_EV_ALIAS("CYCLES_L1I_MEM_STALLED", IAP_EVENT_86H_00H) \ -__PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS", IAP_EVENT_08H_07H) \ -__PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS_LD", IAP_EVENT_08H_05H) \ -__PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS_ST", IAP_EVENT_08H_06H) \ -__PMC_EV_ALIAS("DATA_TLB_MISSES.UTLB_MISS_LD", IAP_EVENT_08H_09H) \ -__PMC_EV_ALIAS("DELAYED_BYPASS.FP", IAP_EVENT_19H_00H) \ -__PMC_EV_ALIAS("DELAYED_BYPASS.LOAD", IAP_EVENT_19H_01H) \ -__PMC_EV_ALIAS("DELAYED_BYPASS.SIMD", IAP_EVENT_19H_02H) \ -__PMC_EV_ALIAS("DIV", IAP_EVENT_13H_00H) \ -__PMC_EV_ALIAS("DIV.AR", IAP_EVENT_13H_81H) \ -__PMC_EV_ALIAS("DIV.S", IAP_EVENT_13H_01H) \ -__PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_08H_01H) \ -__PMC_EV_ALIAS("DTLB_MISSES.L0_MISS_LD", IAP_EVENT_08H_04H) \ -__PMC_EV_ALIAS("DTLB_MISSES.MISS_LD", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_MISSES.MISS_ST", IAP_EVENT_08H_08H) \ -__PMC_EV_ALIAS("EIST_TRANS", IAP_EVENT_3AH_00H) \ -__PMC_EV_ALIAS("ESP.ADDITIONS", IAP_EVENT_ABH_02H) \ -__PMC_EV_ALIAS("ESP.SYNCH", IAP_EVENT_ABH_01H) \ -__PMC_EV_ALIAS("EXT_SNOOP", IAP_EVENT_77H) \ -__PMC_EV_ALIAS("FP_ASSIST", IAP_EVENT_11H_01H) \ -__PMC_EV_ALIAS("FP_ASSIST.AR", IAP_EVENT_11H_81H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE", IAP_EVENT_10H_00H) \ -__PMC_EV_ALIAS("FP_MMX_TRANS_TO_FP", IAP_EVENT_CCH_02H) \ -__PMC_EV_ALIAS("FP_MMX_TRANS_TO_MMX", IAP_EVENT_CCH_01H) \ -__PMC_EV_ALIAS("HW_INT_RCV", IAP_EVENT_C8H_00H) \ -__PMC_EV_ALIAS("ICACHE.ACCESSES", IAP_EVENT_80H_03H) \ -__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("IDLE_DURING_DIV", IAP_EVENT_18H_00H) \ -__PMC_EV_ALIAS("ILD_STALL", IAP_EVENT_87H_00H) \ -__PMC_EV_ALIAS("INST_QUEUE.FULL", IAP_EVENT_83H_02H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.LOADS", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("INST_RETIRED.OTHER", IAP_EVENT_C0H_04H) \ -__PMC_EV_ALIAS("INST_RETIRED.STORES", IAP_EVENT_C0H_02H) \ -__PMC_EV_ALIAS("ITLB.FLUSH", IAP_EVENT_82H_04H) \ -__PMC_EV_ALIAS("ITLB.LARGE_MISS", IAP_EVENT_82H_10H) \ -__PMC_EV_ALIAS("ITLB.MISSES", IAP_EVENT_82H_02H) \ -__PMC_EV_ALIAS("ITLB.SMALL_MISS", IAP_EVENT_82H_02H) \ -__PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C9H_00H) \ -__PMC_EV_ALIAS("L1D_ALL_CACHE_REF", IAP_EVENT_43H_02H) \ -__PMC_EV_ALIAS("L1D_ALL_REF", IAP_EVENT_43H_01H) \ -__PMC_EV_ALIAS("L1D_CACHE.LD", IAP_EVENT_40H_21H) \ -__PMC_EV_ALIAS("L1D_CACHE.ST", IAP_EVENT_41H_22H) \ -__PMC_EV_ALIAS("L1D_CACHE_LOCK", IAP_EVENT_42H) \ -__PMC_EV_ALIAS("L1D_CACHE_LOCK_DURATION", IAP_EVENT_42H_10H) \ -__PMC_EV_ALIAS("L1D_M_EVICT", IAP_EVENT_47H_00H) \ -__PMC_EV_ALIAS("L1D_M_REPL", IAP_EVENT_46H_00H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS", IAP_EVENT_48H_00H) \ -__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_10H) \ -__PMC_EV_ALIAS("L1D_REPL", IAP_EVENT_45H_0FH) \ -__PMC_EV_ALIAS("L1D_SPLIT.LOADS", IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("L1D_SPLIT.STORES", IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("L1I_MISSES", IAP_EVENT_81H_00H) \ -__PMC_EV_ALIAS("L1I_READS", IAP_EVENT_80H_00H) \ -__PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \ -__PMC_EV_ALIAS("L2_DBUS_BUSY_RD", IAP_EVENT_23H) \ -__PMC_EV_ALIAS("L2_IFETCH", IAP_EVENT_28H) \ -__PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \ -__PMC_EV_ALIAS("L2_LINES_IN", IAP_EVENT_24H) \ -__PMC_EV_ALIAS("L2_LINES_OUT", IAP_EVENT_26H) \ -__PMC_EV_ALIAS("L2_LOCK", IAP_EVENT_2BH) \ -__PMC_EV_ALIAS("L2_M_LINES_IN", IAP_EVENT_25H) \ -__PMC_EV_ALIAS("L2_M_LINES_OUT", IAP_EVENT_27H) \ -__PMC_EV_ALIAS("L2_NO_REQ", IAP_EVENT_32H) \ -__PMC_EV_ALIAS("L2_REJECT_BUSQ", IAP_EVENT_30H) \ -__PMC_EV_ALIAS("L2_RQSTS", IAP_EVENT_2EH) \ -__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.I_STATE", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.MESI", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \ -__PMC_EV_ALIAS("LOAD_BLOCK.L1D", IAP_EVENT_03H_20H) \ -__PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("LOAD_BLOCK.STA", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_04H) \ -__PMC_EV_ALIAS("LOAD_BLOCK.UNTIL_RETIRE", IAP_EVENT_03H_10H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_00H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_01H) \ -__PMC_EV_ALIAS("MACHINE_NUKES.MEM_ORDER", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACRO_INSTS.ALL_DECODED", IAP_EVENT_AAH_03H) \ -__PMC_EV_ALIAS("MACRO_INSTS.CISC_DECODED", IAP_EVENT_AAH_02H) \ -__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.RESET", IAP_EVENT_09H_01H) \ -__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.SUCCESS", IAP_EVENT_09H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_LINE_MISS", IAP_EVENT_CBH_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_MISS", IAP_EVENT_CBH_02H) \ -__PMC_EV_ALIAS("MUL", IAP_EVENT_12H_00H) \ -__PMC_EV_ALIAS("MUL.AR", IAP_EVENT_12H_81H) \ -__PMC_EV_ALIAS("MUL.S", IAP_EVENT_12H_01H) \ -__PMC_EV_ALIAS("PAGE_WALKS.CYCLES", IAP_EVENT_0CH_03H) \ -__PMC_EV_ALIAS("PAGE_WALKS.WALKS", IAP_EVENT_0CH_03H) \ -__PMC_EV_ALIAS("PREFETCH.PREFETCHNTA", IAP_EVENT_07H_08H) \ -__PMC_EV_ALIAS("PREFETCH.PREFETCHT0", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("PREFETCH.SW_L2", IAP_EVENT_07H_06H) \ -__PMC_EV_ALIAS("PREF_RQSTS_DN", IAP_EVENT_F8H_00H) \ -__PMC_EV_ALIAS("PREF_RQSTS_UP", IAP_EVENT_F0H_00H) \ -__PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ -__PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("RAT_STALLS.FPSW", IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("RAT_STALLS.PARTIAL_CYCLES", IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_DCH_1FH) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.BR_MISS_CLEAR", IAP_EVENT_DCH_10H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_DCH_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.LD_ST", IAP_EVENT_DCH_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_DCH_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_DCH_02H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED", IAP_EVENT_A0H_00H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT2", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT3", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT4", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT5", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("SB_DRAIN_CYCLES", IAP_EVENT_04H_01H) \ -__PMC_EV_ALIAS("SEGMENT_REG_LOADS.ANY", IAP_EVENT_06H_00H) \ -__PMC_EV_ALIAS("SEG_REG_RENAMES.ANY", IAP_EVENT_D5H_0FH) \ -__PMC_EV_ALIAS("SEG_REG_RENAMES.DS", IAP_EVENT_D5H_02H) \ -__PMC_EV_ALIAS("SEG_REG_RENAMES.ES", IAP_EVENT_D5H_01H) \ -__PMC_EV_ALIAS("SEG_REG_RENAMES.FS", IAP_EVENT_D5H_04H) \ -__PMC_EV_ALIAS("SEG_REG_RENAMES.GS", IAP_EVENT_D5H_08H) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS.ANY", IAP_EVENT_D4H_0FH) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS.DS", IAP_EVENT_D4H_02H) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS.ES", IAP_EVENT_D4H_01H) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS.FS", IAP_EVENT_D4H_04H) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS.GS", IAP_EVENT_D4H_08H) \ -__PMC_EV_ALIAS("SIMD_ASSIST", IAP_EVENT_CDH_00H) \ -__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", \ - IAP_EVENT_CAH_04H) \ -__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_SINGLE", \ - IAP_EVENT_CAH_01H) \ -__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", \ - IAP_EVENT_CAH_08H) \ -__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", \ - IAP_EVENT_CAH_02H) \ -__PMC_EV_ALIAS("SIMD_INSTR_RETIRED", IAP_EVENT_CEH_00H) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.ANY", IAP_EVENT_C7H_1FH) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.VECTOR", IAP_EVENT_C7H_10H) \ -__PMC_EV_ALIAS("SIMD_SAT_INSTR_RETIRED", IAP_EVENT_CFH_00H) \ -__PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC.AR", IAP_EVENT_B1H_80H) \ -__PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC.S", IAP_EVENT_B1H_00H) \ -__PMC_EV_ALIAS("SIMD_UOPS_EXEC.AR", IAP_EVENT_B0H_80H) \ -__PMC_EV_ALIAS("SIMD_UOPS_EXEC.S", IAP_EVENT_B0H_00H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", IAP_EVENT_B3H_A0H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", IAP_EVENT_B3H_20H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL.AR", IAP_EVENT_B3H_90H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL.S", IAP_EVENT_B3H_10H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL.AR", IAP_EVENT_B3H_81H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL.S", IAP_EVENT_B3H_01H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK.AR", IAP_EVENT_B3H_84H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK.S", IAP_EVENT_B3H_04H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT.AR", IAP_EVENT_B3H_82H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT.S", IAP_EVENT_B3H_02H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK.AR", IAP_EVENT_B3H_88H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK.S", IAP_EVENT_B3H_08H) \ -__PMC_EV_ALIAS("SNOOP_STALL_DRV", IAP_EVENT_7EH) \ -__PMC_EV_ALIAS("SSE_PRE_EXEC.L2", IAP_EVENT_07H_02H) \ -__PMC_EV_ALIAS("SSE_PRE_EXEC.STORES", IAP_EVENT_07H_03H) \ -__PMC_EV_ALIAS("SSE_PRE_MISS.L1", IAP_EVENT_4BH_01H) \ -__PMC_EV_ALIAS("SSE_PRE_MISS.L2", IAP_EVENT_4BH_02H) \ -__PMC_EV_ALIAS("SSE_PRE_MISS.NTA", IAP_EVENT_4BH_00H) \ -__PMC_EV_ALIAS("STORE_BLOCK.ORDER", IAP_EVENT_04H_02H) \ -__PMC_EV_ALIAS("STORE_BLOCK.SNOOP", IAP_EVENT_04H_08H) \ -__PMC_EV_ALIAS("STORE_FORWARDS.GOOD", IAP_EVENT_02H_81H) \ -__PMC_EV_ALIAS("THERMAL_TRIP", IAP_EVENT_3BH_C0H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_10H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.FUSED", IAP_EVENT_C2H_07H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.LD_IND_BR", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSION", IAP_EVENT_C2H_04H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.NON_FUSED", IAP_EVENT_C2H_08H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.STD_STA", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("X87_COMP_OPS_EXE.ANY.AR", IAP_EVENT_10H_81H) \ -__PMC_EV_ALIAS("X87_COMP_OPS_EXE.ANY.S", IAP_EVENT_10H_01H) \ -__PMC_EV_ALIAS("X87_OPS_RETIRED.ANY", IAP_EVENT_C1H_FEH) \ -__PMC_EV_ALIAS("X87_OPS_RETIRED.FXCH", IAP_EVENT_C1H_01H) - -/* - * Aliases for Atom Silvermont PMCs. - */ -#define __PMC_EV_ALIAS_ATOM_SILVERMONT() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("REHABQ.LD_BLOCK_ST_FORWARD", IAP_EVENT_03H_01H) \ -__PMC_EV_ALIAS("REHABQ.LD_BLOCK_STD_NOTREADY", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("REHABQ.ST_SPLITS", IAP_EVENT_03H_04H) \ -__PMC_EV_ALIAS("REHABQ.LD_SPLITS", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("REHABQ.LOCK", IAP_EVENT_03H_10H) \ -__PMC_EV_ALIAS("REHABQ.STA_FULL", IAP_EVENT_03H_20H) \ -__PMC_EV_ALIAS("REHABQ.ANY_LD", IAP_EVENT_03H_40H) \ -__PMC_EV_ALIAS("REHABQ.ANY_ST", IAP_EVENT_03H_80H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.L1_MISS_LOADS", IAP_EVENT_04H_01H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.L2_HIT_LOADS", IAP_EVENT_04H_02H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.L2_MISS_LOADS", IAP_EVENT_04H_04H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.DTLB_MISS_LOADS", IAP_EVENT_04H_08H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.UTLB_MISS", IAP_EVENT_04H_10H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.HITM", IAP_EVENT_04H_20H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_04H_40H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_04H_80H) \ -__PMC_EV_ALIAS("PAGE_WALKS.D_SIDE_CYCLES", IAP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("PAGE_WALKS.I_SIDE_CYCLES", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("PAGE_WALKS.WALKS", IAP_EVENT_05H_03H) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("L2_REJECT_XQ.ALL", IAP_EVENT_30H_00H) \ -__PMC_EV_ALIAS("CORE_REJECT_L2Q.ALL", IAP_EVENT_31H_00H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("ICACHE.HIT", IAP_EVENT_80H_01H) \ -__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("ICACHE.ACCESSES", IAP_EVENT_80H_03H) \ -__PMC_EV_ALIAS("NIP_STALL.ICACHE_MISS", IAP_EVENT_B6H_04H) \ -__PMC_EV_ALIAS("OFFCORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("OFFCORE_RESPONSE_1", IAP_EVENT_B7H_02H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.MS", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_10H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_01H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.FP_ASSIST", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.ALL", IAP_EVENT_C3H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.JCC", IAP_EVENT_C4H_7EH) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_BFH) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NON_RETURN_IND", IAP_EVENT_C4H_EBH) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.RETURN", IAP_EVENT_C4H_F7H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CALL", IAP_EVENT_C4H_F9H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.IND_CALL", IAP_EVENT_C4H_FBH) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.REL_CALL", IAP_EVENT_C4H_FDH) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN_JCC", IAP_EVENT_C4H_FEH) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.JCC", IAP_EVENT_C5H_7EH) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.FAR", IAP_EVENT_C5H_BFH) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NON_RETURN_IND", IAP_EVENT_C5H_EBH) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.RETURN", IAP_EVENT_C5H_F7H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CALL", IAP_EVENT_C5H_F9H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.IND_CALL", IAP_EVENT_C5H_FBH) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.REL_CALL", IAP_EVENT_C5H_FDH) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN_JCC", IAP_EVENT_C5H_FEH) \ -__PMC_EV_ALIAS("NO_ALLOC_CYCLES.ROB_FULL", IAP_EVENT_CAH_01H) \ -__PMC_EV_ALIAS("NO_ALLOC_CYCLES.RAT_STALL", IAP_EVENT_CAH_20H) \ -__PMC_EV_ALIAS("NO_ALLOC_CYCLES.ALL", IAP_EVENT_CAH_3FH) \ -__PMC_EV_ALIAS("NO_ALLOC_CYCLES.NOT_DELIVERED", IAP_EVENT_CAH_50H) \ -__PMC_EV_ALIAS("RS_FULL_STALL.MEC", IAP_EVENT_CBH_01H) \ -__PMC_EV_ALIAS("RS_FULL_STALL.ALL", IAP_EVENT_CBH_1FH) \ -__PMC_EV_ALIAS("CYCLES_DIV_BUSY.ANY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("BACLEARS.ALL", IAP_EVENT_E6H_01H) \ -__PMC_EV_ALIAS("BACLEARS.RETURN", IAP_EVENT_E6H_08H) \ -__PMC_EV_ALIAS("BACLEARS.COND", IAP_EVENT_E6H_10H) \ -__PMC_EV_ALIAS("MS_DECODED.MS_ENTRY", IAP_EVENT_E7H_01H) - -/* - * Aliases for Broadwell PMC events. - */ -#define __PMC_EV_ALIAS_BROADWELL() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \ -__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ -__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \ -__PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \ -__PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \ -__PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ - IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \ - IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ -__PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H) \ -__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \ - IAP_EVENT_58H_04H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \ - IAP_EVENT_58H_08H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ -__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \ - IAP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ - IAP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ -__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ -__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ -__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ -__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ -__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ -__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ -__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXE.COND", IAP_EVENT_89H_01H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ -__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_U_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ -__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ -__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_HIT", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ - IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ - IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ - IAP_EVENT_D3H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ -__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ -__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ -__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ -__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ -__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H) - -/* - * Aliases for Broadwell XEON PMC events. - */ -#define __PMC_EV_ALIAS_BROADWELL_XEON() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \ -__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ -__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) /**/ \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \ -__PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \ -__PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \ -__PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ - IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \ - IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ -__PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H) \ -__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \ - IAP_EVENT_58H_04H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \ - IAP_EVENT_58H_08H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ -__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \ - IAP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ - IAP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ -__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ -__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ -__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ -__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ -__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ -__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ -__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXE.COND", IAP_EVENT_89H_01H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ -__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_U_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ -__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ -__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_HIT", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ - IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ - IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ - IAP_EVENT_D3H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ -__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ -__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ -__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ -__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ -__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H) - -/* - * Alisases for Skylake - */ -#define __PMC_EV_ALIAS_SKYLAKE() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_PENDING", IAP_EVENT_08H_10H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_20H) \ -__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_01H) \ -__PMC_EV_ALIAS("INT_MISC.CLEAR_RESTEER_CYCLES", IAP_EVENT_0DH_80H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.VECTORS_WIDTH_MISMATCH", IAP_EVENT_0EH_02H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ -__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_22H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_24H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_MISS", IAP_EVENT_24H_27H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_38H) \ -__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_3FH) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_42H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_44H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_D8H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_REFERENCES", IAP_EVENT_24H_E7H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \ -__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_EFH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", \ - IAP_EVENT_3CH_02H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.FB_FULL", IAP_EVENT_48H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ - IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_0EH) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_PENDING", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_20H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_01H) \ -__PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H) \ -__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \ - IAP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", \ - IAP_EVENT_60H_10H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ -__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ -__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ -__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ -__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ -__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ -__PMC_EV_ALIAS("ICACHE_16B.IFDATA_STALL", IAP_EVENT_80H_04H) \ -__PMC_EV_ALIAS("ICACHE_64B.IFTAG_HIT", IAP_EVENT_83H_01H) \ -__PMC_EV_ALIAS("ICACHE_64B.IFTAG_MISS", IAP_EVENT_83H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_0EH) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_PENDING", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_20H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_MISS", IAP_EVENT_A3H_01H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L3_MISS", IAP_EVENT_A3H_02H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_TOTAL", IAP_EVENT_A3H_04H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L2_MISS", IAP_EVENT_A3H_05H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L3_MISS", IAP_EVENT_A3H_06H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_MISS", IAP_EVENT_A3H_08H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L1D_MISS", IAP_EVENT_A3H_0CH) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_MEM_ANY", IAP_EVENT_A3H_10H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_MEM_ANY", IAP_EVENT_A3H_14H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.EXE_BOUND_0_PORTS", IAP_EVENT_A6H_01H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.1_PORTS_UTIL", IAP_EVENT_A6H_02H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.2_PORTS_UTIL", IAP_EVENT_A6H_04H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.3_PORTS_UTIL", IAP_EVENT_A6H_08H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.4_PORTS_UTIL", IAP_EVENT_A6H_10H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.BOUND_ON_STORES", IAP_EVENT_A6H_40H) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ -__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", \ - IAP_EVENT_B0H_10H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_REQUESTS", IAP_EVENT_B0H_80H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.X87", IAP_EVENT_B1H_10H) \ -__PMC_EV_ALIAS("OFF_CORE_REQUEST_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.ANY", IAP_EVENT_C1H_3FH) \ -__PMC_EV_ALIAS("UOPS_RETIRED.STALL_CYCLES", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_U_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_TAKEN", IAP_EVENT_C5H_20H) \ -__PMC_EV_ALIAS("FRONTEND_RETIRED.DSB_MISS", IAP_EVENT_C6H_01H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_01H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.128B_PACKED_DOUBLE", \ - IAP_EVENT_C7H_04H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.128B_PACKED_SINGLE", \ - IAP_EVENT_C7H_08H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.256B_PACKED_DOUBLE", \ - IAP_EVENT_C7H_10H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.256B_PACKED_SINGLE", \ - IAP_EVENT_C7H_20H) \ -__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ -__PMC_EV_ALIAS("HW_INTERRUPTS.RECEIVED", IAP_EVENT_CBH_01H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_HIT", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.FB_HIT", IAP_EVENT_D1H_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", \ - IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", \ - IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) - -/* - * Alisases for Skylake Xeon (Intel Xeon Scalable Processors). - */ -#define __PMC_EV_ALIAS_SKYLAKE_XEON() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", \ - IAP_EVENT_08H_04H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_1G", IAP_EVENT_08H_08H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_PENDING", IAP_EVENT_08H_10H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_20H) \ -__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_01H) \ -__PMC_EV_ALIAS("INT_MISC.CLEAR_RESTEER_CYCLES", IAP_EVENT_0DH_80H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.VECTORS_WIDTH_MISMATCH", IAP_EVENT_0EH_02H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ -__PMC_EV_ALIAS("ARITH.DIVIDER_ACTIVE", IAP_EVENT_14H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_22H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_24H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_MISS", IAP_EVENT_24H_27H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_38H) \ -__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_3FH) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_42H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_44H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_D8H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_REFERENCES", IAP_EVENT_24H_E7H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \ -__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ -__PMC_EV_ALIAS("CORE_POWER.LVL0_TURBO_LICENSE", IAP_EVENT_28H_07H) \ -__PMC_EV_ALIAS("CORE_POWER.LVL1_TURBO_LICENSE", IAP_EVENT_28H_18H) \ -__PMC_EV_ALIAS("CORE_POWER.LVL2_TURBO_LICENSE", IAP_EVENT_28H_20H) \ -__PMC_EV_ALIAS("CORE_POWER.THROTTLE", IAP_EVENT_28H_40H) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", \ - IAP_EVENT_3CH_02H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.FB_FULL", IAP_EVENT_48H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ - IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \ - IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", \ - IAP_EVENT_49H_04H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_1G", \ - IAP_EVENT_49H_08H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_0EH) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_PENDING", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_20H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ -__PMC_EV_ALIAS("EPT.WALK_PENDING", IAP_EVENT_4FH_10H) \ -__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("TX_MEM.ABORT_CONFLICT", IAP_EVENT_54H_01H) \ -__PMC_EV_ALIAS("TX_MEM.ABORT_CAPACITY", IAP_EVENT_54H_02H) \ -__PMC_EV_ALIAS("TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", \ - IAP_EVENT_54H_04H) \ -__PMC_EV_ALIAS("TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", \ - IAP_EVENT_54H_08H) \ -__PMC_EV_ALIAS("TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", \ - IAP_EVENT_54H_10H) \ -__PMC_EV_ALIAS("TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", \ - IAP_EVENT_54H_20H) \ -__PMC_EV_ALIAS("TX_MEM.ABORT_HLE_ELISION_BUFFER_FULL", \ - IAP_EVENT_54H_40H) \ -__PMC_EV_ALIAS("TX_EXEC.MISC1", IAP_EVENT_5DH_01H) \ -__PMC_EV_ALIAS("TX_EXEC.MISC2", IAP_EVENT_5DH_02H) \ -__PMC_EV_ALIAS("TX_EXEC.MISC3", IAP_EVENT_5DH_04H) \ -__PMC_EV_ALIAS("TX_EXEC.MISC4", IAP_EVENT_5DH_08H) \ -__PMC_EV_ALIAS("TX_EXEC.MISC5", IAP_EVENT_5DH_10H) \ -__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \ - IAP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", \ - IAP_EVENT_60H_10H) \ -__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ -__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ -__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ -__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ -__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ -__PMC_EV_ALIAS("ICACHE_16B.IFDATA_STALL", IAP_EVENT_80H_04H) \ -__PMC_EV_ALIAS("ICACHE_64B.IFTAG_HIT", IAP_EVENT_83H_01H) \ -__PMC_EV_ALIAS("ICACHE_64B.IFTAG_MISS", IAP_EVENT_83H_02H) \ -__PMC_EV_ALIAS("ICACHE_64B.IFTAG_STALL", IAP_EVENT_83H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_2M_4M", IAP_EVENT_85H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_1G", IAP_EVENT_85H_08H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_0EH) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_PENDING", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_20H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_6", IAP_EVENT_A1H_40H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_7", IAP_EVENT_A1H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_MISS", IAP_EVENT_A3H_01H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L3_MISS", IAP_EVENT_A3H_02H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_TOTAL", IAP_EVENT_A3H_04H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L2_MISS", IAP_EVENT_A3H_05H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L3_MISS", IAP_EVENT_A3H_06H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_MISS", IAP_EVENT_A3H_08H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L1D_MISS", IAP_EVENT_A3H_0CH) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_MEM_ANY", IAP_EVENT_A3H_10H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_MEM_ANY", IAP_EVENT_A3H_14H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.EXE_BOUND_0_PORTS", IAP_EVENT_A6H_01H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.1_PORTS_UTIL", IAP_EVENT_A6H_02H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.2_PORTS_UTIL", IAP_EVENT_A6H_04H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.3_PORTS_UTIL", IAP_EVENT_A6H_08H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.4_PORTS_UTIL", IAP_EVENT_A6H_10H) \ -__PMC_EV_ALIAS("EXE_ACTIVITY.BOUND_ON_STORES", IAP_EVENT_A6H_40H) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ -__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", \ - IAP_EVENT_B0H_10H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_REQUESTS", IAP_EVENT_B0H_80H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.X87", IAP_EVENT_B1H_10H) \ -__PMC_EV_ALIAS("OFF_CORE_REQUEST_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.ANY", IAP_EVENT_C1H_3FH) \ -__PMC_EV_ALIAS("UOPS_RETIRED.STALL_CYCLES", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.COUNT", IAP_EVENT_C3H_01H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_TAKEN", IAP_EVENT_C5H_20H) \ -__PMC_EV_ALIAS("FRONTEND_RETIRED.DSB_MISS", IAP_EVENT_C6H_01H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_01H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.128B_PACKED_DOUBLE", \ - IAP_EVENT_C7H_04H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.128B_PACKED_SINGLE", \ - IAP_EVENT_C7H_08H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.256B_PACKED_DOUBLE", \ - IAP_EVENT_C7H_10H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.256B_PACKED_SINGLE", \ - IAP_EVENT_C7H_20H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.512B_PACKED_DOUBLE", \ - IAP_EVENT_C7H_40H) \ -__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.512B_PACKED_SINGLE", \ - IAP_EVENT_C7H_80H) \ -__PMC_EV_ALIAS("HLE_RETIRED.START", IAP_EVENT_C8H_01H) \ -__PMC_EV_ALIAS("HLE_RETIRED.COMMIT", IAP_EVENT_C8H_02H) \ -__PMC_EV_ALIAS("HLE_RETIRED.ABORTED", IAP_EVENT_C8H_04H) \ -__PMC_EV_ALIAS("HLE_RETIRED.ABORTED_MEM", IAP_EVENT_C8H_08H) \ -__PMC_EV_ALIAS("HLE_RETIRED.ABORTED_TIMER", IAP_EVENT_C8H_10H) \ -__PMC_EV_ALIAS("HLE_RETIRED.ABORTED_UNFRIENDLY", IAP_EVENT_C8H_20H) \ -__PMC_EV_ALIAS("HLE_RETIRED.ABORTED_MEMTYPE", IAP_EVENT_C8H_40H) \ -__PMC_EV_ALIAS("HLE_RETIRED.ABORTED_EVENTS", IAP_EVENT_C8H_80H) \ -__PMC_EV_ALIAS("RTM_RETIRED.START", IAP_EVENT_C9H_01H) \ -__PMC_EV_ALIAS("RTM_RETIRED.COMMIT", IAP_EVENT_C9H_02H) \ -__PMC_EV_ALIAS("RTM_RETIRED.ABORTED", IAP_EVENT_C9H_04H) \ -__PMC_EV_ALIAS("RTM_RETIRED.ABORTED_MEM", IAP_EVENT_C9H_08H) \ -__PMC_EV_ALIAS("RTM_RETIRED.ABORTED_TIMER", IAP_EVENT_C9H_10H) \ -__PMC_EV_ALIAS("RTM_RETIRED.ABORTED_UNFRIENDLY", IAP_EVENT_C9H_20H) \ -__PMC_EV_ALIAS("RTM_RETIRED.ABORTED_MEMTYPE", IAP_EVENT_C9H_40H) \ -__PMC_EV_ALIAS("RTM_RETIRED.ABORTED_EVENTS", IAP_EVENT_C9H_80H) \ -__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ -__PMC_EV_ALIAS("HW_INTERRUPTS.RECEIVED", IAP_EVENT_CBH_01H) \ -__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_HIT", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.FB_HIT", IAP_EVENT_D1H_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", \ - IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", \ - IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", \ - IAP_EVENT_D3H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", \ - IAP_EVENT_D3H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", \ - IAP_EVENT_D3H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", \ - IAP_EVENT_D3H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_MISC_RETIRED.UC", IAP_EVENT_D4H_04H) \ -__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_1FH) \ -__PMC_EV_ALIAS("L2_LINES_OUT.SILENT", IAP_EVENT_F2H_01H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.NON_SILENT", IAP_EVENT_F2H_02H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.USELESS_PREF", IAP_EVENT_F2H_04H) \ -__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) \ -__PMC_EV_ALIAS("IDI_MISC.WB_UPGRADE", IAP_EVENT_FEH_02H) \ -__PMC_EV_ALIAS("IDI_MISC.WB_DOWNGRADE", IAP_EVENT_FEH_04H) - -/* - * Aliases for Core PMC events. - */ -#define __PMC_EV_ALIAS_CORE() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("BAClears", IAP_EVENT_E6H_00H) \ -__PMC_EV_ALIAS("BTB_Misses", IAP_EVENT_E2H_00H) \ -__PMC_EV_ALIAS("Br_BAC_Missp_Exec", IAP_EVENT_8AH_00H) \ -__PMC_EV_ALIAS("Br_Bogus", IAP_EVENT_E4H_00H) \ -__PMC_EV_ALIAS("Br_Call_Exec", IAP_EVENT_92H_00H) \ -__PMC_EV_ALIAS("Br_Call_Missp_Exec", IAP_EVENT_93H_00H) \ -__PMC_EV_ALIAS("Br_Cnd_Exec", IAP_EVENT_8BH_00H) \ -__PMC_EV_ALIAS("Br_Cnd_Missp_Exec", IAP_EVENT_8CH_00H) \ -__PMC_EV_ALIAS("Br_Ind_Call_Exec", IAP_EVENT_94H_00H) \ -__PMC_EV_ALIAS("Br_Ind_Exec", IAP_EVENT_8DH_00H) \ -__PMC_EV_ALIAS("Br_Ind_Missp_Exec", IAP_EVENT_8EH_00H) \ -__PMC_EV_ALIAS("Br_Inst_Exec", IAP_EVENT_88H_00H) \ -__PMC_EV_ALIAS("Br_Instr_Decoded", IAP_EVENT_E0H_00H) \ -__PMC_EV_ALIAS("Br_Instr_Ret", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("Br_MisPred_Ret", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("Br_MisPred_Taken_Ret", IAP_EVENT_CAH_00H) \ -__PMC_EV_ALIAS("Br_Missp_Exec", IAP_EVENT_89H_00H) \ -__PMC_EV_ALIAS("Br_Ret_BAC_Missp_Exec", IAP_EVENT_91H_00H) \ -__PMC_EV_ALIAS("Br_Ret_Exec", IAP_EVENT_8FH_00H) \ -__PMC_EV_ALIAS("Br_Ret_Missp_Exec", IAP_EVENT_90H_00H) \ -__PMC_EV_ALIAS("Br_Taken_Ret", IAP_EVENT_C9H_00H) \ -__PMC_EV_ALIAS("Bus_BNR_Clocks", IAP_EVENT_61H_00H) \ -__PMC_EV_ALIAS("Bus_DRDY_Clocks", IAP_EVENT_62H_00H) \ -__PMC_EV_ALIAS("Bus_Data_Rcv", IAP_EVENT_64H_40H) \ -__PMC_EV_ALIAS("Bus_Locks_Clocks", IAP_EVENT_63H) \ -__PMC_EV_ALIAS("Bus_Not_In_Use", IAP_EVENT_7DH) \ -__PMC_EV_ALIAS("Bus_Req_Outstanding", IAP_EVENT_60H) \ -__PMC_EV_ALIAS("Bus_Snoop_Stall", IAP_EVENT_7EH_00H) \ -__PMC_EV_ALIAS("Bus_Snoops", IAP_EVENT_77H) \ -__PMC_EV_ALIAS("Bus_Trans_Any", IAP_EVENT_70H) \ -__PMC_EV_ALIAS("Bus_Trans_Brd", IAP_EVENT_65H) \ -__PMC_EV_ALIAS("Bus_Trans_Burst", IAP_EVENT_6EH) \ -__PMC_EV_ALIAS("Bus_Trans_Def", IAP_EVENT_6DH) \ -__PMC_EV_ALIAS("Bus_Trans_IO", IAP_EVENT_6CH) \ -__PMC_EV_ALIAS("Bus_Trans_Ifetch", IAP_EVENT_68H) \ -__PMC_EV_ALIAS("Bus_Trans_Inval", IAP_EVENT_69H) \ -__PMC_EV_ALIAS("Bus_Trans_Mem", IAP_EVENT_6FH) \ -__PMC_EV_ALIAS("Bus_Trans_P", IAP_EVENT_6BH) \ -__PMC_EV_ALIAS("Bus_Trans_Pwr", IAP_EVENT_6AH) \ -__PMC_EV_ALIAS("Bus_Trans_RFO", IAP_EVENT_66H) \ -__PMC_EV_ALIAS("Bus_Trans_WB", IAP_EVENT_67H) \ -__PMC_EV_ALIAS("Cycles_Div_Busy", IAP_EVENT_14H_00H) \ -__PMC_EV_ALIAS("Cycles_Int_Masked", IAP_EVENT_C6H_00H) \ -__PMC_EV_ALIAS("Cycles_Int_Pending_Masked", IAP_EVENT_C7H_00H) \ -__PMC_EV_ALIAS("DCU_Snoop_To_Share", IAP_EVENT_78H) \ -__PMC_EV_ALIAS("DCache_Cache_LD", IAP_EVENT_40H) \ -__PMC_EV_ALIAS("DCache_Cache_Lock", IAP_EVENT_42H) \ -__PMC_EV_ALIAS("DCache_Cache_ST", IAP_EVENT_41H) \ -__PMC_EV_ALIAS("DCache_M_Evict", IAP_EVENT_47H_00H) \ -__PMC_EV_ALIAS("DCache_M_Repl", IAP_EVENT_46H_00H) \ -__PMC_EV_ALIAS("DCache_Pend_Miss", IAP_EVENT_48H_00H) \ -__PMC_EV_ALIAS("DCache_Repl", IAP_EVENT_45H_0FH) \ -__PMC_EV_ALIAS("Data_Mem_Cache_Ref", IAP_EVENT_44H_02H) \ -__PMC_EV_ALIAS("Data_Mem_Ref", IAP_EVENT_43H_01H) \ -__PMC_EV_ALIAS("Dbus_Busy", IAP_EVENT_22H) \ -__PMC_EV_ALIAS("Dbus_Busy_Rd", IAP_EVENT_23H) \ -__PMC_EV_ALIAS("Div", IAP_EVENT_13H_00H) \ -__PMC_EV_ALIAS("Dtlb_Miss", IAP_EVENT_49H_00H) \ -__PMC_EV_ALIAS("ESP_Uops", IAP_EVENT_D7H_00H) \ -__PMC_EV_ALIAS("EST_Trans", IAP_EVENT_3AH) \ -__PMC_EV_ALIAS("FP_Assist", IAP_EVENT_11H_00H) \ -__PMC_EV_ALIAS("FP_Comp_Instr_Ret", IAP_EVENT_C1H_00H) \ -__PMC_EV_ALIAS("FP_Comps_Op_Exe", IAP_EVENT_10H_00H) \ -__PMC_EV_ALIAS("FP_MMX_Trans", IAP_EVENT_CCH_01H) \ -__PMC_EV_ALIAS("Fused_Ld_Uops_Ret", IAP_EVENT_DAH_01H) \ -__PMC_EV_ALIAS("Fused_St_Uops_Ret", IAP_EVENT_DAH_02H) \ -__PMC_EV_ALIAS("Fused_Uops_Ret", IAP_EVENT_DAH_00H) \ -__PMC_EV_ALIAS("HW_Int_Rx", IAP_EVENT_C8H_00H) \ -__PMC_EV_ALIAS("ICache_Misses", IAP_EVENT_81H_00H) \ -__PMC_EV_ALIAS("ICache_Reads", IAP_EVENT_80H_00H) \ -__PMC_EV_ALIAS("IFU_Mem_Stall", IAP_EVENT_86H_00H) \ -__PMC_EV_ALIAS("ILD_Stall", IAP_EVENT_87H_00H) \ -__PMC_EV_ALIAS("ITLB_Misses", IAP_EVENT_85H_00H) \ -__PMC_EV_ALIAS("Instr_Decoded", IAP_EVENT_D0H_00H) \ -__PMC_EV_ALIAS("Instr_Ret", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("L1_Pref_Req", IAP_EVENT_4FH_00H) \ -__PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \ -__PMC_EV_ALIAS("L2_IFetch", IAP_EVENT_28H) \ -__PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \ -__PMC_EV_ALIAS("L2_Lines_In", IAP_EVENT_24H) \ -__PMC_EV_ALIAS("L2_Lines_Out", IAP_EVENT_26H) \ -__PMC_EV_ALIAS("L2_M_Lines_In", IAP_EVENT_25H) \ -__PMC_EV_ALIAS("L2_M_Lines_Out", IAP_EVENT_27H) \ -__PMC_EV_ALIAS("L2_No_Request_Cycles", IAP_EVENT_32H) \ -__PMC_EV_ALIAS("L2_Reject_Cycles", IAP_EVENT_30H) \ -__PMC_EV_ALIAS("L2_Rqsts", IAP_EVENT_2EH) \ -__PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \ -__PMC_EV_ALIAS("LD_Blocks", IAP_EVENT_03H_00H) \ -__PMC_EV_ALIAS("LLC_Misses", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("LLC_Reference", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("MMX_Assist", IAP_EVENT_CDH_00H) \ -__PMC_EV_ALIAS("MMX_FP_Trans", IAP_EVENT_CCH_00H) \ -__PMC_EV_ALIAS("MMX_Instr_Exec", IAP_EVENT_B0H_00H) \ -__PMC_EV_ALIAS("MMX_Instr_Ret", IAP_EVENT_CEH_00H) \ -__PMC_EV_ALIAS("Misalign_Mem_Ref", IAP_EVENT_05H_00H) \ -__PMC_EV_ALIAS("Mul", IAP_EVENT_12H_00H) \ -__PMC_EV_ALIAS("NonHlt_Ref_Cycles", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("Pref_Rqsts_Dn", IAP_EVENT_F8H_00H) \ -__PMC_EV_ALIAS("Pref_Rqsts_Up", IAP_EVENT_F0H_00H) \ -__PMC_EV_ALIAS("Resource_Stall", IAP_EVENT_A2H_00H) \ -__PMC_EV_ALIAS("SD_Drains", IAP_EVENT_04H_00H) \ -__PMC_EV_ALIAS("SIMD_FP_DP_P_Comp_Ret", IAP_EVENT_D9H_02H) \ -__PMC_EV_ALIAS("SIMD_FP_DP_P_Ret", IAP_EVENT_D8H_02H) \ -__PMC_EV_ALIAS("SIMD_FP_DP_S_Comp_Ret", IAP_EVENT_D9H_03H) \ -__PMC_EV_ALIAS("SIMD_FP_DP_S_Ret", IAP_EVENT_D8H_03H) \ -__PMC_EV_ALIAS("SIMD_FP_SP_P_Comp_Ret", IAP_EVENT_D9H_00H) \ -__PMC_EV_ALIAS("SIMD_FP_SP_Ret", IAP_EVENT_D8H_00H) \ -__PMC_EV_ALIAS("SIMD_FP_SP_S_Comp_Ret", IAP_EVENT_D9H_01H) \ -__PMC_EV_ALIAS("SIMD_FP_SP_S_Ret", IAP_EVENT_D8H_01H) \ -__PMC_EV_ALIAS("SIMD_Int_128_Ret", IAP_EVENT_D8H_04H) \ -__PMC_EV_ALIAS("SIMD_Int_Pari_Exec", IAP_EVENT_B3H_20H) \ -__PMC_EV_ALIAS("SIMD_Int_Pck_Exec", IAP_EVENT_B3H_04H) \ -__PMC_EV_ALIAS("SIMD_Int_Plog_Exec", IAP_EVENT_B3H_10H) \ -__PMC_EV_ALIAS("SIMD_Int_Pmul_Exec", IAP_EVENT_B3H_01H) \ -__PMC_EV_ALIAS("SIMD_Int_Psft_Exec", IAP_EVENT_B3H_02H) \ -__PMC_EV_ALIAS("SIMD_Int_Sat_Exec", IAP_EVENT_B1H_00H) \ -__PMC_EV_ALIAS("SIMD_Int_Upck_Exec", IAP_EVENT_B3H_08H) \ -__PMC_EV_ALIAS("SMC_Detected", IAP_EVENT_C3H_00H) \ -__PMC_EV_ALIAS("SSE_NTStores_Miss", IAP_EVENT_4BH_03H) \ -__PMC_EV_ALIAS("SSE_NTStores_Ret", IAP_EVENT_07H_03H) \ -__PMC_EV_ALIAS("SSE_PrefNta_Miss", IAP_EVENT_4BH_00H) \ -__PMC_EV_ALIAS("SSE_PrefNta_Ret", IAP_EVENT_07H_00H) \ -__PMC_EV_ALIAS("SSE_PrefT1_Miss", IAP_EVENT_4BH_01H) \ -__PMC_EV_ALIAS("SSE_PrefT1_Ret", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("SSE_PrefT2_Miss", IAP_EVENT_4BH_02H) \ -__PMC_EV_ALIAS("SSE_PrefT2_Ret", IAP_EVENT_07H_02H) \ -__PMC_EV_ALIAS("Seg_Reg_Loads", IAP_EVENT_06H_00H) \ -__PMC_EV_ALIAS("Serial_Execution_Cycles", IAP_EVENT_3CH_02H) \ -__PMC_EV_ALIAS("Thermal_Trip", IAP_EVENT_3BH_C0H) \ -__PMC_EV_ALIAS("Unfusion", IAP_EVENT_DBH_00H) \ -__PMC_EV_ALIAS("Unhalted_Core_Cycles", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("Uops_Ret", IAP_EVENT_C2H_00H) - -/* - * Aliases for Core2 PMC events. - */ -#define __PMC_EV_ALIAS_CORE2() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("BACLEARS", IAP_EVENT_E6H_00H) \ -__PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_00H) \ -__PMC_EV_ALIAS("BR_BAC_MISSP_EXEC", IAP_EVENT_8AH_00H) \ -__PMC_EV_ALIAS("BR_CALL_EXEC", IAP_EVENT_92H_00H) \ -__PMC_EV_ALIAS("BR_CALL_MISSP_EXEC", IAP_EVENT_93H_00H) \ -__PMC_EV_ALIAS("BR_CND_EXEC", IAP_EVENT_8BH_00H) \ -__PMC_EV_ALIAS("BR_CND_MISSP_EXEC", IAP_EVENT_8CH_00H) \ -__PMC_EV_ALIAS("BR_IND_CALL_EXEC", IAP_EVENT_94H_00H) \ -__PMC_EV_ALIAS("BR_IND_EXEC", IAP_EVENT_8DH_00H) \ -__PMC_EV_ALIAS("BR_IND_MISSP_EXEC", IAP_EVENT_8EH_00H) \ -__PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_00H) \ -__PMC_EV_ALIAS("BR_INST_EXEC", IAP_EVENT_88H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ANY", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_NOT_TAKEN", \ - IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_TAKEN", \ - IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_NOT_TAKEN", \ - IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_TAKEN", \ - IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN", IAP_EVENT_C4H_0CH) \ -__PMC_EV_ALIAS("BR_MISSP_EXEC", IAP_EVENT_89H_00H) \ -__PMC_EV_ALIAS("BR_RET_BAC_MISSP_EXEC", IAP_EVENT_91H_00H) \ -__PMC_EV_ALIAS("BR_RET_EXEC", IAP_EVENT_8FH_00H) \ -__PMC_EV_ALIAS("BR_RET_MISSP_EXEC", IAP_EVENT_90H_00H) \ -__PMC_EV_ALIAS("BR_TKN_BUBBLE_1", IAP_EVENT_97H_00H) \ -__PMC_EV_ALIAS("BR_TKN_BUBBLE_2", IAP_EVENT_98H_00H) \ -__PMC_EV_ALIAS("BUSQ_EMPTY", IAP_EVENT_7DH) \ -__PMC_EV_ALIAS("BUS_BNR_DRV", IAP_EVENT_61H) \ -__PMC_EV_ALIAS("BUS_DATA_RCV", IAP_EVENT_64H) \ -__PMC_EV_ALIAS("BUS_DRDY_CLOCKS", IAP_EVENT_62H) \ -__PMC_EV_ALIAS("BUS_HITM_DRV", IAP_EVENT_7BH) \ -__PMC_EV_ALIAS("BUS_HIT_DRV", IAP_EVENT_7AH) \ -__PMC_EV_ALIAS("BUS_IO_WAIT", IAP_EVENT_7FH) \ -__PMC_EV_ALIAS("BUS_LOCK_CLOCKS", IAP_EVENT_63H) \ -__PMC_EV_ALIAS("BUS_REQUEST_OUTSTANDING", \ - IAP_EVENT_60H) \ -__PMC_EV_ALIAS("BUS_TRANS_ANY", IAP_EVENT_70H) \ -__PMC_EV_ALIAS("BUS_TRANS_BRD", IAP_EVENT_65H) \ -__PMC_EV_ALIAS("BUS_TRANS_BURST", IAP_EVENT_6EH) \ -__PMC_EV_ALIAS("BUS_TRANS_DEF", IAP_EVENT_6DH) \ -__PMC_EV_ALIAS("BUS_TRANS_IFETCH", IAP_EVENT_68H) \ -__PMC_EV_ALIAS("BUS_TRANS_INVAL", IAP_EVENT_69H) \ -__PMC_EV_ALIAS("BUS_TRANS_IO", IAP_EVENT_6CH) \ -__PMC_EV_ALIAS("BUS_TRANS_MEM", IAP_EVENT_6FH) \ -__PMC_EV_ALIAS("BUS_TRANS_P", IAP_EVENT_6BH) \ -__PMC_EV_ALIAS("BUS_TRANS_PWR", IAP_EVENT_6AH) \ -__PMC_EV_ALIAS("BUS_TRANS_RFO", IAP_EVENT_66H) \ -__PMC_EV_ALIAS("BUS_TRANS_WB", IAP_EVENT_67H) \ -__PMC_EV_ALIAS("CMP_SNOOP", IAP_EVENT_78H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.BUS", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", \ - IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.NO_OTHER", \ - IAP_EVENT_3CH_02H) \ -__PMC_EV_ALIAS("CYCLES_DIV_BUSY", IAP_EVENT_14H_00H) \ -__PMC_EV_ALIAS("CYCLES_INT_MASKED", IAP_EVENT_C6H_01H) \ -__PMC_EV_ALIAS("CYCLES_INT_PENDING_AND_MASKED", \ - IAP_EVENT_C6H_02H) \ -__PMC_EV_ALIAS("CYCLES_L1I_MEM_STALLED", IAP_EVENT_86H_00H) \ -__PMC_EV_ALIAS("DELAYED_BYPASS.FP", IAP_EVENT_19H_00H) \ -__PMC_EV_ALIAS("DELAYED_BYPASS.LOAD", IAP_EVENT_19H_01H) \ -__PMC_EV_ALIAS("DELAYED_BYPASS.SIMD", IAP_EVENT_19H_02H) \ -__PMC_EV_ALIAS("DIV", IAP_EVENT_13H_00H) \ -__PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_08H_01H) \ -__PMC_EV_ALIAS("DTLB_MISSES.L0_MISS_LD", IAP_EVENT_08H_04H) \ -__PMC_EV_ALIAS("DTLB_MISSES.MISS_LD", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_MISSES.MISS_ST", IAP_EVENT_08H_08H) \ -__PMC_EV_ALIAS("EIST_TRANS", IAP_EVENT_3AH_00H) \ -__PMC_EV_ALIAS("ESP.ADDITIONS", IAP_EVENT_ABH_02H) \ -__PMC_EV_ALIAS("ESP.SYNCH", IAP_EVENT_ABH_01H) \ -__PMC_EV_ALIAS("EXT_SNOOP", IAP_EVENT_77H) \ -__PMC_EV_ALIAS("FP_ASSIST", IAP_EVENT_11H_00H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE", IAP_EVENT_10H_00H) \ -__PMC_EV_ALIAS("FP_MMX_TRANS_TO_FP", IAP_EVENT_CCH_02H) \ -__PMC_EV_ALIAS("FP_MMX_TRANS_TO_MMX", IAP_EVENT_CCH_01H) \ -__PMC_EV_ALIAS("HW_INT_RCV", IAP_EVENT_C8H_00H) \ -__PMC_EV_ALIAS("IDLE_DURING_DIV", IAP_EVENT_18H_00H) \ -__PMC_EV_ALIAS("ILD_STALL", IAP_EVENT_87H_00H) \ -__PMC_EV_ALIAS("INST_QUEUE.FULL", IAP_EVENT_83H_02H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.LOADS", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("INST_RETIRED.OTHER", IAP_EVENT_C0H_04H) \ -__PMC_EV_ALIAS("INST_RETIRED.STORES", IAP_EVENT_C0H_02H) \ -__PMC_EV_ALIAS("INST_RETIRED.VM_H", IAP_EVENT_C0H_08H) \ -__PMC_EV_ALIAS("ITLB.FLUSH", IAP_EVENT_82H_40H) \ -__PMC_EV_ALIAS("ITLB.LARGE_MISS", IAP_EVENT_82H_10H) \ -__PMC_EV_ALIAS("ITLB.MISSES", IAP_EVENT_82H_12H) \ -__PMC_EV_ALIAS("ITLB.SMALL_MISS", IAP_EVENT_82H_02H) \ -__PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C9H_00H) \ -__PMC_EV_ALIAS("L1D_ALL_CACHE_REF", IAP_EVENT_43H_02H) \ -__PMC_EV_ALIAS("L1D_ALL_REF", IAP_EVENT_43H_01H) \ -__PMC_EV_ALIAS("L1D_CACHE_LD", IAP_EVENT_40H) \ -__PMC_EV_ALIAS("L1D_CACHE_LOCK", IAP_EVENT_42H) \ -__PMC_EV_ALIAS("L1D_CACHE_LOCK_DURATION", IAP_EVENT_42H_10H) \ -__PMC_EV_ALIAS("L1D_CACHE_ST", IAP_EVENT_41H) \ -__PMC_EV_ALIAS("L1D_M_EVICT", IAP_EVENT_47H_00H) \ -__PMC_EV_ALIAS("L1D_M_REPL", IAP_EVENT_46H_00H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS", IAP_EVENT_48H_00H) \ -__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_10H) \ -__PMC_EV_ALIAS("L1D_REPL", IAP_EVENT_45H_0FH) \ -__PMC_EV_ALIAS("L1D_SPLIT.LOADS", IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("L1D_SPLIT.STORES", IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("L1I_MISSES", IAP_EVENT_81H_00H) \ -__PMC_EV_ALIAS("L1I_READS", IAP_EVENT_80H_00H) \ -__PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \ -__PMC_EV_ALIAS("L2_DBUS_BUSY_RD", IAP_EVENT_23H) \ -__PMC_EV_ALIAS("L2_IFETCH", IAP_EVENT_28H) \ -__PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \ -__PMC_EV_ALIAS("L2_LINES_IN", IAP_EVENT_24H) \ -__PMC_EV_ALIAS("L2_LINES_OUT", IAP_EVENT_26H) \ -__PMC_EV_ALIAS("L2_LOCK", IAP_EVENT_2BH) \ -__PMC_EV_ALIAS("L2_M_LINES_IN", IAP_EVENT_25H) \ -__PMC_EV_ALIAS("L2_M_LINES_OUT", IAP_EVENT_27H) \ -__PMC_EV_ALIAS("L2_NO_REQ", IAP_EVENT_32H) \ -__PMC_EV_ALIAS("L2_REJECT_BUSQ", IAP_EVENT_30H) \ -__PMC_EV_ALIAS("L2_RQSTS", IAP_EVENT_2EH) \ -__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.I_STATE", \ - IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.MESI", \ - IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \ -__PMC_EV_ALIAS("LOAD_BLOCK.L1D", IAP_EVENT_03H_20H) \ -__PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", \ - IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("LOAD_BLOCK.STA", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_04H) \ -__PMC_EV_ALIAS("LOAD_BLOCK.UNTIL_RETIRE", IAP_EVENT_03H_10H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_00H) \ -__PMC_EV_ALIAS("MACHINE_NUKES.MEM_ORDER", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACHINE_NUKES.SMC", IAP_EVENT_C3H_01H) \ -__PMC_EV_ALIAS("MACRO_INSTS.CISC_DECODED", IAP_EVENT_AAH_08H) \ -__PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_AAH_01H) \ -__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.RESET", \ - IAP_EVENT_09H_01H) \ -__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.SUCCESS", \ - IAP_EVENT_09H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", \ - IAP_EVENT_CBH_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_LINE_MISS", \ - IAP_EVENT_CBH_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_MISS", \ - IAP_EVENT_CBH_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_LINE_MISS", \ - IAP_EVENT_CBH_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_MISS", \ - IAP_EVENT_CBH_04H) \ -__PMC_EV_ALIAS("MUL", IAP_EVENT_12H_00H) \ -__PMC_EV_ALIAS("PAGE_WALKS.COUNT", IAP_EVENT_0CH_01H) \ -__PMC_EV_ALIAS("PAGE_WALKS.CYCLES", IAP_EVENT_0CH_02H) \ -__PMC_EV_ALIAS("PREF_RQSTS_DN", IAP_EVENT_F8H_00H) \ -__PMC_EV_ALIAS("PREF_RQSTS_UP", IAP_EVENT_F0H_00H) \ -__PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ -__PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("RAT_STALLS.FPSW", IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("RAT_STALLS.OTHER_SERIALIZATION_STALLS", \ - IAP_EVENT_D2H_10H) \ -__PMC_EV_ALIAS("RAT_STALLS.PARTIAL_CYCLES", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_DCH_1FH) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.BR_MISS_CLEAR", \ - IAP_EVENT_DCH_10H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_DCH_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.LD_ST", IAP_EVENT_DCH_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", \ - IAP_EVENT_DCH_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_DCH_02H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED", IAP_EVENT_A0H_00H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT2", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT3", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT4", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT5", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("SB_DRAIN_CYCLES", IAP_EVENT_04H_01H) \ -__PMC_EV_ALIAS("SEGMENT_REG_LOADS", IAP_EVENT_06H_00H) \ -__PMC_EV_ALIAS("SEG_REG_RENAMES.ANY", IAP_EVENT_D5H_0FH) \ -__PMC_EV_ALIAS("SEG_REG_RENAMES.DS", IAP_EVENT_D5H_02H) \ -__PMC_EV_ALIAS("SEG_REG_RENAMES.ES", IAP_EVENT_D5H_01H) \ -__PMC_EV_ALIAS("SEG_REG_RENAMES.FS", IAP_EVENT_D5H_04H) \ -__PMC_EV_ALIAS("SEG_REG_RENAMES.GS", IAP_EVENT_D5H_08H) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS.ANY", IAP_EVENT_D4H_0FH) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS.DS", IAP_EVENT_D4H_02H) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS.ES", IAP_EVENT_D4H_01H) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS.FS", IAP_EVENT_D4H_04H) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS.GS", IAP_EVENT_D4H_08H) \ -__PMC_EV_ALIAS("SIMD_ASSIST", IAP_EVENT_CDH_00H) \ -__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", \ - IAP_EVENT_CAH_04H) \ -__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_SINGLE", \ - IAP_EVENT_CAH_01H) \ -__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", \ - IAP_EVENT_CAH_08H) \ -__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", \ - IAP_EVENT_CAH_02H) \ -__PMC_EV_ALIAS("SIMD_INSTR_RETIRED", IAP_EVENT_CEH_00H) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.ANY", IAP_EVENT_C7H_1FH) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_DOUBLE", \ - IAP_EVENT_C7H_04H) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_SINGLE", \ - IAP_EVENT_C7H_01H) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_DOUBLE", \ - IAP_EVENT_C7H_08H) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_SINGLE", \ - IAP_EVENT_C7H_02H) \ -__PMC_EV_ALIAS("SIMD_INST_RETIRED.VECTOR", IAP_EVENT_C7H_10H) \ -__PMC_EV_ALIAS("SIMD_SAT_INSTR_RETIRED", IAP_EVENT_CFH_00H) \ -__PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC", IAP_EVENT_B1H_00H) \ -__PMC_EV_ALIAS("SIMD_UOPS_EXEC", IAP_EVENT_B0H_00H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC", IAP_EVENT_B3H_20H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL", IAP_EVENT_B3H_10H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL", IAP_EVENT_B3H_01H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK", IAP_EVENT_B3H_04H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT", IAP_EVENT_B3H_02H) \ -__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK", IAP_EVENT_B3H_08H) \ -__PMC_EV_ALIAS("SNOOP_STALL_DRV", IAP_EVENT_7EH) \ -__PMC_EV_ALIAS("SSE_PRE_EXEC.L1", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("SSE_PRE_EXEC.L2", IAP_EVENT_07H_02H) \ -__PMC_EV_ALIAS("SSE_PRE_EXEC.NTA", IAP_EVENT_07H_00H) \ -__PMC_EV_ALIAS("SSE_PRE_EXEC.STORES", IAP_EVENT_07H_03H) \ -__PMC_EV_ALIAS("SSE_PRE_MISS.L1", IAP_EVENT_4BH_01H) \ -__PMC_EV_ALIAS("SSE_PRE_MISS.L2", IAP_EVENT_4BH_02H) \ -__PMC_EV_ALIAS("SSE_PRE_MISS.NTA", IAP_EVENT_4BH_00H) \ -__PMC_EV_ALIAS("STORE_BLOCK.ORDER", IAP_EVENT_04H_02H) \ -__PMC_EV_ALIAS("STORE_BLOCK.SNOOP", IAP_EVENT_04H_08H) \ -__PMC_EV_ALIAS("THERMAL_TRIP", IAP_EVENT_3BH_C0H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_0FH) \ -__PMC_EV_ALIAS("UOPS_RETIRED.FUSED", IAP_EVENT_C2H_07H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.LD_IND_BR", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSION", IAP_EVENT_C2H_04H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.NON_FUSED", IAP_EVENT_C2H_08H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.STD_STA", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("X87_OPS_RETIRED.ANY", IAP_EVENT_C1H_FEH) \ -__PMC_EV_ALIAS("X87_OPS_RETIRED.FXCH", IAP_EVENT_C1H_01H) - -/* - * Core i7 and Xeon 5500 events removed between 253669-031US June 2009 - * and 253669-040US October 2011. - */ -#define __PMC_EV_ALIAS_COREI7_OLD() \ -__PMC_EV_ALIAS("SB_FORWARD.ANY", IAP_EVENT_02H_01H) \ -__PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_01H) \ -__PMC_EV_ALIAS("LOAD_BLOCK.ADDRESS_OFFSET", IAP_EVENT_03H_04H) \ -__PMC_EV_ALIAS("SB_DRAIN.CYCLES", IAP_EVENT_04H_01H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOAD", IAP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORE", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.ANY", IAP_EVENT_05H_03H) \ -__PMC_EV_ALIAS("STORE_BLOCKS.NOT_STA", IAP_EVENT_06H_01H) \ -__PMC_EV_ALIAS("STORE_BLOCKS.STA", IAP_EVENT_06H_02H) \ -__PMC_EV_ALIAS("STORE_BLOCKS.ANY", IAP_EVENT_06H_0FH) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDP_MISS", IAP_EVENT_08H_40H) \ -__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.RESET", IAP_EVENT_09H_01H) \ -__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.SUCCESS", IAP_EVENT_09H_02H) \ -__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.WATCHDOG", IAP_EVENT_09H_04H) \ -__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.WATCH_CYCLES", IAP_EVENT_09H_08H)\ -__PMC_EV_ALIAS("HW_INT.RCV", IAP_EVENT_1DH_01H) \ -__PMC_EV_ALIAS("HW_INT.CYCLES_MASKED", IAP_EVENT_1DH_02H) \ -__PMC_EV_ALIAS("HW_INT.CYCLES_PENDING_AND_MASKED", IAP_EVENT_1DH_04H) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.E_STATE", IAP_EVENT_27H_04H) \ -__PMC_EV_ALIAS("UOPS_DECODED.DEC0", IAP_EVENT_3DH_01H) \ -__PMC_EV_ALIAS("L1D_CACHE_ST.I_STATE", IAP_EVENT_41H_01H) \ -__PMC_EV_ALIAS("L1D_CACHE_ST.MESI", IAP_EVENT_41H_0FH) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.LOAD_BUFFERS_FULL", IAP_EVENT_48H_02H) \ -__PMC_EV_ALIAS("DTLB_MISSES.PDP_MISS", IAP_EVENT_49H_40H) \ -__PMC_EV_ALIAS("SSE_MEM_EXEC.NTA", IAP_EVENT_4BH_01H) \ -__PMC_EV_ALIAS("SSE_MEM_EXEC.STREAMING_STORES", IAP_EVENT_4BH_08H) \ -__PMC_EV_ALIAS("SFENCE_CYCLES", IAP_EVENT_4DH_01H) \ -__PMC_EV_ALIAS("EPT.EPDE_MISS", IAP_EVENT_4FH_02H) \ -__PMC_EV_ALIAS("EPT.EPDPE_HIT", IAP_EVENT_4FH_04H) \ -__PMC_EV_ALIAS("EPT.EPDPE_MISS", IAP_EVENT_4FH_08H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", \ - IAP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("IFU_IVC.FULL", IAP_EVENT_81H_01H) \ -__PMC_EV_ALIAS("IFU_IVC.L1I_EVICTION", IAP_EVENT_81H_02H) \ -__PMC_EV_ALIAS("L1I_OPPORTUNISTIC_HITS", IAP_EVENT_83H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_CYCLES", IAP_EVENT_85H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.PMH_BUSY_CYCLES", IAP_EVENT_85H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ITLB_MISSES.PDE_MISS", IAP_EVENT_85H_20H) \ -__PMC_EV_ALIAS("ITLB_MISSES.PDP_MISS", IAP_EVENT_85H_40H) \ -__PMC_EV_ALIAS("ITLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_85H_80H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_DATA", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_CODE", IAP_EVENT_B0H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.READ", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.RFO", IAP_EVENT_B0H_10H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.UNCACHED_MEM", IAP_EVENT_B0H_20H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY", IAP_EVENT_B0H_80H) \ -__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.DATA", IAP_EVENT_B3H_01H) \ -__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", \ - IAP_EVENT_B3H_02H) \ -__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.CODE", IAP_EVENT_B3H_04H) \ -__PMC_EV_ALIAS("PIC_ACCESSES.TPR_READS", IAP_EVENT_BAH_01H) \ -__PMC_EV_ALIAS("PIC_ACCESSES.TPR_WRITES", IAP_EVENT_BAH_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.FUSION_ASSIST", IAP_EVENT_C3H_10H) \ -__PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_01H) \ -__PMC_EV_ALIAS("BPU_CLEARS.ANY", IAP_EVENT_E8H_03H) \ -__PMC_EV_ALIAS("L2_HW_PREFETCH.HIT", IAP_EVENT_F3H_01H) \ -__PMC_EV_ALIAS("L2_HW_PREFETCH.ALLOC", IAP_EVENT_F3H_02H) \ -__PMC_EV_ALIAS("L2_HW_PREFETCH.DATA_TRIGGER", IAP_EVENT_F3H_04H) \ -__PMC_EV_ALIAS("L2_HW_PREFETCH.CODE_TRIGGER", IAP_EVENT_F3H_08H) \ -__PMC_EV_ALIAS("L2_HW_PREFETCH.DCA_TRIGGER", IAP_EVENT_F3H_10H) \ -__PMC_EV_ALIAS("L2_HW_PREFETCH.KICK_START", IAP_EVENT_F3H_20H) \ -__PMC_EV_ALIAS("SQ_MISC.PROMOTION", IAP_EVENT_F4H_01H) \ -__PMC_EV_ALIAS("SQ_MISC.PROMOTION_POST_GO", IAP_EVENT_F4H_02H) \ -__PMC_EV_ALIAS("SQ_MISC.LRU_HINTS", IAP_EVENT_F4H_04H) \ -__PMC_EV_ALIAS("SQ_MISC.FILL_DROPPED", IAP_EVENT_F4H_08H) \ -__PMC_EV_ALIAS("SEGMENT_REG_LOADS", IAP_EVENT_F8H_01H) - -/* - * Aliases for Core i7 and Xeon 5500 PMC events (253669-033US December 2009) - */ -#define __PMC_EV_ALIAS_COREI7() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("SB_DRAIN.ANY", IAP_EVENT_04H_07H) \ -__PMC_EV_ALIAS("STORE_BLOCKS.AT_RET", IAP_EVENT_06H_04H) \ -__PMC_EV_ALIAS("STORE_BLOCKS.L1D_BLOCK", IAP_EVENT_06H_08H) \ -__PMC_EV_ALIAS("PARTIAL_ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.ANY", IAP_EVENT_08H_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_MISS", IAP_EVENT_08H_20H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", \ - IAP_EVENT_08H_80H) \ -__PMC_EV_ALIAS("MEM_INST_RETIRED.LOADS", IAP_EVENT_0BH_01H) \ -__PMC_EV_ALIAS("MEM_INST_RETIRED.STORES", IAP_EVENT_0BH_02H) \ -__PMC_EV_ALIAS("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD", \ - IAP_EVENT_0BH_10H) \ -__PMC_EV_ALIAS("MEM_STORE_RETIRED.DTLB_MISS", IAP_EVENT_0CH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.STALLED_CYCLES", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.FUSED", IAP_EVENT_0EH_02H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN", \ - IAP_EVENT_0FH_01H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", \ - IAP_EVENT_0FH_02H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", \ - IAP_EVENT_0FH_08H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_DRAM", \ - IAP_EVENT_0FH_10H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM", IAP_EVENT_0FH_20H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.UNCACHEABLE", IAP_EVENT_0FH_80H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.MMX", IAP_EVENT_10H_02H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP", IAP_EVENT_10H_04H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE2_INTEGER", IAP_EVENT_10H_08H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED", IAP_EVENT_10H_10H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR", IAP_EVENT_10H_20H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", \ - IAP_EVENT_10H_40H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", \ - IAP_EVENT_10H_80H) \ -__PMC_EV_ALIAS("SIMD_INT_128.PACKED_MPY", IAP_EVENT_12H_01H) \ -__PMC_EV_ALIAS("SIMD_INT_128.PACKED_SHIFT", IAP_EVENT_12H_02H) \ -__PMC_EV_ALIAS("SIMD_INT_128.PACK", IAP_EVENT_12H_04H) \ -__PMC_EV_ALIAS("SIMD_INT_128.UNPACK", IAP_EVENT_12H_08H) \ -__PMC_EV_ALIAS("SIMD_INT_128.PACKED_LOGICAL", IAP_EVENT_12H_10H) \ -__PMC_EV_ALIAS("SIMD_INT_128.PACKED_ARITH", IAP_EVENT_12H_20H) \ -__PMC_EV_ALIAS("SIMD_INT_128.SHUFFLE_MOVE", IAP_EVENT_12H_40H) \ -__PMC_EV_ALIAS("LOAD_DISPATCH.RS", IAP_EVENT_13H_01H) \ -__PMC_EV_ALIAS("LOAD_DISPATCH.RS_DELAYED", IAP_EVENT_13H_02H) \ -__PMC_EV_ALIAS("LOAD_DISPATCH.MOB", IAP_EVENT_13H_04H) \ -__PMC_EV_ALIAS("LOAD_DISPATCH.ANY", IAP_EVENT_13H_07H) \ -__PMC_EV_ALIAS("ARITH.CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \ -__PMC_EV_ALIAS("ARITH.MUL", IAP_EVENT_14H_02H) \ -__PMC_EV_ALIAS("INST_QUEUE_WRITES", IAP_EVENT_17H_01H) \ -__PMC_EV_ALIAS("INST_DECODED.DEC0", IAP_EVENT_18H_01H) \ -__PMC_EV_ALIAS("TWO_UOP_INSTS_DECODED", IAP_EVENT_19H_01H) \ -__PMC_EV_ALIAS("INST_QUEUE_WRITE_CYCLES", IAP_EVENT_1EH_01H) \ -__PMC_EV_ALIAS("LSD_OVERFLOW", IAP_EVENT_20H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.LD_HIT", IAP_EVENT_24H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.LD_MISS", IAP_EVENT_24H_02H) \ -__PMC_EV_ALIAS("L2_RQSTS.LOADS", IAP_EVENT_24H_03H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_04H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFOS", IAP_EVENT_24H_0CH) \ -__PMC_EV_ALIAS("L2_RQSTS.IFETCH_HIT", IAP_EVENT_24H_10H) \ -__PMC_EV_ALIAS("L2_RQSTS.IFETCH_MISS", IAP_EVENT_24H_20H) \ -__PMC_EV_ALIAS("L2_RQSTS.IFETCHES", IAP_EVENT_24H_30H) \ -__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_HIT", IAP_EVENT_24H_40H) \ -__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_MISS", IAP_EVENT_24H_80H) \ -__PMC_EV_ALIAS("L2_RQSTS.PREFETCHES", IAP_EVENT_24H_C0H) \ -__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_AAH) \ -__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.I_STATE", IAP_EVENT_26H_01H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.S_STATE", IAP_EVENT_26H_02H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.E_STATE", IAP_EVENT_26H_04H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.M_STATE", IAP_EVENT_26H_08H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.MESI", IAP_EVENT_26H_0FH) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.I_STATE", IAP_EVENT_26H_10H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.S_STATE", IAP_EVENT_26H_20H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.E_STATE", IAP_EVENT_26H_40H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.M_STATE", IAP_EVENT_26H_80H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.MESI", IAP_EVENT_26H_F0H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.ANY", IAP_EVENT_26H_FFH) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.I_STATE", IAP_EVENT_27H_01H) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.S_STATE", IAP_EVENT_27H_02H) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.M_STATE", IAP_EVENT_27H_08H) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.HIT", IAP_EVENT_27H_0EH) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.MESI", IAP_EVENT_27H_0FH) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.I_STATE", IAP_EVENT_27H_10H) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.S_STATE", IAP_EVENT_27H_20H) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.E_STATE", IAP_EVENT_27H_40H) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.M_STATE", IAP_EVENT_27H_80H) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.HIT", IAP_EVENT_27H_E0H) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.MESI", IAP_EVENT_27H_F0H) \ -__PMC_EV_ALIAS("L1D_WB_L2.I_STATE", IAP_EVENT_28H_01H) \ -__PMC_EV_ALIAS("L1D_WB_L2.S_STATE", IAP_EVENT_28H_02H) \ -__PMC_EV_ALIAS("L1D_WB_L2.E_STATE", IAP_EVENT_28H_04H) \ -__PMC_EV_ALIAS("L1D_WB_L2.M_STATE", IAP_EVENT_28H_08H) \ -__PMC_EV_ALIAS("L1D_WB_L2.MESI", IAP_EVENT_28H_0FH) \ -__PMC_EV_ALIAS("L3_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("L3_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("L1D_CACHE_LD.I_STATE", IAP_EVENT_40H_01H) \ -__PMC_EV_ALIAS("L1D_CACHE_LD.S_STATE", IAP_EVENT_40H_02H) \ -__PMC_EV_ALIAS("L1D_CACHE_LD.E_STATE", IAP_EVENT_40H_04H) \ -__PMC_EV_ALIAS("L1D_CACHE_LD.M_STATE", IAP_EVENT_40H_08H) \ -__PMC_EV_ALIAS("L1D_CACHE_LD.MESI", IAP_EVENT_40H_0FH) \ -__PMC_EV_ALIAS("L1D_CACHE_ST.S_STATE", IAP_EVENT_41H_02H) \ -__PMC_EV_ALIAS("L1D_CACHE_ST.E_STATE", IAP_EVENT_41H_04H) \ -__PMC_EV_ALIAS("L1D_CACHE_ST.M_STATE", IAP_EVENT_41H_08H) \ -__PMC_EV_ALIAS("L1D_CACHE_LOCK.HIT", IAP_EVENT_42H_01H) \ -__PMC_EV_ALIAS("L1D_CACHE_LOCK.S_STATE", IAP_EVENT_42H_02H) \ -__PMC_EV_ALIAS("L1D_CACHE_LOCK.E_STATE", IAP_EVENT_42H_04H) \ -__PMC_EV_ALIAS("L1D_CACHE_LOCK.M_STATE", IAP_EVENT_42H_08H) \ -__PMC_EV_ALIAS("L1D_ALL_REF.ANY", IAP_EVENT_43H_01H) \ -__PMC_EV_ALIAS("L1D_ALL_REF.CACHEABLE", IAP_EVENT_43H_02H) \ -__PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("DTLB_MISSES.PDE_MISS", IAP_EVENT_49H_20H) \ -__PMC_EV_ALIAS("DTLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_49H_80H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_01H) \ -__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_01H) \ -__PMC_EV_ALIAS("L1D_PREFETCH.MISS", IAP_EVENT_4EH_02H) \ -__PMC_EV_ALIAS("L1D_PREFETCH.TRIGGERS", IAP_EVENT_4EH_04H) \ -__PMC_EV_ALIAS("L1D.REPL", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("L1D.M_REPL", IAP_EVENT_51H_02H) \ -__PMC_EV_ALIAS("L1D.M_EVICT", IAP_EVENT_51H_04H) \ -__PMC_EV_ALIAS("L1D.M_SNOOP_EVICT", IAP_EVENT_51H_08H) \ -__PMC_EV_ALIAS("L1D_CACHE_PREFETCH_LOCK_FB_HIT", IAP_EVENT_52H_01H) \ -__PMC_EV_ALIAS("L1D_CACHE_LOCK_FB_HIT", IAP_EVENT_53H_01H) \ -__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D_L2", IAP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IO_TRANSACTIONS", IAP_EVENT_6CH_01H) \ -__PMC_EV_ALIAS("L1I.HITS", IAP_EVENT_80H_01H) \ -__PMC_EV_ALIAS("L1I.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("L1I.READS", IAP_EVENT_80H_03H) \ -__PMC_EV_ALIAS("L1I.CYCLES_STALLED", IAP_EVENT_80H_04H) \ -__PMC_EV_ALIAS("LARGE_ITLB.HIT", IAP_EVENT_82H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.ANY", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("ILD_STALL.MRU", IAP_EVENT_87H_02H) \ -__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("ILD_STALL.REGEN", IAP_EVENT_87H_08H) \ -__PMC_EV_ALIAS("ILD_STALL.ANY", IAP_EVENT_87H_0FH) \ -__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NON_CALLS", IAP_EVENT_88H_07H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NEAR_CALLS", IAP_EVENT_88H_30H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_40H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.ANY", IAP_EVENT_88H_7FH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT", IAP_EVENT_89H_02H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NON_CALLS", IAP_EVENT_89H_07H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NEAR_CALLS", IAP_EVENT_89H_30H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_40H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ANY", IAP_EVENT_89H_7FH) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.LOAD", IAP_EVENT_A2H_02H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_A2H_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.STORE", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_A2H_10H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_A2H_20H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ -__PMC_EV_ALIAS("MACRO_INSTS.FUSIONS_DECODED", IAP_EVENT_A6H_01H) \ -__PMC_EV_ALIAS("BACLEAR_FORCE_IQ", IAP_EVENT_A7H_01H) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.L1D_WRITEBACK", IAP_EVENT_B0H_40H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT0", IAP_EVENT_B1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT1", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT2_CORE", IAP_EVENT_B1H_04H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT3_CORE", IAP_EVENT_B1H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT4_CORE", IAP_EVENT_B1H_10H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", \ - IAP_EVENT_B1H_1FH) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT5", IAP_EVENT_B1H_20H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES", IAP_EVENT_B1H_3FH) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT015", IAP_EVENT_B1H_40H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT234", IAP_EVENT_B1H_80H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_SQ_FULL", IAP_EVENT_B2H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("SNOOP_RESPONSE.HIT", IAP_EVENT_B8H_01H) \ -__PMC_EV_ALIAS("SNOOP_RESPONSE.HITE", IAP_EVENT_B8H_02H) \ -__PMC_EV_ALIAS("SNOOP_RESPONSE.HITM", IAP_EVENT_B8H_04H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ -__PMC_EV_ALIAS("INST_RETIRED.MMX", IAP_EVENT_C0H_04H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSED", IAP_EVENT_C2H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEM_ORDER", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ -__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \ -__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ -__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \ -__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \ -__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.VECTOR_INTEGER", IAP_EVENT_C7H_10H) \ -__PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C8H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_HIT", IAP_EVENT_CBH_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_UNSHARED_HIT", IAP_EVENT_CBH_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", \ - IAP_EVENT_CBH_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_MISS", IAP_EVENT_CBH_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.HIT_LFB", IAP_EVENT_CBH_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_80H) \ -__PMC_EV_ALIAS("FP_MMX_TRANS.TO_FP", IAP_EVENT_CCH_01H) \ -__PMC_EV_ALIAS("FP_MMX_TRANS.TO_MMX", IAP_EVENT_CCH_02H) \ -__PMC_EV_ALIAS("FP_MMX_TRANS.ANY", IAP_EVENT_CCH_03H) \ -__PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_D0H_01H) \ -__PMC_EV_ALIAS("UOPS_DECODED.MS", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("UOPS_DECODED.ESP_FOLDING", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("UOPS_DECODED.ESP_SYNC", IAP_EVENT_D1H_08H) \ -__PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("RAT_STALLS.REGISTERS", IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("RAT_STALLS.SCOREBOARD", IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS", IAP_EVENT_D4H_01H) \ -__PMC_EV_ALIAS("ES_REG_RENAMES", IAP_EVENT_D5H_01H) \ -__PMC_EV_ALIAS("UOP_UNFUSION", IAP_EVENT_DBH_01H) \ -__PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \ -__PMC_EV_ALIAS("BPU_MISSED_CALL_RET", IAP_EVENT_E5H_01H) \ -__PMC_EV_ALIAS("BACLEAR.CLEAR", IAP_EVENT_E6H_01H) \ -__PMC_EV_ALIAS("BACLEAR.BAD_TARGET", IAP_EVENT_E6H_02H) \ -__PMC_EV_ALIAS("BPU_CLEARS.EARLY", IAP_EVENT_E8H_01H) \ -__PMC_EV_ALIAS("BPU_CLEARS.LATE", IAP_EVENT_E8H_02H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.LOAD", IAP_EVENT_F0H_01H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.RFO", IAP_EVENT_F0H_02H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.IFETCH", IAP_EVENT_F0H_04H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.PREFETCH", IAP_EVENT_F0H_08H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.L1D_WB", IAP_EVENT_F0H_10H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.FILL", IAP_EVENT_F0H_20H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.ANY", IAP_EVENT_F0H_80H) \ -__PMC_EV_ALIAS("L2_LINES_IN.S_STATE", IAP_EVENT_F1H_02H) \ -__PMC_EV_ALIAS("L2_LINES_IN.E_STATE", IAP_EVENT_F1H_04H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ANY", IAP_EVENT_F1H_07H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_CLEAN", IAP_EVENT_F2H_04H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_DIRTY", IAP_EVENT_F2H_08H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.ANY", IAP_EVENT_F2H_0FH) \ -__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) \ -__PMC_EV_ALIAS("SQ_FULL_STALL_CYCLES", IAP_EVENT_F6H_01H) \ -__PMC_EV_ALIAS("FP_ASSIST.ALL", IAP_EVENT_F7H_01H) \ -__PMC_EV_ALIAS("FP_ASSIST.OUTPUT", IAP_EVENT_F7H_02H) \ -__PMC_EV_ALIAS("FP_ASSIST.INPUT", IAP_EVENT_F7H_04H) \ -__PMC_EV_ALIAS("SIMD_INT_64.PACKED_MPY", IAP_EVENT_FDH_01H) \ -__PMC_EV_ALIAS("SIMD_INT_64.PACKED_SHIFT", IAP_EVENT_FDH_02H) \ -__PMC_EV_ALIAS("SIMD_INT_64.PACK", IAP_EVENT_FDH_04H) \ -__PMC_EV_ALIAS("SIMD_INT_64.UNPACK", IAP_EVENT_FDH_08H) \ -__PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H) \ -__PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H) \ -__PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H) \ -__PMC_EV_ALIAS_COREI7_OLD() - -/* - * Aliases for Westmere PMC events (253669-033US December 2009) - */ -#define __PMC_EV_ALIAS_WESTMERE() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("SB_DRAIN.ANY", IAP_EVENT_04H_07H) \ -__PMC_EV_ALIAS("MISALIGN_MEMORY.STORE", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("STORE_BLOCKS.AT_RET", IAP_EVENT_06H_04H) \ -__PMC_EV_ALIAS("STORE_BLOCKS.L1D_BLOCK", IAP_EVENT_06H_08H) \ -__PMC_EV_ALIAS("PARTIAL_ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.ANY", IAP_EVENT_08H_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_CYCLES", IAP_EVENT_08H_04H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_MISS", IAP_EVENT_08H_20H) \ -__PMC_EV_ALIAS("MEM_INST_RETIRED.LOADS", IAP_EVENT_0BH_01H) \ -__PMC_EV_ALIAS("MEM_INST_RETIRED.STORES", IAP_EVENT_0BH_02H) \ -__PMC_EV_ALIAS("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD", \ - IAP_EVENT_0BH_10H) \ -__PMC_EV_ALIAS("MEM_STORE_RETIRED.DTLB_MISS", IAP_EVENT_0CH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.STALLED_CYCLES", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.FUSED", IAP_EVENT_0EH_02H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_HITM", IAP_EVENT_0FH_02H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", \ - IAP_EVENT_0FH_08H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM", IAP_EVENT_0FH_10H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_DRAM", IAP_EVENT_0FH_20H) \ -__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.UNCACHEABLE", IAP_EVENT_0FH_80H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.MMX", IAP_EVENT_10H_02H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP", IAP_EVENT_10H_04H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE2_INTEGER", IAP_EVENT_10H_08H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED", IAP_EVENT_10H_10H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR", IAP_EVENT_10H_20H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", \ - IAP_EVENT_10H_40H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", \ - IAP_EVENT_10H_80H) \ -__PMC_EV_ALIAS("SIMD_INT_128.PACKED_MPY", IAP_EVENT_12H_01H) \ -__PMC_EV_ALIAS("SIMD_INT_128.PACKED_SHIFT", IAP_EVENT_12H_02H) \ -__PMC_EV_ALIAS("SIMD_INT_128.PACK", IAP_EVENT_12H_04H) \ -__PMC_EV_ALIAS("SIMD_INT_128.UNPACK", IAP_EVENT_12H_08H) \ -__PMC_EV_ALIAS("SIMD_INT_128.PACKED_LOGICAL", IAP_EVENT_12H_10H) \ -__PMC_EV_ALIAS("SIMD_INT_128.PACKED_ARITH", IAP_EVENT_12H_20H) \ -__PMC_EV_ALIAS("SIMD_INT_128.SHUFFLE_MOVE", IAP_EVENT_12H_40H) \ -__PMC_EV_ALIAS("LOAD_DISPATCH.RS", IAP_EVENT_13H_01H) \ -__PMC_EV_ALIAS("LOAD_DISPATCH.RS_DELAYED", IAP_EVENT_13H_02H) \ -__PMC_EV_ALIAS("LOAD_DISPATCH.MOB", IAP_EVENT_13H_04H) \ -__PMC_EV_ALIAS("LOAD_DISPATCH.ANY", IAP_EVENT_13H_07H) \ -__PMC_EV_ALIAS("ARITH.CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \ -__PMC_EV_ALIAS("ARITH.MUL", IAP_EVENT_14H_02H) \ -__PMC_EV_ALIAS("INST_QUEUE_WRITES", IAP_EVENT_17H_01H) \ -__PMC_EV_ALIAS("INST_DECODED.DEC0", IAP_EVENT_18H_01H) \ -__PMC_EV_ALIAS("TWO_UOP_INSTS_DECODED", IAP_EVENT_19H_01H) \ -__PMC_EV_ALIAS("INST_QUEUE_WRITE_CYCLES", IAP_EVENT_1EH_01H) \ -__PMC_EV_ALIAS("LSD_OVERFLOW", IAP_EVENT_20H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.LD_HIT", IAP_EVENT_24H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.LD_MISS", IAP_EVENT_24H_02H) \ -__PMC_EV_ALIAS("L2_RQSTS.LOADS", IAP_EVENT_24H_03H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_04H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFOS", IAP_EVENT_24H_0CH) \ -__PMC_EV_ALIAS("L2_RQSTS.IFETCH_HIT", IAP_EVENT_24H_10H) \ -__PMC_EV_ALIAS("L2_RQSTS.IFETCH_MISS", IAP_EVENT_24H_20H) \ -__PMC_EV_ALIAS("L2_RQSTS.IFETCHES", IAP_EVENT_24H_30H) \ -__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_HIT", IAP_EVENT_24H_40H) \ -__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_MISS", IAP_EVENT_24H_80H) \ -__PMC_EV_ALIAS("L2_RQSTS.PREFETCHES", IAP_EVENT_24H_C0H) \ -__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_AAH) \ -__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.I_STATE", IAP_EVENT_26H_01H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.S_STATE", IAP_EVENT_26H_02H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.E_STATE", IAP_EVENT_26H_04H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.M_STATE", IAP_EVENT_26H_08H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.MESI", IAP_EVENT_26H_0FH) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.I_STATE", IAP_EVENT_26H_10H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.S_STATE", IAP_EVENT_26H_20H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.E_STATE", IAP_EVENT_26H_40H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.M_STATE", IAP_EVENT_26H_80H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.MESI", IAP_EVENT_26H_F0H) \ -__PMC_EV_ALIAS("L2_DATA_RQSTS.ANY", IAP_EVENT_26H_FFH) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.I_STATE", IAP_EVENT_27H_01H) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.S_STATE", IAP_EVENT_27H_02H) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.M_STATE", IAP_EVENT_27H_08H) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.HIT", IAP_EVENT_27H_0EH) \ -__PMC_EV_ALIAS("L2_WRITE.RFO.MESI", IAP_EVENT_27H_0FH) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.I_STATE", IAP_EVENT_27H_10H) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.S_STATE", IAP_EVENT_27H_20H) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.E_STATE", IAP_EVENT_27H_40H) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.M_STATE", IAP_EVENT_27H_80H) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.HIT", IAP_EVENT_27H_E0H) \ -__PMC_EV_ALIAS("L2_WRITE.LOCK.MESI", IAP_EVENT_27H_F0H) \ -__PMC_EV_ALIAS("L1D_WB_L2.I_STATE", IAP_EVENT_28H_01H) \ -__PMC_EV_ALIAS("L1D_WB_L2.S_STATE", IAP_EVENT_28H_02H) \ -__PMC_EV_ALIAS("L1D_WB_L2.E_STATE", IAP_EVENT_28H_04H) \ -__PMC_EV_ALIAS("L1D_WB_L2.M_STATE", IAP_EVENT_28H_08H) \ -__PMC_EV_ALIAS("L1D_WB_L2.MESI", IAP_EVENT_28H_0FH) \ -__PMC_EV_ALIAS("L3_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_02H) \ -__PMC_EV_ALIAS("L3_LAT_CACHE.MISS", IAP_EVENT_2EH_01H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_MISSES.WALK_CYCLES", IAP_EVENT_49H_04H) \ -__PMC_EV_ALIAS("DTLB_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("DTLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_49H_80H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_01H) \ -__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_01H) \ -__PMC_EV_ALIAS("L1D_PREFETCH.MISS", IAP_EVENT_4EH_02H) \ -__PMC_EV_ALIAS("L1D_PREFETCH.TRIGGERS", IAP_EVENT_4EH_04H) \ -__PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H) \ -__PMC_EV_ALIAS("L1D.REPL", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("L1D.M_REPL", IAP_EVENT_51H_02H) \ -__PMC_EV_ALIAS("L1D.M_EVICT", IAP_EVENT_51H_04H) \ -__PMC_EV_ALIAS("L1D.M_SNOOP_EVICT", IAP_EVENT_51H_08H) \ -__PMC_EV_ALIAS("L1D_CACHE_PREFETCH_LOCK_FB_HIT", IAP_EVENT_52H_01H) \ -__PMC_EV_ALIAS("L1D_CACHE_LOCK_FB_HIT", IAP_EVENT_53H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", \ - IAP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D_L2", IAP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IO_TRANSACTIONS", IAP_EVENT_6CH_01H) \ -__PMC_EV_ALIAS("L1I.HITS", IAP_EVENT_80H_01H) \ -__PMC_EV_ALIAS("L1I.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("L1I.READS", IAP_EVENT_80H_03H) \ -__PMC_EV_ALIAS("L1I.CYCLES_STALLED", IAP_EVENT_80H_04H) \ -__PMC_EV_ALIAS("LARGE_ITLB.HIT", IAP_EVENT_82H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.ANY", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_CYCLES", IAP_EVENT_85H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_85H_80H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("ILD_STALL.MRU", IAP_EVENT_87H_02H) \ -__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("ILD_STALL.REGEN", IAP_EVENT_87H_08H) \ -__PMC_EV_ALIAS("ILD_STALL.ANY", IAP_EVENT_87H_0FH) \ -__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NON_CALLS", IAP_EVENT_88H_07H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NEAR_CALLS", IAP_EVENT_88H_30H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_40H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.ANY", IAP_EVENT_88H_7FH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT", IAP_EVENT_89H_02H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NON_CALLS", IAP_EVENT_89H_07H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NEAR_CALLS", IAP_EVENT_89H_30H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_40H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ANY", IAP_EVENT_89H_7FH) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.LOAD", IAP_EVENT_A2H_02H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_A2H_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.STORE", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_A2H_10H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_A2H_20H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ -__PMC_EV_ALIAS("MACRO_INSTS.FUSIONS_DECODED", IAP_EVENT_A6H_01H) \ -__PMC_EV_ALIAS("BACLEAR_FORCE_IQ", IAP_EVENT_A7H_01H) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_DATA", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_CODE", IAP_EVENT_B0H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.READ", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.RFO", IAP_EVENT_B0H_10H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.L1D_WRITEBACK", IAP_EVENT_B0H_40H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY", IAP_EVENT_B0H_80H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT0", IAP_EVENT_B1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT1", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT2_CORE", IAP_EVENT_B1H_04H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT3_CORE", IAP_EVENT_B1H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT4_CORE", IAP_EVENT_B1H_10H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", \ - IAP_EVENT_B1H_1FH) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT5", IAP_EVENT_B1H_20H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES", IAP_EVENT_B1H_3FH) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT015", IAP_EVENT_B1H_40H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.PORT234", IAP_EVENT_B1H_80H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_SQ_FULL", IAP_EVENT_B2H_01H) \ -__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.DATA", IAP_EVENT_B3H_01H) \ -__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", \ - IAP_EVENT_B3H_02H) \ -__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.CODE", IAP_EVENT_B3H_04H) \ -__PMC_EV_ALIAS("SNOOPQ_REQUESTS.CODE", IAP_EVENT_B4H_01H) \ -__PMC_EV_ALIAS("SNOOPQ_REQUESTS.DATA", IAP_EVENT_B4H_02H) \ -__PMC_EV_ALIAS("SNOOPQ_REQUESTS.INVALIDATE", IAP_EVENT_B4H_04H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("SNOOP_RESPONSE.HIT", IAP_EVENT_B8H_01H) \ -__PMC_EV_ALIAS("SNOOP_RESPONSE.HITE", IAP_EVENT_B8H_02H) \ -__PMC_EV_ALIAS("SNOOP_RESPONSE.HITM", IAP_EVENT_B8H_04H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ -__PMC_EV_ALIAS("INST_RETIRED.MMX", IAP_EVENT_C0H_04H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSED", IAP_EVENT_C2H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEM_ORDER", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ANY_P", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ANY_P", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ -__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \ -__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ -__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \ -__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \ -__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.VECTOR_INTEGER", IAP_EVENT_C7H_10H) \ -__PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C8H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_HIT", IAP_EVENT_CBH_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_UNSHARED_HIT", IAP_EVENT_CBH_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", \ - IAP_EVENT_CBH_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_MISS", IAP_EVENT_CBH_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.HIT_LFB", IAP_EVENT_CBH_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_80H) \ -__PMC_EV_ALIAS("FP_MMX_TRANS.TO_FP", IAP_EVENT_CCH_01H) \ -__PMC_EV_ALIAS("FP_MMX_TRANS.TO_MMX", IAP_EVENT_CCH_02H) \ -__PMC_EV_ALIAS("FP_MMX_TRANS.ANY", IAP_EVENT_CCH_03H) \ -__PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_D0H_01H) \ -__PMC_EV_ALIAS("UOPS_DECODED.STALL_CYCLES", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("UOPS_DECODED.MS", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("UOPS_DECODED.ESP_FOLDING", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("UOPS_DECODED.ESP_SYNC", IAP_EVENT_D1H_08H) \ -__PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("RAT_STALLS.REGISTERS", IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("RAT_STALLS.SCOREBOARD", IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ -__PMC_EV_ALIAS("SEG_RENAME_STALLS", IAP_EVENT_D4H_01H) \ -__PMC_EV_ALIAS("ES_REG_RENAMES", IAP_EVENT_D5H_01H) \ -__PMC_EV_ALIAS("UOP_UNFUSION", IAP_EVENT_DBH_01H) \ -__PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \ -__PMC_EV_ALIAS("BPU_MISSED_CALL_RET", IAP_EVENT_E5H_01H) \ -__PMC_EV_ALIAS("BACLEAR.CLEAR", IAP_EVENT_E6H_01H) \ -__PMC_EV_ALIAS("BACLEAR.BAD_TARGET", IAP_EVENT_E6H_02H) \ -__PMC_EV_ALIAS("BPU_CLEARS.EARLY", IAP_EVENT_E8H_01H) \ -__PMC_EV_ALIAS("BPU_CLEARS.LATE", IAP_EVENT_E8H_02H) \ -__PMC_EV_ALIAS("THREAD_ACTIVE", IAP_EVENT_ECH_01H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.LOAD", IAP_EVENT_F0H_01H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.RFO", IAP_EVENT_F0H_02H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.IFETCH", IAP_EVENT_F0H_04H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.PREFETCH", IAP_EVENT_F0H_08H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.L1D_WB", IAP_EVENT_F0H_10H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.FILL", IAP_EVENT_F0H_20H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_TRANSACTIONS.ANY", IAP_EVENT_F0H_80H) \ -__PMC_EV_ALIAS("L2_LINES_IN.S_STATE", IAP_EVENT_F1H_02H) \ -__PMC_EV_ALIAS("L2_LINES_IN.E_STATE", IAP_EVENT_F1H_04H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ANY", IAP_EVENT_F1H_07H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_CLEAN", IAP_EVENT_F2H_04H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_DIRTY", IAP_EVENT_F2H_08H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.ANY", IAP_EVENT_F2H_0FH) \ -__PMC_EV_ALIAS("SQ_MISC.LRU_HINTS", IAP_EVENT_F4H_04H) \ -__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) \ -__PMC_EV_ALIAS("SQ_FULL_STALL_CYCLES", IAP_EVENT_F6H_01H) \ -__PMC_EV_ALIAS("FP_ASSIST.ALL", IAP_EVENT_F7H_01H) \ -__PMC_EV_ALIAS("FP_ASSIST.OUTPUT", IAP_EVENT_F7H_02H) \ -__PMC_EV_ALIAS("FP_ASSIST.INPUT", IAP_EVENT_F7H_04H) \ -__PMC_EV_ALIAS("SIMD_INT_64.PACKED_MPY", IAP_EVENT_FDH_01H) \ -__PMC_EV_ALIAS("SIMD_INT_64.PACKED_SHIFT", IAP_EVENT_FDH_02H) \ -__PMC_EV_ALIAS("SIMD_INT_64.PACK", IAP_EVENT_FDH_04H) \ -__PMC_EV_ALIAS("SIMD_INT_64.UNPACK", IAP_EVENT_FDH_08H) \ -__PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H) \ -__PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H) \ -__PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H) - -/* - * Aliases for Haswell core PMC events - */ -#define __PMC_EV_ALIAS_HASWELL_XEON() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", \ - IAP_EVENT_08H_04H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_2M", IAP_EVENT_08H_40H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_60H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_CACHE_MISS", IAP_EVENT_08H_80H) \ -__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_42H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_22H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_44H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_24H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_MISS", IAP_EVENT_24H_27H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_REFERENCES", IAP_EVENT_24H_E7H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \ -__PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \ -__PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \ -__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_3FH) \ -__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ -__PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ - IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \ - IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", \ - IAP_EVENT_49H_04H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_0EH) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_2M", IAP_EVENT_49H_40H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_60H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.PDE_CACHE_MISS", IAP_EVENT_49H_80H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ -__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \ - IAP_EVENT_58H_04H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \ - IAP_EVENT_58H_08H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ -__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \ - IAP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ - IAP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ -__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ -__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ -__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ -__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ -__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ -__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ -__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("TLB_MISSES.WALK_COMPLETED_2M_4M", IAP_EVENT_85H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_0EH) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_2M", IAP_EVENT_85H_40H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_60H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_84H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_84H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ -__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L2_PENDING", IAP_EVENT_A3H_05H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L1D_PENDING", IAP_EVENT_A3H_0CH) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_MEMORY", IAP_EVENT_BCH_28H) \ -__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_U_RETIRED.CONDITIONAL", IAP_EVENT_C5H_04H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_TAKEN", IAP_EVENT_C5H_20H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ -__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ -__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ - IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ - IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \ - IAP_EVENT_D2H_0FH) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ - IAP_EVENT_D3H_01H) \ -__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \ -__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ -__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ -__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ -__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ -__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ -__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_06H) - - -#define __PMC_EV_ALIAS_HASWELL() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", \ - IAP_EVENT_08H_04H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_2M", IAP_EVENT_08H_40H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_60H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_CACHE_MISS", IAP_EVENT_08H_80H) \ -__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_42H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_22H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_44H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_24H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_MISS", IAP_EVENT_24H_27H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_REFERENCES", IAP_EVENT_24H_E7H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \ -__PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \ -__PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \ -__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_3FH) \ -__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ -__PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ - IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \ - IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", \ - IAP_EVENT_49H_04H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_0EH) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_2M", IAP_EVENT_49H_40H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_60H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.PDE_CACHE_MISS", IAP_EVENT_49H_80H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ -__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \ - IAP_EVENT_58H_04H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \ - IAP_EVENT_58H_08H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ -__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \ - IAP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ - IAP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ -__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ -__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ -__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ -__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ -__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ -__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ -__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("TLB_MISSES.WALK_COMPLETED_2M_4M", IAP_EVENT_85H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_0EH) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_2M", IAP_EVENT_85H_40H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_60H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_84H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_84H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ -__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L2_PENDING", IAP_EVENT_A3H_05H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L1D_PENDING", IAP_EVENT_A3H_0CH) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \ -__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_MEMORY", IAP_EVENT_BCH_28H) \ -__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_U_RETIRED.CONDITIONAL", IAP_EVENT_C5H_04H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_TAKEN", IAP_EVENT_C5H_20H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ -__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ -__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ - IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ - IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \ - IAP_EVENT_D2H_0FH) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ - IAP_EVENT_D3H_01H) \ -__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \ -__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ -__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ -__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ -__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ -__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ -__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_06H) - - -#define __PMC_EV_ALIAS_IVYBRIDGE() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_81H)\ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_82H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_84H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_PG_WALK_DURATION", \ - IAP_EVENT_08H_88H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \ - IAP_EVENT_10H_10H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \ - IAP_EVENT_10H_20H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \ -__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \ -__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \ -__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ - IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ -__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \ - IAP_EVENT_58H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", \ - IAP_EVENT_58H_02H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_04H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_ELIMINATED", IAP_EVENT_58H_08H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ -__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_5FH_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \ - IAP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ - IAP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ -__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ -__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ -__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ -__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ -__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ -__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ -__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("ICACHE.IFETCH_STALL", IAP_EVENT_80H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_84H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_84H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ -__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", IAP_EVENT_A3H_04H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ -__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ -__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ -__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.WB", IAP_EVENT_C1H_80H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ -__PMC_EV_ALIAS("BR_MISP_U_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ -__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ -__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ - IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ - IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \ - IAP_EVENT_D2H_0FH) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ - IAP_EVENT_D3H_01H) \ -__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \ -__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ -__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ -__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ -__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ -__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ -__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) - -/* - * Aliases for Ivy Bridge Xeon PMC events (325462-045US January 2013) - */ -#define __PMC_EV_ALIAS_IVYBRIDGE_XEON() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_81H)\ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_82H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_84H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_PG_WALK_DURATION", \ - IAP_EVENT_08H_88H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \ - IAP_EVENT_10H_10H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \ - IAP_EVENT_10H_20H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \ -__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \ -__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \ -__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ - IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ -__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", IAP_EVENT_58H_01H)\ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", \ - IAP_EVENT_58H_02H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_04H) \ -__PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_ELIMINATED", IAP_EVENT_58H_08H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ -__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_5FH_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \ - IAP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ - IAP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ -__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ -__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ -__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ -__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ -__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ -__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ -__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ -__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("ICACHE.IFETCH_STALL", IAP_EVENT_80H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_84H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_84H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ -__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", IAP_EVENT_A3H_04H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ -__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ -__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ -__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \ -__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.WB", IAP_EVENT_C1H_80H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ -__PMC_EV_ALIAS("BR_MISP_U_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ -__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ -__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ -__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ - IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ - IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ - IAP_EVENT_D3H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ - IAP_EVENT_D3H_03H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", \ - IAP_EVENT_D3H_0CH) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", \ - IAP_EVENT_D3H_10H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD", \ - IAP_EVENT_D3H_20H) \ -__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \ -__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ -__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ -__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ -__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ -__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ -__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH) - -/* - * Aliases for Sandy Bridge PMC events (253669-039US May 2011) - */ -#define __PMC_EV_ALIAS_SANDYBRIDGE() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LD_BLOCKS.DATA_UNKNOWN", IAP_EVENT_03H_01H) \ -__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("LD_BLOCKS.ALL_BLOCK", IAP_EVENT_03H_10H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", IAP_EVENT_07H_08H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_04H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ -__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ -__PMC_EV_ALIAS("INT_MISC.RAT_STALL_CYCLES", IAP_EVENT_0DH_40H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \ - IAP_EVENT_10H_10H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \ - IAP_EVENT_10H_20H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \ -__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \ -__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \ -__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ -__PMC_EV_ALIAS("INSTS_WRITTEN_TO_IQ.INSTS", IAP_EVENT_17H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_E", IAP_EVENT_27H_04H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ - IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ -__PMC_EV_ALIAS("HW_PRE_REQ.DL1_MISS", IAP_EVENT_4EH_02H) \ -__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("L1D.ALLOCATED_IN_M", IAP_EVENT_51H_02H) \ -__PMC_EV_ALIAS("L1D.EVICTION", IAP_EVENT_51H_04H) \ -__PMC_EV_ALIAS("L1D.ALL_M_REPLACEMENT", IAP_EVENT_51H_08H) \ -__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", IAP_EVENT_59H_20H) \ -__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", IAP_EVENT_59H_40H) \ -__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", IAP_EVENT_59H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_FL_EMPTY", IAP_EVENT_5BH_0CH) \ -__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_PRF_CONTROL", IAP_EVENT_5BH_0FH) \ -__PMC_EV_ALIAS("RESOURCE_STALLS2.BOB_FULL", IAP_EVENT_5BH_40H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS2.OOO_RSRC", IAP_EVENT_5BH_4FH) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ -__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ - IAP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ -__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ -__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ -__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ -__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ -__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ -__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_84H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_84H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ -__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.LB", IAP_EVENT_A2H_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.FCSW", IAP_EVENT_A2H_20H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ -__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ -__PMC_EV_ALIAS("DSB_FILL.OTHER_CANCEL", IAP_EVENT_ACH_02H) \ -__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ -__PMC_EV_ALIAS("DSB_FILL.ALL_CANCEL", IAP_EVENT_ACH_0AH) \ -__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED.THREAD", IAP_EVENT_B1H_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED.CORE", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \ -__PMC_EV_ALIAS("AGU_BYPASS_CANCEL.COUNT", IAP_EVENT_B6H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ -__PMC_EV_ALIAS("L1D_BLOCKS.BANK_CONFLICT_CYCLES", IAP_EVENT_BFH_05H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.ITLB_MISS_RETIRED", IAP_EVENT_C1H_02H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCH", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES_PS", IAP_EVENT_C5H_04H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ -__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ -__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ - IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ - IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", \ - IAP_EVENT_D4H_02H) \ -__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ -__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ -__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ -__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ -__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ -__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH) \ -__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) - -/* - * Aliases for Sandy Bridge Xeon PMC events (253669-044US August 2012) - */ -#define __PMC_EV_ALIAS_SANDYBRIDGE_XEON() \ -__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ -__PMC_EV_ALIAS("LD_BLOCKS.DATA_UNKNOWN", IAP_EVENT_03H_01H) \ -__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("LD_BLOCKS.ALL_BLOCK", IAP_EVENT_03H_10H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", IAP_EVENT_07H_08H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_04H) \ -__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ -__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ -__PMC_EV_ALIAS("INT_MISC.RAT_STALL_CYCLES", IAP_EVENT_0DH_40H) \ -__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \ - IAP_EVENT_10H_10H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \ - IAP_EVENT_10H_20H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \ -__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \ -__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \ -__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \ -__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ -__PMC_EV_ALIAS("INSTS_WRITTEN_TO_IQ.INSTS", IAP_EVENT_17H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ -__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ -__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ -__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ -__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_E", IAP_EVENT_27H_04H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ -__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_S", IAP_EVENT_28H_02H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ -__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ -__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ -__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ -__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ -__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ - IAP_EVENT_49H_01H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ -__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ -__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ -__PMC_EV_ALIAS("HW_PRE_REQ.DL1_MISS", IAP_EVENT_4EH_02H) \ -__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ -__PMC_EV_ALIAS("L1D.ALLOCATED_IN_M", IAP_EVENT_51H_02H) \ -__PMC_EV_ALIAS("L1D.EVICTION", IAP_EVENT_51H_04H) \ -__PMC_EV_ALIAS("L1D.ALL_M_REPLACEMENT", IAP_EVENT_51H_08H) \ -__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", IAP_EVENT_59H_20H) \ -__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", IAP_EVENT_59H_40H) \ -__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", IAP_EVENT_59H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_FL_EMPTY", IAP_EVENT_5BH_0CH) \ -__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_PRF_CONTROL", IAP_EVENT_5BH_0FH) \ -__PMC_EV_ALIAS("RESOURCE_STALLS2.BOB_FULL", IAP_EVENT_5BH_40H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS2.OOO_RSRC", IAP_EVENT_5BH_4FH) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ -__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ -__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ - IAP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ - IAP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ - IAP_EVENT_60H_08H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ - IAP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ -__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ -__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ -__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ -__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ -__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ -__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ -__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ -__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ -__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_84H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_84H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ -__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.LB", IAP_EVENT_A2H_02H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.FCSW", IAP_EVENT_A2H_20H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ -__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_02H) \ -__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", IAP_EVENT_A3H_04H) \ -__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ -__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ -__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ -__PMC_EV_ALIAS("DSB_FILL.OTHER_CANCEL", IAP_EVENT_ACH_02H) \ -__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ -__PMC_EV_ALIAS("DSB_FILL.ALL_CANCEL", IAP_EVENT_ACH_0AH) \ -__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED.THREAD", IAP_EVENT_B1H_01H) \ -__PMC_EV_ALIAS("UOPS_DISPATCHED.CORE", IAP_EVENT_B1H_02H) \ -__PMC_EV_ALIAS("OFFCORE_REQUESTS_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \ -__PMC_EV_ALIAS("AGU_BYPASS_CANCEL.COUNT", IAP_EVENT_B6H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ -__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ -__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ -__PMC_EV_ALIAS("L1D_BLOCKS.BANK_CONFLICT_CYCLES", IAP_EVENT_BFH_05H) \ -__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ -__PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.ITLB_MISS_RETIRED", IAP_EVENT_C1H_02H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ -__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ -__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ -__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCH", IAP_EVENT_C4H_00H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ -__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES_PS", IAP_EVENT_C5H_04H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ -__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ -__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ -__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ -__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ -__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ -__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ -__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ - IAP_EVENT_D2H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ - IAP_EVENT_D2H_02H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ - IAP_EVENT_D2H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ - IAP_EVENT_D2H_08H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \ - IAP_EVENT_D2H_0FH) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ - IAP_EVENT_D3H_01H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", \ - IAP_EVENT_D3H_04H) \ -__PMC_EV_ALIAS("MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", \ - IAP_EVENT_D4H_02H) \ -__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ -__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ -__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ -__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ -__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ -__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ -__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ -__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ -__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ -__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \ -__PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH) \ -__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) - -/* timestamp counters. */ -#define __PMC_EV_TSC() \ - __PMC_EV(TSC, TSC) - -#define PMC_EV_TSC_FIRST PMC_EV_TSC_TSC -#define PMC_EV_TSC_LAST PMC_EV_TSC_TSC - -/* - * Software events are dynamically defined. - */ - -#define PMC_EV_DYN_COUNT 0x1000 - -#define PMC_EV_SOFT_FIRST 0x20000 -#define PMC_EV_SOFT_LAST (PMC_EV_SOFT_FIRST + PMC_EV_DYN_COUNT - 1) - -#define __PMC_EV_UCF() \ -__PMC_EV(UCF, UCLOCK) - -#define PMC_EV_UCF_FIRST PMC_EV_UCF_UCLOCK -#define PMC_EV_UCF_LAST PMC_EV_UCF_UCLOCK - -#define __PMC_EV_UCP() \ -__PMC_EV(UCP, EVENT_00H_01H) \ -__PMC_EV(UCP, EVENT_00H_02H) \ -__PMC_EV(UCP, EVENT_00H_04H) \ -__PMC_EV(UCP, EVENT_01H_01H) \ -__PMC_EV(UCP, EVENT_01H_02H) \ -__PMC_EV(UCP, EVENT_01H_04H) \ -__PMC_EV(UCP, EVENT_02H_01H) \ -__PMC_EV(UCP, EVENT_03H_01H) \ -__PMC_EV(UCP, EVENT_03H_02H) \ -__PMC_EV(UCP, EVENT_03H_04H) \ -__PMC_EV(UCP, EVENT_03H_08H) \ -__PMC_EV(UCP, EVENT_03H_10H) \ -__PMC_EV(UCP, EVENT_03H_20H) \ -__PMC_EV(UCP, EVENT_03H_40H) \ -__PMC_EV(UCP, EVENT_04H_01H) \ -__PMC_EV(UCP, EVENT_04H_02H) \ -__PMC_EV(UCP, EVENT_04H_04H) \ -__PMC_EV(UCP, EVENT_04H_08H) \ -__PMC_EV(UCP, EVENT_04H_10H) \ -__PMC_EV(UCP, EVENT_05H_01H) \ -__PMC_EV(UCP, EVENT_05H_02H) \ -__PMC_EV(UCP, EVENT_05H_04H) \ -__PMC_EV(UCP, EVENT_06H_01H) \ -__PMC_EV(UCP, EVENT_06H_02H) \ -__PMC_EV(UCP, EVENT_06H_04H) \ -__PMC_EV(UCP, EVENT_06H_08H) \ -__PMC_EV(UCP, EVENT_06H_10H) \ -__PMC_EV(UCP, EVENT_06H_20H) \ -__PMC_EV(UCP, EVENT_07H_01H) \ -__PMC_EV(UCP, EVENT_07H_02H) \ -__PMC_EV(UCP, EVENT_07H_04H) \ -__PMC_EV(UCP, EVENT_07H_08H) \ -__PMC_EV(UCP, EVENT_07H_10H) \ -__PMC_EV(UCP, EVENT_07H_20H) \ -__PMC_EV(UCP, EVENT_07H_24H) \ -__PMC_EV(UCP, EVENT_08H_01H) \ -__PMC_EV(UCP, EVENT_08H_02H) \ -__PMC_EV(UCP, EVENT_08H_04H) \ -__PMC_EV(UCP, EVENT_08H_03H) \ -__PMC_EV(UCP, EVENT_09H_01H) \ -__PMC_EV(UCP, EVENT_09H_02H) \ -__PMC_EV(UCP, EVENT_09H_04H) \ -__PMC_EV(UCP, EVENT_09H_03H) \ -__PMC_EV(UCP, EVENT_0AH_01H) \ -__PMC_EV(UCP, EVENT_0AH_02H) \ -__PMC_EV(UCP, EVENT_0AH_04H) \ -__PMC_EV(UCP, EVENT_0AH_08H) \ -__PMC_EV(UCP, EVENT_0AH_0FH) \ -__PMC_EV(UCP, EVENT_0BH_01H) \ -__PMC_EV(UCP, EVENT_0BH_02H) \ -__PMC_EV(UCP, EVENT_0BH_04H) \ -__PMC_EV(UCP, EVENT_0BH_08H) \ -__PMC_EV(UCP, EVENT_0BH_10H) \ -__PMC_EV(UCP, EVENT_0BH_1FH) \ -__PMC_EV(UCP, EVENT_0CH_01H) \ -__PMC_EV(UCP, EVENT_0CH_02H) \ -__PMC_EV(UCP, EVENT_0CH_04H_E) \ -__PMC_EV(UCP, EVENT_0CH_04H_F) \ -__PMC_EV(UCP, EVENT_0CH_04H_M) \ -__PMC_EV(UCP, EVENT_0CH_04H_S) \ -__PMC_EV(UCP, EVENT_0CH_08H_E) \ -__PMC_EV(UCP, EVENT_0CH_08H_F) \ -__PMC_EV(UCP, EVENT_0CH_08H_M) \ -__PMC_EV(UCP, EVENT_0CH_08H_S) \ -__PMC_EV(UCP, EVENT_20H_01H) \ -__PMC_EV(UCP, EVENT_20H_02H) \ -__PMC_EV(UCP, EVENT_20H_04H) \ -__PMC_EV(UCP, EVENT_20H_08H) \ -__PMC_EV(UCP, EVENT_20H_10H) \ -__PMC_EV(UCP, EVENT_20H_20H) \ -__PMC_EV(UCP, EVENT_21H_01H) \ -__PMC_EV(UCP, EVENT_21H_02H) \ -__PMC_EV(UCP, EVENT_21H_04H) \ -__PMC_EV(UCP, EVENT_22H_01H) \ -__PMC_EV(UCP, EVENT_22H_02H) \ -__PMC_EV(UCP, EVENT_22H_04H) \ -__PMC_EV(UCP, EVENT_22H_08H) \ -__PMC_EV(UCP, EVENT_22H_10H) \ -__PMC_EV(UCP, EVENT_22H_20H) \ -__PMC_EV(UCP, EVENT_22H_40H) \ -__PMC_EV(UCP, EVENT_22H_80H) \ -__PMC_EV(UCP, EVENT_23H_01H) \ -__PMC_EV(UCP, EVENT_23H_02H) \ -__PMC_EV(UCP, EVENT_23H_04H) \ -__PMC_EV(UCP, EVENT_24H_02H) \ -__PMC_EV(UCP, EVENT_24H_04H) \ -__PMC_EV(UCP, EVENT_25H_01H) \ -__PMC_EV(UCP, EVENT_25H_02H) \ -__PMC_EV(UCP, EVENT_25H_04H) \ -__PMC_EV(UCP, EVENT_26H_01H) \ -__PMC_EV(UCP, EVENT_27H_01H) \ -__PMC_EV(UCP, EVENT_27H_02H) \ -__PMC_EV(UCP, EVENT_27H_04H) \ -__PMC_EV(UCP, EVENT_27H_08H) \ -__PMC_EV(UCP, EVENT_27H_10H) \ -__PMC_EV(UCP, EVENT_27H_20H) \ -__PMC_EV(UCP, EVENT_28H_01H) \ -__PMC_EV(UCP, EVENT_28H_02H) \ -__PMC_EV(UCP, EVENT_28H_04H) \ -__PMC_EV(UCP, EVENT_28H_08H) \ -__PMC_EV(UCP, EVENT_28H_10H) \ -__PMC_EV(UCP, EVENT_28H_20H) \ -__PMC_EV(UCP, EVENT_29H_01H) \ -__PMC_EV(UCP, EVENT_29H_02H) \ -__PMC_EV(UCP, EVENT_29H_04H) \ -__PMC_EV(UCP, EVENT_29H_08H) \ -__PMC_EV(UCP, EVENT_29H_10H) \ -__PMC_EV(UCP, EVENT_29H_20H) \ -__PMC_EV(UCP, EVENT_2AH_01H) \ -__PMC_EV(UCP, EVENT_2AH_02H) \ -__PMC_EV(UCP, EVENT_2AH_04H) \ -__PMC_EV(UCP, EVENT_2AH_07H) \ -__PMC_EV(UCP, EVENT_2BH_01H) \ -__PMC_EV(UCP, EVENT_2BH_02H) \ -__PMC_EV(UCP, EVENT_2BH_04H) \ -__PMC_EV(UCP, EVENT_2BH_07H) \ -__PMC_EV(UCP, EVENT_2CH_01H) \ -__PMC_EV(UCP, EVENT_2CH_02H) \ -__PMC_EV(UCP, EVENT_2CH_04H) \ -__PMC_EV(UCP, EVENT_2CH_07H) \ -__PMC_EV(UCP, EVENT_2DH_01H) \ -__PMC_EV(UCP, EVENT_2DH_02H) \ -__PMC_EV(UCP, EVENT_2DH_04H) \ -__PMC_EV(UCP, EVENT_2DH_07H) \ -__PMC_EV(UCP, EVENT_2EH_01H) \ -__PMC_EV(UCP, EVENT_2EH_02H) \ -__PMC_EV(UCP, EVENT_2EH_04H) \ -__PMC_EV(UCP, EVENT_2EH_07H) \ -__PMC_EV(UCP, EVENT_2FH_01H) \ -__PMC_EV(UCP, EVENT_2FH_02H) \ -__PMC_EV(UCP, EVENT_2FH_04H) \ -__PMC_EV(UCP, EVENT_2FH_07H) \ -__PMC_EV(UCP, EVENT_2FH_08H) \ -__PMC_EV(UCP, EVENT_2FH_10H) \ -__PMC_EV(UCP, EVENT_2FH_20H) \ -__PMC_EV(UCP, EVENT_2FH_38H) \ -__PMC_EV(UCP, EVENT_30H_01H) \ -__PMC_EV(UCP, EVENT_30H_02H) \ -__PMC_EV(UCP, EVENT_30H_04H) \ -__PMC_EV(UCP, EVENT_30H_07H) \ -__PMC_EV(UCP, EVENT_31H_01H) \ -__PMC_EV(UCP, EVENT_31H_02H) \ -__PMC_EV(UCP, EVENT_31H_04H) \ -__PMC_EV(UCP, EVENT_31H_07H) \ -__PMC_EV(UCP, EVENT_32H_01H) \ -__PMC_EV(UCP, EVENT_32H_02H) \ -__PMC_EV(UCP, EVENT_32H_04H) \ -__PMC_EV(UCP, EVENT_32H_07H) \ -__PMC_EV(UCP, EVENT_33H_01H) \ -__PMC_EV(UCP, EVENT_33H_02H) \ -__PMC_EV(UCP, EVENT_33H_04H) \ -__PMC_EV(UCP, EVENT_33H_07H) \ -__PMC_EV(UCP, EVENT_34H_01H) \ -__PMC_EV(UCP, EVENT_34H_02H) \ -__PMC_EV(UCP, EVENT_34H_04H) \ -__PMC_EV(UCP, EVENT_34H_06H) \ -__PMC_EV(UCP, EVENT_34H_08H) \ -__PMC_EV(UCP, EVENT_34H_10H) \ -__PMC_EV(UCP, EVENT_34H_20H) \ -__PMC_EV(UCP, EVENT_34H_40H) \ -__PMC_EV(UCP, EVENT_34H_80H) \ -__PMC_EV(UCP, EVENT_35H_01H) \ -__PMC_EV(UCP, EVENT_35H_02H) \ -__PMC_EV(UCP, EVENT_35H_04H) \ -__PMC_EV(UCP, EVENT_40H_01H) \ -__PMC_EV(UCP, EVENT_40H_02H) \ -__PMC_EV(UCP, EVENT_40H_04H) \ -__PMC_EV(UCP, EVENT_40H_08H) \ -__PMC_EV(UCP, EVENT_40H_10H) \ -__PMC_EV(UCP, EVENT_40H_20H) \ -__PMC_EV(UCP, EVENT_40H_07H) \ -__PMC_EV(UCP, EVENT_40H_38H) \ -__PMC_EV(UCP, EVENT_41H_01H) \ -__PMC_EV(UCP, EVENT_41H_02H) \ -__PMC_EV(UCP, EVENT_41H_04H) \ -__PMC_EV(UCP, EVENT_41H_08H) \ -__PMC_EV(UCP, EVENT_41H_10H) \ -__PMC_EV(UCP, EVENT_41H_20H) \ -__PMC_EV(UCP, EVENT_41H_07H) \ -__PMC_EV(UCP, EVENT_41H_38H) \ -__PMC_EV(UCP, EVENT_42H_01H) \ -__PMC_EV(UCP, EVENT_42H_02H) \ -__PMC_EV(UCP, EVENT_42H_04H) \ -__PMC_EV(UCP, EVENT_42H_08H) \ -__PMC_EV(UCP, EVENT_43H_01H) \ -__PMC_EV(UCP, EVENT_43H_02H) \ -__PMC_EV(UCP, EVENT_60H_01H) \ -__PMC_EV(UCP, EVENT_60H_02H) \ -__PMC_EV(UCP, EVENT_60H_04H) \ -__PMC_EV(UCP, EVENT_61H_01H) \ -__PMC_EV(UCP, EVENT_61H_02H) \ -__PMC_EV(UCP, EVENT_61H_04H) \ -__PMC_EV(UCP, EVENT_62H_01H) \ -__PMC_EV(UCP, EVENT_62H_02H) \ -__PMC_EV(UCP, EVENT_62H_04H) \ -__PMC_EV(UCP, EVENT_63H_01H) \ -__PMC_EV(UCP, EVENT_63H_02H) \ -__PMC_EV(UCP, EVENT_63H_04H) \ -__PMC_EV(UCP, EVENT_63H_08H) \ -__PMC_EV(UCP, EVENT_63H_10H) \ -__PMC_EV(UCP, EVENT_63H_20H) \ -__PMC_EV(UCP, EVENT_64H_01H) \ -__PMC_EV(UCP, EVENT_64H_02H) \ -__PMC_EV(UCP, EVENT_64H_04H) \ -__PMC_EV(UCP, EVENT_64H_08H) \ -__PMC_EV(UCP, EVENT_64H_10H) \ -__PMC_EV(UCP, EVENT_64H_20H) \ -__PMC_EV(UCP, EVENT_65H_01H) \ -__PMC_EV(UCP, EVENT_65H_02H) \ -__PMC_EV(UCP, EVENT_65H_04H) \ -__PMC_EV(UCP, EVENT_66H_01H) \ -__PMC_EV(UCP, EVENT_66H_02H) \ -__PMC_EV(UCP, EVENT_66H_04H) \ -__PMC_EV(UCP, EVENT_67H_01H) \ -__PMC_EV(UCP, EVENT_80H_01H) \ -__PMC_EV(UCP, EVENT_80H_02H) \ -__PMC_EV(UCP, EVENT_80H_04H) \ -__PMC_EV(UCP, EVENT_80H_08H) \ -__PMC_EV(UCP, EVENT_81H_01H) \ -__PMC_EV(UCP, EVENT_81H_02H) \ -__PMC_EV(UCP, EVENT_81H_04H) \ -__PMC_EV(UCP, EVENT_81H_08H) \ -__PMC_EV(UCP, EVENT_81H_20H) \ -__PMC_EV(UCP, EVENT_81H_80H) \ -__PMC_EV(UCP, EVENT_82H_01H) \ -__PMC_EV(UCP, EVENT_83H_01H) \ -__PMC_EV(UCP, EVENT_83H_02H) \ -__PMC_EV(UCP, EVENT_83H_04H) \ -__PMC_EV(UCP, EVENT_83H_08H) \ -__PMC_EV(UCP, EVENT_84H_01H) \ -__PMC_EV(UCP, EVENT_84H_02H) \ -__PMC_EV(UCP, EVENT_84H_04H) \ -__PMC_EV(UCP, EVENT_84H_08H) \ -__PMC_EV(UCP, EVENT_85H_02H) \ -__PMC_EV(UCP, EVENT_86H_01H) - -#define PMC_EV_UCP_FIRST PMC_EV_UCP_EVENT_00H_01H -#define PMC_EV_UCP_LAST PMC_EV_UCP_EVENT_86H_01H - -/* - * Aliases for Broadwell uncore PMC events - */ -#define __PMC_EV_ALIAS_BROADWELLUC() \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.MISS", UCP_EVENT_22H_01H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL", UCP_EVENT_22H_02H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HIT", UCP_EVENT_22H_04H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HITM", UCP_EVENT_22H_08H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL_M", UCP_EVENT_22H_10H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", \ - UCP_EVENT_22H_20H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", UCP_EVENT_22H_40H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", \ - UCP_EVENT_22H_80H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.M", UCP_EVENT_34H_01H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ES", UCP_EVENT_34H_06H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.I", UCP_EVENT_34H_08H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.READ_FILTER", UCP_EVENT_34H_10H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", UCP_EVENT_34H_20H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", UCP_EVENT_34H_40H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", \ - UCP_EVENT_34H_80H) \ -__PMC_EV_ALIAS("UNC_ARB_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H) \ -__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.ALL", UCP_EVENT_81H_01H) \ -__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H) \ -__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H) \ -__PMC_EV_ALIAS("UNC_ARB_COH_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H) \ -__PMC_EV_ALIAS("UNC_ARB_COH_TRK_REQUEST.ALL", UCP_EVENT_84H_01H) - -#define __PMC_EV_ALIAS_COREI7UC() \ -__PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \ -__PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \ -__PMC_EV_ALIAS("GQ_CYCLES_FULL.PEER_PROBE_TRACKER", UCP_EVENT_00H_04H) \ -__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.READ_TRACKER", UCP_EVENT_01H_01H) \ -__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER", UCP_EVENT_01H_02H) \ -__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER", \ - UCP_EVENT_01H_04H) \ -__PMC_EV_ALIAS("GQ_ALLOC.READ_TRACKER", UCP_EVENT_03H_01H) \ -__PMC_EV_ALIAS("GQ_ALLOC.RT_L3_MISS", UCP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_L3_RESP", UCP_EVENT_03H_04H) \ -__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_RTID_ACQUIRED", UCP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("GQ_ALLOC.WT_TO_RTID_ACQUIRED", UCP_EVENT_03H_10H) \ -__PMC_EV_ALIAS("GQ_ALLOC.WRITE_TRACKER", UCP_EVENT_03H_20H) \ -__PMC_EV_ALIAS("GQ_ALLOC.PEER_PROBE_TRACKER", UCP_EVENT_03H_40H) \ -__PMC_EV_ALIAS("GQ_DATA.FROM_QPI", UCP_EVENT_04H_01H) \ -__PMC_EV_ALIAS("GQ_DATA.FROM_QMC", UCP_EVENT_04H_02H) \ -__PMC_EV_ALIAS("GQ_DATA.FROM_L3", UCP_EVENT_04H_04H) \ -__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_02", UCP_EVENT_04H_08H) \ -__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_13", UCP_EVENT_04H_10H) \ -__PMC_EV_ALIAS("GQ_DATA.TO_QPI_QMC", UCP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("GQ_DATA.TO_L3", UCP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("GQ_DATA.TO_CORES", UCP_EVENT_05H_04H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.I_STATE", UCP_EVENT_06H_01H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.S_STATE", UCP_EVENT_06H_02H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE", UCP_EVENT_06H_04H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE", UCP_EVENT_06H_08H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.CONFLICT", UCP_EVENT_06H_10H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.WB", UCP_EVENT_06H_20H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.I_STATE", UCP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.S_STATE", UCP_EVENT_07H_02H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE", UCP_EVENT_07H_04H)\ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE", UCP_EVENT_07H_08H)\ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.CONFLICT", UCP_EVENT_07H_10H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.WB", UCP_EVENT_07H_20H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.HITM", UCP_EVENT_07H_24H) \ -__PMC_EV_ALIAS("L3_HITS.READ", UCP_EVENT_08H_01H) \ -__PMC_EV_ALIAS("L3_HITS.WRITE", UCP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("L3_HITS.PROBE", UCP_EVENT_08H_04H) \ -__PMC_EV_ALIAS("L3_HITS.ANY", UCP_EVENT_08H_03H) \ -__PMC_EV_ALIAS("L3_MISS.READ", UCP_EVENT_09H_01H) \ -__PMC_EV_ALIAS("L3_MISS.WRITE", UCP_EVENT_09H_02H) \ -__PMC_EV_ALIAS("L3_MISS.PROBE", UCP_EVENT_09H_04H) \ -__PMC_EV_ALIAS("L3_MISS.ANY", UCP_EVENT_09H_03H) \ -__PMC_EV_ALIAS("L3_LINES_IN.M_STATE", UCP_EVENT_0AH_01H) \ -__PMC_EV_ALIAS("L3_LINES_IN.E_STATE", UCP_EVENT_0AH_02H) \ -__PMC_EV_ALIAS("L3_LINES_IN.S_STATE", UCP_EVENT_0AH_04H) \ -__PMC_EV_ALIAS("L3_LINES_IN.F_STATE", UCP_EVENT_0AH_08H) \ -__PMC_EV_ALIAS("L3_LINES_IN.ANY", UCP_EVENT_0AH_0FH) \ -__PMC_EV_ALIAS("L3_LINES_OUT.M_STATE", UCP_EVENT_0BH_01H) \ -__PMC_EV_ALIAS("L3_LINES_OUT.E_STATE", UCP_EVENT_0BH_02H) \ -__PMC_EV_ALIAS("L3_LINES_OUT.S_STATE", UCP_EVENT_0BH_04H) \ -__PMC_EV_ALIAS("L3_LINES_OUT.I_STATE", UCP_EVENT_0BH_08H) \ -__PMC_EV_ALIAS("L3_LINES_OUT.F_STATE", UCP_EVENT_0BH_10H) \ -__PMC_EV_ALIAS("L3_LINES_OUT.ANY", UCP_EVENT_0BH_1FH) \ -__PMC_EV_ALIAS("QHL_REQUESTS.IOH_READS", UCP_EVENT_20H_01H) \ -__PMC_EV_ALIAS("QHL_REQUESTS.IOH_WRITES", UCP_EVENT_20H_02H) \ -__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_READS", UCP_EVENT_20H_04H) \ -__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_WRITES", UCP_EVENT_20H_08H) \ -__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_READS", UCP_EVENT_20H_10H) \ -__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_WRITES", UCP_EVENT_20H_20H) \ -__PMC_EV_ALIAS("QHL_CYCLES_FULL.IOH", UCP_EVENT_21H_01H) \ -__PMC_EV_ALIAS("QHL_CYCLES_FULL.REMOTE", UCP_EVENT_21H_02H) \ -__PMC_EV_ALIAS("QHL_CYCLES_FULL.LOCAL", UCP_EVENT_21H_04H) \ -__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.IOH", UCP_EVENT_22H_01H) \ -__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.REMOTE", UCP_EVENT_22H_02H) \ -__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.LOCAL", UCP_EVENT_22H_04H) \ -__PMC_EV_ALIAS("QHL_OCCUPANCY.IOH", UCP_EVENT_23H_01H) \ -__PMC_EV_ALIAS("QHL_OCCUPANCY.REMOTE", UCP_EVENT_23H_02H) \ -__PMC_EV_ALIAS("QHL_OCCUPANCY.LOCAL", UCP_EVENT_23H_04H) \ -__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.2WAY", UCP_EVENT_24H_02H) \ -__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.3WAY", UCP_EVENT_24H_04H) \ -__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.IOH", UCP_EVENT_25H_01H) \ -__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.REMOTE", UCP_EVENT_25H_02H) \ -__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.LOCAL", UCP_EVENT_25H_04H) \ -__PMC_EV_ALIAS("QHL_TO_QMC_BYPASS", UCP_EVENT_26H_01H) \ -__PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH0", UCP_EVENT_27H_01H) \ -__PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH1", UCP_EVENT_27H_02H) \ -__PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH2", UCP_EVENT_27H_04H) \ -__PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH0", UCP_EVENT_27H_08H) \ -__PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH1", UCP_EVENT_27H_10H) \ -__PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH2", UCP_EVENT_27H_20H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH0", UCP_EVENT_28H_01H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH1", UCP_EVENT_28H_02H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH2", UCP_EVENT_28H_04H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH0", UCP_EVENT_28H_08H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH1", UCP_EVENT_28H_10H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH2", UCP_EVENT_28H_20H) \ -__PMC_EV_ALIAS("QMC_BUSY.READ.CH0", UCP_EVENT_29H_01H) \ -__PMC_EV_ALIAS("QMC_BUSY.READ.CH1", UCP_EVENT_29H_02H) \ -__PMC_EV_ALIAS("QMC_BUSY.READ.CH2", UCP_EVENT_29H_04H) \ -__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH0", UCP_EVENT_29H_08H) \ -__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH1", UCP_EVENT_29H_10H) \ -__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH2", UCP_EVENT_29H_20H) \ -__PMC_EV_ALIAS("QMC_OCCUPANCY.CH0", UCP_EVENT_2AH_01H) \ -__PMC_EV_ALIAS("QMC_OCCUPANCY.CH1", UCP_EVENT_2AH_02H) \ -__PMC_EV_ALIAS("QMC_OCCUPANCY.CH2", UCP_EVENT_2AH_04H) \ -__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH0", UCP_EVENT_2BH_01H) \ -__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH1", UCP_EVENT_2BH_02H) \ -__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH2", UCP_EVENT_2BH_04H) \ -__PMC_EV_ALIAS("QMC_ISSOC_READS.ANY", UCP_EVENT_2BH_07H) \ -__PMC_EV_ALIAS("QMC_NORMAL_READS.CH0", UCP_EVENT_2CH_01H) \ -__PMC_EV_ALIAS("QMC_NORMAL_READS.CH1", UCP_EVENT_2CH_02H) \ -__PMC_EV_ALIAS("QMC_NORMAL_READS.CH2", UCP_EVENT_2CH_04H) \ -__PMC_EV_ALIAS("QMC_NORMAL_READS.ANY", UCP_EVENT_2CH_07H) \ -__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH0", UCP_EVENT_2DH_01H) \ -__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH1", UCP_EVENT_2DH_02H) \ -__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH2", UCP_EVENT_2DH_04H) \ -__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.ANY", UCP_EVENT_2DH_07H) \ -__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH0", UCP_EVENT_2EH_01H) \ -__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH1", UCP_EVENT_2EH_02H) \ -__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH2", UCP_EVENT_2EH_04H) \ -__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.ANY", UCP_EVENT_2EH_07H) \ -__PMC_EV_ALIAS("QMC_WRITES.FULL.CH0", UCP_EVENT_2FH_01H) \ -__PMC_EV_ALIAS("QMC_WRITES.FULL.CH1", UCP_EVENT_2FH_02H) \ -__PMC_EV_ALIAS("QMC_WRITES.FULL.CH2", UCP_EVENT_2FH_04H) \ -__PMC_EV_ALIAS("QMC_WRITES.FULL.ANY", UCP_EVENT_2FH_07H) \ -__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH0", UCP_EVENT_2FH_08H) \ -__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH1", UCP_EVENT_2FH_10H) \ -__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH2", UCP_EVENT_2FH_20H) \ -__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.ANY", UCP_EVENT_2FH_38H) \ -__PMC_EV_ALIAS("QMC_CANCEL.CH0", UCP_EVENT_30H_01H) \ -__PMC_EV_ALIAS("QMC_CANCEL.CH1", UCP_EVENT_30H_02H) \ -__PMC_EV_ALIAS("QMC_CANCEL.CH2", UCP_EVENT_30H_04H) \ -__PMC_EV_ALIAS("QMC_CANCEL.ANY", UCP_EVENT_30H_07H) \ -__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH0", UCP_EVENT_31H_01H) \ -__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH1", UCP_EVENT_31H_02H) \ -__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH2", UCP_EVENT_31H_04H) \ -__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.ANY", UCP_EVENT_31H_07H) \ -__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.LOCAL", UCP_EVENT_33H_04H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0", \ - UCP_EVENT_40H_01H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0", \ - UCP_EVENT_40H_02H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0", \ - UCP_EVENT_40H_04H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1", \ - UCP_EVENT_40H_08H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1", \ - UCP_EVENT_40H_10H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1", \ - UCP_EVENT_40H_20H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_0", UCP_EVENT_40H_07H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_1", UCP_EVENT_40H_38H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0", \ - UCP_EVENT_41H_01H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0", \ - UCP_EVENT_41H_02H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0", \ - UCP_EVENT_41H_04H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1", \ - UCP_EVENT_41H_08H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1", \ - UCP_EVENT_41H_10H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1", \ - UCP_EVENT_41H_20H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_0", UCP_EVENT_41H_07H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_1", UCP_EVENT_41H_38H) \ -__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_0", UCP_EVENT_42H_02H) \ -__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_1", UCP_EVENT_42H_08H) \ -__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0", UCP_EVENT_43H_01H) \ -__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1", UCP_EVENT_43H_02H) \ -__PMC_EV_ALIAS("DRAM_OPEN.CH0", UCP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("DRAM_OPEN.CH1", UCP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("DRAM_OPEN.CH2", UCP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH0", UCP_EVENT_61H_01H) \ -__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH1", UCP_EVENT_61H_02H) \ -__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH2", UCP_EVENT_61H_04H) \ -__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH0", UCP_EVENT_62H_01H) \ -__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH1", UCP_EVENT_62H_02H) \ -__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH2", UCP_EVENT_62H_04H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.CH0", UCP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH0", UCP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.CH1", UCP_EVENT_63H_04H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH1", UCP_EVENT_63H_08H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.CH2", UCP_EVENT_63H_10H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH2", UCP_EVENT_63H_20H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH0", UCP_EVENT_64H_01H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH0", UCP_EVENT_64H_02H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH1", UCP_EVENT_64H_04H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH1", UCP_EVENT_64H_08H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH2", UCP_EVENT_64H_10H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH2", UCP_EVENT_64H_20H) \ -__PMC_EV_ALIAS("DRAM_REFRESH.CH0", UCP_EVENT_65H_01H) \ -__PMC_EV_ALIAS("DRAM_REFRESH.CH1", UCP_EVENT_65H_02H) \ -__PMC_EV_ALIAS("DRAM_REFRESH.CH2", UCP_EVENT_65H_04H) \ -__PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H) \ -__PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H) \ -__PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H) - -/* - * Aliases for Haswell uncore PMC events - */ -#define __PMC_EV_ALIAS_HASWELLUC() \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.MISS", UCP_EVENT_22H_01H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL", UCP_EVENT_22H_02H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HIT", UCP_EVENT_22H_04H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HITM", UCP_EVENT_22H_08H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL_M", UCP_EVENT_22H_10H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", \ - UCP_EVENT_22H_20H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", UCP_EVENT_22H_40H) \ -__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", \ - UCP_EVENT_22H_80H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.M", UCP_EVENT_34H_01H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ES", UCP_EVENT_34H_06H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.I", UCP_EVENT_34H_08H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.READ_FILTER", UCP_EVENT_34H_10H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", UCP_EVENT_34H_20H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", UCP_EVENT_34H_40H) \ -__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", \ - UCP_EVENT_34H_80H) \ -__PMC_EV_ALIAS("UNC_ARB_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H) \ -__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.ALL", UCP_EVENT_81H_01H) \ -__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H) \ -__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H) \ -__PMC_EV_ALIAS("UNC_ARB_COH_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H) \ -__PMC_EV_ALIAS("UNC_ARB_COH_TRK_REQUEST.ALL", UCP_EVENT_84H_01H) - - -#define __PMC_EV_ALIAS_WESTMEREUC() \ -__PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \ -__PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \ -__PMC_EV_ALIAS("GQ_CYCLES_FULL.PEER_PROBE_TRACKER", UCP_EVENT_00H_04H) \ -__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.READ_TRACKER", UCP_EVENT_01H_01H) \ -__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER", UCP_EVENT_01H_02H) \ -__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER", \ - UCP_EVENT_01H_04H) \ -__PMC_EV_ALIAS("GQ_OCCUPANCY.READ_TRACKER", UCP_EVENT_02H_01H) \ -__PMC_EV_ALIAS("GQ_ALLOC.READ_TRACKER", UCP_EVENT_03H_01H) \ -__PMC_EV_ALIAS("GQ_ALLOC.RT_L3_MISS", UCP_EVENT_03H_02H) \ -__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_L3_RESP", UCP_EVENT_03H_04H) \ -__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_RTID_ACQUIRED", UCP_EVENT_03H_08H) \ -__PMC_EV_ALIAS("GQ_ALLOC.WT_TO_RTID_ACQUIRED", UCP_EVENT_03H_10H) \ -__PMC_EV_ALIAS("GQ_ALLOC.WRITE_TRACKER", UCP_EVENT_03H_20H) \ -__PMC_EV_ALIAS("GQ_ALLOC.PEER_PROBE_TRACKER", UCP_EVENT_03H_40H) \ -__PMC_EV_ALIAS("GQ_DATA.FROM_QPI", UCP_EVENT_04H_01H) \ -__PMC_EV_ALIAS("GQ_DATA.FROM_QMC", UCP_EVENT_04H_02H) \ -__PMC_EV_ALIAS("GQ_DATA.FROM_L3", UCP_EVENT_04H_04H) \ -__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_02", UCP_EVENT_04H_08H) \ -__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_13", UCP_EVENT_04H_10H) \ -__PMC_EV_ALIAS("GQ_DATA.TO_QPI_QMC", UCP_EVENT_05H_01H) \ -__PMC_EV_ALIAS("GQ_DATA.TO_L3", UCP_EVENT_05H_02H) \ -__PMC_EV_ALIAS("GQ_DATA.TO_CORES", UCP_EVENT_05H_04H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.I_STATE", UCP_EVENT_06H_01H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.S_STATE", UCP_EVENT_06H_02H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE", UCP_EVENT_06H_04H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE", UCP_EVENT_06H_08H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.CONFLICT", UCP_EVENT_06H_10H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.WB", UCP_EVENT_06H_20H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.I_STATE", UCP_EVENT_07H_01H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.S_STATE", UCP_EVENT_07H_02H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE", UCP_EVENT_07H_04H)\ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE", UCP_EVENT_07H_08H)\ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.CONFLICT", UCP_EVENT_07H_10H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.WB", UCP_EVENT_07H_20H) \ -__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.HITM", UCP_EVENT_07H_24H) \ -__PMC_EV_ALIAS("L3_HITS.READ", UCP_EVENT_08H_01H) \ -__PMC_EV_ALIAS("L3_HITS.WRITE", UCP_EVENT_08H_02H) \ -__PMC_EV_ALIAS("L3_HITS.PROBE", UCP_EVENT_08H_04H) \ -__PMC_EV_ALIAS("L3_HITS.ANY", UCP_EVENT_08H_03H) \ -__PMC_EV_ALIAS("L3_MISS.READ", UCP_EVENT_09H_01H) \ -__PMC_EV_ALIAS("L3_MISS.WRITE", UCP_EVENT_09H_02H) \ -__PMC_EV_ALIAS("L3_MISS.PROBE", UCP_EVENT_09H_04H) \ -__PMC_EV_ALIAS("L3_MISS.ANY", UCP_EVENT_09H_03H) \ -__PMC_EV_ALIAS("L3_LINES_IN.M_STATE", UCP_EVENT_0AH_01H) \ -__PMC_EV_ALIAS("L3_LINES_IN.E_STATE", UCP_EVENT_0AH_02H) \ -__PMC_EV_ALIAS("L3_LINES_IN.S_STATE", UCP_EVENT_0AH_04H) \ -__PMC_EV_ALIAS("L3_LINES_IN.F_STATE", UCP_EVENT_0AH_08H) \ -__PMC_EV_ALIAS("L3_LINES_IN.ANY", UCP_EVENT_0AH_0FH) \ -__PMC_EV_ALIAS("L3_LINES_OUT.M_STATE", UCP_EVENT_0BH_01H) \ -__PMC_EV_ALIAS("L3_LINES_OUT.E_STATE", UCP_EVENT_0BH_02H) \ -__PMC_EV_ALIAS("L3_LINES_OUT.S_STATE", UCP_EVENT_0BH_04H) \ -__PMC_EV_ALIAS("L3_LINES_OUT.I_STATE", UCP_EVENT_0BH_08H) \ -__PMC_EV_ALIAS("L3_LINES_OUT.F_STATE", UCP_EVENT_0BH_10H) \ -__PMC_EV_ALIAS("L3_LINES_OUT.ANY", UCP_EVENT_0BH_1FH) \ -__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S", UCP_EVENT_0CH_01H) \ -__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I", UCP_EVENT_0CH_02H) \ -__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_E", UCP_EVENT_0CH_04H_E) \ -__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_F", UCP_EVENT_0CH_04H_F) \ -__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_M", UCP_EVENT_0CH_04H_M) \ -__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_S", UCP_EVENT_0CH_04H_S) \ -__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_E", UCP_EVENT_0CH_08H_E) \ -__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_F", UCP_EVENT_0CH_08H_F) \ -__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_M", UCP_EVENT_0CH_08H_M) \ -__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_S", UCP_EVENT_0CH_08H_S) \ -__PMC_EV_ALIAS("QHL_REQUESTS.IOH_READS", UCP_EVENT_20H_01H) \ -__PMC_EV_ALIAS("QHL_REQUESTS.IOH_WRITES", UCP_EVENT_20H_02H) \ -__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_READS", UCP_EVENT_20H_04H) \ -__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_WRITES", UCP_EVENT_20H_08H) \ -__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_READS", UCP_EVENT_20H_10H) \ -__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_WRITES", UCP_EVENT_20H_20H) \ -__PMC_EV_ALIAS("QHL_CYCLES_FULL.IOH", UCP_EVENT_21H_01H) \ -__PMC_EV_ALIAS("QHL_CYCLES_FULL.REMOTE", UCP_EVENT_21H_02H) \ -__PMC_EV_ALIAS("QHL_CYCLES_FULL.LOCAL", UCP_EVENT_21H_04H) \ -__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.IOH", UCP_EVENT_22H_01H) \ -__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.REMOTE", UCP_EVENT_22H_02H) \ -__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.LOCAL", UCP_EVENT_22H_04H) \ -__PMC_EV_ALIAS("QHL_OCCUPANCY.IOH", UCP_EVENT_23H_01H) \ -__PMC_EV_ALIAS("QHL_OCCUPANCY.REMOTE", UCP_EVENT_23H_02H) \ -__PMC_EV_ALIAS("QHL_OCCUPANCY.LOCAL", UCP_EVENT_23H_04H) \ -__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.2WAY", UCP_EVENT_24H_02H) \ -__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.3WAY", UCP_EVENT_24H_04H) \ -__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.IOH", UCP_EVENT_25H_01H) \ -__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.REMOTE", UCP_EVENT_25H_02H) \ -__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.LOCAL", UCP_EVENT_25H_04H) \ -__PMC_EV_ALIAS("QHL_TO_QMC_BYPASS", UCP_EVENT_26H_01H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH0", UCP_EVENT_28H_01H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH1", UCP_EVENT_28H_02H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH2", UCP_EVENT_28H_04H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH0", UCP_EVENT_28H_08H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH1", UCP_EVENT_28H_10H) \ -__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH2", UCP_EVENT_28H_20H) \ -__PMC_EV_ALIAS("QMC_BUSY.READ.CH0", UCP_EVENT_29H_01H) \ -__PMC_EV_ALIAS("QMC_BUSY.READ.CH1", UCP_EVENT_29H_02H) \ -__PMC_EV_ALIAS("QMC_BUSY.READ.CH2", UCP_EVENT_29H_04H) \ -__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH0", UCP_EVENT_29H_08H) \ -__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH1", UCP_EVENT_29H_10H) \ -__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH2", UCP_EVENT_29H_20H) \ -__PMC_EV_ALIAS("QMC_OCCUPANCY.CH0", UCP_EVENT_2AH_01H) \ -__PMC_EV_ALIAS("QMC_OCCUPANCY.CH1", UCP_EVENT_2AH_02H) \ -__PMC_EV_ALIAS("QMC_OCCUPANCY.CH2", UCP_EVENT_2AH_04H) \ -__PMC_EV_ALIAS("QMC_OCCUPANCY.ANY", UCP_EVENT_2AH_07H) \ -__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH0", UCP_EVENT_2BH_01H) \ -__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH1", UCP_EVENT_2BH_02H) \ -__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH2", UCP_EVENT_2BH_04H) \ -__PMC_EV_ALIAS("QMC_ISSOC_READS.ANY", UCP_EVENT_2BH_07H) \ -__PMC_EV_ALIAS("QMC_NORMAL_READS.CH0", UCP_EVENT_2CH_01H) \ -__PMC_EV_ALIAS("QMC_NORMAL_READS.CH1", UCP_EVENT_2CH_02H) \ -__PMC_EV_ALIAS("QMC_NORMAL_READS.CH2", UCP_EVENT_2CH_04H) \ -__PMC_EV_ALIAS("QMC_NORMAL_READS.ANY", UCP_EVENT_2CH_07H) \ -__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH0", UCP_EVENT_2DH_01H) \ -__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH1", UCP_EVENT_2DH_02H) \ -__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH2", UCP_EVENT_2DH_04H) \ -__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.ANY", UCP_EVENT_2DH_07H) \ -__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH0", UCP_EVENT_2EH_01H) \ -__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH1", UCP_EVENT_2EH_02H) \ -__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH2", UCP_EVENT_2EH_04H) \ -__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.ANY", UCP_EVENT_2EH_07H) \ -__PMC_EV_ALIAS("QMC_WRITES.FULL.CH0", UCP_EVENT_2FH_01H) \ -__PMC_EV_ALIAS("QMC_WRITES.FULL.CH1", UCP_EVENT_2FH_02H) \ -__PMC_EV_ALIAS("QMC_WRITES.FULL.CH2", UCP_EVENT_2FH_04H) \ -__PMC_EV_ALIAS("QMC_WRITES.FULL.ANY", UCP_EVENT_2FH_07H) \ -__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH0", UCP_EVENT_2FH_08H) \ -__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH1", UCP_EVENT_2FH_10H) \ -__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH2", UCP_EVENT_2FH_20H) \ -__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.ANY", UCP_EVENT_2FH_38H) \ -__PMC_EV_ALIAS("QMC_CANCEL.CH0", UCP_EVENT_30H_01H) \ -__PMC_EV_ALIAS("QMC_CANCEL.CH1", UCP_EVENT_30H_02H) \ -__PMC_EV_ALIAS("QMC_CANCEL.CH2", UCP_EVENT_30H_04H) \ -__PMC_EV_ALIAS("QMC_CANCEL.ANY", UCP_EVENT_30H_07H) \ -__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH0", UCP_EVENT_31H_01H) \ -__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH1", UCP_EVENT_31H_02H) \ -__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH2", UCP_EVENT_31H_04H) \ -__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.ANY", UCP_EVENT_31H_07H) \ -__PMC_EV_ALIAS("IMC_RETRY.CH0", UCP_EVENT_32H_01H) \ -__PMC_EV_ALIAS("IMC_RETRY.CH1", UCP_EVENT_32H_02H) \ -__PMC_EV_ALIAS("IMC_RETRY.CH2", UCP_EVENT_32H_04H) \ -__PMC_EV_ALIAS("IMC_RETRY.ANY", UCP_EVENT_32H_07H) \ -__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.IOH", UCP_EVENT_33H_01H) \ -__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.REMOTE", UCP_EVENT_33H_02H) \ -__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.LOCAL", UCP_EVENT_33H_04H) \ -__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.ANY", UCP_EVENT_33H_07H) \ -__PMC_EV_ALIAS("QHL_SLEEPS.IOH_ORDER", UCP_EVENT_34H_01H) \ -__PMC_EV_ALIAS("QHL_SLEEPS.REMOTE_ORDER", UCP_EVENT_34H_02H) \ -__PMC_EV_ALIAS("QHL_SLEEPS.LOCAL_ORDER", UCP_EVENT_34H_04H) \ -__PMC_EV_ALIAS("QHL_SLEEPS.IOH_CONFLICT", UCP_EVENT_34H_08H) \ -__PMC_EV_ALIAS("QHL_SLEEPS.REMOTE_CONFLICT", UCP_EVENT_34H_10H) \ -__PMC_EV_ALIAS("QHL_SLEEPS.LOCAL_CONFLICT", UCP_EVENT_34H_20H) \ -__PMC_EV_ALIAS("ADDR_OPCODE_MATCH.IOH", UCP_EVENT_35H_01H) \ -__PMC_EV_ALIAS("ADDR_OPCODE_MATCH.REMOTE", UCP_EVENT_35H_02H) \ -__PMC_EV_ALIAS("ADDR_OPCODE_MATCH.LOCAL", UCP_EVENT_35H_04H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0", \ - UCP_EVENT_40H_01H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0", \ - UCP_EVENT_40H_02H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0", \ - UCP_EVENT_40H_04H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1", \ - UCP_EVENT_40H_08H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1", \ - UCP_EVENT_40H_10H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1", \ - UCP_EVENT_40H_20H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_0", UCP_EVENT_40H_07H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_1", UCP_EVENT_40H_38H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0", \ - UCP_EVENT_41H_01H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0", \ - UCP_EVENT_41H_02H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0", \ - UCP_EVENT_41H_04H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1", \ - UCP_EVENT_41H_08H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1", \ - UCP_EVENT_41H_10H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1", \ - UCP_EVENT_41H_20H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_0", UCP_EVENT_41H_07H) \ -__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_1", UCP_EVENT_41H_38H) \ -__PMC_EV_ALIAS("QPI_TX_HEADER.FULL.LINK_0", UCP_EVENT_42H_01H) \ -__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_0", UCP_EVENT_42H_02H) \ -__PMC_EV_ALIAS("QPI_TX_HEADER.FULL.LINK_1", UCP_EVENT_42H_04H) \ -__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_1", UCP_EVENT_42H_08H) \ -__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0", UCP_EVENT_43H_01H) \ -__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1", UCP_EVENT_43H_02H) \ -__PMC_EV_ALIAS("DRAM_OPEN.CH0", UCP_EVENT_60H_01H) \ -__PMC_EV_ALIAS("DRAM_OPEN.CH1", UCP_EVENT_60H_02H) \ -__PMC_EV_ALIAS("DRAM_OPEN.CH2", UCP_EVENT_60H_04H) \ -__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH0", UCP_EVENT_61H_01H) \ -__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH1", UCP_EVENT_61H_02H) \ -__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH2", UCP_EVENT_61H_04H) \ -__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH0", UCP_EVENT_62H_01H) \ -__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH1", UCP_EVENT_62H_02H) \ -__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH2", UCP_EVENT_62H_04H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.CH0", UCP_EVENT_63H_01H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH0", UCP_EVENT_63H_02H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.CH1", UCP_EVENT_63H_04H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH1", UCP_EVENT_63H_08H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.CH2", UCP_EVENT_63H_10H) \ -__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH2", UCP_EVENT_63H_20H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH0", UCP_EVENT_64H_01H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH0", UCP_EVENT_64H_02H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH1", UCP_EVENT_64H_04H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH1", UCP_EVENT_64H_08H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH2", UCP_EVENT_64H_10H) \ -__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH2", UCP_EVENT_64H_20H) \ -__PMC_EV_ALIAS("DRAM_REFRESH.CH0", UCP_EVENT_65H_01H) \ -__PMC_EV_ALIAS("DRAM_REFRESH.CH1", UCP_EVENT_65H_02H) \ -__PMC_EV_ALIAS("DRAM_REFRESH.CH2", UCP_EVENT_65H_04H) \ -__PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H) \ -__PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H) \ -__PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H) \ -__PMC_EV_ALIAS("DRAM_THERMAL_THROTTLED", UCP_EVENT_67H_01H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_0", UCP_EVENT_80H_01H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_1", UCP_EVENT_80H_02H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_2", UCP_EVENT_80H_04H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_3", UCP_EVENT_80H_08H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_0", UCP_EVENT_81H_01H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_1", UCP_EVENT_81H_02H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_2", UCP_EVENT_81H_04H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_3", UCP_EVENT_81H_08H) \ -__PMC_EV_ALIAS("PROCHOT_ASSERTION", UCP_EVENT_82H_01H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_0", UCP_EVENT_83H_01H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_1", UCP_EVENT_83H_02H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_2", UCP_EVENT_83H_04H) \ -__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_3", UCP_EVENT_83H_08H) \ -__PMC_EV_ALIAS("TURBO_MODE.CORE_0", UCP_EVENT_84H_01H) \ -__PMC_EV_ALIAS("TURBO_MODE.CORE_1", UCP_EVENT_84H_02H) \ -__PMC_EV_ALIAS("TURBO_MODE.CORE_2", UCP_EVENT_84H_04H) \ -__PMC_EV_ALIAS("TURBO_MODE.CORE_3", UCP_EVENT_84H_08H) \ -__PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_ENABLE", UCP_EVENT_85H_02H) \ -__PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_DISABLE", UCP_EVENT_86H_01H) - - -#define __PMC_EV_ALIAS_SANDYBRIDGEUC() \ -__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPIHITI", UCP_EVENT_22H_01H) \ -__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPIHITFSE", UCP_EVENT_22H_02H) \ -__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPSHITFSE", UCP_EVENT_22H_04H) \ -__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPSFWDM", UCP_EVENT_22H_08H) \ -__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.AND_EXTERNAL", UCP_EVENT_22H_20H) \ -__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.AND_XCORE", UCP_EVENT_22H_40H) \ -__PMC_EV_ALIAS("CB0_XSNP_RESPONSE_AND_XCORE2", UCP_EVENT_22H_80H) \ -__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.M", UCP_EVENT_34H_01H) \ -__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.E", UCP_EVENT_34H_02H) \ -__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.S", UCP_EVENT_34H_04H) \ -__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.I", UCP_EVENT_34H_08H) \ -__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_READ", UCP_EVENT_34H_10H) \ -__PMC_EV_ALIAS("CB0_CACHE_LOOKUP_AND_READ2", UCP_EVENT_34H_20H) \ -__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_EXTSNP", UCP_EVENT_34H_40H) \ -__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_ANY", UCP_EVENT_34H_80H) \ -__PMC_EV_ALIAS("IMPH_CB0_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H) \ -__PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.ALL", UCP_EVENT_81H_01H) \ -__PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H) \ -__PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H) \ -__PMC_EV_ALIAS("IMPH_C0H_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H) \ -__PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_84H_01H) +#define __PMC_EV_UCP() \ + __PMC_EV(UCP, EVENT_0CH_04H_E) \ + __PMC_EV(UCP, EVENT_0CH_04H_F) \ + __PMC_EV(UCP, EVENT_0CH_04H_M) \ + __PMC_EV(UCP, EVENT_0CH_04H_S) \ + __PMC_EV(UCP, EVENT_0CH_08H_E) \ + __PMC_EV(UCP, EVENT_0CH_08H_F) \ + __PMC_EV(UCP, EVENT_0CH_08H_M) \ + __PMC_EV(UCP, EVENT_0CH_08H_S) \ /* * Intel XScale events from: * * Intel XScale Core Developer's Manual * January, 2004, #27347302 * * 3rd Generation Intel XScale Microarchitecture * Developer's Manual * May 2007, #31628302 * * First 14 events are for 1st and 2nd Generation Intel XScale cores. The * remaining are available only on 3rd Generation Intel XScale cores. */ #define __PMC_EV_XSCALE() \ __PMC_EV(XSCALE, IC_FETCH) \ __PMC_EV(XSCALE, IC_MISS) \ __PMC_EV(XSCALE, DATA_DEPENDENCY_STALLED) \ __PMC_EV(XSCALE, ITLB_MISS) \ __PMC_EV(XSCALE, DTLB_MISS) \ __PMC_EV(XSCALE, BRANCH_RETIRED) \ __PMC_EV(XSCALE, BRANCH_MISPRED) \ __PMC_EV(XSCALE, INSTR_RETIRED) \ __PMC_EV(XSCALE, DC_FULL_CYCLE) \ __PMC_EV(XSCALE, DC_FULL_CONTIG) \ __PMC_EV(XSCALE, DC_ACCESS) \ __PMC_EV(XSCALE, DC_MISS) \ __PMC_EV(XSCALE, DC_WRITEBACK) \ __PMC_EV(XSCALE, PC_CHANGE) \ __PMC_EV(XSCALE, BRANCH_RETIRED_ALL) \ __PMC_EV(XSCALE, INSTR_CYCLE) \ __PMC_EV(XSCALE, CP_STALL) \ __PMC_EV(XSCALE, PC_CHANGE_ALL) \ __PMC_EV(XSCALE, PIPELINE_FLUSH) \ __PMC_EV(XSCALE, BACKEND_STALL) \ __PMC_EV(XSCALE, MULTIPLIER_USE) \ __PMC_EV(XSCALE, MULTIPLIER_STALLED) \ __PMC_EV(XSCALE, DATA_CACHE_STALLED) \ __PMC_EV(XSCALE, L2_CACHE_REQ) \ __PMC_EV(XSCALE, L2_CACHE_MISS) \ __PMC_EV(XSCALE, ADDRESS_BUS_TRANS) \ __PMC_EV(XSCALE, SELF_ADDRESS_BUS_TRANS) \ __PMC_EV(XSCALE, DATA_BUS_TRANS) #define PMC_EV_XSCALE_FIRST PMC_EV_XSCALE_IC_FETCH #define PMC_EV_XSCALE_LAST PMC_EV_XSCALE_DATA_BUS_TRANS /* * ARMv7 Events */ #define __PMC_EV_ARMV7() \ __PMC_EV(ARMV7, EVENT_00H) \ __PMC_EV(ARMV7, EVENT_01H) \ __PMC_EV(ARMV7, EVENT_02H) \ __PMC_EV(ARMV7, EVENT_03H) \ __PMC_EV(ARMV7, EVENT_04H) \ __PMC_EV(ARMV7, EVENT_05H) \ __PMC_EV(ARMV7, EVENT_06H) \ __PMC_EV(ARMV7, EVENT_07H) \ __PMC_EV(ARMV7, EVENT_08H) \ __PMC_EV(ARMV7, EVENT_09H) \ __PMC_EV(ARMV7, EVENT_0AH) \ __PMC_EV(ARMV7, EVENT_0BH) \ __PMC_EV(ARMV7, EVENT_0CH) \ __PMC_EV(ARMV7, EVENT_0DH) \ __PMC_EV(ARMV7, EVENT_0EH) \ __PMC_EV(ARMV7, EVENT_0FH) \ __PMC_EV(ARMV7, EVENT_10H) \ __PMC_EV(ARMV7, EVENT_11H) \ __PMC_EV(ARMV7, EVENT_12H) \ __PMC_EV(ARMV7, EVENT_13H) \ __PMC_EV(ARMV7, EVENT_14H) \ __PMC_EV(ARMV7, EVENT_15H) \ __PMC_EV(ARMV7, EVENT_16H) \ __PMC_EV(ARMV7, EVENT_17H) \ __PMC_EV(ARMV7, EVENT_18H) \ __PMC_EV(ARMV7, EVENT_19H) \ __PMC_EV(ARMV7, EVENT_1AH) \ __PMC_EV(ARMV7, EVENT_1BH) \ __PMC_EV(ARMV7, EVENT_1CH) \ __PMC_EV(ARMV7, EVENT_1DH) \ __PMC_EV(ARMV7, EVENT_1EH) \ __PMC_EV(ARMV7, EVENT_1FH) \ __PMC_EV(ARMV7, EVENT_20H) \ __PMC_EV(ARMV7, EVENT_21H) \ __PMC_EV(ARMV7, EVENT_22H) \ __PMC_EV(ARMV7, EVENT_23H) \ __PMC_EV(ARMV7, EVENT_24H) \ __PMC_EV(ARMV7, EVENT_25H) \ __PMC_EV(ARMV7, EVENT_26H) \ __PMC_EV(ARMV7, EVENT_27H) \ __PMC_EV(ARMV7, EVENT_28H) \ __PMC_EV(ARMV7, EVENT_29H) \ __PMC_EV(ARMV7, EVENT_2AH) \ __PMC_EV(ARMV7, EVENT_2BH) \ __PMC_EV(ARMV7, EVENT_2CH) \ __PMC_EV(ARMV7, EVENT_2DH) \ __PMC_EV(ARMV7, EVENT_2EH) \ __PMC_EV(ARMV7, EVENT_2FH) \ __PMC_EV(ARMV7, EVENT_30H) \ __PMC_EV(ARMV7, EVENT_31H) \ __PMC_EV(ARMV7, EVENT_32H) \ __PMC_EV(ARMV7, EVENT_33H) \ __PMC_EV(ARMV7, EVENT_34H) \ __PMC_EV(ARMV7, EVENT_35H) \ __PMC_EV(ARMV7, EVENT_36H) \ __PMC_EV(ARMV7, EVENT_37H) \ __PMC_EV(ARMV7, EVENT_38H) \ __PMC_EV(ARMV7, EVENT_39H) \ __PMC_EV(ARMV7, EVENT_3AH) \ __PMC_EV(ARMV7, EVENT_3BH) \ __PMC_EV(ARMV7, EVENT_3CH) \ __PMC_EV(ARMV7, EVENT_3DH) \ __PMC_EV(ARMV7, EVENT_3EH) \ __PMC_EV(ARMV7, EVENT_3FH) \ __PMC_EV(ARMV7, EVENT_40H) \ __PMC_EV(ARMV7, EVENT_41H) \ __PMC_EV(ARMV7, EVENT_42H) \ __PMC_EV(ARMV7, EVENT_43H) \ __PMC_EV(ARMV7, EVENT_44H) \ __PMC_EV(ARMV7, EVENT_45H) \ __PMC_EV(ARMV7, EVENT_46H) \ __PMC_EV(ARMV7, EVENT_47H) \ __PMC_EV(ARMV7, EVENT_48H) \ __PMC_EV(ARMV7, EVENT_49H) \ __PMC_EV(ARMV7, EVENT_4AH) \ __PMC_EV(ARMV7, EVENT_4BH) \ __PMC_EV(ARMV7, EVENT_4CH) \ __PMC_EV(ARMV7, EVENT_4DH) \ __PMC_EV(ARMV7, EVENT_4EH) \ __PMC_EV(ARMV7, EVENT_4FH) \ __PMC_EV(ARMV7, EVENT_50H) \ __PMC_EV(ARMV7, EVENT_51H) \ __PMC_EV(ARMV7, EVENT_52H) \ __PMC_EV(ARMV7, EVENT_53H) \ __PMC_EV(ARMV7, EVENT_54H) \ __PMC_EV(ARMV7, EVENT_55H) \ __PMC_EV(ARMV7, EVENT_56H) \ __PMC_EV(ARMV7, EVENT_57H) \ __PMC_EV(ARMV7, EVENT_58H) \ __PMC_EV(ARMV7, EVENT_59H) \ __PMC_EV(ARMV7, EVENT_5AH) \ __PMC_EV(ARMV7, EVENT_5BH) \ __PMC_EV(ARMV7, EVENT_5CH) \ __PMC_EV(ARMV7, EVENT_5DH) \ __PMC_EV(ARMV7, EVENT_5EH) \ __PMC_EV(ARMV7, EVENT_5FH) \ __PMC_EV(ARMV7, EVENT_60H) \ __PMC_EV(ARMV7, EVENT_61H) \ __PMC_EV(ARMV7, EVENT_62H) \ __PMC_EV(ARMV7, EVENT_63H) \ __PMC_EV(ARMV7, EVENT_64H) \ __PMC_EV(ARMV7, EVENT_65H) \ __PMC_EV(ARMV7, EVENT_66H) \ __PMC_EV(ARMV7, EVENT_67H) \ __PMC_EV(ARMV7, EVENT_68H) \ __PMC_EV(ARMV7, EVENT_69H) \ __PMC_EV(ARMV7, EVENT_6AH) \ __PMC_EV(ARMV7, EVENT_6BH) \ __PMC_EV(ARMV7, EVENT_6CH) \ __PMC_EV(ARMV7, EVENT_6DH) \ __PMC_EV(ARMV7, EVENT_6EH) \ __PMC_EV(ARMV7, EVENT_6FH) \ __PMC_EV(ARMV7, EVENT_70H) \ __PMC_EV(ARMV7, EVENT_71H) \ __PMC_EV(ARMV7, EVENT_72H) \ __PMC_EV(ARMV7, EVENT_73H) \ __PMC_EV(ARMV7, EVENT_74H) \ __PMC_EV(ARMV7, EVENT_75H) \ __PMC_EV(ARMV7, EVENT_76H) \ __PMC_EV(ARMV7, EVENT_77H) \ __PMC_EV(ARMV7, EVENT_78H) \ __PMC_EV(ARMV7, EVENT_79H) \ __PMC_EV(ARMV7, EVENT_7AH) \ __PMC_EV(ARMV7, EVENT_7BH) \ __PMC_EV(ARMV7, EVENT_7CH) \ __PMC_EV(ARMV7, EVENT_7DH) \ __PMC_EV(ARMV7, EVENT_7EH) \ __PMC_EV(ARMV7, EVENT_7FH) \ __PMC_EV(ARMV7, EVENT_80H) \ __PMC_EV(ARMV7, EVENT_81H) \ __PMC_EV(ARMV7, EVENT_82H) \ __PMC_EV(ARMV7, EVENT_83H) \ __PMC_EV(ARMV7, EVENT_84H) \ __PMC_EV(ARMV7, EVENT_85H) \ __PMC_EV(ARMV7, EVENT_86H) \ __PMC_EV(ARMV7, EVENT_87H) \ __PMC_EV(ARMV7, EVENT_88H) \ __PMC_EV(ARMV7, EVENT_89H) \ __PMC_EV(ARMV7, EVENT_8AH) \ __PMC_EV(ARMV7, EVENT_8BH) \ __PMC_EV(ARMV7, EVENT_8CH) \ __PMC_EV(ARMV7, EVENT_8DH) \ __PMC_EV(ARMV7, EVENT_8EH) \ __PMC_EV(ARMV7, EVENT_8FH) \ __PMC_EV(ARMV7, EVENT_90H) \ __PMC_EV(ARMV7, EVENT_91H) \ __PMC_EV(ARMV7, EVENT_92H) \ __PMC_EV(ARMV7, EVENT_93H) \ __PMC_EV(ARMV7, EVENT_94H) \ __PMC_EV(ARMV7, EVENT_95H) \ __PMC_EV(ARMV7, EVENT_96H) \ __PMC_EV(ARMV7, EVENT_97H) \ __PMC_EV(ARMV7, EVENT_98H) \ __PMC_EV(ARMV7, EVENT_99H) \ __PMC_EV(ARMV7, EVENT_9AH) \ __PMC_EV(ARMV7, EVENT_9BH) \ __PMC_EV(ARMV7, EVENT_9CH) \ __PMC_EV(ARMV7, EVENT_9DH) \ __PMC_EV(ARMV7, EVENT_9EH) \ __PMC_EV(ARMV7, EVENT_9FH) \ __PMC_EV(ARMV7, EVENT_A0H) \ __PMC_EV(ARMV7, EVENT_A1H) \ __PMC_EV(ARMV7, EVENT_A2H) \ __PMC_EV(ARMV7, EVENT_A3H) \ __PMC_EV(ARMV7, EVENT_A4H) \ __PMC_EV(ARMV7, EVENT_A5H) \ __PMC_EV(ARMV7, EVENT_A6H) \ __PMC_EV(ARMV7, EVENT_A7H) \ __PMC_EV(ARMV7, EVENT_A8H) \ __PMC_EV(ARMV7, EVENT_A9H) \ __PMC_EV(ARMV7, EVENT_AAH) \ __PMC_EV(ARMV7, EVENT_ABH) \ __PMC_EV(ARMV7, EVENT_ACH) \ __PMC_EV(ARMV7, EVENT_ADH) \ __PMC_EV(ARMV7, EVENT_AEH) \ __PMC_EV(ARMV7, EVENT_AFH) \ __PMC_EV(ARMV7, EVENT_B0H) \ __PMC_EV(ARMV7, EVENT_B1H) \ __PMC_EV(ARMV7, EVENT_B2H) \ __PMC_EV(ARMV7, EVENT_B3H) \ __PMC_EV(ARMV7, EVENT_B4H) \ __PMC_EV(ARMV7, EVENT_B5H) \ __PMC_EV(ARMV7, EVENT_B6H) \ __PMC_EV(ARMV7, EVENT_B7H) \ __PMC_EV(ARMV7, EVENT_B8H) \ __PMC_EV(ARMV7, EVENT_B9H) \ __PMC_EV(ARMV7, EVENT_BAH) \ __PMC_EV(ARMV7, EVENT_BBH) \ __PMC_EV(ARMV7, EVENT_BCH) \ __PMC_EV(ARMV7, EVENT_BDH) \ __PMC_EV(ARMV7, EVENT_BEH) \ __PMC_EV(ARMV7, EVENT_BFH) \ __PMC_EV(ARMV7, EVENT_C0H) \ __PMC_EV(ARMV7, EVENT_C1H) \ __PMC_EV(ARMV7, EVENT_C2H) \ __PMC_EV(ARMV7, EVENT_C3H) \ __PMC_EV(ARMV7, EVENT_C4H) \ __PMC_EV(ARMV7, EVENT_C5H) \ __PMC_EV(ARMV7, EVENT_C6H) \ __PMC_EV(ARMV7, EVENT_C7H) \ __PMC_EV(ARMV7, EVENT_C8H) \ __PMC_EV(ARMV7, EVENT_C9H) \ __PMC_EV(ARMV7, EVENT_CAH) \ __PMC_EV(ARMV7, EVENT_CBH) \ __PMC_EV(ARMV7, EVENT_CCH) \ __PMC_EV(ARMV7, EVENT_CDH) \ __PMC_EV(ARMV7, EVENT_CEH) \ __PMC_EV(ARMV7, EVENT_CFH) \ __PMC_EV(ARMV7, EVENT_D0H) \ __PMC_EV(ARMV7, EVENT_D1H) \ __PMC_EV(ARMV7, EVENT_D2H) \ __PMC_EV(ARMV7, EVENT_D3H) \ __PMC_EV(ARMV7, EVENT_D4H) \ __PMC_EV(ARMV7, EVENT_D5H) \ __PMC_EV(ARMV7, EVENT_D6H) \ __PMC_EV(ARMV7, EVENT_D7H) \ __PMC_EV(ARMV7, EVENT_D8H) \ __PMC_EV(ARMV7, EVENT_D9H) \ __PMC_EV(ARMV7, EVENT_DAH) \ __PMC_EV(ARMV7, EVENT_DBH) \ __PMC_EV(ARMV7, EVENT_DCH) \ __PMC_EV(ARMV7, EVENT_DDH) \ __PMC_EV(ARMV7, EVENT_DEH) \ __PMC_EV(ARMV7, EVENT_DFH) \ __PMC_EV(ARMV7, EVENT_E0H) \ __PMC_EV(ARMV7, EVENT_E1H) \ __PMC_EV(ARMV7, EVENT_E2H) \ __PMC_EV(ARMV7, EVENT_E3H) \ __PMC_EV(ARMV7, EVENT_E4H) \ __PMC_EV(ARMV7, EVENT_E5H) \ __PMC_EV(ARMV7, EVENT_E6H) \ __PMC_EV(ARMV7, EVENT_E7H) \ __PMC_EV(ARMV7, EVENT_E8H) \ __PMC_EV(ARMV7, EVENT_E9H) \ __PMC_EV(ARMV7, EVENT_EAH) \ __PMC_EV(ARMV7, EVENT_EBH) \ __PMC_EV(ARMV7, EVENT_ECH) \ __PMC_EV(ARMV7, EVENT_EDH) \ __PMC_EV(ARMV7, EVENT_EEH) \ __PMC_EV(ARMV7, EVENT_EFH) \ __PMC_EV(ARMV7, EVENT_F0H) \ __PMC_EV(ARMV7, EVENT_F1H) \ __PMC_EV(ARMV7, EVENT_F2H) \ __PMC_EV(ARMV7, EVENT_F3H) \ __PMC_EV(ARMV7, EVENT_F4H) \ __PMC_EV(ARMV7, EVENT_F5H) \ __PMC_EV(ARMV7, EVENT_F6H) \ __PMC_EV(ARMV7, EVENT_F7H) \ __PMC_EV(ARMV7, EVENT_F8H) \ __PMC_EV(ARMV7, EVENT_F9H) \ __PMC_EV(ARMV7, EVENT_FAH) \ __PMC_EV(ARMV7, EVENT_FBH) \ __PMC_EV(ARMV7, EVENT_FCH) \ __PMC_EV(ARMV7, EVENT_FDH) \ __PMC_EV(ARMV7, EVENT_FEH) \ __PMC_EV(ARMV7, EVENT_FFH) #define PMC_EV_ARMV7_FIRST PMC_EV_ARMV7_EVENT_00H #define PMC_EV_ARMV7_LAST PMC_EV_ARMV7_EVENT_FFH #define __PMC_EV_ALIAS_ARMV7_COMMON() \ __PMC_EV_ALIAS("PMNC_SW_INCR", ARMV7_EVENT_00H) \ __PMC_EV_ALIAS("L1_ICACHE_REFILL", ARMV7_EVENT_01H) \ __PMC_EV_ALIAS("ITLB_REFILL", ARMV7_EVENT_02H) \ __PMC_EV_ALIAS("L1_DCACHE_REFILL", ARMV7_EVENT_03H) \ __PMC_EV_ALIAS("L1_DCACHE_ACCESS", ARMV7_EVENT_04H) \ __PMC_EV_ALIAS("DTLB_REFILL", ARMV7_EVENT_05H) \ __PMC_EV_ALIAS("MEM_READ", ARMV7_EVENT_06H) \ __PMC_EV_ALIAS("MEM_WRITE", ARMV7_EVENT_07H) \ __PMC_EV_ALIAS("EXC_TAKEN", ARMV7_EVENT_09H) \ __PMC_EV_ALIAS("EXC_EXECUTED", ARMV7_EVENT_0AH) \ __PMC_EV_ALIAS("CID_WRITE", ARMV7_EVENT_0BH) \ __PMC_EV_ALIAS("PC_WRITE", ARMV7_EVENT_0CH) \ __PMC_EV_ALIAS("PC_IMM_BRANCH", ARMV7_EVENT_0DH) \ __PMC_EV_ALIAS("MEM_UNALIGNED_ACCESS", ARMV7_EVENT_0FH) \ __PMC_EV_ALIAS("PC_BRANCH_MIS_PRED", ARMV7_EVENT_10H) \ __PMC_EV_ALIAS("CLOCK_CYCLES", ARMV7_EVENT_11H) \ __PMC_EV_ALIAS("PC_BRANCH_PRED", ARMV7_EVENT_12H) #define __PMC_EV_ALIAS_ARMV7_COMMON_A8() \ __PMC_EV_ALIAS_ARMV7_COMMON() \ __PMC_EV_ALIAS("INSTR_EXECUTED", ARMV7_EVENT_08H) \ __PMC_EV_ALIAS("PC_PROC_RETURN", ARMV7_EVENT_0EH) \ __PMC_EV_ALIAS("MEM_ACCESS", ARMV7_EVENT_13H) \ __PMC_EV_ALIAS("L1_ICACHE_ACCESS", ARMV7_EVENT_14H) \ __PMC_EV_ALIAS("L1_DCACHE_WB", ARMV7_EVENT_15H) \ __PMC_EV_ALIAS("L2_CACHE_ACCESS", ARMV7_EVENT_16H) \ __PMC_EV_ALIAS("L2_CACHE_REFILL", ARMV7_EVENT_17H) \ __PMC_EV_ALIAS("L2_CACHE_WB", ARMV7_EVENT_18H) \ __PMC_EV_ALIAS("BUS_ACCESS", ARMV7_EVENT_19H) \ __PMC_EV_ALIAS("MEM_ERROR", ARMV7_EVENT_1AH) \ __PMC_EV_ALIAS("INSTR_SPEC", ARMV7_EVENT_1BH) \ __PMC_EV_ALIAS("TTBR_WRITE", ARMV7_EVENT_1CH) \ __PMC_EV_ALIAS("BUS_CYCLES", ARMV7_EVENT_1DH) \ __PMC_EV_ALIAS("CPU_CYCLES", ARMV7_EVENT_FFH) #define __PMC_EV_ALIAS_ARMV7_CORTEX_A8() \ __PMC_EV_ALIAS_ARMV7_COMMON_A8() \ __PMC_EV_ALIAS("WRITE_BUF_FULL", ARMV7_EVENT_40H) \ __PMC_EV_ALIAS("L2_STORE_MERGED", ARMV7_EVENT_41H) \ __PMC_EV_ALIAS("L2_STORE_BUFFERABLE", ARMV7_EVENT_42H) \ __PMC_EV_ALIAS("L2_ACCESS", ARMV7_EVENT_43H) \ __PMC_EV_ALIAS("L2_CACHE_MISS", ARMV7_EVENT_44H) \ __PMC_EV_ALIAS("AXI_READ", ARMV7_EVENT_45H) \ __PMC_EV_ALIAS("AXI_WRITE", ARMV7_EVENT_46H) \ __PMC_EV_ALIAS("MEM_REPLAY_EVT", ARMV7_EVENT_47H) \ __PMC_EV_ALIAS("MEM_UNALIGNED_ACCESS_REPLAY", ARMV7_EVENT_48H) \ __PMC_EV_ALIAS("L1_DCACHE_HASH_MISS", ARMV7_EVENT_49H) \ __PMC_EV_ALIAS("L1_ICACHE_HASH_MISS", ARMV7_EVENT_4AH) \ __PMC_EV_ALIAS("L1_CACHE_PAGECOL_ALIAS", ARMV7_EVENT_4BH) \ __PMC_EV_ALIAS("L1_DCACHE_NEON_ACCESS", ARMV7_EVENT_4CH) \ __PMC_EV_ALIAS("L1_DCACHE_NEON_CACHEABLE", ARMV7_EVENT_4DH) \ __PMC_EV_ALIAS("L2_CACHE_NEON_MEM_ACCESS", ARMV7_EVENT_4EH) \ __PMC_EV_ALIAS("L2_CACHE_NEON_HIT", ARMV7_EVENT_4FH) \ __PMC_EV_ALIAS("L1_CACHE_ACCESS_NOCP15", ARMV7_EVENT_50H) \ __PMC_EV_ALIAS("RET_STACK_MISPREDICT", ARMV7_EVENT_51H) \ __PMC_EV_ALIAS("BRANCH_DIR_MISPREDICT", ARMV7_EVENT_52H) \ __PMC_EV_ALIAS("PRED_BRANCH_PRED_TAKEN", ARMV7_EVENT_53H) \ __PMC_EV_ALIAS("PRED_BRANCH_EXEC_TAKEN", ARMV7_EVENT_54H) \ __PMC_EV_ALIAS("OPS_ISSUED", ARMV7_EVENT_55H) \ __PMC_EV_ALIAS("CYCLES_NO_INSTRUCTION", ARMV7_EVENT_56H) \ __PMC_EV_ALIAS("INSTRUCTIONS_ISSUED_CYCLE", ARMV7_EVENT_57H) \ __PMC_EV_ALIAS("CYCLES_STALLED_NEON_MRC", ARMV7_EVENT_58H) \ __PMC_EV_ALIAS("CYCLES_STALLED_NEON_FULLQ", ARMV7_EVENT_59H) \ __PMC_EV_ALIAS("CYCLES_NONIDLE_NEON_INT", ARMV7_EVENT_5AH) \ __PMC_EV_ALIAS("PMUEXTIN0_EVT", ARMV7_EVENT_70H) \ __PMC_EV_ALIAS("PMUEXTIN1_EVT", ARMV7_EVENT_71H) \ __PMC_EV_ALIAS("PMUEXTIN_EVT", ARMV7_EVENT_72H) #define PMC_EV_ARMV7_CORTEX_A8_FIRST PMC_EV_ARMV7_PMNC_SW_INCR #define PMC_EV_ARMV7_CORTEX_A8_LAST PMC_EV_ARMV7_PMUEXTIN_EVT #define __PMC_EV_ALIAS_ARMV7_CORTEX_A9() \ __PMC_EV_ALIAS_ARMV7_COMMON() \ __PMC_EV_ALIAS("JAVA_BYTECODE", ARMV7_EVENT_40H) \ __PMC_EV_ALIAS("SOFTWARE_JAVA_BYTECODE", ARMV7_EVENT_41H) \ __PMC_EV_ALIAS("JAZELLE_BACKWARD_BRANCH", ARMV7_EVENT_42H) \ __PMC_EV_ALIAS("COHERENT_LINEFILL_MISSC", ARMV7_EVENT_50H) \ __PMC_EV_ALIAS("COHERENT_LINEFILL_HITC", ARMV7_EVENT_51H) \ __PMC_EV_ALIAS("INSTR_CACHE_DEPENDENT_STALL", ARMV7_EVENT_60H) \ __PMC_EV_ALIAS("DATA_CACHE_DEPENDENT_STALL", ARMV7_EVENT_61H) \ __PMC_EV_ALIAS("MAIN_TLB_MISS_STALL", ARMV7_EVENT_62H) \ __PMC_EV_ALIAS("STREX_PASSED", ARMV7_EVENT_63H) \ __PMC_EV_ALIAS("STREX_FAILED", ARMV7_EVENT_64H) \ __PMC_EV_ALIAS("DATA_EVICTION", ARMV7_EVENT_65H) \ __PMC_EV_ALIAS("ISSUE_DNOT_DISPATCH_ANY_INSTR", ARMV7_EVENT_66H) \ __PMC_EV_ALIAS("ISSUE_IS_EMPTY", ARMV7_EVENT_67H) \ __PMC_EV_ALIAS("INSTR_RENAMED", ARMV7_EVENT_68H) \ __PMC_EV_ALIAS("PREDICTABLE_FUNCTION_RETURN", ARMV7_EVENT_6EH) \ __PMC_EV_ALIAS("MAIN_EXECUTION_UNIT_PIPE", ARMV7_EVENT_70H) \ __PMC_EV_ALIAS("SECOND_EXECUTION_UNIT_PIPE", ARMV7_EVENT_71H) \ __PMC_EV_ALIAS("LOAD_STORE_PIPE", ARMV7_EVENT_72H) \ __PMC_EV_ALIAS("FLOATING_POINT_INSTR_RENAMED", ARMV7_EVENT_73H) \ __PMC_EV_ALIAS("NEON_INSTRS_RENAMED", ARMV7_EVENT_74H) \ __PMC_EV_ALIAS("PLD_STALL", ARMV7_EVENT_80H) \ __PMC_EV_ALIAS("WRITE_STALL", ARMV7_EVENT_81H) \ __PMC_EV_ALIAS("INSTR_MAIN_TLB_MISS_STALL", ARMV7_EVENT_82H) \ __PMC_EV_ALIAS("DATA_MAIN_TLB_MISS_STALL", ARMV7_EVENT_83H) \ __PMC_EV_ALIAS("INSTR_MICRO_TLB_MISS_STALL", ARMV7_EVENT_84H) \ __PMC_EV_ALIAS("DATA_MICRO_TLB_MISS_STALL", ARMV7_EVENT_85H) \ __PMC_EV_ALIAS("DMB_STALL", ARMV7_EVENT_86H) \ __PMC_EV_ALIAS("INTEGER_CORE_CLOCK_ENABLED", ARMV7_EVENT_8AH) \ __PMC_EV_ALIAS("DATA_ENGINE_CLOCK_ENABLED", ARMV7_EVENT_8BH) \ __PMC_EV_ALIAS("ISB", ARMV7_EVENT_90H) \ __PMC_EV_ALIAS("DSB", ARMV7_EVENT_91H) \ __PMC_EV_ALIAS("DMB", ARMV7_EVENT_92H) \ __PMC_EV_ALIAS("EXTERNAL_INTERRUPT", ARMV7_EVENT_93H) \ __PMC_EV_ALIAS("PLE_CACHE_LINE_REQ_COMPLETED", ARMV7_EVENT_A0H) \ __PMC_EV_ALIAS("PLE_CACHE_LINE_REQ_SKIPPED", ARMV7_EVENT_A1H) \ __PMC_EV_ALIAS("PLE_FIFO_FLUSH", ARMV7_EVENT_A2H) \ __PMC_EV_ALIAS("PLE_REQUEST_COMPLETED", ARMV7_EVENT_A3H) \ __PMC_EV_ALIAS("PLE_FIFO_OVERFLOW", ARMV7_EVENT_A4H) \ __PMC_EV_ALIAS("PLE_REQUEST_PROGRAMMED", ARMV7_EVENT_A5H) /* * ARMv8 Events */ #define __PMC_EV_ARMV8() \ __PMC_EV(ARMV8, EVENT_00H) \ __PMC_EV(ARMV8, EVENT_01H) \ __PMC_EV(ARMV8, EVENT_02H) \ __PMC_EV(ARMV8, EVENT_03H) \ __PMC_EV(ARMV8, EVENT_04H) \ __PMC_EV(ARMV8, EVENT_05H) \ __PMC_EV(ARMV8, EVENT_06H) \ __PMC_EV(ARMV8, EVENT_07H) \ __PMC_EV(ARMV8, EVENT_08H) \ __PMC_EV(ARMV8, EVENT_09H) \ __PMC_EV(ARMV8, EVENT_0AH) \ __PMC_EV(ARMV8, EVENT_0BH) \ __PMC_EV(ARMV8, EVENT_0CH) \ __PMC_EV(ARMV8, EVENT_0DH) \ __PMC_EV(ARMV8, EVENT_0EH) \ __PMC_EV(ARMV8, EVENT_0FH) \ __PMC_EV(ARMV8, EVENT_10H) \ __PMC_EV(ARMV8, EVENT_11H) \ __PMC_EV(ARMV8, EVENT_12H) \ __PMC_EV(ARMV8, EVENT_13H) \ __PMC_EV(ARMV8, EVENT_14H) \ __PMC_EV(ARMV8, EVENT_15H) \ __PMC_EV(ARMV8, EVENT_16H) \ __PMC_EV(ARMV8, EVENT_17H) \ __PMC_EV(ARMV8, EVENT_18H) \ __PMC_EV(ARMV8, EVENT_19H) \ __PMC_EV(ARMV8, EVENT_1AH) \ __PMC_EV(ARMV8, EVENT_1BH) \ __PMC_EV(ARMV8, EVENT_1CH) \ __PMC_EV(ARMV8, EVENT_1DH) \ __PMC_EV(ARMV8, EVENT_1EH) \ __PMC_EV(ARMV8, EVENT_1FH) \ __PMC_EV(ARMV8, EVENT_20H) \ __PMC_EV(ARMV8, EVENT_21H) \ __PMC_EV(ARMV8, EVENT_22H) \ __PMC_EV(ARMV8, EVENT_23H) \ __PMC_EV(ARMV8, EVENT_24H) \ __PMC_EV(ARMV8, EVENT_25H) \ __PMC_EV(ARMV8, EVENT_26H) \ __PMC_EV(ARMV8, EVENT_27H) \ __PMC_EV(ARMV8, EVENT_28H) \ __PMC_EV(ARMV8, EVENT_29H) \ __PMC_EV(ARMV8, EVENT_2AH) \ __PMC_EV(ARMV8, EVENT_2BH) \ __PMC_EV(ARMV8, EVENT_2CH) \ __PMC_EV(ARMV8, EVENT_2DH) \ __PMC_EV(ARMV8, EVENT_2EH) \ __PMC_EV(ARMV8, EVENT_2FH) \ __PMC_EV(ARMV8, EVENT_30H) \ __PMC_EV(ARMV8, EVENT_31H) \ __PMC_EV(ARMV8, EVENT_32H) \ __PMC_EV(ARMV8, EVENT_33H) \ __PMC_EV(ARMV8, EVENT_34H) \ __PMC_EV(ARMV8, EVENT_35H) \ __PMC_EV(ARMV8, EVENT_36H) \ __PMC_EV(ARMV8, EVENT_37H) \ __PMC_EV(ARMV8, EVENT_38H) \ __PMC_EV(ARMV8, EVENT_39H) \ __PMC_EV(ARMV8, EVENT_3AH) \ __PMC_EV(ARMV8, EVENT_3BH) \ __PMC_EV(ARMV8, EVENT_3CH) \ __PMC_EV(ARMV8, EVENT_3DH) \ __PMC_EV(ARMV8, EVENT_3EH) \ __PMC_EV(ARMV8, EVENT_3FH) \ __PMC_EV(ARMV8, EVENT_40H) \ __PMC_EV(ARMV8, EVENT_41H) \ __PMC_EV(ARMV8, EVENT_42H) \ __PMC_EV(ARMV8, EVENT_43H) \ __PMC_EV(ARMV8, EVENT_44H) \ __PMC_EV(ARMV8, EVENT_45H) \ __PMC_EV(ARMV8, EVENT_46H) \ __PMC_EV(ARMV8, EVENT_47H) \ __PMC_EV(ARMV8, EVENT_48H) \ __PMC_EV(ARMV8, EVENT_49H) \ __PMC_EV(ARMV8, EVENT_4AH) \ __PMC_EV(ARMV8, EVENT_4BH) \ __PMC_EV(ARMV8, EVENT_4CH) \ __PMC_EV(ARMV8, EVENT_4DH) \ __PMC_EV(ARMV8, EVENT_4EH) \ __PMC_EV(ARMV8, EVENT_4FH) \ __PMC_EV(ARMV8, EVENT_50H) \ __PMC_EV(ARMV8, EVENT_51H) \ __PMC_EV(ARMV8, EVENT_52H) \ __PMC_EV(ARMV8, EVENT_53H) \ __PMC_EV(ARMV8, EVENT_54H) \ __PMC_EV(ARMV8, EVENT_55H) \ __PMC_EV(ARMV8, EVENT_56H) \ __PMC_EV(ARMV8, EVENT_57H) \ __PMC_EV(ARMV8, EVENT_58H) \ __PMC_EV(ARMV8, EVENT_59H) \ __PMC_EV(ARMV8, EVENT_5AH) \ __PMC_EV(ARMV8, EVENT_5BH) \ __PMC_EV(ARMV8, EVENT_5CH) \ __PMC_EV(ARMV8, EVENT_5DH) \ __PMC_EV(ARMV8, EVENT_5EH) \ __PMC_EV(ARMV8, EVENT_5FH) \ __PMC_EV(ARMV8, EVENT_60H) \ __PMC_EV(ARMV8, EVENT_61H) \ __PMC_EV(ARMV8, EVENT_62H) \ __PMC_EV(ARMV8, EVENT_63H) \ __PMC_EV(ARMV8, EVENT_64H) \ __PMC_EV(ARMV8, EVENT_65H) \ __PMC_EV(ARMV8, EVENT_66H) \ __PMC_EV(ARMV8, EVENT_67H) \ __PMC_EV(ARMV8, EVENT_68H) \ __PMC_EV(ARMV8, EVENT_69H) \ __PMC_EV(ARMV8, EVENT_6AH) \ __PMC_EV(ARMV8, EVENT_6BH) \ __PMC_EV(ARMV8, EVENT_6CH) \ __PMC_EV(ARMV8, EVENT_6DH) \ __PMC_EV(ARMV8, EVENT_6EH) \ __PMC_EV(ARMV8, EVENT_6FH) \ __PMC_EV(ARMV8, EVENT_70H) \ __PMC_EV(ARMV8, EVENT_71H) \ __PMC_EV(ARMV8, EVENT_72H) \ __PMC_EV(ARMV8, EVENT_73H) \ __PMC_EV(ARMV8, EVENT_74H) \ __PMC_EV(ARMV8, EVENT_75H) \ __PMC_EV(ARMV8, EVENT_76H) \ __PMC_EV(ARMV8, EVENT_77H) \ __PMC_EV(ARMV8, EVENT_78H) \ __PMC_EV(ARMV8, EVENT_79H) \ __PMC_EV(ARMV8, EVENT_7AH) \ __PMC_EV(ARMV8, EVENT_7BH) \ __PMC_EV(ARMV8, EVENT_7CH) \ __PMC_EV(ARMV8, EVENT_7DH) \ __PMC_EV(ARMV8, EVENT_7EH) \ __PMC_EV(ARMV8, EVENT_7FH) \ __PMC_EV(ARMV8, EVENT_80H) \ __PMC_EV(ARMV8, EVENT_81H) \ __PMC_EV(ARMV8, EVENT_82H) \ __PMC_EV(ARMV8, EVENT_83H) \ __PMC_EV(ARMV8, EVENT_84H) \ __PMC_EV(ARMV8, EVENT_85H) \ __PMC_EV(ARMV8, EVENT_86H) \ __PMC_EV(ARMV8, EVENT_87H) \ __PMC_EV(ARMV8, EVENT_88H) \ __PMC_EV(ARMV8, EVENT_89H) \ __PMC_EV(ARMV8, EVENT_8AH) \ __PMC_EV(ARMV8, EVENT_8BH) \ __PMC_EV(ARMV8, EVENT_8CH) \ __PMC_EV(ARMV8, EVENT_8DH) \ __PMC_EV(ARMV8, EVENT_8EH) \ __PMC_EV(ARMV8, EVENT_8FH) \ __PMC_EV(ARMV8, EVENT_90H) \ __PMC_EV(ARMV8, EVENT_91H) \ __PMC_EV(ARMV8, EVENT_92H) \ __PMC_EV(ARMV8, EVENT_93H) \ __PMC_EV(ARMV8, EVENT_94H) \ __PMC_EV(ARMV8, EVENT_95H) \ __PMC_EV(ARMV8, EVENT_96H) \ __PMC_EV(ARMV8, EVENT_97H) \ __PMC_EV(ARMV8, EVENT_98H) \ __PMC_EV(ARMV8, EVENT_99H) \ __PMC_EV(ARMV8, EVENT_9AH) \ __PMC_EV(ARMV8, EVENT_9BH) \ __PMC_EV(ARMV8, EVENT_9CH) \ __PMC_EV(ARMV8, EVENT_9DH) \ __PMC_EV(ARMV8, EVENT_9EH) \ __PMC_EV(ARMV8, EVENT_9FH) \ __PMC_EV(ARMV8, EVENT_A0H) \ __PMC_EV(ARMV8, EVENT_A1H) \ __PMC_EV(ARMV8, EVENT_A2H) \ __PMC_EV(ARMV8, EVENT_A3H) \ __PMC_EV(ARMV8, EVENT_A4H) \ __PMC_EV(ARMV8, EVENT_A5H) \ __PMC_EV(ARMV8, EVENT_A6H) \ __PMC_EV(ARMV8, EVENT_A7H) \ __PMC_EV(ARMV8, EVENT_A8H) \ __PMC_EV(ARMV8, EVENT_A9H) \ __PMC_EV(ARMV8, EVENT_AAH) \ __PMC_EV(ARMV8, EVENT_ABH) \ __PMC_EV(ARMV8, EVENT_ACH) \ __PMC_EV(ARMV8, EVENT_ADH) \ __PMC_EV(ARMV8, EVENT_AEH) \ __PMC_EV(ARMV8, EVENT_AFH) \ __PMC_EV(ARMV8, EVENT_B0H) \ __PMC_EV(ARMV8, EVENT_B1H) \ __PMC_EV(ARMV8, EVENT_B2H) \ __PMC_EV(ARMV8, EVENT_B3H) \ __PMC_EV(ARMV8, EVENT_B4H) \ __PMC_EV(ARMV8, EVENT_B5H) \ __PMC_EV(ARMV8, EVENT_B6H) \ __PMC_EV(ARMV8, EVENT_B7H) \ __PMC_EV(ARMV8, EVENT_B8H) \ __PMC_EV(ARMV8, EVENT_B9H) \ __PMC_EV(ARMV8, EVENT_BAH) \ __PMC_EV(ARMV8, EVENT_BBH) \ __PMC_EV(ARMV8, EVENT_BCH) \ __PMC_EV(ARMV8, EVENT_BDH) \ __PMC_EV(ARMV8, EVENT_BEH) \ __PMC_EV(ARMV8, EVENT_BFH) \ __PMC_EV(ARMV8, EVENT_C0H) \ __PMC_EV(ARMV8, EVENT_C1H) \ __PMC_EV(ARMV8, EVENT_C2H) \ __PMC_EV(ARMV8, EVENT_C3H) \ __PMC_EV(ARMV8, EVENT_C4H) \ __PMC_EV(ARMV8, EVENT_C5H) \ __PMC_EV(ARMV8, EVENT_C6H) \ __PMC_EV(ARMV8, EVENT_C7H) \ __PMC_EV(ARMV8, EVENT_C8H) \ __PMC_EV(ARMV8, EVENT_C9H) \ __PMC_EV(ARMV8, EVENT_CAH) \ __PMC_EV(ARMV8, EVENT_CBH) \ __PMC_EV(ARMV8, EVENT_CCH) \ __PMC_EV(ARMV8, EVENT_CDH) \ __PMC_EV(ARMV8, EVENT_CEH) \ __PMC_EV(ARMV8, EVENT_CFH) \ __PMC_EV(ARMV8, EVENT_D0H) \ __PMC_EV(ARMV8, EVENT_D1H) \ __PMC_EV(ARMV8, EVENT_D2H) \ __PMC_EV(ARMV8, EVENT_D3H) \ __PMC_EV(ARMV8, EVENT_D4H) \ __PMC_EV(ARMV8, EVENT_D5H) \ __PMC_EV(ARMV8, EVENT_D6H) \ __PMC_EV(ARMV8, EVENT_D7H) \ __PMC_EV(ARMV8, EVENT_D8H) \ __PMC_EV(ARMV8, EVENT_D9H) \ __PMC_EV(ARMV8, EVENT_DAH) \ __PMC_EV(ARMV8, EVENT_DBH) \ __PMC_EV(ARMV8, EVENT_DCH) \ __PMC_EV(ARMV8, EVENT_DDH) \ __PMC_EV(ARMV8, EVENT_DEH) \ __PMC_EV(ARMV8, EVENT_DFH) \ __PMC_EV(ARMV8, EVENT_E0H) \ __PMC_EV(ARMV8, EVENT_E1H) \ __PMC_EV(ARMV8, EVENT_E2H) \ __PMC_EV(ARMV8, EVENT_E3H) \ __PMC_EV(ARMV8, EVENT_E4H) \ __PMC_EV(ARMV8, EVENT_E5H) \ __PMC_EV(ARMV8, EVENT_E6H) \ __PMC_EV(ARMV8, EVENT_E7H) \ __PMC_EV(ARMV8, EVENT_E8H) \ __PMC_EV(ARMV8, EVENT_E9H) \ __PMC_EV(ARMV8, EVENT_EAH) \ __PMC_EV(ARMV8, EVENT_EBH) \ __PMC_EV(ARMV8, EVENT_ECH) \ __PMC_EV(ARMV8, EVENT_EDH) \ __PMC_EV(ARMV8, EVENT_EEH) \ __PMC_EV(ARMV8, EVENT_EFH) \ __PMC_EV(ARMV8, EVENT_F0H) \ __PMC_EV(ARMV8, EVENT_F1H) \ __PMC_EV(ARMV8, EVENT_F2H) \ __PMC_EV(ARMV8, EVENT_F3H) \ __PMC_EV(ARMV8, EVENT_F4H) \ __PMC_EV(ARMV8, EVENT_F5H) \ __PMC_EV(ARMV8, EVENT_F6H) \ __PMC_EV(ARMV8, EVENT_F7H) \ __PMC_EV(ARMV8, EVENT_F8H) \ __PMC_EV(ARMV8, EVENT_F9H) \ __PMC_EV(ARMV8, EVENT_FAH) \ __PMC_EV(ARMV8, EVENT_FBH) \ __PMC_EV(ARMV8, EVENT_FCH) \ __PMC_EV(ARMV8, EVENT_FDH) \ __PMC_EV(ARMV8, EVENT_FEH) \ __PMC_EV(ARMV8, EVENT_FFH) #define PMC_EV_ARMV8_FIRST PMC_EV_ARMV8_EVENT_00H #define PMC_EV_ARMV8_LAST PMC_EV_ARMV8_EVENT_FFH #define __PMC_EV_ALIAS_ARMV8_COMMON() \ __PMC_EV_ALIAS("SW_INCR", ARMV8_EVENT_00H) \ __PMC_EV_ALIAS("L1I_CACHE_REFILL", ARMV8_EVENT_01H) \ __PMC_EV_ALIAS("L1I_TLB_REFILL", ARMV8_EVENT_02H) \ __PMC_EV_ALIAS("L1D_CACHE_REFILL", ARMV8_EVENT_03H) \ __PMC_EV_ALIAS("L1D_CACHE", ARMV8_EVENT_04H) \ __PMC_EV_ALIAS("L1D_TLB_REFILL", ARMV8_EVENT_05H) \ __PMC_EV_ALIAS("INST_RETIRED", ARMV8_EVENT_08H) \ __PMC_EV_ALIAS("EXC_TAKEN", ARMV8_EVENT_09H) \ __PMC_EV_ALIAS("EXC_RETURN", ARMV8_EVENT_0AH) \ __PMC_EV_ALIAS("CID_WRITE_RETIRED", ARMV8_EVENT_0BH) \ __PMC_EV_ALIAS("BR_MIS_PRED", ARMV8_EVENT_10H) \ __PMC_EV_ALIAS("CPU_CYCLES", ARMV8_EVENT_11H) \ __PMC_EV_ALIAS("BR_PRED", ARMV8_EVENT_12H) \ __PMC_EV_ALIAS("MEM_ACCESS", ARMV8_EVENT_13H) \ __PMC_EV_ALIAS("L1I_CACHE", ARMV8_EVENT_14H) \ __PMC_EV_ALIAS("L1D_CACHE_WB", ARMV8_EVENT_15H) \ __PMC_EV_ALIAS("L2D_CACHE", ARMV8_EVENT_16H) \ __PMC_EV_ALIAS("L2D_CACHE_REFILL", ARMV8_EVENT_17H) \ __PMC_EV_ALIAS("L2D_CACHE_WB", ARMV8_EVENT_18H) \ __PMC_EV_ALIAS("BUS_ACCESS", ARMV8_EVENT_19H) \ __PMC_EV_ALIAS("MEMORY_ERROR", ARMV8_EVENT_1AH) \ __PMC_EV_ALIAS("BUS_CYCLES", ARMV8_EVENT_1DH) \ __PMC_EV_ALIAS("CHAIN", ARMV8_EVENT_1EH) \ __PMC_EV_ALIAS("BUS_ACCESS_LD", ARMV8_EVENT_60H) \ __PMC_EV_ALIAS("BUS_ACCESS_ST", ARMV8_EVENT_61H) \ __PMC_EV_ALIAS("BR_INDIRECT_SPEC", ARMV8_EVENT_7AH) \ __PMC_EV_ALIAS("EXC_IRQ", ARMV8_EVENT_86H) \ __PMC_EV_ALIAS("EXC_FIQ", ARMV8_EVENT_87H) #define __PMC_EV_ALIAS_ARMV8_CORTEX_A53() \ __PMC_EV_ALIAS_ARMV8_COMMON() \ __PMC_EV_ALIAS("LD_RETIRED", ARMV8_EVENT_06H) \ __PMC_EV_ALIAS("ST_RETIRED", ARMV8_EVENT_07H) \ __PMC_EV_ALIAS("PC_WRITE_RETIRED", ARMV8_EVENT_0CH) \ __PMC_EV_ALIAS("BR_IMMED_RETIRED", ARMV8_EVENT_0DH) \ __PMC_EV_ALIAS("BR_RETURN_RETIRED", ARMV8_EVENT_0EH) \ __PMC_EV_ALIAS("UNALIGNED_LDST_RETIRED",ARMV8_EVENT_0FH) #define __PMC_EV_ALIAS_ARMV8_CORTEX_A57() \ __PMC_EV_ALIAS_ARMV8_COMMON() \ __PMC_EV_ALIAS("INST_SPEC", ARMV8_EVENT_1BH) \ __PMC_EV_ALIAS("TTBR_WRITE_RETIRED", ARMV8_EVENT_1CH) \ __PMC_EV_ALIAS("L1D_CACHE_LD", ARMV8_EVENT_40H) \ __PMC_EV_ALIAS("L1D_CACHE_ST", ARMV8_EVENT_41H) \ __PMC_EV_ALIAS("L1D_CACHE_REFILL_LD", ARMV8_EVENT_42H) \ __PMC_EV_ALIAS("L1D_CACHE_REFILL_ST", ARMV8_EVENT_43H) \ __PMC_EV_ALIAS("L1D_CACHE_WB_VICTIM", ARMV8_EVENT_46H) \ __PMC_EV_ALIAS("L1D_CACHE_WB_CLEAN", ARMV8_EVENT_47H) \ __PMC_EV_ALIAS("L1D_CACHE_INVAL", ARMV8_EVENT_48H) \ __PMC_EV_ALIAS("L1D_TLB_REFILL_LD", ARMV8_EVENT_4CH) \ __PMC_EV_ALIAS("L1D_TLB_REFILL_ST", ARMV8_EVENT_4DH) \ __PMC_EV_ALIAS("L2D_CACHE_LD", ARMV8_EVENT_50H) \ __PMC_EV_ALIAS("L2D_CACHE_ST", ARMV8_EVENT_51H) \ __PMC_EV_ALIAS("L2D_CACHE_REFILL_LD", ARMV8_EVENT_52H) \ __PMC_EV_ALIAS("L2D_CACHE_REFILL_ST", ARMV8_EVENT_53H) \ __PMC_EV_ALIAS("L2D_CACHE_WB_VICTIM", ARMV8_EVENT_56H) \ __PMC_EV_ALIAS("L2D_CACHE_WB_CLEAN", ARMV8_EVENT_57H) \ __PMC_EV_ALIAS("L2D_CACHE_INVAL", ARMV8_EVENT_58H) \ __PMC_EV_ALIAS("BUS_ACCESS_SHARED", ARMV8_EVENT_62H) \ __PMC_EV_ALIAS("BUS_ACCESS_NOT_SHARED", ARMV8_EVENT_63H) \ __PMC_EV_ALIAS("BUS_ACCESS_NORMAL", ARMV8_EVENT_64H) \ __PMC_EV_ALIAS("BUS_ACCESS_PERIPH", ARMV8_EVENT_65H) \ __PMC_EV_ALIAS("MEM_ACCESS_LD", ARMV8_EVENT_66H) \ __PMC_EV_ALIAS("MEM_ACCESS_ST", ARMV8_EVENT_67H) \ __PMC_EV_ALIAS("UNALIGNED_LD_SPEC", ARMV8_EVENT_68H) \ __PMC_EV_ALIAS("UNALIGNED_ST_SPEC", ARMV8_EVENT_69H) \ __PMC_EV_ALIAS("UNALIGNED_LDST_SPEC", ARMV8_EVENT_6AH) \ __PMC_EV_ALIAS("LDREX_SPEC", ARMV8_EVENT_6CH) \ __PMC_EV_ALIAS("STREX_PASS_SPEC", ARMV8_EVENT_6DH) \ __PMC_EV_ALIAS("STREX_FAIL_SPEC", ARMV8_EVENT_6EH) \ __PMC_EV_ALIAS("LD_SPEC", ARMV8_EVENT_70H) \ __PMC_EV_ALIAS("ST_SPEC", ARMV8_EVENT_71H) \ __PMC_EV_ALIAS("LDST_SPEC", ARMV8_EVENT_72H) \ __PMC_EV_ALIAS("DP_SPEC", ARMV8_EVENT_73H) \ __PMC_EV_ALIAS("ASE_SPEC", ARMV8_EVENT_74H) \ __PMC_EV_ALIAS("VFP_SPEC", ARMV8_EVENT_75H) \ __PMC_EV_ALIAS("PC_WRITE_SPEC", ARMV8_EVENT_76H) \ __PMC_EV_ALIAS("CRYPTO_SPEC", ARMV8_EVENT_77H) \ __PMC_EV_ALIAS("BR_IMMED_SPEC", ARMV8_EVENT_78H) \ __PMC_EV_ALIAS("BR_RETURN_SPEC", ARMV8_EVENT_79H) \ __PMC_EV_ALIAS("ISB_SPEC", ARMV8_EVENT_7CH) \ __PMC_EV_ALIAS("DSB_SPEC", ARMV8_EVENT_7DH) \ __PMC_EV_ALIAS("DMB_SPEC", ARMV8_EVENT_7EH) \ __PMC_EV_ALIAS("EXC_UNDEF", ARMV8_EVENT_81H) \ __PMC_EV_ALIAS("EXC_SVC", ARMV8_EVENT_82H) \ __PMC_EV_ALIAS("EXC_PABORT", ARMV8_EVENT_83H) \ __PMC_EV_ALIAS("EXC_DABORT", ARMV8_EVENT_84H) \ __PMC_EV_ALIAS("EXC_SMC", ARMV8_EVENT_88H) \ __PMC_EV_ALIAS("EXC_HVC", ARMV8_EVENT_8AH) \ __PMC_EV_ALIAS("EXC_TRAP_PABORT", ARMV8_EVENT_8BH) \ __PMC_EV_ALIAS("EXC_TRAP_DABORT", ARMV8_EVENT_8CH) \ __PMC_EV_ALIAS("EXC_TRAP_OTHER", ARMV8_EVENT_8DH) \ __PMC_EV_ALIAS("EXC_TRAP_IRQ", ARMV8_EVENT_8EH) \ __PMC_EV_ALIAS("EXC_TRAP_FIQ", ARMV8_EVENT_8FH) \ __PMC_EV_ALIAS("RC_LD_SPEC", ARMV8_EVENT_90H) \ __PMC_EV_ALIAS("RC_ST_SPEC", ARMV8_EVENT_91H) /* * MIPS Events from "Programming the MIPS32 24K Core Family", * Document Number: MD00355 Revision 04.63 December 19, 2008 * These events are kept in the order found in Table 7.4. * For counters which are different between the left hand * column (0/2) and the right hand column (1/3) the left * hand is given first, e.g. BRANCH_COMPLETED and BRANCH_MISPRED * in the definition below. */ #define __PMC_EV_MIPS24K() \ __PMC_EV(MIPS24K, CYCLE) \ __PMC_EV(MIPS24K, INSTR_EXECUTED) \ __PMC_EV(MIPS24K, BRANCH_COMPLETED) \ __PMC_EV(MIPS24K, BRANCH_MISPRED) \ __PMC_EV(MIPS24K, RETURN) \ __PMC_EV(MIPS24K, RETURN_MISPRED) \ __PMC_EV(MIPS24K, RETURN_NOT_31) \ __PMC_EV(MIPS24K, RETURN_NOTPRED) \ __PMC_EV(MIPS24K, ITLB_ACCESS) \ __PMC_EV(MIPS24K, ITLB_MISS) \ __PMC_EV(MIPS24K, DTLB_ACCESS) \ __PMC_EV(MIPS24K, DTLB_MISS) \ __PMC_EV(MIPS24K, JTLB_IACCESS) \ __PMC_EV(MIPS24K, JTLB_IMISS) \ __PMC_EV(MIPS24K, JTLB_DACCESS) \ __PMC_EV(MIPS24K, JTLB_DMISS) \ __PMC_EV(MIPS24K, IC_FETCH) \ __PMC_EV(MIPS24K, IC_MISS) \ __PMC_EV(MIPS24K, DC_LOADSTORE) \ __PMC_EV(MIPS24K, DC_WRITEBACK) \ __PMC_EV(MIPS24K, DC_MISS) \ __PMC_EV(MIPS24K, STORE_MISS) \ __PMC_EV(MIPS24K, LOAD_MISS) \ __PMC_EV(MIPS24K, INTEGER_COMPLETED) \ __PMC_EV(MIPS24K, FP_COMPLETED) \ __PMC_EV(MIPS24K, LOAD_COMPLETED) \ __PMC_EV(MIPS24K, STORE_COMPLETED) \ __PMC_EV(MIPS24K, BARRIER_COMPLETED) \ __PMC_EV(MIPS24K, MIPS16_COMPLETED) \ __PMC_EV(MIPS24K, NOP_COMPLETED) \ __PMC_EV(MIPS24K, INTEGER_MULDIV_COMPLETED)\ __PMC_EV(MIPS24K, RF_STALL) \ __PMC_EV(MIPS24K, INSTR_REFETCH) \ __PMC_EV(MIPS24K, STORE_COND_COMPLETED) \ __PMC_EV(MIPS24K, STORE_COND_FAILED) \ __PMC_EV(MIPS24K, ICACHE_REQUESTS) \ __PMC_EV(MIPS24K, ICACHE_HIT) \ __PMC_EV(MIPS24K, L2_WRITEBACK) \ __PMC_EV(MIPS24K, L2_ACCESS) \ __PMC_EV(MIPS24K, L2_MISS) \ __PMC_EV(MIPS24K, L2_ERR_CORRECTED) \ __PMC_EV(MIPS24K, EXCEPTIONS) \ __PMC_EV(MIPS24K, RF_CYCLES_STALLED) \ __PMC_EV(MIPS24K, IFU_CYCLES_STALLED) \ __PMC_EV(MIPS24K, ALU_CYCLES_STALLED) \ __PMC_EV(MIPS24K, UNCACHED_LOAD) \ __PMC_EV(MIPS24K, UNCACHED_STORE) \ __PMC_EV(MIPS24K, CP2_REG_TO_REG_COMPLETED)\ __PMC_EV(MIPS24K, MFTC_COMPLETED) \ __PMC_EV(MIPS24K, IC_BLOCKED_CYCLES) \ __PMC_EV(MIPS24K, DC_BLOCKED_CYCLES) \ __PMC_EV(MIPS24K, L2_IMISS_STALL_CYCLES) \ __PMC_EV(MIPS24K, L2_DMISS_STALL_CYCLES) \ __PMC_EV(MIPS24K, DMISS_CYCLES) \ __PMC_EV(MIPS24K, L2_MISS_CYCLES) \ __PMC_EV(MIPS24K, UNCACHED_BLOCK_CYCLES) \ __PMC_EV(MIPS24K, MDU_STALL_CYCLES) \ __PMC_EV(MIPS24K, FPU_STALL_CYCLES) \ __PMC_EV(MIPS24K, CP2_STALL_CYCLES) \ __PMC_EV(MIPS24K, COREXTEND_STALL_CYCLES) \ __PMC_EV(MIPS24K, ISPRAM_STALL_CYCLES) \ __PMC_EV(MIPS24K, DSPRAM_STALL_CYCLES) \ __PMC_EV(MIPS24K, CACHE_STALL_CYCLES) \ __PMC_EV(MIPS24K, LOAD_TO_USE_STALLS) \ __PMC_EV(MIPS24K, BASE_MISPRED_STALLS) \ __PMC_EV(MIPS24K, CPO_READ_STALLS) \ __PMC_EV(MIPS24K, BRANCH_MISPRED_CYCLES) \ __PMC_EV(MIPS24K, IFETCH_BUFFER_FULL) \ __PMC_EV(MIPS24K, FETCH_BUFFER_ALLOCATED) \ __PMC_EV(MIPS24K, EJTAG_ITRIGGER) \ __PMC_EV(MIPS24K, EJTAG_DTRIGGER) \ __PMC_EV(MIPS24K, FSB_LT_QUARTER) \ __PMC_EV(MIPS24K, FSB_QUARTER_TO_HALF) \ __PMC_EV(MIPS24K, FSB_GT_HALF) \ __PMC_EV(MIPS24K, FSB_FULL_PIPELINE_STALLS)\ __PMC_EV(MIPS24K, LDQ_LT_QUARTER) \ __PMC_EV(MIPS24K, LDQ_QUARTER_TO_HALF) \ __PMC_EV(MIPS24K, LDQ_GT_HALF) \ __PMC_EV(MIPS24K, LDQ_FULL_PIPELINE_STALLS)\ __PMC_EV(MIPS24K, WBB_LT_QUARTER) \ __PMC_EV(MIPS24K, WBB_QUARTER_TO_HALF) \ __PMC_EV(MIPS24K, WBB_GT_HALF) \ __PMC_EV(MIPS24K, WBB_FULL_PIPELINE_STALLS) \ __PMC_EV(MIPS24K, REQUEST_LATENCY) \ __PMC_EV(MIPS24K, REQUEST_COUNT) #define PMC_EV_MIPS24K_FIRST PMC_EV_MIPS24K_CYCLE #define PMC_EV_MIPS24K_LAST PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS /* * MIPS74k events. Similar to MIPS24k, the arrangement * is (0,2) then (1,3) events. */ #define __PMC_EV_MIPS74K() \ __PMC_EV(MIPS74K, CYCLES) \ __PMC_EV(MIPS74K, INSTR_EXECUTED) \ __PMC_EV(MIPS74K, PREDICTED_JR_31) \ __PMC_EV(MIPS74K, JR_31_MISPREDICTIONS) \ __PMC_EV(MIPS74K, REDIRECT_STALLS) \ __PMC_EV(MIPS74K, JR_31_NO_PREDICTIONS) \ __PMC_EV(MIPS74K, ITLB_ACCESSES) \ __PMC_EV(MIPS74K, ITLB_MISSES) \ __PMC_EV(MIPS74K, JTLB_INSN_MISSES) \ __PMC_EV(MIPS74K, ICACHE_ACCESSES) \ __PMC_EV(MIPS74K, ICACHE_MISSES) \ __PMC_EV(MIPS74K, ICACHE_MISS_STALLS) \ __PMC_EV(MIPS74K, UNCACHED_IFETCH_STALLS) \ __PMC_EV(MIPS74K, PDTRACE_BACK_STALLS) \ __PMC_EV(MIPS74K, IFU_REPLAYS) \ __PMC_EV(MIPS74K, KILLED_FETCH_SLOTS) \ __PMC_EV(MIPS74K, IFU_IDU_MISS_PRED_UPSTREAM_CYCLES) \ __PMC_EV(MIPS74K, IFU_IDU_NO_FETCH_CYCLES) \ __PMC_EV(MIPS74K, IFU_IDU_CLOGED_DOWNSTREAM_CYCLES) \ __PMC_EV(MIPS74K, DDQ0_FULL_DR_STALLS) \ __PMC_EV(MIPS74K, DDQ1_FULL_DR_STALLS) \ __PMC_EV(MIPS74K, ALCB_FULL_DR_STALLS) \ __PMC_EV(MIPS74K, AGCB_FULL_DR_STALLS) \ __PMC_EV(MIPS74K, CLDQ_FULL_DR_STALLS) \ __PMC_EV(MIPS74K, IODQ_FULL_DR_STALLS) \ __PMC_EV(MIPS74K, ALU_EMPTY_CYCLES) \ __PMC_EV(MIPS74K, AGEN_EMPTY_CYCLES) \ __PMC_EV(MIPS74K, ALU_OPERANDS_NOT_READY_CYCLES) \ __PMC_EV(MIPS74K, AGEN_OPERANDS_NOT_READY_CYCLES) \ __PMC_EV(MIPS74K, ALU_NO_ISSUES_CYCLES) \ __PMC_EV(MIPS74K, AGEN_NO_ISSUES_CYCLES) \ __PMC_EV(MIPS74K, ALU_BUBBLE_CYCLES) \ __PMC_EV(MIPS74K, AGEN_BUBBLE_CYCLES) \ __PMC_EV(MIPS74K, SINGLE_ISSUE_CYCLES) \ __PMC_EV(MIPS74K, DUAL_ISSUE_CYCLES) \ __PMC_EV(MIPS74K, OOO_ALU_ISSUE_CYCLES) \ __PMC_EV(MIPS74K, OOO_AGEN_ISSUE_CYCLES) \ __PMC_EV(MIPS74K, JALR_JALR_HB_INSNS) \ __PMC_EV(MIPS74K, DCACHE_LINE_REFILL_REQUESTS) \ __PMC_EV(MIPS74K, DCACHE_LOAD_ACCESSES) \ __PMC_EV(MIPS74K, DCACHE_ACCESSES) \ __PMC_EV(MIPS74K, DCACHE_WRITEBACKS) \ __PMC_EV(MIPS74K, DCACHE_MISSES) \ __PMC_EV(MIPS74K, JTLB_DATA_ACCESSES) \ __PMC_EV(MIPS74K, JTLB_DATA_MISSES) \ __PMC_EV(MIPS74K, LOAD_STORE_REPLAYS) \ __PMC_EV(MIPS74K, VA_TRANSALTION_CORNER_CASES) \ __PMC_EV(MIPS74K, LOAD_STORE_BLOCKED_CYCLES) \ __PMC_EV(MIPS74K, LOAD_STORE_NO_FILL_REQUESTS) \ __PMC_EV(MIPS74K, L2_CACHE_WRITEBACKS) \ __PMC_EV(MIPS74K, L2_CACHE_ACCESSES) \ __PMC_EV(MIPS74K, L2_CACHE_MISSES) \ __PMC_EV(MIPS74K, L2_CACHE_MISS_CYCLES) \ __PMC_EV(MIPS74K, FSB_FULL_STALLS) \ __PMC_EV(MIPS74K, FSB_OVER_50_FULL) \ __PMC_EV(MIPS74K, LDQ_FULL_STALLS) \ __PMC_EV(MIPS74K, LDQ_OVER_50_FULL) \ __PMC_EV(MIPS74K, WBB_FULL_STALLS) \ __PMC_EV(MIPS74K, WBB_OVER_50_FULL) \ __PMC_EV(MIPS74K, LOAD_MISS_CONSUMER_REPLAYS) \ __PMC_EV(MIPS74K, CP1_CP2_LOAD_INSNS) \ __PMC_EV(MIPS74K, JR_NON_31_INSNS) \ __PMC_EV(MIPS74K, MISPREDICTED_JR_31_INSNS) \ __PMC_EV(MIPS74K, BRANCH_INSNS) \ __PMC_EV(MIPS74K, CP1_CP2_COND_BRANCH_INSNS) \ __PMC_EV(MIPS74K, BRANCH_LIKELY_INSNS) \ __PMC_EV(MIPS74K, MISPREDICTED_BRANCH_LIKELY_INSNS) \ __PMC_EV(MIPS74K, COND_BRANCH_INSNS) \ __PMC_EV(MIPS74K, MISPREDICTED_BRANCH_INSNS) \ __PMC_EV(MIPS74K, INTEGER_INSNS) \ __PMC_EV(MIPS74K, FPU_INSNS) \ __PMC_EV(MIPS74K, LOAD_INSNS) \ __PMC_EV(MIPS74K, STORE_INSNS) \ __PMC_EV(MIPS74K, J_JAL_INSNS) \ __PMC_EV(MIPS74K, MIPS16_INSNS) \ __PMC_EV(MIPS74K, NOP_INSNS) \ __PMC_EV(MIPS74K, NT_MUL_DIV_INSNS) \ __PMC_EV(MIPS74K, DSP_INSNS) \ __PMC_EV(MIPS74K, ALU_DSP_SATURATION_INSNS) \ __PMC_EV(MIPS74K, DSP_BRANCH_INSNS) \ __PMC_EV(MIPS74K, MDU_DSP_SATURATION_INSNS) \ __PMC_EV(MIPS74K, UNCACHED_LOAD_INSNS) \ __PMC_EV(MIPS74K, UNCACHED_STORE_INSNS) \ __PMC_EV(MIPS74K, EJTAG_INSN_TRIGGERS) \ __PMC_EV(MIPS74K, CP1_BRANCH_MISPREDICTIONS) \ __PMC_EV(MIPS74K, SC_INSNS) \ __PMC_EV(MIPS74K, FAILED_SC_INSNS) \ __PMC_EV(MIPS74K, PREFETCH_INSNS) \ __PMC_EV(MIPS74K, CACHE_HIT_PREFETCH_INSNS) \ __PMC_EV(MIPS74K, NO_INSN_CYCLES) \ __PMC_EV(MIPS74K, LOAD_MISS_INSNS) \ __PMC_EV(MIPS74K, ONE_INSN_CYCLES) \ __PMC_EV(MIPS74K, TWO_INSNS_CYCLES) \ __PMC_EV(MIPS74K, GFIFO_BLOCKED_CYCLES) \ __PMC_EV(MIPS74K, CP1_CP2_STORE_INSNS) \ __PMC_EV(MIPS74K, MISPREDICTION_STALLS) \ __PMC_EV(MIPS74K, MISPREDICTED_BRANCH_INSNS_CYCLES) \ __PMC_EV(MIPS74K, EXCEPTIONS_TAKEN) \ __PMC_EV(MIPS74K, GRADUATION_REPLAYS) \ __PMC_EV(MIPS74K, COREEXTEND_EVENTS) \ __PMC_EV(MIPS74K, ISPRAM_EVENTS) \ __PMC_EV(MIPS74K, DSPRAM_EVENTS) \ __PMC_EV(MIPS74K, L2_CACHE_SINGLE_BIT_ERRORS) \ __PMC_EV(MIPS74K, SYSTEM_EVENT_0) \ __PMC_EV(MIPS74K, SYSTEM_EVENT_1) \ __PMC_EV(MIPS74K, SYSTEM_EVENT_2) \ __PMC_EV(MIPS74K, SYSTEM_EVENT_3) \ __PMC_EV(MIPS74K, SYSTEM_EVENT_4) \ __PMC_EV(MIPS74K, SYSTEM_EVENT_5) \ __PMC_EV(MIPS74K, SYSTEM_EVENT_6) \ __PMC_EV(MIPS74K, SYSTEM_EVENT_7) \ __PMC_EV(MIPS74K, OCP_ALL_REQUESTS) \ __PMC_EV(MIPS74K, OCP_ALL_CACHEABLE_REQUESTS) \ __PMC_EV(MIPS74K, OCP_READ_REQUESTS) \ __PMC_EV(MIPS74K, OCP_READ_CACHEABLE_REQUESTS) \ __PMC_EV(MIPS74K, OCP_WRITE_REQUESTS) \ __PMC_EV(MIPS74K, OCP_WRITE_CACHEABLE_REQUESTS) \ __PMC_EV(MIPS74K, FSB_LESS_25_FULL) \ __PMC_EV(MIPS74K, FSB_25_50_FULL) \ __PMC_EV(MIPS74K, LDQ_LESS_25_FULL) \ __PMC_EV(MIPS74K, LDQ_25_50_FULL) \ __PMC_EV(MIPS74K, WBB_LESS_25_FULL) \ __PMC_EV(MIPS74K, WBB_25_50_FULL) #define PMC_EV_MIPS74K_FIRST PMC_EV_MIPS74K_CYCLES #define PMC_EV_MIPS74K_LAST PMC_EV_MIPS74K_WBB_25_50_FULL /* * Cavium Octeon counters. Obtained from cvmx-core.h */ #define __PMC_EV_OCTEON() \ __PMC_EV(OCTEON, CLK) \ __PMC_EV(OCTEON, ISSUE) \ __PMC_EV(OCTEON, RET) \ __PMC_EV(OCTEON, NISSUE) \ __PMC_EV(OCTEON, SISSUE) \ __PMC_EV(OCTEON, DISSUE) \ __PMC_EV(OCTEON, IFI) \ __PMC_EV(OCTEON, BR) \ __PMC_EV(OCTEON, BRMIS) \ __PMC_EV(OCTEON, J) \ __PMC_EV(OCTEON, JMIS) \ __PMC_EV(OCTEON, REPLAY) \ __PMC_EV(OCTEON, IUNA) \ __PMC_EV(OCTEON, TRAP) \ __PMC_EV(OCTEON, UULOAD) \ __PMC_EV(OCTEON, UUSTORE) \ __PMC_EV(OCTEON, ULOAD) \ __PMC_EV(OCTEON, USTORE) \ __PMC_EV(OCTEON, EC) \ __PMC_EV(OCTEON, MC) \ __PMC_EV(OCTEON, CC) \ __PMC_EV(OCTEON, CSRC) \ __PMC_EV(OCTEON, CFETCH) \ __PMC_EV(OCTEON, CPREF) \ __PMC_EV(OCTEON, ICA) \ __PMC_EV(OCTEON, II) \ __PMC_EV(OCTEON, IP) \ __PMC_EV(OCTEON, CIMISS) \ __PMC_EV(OCTEON, WBUF) \ __PMC_EV(OCTEON, WDAT) \ __PMC_EV(OCTEON, WBUFLD) \ __PMC_EV(OCTEON, WBUFFL) \ __PMC_EV(OCTEON, WBUFTR) \ __PMC_EV(OCTEON, BADD) \ __PMC_EV(OCTEON, BADDL2) \ __PMC_EV(OCTEON, BFILL) \ __PMC_EV(OCTEON, DDIDS) \ __PMC_EV(OCTEON, IDIDS) \ __PMC_EV(OCTEON, DIDNA) \ __PMC_EV(OCTEON, LDS) \ __PMC_EV(OCTEON, LMLDS) \ __PMC_EV(OCTEON, IOLDS) \ __PMC_EV(OCTEON, DMLDS) \ __PMC_EV(OCTEON, STS) \ __PMC_EV(OCTEON, LMSTS) \ __PMC_EV(OCTEON, IOSTS) \ __PMC_EV(OCTEON, IOBDMA) \ __PMC_EV(OCTEON, DTLB) \ __PMC_EV(OCTEON, DTLBAD) \ __PMC_EV(OCTEON, ITLB) \ __PMC_EV(OCTEON, SYNC) \ __PMC_EV(OCTEON, SYNCIOB) \ __PMC_EV(OCTEON, SYNCW) #define PMC_EV_OCTEON_FIRST PMC_EV_OCTEON_CLK #define PMC_EV_OCTEON_LAST PMC_EV_OCTEON_SYNCW #define __PMC_EV_PPC7450() \ __PMC_EV(PPC7450, CYCLE) \ __PMC_EV(PPC7450, INSTR_COMPLETED) \ __PMC_EV(PPC7450, TLB_BIT_TRANSITIONS) \ __PMC_EV(PPC7450, INSTR_DISPATCHED) \ __PMC_EV(PPC7450, PMON_EXCEPT) \ __PMC_EV(PPC7450, PMON_SIG) \ __PMC_EV(PPC7450, VPU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VFPU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VIU1_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VIU2_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MTVSCR_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MTVRSAVE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VPU_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, VFPU_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, VIU1_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, VIU2_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, MFVSCR_SYNC_CYCLES) \ __PMC_EV(PPC7450, VSCR_SAT_SET) \ __PMC_EV(PPC7450, STORE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, L1_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L1_DATA_SNOOPS) \ __PMC_EV(PPC7450, UNRESOLVED_BRANCHES) \ __PMC_EV(PPC7450, SPEC_BUFFER_CYCLES) \ __PMC_EV(PPC7450, BRANCH_UNIT_STALL_CYCLES) \ __PMC_EV(PPC7450, TRUE_BRANCH_TARGET_HITS) \ __PMC_EV(PPC7450, BRANCH_LINK_STAC_PREDICTED) \ __PMC_EV(PPC7450, GPR_ISSUE_QUEUE_DISPATCHES) \ __PMC_EV(PPC7450, CYCLES_THREE_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES) \ __PMC_EV(PPC7450, THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES) \ __PMC_EV(PPC7450, CYCLES_NO_COMPLETED_INSTRS) \ __PMC_EV(PPC7450, IU2_INSTR_COMPLETED) \ __PMC_EV(PPC7450, BRANCHES_COMPLETED) \ __PMC_EV(PPC7450, EIEIO_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MTSPR_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SC_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LS_LM_COMPLETED) \ __PMC_EV(PPC7450, ITLB_HW_TABLE_SEARCH_CYCLES) \ __PMC_EV(PPC7450, DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, L1_INSTR_CACHE_ACCESSES) \ __PMC_EV(PPC7450, INSTR_BKPT_MATCHES) \ __PMC_EV(PPC7450, L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD)\ __PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_ON_MODIFIED) \ __PMC_EV(PPC7450, LOAD_MISS_ALIAS) \ __PMC_EV(PPC7450, LOAD_MISS_ALIAS_ON_TOUCH) \ __PMC_EV(PPC7450, TOUCH_ALIAS) \ __PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_CASTOUT_QUEUE) \ __PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_CASTOUT) \ __PMC_EV(PPC7450, L1_DATA_SNOOP_HITS) \ __PMC_EV(PPC7450, WRITE_THROUGH_STORES) \ __PMC_EV(PPC7450, CACHE_INHIBITED_STORES) \ __PMC_EV(PPC7450, L1_DATA_LOAD_HIT) \ __PMC_EV(PPC7450, L1_DATA_TOUCH_HIT) \ __PMC_EV(PPC7450, L1_DATA_STORE_HIT) \ __PMC_EV(PPC7450, L1_DATA_TOTAL_HITS) \ __PMC_EV(PPC7450, DST_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, REFRESHED_DSTS) \ __PMC_EV(PPC7450, SUCCESSFUL_DST_TABLE_SEARCHES) \ __PMC_EV(PPC7450, DSS_INSTR_COMPLETED) \ __PMC_EV(PPC7450, DST_STREAM_0_CACHE_LINE_FETCHES) \ __PMC_EV(PPC7450, VTQ_SUSPENDS_DUE_TO_CTX_CHANGE) \ __PMC_EV(PPC7450, VTQ_LINE_FETCH_HIT) \ __PMC_EV(PPC7450, VEC_LOAD_INSTR_COMPLETED) \ __PMC_EV(PPC7450, FP_STORE_INSTR_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, FPU_RENORMALIZATION) \ __PMC_EV(PPC7450, FPU_DENORMALIZATION) \ __PMC_EV(PPC7450, FP_STORE_CAUSES_STALL_IN_LSU) \ __PMC_EV(PPC7450, LD_ST_TRUE_ALIAS_STALL) \ __PMC_EV(PPC7450, LSU_INDEXED_ALIAS_STALL) \ __PMC_EV(PPC7450, LSU_ALIAS_VS_FSQ_WB0_WB1) \ __PMC_EV(PPC7450, LSU_ALIAS_VS_CSQ) \ __PMC_EV(PPC7450, LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0) \ __PMC_EV(PPC7450, LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0) \ __PMC_EV(PPC7450, LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1) \ __PMC_EV(PPC7450, LSU_TOUCH_ALIAS_VS_CSQ) \ __PMC_EV(PPC7450, LSU_LMQ_FULL_STALL) \ __PMC_EV(PPC7450, FP_LOAD_INSTR_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, FP_LOAD_DOUBLE_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, LSU_RA_LATCH_STALL) \ __PMC_EV(PPC7450, LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL) \ __PMC_EV(PPC7450, LSU_LMQ_INDEX_ALIAS) \ __PMC_EV(PPC7450, LSU_STORE_QUEUE_INDEX_ALIAS) \ __PMC_EV(PPC7450, LSU_CSQ_FORWARDING) \ __PMC_EV(PPC7450, LSU_MISALIGNED_LOAD_FINISH) \ __PMC_EV(PPC7450, LSU_MISALIGN_STORE_COMPLETED) \ __PMC_EV(PPC7450, LSU_MISALIGN_STALL) \ __PMC_EV(PPC7450, FP_ONE_QUARTER_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_ONE_HALF_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_ALL_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_DENORMALIZED_RESULT) \ __PMC_EV(PPC7450, L1_DATA_TOTAL_MISSES) \ __PMC_EV(PPC7450, DISPATCHES_TO_FPR_ISSUE_QUEUE) \ __PMC_EV(PPC7450, LSU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LOAD_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SS_SM_INSTR_COMPLETED) \ __PMC_EV(PPC7450, TLBIE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LWARX_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MFSPR_INSTR_COMPLETED) \ __PMC_EV(PPC7450, REFETCH_SERIALIZATION) \ __PMC_EV(PPC7450, COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, CYCLES_ONE_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, CYCLES_TWO_INSTR_COMPLETED) \ __PMC_EV(PPC7450, ITLB_NON_SPECULATIVE_MISSES) \ __PMC_EV(PPC7450, CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS) \ __PMC_EV(PPC7450, L1_DATA_LOAD_ACCESS_MISS) \ __PMC_EV(PPC7450, L1_DATA_TOUCH_MISS) \ __PMC_EV(PPC7450, L1_DATA_STORE_MISS) \ __PMC_EV(PPC7450, L1_DATA_TOUCH_MISS_CYCLES) \ __PMC_EV(PPC7450, L1_DATA_CYCLES_USED) \ __PMC_EV(PPC7450, DST_STREAM_1_CACHE_LINE_FETCHES) \ __PMC_EV(PPC7450, VTQ_STREAM_CANCELED_PREMATURELY) \ __PMC_EV(PPC7450, VTQ_RESUMES_DUE_TO_CTX_CHANGE) \ __PMC_EV(PPC7450, VTQ_LINE_FETCH_MISS) \ __PMC_EV(PPC7450, VTQ_LINE_FETCH) \ __PMC_EV(PPC7450, TLBIE_SNOOPS) \ __PMC_EV(PPC7450, L1_INSTR_CACHE_RELOADS) \ __PMC_EV(PPC7450, L1_DATA_CACHE_RELOADS) \ __PMC_EV(PPC7450, L1_DATA_CACHE_CASTOUTS_TO_L2) \ __PMC_EV(PPC7450, STORE_MERGE_GATHER) \ __PMC_EV(PPC7450, CACHEABLE_STORE_MERGE_TO_32_BYTES) \ __PMC_EV(PPC7450, DATA_BKPT_MATCHES) \ __PMC_EV(PPC7450, FALL_THROUGH_BRANCHES_PROCESSED) \ __PMC_EV(PPC7450, \ FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \ __PMC_EV(PPC7450, SECOND_SPECULATION_BUFFER_ACTIVE) \ __PMC_EV(PPC7450, BPU_STALL_ON_LR_DEPENDENCY) \ __PMC_EV(PPC7450, BTIC_MISS) \ __PMC_EV(PPC7450, BRANCH_LINK_STACK_CORRECTLY_RESOLVED) \ __PMC_EV(PPC7450, FPR_ISSUE_STALLED) \ __PMC_EV(PPC7450, SWITCHES_BETWEEN_PRIV_USER) \ __PMC_EV(PPC7450, LSU_COMPLETES_FP_STORE_SINGLE) \ __PMC_EV(PPC7450, VR_ISSUE_QUEUE_DISPATCHES) \ __PMC_EV(PPC7450, VR_STALLS) \ __PMC_EV(PPC7450, GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, FPR_ISSUE_QUEUE_ENTRIES) \ __PMC_EV(PPC7450, FPU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, STWCX_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LS_LM_INSTR_PIECES) \ __PMC_EV(PPC7450, ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, DTLB_MISSES) \ __PMC_EV(PPC7450, CANCELLED_L1_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L1_DATA_CACHE_OP_HIT) \ __PMC_EV(PPC7450, L1_DATA_LOAD_MISS_CYCLES) \ __PMC_EV(PPC7450, L1_DATA_PUSHES) \ __PMC_EV(PPC7450, L1_DATA_TOTAL_MISS) \ __PMC_EV(PPC7450, VT2_FETCHES) \ __PMC_EV(PPC7450, TAKEN_BRANCHES_PROCESSED) \ __PMC_EV(PPC7450, BRANCH_FLUSHES) \ __PMC_EV(PPC7450, \ SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \ __PMC_EV(PPC7450, THIRD_SPECULATION_BUFFER_ACTIVE) \ __PMC_EV(PPC7450, BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY) \ __PMC_EV(PPC7450, FAST_BTIC_HIT) \ __PMC_EV(PPC7450, BRANCH_LINK_STACK_MISPREDICTED) \ __PMC_EV(PPC7450, CYCLES_THREE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, CYCLES_NO_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, GPR_ISSUE_QUEUE_STALLED) \ __PMC_EV(PPC7450, IU1_INSTR_COMPLETED) \ __PMC_EV(PPC7450, DSSALL_INSTR_COMPLETED) \ __PMC_EV(PPC7450, TLBSYNC_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SYNC_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SS_SM_INSTR_PIECES) \ __PMC_EV(PPC7450, DTLB_HW_SEARCH_CYCLES) \ __PMC_EV(PPC7450, SNOOP_RETRIES) \ __PMC_EV(PPC7450, SUCCESSFUL_STWCX) \ __PMC_EV(PPC7450, DST_STREAM_3_CACHE_LINE_FETCHES) \ __PMC_EV(PPC7450, \ THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \ __PMC_EV(PPC7450, MISPREDICTED_BRANCHES) \ __PMC_EV(PPC7450, FOLDED_BRANCHES) \ __PMC_EV(PPC7450, FP_STORE_DOUBLE_COMPLETES_IN_LSU) \ __PMC_EV(PPC7450, L2_CACHE_HITS) \ __PMC_EV(PPC7450, L3_CACHE_HITS) \ __PMC_EV(PPC7450, L2_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L3_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L2_DATA_CACHE_MISSES) \ __PMC_EV(PPC7450, L3_DATA_CACHE_MISSES) \ __PMC_EV(PPC7450, L2_LOAD_HITS) \ __PMC_EV(PPC7450, L2_STORE_HITS) \ __PMC_EV(PPC7450, L3_LOAD_HITS) \ __PMC_EV(PPC7450, L3_STORE_HITS) \ __PMC_EV(PPC7450, L2_TOUCH_HITS) \ __PMC_EV(PPC7450, L3_TOUCH_HITS) \ __PMC_EV(PPC7450, SNOOP_MODIFIED) \ __PMC_EV(PPC7450, SNOOP_VALID) \ __PMC_EV(PPC7450, INTERVENTION) \ __PMC_EV(PPC7450, L2_CACHE_MISSES) \ __PMC_EV(PPC7450, L3_CACHE_MISSES) \ __PMC_EV(PPC7450, L2_CACHE_CASTOUTS) \ __PMC_EV(PPC7450, L3_CACHE_CASTOUTS) \ __PMC_EV(PPC7450, L2SQ_FULL_CYCLES) \ __PMC_EV(PPC7450, L3SQ_FULL_CYCLES) \ __PMC_EV(PPC7450, RAQ_FULL_CYCLES) \ __PMC_EV(PPC7450, WAQ_FULL_CYCLES) \ __PMC_EV(PPC7450, L1_EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, L2_EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, L3_EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, EXTERNAL_PUSHES) \ __PMC_EV(PPC7450, EXTERNAL_SNOOP_RETRY) \ __PMC_EV(PPC7450, DTQ_FULL_CYCLES) \ __PMC_EV(PPC7450, BUS_RETRY) \ __PMC_EV(PPC7450, L2_VALID_REQUEST) \ __PMC_EV(PPC7450, BORDQ_FULL) \ __PMC_EV(PPC7450, BUS_TAS_FOR_READS) \ __PMC_EV(PPC7450, BUS_TAS_FOR_WRITES) \ __PMC_EV(PPC7450, BUS_READS_NOT_RETRIED) \ __PMC_EV(PPC7450, BUS_WRITES_NOT_RETRIED) \ __PMC_EV(PPC7450, BUS_READS_WRITES_NOT_RETRIED) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_L1_RETRY) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_COLLISION) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_INTERVENTION_ORDERING) \ __PMC_EV(PPC7450, SNOOP_REQUESTS) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_REQUEST) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_LOAD) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_STORE) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH) \ __PMC_EV(PPC7450, \ PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_FULL) #define PMC_EV_PPC7450_FIRST PMC_EV_PPC7450_CYCLE #define PMC_EV_PPC7450_LAST PMC_EV_PPC7450_PREFETCH_ENGINE_FULL #define __PMC_EV_PPC970() \ __PMC_EV(PPC970, INSTR_COMPLETED) \ __PMC_EV(PPC970, MARKED_GROUP_DISPATCH) \ __PMC_EV(PPC970, MARKED_STORE_COMPLETED) \ __PMC_EV(PPC970, GCT_EMPTY) \ __PMC_EV(PPC970, RUN_CYCLES) \ __PMC_EV(PPC970, OVERFLOW) \ __PMC_EV(PPC970, CYCLES) \ __PMC_EV(PPC970, THRESHOLD_TIMEOUT) \ __PMC_EV(PPC970, GROUP_DISPATCH) \ __PMC_EV(PPC970, BR_MARKED_INSTR_FINISH) \ __PMC_EV(PPC970, GCT_EMPTY_BY_SRQ_FULL) \ __PMC_EV(PPC970, STOP_COMPLETION) \ __PMC_EV(PPC970, LSU_EMPTY) \ __PMC_EV(PPC970, MARKED_STORE_WITH_INTR) \ __PMC_EV(PPC970, CYCLES_IN_SUPER) \ __PMC_EV(PPC970, VPU_MARKED_INSTR_COMPLETED) \ __PMC_EV(PPC970, FXU0_IDLE_FXU1_BUSY) \ __PMC_EV(PPC970, SRQ_EMPTY) \ __PMC_EV(PPC970, MARKED_GROUP_COMPLETED) \ __PMC_EV(PPC970, CR_MARKED_INSTR_FINISH) \ __PMC_EV(PPC970, DISPATCH_SUCCESS) \ __PMC_EV(PPC970, FXU0_IDLE_FXU1_IDLE) \ __PMC_EV(PPC970, ONE_PLUS_INSTR_COMPLETED) \ __PMC_EV(PPC970, GROUP_MARKED_IDU) \ __PMC_EV(PPC970, MARKED_GROUP_COMPLETE_TIMEOUT) \ __PMC_EV(PPC970, FXU0_BUSY_FXU1_BUSY) \ __PMC_EV(PPC970, MARKED_STORE_SENT_TO_STS) \ __PMC_EV(PPC970, FXU_MARKED_INSTR_FINISHED) \ __PMC_EV(PPC970, MARKED_GROUP_ISSUED) \ __PMC_EV(PPC970, FXU0_BUSY_FXU1_IDLE) \ __PMC_EV(PPC970, GROUP_COMPLETED) \ __PMC_EV(PPC970, FPU_MARKED_INSTR_COMPLETED) \ __PMC_EV(PPC970, MARKED_INSTR_FINISH_ANY_UNIT) \ __PMC_EV(PPC970, EXTERNAL_INTERRUPT) \ __PMC_EV(PPC970, GROUP_DISPATCH_REJECT) \ __PMC_EV(PPC970, LSU_MARKED_INSTR_FINISH) \ __PMC_EV(PPC970, TIMEBASE_EVENT) \ __PMC_EV(PPC970, LSU_COMPLETION_STALL) \ __PMC_EV(PPC970, FXU_COMPLETION_STALL) \ __PMC_EV(PPC970, DCACHE_MISS_COMPLETION_STALL) \ __PMC_EV(PPC970, FPU_COMPLETION_STALL) \ __PMC_EV(PPC970, FXU_LONG_INSTR_COMPLETION_STALL) \ __PMC_EV(PPC970, REJECT_COMPLETION_STALL) \ __PMC_EV(PPC970, FPU_LONG_INSTR_COMPLETION_STALL) \ __PMC_EV(PPC970, GCT_EMPTY_BY_ICACHE_MISS) \ __PMC_EV(PPC970, REJECT_COMPLETION_STALL_ERAT_MISS) \ __PMC_EV(PPC970, GCT_EMPTY_BY_BRANCH_MISS_PREDICT) \ __PMC_EV(PPC970, BUS_HIGH) \ __PMC_EV(PPC970, BUS_LOW) \ __PMC_EV(PPC970, ADDER) #define PMC_EV_PPC970_FIRST PMC_EV_PPC970_INSTR_COMPLETED #define PMC_EV_PPC970_LAST PMC_EV_PPC970_ADDER #define __PMC_EV_E500() \ __PMC_EV(E500, CYCLES) \ __PMC_EV(E500, INSTR_COMPLETED) \ __PMC_EV(E500, UOPS_COMPLETED) \ __PMC_EV(E500, INSTR_FETCHED) \ __PMC_EV(E500, UOPS_DECODED) \ __PMC_EV(E500, PM_EVENT_TRANSITIONS) \ __PMC_EV(E500, PM_EVENT_CYCLES) \ __PMC_EV(E500, BRANCH_INSTRS_COMPLETED) \ __PMC_EV(E500, LOAD_UOPS_COMPLETED) \ __PMC_EV(E500, STORE_UOPS_COMPLETED) \ __PMC_EV(E500, CQ_REDIRECTS) \ __PMC_EV(E500, BRANCHES_FINISHED) \ __PMC_EV(E500, TAKEN_BRANCHES_FINISHED) \ __PMC_EV(E500, FINISHED_UNCOND_BRANCHES_MISS_BTB) \ __PMC_EV(E500, BRANCH_MISPRED) \ __PMC_EV(E500, BTB_BRANCH_MISPRED_FROM_DIRECTION) \ __PMC_EV(E500, BTB_HITS_PSEUDO_HITS) \ __PMC_EV(E500, CYCLES_DECODE_STALLED) \ __PMC_EV(E500, CYCLES_ISSUE_STALLED) \ __PMC_EV(E500, CYCLES_BRANCH_ISSUE_STALLED) \ __PMC_EV(E500, CYCLES_SU1_SCHED_STALLED) \ __PMC_EV(E500, CYCLES_SU2_SCHED_STALLED) \ __PMC_EV(E500, CYCLES_MU_SCHED_STALLED) \ __PMC_EV(E500, CYCLES_LRU_SCHED_STALLED) \ __PMC_EV(E500, CYCLES_BU_SCHED_STALLED) \ __PMC_EV(E500, TOTAL_TRANSLATED) \ __PMC_EV(E500, LOADS_TRANSLATED) \ __PMC_EV(E500, STORES_TRANSLATED) \ __PMC_EV(E500, TOUCHES_TRANSLATED) \ __PMC_EV(E500, CACHEOPS_TRANSLATED) \ __PMC_EV(E500, CACHE_INHIBITED_ACCESS_TRANSLATED) \ __PMC_EV(E500, GUARDED_LOADS_TRANSLATED) \ __PMC_EV(E500, WRITE_THROUGH_STORES_TRANSLATED) \ __PMC_EV(E500, MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED) \ __PMC_EV(E500, TOTAL_ALLOCATED_TO_DLFB) \ __PMC_EV(E500, LOADS_TRANSLATED_ALLOCATED_TO_DLFB) \ __PMC_EV(E500, STORES_COMPLETED_ALLOCATED_TO_DLFB) \ __PMC_EV(E500, TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB) \ __PMC_EV(E500, STORES_COMPLETED) \ __PMC_EV(E500, DATA_L1_CACHE_LOCKS) \ __PMC_EV(E500, DATA_L1_CACHE_RELOADS) \ __PMC_EV(E500, DATA_L1_CACHE_CASTOUTS) \ __PMC_EV(E500, LOAD_MISS_DLFB_FULL) \ __PMC_EV(E500, LOAD_MISS_LDQ_FULL) \ __PMC_EV(E500, LOAD_GUARDED_MISS) \ __PMC_EV(E500, STORE_TRANSLATE_WHEN_QUEUE_FULL) \ __PMC_EV(E500, ADDRESS_COLLISION) \ __PMC_EV(E500, DATA_MMU_MISS) \ __PMC_EV(E500, DATA_MMU_BUSY) \ __PMC_EV(E500, PART2_MISALIGNED_CACHE_ACCESS) \ __PMC_EV(E500, LOAD_MISS_DLFB_FULL_CYCLES) \ __PMC_EV(E500, LOAD_MISS_LDQ_FULL_CYCLES) \ __PMC_EV(E500, LOAD_GUARDED_MISS_CYCLES) \ __PMC_EV(E500, STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES) \ __PMC_EV(E500, ADDRESS_COLLISION_CYCLES) \ __PMC_EV(E500, DATA_MMU_MISS_CYCLES) \ __PMC_EV(E500, DATA_MMU_BUSY_CYCLES) \ __PMC_EV(E500, PART2_MISALIGNED_CACHE_ACCESS_CYCLES) \ __PMC_EV(E500, INSTR_L1_CACHE_LOCKS) \ __PMC_EV(E500, INSTR_L1_CACHE_RELOADS) \ __PMC_EV(E500, INSTR_L1_CACHE_FETCHES) \ __PMC_EV(E500, INSTR_MMU_TLB4K_RELOADS) \ __PMC_EV(E500, INSTR_MMU_VSP_RELOADS) \ __PMC_EV(E500, DATA_MMU_TLB4K_RELOADS) \ __PMC_EV(E500, DATA_MMU_VSP_RELOADS) \ __PMC_EV(E500, L2MMU_MISSES) \ __PMC_EV(E500, BIU_MASTER_REQUESTS) \ __PMC_EV(E500, BIU_MASTER_INSTR_SIDE_REQUESTS) \ __PMC_EV(E500, BIU_MASTER_DATA_SIDE_REQUESTS) \ __PMC_EV(E500, BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS) \ __PMC_EV(E500, BIU_MASTER_RETRIES) \ __PMC_EV(E500, SNOOP_REQUESTS) \ __PMC_EV(E500, SNOOP_HITS) \ __PMC_EV(E500, SNOOP_PUSHES) \ __PMC_EV(E500, SNOOP_RETRIES) \ __PMC_EV(E500, DLFB_LOAD_MISS_CYCLES) \ __PMC_EV(E500, ILFB_FETCH_MISS_CYCLES) \ __PMC_EV(E500, EXT_INPU_INTR_LATENCY_CYCLES) \ __PMC_EV(E500, CRIT_INPUT_INTR_LATENCY_CYCLES) \ __PMC_EV(E500, EXT_INPUT_INTR_PENDING_LATENCY_CYCLES) \ __PMC_EV(E500, CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES) \ __PMC_EV(E500, PMC0_OVERFLOW) \ __PMC_EV(E500, PMC1_OVERFLOW) \ __PMC_EV(E500, PMC2_OVERFLOW) \ __PMC_EV(E500, PMC3_OVERFLOW) \ __PMC_EV(E500, INTERRUPTS_TAKEN) \ __PMC_EV(E500, EXT_INPUT_INTR_TAKEN) \ __PMC_EV(E500, CRIT_INPUT_INTR_TAKEN) \ __PMC_EV(E500, SYSCALL_TRAP_INTR) \ __PMC_EV(E500, TLB_BIT_TRANSITIONS) \ __PMC_EV(E500, L2_LINEFILL_BUFFER) \ __PMC_EV(E500, LV2_VS) \ __PMC_EV(E500, CASTOUTS_RELEASED) \ __PMC_EV(E500, INTV_ALLOCATIONS) \ __PMC_EV(E500, DLFB_RETRIES_TO_MBAR) \ __PMC_EV(E500, STORE_RETRIES) \ __PMC_EV(E500, STASH_L1_HITS) \ __PMC_EV(E500, STASH_L2_HITS) \ __PMC_EV(E500, STASH_BUSY_1) \ __PMC_EV(E500, STASH_BUSY_2) \ __PMC_EV(E500, STASH_BUSY_3) \ __PMC_EV(E500, STASH_HITS) \ __PMC_EV(E500, STASH_HIT_DLFB) \ __PMC_EV(E500, STASH_REQUESTS) \ __PMC_EV(E500, STASH_REQUESTS_L1) \ __PMC_EV(E500, STASH_REQUESTS_L2) \ __PMC_EV(E500, STALLS_NO_CAQ_OR_COB) \ __PMC_EV(E500, L2_CACHE_ACCESSES) \ __PMC_EV(E500, L2_HIT_CACHE_ACCESSES) \ __PMC_EV(E500, L2_CACHE_DATA_ACCESSES) \ __PMC_EV(E500, L2_CACHE_DATA_HITS) \ __PMC_EV(E500, L2_CACHE_INSTR_ACCESSES) \ __PMC_EV(E500, L2_CACHE_INSTR_HITS) \ __PMC_EV(E500, L2_CACHE_ALLOCATIONS) \ __PMC_EV(E500, L2_CACHE_DATA_ALLOCATIONS) \ __PMC_EV(E500, L2_CACHE_DIRTY_DATA_ALLOCATIONS) \ __PMC_EV(E500, L2_CACHE_INSTR_ALLOCATIONS) \ __PMC_EV(E500, L2_CACHE_UPDATES) \ __PMC_EV(E500, L2_CACHE_CLEAN_UPDATES) \ __PMC_EV(E500, L2_CACHE_DIRTY_UPDATES) \ __PMC_EV(E500, L2_CACHE_CLEAN_REDUNDANT_UPDATES) \ __PMC_EV(E500, L2_CACHE_DIRTY_REDUNDANT_UPDATES) \ __PMC_EV(E500, L2_CACHE_LOCKS) \ __PMC_EV(E500, L2_CACHE_CASTOUTS) \ __PMC_EV(E500, L2_CACHE_DATA_DIRTY_HITS) \ __PMC_EV(E500, INSTR_LFB_WENT_HIGH_PRIORITY) \ __PMC_EV(E500, SNOOP_THROTTLING_TURNED_ON) \ __PMC_EV(E500, L2_CLEAN_LINE_INVALIDATIONS) \ __PMC_EV(E500, L2_INCOHERENT_LINE_INVALIDATIONS) \ __PMC_EV(E500, L2_COHERENT_LINE_INVALIDATIONS) \ __PMC_EV(E500, COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES) \ __PMC_EV(E500, IAC1S_DETECTED) \ __PMC_EV(E500, IAC2S_DETECTED) \ __PMC_EV(E500, DAC1S_DTECTED) \ __PMC_EV(E500, DAC2S_DTECTED) \ __PMC_EV(E500, DVT0_DETECTED) \ __PMC_EV(E500, DVT1_DETECTED) \ __PMC_EV(E500, DVT2_DETECTED) \ __PMC_EV(E500, DVT3_DETECTED) \ __PMC_EV(E500, DVT4_DETECTED) \ __PMC_EV(E500, DVT5_DETECTED) \ __PMC_EV(E500, DVT6_DETECTED) \ __PMC_EV(E500, DVT7_DETECTED) \ __PMC_EV(E500, CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL) \ __PMC_EV(E500, FPU_DOUBLE_PUMP) \ __PMC_EV(E500, FPU_FINISH) \ __PMC_EV(E500, FPU_DIVIDE_CYCLES) \ __PMC_EV(E500, FPU_DENORM_INPUT_CYCLES) \ __PMC_EV(E500, FPU_RESULT_STALL_CYCLES) \ __PMC_EV(E500, FPU_FPSCR_FULL_STALL) \ __PMC_EV(E500, FPU_PIPE_SYNC_STALLS) \ __PMC_EV(E500, FPU_INPUT_DATA_STALLS) \ __PMC_EV(E500, DECORATED_LOADS) \ __PMC_EV(E500, DECORATED_STORES) \ __PMC_EV(E500, LOAD_RETRIES) \ __PMC_EV(E500, STWCX_SUCCESSES) \ __PMC_EV(E500, STWCX_FAILURES) \ #define PMC_EV_E500_FIRST PMC_EV_E500_CYCLES #define PMC_EV_E500_LAST PMC_EV_E500_STWCX_FAILURES /* * All known PMC events. * * PMC event numbers are allocated sparsely to allow new PMC events to * be added to a PMC class without breaking ABI compatibility. The * current allocation scheme is: * * START #EVENTS DESCRIPTION * 0 0x1000 Reserved * 0x1000 0x0001 TSC * 0x2000 0x0080 AMD K7 events * 0x2080 0x0100 AMD K8 events * 0x10000 0x0080 INTEL architectural fixed-function events * 0x10080 0x0F80 INTEL architectural programmable events * 0x11000 0x0080 INTEL Pentium 4 events * 0x11080 0x0080 INTEL Pentium MMX events * 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events * 0x11200 0x00FF INTEL XScale events * 0x11300 0x00FF MIPS 24K events * 0x11400 0x00FF Octeon events * 0x11500 0x00FF MIPS 74K events * 0x13000 0x00FF MPC7450 events * 0x13100 0x00FF IBM PPC970 events * 0x13300 0x00FF Freescale e500 events * 0x14000 0x0100 ARMv7 events * 0x14100 0x0100 ARMv8 events * 0x20000 0x1000 Software events */ #define __PMC_EVENTS() \ __PMC_EV_BLOCK(TSC, 0x01000) \ __PMC_EV_TSC() \ + __PMC_EV_BLOCK(IAF, 0x10000) \ + __PMC_EV_IAF() \ __PMC_EV_BLOCK(K7, 0x2000) \ __PMC_EV_K7() \ - __PMC_EV_BLOCK(K8, 0x2080) \ + __PMC_EV_BLOCK(K8, 0x2080) \ __PMC_EV_K8() \ - __PMC_EV_BLOCK(IAF, 0x10000) \ - __PMC_EV_IAF() \ - __PMC_EV_BLOCK(IAP, 0x10080) \ - __PMC_EV_IAP() \ - __PMC_EV_BLOCK(P4, 0x11000) \ - __PMC_EV_P4() \ - __PMC_EV_BLOCK(P5, 0x11080) \ - __PMC_EV_P5() \ - __PMC_EV_BLOCK(P6, 0x11100) \ - __PMC_EV_P6() \ __PMC_EV_BLOCK(XSCALE, 0x11200) \ __PMC_EV_XSCALE() \ __PMC_EV_BLOCK(MIPS24K, 0x11300) \ __PMC_EV_MIPS24K() \ __PMC_EV_BLOCK(OCTEON, 0x11400) \ __PMC_EV_OCTEON() \ - __PMC_EV_BLOCK(MIPS74K, 0x11500) \ + __PMC_EV_BLOCK(MIPS74K, 0x11500) \ __PMC_EV_MIPS74K() \ - __PMC_EV_BLOCK(UCF, 0x12000) \ - __PMC_EV_UCF() \ - __PMC_EV_BLOCK(UCP, 0x12080) \ + __PMC_EV_BLOCK(UCP, 0x12080) \ __PMC_EV_UCP() \ __PMC_EV_BLOCK(PPC7450, 0x13000) \ __PMC_EV_PPC7450() \ __PMC_EV_BLOCK(PPC970, 0x13100) \ __PMC_EV_PPC970() \ __PMC_EV_BLOCK(E500, 0x13300) \ __PMC_EV_E500() \ __PMC_EV_BLOCK(ARMV7, 0x14000) \ __PMC_EV_ARMV7() \ __PMC_EV_BLOCK(ARMV8, 0x14100) \ __PMC_EV_ARMV8() #define PMC_EVENT_FIRST PMC_EV_TSC_TSC #define PMC_EVENT_LAST PMC_EV_SOFT_LAST #endif /* _DEV_HWPMC_PMC_EVENTS_H_ */ diff --git a/sys/i386/include/pmc_mdep.h b/sys/i386/include/pmc_mdep.h index 9b874ebabcf4..8ea7a0f9e120 100644 --- a/sys/i386/include/pmc_mdep.h +++ b/sys/i386/include/pmc_mdep.h @@ -1,179 +1,167 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2003-2005,2008 Joseph Koshy * Copyright (c) 2007 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by A. Joseph Koshy under * sponsorship from the FreeBSD Foundation and Google, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_PMC_MDEP_H #define _MACHINE_PMC_MDEP_H 1 #ifdef _KERNEL struct pmc_mdep; #endif /* * On the i386 platform we support the following PMCs. * * TSC The timestamp counter * K7 AMD Athlon XP/MP and other 32 bit processors. * K8 AMD Athlon64 and Opteron PMCs in 32 bit mode. * PIV Intel P4/HTT and P4/EMT64 * PPRO Intel Pentium Pro, Pentium-II, Pentium-III, Celeron and * Pentium-M processors * PENTIUM Intel Pentium MMX. * IAP Intel Core/Core2/Atom programmable PMCs. * IAF Intel fixed-function PMCs. * UCP Intel Uncore programmable PMCs. * UCF Intel Uncore fixed-function PMCs. */ #include /* K7 and K8 */ #include -#include -#include -#include #include #include /* * Intel processors implementing V2 and later of the Intel performance * measurement architecture have PMCs of the following classes: TSC, * IAF, IAP, UCF and UCP. */ #define PMC_MDEP_CLASS_INDEX_TSC 1 #define PMC_MDEP_CLASS_INDEX_K7 2 #define PMC_MDEP_CLASS_INDEX_K8 2 -#define PMC_MDEP_CLASS_INDEX_P4 2 -#define PMC_MDEP_CLASS_INDEX_P5 2 -#define PMC_MDEP_CLASS_INDEX_P6 2 #define PMC_MDEP_CLASS_INDEX_IAP 2 #define PMC_MDEP_CLASS_INDEX_IAF 3 #define PMC_MDEP_CLASS_INDEX_UCP 4 #define PMC_MDEP_CLASS_INDEX_UCF 5 /* * Architecture specific extensions to structures. */ union pmc_md_op_pmcallocate { struct pmc_md_amd_op_pmcallocate pm_amd; struct pmc_md_iaf_op_pmcallocate pm_iaf; struct pmc_md_iap_op_pmcallocate pm_iap; struct pmc_md_ucf_op_pmcallocate pm_ucf; struct pmc_md_ucp_op_pmcallocate pm_ucp; - struct pmc_md_p4_op_pmcallocate pm_p4; - struct pmc_md_pentium_op_pmcallocate pm_pentium; - struct pmc_md_ppro_op_pmcallocate pm_ppro; uint64_t __pad[4]; }; /* Logging */ #define PMCLOG_READADDR PMCLOG_READ32 #define PMCLOG_EMITADDR PMCLOG_EMIT32 #ifdef _KERNEL /* MD extension for 'struct pmc' */ union pmc_md_pmc { struct pmc_md_amd_pmc pm_amd; struct pmc_md_iaf_pmc pm_iaf; struct pmc_md_iap_pmc pm_iap; struct pmc_md_ucf_pmc pm_ucf; struct pmc_md_ucp_pmc pm_ucp; - struct pmc_md_p4_pmc pm_p4; - struct pmc_md_pentium_pmc pm_pentium; - struct pmc_md_ppro_pmc pm_ppro; }; struct pmc; struct pmc_mdep; #define PMC_TRAPFRAME_TO_PC(TF) ((TF)->tf_eip) #define PMC_TRAPFRAME_TO_FP(TF) ((TF)->tf_ebp) /* * The layout of the stack frame on entry into the NMI handler depends on * whether a privilege level change (and consequent stack switch) was * required for entry. * * When processing an interrupt when in user mode, the processor switches * stacks, and saves the user mode stack pointer on the kernel stack. The * user mode stack pointer is then available to the interrupt handler * at frame->tf_esp. * * When processing an interrupt while in kernel mode, the processor * continues to use the existing (kernel) stack. Therefore we determine * the stack pointer for the interrupted kernel procedure by adding an * offset to the current frame pointer. */ #define PMC_TRAPFRAME_TO_USER_SP(TF) ((TF)->tf_esp) #define PMC_TRAPFRAME_TO_KERNEL_SP(TF) ((uintptr_t) &((TF)->tf_esp)) #define PMC_IN_KERNEL_STACK(S,START,END) \ ((S) >= (START) && (S) < (END)) #define PMC_IN_KERNEL(va) INKERNEL(va) #define PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS) #define PMC_IN_TRAP_HANDLER(PC) \ ((PC) >= (uintptr_t)start_exceptions + setidt_disp && \ (PC) < (uintptr_t) end_exceptions + setidt_disp) #define PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(I) \ (((I) & 0x00ffffff) == 0xe58955) /* pushl %ebp; movl %esp,%ebp */ #define PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(I) \ (((I) & 0x0000ffff) == 0xe589) /* movl %esp,%ebp */ #define PMC_AT_FUNCTION_EPILOGUE_RET(I) \ (((I) & 0xFF) == 0xC3) /* ret */ /* Build a fake kernel trapframe from current instruction pointer. */ #define PMC_FAKE_TRAPFRAME(TF) \ do { \ (TF)->tf_cs = 0; (TF)->tf_eflags = 0; \ __asm __volatile("movl %%ebp,%0" : "=r" ((TF)->tf_ebp)); \ __asm __volatile("movl %%esp,%0" : "=r" ((TF)->tf_esp)); \ __asm __volatile("call 1f \n\t1: pop %0" : "=r"((TF)->tf_eip)); \ } while (0) /* * Prototypes */ void start_exceptions(void), end_exceptions(void); struct pmc_mdep *pmc_amd_initialize(void); void pmc_amd_finalize(struct pmc_mdep *_md); struct pmc_mdep *pmc_intel_initialize(void); void pmc_intel_finalize(struct pmc_mdep *_md); #endif /* _KERNEL */ #endif /* _MACHINE_PMC_MDEP_H */ diff --git a/sys/modules/hwpmc/Makefile b/sys/modules/hwpmc/Makefile index 1db7a661c09c..df5422808c24 100644 --- a/sys/modules/hwpmc/Makefile +++ b/sys/modules/hwpmc/Makefile @@ -1,39 +1,39 @@ # # $FreeBSD$ # .PATH: ${SRCTOP}/sys/dev/hwpmc KMOD= hwpmc SRCS= hwpmc_mod.c hwpmc_logging.c hwpmc_soft.c vnode_if.h .if ${MACHINE_CPUARCH} == "aarch64" SRCS+= hwpmc_arm64.c hwpmc_arm64_md.c .endif .if ${MACHINE_CPUARCH} == "amd64" -SRCS+= hwpmc_amd.c hwpmc_core.c hwpmc_intel.c hwpmc_piv.c hwpmc_tsc.c +SRCS+= hwpmc_amd.c hwpmc_core.c hwpmc_intel.c hwpmc_tsc.c SRCS+= hwpmc_x86.c hwpmc_uncore.c SRCS+= device_if.h bus_if.h .endif .if ${MACHINE_CPUARCH} == "arm" SRCS+= hwpmc_arm.c .endif .if ${MACHINE_CPUARCH} == "i386" -SRCS+= hwpmc_amd.c hwpmc_core.c hwpmc_intel.c hwpmc_piv.c hwpmc_ppro.c -SRCS+= hwpmc_pentium.c hwpmc_tsc.c hwpmc_x86.c hwpmc_uncore.c +SRCS+= hwpmc_amd.c hwpmc_core.c hwpmc_intel.c +SRCS+= hwpmc_tsc.c hwpmc_x86.c hwpmc_uncore.c SRCS+= device_if.h bus_if.h .endif .if ${MACHINE_CPUARCH} == "powerpc" SRCS+= hwpmc_powerpc.c hwpmc_e500.c hwpmc_mpc7xxx.c hwpmc_ppc970.c .endif .if ${MACHINE_CPUARCH} == "sparc64" SRCS+= hwpmc_sparc64.c .endif .include