diff --git a/sys/dev/ichiic/ig4_pci.c b/sys/dev/ichiic/ig4_pci.c index ec27e95b2556..203c962fa304 100644 --- a/sys/dev/ichiic/ig4_pci.c +++ b/sys/dev/ichiic/ig4_pci.c @@ -1,241 +1,231 @@ /* * Copyright (c) 2014 The DragonFly Project. All rights reserved. * * This code is derived from software contributed to The DragonFly Project * by Matthew Dillon and was subsequently ported * to FreeBSD by Michael Gmelin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Intel fourth generation mobile cpus integrated I2C device. * * See ig4_reg.h for datasheet reference and notes. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static int ig4iic_pci_detach(device_t dev); #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 #define PCI_CHIP_BRASWELL_I2C_1 0x22c18086 #define PCI_CHIP_BRASWELL_I2C_2 0x22c28086 #define PCI_CHIP_BRASWELL_I2C_3 0x22c38086 #define PCI_CHIP_BRASWELL_I2C_5 0x22c58086 #define PCI_CHIP_BRASWELL_I2C_6 0x22c68086 #define PCI_CHIP_BRASWELL_I2C_7 0x22c78086 #define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086 #define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086 #define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086 #define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086 #define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086 #define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086 +#define PCI_CHIP_APL_I2C_0 0x5aac8086 +#define PCI_CHIP_APL_I2C_1 0x5aae8086 +#define PCI_CHIP_APL_I2C_2 0x5ab08086 +#define PCI_CHIP_APL_I2C_3 0x5ab28086 +#define PCI_CHIP_APL_I2C_4 0x5ab48086 +#define PCI_CHIP_APL_I2C_5 0x5ab68086 +#define PCI_CHIP_APL_I2C_6 0x5ab88086 +#define PCI_CHIP_APL_I2C_7 0x5aba8086 + +struct ig4iic_pci_device { + uint32_t devid; + const char *desc; + enum ig4_vers version; +}; + +static struct ig4iic_pci_device ig4iic_pci_devices[] = { + { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL}, + { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL}, + { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM}, + { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM}, + { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM}, + { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM}, + { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM}, + { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM}, + { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE}, + { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE}, + { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE}, + { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE}, + { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE}, + { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE}, + { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_SKYLAKE}, + { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_SKYLAKE}, + { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_SKYLAKE}, + { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_SKYLAKE}, + { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_SKYLAKE}, + { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_SKYLAKE}, + { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_SKYLAKE}, + { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_SKYLAKE}, + { 0, NULL, 0 }, +}; static int ig4iic_pci_probe(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); - - switch(pci_get_devid(dev)) { - case PCI_CHIP_LYNXPT_LP_I2C_1: - device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-1"); - sc->version = IG4_HASWELL; - break; - case PCI_CHIP_LYNXPT_LP_I2C_2: - device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-2"); - sc->version = IG4_HASWELL; - break; - case PCI_CHIP_BRASWELL_I2C_1: - device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 1"); - sc->version = IG4_ATOM; - break; - case PCI_CHIP_BRASWELL_I2C_2: - device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 2"); - sc->version = IG4_ATOM; - break; - case PCI_CHIP_BRASWELL_I2C_3: - device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 3"); - sc->version = IG4_ATOM; - break; - case PCI_CHIP_BRASWELL_I2C_5: - device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 5"); - sc->version = IG4_ATOM; - break; - case PCI_CHIP_BRASWELL_I2C_6: - device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 6"); - sc->version = IG4_ATOM; - break; - case PCI_CHIP_BRASWELL_I2C_7: - device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 7"); - sc->version = IG4_ATOM; - break; - case PCI_CHIP_SKYLAKE_I2C_0: - device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-0"); - sc->version = IG4_SKYLAKE; - break; - case PCI_CHIP_SKYLAKE_I2C_1: - device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-1"); - sc->version = IG4_SKYLAKE; - break; - case PCI_CHIP_SKYLAKE_I2C_2: - device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-2"); - sc->version = IG4_SKYLAKE; - break; - case PCI_CHIP_SKYLAKE_I2C_3: - device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-3"); - sc->version = IG4_SKYLAKE; - break; - case PCI_CHIP_SKYLAKE_I2C_4: - device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-4"); - sc->version = IG4_SKYLAKE; - break; - case PCI_CHIP_SKYLAKE_I2C_5: - device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-5"); - sc->version = IG4_SKYLAKE; - break; - default: - return (ENXIO); + uint32_t devid; + int i; + + devid = pci_get_devid(dev); + for (i = 0; ig4iic_pci_devices[i].devid != 0; i++) { + if (ig4iic_pci_devices[i].devid == devid) { + device_set_desc(dev, ig4iic_pci_devices[i].desc); + sc->version = ig4iic_pci_devices[i].version; + return (BUS_PROBE_DEFAULT); + } } - return (BUS_PROBE_DEFAULT); + return (ENXIO); } static int ig4iic_pci_attach(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); int error; sc->dev = dev; sc->regs_rid = PCIR_BAR(0); sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regs_rid, RF_ACTIVE); if (sc->regs_res == NULL) { device_printf(dev, "unable to map registers\n"); ig4iic_pci_detach(dev); return (ENXIO); } sc->intr_rid = 0; if (pci_alloc_msi(dev, &sc->intr_rid)) { device_printf(dev, "Using MSI\n"); } sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); if (sc->intr_res == NULL) { device_printf(dev, "unable to map interrupt\n"); ig4iic_pci_detach(dev); return (ENXIO); } sc->platform_attached = 1; error = ig4iic_attach(sc); if (error) ig4iic_pci_detach(dev); return (error); } static int ig4iic_pci_detach(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); int error; if (sc->platform_attached) { error = ig4iic_detach(sc); if (error) return (error); sc->platform_attached = 0; } if (sc->intr_res) { bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, sc->intr_res); sc->intr_res = NULL; } if (sc->intr_rid != 0) pci_release_msi(dev); if (sc->regs_res) { bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, sc->regs_res); sc->regs_res = NULL; } return (0); } static device_method_t ig4iic_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ig4iic_pci_probe), DEVMETHOD(device_attach, ig4iic_pci_attach), DEVMETHOD(device_detach, ig4iic_pci_detach), DEVMETHOD(iicbus_transfer, ig4iic_transfer), DEVMETHOD(iicbus_reset, ig4iic_reset), DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD_END }; static driver_t ig4iic_pci_driver = { "ig4iic_pci", ig4iic_pci_methods, sizeof(struct ig4iic_softc) }; static devclass_t ig4iic_pci_devclass; DRIVER_MODULE_ORDERED(ig4iic_pci, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0, SI_ORDER_ANY); MODULE_DEPEND(ig4iic_pci, pci, 1, 1, 1); MODULE_DEPEND(ig4iic_pci, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); MODULE_VERSION(ig4iic_pci, 1); diff --git a/sys/dev/ichiic/ig4_var.h b/sys/dev/ichiic/ig4_var.h index c1007762f6c5..635ec550c133 100644 --- a/sys/dev/ichiic/ig4_var.h +++ b/sys/dev/ichiic/ig4_var.h @@ -1,111 +1,111 @@ /* * Copyright (c) 2014 The DragonFly Project. All rights reserved. * * This code is derived from software contributed to The DragonFly Project * by Matthew Dillon and was subsequently ported * to FreeBSD by Michael Gmelin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _ICHIIC_IG4_VAR_H_ #define _ICHIIC_IG4_VAR_H_ #include "bus_if.h" #include "device_if.h" #include "pci_if.h" #include "iicbus_if.h" #define IG4_RBUFSIZE 128 #define IG4_RBUFMASK (IG4_RBUFSIZE - 1) enum ig4_op { IG4_IDLE, IG4_READ, IG4_WRITE }; -enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE }; +enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL }; struct ig4iic_softc { device_t dev; struct intr_config_hook enum_hook; device_t iicbus; struct resource *regs_res; int regs_rid; struct resource *intr_res; int intr_rid; void *intr_handle; int intr_type; enum ig4_vers version; enum ig4_op op; int cmd; int rnext; int rpos; char rbuf[IG4_RBUFSIZE]; int error; uint8_t last_slave; int platform_attached : 1; int use_10bit : 1; int slave_valid : 1; int read_started : 1; int write_started : 1; /* * Locking semantics: * * Functions implementing the icbus interface that interact * with the controller acquire an exclusive lock on call_lock * to prevent interleaving of calls to the interface and a lock on * io_lock right afterwards, to synchronize controller I/O activity. * * The interrupt handler can only read data while no iicbus call * is in progress or while io_lock is dropped during mtx_sleep in * wait_status and set_controller. It is safe to drop io_lock in those * places, because the interrupt handler only accesses those registers: * * - IG4_REG_I2C_STA (I2C Status) * - IG4_REG_DATA_CMD (Data Buffer and Command) * - IG4_REG_CLR_INTR (Clear Interrupt) * * Locking outside of those places is required to make the content * of rpos/rnext predictable (e.g. whenever data_read is called and in * ig4iic_transfer). */ struct sx call_lock; struct mtx io_lock; }; typedef struct ig4iic_softc ig4iic_softc_t; /* Attach/Detach called from ig4iic_pci_*() */ int ig4iic_attach(ig4iic_softc_t *sc); int ig4iic_detach(ig4iic_softc_t *sc); /* iicbus methods */ extern iicbus_transfer_t ig4iic_transfer; extern iicbus_reset_t ig4iic_reset; #endif /* _ICHIIC_IG4_VAR_H_ */