diff --git a/usr.sbin/bhyve/uart_backend.c b/usr.sbin/bhyve/uart_backend.c index 8d91f4f671e1..51844cbf1170 100644 --- a/usr.sbin/bhyve/uart_backend.c +++ b/usr.sbin/bhyve/uart_backend.c @@ -1,348 +1,368 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2012 NetApp, Inc. * Copyright (c) 2013 Neel Natu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include +#include #include #include #include #include #include #include #include "debug.h" #include "mevent.h" #include "uart_backend.h" struct ttyfd { bool opened; int rfd; /* fd for reading */ int wfd; /* fd for writing, may be == rfd */ }; #define FIFOSZ 16 struct fifo { uint8_t buf[FIFOSZ]; int rindex; /* index to read from */ int windex; /* index to write to */ int num; /* number of characters in the fifo */ int size; /* size of the fifo */ }; struct uart_softc { struct ttyfd tty; struct fifo rxfifo; struct mevent *mev; + pthread_mutex_t mtx; }; static bool uart_stdio; /* stdio in use for i/o */ static struct termios tio_stdio_orig; static void ttyclose(void) { tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig); } static void ttyopen(struct ttyfd *tf) { struct termios orig, new; tcgetattr(tf->rfd, &orig); new = orig; cfmakeraw(&new); new.c_cflag |= CLOCAL; tcsetattr(tf->rfd, TCSANOW, &new); if (uart_stdio) { tio_stdio_orig = orig; atexit(ttyclose); } raw_stdio = 1; } static int ttyread(struct ttyfd *tf) { unsigned char rb; if (read(tf->rfd, &rb, 1) == 1) return (rb); else return (-1); } static void ttywrite(struct ttyfd *tf, unsigned char wb) { (void)write(tf->wfd, &wb, 1); } static bool rxfifo_available(struct uart_softc *sc) { return (sc->rxfifo.num < sc->rxfifo.size); } int uart_rxfifo_getchar(struct uart_softc *sc) { struct fifo *fifo; int c, error, wasfull; wasfull = 0; fifo = &sc->rxfifo; if (fifo->num > 0) { if (!rxfifo_available(sc)) wasfull = 1; c = fifo->buf[fifo->rindex]; fifo->rindex = (fifo->rindex + 1) % fifo->size; fifo->num--; if (wasfull) { if (sc->tty.opened) { error = mevent_enable(sc->mev); assert(error == 0); } } return (c); } else return (-1); } int uart_rxfifo_numchars(struct uart_softc *sc) { return (sc->rxfifo.num); } static int rxfifo_putchar(struct uart_softc *sc, uint8_t ch) { struct fifo *fifo; int error; fifo = &sc->rxfifo; if (fifo->num < fifo->size) { fifo->buf[fifo->windex] = ch; fifo->windex = (fifo->windex + 1) % fifo->size; fifo->num++; if (!rxfifo_available(sc)) { if (sc->tty.opened) { /* * Disable mevent callback if the FIFO is full. */ error = mevent_disable(sc->mev); assert(error == 0); } } return (0); } else return (-1); } void uart_rxfifo_drain(struct uart_softc *sc, bool loopback) { int ch; if (loopback) { (void)ttyread(&sc->tty); } else { while (rxfifo_available(sc) && ((ch = ttyread(&sc->tty)) != -1)) rxfifo_putchar(sc, ch); } } int uart_rxfifo_putchar(struct uart_softc *sc, uint8_t ch, bool loopback) { if (loopback) { return (rxfifo_putchar(sc, ch)); } else if (sc->tty.opened) { ttywrite(&sc->tty, ch); return (0); } else { /* Drop on the floor. */ return (0); } } void uart_rxfifo_reset(struct uart_softc *sc, int size) { char flushbuf[32]; struct fifo *fifo; ssize_t nread; int error; fifo = &sc->rxfifo; bzero(fifo, sizeof(struct fifo)); fifo->size = size; if (sc->tty.opened) { /* * Flush any unread input from the tty buffer. */ while (1) { nread = read(sc->tty.rfd, flushbuf, sizeof(flushbuf)); if (nread != sizeof(flushbuf)) break; } /* * Enable mevent to trigger when new characters are available * on the tty fd. */ error = mevent_enable(sc->mev); assert(error == 0); } } int uart_rxfifo_size(struct uart_softc *sc __unused) { return (FIFOSZ); } #ifdef BHYVE_SNAPSHOT int uart_rxfifo_snapshot(struct uart_softc *sc, struct vm_snapshot_meta *meta) { int ret; SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.rindex, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.windex, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.num, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.size, meta, ret, done); SNAPSHOT_BUF_OR_LEAVE(sc->rxfifo.buf, sizeof(sc->rxfifo.buf), meta, ret, done); done: return (ret); } #endif static int uart_stdio_backend(struct uart_softc *sc) { #ifndef WITHOUT_CAPSICUM cap_rights_t rights; cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ }; #endif if (uart_stdio) return (-1); sc->tty.rfd = STDIN_FILENO; sc->tty.wfd = STDOUT_FILENO; sc->tty.opened = true; if (fcntl(sc->tty.rfd, F_SETFL, O_NONBLOCK) != 0) return (-1); if (fcntl(sc->tty.wfd, F_SETFL, O_NONBLOCK) != 0) return (-1); #ifndef WITHOUT_CAPSICUM cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ); if (caph_rights_limit(sc->tty.rfd, &rights) == -1) errx(EX_OSERR, "Unable to apply rights for sandbox"); if (caph_ioctls_limit(sc->tty.rfd, cmds, nitems(cmds)) == -1) errx(EX_OSERR, "Unable to apply rights for sandbox"); #endif uart_stdio = true; return (0); } static int uart_tty_backend(struct uart_softc *sc, const char *path) { #ifndef WITHOUT_CAPSICUM cap_rights_t rights; cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ }; #endif int fd; fd = open(path, O_RDWR | O_NONBLOCK); if (fd < 0) return (-1); if (!isatty(fd)) { close(fd); return (-1); } sc->tty.rfd = sc->tty.wfd = fd; sc->tty.opened = true; #ifndef WITHOUT_CAPSICUM cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ, CAP_WRITE); if (caph_rights_limit(fd, &rights) == -1) errx(EX_OSERR, "Unable to apply rights for sandbox"); if (caph_ioctls_limit(fd, cmds, nitems(cmds)) == -1) errx(EX_OSERR, "Unable to apply rights for sandbox"); #endif return (0); } struct uart_softc * uart_init(void) { - return (calloc(1, sizeof(struct uart_softc))); + struct uart_softc *sc = calloc(1, sizeof(struct uart_softc)); + if (sc == NULL) + return (NULL); + + pthread_mutex_init(&sc->mtx, NULL); + + return (sc); } int uart_tty_open(struct uart_softc *sc, const char *path, void (*drain)(int, enum ev_type, void *), void *arg) { int retval; if (strcmp("stdio", path) == 0) retval = uart_stdio_backend(sc); else retval = uart_tty_backend(sc, path); if (retval == 0) { ttyopen(&sc->tty); sc->mev = mevent_add(sc->tty.rfd, EVF_READ, drain, arg); assert(sc->mev != NULL); } return (retval); } + +void +uart_softc_lock(struct uart_softc *sc) +{ + pthread_mutex_lock(&sc->mtx); +} + +void +uart_softc_unlock(struct uart_softc *sc) +{ + pthread_mutex_unlock(&sc->mtx); +} diff --git a/usr.sbin/bhyve/uart_backend.h b/usr.sbin/bhyve/uart_backend.h index fa7949ad6d1c..ecf785ffd893 100644 --- a/usr.sbin/bhyve/uart_backend.h +++ b/usr.sbin/bhyve/uart_backend.h @@ -1,55 +1,56 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2012 NetApp, Inc. * Copyright (c) 2013 Neel Natu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef _UART_BACKEND_H_ #define _UART_BACKEND_H_ #include #include "mevent.h" struct uart_softc; struct vm_snapshot_meta; void uart_rxfifo_drain(struct uart_softc *sc, bool loopback); int uart_rxfifo_getchar(struct uart_softc *sc); int uart_rxfifo_numchars(struct uart_softc *sc); int uart_rxfifo_putchar(struct uart_softc *sc, uint8_t ch, bool loopback); void uart_rxfifo_reset(struct uart_softc *sc, int size); int uart_rxfifo_size(struct uart_softc *sc); #ifdef BHYVE_SNAPSHOT int uart_rxfifo_snapshot(struct uart_softc *sc, struct vm_snapshot_meta *meta); #endif struct uart_softc *uart_init(void); int uart_tty_open(struct uart_softc *sc, const char *path, void (*drain)(int, enum ev_type, void *), void *arg); - +void uart_softc_lock(struct uart_softc *sc); +void uart_softc_unlock(struct uart_softc *sc); #endif /* _UART_BACKEND_H_ */ diff --git a/usr.sbin/bhyve/uart_emul.c b/usr.sbin/bhyve/uart_emul.c index 58d6697e4fea..bc71d4760634 100644 --- a/usr.sbin/bhyve/uart_emul.c +++ b/usr.sbin/bhyve/uart_emul.c @@ -1,488 +1,485 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2012 NetApp, Inc. * Copyright (c) 2013 Neel Natu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include "uart_backend.h" #include "uart_emul.h" #define COM1_BASE 0x3F8 #define COM1_IRQ 4 #define COM2_BASE 0x2F8 #define COM2_IRQ 3 #define COM3_BASE 0x3E8 #define COM3_IRQ 4 #define COM4_BASE 0x2E8 #define COM4_IRQ 3 #define DEFAULT_RCLK 1843200 #define DEFAULT_BAUD 115200 #define FCR_RX_MASK 0xC0 #define MCR_OUT1 0x04 #define MCR_OUT2 0x08 #define MSR_DELTA_MASK 0x0f #ifndef REG_SCR #define REG_SCR com_scr #endif static struct { int baseaddr; int irq; bool inuse; } uart_lres[] = { { COM1_BASE, COM1_IRQ, false}, { COM2_BASE, COM2_IRQ, false}, { COM3_BASE, COM3_IRQ, false}, { COM4_BASE, COM4_IRQ, false}, }; #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0])) struct uart_ns16550_softc { struct uart_softc *backend; - pthread_mutex_t mtx; /* protects all softc elements */ uint8_t data; /* Data register (R/W) */ uint8_t ier; /* Interrupt enable register (R/W) */ uint8_t lcr; /* Line control register (R/W) */ uint8_t mcr; /* Modem control register (R/W) */ uint8_t lsr; /* Line status register (R/W) */ uint8_t msr; /* Modem status register (R/W) */ uint8_t fcr; /* FIFO control register (W) */ uint8_t scr; /* Scratch register (R/W) */ uint8_t dll; /* Baudrate divisor latch LSB */ uint8_t dlh; /* Baudrate divisor latch MSB */ bool thre_int_pending; /* THRE interrupt pending */ void *arg; uart_intr_func_t intr_assert; uart_intr_func_t intr_deassert; }; static uint8_t modem_status(uint8_t mcr) { uint8_t msr; if (mcr & MCR_LOOPBACK) { /* * In the loopback mode certain bits from the MCR are * reflected back into MSR. */ msr = 0; if (mcr & MCR_RTS) msr |= MSR_CTS; if (mcr & MCR_DTR) msr |= MSR_DSR; if (mcr & MCR_OUT1) msr |= MSR_RI; if (mcr & MCR_OUT2) msr |= MSR_DCD; } else { /* * Always assert DCD and DSR so tty open doesn't block * even if CLOCAL is turned off. */ msr = MSR_DCD | MSR_DSR; } assert((msr & MSR_DELTA_MASK) == 0); return (msr); } /* * The IIR returns a prioritized interrupt reason: * - receive data available * - transmit holding register empty * - modem status change * * Return an interrupt reason if one is available. */ static int uart_intr_reason(struct uart_ns16550_softc *sc) { if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0) return (IIR_RLS); else if (uart_rxfifo_numchars(sc->backend) > 0 && (sc->ier & IER_ERXRDY) != 0) return (IIR_RXTOUT); else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0) return (IIR_TXRDY); else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0) return (IIR_MLSC); else return (IIR_NOPEND); } static void uart_reset(struct uart_ns16550_softc *sc) { uint16_t divisor; divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16; sc->dll = divisor; sc->dlh = divisor >> 16; sc->msr = modem_status(sc->mcr); uart_rxfifo_reset(sc->backend, 1); } /* * Toggle the COM port's intr pin depending on whether or not we have an * interrupt condition to report to the processor. */ static void uart_toggle_intr(struct uart_ns16550_softc *sc) { uint8_t intr_reason; intr_reason = uart_intr_reason(sc); if (intr_reason == IIR_NOPEND) (*sc->intr_deassert)(sc->arg); else (*sc->intr_assert)(sc->arg); } static void uart_drain(int fd __unused, enum ev_type ev, void *arg) { struct uart_ns16550_softc *sc; bool loopback; sc = arg; assert(ev == EVF_READ); /* * This routine is called in the context of the mevent thread * to take out the softc lock to protect against concurrent * access from a vCPU i/o exit */ - pthread_mutex_lock(&sc->mtx); + uart_softc_lock(sc->backend); loopback = (sc->mcr & MCR_LOOPBACK) != 0; uart_rxfifo_drain(sc->backend, loopback); if (!loopback) uart_toggle_intr(sc); - pthread_mutex_unlock(&sc->mtx); + uart_softc_unlock(sc->backend); } void uart_ns16550_write(struct uart_ns16550_softc *sc, int offset, uint8_t value) { int fifosz; uint8_t msr; - pthread_mutex_lock(&sc->mtx); + uart_softc_lock(sc->backend); /* * Take care of the special case DLAB accesses first */ if ((sc->lcr & LCR_DLAB) != 0) { if (offset == REG_DLL) { sc->dll = value; goto done; } if (offset == REG_DLH) { sc->dlh = value; goto done; } } switch (offset) { case REG_DATA: if (uart_rxfifo_putchar(sc->backend, value, (sc->mcr & MCR_LOOPBACK) != 0)) sc->lsr |= LSR_OE; sc->thre_int_pending = true; break; case REG_IER: /* Set pending when IER_ETXRDY is raised (edge-triggered). */ if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0) sc->thre_int_pending = true; /* * Apply mask so that bits 4-7 are 0 * Also enables bits 0-3 only if they're 1 */ sc->ier = value & 0x0F; break; case REG_FCR: /* * When moving from FIFO and 16450 mode and vice versa, * the FIFO contents are reset. */ if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) { fifosz = (value & FCR_ENABLE) ? uart_rxfifo_size(sc->backend) : 1; uart_rxfifo_reset(sc->backend, fifosz); } /* * The FCR_ENABLE bit must be '1' for the programming * of other FCR bits to be effective. */ if ((value & FCR_ENABLE) == 0) { sc->fcr = 0; } else { if ((value & FCR_RCV_RST) != 0) uart_rxfifo_reset(sc->backend, uart_rxfifo_size(sc->backend)); sc->fcr = value & (FCR_ENABLE | FCR_DMA | FCR_RX_MASK); } break; case REG_LCR: sc->lcr = value; break; case REG_MCR: /* Apply mask so that bits 5-7 are 0 */ sc->mcr = value & 0x1F; msr = modem_status(sc->mcr); /* * Detect if there has been any change between the * previous and the new value of MSR. If there is * then assert the appropriate MSR delta bit. */ if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS)) sc->msr |= MSR_DCTS; if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR)) sc->msr |= MSR_DDSR; if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD)) sc->msr |= MSR_DDCD; if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0) sc->msr |= MSR_TERI; /* * Update the value of MSR while retaining the delta * bits. */ sc->msr &= MSR_DELTA_MASK; sc->msr |= msr; break; case REG_LSR: /* * Line status register is not meant to be written to * during normal operation. */ break; case REG_MSR: /* * As far as I can tell MSR is a read-only register. */ break; case REG_SCR: sc->scr = value; break; default: break; } done: uart_toggle_intr(sc); - pthread_mutex_unlock(&sc->mtx); + uart_softc_unlock(sc->backend); } uint8_t uart_ns16550_read(struct uart_ns16550_softc *sc, int offset) { uint8_t iir, intr_reason, reg; - pthread_mutex_lock(&sc->mtx); + uart_softc_lock(sc->backend); /* * Take care of the special case DLAB accesses first */ if ((sc->lcr & LCR_DLAB) != 0) { if (offset == REG_DLL) { reg = sc->dll; goto done; } if (offset == REG_DLH) { reg = sc->dlh; goto done; } } switch (offset) { case REG_DATA: reg = uart_rxfifo_getchar(sc->backend); break; case REG_IER: reg = sc->ier; break; case REG_IIR: iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0; intr_reason = uart_intr_reason(sc); /* * Deal with side effects of reading the IIR register */ if (intr_reason == IIR_TXRDY) sc->thre_int_pending = false; iir |= intr_reason; reg = iir; break; case REG_LCR: reg = sc->lcr; break; case REG_MCR: reg = sc->mcr; break; case REG_LSR: /* Transmitter is always ready for more data */ sc->lsr |= LSR_TEMT | LSR_THRE; /* Check for new receive data */ if (uart_rxfifo_numchars(sc->backend) > 0) sc->lsr |= LSR_RXRDY; else sc->lsr &= ~LSR_RXRDY; reg = sc->lsr; /* The LSR_OE bit is cleared on LSR read */ sc->lsr &= ~LSR_OE; break; case REG_MSR: /* * MSR delta bits are cleared on read */ reg = sc->msr; sc->msr &= ~MSR_DELTA_MASK; break; case REG_SCR: reg = sc->scr; break; default: reg = 0xFF; break; } done: uart_toggle_intr(sc); - pthread_mutex_unlock(&sc->mtx); + uart_softc_unlock(sc->backend); return (reg); } int uart_legacy_alloc(int which, int *baseaddr, int *irq) { if (which < 0 || which >= (int)UART_NLDEVS || uart_lres[which].inuse) return (-1); uart_lres[which].inuse = true; *baseaddr = uart_lres[which].baseaddr; *irq = uart_lres[which].irq; return (0); } struct uart_ns16550_softc * uart_ns16550_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert, void *arg) { struct uart_ns16550_softc *sc; sc = calloc(1, sizeof(struct uart_ns16550_softc)); sc->arg = arg; sc->intr_assert = intr_assert; sc->intr_deassert = intr_deassert; sc->backend = uart_init(); - pthread_mutex_init(&sc->mtx, NULL); - uart_reset(sc); return (sc); } int uart_ns16550_tty_open(struct uart_ns16550_softc *sc, const char *device) { return (uart_tty_open(sc->backend, device, uart_drain, sc)); } #ifdef BHYVE_SNAPSHOT int uart_ns16550_snapshot(struct uart_ns16550_softc *sc, struct vm_snapshot_meta *meta) { int ret; SNAPSHOT_VAR_OR_LEAVE(sc->data, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->ier, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->lcr, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->mcr, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->lsr, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->msr, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->fcr, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->scr, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->dll, meta, ret, done); SNAPSHOT_VAR_OR_LEAVE(sc->dlh, meta, ret, done); ret = uart_rxfifo_snapshot(sc->backend, meta); sc->thre_int_pending = 1; done: return (ret); } #endif diff --git a/usr.sbin/bhyve/uart_pl011.c b/usr.sbin/bhyve/uart_pl011.c index e2d5c8bf5657..fb576451c544 100644 --- a/usr.sbin/bhyve/uart_pl011.c +++ b/usr.sbin/bhyve/uart_pl011.c @@ -1,394 +1,390 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2020 Andrew Turner * * This work was supported by Innovate UK project 105694, "Digital Security * by Design (DSbD) Technology Platform Prototype". * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include -#include #include #include #include #include "uart_backend.h" #include "uart_emul.h" #define UART_FIFO_SIZE 16 #define UARTDR 0x00 #define UARTDR_RSR_SHIFT 8 #define UARTRSR 0x01 #define UARTRSR_OE (1 << 3) #define UARTFR 0x06 #define UARTFR_TXFE (1 << 7) #define UARTFR_RXFF (1 << 6) #define UARTFR_TXFF (1 << 5) #define UARTFR_RXFE (1 << 4) #define UARTRTINTR (1 << 6) #define UARTTXINTR (1 << 5) #define UARTRXINTR (1 << 4) #define UARTIBRD 0x09 #define UARTFBRD 0x0a #define UARTFBRD_MASK 0x003f #define UARTLCR_H 0x0b #define UARTLCR_H_MASK 0x00ff #define UARTLCR_H_FEN (1 << 4) #define UARTCR 0x0c /* TODO: Check the flags in the UARTCR register */ #define UARTCR_MASK 0xffc7 #define UARTCR_LBE (1 << 7) #define UARTIFLS 0x0d #define UARTIFLS_MASK 0x003f #define UARTIFLS_RXIFLSEL(x) (((x) >> 3) & 0x7) #define UARTIFLS_TXIFLSEL(x) (((x) >> 0) & 0x7) #define UARTIMSC 0x0e #define UARTIMSC_MASK 0x07ff #define UARTRIS 0x0f #define UARTMIS 0x10 #define UARTICR 0x11 #define UARTPeriphID 0x00241011 #define UARTPeriphID0 0x3f8 #define UARTPeriphID0_VAL (((UARTPeriphID) >> 0) & 0xff) #define UARTPeriphID1 0x3f9 #define UARTPeriphID1_VAL (((UARTPeriphID) >> 8) & 0xff) #define UARTPeriphID2 0x3fa #define UARTPeriphID2_VAL (((UARTPeriphID) >> 16) & 0xff) #define UARTPeriphID3 0x3fb #define UARTPeriphID3_VAL (((UARTPeriphID) >> 24) & 0xff) #define UARTPCellID 0xb105f00d #define UARTPCellID0 0x3fc #define UARTPCellID0_VAL (((UARTPCellID) >> 0) & 0xff) #define UARTPCellID1 0x3fd #define UARTPCellID1_VAL (((UARTPCellID) >> 8) & 0xff) #define UARTPCellID2 0x3fe #define UARTPCellID2_VAL (((UARTPCellID) >> 16) & 0xff) #define UARTPCellID3 0x3ff #define UARTPCellID3_VAL (((UARTPCellID) >> 24) & 0xff) struct uart_pl011_softc { struct uart_softc *backend; - pthread_mutex_t mtx; /* protects all softc elements */ uint16_t irq_state; uint16_t rsr; uint16_t cr; uint16_t ifls; uint16_t imsc; uint16_t lcr_h; uint16_t ibrd; uint16_t fbrd; void *arg; uart_intr_func_t intr_assert; uart_intr_func_t intr_deassert; }; static void uart_reset(struct uart_pl011_softc *sc) { sc->ifls = 0x12; /* no fifo until enabled by software */ uart_rxfifo_reset(sc->backend, 1); } static int uart_rx_trigger_level(struct uart_pl011_softc *sc) { /* If the FIFO is disabled trigger when we have any data */ if ((sc->lcr_h & UARTLCR_H_FEN) != 0) return (1); /* Trigger base on how full the fifo is */ switch (UARTIFLS_RXIFLSEL(sc->ifls)) { case 0: return (UART_FIFO_SIZE / 8); case 1: return (UART_FIFO_SIZE / 4); case 2: return (UART_FIFO_SIZE / 2); case 3: return (UART_FIFO_SIZE * 3 / 4); case 4: return (UART_FIFO_SIZE * 7 / 8); default: /* TODO: Find out what happens in this case */ return (UART_FIFO_SIZE); } } static void uart_toggle_intr(struct uart_pl011_softc *sc) { if ((sc->irq_state & sc->imsc) == 0) (*sc->intr_deassert)(sc->arg); else (*sc->intr_assert)(sc->arg); } static void uart_drain(int fd __unused, enum ev_type ev, void *arg) { struct uart_pl011_softc *sc; int old_size, trig_lvl; bool loopback; sc = arg; assert(ev == EVF_READ); /* * This routine is called in the context of the mevent thread * to take out the softc lock to protect against concurrent * access from a vCPU i/o exit */ - pthread_mutex_lock(&sc->mtx); + uart_softc_lock(sc->backend); old_size = uart_rxfifo_numchars(sc->backend); loopback = (sc->cr & UARTCR_LBE) != 0; uart_rxfifo_drain(sc->backend, loopback); /* If we cross the trigger level raise UARTRXINTR */ trig_lvl = uart_rx_trigger_level(sc); if (old_size < trig_lvl && uart_rxfifo_numchars(sc->backend) >= trig_lvl) sc->irq_state |= UARTRXINTR; if (uart_rxfifo_numchars(sc->backend) > 0) sc->irq_state |= UARTRTINTR; if (!loopback) uart_toggle_intr(sc); - pthread_mutex_unlock(&sc->mtx); + uart_softc_unlock(sc->backend); } void uart_pl011_write(struct uart_pl011_softc *sc, int offset, uint32_t value) { bool loopback; - pthread_mutex_lock(&sc->mtx); + uart_softc_lock(sc->backend); switch (offset) { case UARTDR: loopback = (sc->cr & UARTCR_LBE) != 0; if (uart_rxfifo_putchar(sc->backend, value & 0xff, loopback)) sc->rsr |= UARTRSR_OE; /* We don't have a TX fifo, so trigger when we have data */ sc->irq_state |= UARTTXINTR; break; case UARTRSR: /* Any write clears this register */ sc->rsr = 0; break; case UARTFR: /* UARTFR is a read-only register */ break; /* TODO: UARTILPR */ case UARTIBRD: sc->ibrd = value; break; case UARTFBRD: sc->fbrd = value & UARTFBRD_MASK; break; case UARTLCR_H: /* Check if the FIFO enable bit changed */ if (((sc->lcr_h ^ value) & UARTLCR_H_FEN) != 0) { if ((value & UARTLCR_H_FEN) != 0) { uart_rxfifo_reset(sc->backend, UART_FIFO_SIZE); } else { uart_rxfifo_reset(sc->backend, 1); } } sc->lcr_h = value & UARTLCR_H_MASK; break; case UARTCR: sc->cr = value & UARTCR_MASK; break; case UARTIFLS: sc->ifls = value & UARTCR_MASK; break; case UARTIMSC: sc->imsc = value & UARTIMSC_MASK; break; case UARTRIS: case UARTMIS: /* UARTRIS and UARTMIS are read-only registers */ break; case UARTICR: sc->irq_state &= ~value; break; default: /* Ignore writes to unassigned/ID registers */ break; } uart_toggle_intr(sc); - pthread_mutex_unlock(&sc->mtx); + uart_softc_unlock(sc->backend); } uint32_t uart_pl011_read(struct uart_pl011_softc *sc, int offset) { uint32_t reg; int fifo_sz; reg = 0; - pthread_mutex_lock(&sc->mtx); + uart_softc_lock(sc->backend); switch (offset) { case UARTDR: reg = uart_rxfifo_getchar(sc->backend); /* Deassert the irq if below the trigger level */ fifo_sz = uart_rxfifo_numchars(sc->backend); if (fifo_sz < uart_rx_trigger_level(sc)) sc->irq_state &= ~UARTRXINTR; if (fifo_sz == 0) sc->irq_state &= ~UARTRTINTR; reg |= sc->rsr << UARTDR_RSR_SHIFT; /* After reading from the fifo there is now space in it */ sc->rsr &= UARTRSR_OE; break; case UARTRSR: /* Any write clears this register */ reg = sc->rsr; break; case UARTFR: /* Transmit is intstant, so the fifo is always empty */ reg = UARTFR_TXFE; /* Set the receive fifo full/empty flags */ fifo_sz = uart_rxfifo_numchars(sc->backend); if (fifo_sz == UART_FIFO_SIZE) reg |= UARTFR_RXFF; else if (fifo_sz == 0) reg |= UARTFR_RXFE; break; /* TODO: UARTILPR */ case UARTIBRD: reg = sc->ibrd; break; case UARTFBRD: reg = sc->fbrd; break; case UARTLCR_H: reg = sc->lcr_h; break; case UARTCR: reg = sc->cr; break; case UARTIMSC: reg = sc->imsc; break; case UARTRIS: reg = sc->irq_state; break; case UARTMIS: reg = sc->irq_state & sc->imsc; break; case UARTICR: reg = 0; break; case UARTPeriphID0: reg = UARTPeriphID0_VAL; break; case UARTPeriphID1: reg =UARTPeriphID1_VAL; break; case UARTPeriphID2: reg = UARTPeriphID2_VAL; break; case UARTPeriphID3: reg = UARTPeriphID3_VAL; break; case UARTPCellID0: reg = UARTPCellID0_VAL; break; case UARTPCellID1: reg = UARTPCellID1_VAL; break; case UARTPCellID2: reg = UARTPCellID2_VAL; break; case UARTPCellID3: reg = UARTPCellID3_VAL; break; default: /* Return 0 in reads from unasigned registers */ reg = 0; break; } uart_toggle_intr(sc); - pthread_mutex_unlock(&sc->mtx); + uart_softc_unlock(sc->backend); return (reg); } struct uart_pl011_softc * uart_pl011_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert, void *arg) { struct uart_pl011_softc *sc; sc = calloc(1, sizeof(struct uart_pl011_softc)); sc->arg = arg; sc->intr_assert = intr_assert; sc->intr_deassert = intr_deassert; sc->backend = uart_init(); - pthread_mutex_init(&sc->mtx, NULL); - uart_reset(sc); return (sc); } int uart_pl011_tty_open(struct uart_pl011_softc *sc, const char *device) { return (uart_tty_open(sc->backend, device, uart_drain, sc)); }