diff --git a/sys/dev/pci/pcivar.h b/sys/dev/pci/pcivar.h index b164e4e5eb53..f624678e4f32 100644 --- a/sys/dev/pci/pcivar.h +++ b/sys/dev/pci/pcivar.h @@ -1,204 +1,210 @@ #ifndef PCI_COMPAT #define PCI_COMPAT #endif /* * Copyright (c) 1997, Stefan Esser * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: pcivar.h,v 1.17 1997/08/21 07:05:54 fsmp Exp $ + * $Id: pcivar.h,v 1.18 1997/08/21 08:31:41 fsmp Exp $ * */ /* some PCI bus constants */ #define PCI_BUSMAX 255 /* highest supported bus number */ #define PCI_SLOTMAX 31 /* highest supported slot number */ #define PCI_FUNCMAX 7 /* highest supported function number */ #define PCI_REGMAX 255 /* highest supported config register addr. */ #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ #ifdef PCI_A64 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ #else typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ #endif /* map register information */ typedef struct { u_int32_t base; u_int8_t type; #define PCI_MAPMEM 0x01 /* memory map */ #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ #define PCI_MAPPORT 0x04 /* port map */ u_int8_t ln2size; u_int8_t ln2range; /* u_int8_t dummy;*/ } pcimap; /* config header information common to all header types */ typedef struct pcicfg { struct pcicfg *parent; struct pcicfg *next; pcimap *map; /* pointer to array of PCI maps */ void *hdrspec; /* pointer to header type specific data */ u_int16_t subvendor; /* card vendor ID */ u_int16_t subdevice; /* card device ID, assigned by card vendor */ u_int16_t vendor; /* chip vendor ID */ u_int16_t device; /* chip device ID, assigned by chip vendor */ u_int16_t cmdreg; /* disable/enable chip and PCI options */ u_int16_t statreg; /* supported PCI features and error state */ u_int8_t class; /* chip PCI class */ u_int8_t subclass; /* chip PCI subclass */ u_int8_t progif; /* chip PCI programming interface */ u_int8_t revid; /* chip revision ID */ u_int8_t hdrtype; /* chip config header type */ u_int8_t cachelnsz; /* cache line size in 4byte units */ u_int8_t intpin; /* PCI interrupt pin */ u_int8_t intline; /* interrupt line (IRQ for PC arch) */ u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ u_int8_t nummaps; /* actual number of PCI maps used */ u_int8_t bus; /* config space bus address */ u_int8_t slot; /* config space slot address */ u_int8_t func; /* config space function number */ u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ } pcicfgregs; /* additional type 1 device config header information (PCI to PCI bridge) */ #ifdef PCI_A64 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) #else #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) #endif /* PCI_A64 */ #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) typedef struct { pci_addr_t pmembase; /* base address of prefetchable memory */ pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ u_int32_t membase; /* base address of memory window */ u_int32_t memlimit; /* topmost address of memory window */ u_int32_t iobase; /* base address of port window */ u_int32_t iolimit; /* topmost address of port window */ u_int16_t secstat; /* secondary bus status register */ u_int16_t bridgectl; /* bridge control register */ u_int8_t seclat; /* CardBus latency timer */ } pcih1cfgregs; /* additional type 2 device config header information (CardBus bridge) */ typedef struct { u_int32_t membase0; /* base address of memory window */ u_int32_t memlimit0; /* topmost address of memory window */ u_int32_t membase1; /* base address of memory window */ u_int32_t memlimit1; /* topmost address of memory window */ u_int32_t iobase0; /* base address of port window */ u_int32_t iolimit0; /* topmost address of port window */ u_int32_t iobase1; /* base address of port window */ u_int32_t iolimit1; /* topmost address of port window */ u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ u_int16_t secstat; /* secondary bus status register */ u_int16_t bridgectl; /* bridge control register */ u_int8_t seclat; /* CardBus latency timer */ } pcih2cfgregs; /* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ typedef struct pciattach { int unit; int pcibushigh; struct pciattach *next; } pciattach; /* externally visible functions */ int pci_probe (pciattach *attach); void pci_drvattach(pcicfgregs *cfg); /* low level PCI config register functions provided by pcibus.c */ int pci_cfgopen (void); int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); /* for compatibility to FreeBSD-2.2 version of PCI code */ #ifdef PCI_COMPAT typedef pcicfgregs *pcici_t; typedef unsigned pcidi_t; typedef void pci_inthand_t(void *arg); #define pci_max_burst_len (3) /* just copied from old PCI code for now ... */ extern struct linker_set pcidevice_set; extern int pci_mechanism; struct pci_device { char* pd_name; char* (*pd_probe ) (pcici_t tag, pcidi_t type); void (*pd_attach) (pcici_t tag, int unit); u_long *pd_count; int (*pd_shutdown) (int, int); }; struct pci_lkm { struct pci_device *dvp; struct pci_lkm *next; }; +#ifdef __i386__ +typedef u_short pci_port_t; +#else +typedef u_int pci_port_t; +#endif + u_long pci_conf_read (pcici_t tag, u_long reg); void pci_conf_write (pcici_t tag, u_long reg, u_long data); void pci_configure (void); -int pci_map_port (pcici_t tag, u_long reg, u_short* pa); +int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr); int pci_unmap_int (pcici_t tag); int pci_register_lkm (struct pci_device *dvp, int if_revision); #endif /* PCI_COMPAT */ diff --git a/sys/pci/pci_compat.c b/sys/pci/pci_compat.c index 8499fcf0115f..9fbf3ee8fdd8 100644 --- a/sys/pci/pci_compat.c +++ b/sys/pci/pci_compat.c @@ -1,405 +1,412 @@ /* * Copyright (c) 1997, Stefan Esser * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: pci_compat.c,v 1.6 1997/08/21 08:42:59 fsmp Exp $ + * $Id: pci_compat.c,v 1.7 1998/04/01 21:07:37 tegge Exp $ * */ #include "pci.h" #if NPCI > 0 /* for compatibility to FreeBSD-2.2 version of PCI code */ #include #include #include #include /* for DATA_SET support */ #include #include #include #include #include #ifdef RESOURCE_CHECK #include #endif #ifdef PCI_COMPAT /* ------------------------------------------------------------------------- */ static int pci_mapno(pcicfgregs *cfg, int reg) { int map = -1; - if ((reg & 0x03) == 0) { map = (reg -0x10) / 4; if (map < 0 || map >= cfg->nummaps) map = -1; } return (map); } static int pci_porten(pcicfgregs *cfg) { return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0); } static int pci_isportmap(pcicfgregs *cfg, int map) { return ((unsigned)map < cfg->nummaps && (cfg->map[map].type & PCI_MAPPORT) != 0); } static int pci_memen(pcicfgregs *cfg) { return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0); } static int pci_ismemmap(pcicfgregs *cfg, int map) { return ((unsigned)map < cfg->nummaps && (cfg->map[map].type & PCI_MAPMEM) != 0); } /* ------------------------------------------------------------------------- */ u_long pci_conf_read(pcici_t tag, u_long reg) { return (pci_cfgread(tag, reg, 4)); } void pci_conf_write(pcici_t tag, u_long reg, u_long data) { pci_cfgwrite(tag, reg, data, 4); } -int pci_map_port(pcici_t cfg, u_long reg, u_short* pa) +int pci_map_port(pcici_t cfg, u_long reg, pci_port_t* pa) { int map; map = pci_mapno(cfg, reg); if (pci_porten(cfg) && pci_isportmap(cfg, map)) { u_int32_t iobase; u_int32_t iosize; iobase = cfg->map[map].base; iosize = 1 << cfg->map[map].ln2size; #ifdef RESOURCE_CHECK if (resource_claim(cfg, REST_PORT, RESF_NONE, iobase, iobase + iosize -1) == 0) #endif /* RESOURCE_CHECK */ { *pa = iobase; return (1); } } return (0); } int pci_map_mem(pcici_t cfg, u_long reg, vm_offset_t* va, vm_offset_t* pa) { int map; map = pci_mapno(cfg, reg); if (pci_memen(cfg) && pci_ismemmap(cfg, map)) { u_int32_t paddr; u_int32_t psize; paddr = cfg->map[map].base; psize = 1 << cfg->map[map].ln2size; #ifdef RESOURCE_CHECK if (resource_claim(cfg, REST_MEM, RESF_NONE, paddr, paddr + psize -1) == 0) #endif /* RESOURCE_CHECK */ { u_int32_t poffs; vm_offset_t vaddr; poffs = paddr - trunc_page(paddr); +#ifdef __i386__ vaddr = (vm_offset_t)pmap_mapdev(paddr-poffs, psize+poffs); +#endif +#ifdef __alpha__ + /* XXX should talk to chipset. + Hardwire pyxis for now */ + vaddr = ALPHA_PHYS_TO_K0SEG(0x8600000000L + + paddr-poffs); +#endif if (vaddr != NULL) { vaddr += poffs; *va = vaddr; *pa = paddr; return (1); } } } return (0); } int pci_map_int(pcici_t cfg, pci_inthand_t *func, void *arg, unsigned *maskptr) { int error; #ifdef APIC_IO int nextpin, muxcnt; #endif if (cfg->intpin != 0) { int irq = cfg->intline; void *dev_instance = (void *)-1; /* XXX use cfg->devdata */ void *idesc; idesc = intr_create(dev_instance, irq, func, arg, maskptr, 0); error = intr_connect(idesc); if (error != 0) return 0; #ifdef APIC_IO nextpin = next_apic_pin(irq); if (nextpin < 0) return 1; /* * Attempt handling of some broken mp tables. * * It's OK to yell (since the mp tables are broken). * * Hanging in the boot is not OK */ muxcnt = 2; nextpin = next_apic_pin(nextpin); while (muxcnt < 5 && nextpin >= 0) { muxcnt++; nextpin = next_apic_pin(nextpin); } if (muxcnt >= 5) { printf("bogus MP table, more than 4 IO APIC pins connected to the same PCI device or ISA/EISA interrupt\n"); return 0; } printf("bogus MP table, %d IO APIC pins connected to the same PCI device or ISA/EISA interrupt\n", muxcnt); nextpin = next_apic_pin(irq); while (nextpin >= 0) { idesc = intr_create(dev_instance, nextpin, func, arg, maskptr, 0); error = intr_connect(idesc); if (error != 0) return 0; printf("Registered extra interrupt handler for int %d (in addition to int %d)\n", nextpin, irq); nextpin = next_apic_pin(nextpin); } #endif } return (1); } int pci_unmap_int(pcici_t cfg) { return (0); /* not supported, yet, since cfg doesn't know about idesc */ } /* ------------------------------------------------------------------------- */ /* * Preliminary support for "wired" PCI devices. * This code supports currently only devices on PCI bus 0, since the * mapping from PCI BIOS bus numbers to configuration file bus numbers * is not yet maintained, whenever a PCI to PCI bridge is found. * The "bus" field of "pciwirecfg" correlates an PCI bus with the bridge * it is attached to. The "biosbus" field is to be updated for each bus, * whose bridge is probed. An entry with bus != 0 and biosbus == 0 is * invalid and will be skipped in the search for a wired unit, but not * in the test for a free unit number. */ typedef struct { char *name; int unit; u_int8_t bus; u_int8_t slot; u_int8_t func; u_int8_t biosbus; } pciwirecfg; static pciwirecfg pci_wireddevs[] = { /* driver, unit, bus, slot, func, BIOS bus */ #ifdef PCI_DEBUG { "ncr", 2, 1, 4, 0, 0 }, { "ed", 2, 1, 5, 0, 0 }, #endif /* PCI_DEBUG */ /* do not delete the end marker that follows this comment !!! */ { NULL } }; /* return unit number of wired device, or -1 if no match */ static int pci_wiredunit(pcicfgregs *cfg, char *name) { pciwirecfg *p; p = pci_wireddevs; while (p->name != NULL) { if (p->bus == cfg->bus && p->slot == cfg->slot && p->func == cfg->func && strcmp(p->name, name) == 0) return (p->unit); p++; } return (-1); } /* return free unit number equal or greater to the one supplied as parameter */ static int pci_freeunit(pcicfgregs *cfg, char *name, int unit) { pciwirecfg *p; p = pci_wireddevs; while (p->name != NULL) { if (p->unit == unit && strcmp(p->name, name) == 0) { p = pci_wireddevs; unit++; } else { p++; } } return (unit); } static char *drvname; static char* pci_probedrv(pcicfgregs *cfg, struct pci_device *dvp) { if (dvp && dvp->pd_probe) { pcidi_t type = (cfg->device << 16) + cfg->vendor; return (dvp->pd_probe(cfg, type)); } return (NULL); } static struct pci_lkm *pci_lkm_head; static struct pci_device* pci_finddrv(pcicfgregs *cfg) { struct pci_device **dvpp; struct pci_device *dvp = NULL; struct pci_lkm *lkm; drvname = NULL; lkm = pci_lkm_head; while (drvname == NULL && lkm != NULL) { dvp = lkm->dvp; drvname = pci_probedrv(cfg, dvp); lkm = lkm->next; } dvpp = (struct pci_device **)pcidevice_set.ls_items; while (drvname == NULL && (dvp = *dvpp++) != NULL) drvname = pci_probedrv(cfg, dvp); return (dvp); } static void pci_drvmessage(pcicfgregs *cfg, char *name, int unit) { if (drvname == NULL || *drvname == '\0') return; printf("%s%d: <%s> rev 0x%02x", name, unit, drvname, cfg->revid); if (cfg->intpin != 0) printf(" int %c irq %d", cfg->intpin + 'a' -1, cfg->intline); printf(" on pci%d.%d.%d\n", cfg->bus, cfg->slot, cfg->func); } void pci_drvattach(pcicfgregs *cfg) { struct pci_device *dvp; dvp = pci_finddrv(cfg); if (dvp != NULL) { int unit; unit = pci_wiredunit(cfg, dvp->pd_name); if (unit < 0) { unit = pci_freeunit(cfg, dvp->pd_name, *dvp->pd_count); *dvp->pd_count = unit +1; } pci_drvmessage(cfg, dvp->pd_name, unit); if (dvp->pd_attach) dvp->pd_attach(cfg, unit); } } /* ------------------------------------------------------------------------- */ static void pci_rescan(void) { /* XXX do nothing, currently, soon to come ... */ } int pci_register_lkm (struct pci_device *dvp, int if_revision) { struct pci_lkm *lkm; if (if_revision != 0) { return (-1); } if (dvp == NULL || dvp->pd_probe == NULL || dvp->pd_attach == NULL) { return (-1); } lkm = malloc (sizeof (*lkm), M_DEVBUF, M_WAITOK); if (lkm != NULL) { return (-1); } lkm->dvp = dvp; lkm->next = pci_lkm_head; pci_lkm_head = lkm; pci_rescan(); return (0); } void pci_configure(void) { pci_probe(NULL); } /* ------------------------------------------------------------------------- */ #endif /* PCI_COMPAT */ #endif /* NPCI > 0 */ diff --git a/sys/pci/pcivar.h b/sys/pci/pcivar.h index b164e4e5eb53..f624678e4f32 100644 --- a/sys/pci/pcivar.h +++ b/sys/pci/pcivar.h @@ -1,204 +1,210 @@ #ifndef PCI_COMPAT #define PCI_COMPAT #endif /* * Copyright (c) 1997, Stefan Esser * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: pcivar.h,v 1.17 1997/08/21 07:05:54 fsmp Exp $ + * $Id: pcivar.h,v 1.18 1997/08/21 08:31:41 fsmp Exp $ * */ /* some PCI bus constants */ #define PCI_BUSMAX 255 /* highest supported bus number */ #define PCI_SLOTMAX 31 /* highest supported slot number */ #define PCI_FUNCMAX 7 /* highest supported function number */ #define PCI_REGMAX 255 /* highest supported config register addr. */ #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ #ifdef PCI_A64 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ #else typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ #endif /* map register information */ typedef struct { u_int32_t base; u_int8_t type; #define PCI_MAPMEM 0x01 /* memory map */ #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ #define PCI_MAPPORT 0x04 /* port map */ u_int8_t ln2size; u_int8_t ln2range; /* u_int8_t dummy;*/ } pcimap; /* config header information common to all header types */ typedef struct pcicfg { struct pcicfg *parent; struct pcicfg *next; pcimap *map; /* pointer to array of PCI maps */ void *hdrspec; /* pointer to header type specific data */ u_int16_t subvendor; /* card vendor ID */ u_int16_t subdevice; /* card device ID, assigned by card vendor */ u_int16_t vendor; /* chip vendor ID */ u_int16_t device; /* chip device ID, assigned by chip vendor */ u_int16_t cmdreg; /* disable/enable chip and PCI options */ u_int16_t statreg; /* supported PCI features and error state */ u_int8_t class; /* chip PCI class */ u_int8_t subclass; /* chip PCI subclass */ u_int8_t progif; /* chip PCI programming interface */ u_int8_t revid; /* chip revision ID */ u_int8_t hdrtype; /* chip config header type */ u_int8_t cachelnsz; /* cache line size in 4byte units */ u_int8_t intpin; /* PCI interrupt pin */ u_int8_t intline; /* interrupt line (IRQ for PC arch) */ u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ u_int8_t nummaps; /* actual number of PCI maps used */ u_int8_t bus; /* config space bus address */ u_int8_t slot; /* config space slot address */ u_int8_t func; /* config space function number */ u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ } pcicfgregs; /* additional type 1 device config header information (PCI to PCI bridge) */ #ifdef PCI_A64 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) #else #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) #endif /* PCI_A64 */ #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) typedef struct { pci_addr_t pmembase; /* base address of prefetchable memory */ pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ u_int32_t membase; /* base address of memory window */ u_int32_t memlimit; /* topmost address of memory window */ u_int32_t iobase; /* base address of port window */ u_int32_t iolimit; /* topmost address of port window */ u_int16_t secstat; /* secondary bus status register */ u_int16_t bridgectl; /* bridge control register */ u_int8_t seclat; /* CardBus latency timer */ } pcih1cfgregs; /* additional type 2 device config header information (CardBus bridge) */ typedef struct { u_int32_t membase0; /* base address of memory window */ u_int32_t memlimit0; /* topmost address of memory window */ u_int32_t membase1; /* base address of memory window */ u_int32_t memlimit1; /* topmost address of memory window */ u_int32_t iobase0; /* base address of port window */ u_int32_t iolimit0; /* topmost address of port window */ u_int32_t iobase1; /* base address of port window */ u_int32_t iolimit1; /* topmost address of port window */ u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ u_int16_t secstat; /* secondary bus status register */ u_int16_t bridgectl; /* bridge control register */ u_int8_t seclat; /* CardBus latency timer */ } pcih2cfgregs; /* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ typedef struct pciattach { int unit; int pcibushigh; struct pciattach *next; } pciattach; /* externally visible functions */ int pci_probe (pciattach *attach); void pci_drvattach(pcicfgregs *cfg); /* low level PCI config register functions provided by pcibus.c */ int pci_cfgopen (void); int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); /* for compatibility to FreeBSD-2.2 version of PCI code */ #ifdef PCI_COMPAT typedef pcicfgregs *pcici_t; typedef unsigned pcidi_t; typedef void pci_inthand_t(void *arg); #define pci_max_burst_len (3) /* just copied from old PCI code for now ... */ extern struct linker_set pcidevice_set; extern int pci_mechanism; struct pci_device { char* pd_name; char* (*pd_probe ) (pcici_t tag, pcidi_t type); void (*pd_attach) (pcici_t tag, int unit); u_long *pd_count; int (*pd_shutdown) (int, int); }; struct pci_lkm { struct pci_device *dvp; struct pci_lkm *next; }; +#ifdef __i386__ +typedef u_short pci_port_t; +#else +typedef u_int pci_port_t; +#endif + u_long pci_conf_read (pcici_t tag, u_long reg); void pci_conf_write (pcici_t tag, u_long reg, u_long data); void pci_configure (void); -int pci_map_port (pcici_t tag, u_long reg, u_short* pa); +int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr); int pci_unmap_int (pcici_t tag); int pci_register_lkm (struct pci_device *dvp, int if_revision); #endif /* PCI_COMPAT */