diff --git a/contrib/llvm-project/clang/include/clang/Basic/BuiltinsAArch64.def b/contrib/llvm-project/clang/include/clang/Basic/BuiltinsAArch64.def index 634bcaed20a6..244280a68d75 100644 --- a/contrib/llvm-project/clang/include/clang/Basic/BuiltinsAArch64.def +++ b/contrib/llvm-project/clang/include/clang/Basic/BuiltinsAArch64.def @@ -1,251 +1,255 @@ //==- BuiltinsAArch64.def - AArch64 Builtin function database ----*- C++ -*-==// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines the AArch64-specific builtin function database. Users of // this file must define the BUILTIN macro to make use of this information. // //===----------------------------------------------------------------------===// // The format of this database matches clang/Basic/Builtins.def. #if defined(BUILTIN) && !defined(LANGBUILTIN) # define LANGBUILTIN(ID, TYPE, ATTRS, BUILTIN_LANG) BUILTIN(ID, TYPE, ATTRS) #endif +#if defined(BUILTIN) && !defined(TARGET_BUILTIN) +# define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS) +#endif + #if defined(BUILTIN) && !defined(TARGET_HEADER_BUILTIN) # define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANG, FEATURE) BUILTIN(ID, TYPE, ATTRS) #endif // In libgcc BUILTIN(__clear_cache, "vv*v*", "i") BUILTIN(__builtin_arm_ldrex, "v.", "t") BUILTIN(__builtin_arm_ldaex, "v.", "t") BUILTIN(__builtin_arm_strex, "i.", "t") BUILTIN(__builtin_arm_stlex, "i.", "t") BUILTIN(__builtin_arm_clrex, "v", "") // Bit manipulation BUILTIN(__builtin_arm_rbit, "UiUi", "nc") BUILTIN(__builtin_arm_rbit64, "WUiWUi", "nc") BUILTIN(__builtin_arm_cls, "UiZUi", "nc") BUILTIN(__builtin_arm_cls64, "UiWUi", "nc") // HINT BUILTIN(__builtin_arm_nop, "v", "") BUILTIN(__builtin_arm_yield, "v", "") BUILTIN(__builtin_arm_wfe, "v", "") BUILTIN(__builtin_arm_wfi, "v", "") BUILTIN(__builtin_arm_sev, "v", "") BUILTIN(__builtin_arm_sevl, "v", "") // CRC32 -BUILTIN(__builtin_arm_crc32b, "UiUiUc", "nc") -BUILTIN(__builtin_arm_crc32cb, "UiUiUc", "nc") -BUILTIN(__builtin_arm_crc32h, "UiUiUs", "nc") -BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc") -BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc") -BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc") -BUILTIN(__builtin_arm_crc32d, "UiUiWUi", "nc") -BUILTIN(__builtin_arm_crc32cd, "UiUiWUi", "nc") +TARGET_BUILTIN(__builtin_arm_crc32b, "UiUiUc", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32cb, "UiUiUc", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32h, "UiUiUs", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32d, "UiUiWUi", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32cd, "UiUiWUi", "nc", "crc") // Memory Tagging Extensions (MTE) BUILTIN(__builtin_arm_irg, "v*v*Ui", "t") BUILTIN(__builtin_arm_addg, "v*v*Ui", "t") BUILTIN(__builtin_arm_gmi, "Uiv*Ui", "t") BUILTIN(__builtin_arm_ldg, "v*v*", "t") BUILTIN(__builtin_arm_stg, "vv*", "t") BUILTIN(__builtin_arm_subp, "Uiv*v*", "t") // Memory barrier BUILTIN(__builtin_arm_dmb, "vUi", "nc") BUILTIN(__builtin_arm_dsb, "vUi", "nc") BUILTIN(__builtin_arm_isb, "vUi", "nc") BUILTIN(__builtin_arm_jcvt, "Zid", "nc") // Prefetch BUILTIN(__builtin_arm_prefetch, "vvC*UiUiUiUi", "nc") // System Registers BUILTIN(__builtin_arm_rsr, "UicC*", "nc") BUILTIN(__builtin_arm_rsr64, "WUicC*", "nc") BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc") BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc") BUILTIN(__builtin_arm_wsr64, "vcC*WUi", "nc") BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc") // MSVC LANGBUILTIN(__dmb, "vUi", "nc", ALL_MS_LANGUAGES) LANGBUILTIN(__dsb, "vUi", "nc", ALL_MS_LANGUAGES) LANGBUILTIN(__isb, "vUi", "nc", ALL_MS_LANGUAGES) LANGBUILTIN(__yield, "v", "", ALL_MS_LANGUAGES) LANGBUILTIN(__wfe, "v", "", ALL_MS_LANGUAGES) LANGBUILTIN(__wfi, "v", "", ALL_MS_LANGUAGES) LANGBUILTIN(__sev, "v", "", ALL_MS_LANGUAGES) LANGBUILTIN(__sevl, "v", "", ALL_MS_LANGUAGES) // Misc BUILTIN(__builtin_sponentry, "v*", "c") // Transactional Memory Extension BUILTIN(__builtin_arm_tstart, "WUi", "nj") BUILTIN(__builtin_arm_tcommit, "v", "n") BUILTIN(__builtin_arm_tcancel, "vWUIi", "n") BUILTIN(__builtin_arm_ttest, "WUi", "nc") // Armv8.5-A FP rounding intrinsics BUILTIN(__builtin_arm_frint32zf, "ff", "") BUILTIN(__builtin_arm_frint32z, "dd", "") BUILTIN(__builtin_arm_frint64zf, "ff", "") BUILTIN(__builtin_arm_frint64z, "dd", "") BUILTIN(__builtin_arm_frint32xf, "ff", "") BUILTIN(__builtin_arm_frint32x, "dd", "") BUILTIN(__builtin_arm_frint64xf, "ff", "") BUILTIN(__builtin_arm_frint64x, "dd", "") // Armv8.5-A Random number generation intrinsics BUILTIN(__builtin_arm_rndr, "iWUi*", "n") BUILTIN(__builtin_arm_rndrrs, "iWUi*", "n") // Armv8.7-A load/store 64-byte intrinsics BUILTIN(__builtin_arm_ld64b, "vvC*WUi*", "n") BUILTIN(__builtin_arm_st64b, "vv*WUiC*", "n") BUILTIN(__builtin_arm_st64bv, "WUiv*WUiC*", "n") BUILTIN(__builtin_arm_st64bv0, "WUiv*WUiC*", "n") TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_BitScanForward64, "UcUNi*ULLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_BitScanReverse64, "UcUNi*ULLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAdd, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement64, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeSub64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement64, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd_acq, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd_rel, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd_nf, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd16_acq, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd16_rel, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd16_nf, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange16_acq, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange16_nf, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange16_rel, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange_acq, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange_nf, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange_rel, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange8_acq, "ccD*cc", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange8_nf, "ccD*cc", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange8_rel, "ccD*cc", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange16_acq, "ssD*ss", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange16_nf, "ssD*ss", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange16_rel, "ssD*ss", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange_acq, "NiNiD*NiNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange_nf, "NiNiD*NiNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange_rel, "NiNiD*NiNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_acq, "LLiLLiD*LLiLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_nf, "LLiLLiD*LLiLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_rel, "LLiLLiD*LLiLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128, "UcLLiD*LLiLLiLLi*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128_acq,"UcLLiD*LLiLLiLLi*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128_nf ,"UcLLiD*LLiLLiLLi*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128_rel,"UcLLiD*LLiLLiLLi*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr16_acq, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr16_nf, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr16_rel, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr_acq, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr_nf, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr_rel, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor16_acq, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor16_nf, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor16_rel, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor_acq, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor_nf, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor_rel, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd16_acq, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd16_nf, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd16_rel, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd_acq, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd_nf, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd_rel, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement16_acq, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement16_nf, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement16_rel, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement_acq, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement_nf, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement_rel, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement64_acq, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement64_nf, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement64_rel, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement16_acq, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement16_nf, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement16_rel, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement_acq, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement_nf, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement_rel, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement64_acq, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement64_nf, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement64_rel, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_ReadWriteBarrier, "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__getReg, "ULLii", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_ReadStatusReg, "LLii", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_WriteStatusReg, "viLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_AddressOfReturnAddress, "v*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__mulh, "SLLiSLLiSLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__umulh, "ULLiULLiULLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") #undef BUILTIN #undef LANGBUILTIN #undef TARGET_HEADER_BUILTIN diff --git a/contrib/llvm-project/clang/include/clang/Basic/BuiltinsARM.def b/contrib/llvm-project/clang/include/clang/Basic/BuiltinsARM.def index be20c24aa28a..0e98f8680063 100644 --- a/contrib/llvm-project/clang/include/clang/Basic/BuiltinsARM.def +++ b/contrib/llvm-project/clang/include/clang/Basic/BuiltinsARM.def @@ -1,339 +1,343 @@ //===--- BuiltinsARM.def - ARM Builtin function database ----*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines the ARM-specific builtin function database. Users of // this file must define the BUILTIN macro to make use of this information. // //===----------------------------------------------------------------------===// // The format of this database matches clang/Basic/Builtins.def. #if defined(BUILTIN) && !defined(LANGBUILTIN) # define LANGBUILTIN(ID, TYPE, ATTRS, BUILTIN_LANG) BUILTIN(ID, TYPE, ATTRS) #endif +#if defined(BUILTIN) && !defined(TARGET_BUILTIN) +# define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS) +#endif + #if defined(BUILTIN) && !defined(TARGET_HEADER_BUILTIN) # define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANG, FEATURE) BUILTIN(ID, TYPE, ATTRS) #endif // In libgcc BUILTIN(__clear_cache, "vv*v*", "i") // 16-bit multiplications BUILTIN(__builtin_arm_smulbb, "iii", "nc") BUILTIN(__builtin_arm_smulbt, "iii", "nc") BUILTIN(__builtin_arm_smultb, "iii", "nc") BUILTIN(__builtin_arm_smultt, "iii", "nc") BUILTIN(__builtin_arm_smulwb, "iii", "nc") BUILTIN(__builtin_arm_smulwt, "iii", "nc") // Saturating arithmetic BUILTIN(__builtin_arm_qadd, "iii", "nc") BUILTIN(__builtin_arm_qsub, "iii", "nc") BUILTIN(__builtin_arm_qdbl, "ii", "nc") BUILTIN(__builtin_arm_ssat, "iiUi", "nc") BUILTIN(__builtin_arm_usat, "UiiUi", "nc") BUILTIN(__builtin_arm_smlabb, "iiii", "nc") BUILTIN(__builtin_arm_smlabt, "iiii", "nc") BUILTIN(__builtin_arm_smlatb, "iiii", "nc") BUILTIN(__builtin_arm_smlatt, "iiii", "nc") BUILTIN(__builtin_arm_smlawb, "iiii", "nc") BUILTIN(__builtin_arm_smlawt, "iiii", "nc") BUILTIN(__builtin_arm_ssat16, "iii", "nc") BUILTIN(__builtin_arm_usat16, "iii", "nc") BUILTIN(__builtin_arm_sxtab16, "iii", "nc") BUILTIN(__builtin_arm_sxtb16, "ii", "nc") BUILTIN(__builtin_arm_uxtab16, "iii", "nc") BUILTIN(__builtin_arm_uxtb16, "ii", "nc") BUILTIN(__builtin_arm_sel, "iii", "nc") BUILTIN(__builtin_arm_qadd8, "iii", "nc") BUILTIN(__builtin_arm_qsub8, "iii", "nc") BUILTIN(__builtin_arm_sadd8, "iii", "nc") BUILTIN(__builtin_arm_shadd8, "iii", "nc") BUILTIN(__builtin_arm_shsub8, "iii", "nc") BUILTIN(__builtin_arm_ssub8, "iii", "nc") BUILTIN(__builtin_arm_uadd8, "UiUiUi", "nc") BUILTIN(__builtin_arm_uhadd8, "UiUiUi", "nc") BUILTIN(__builtin_arm_uhsub8, "UiUiUi", "nc") BUILTIN(__builtin_arm_uqadd8, "UiUiUi", "nc") BUILTIN(__builtin_arm_uqsub8, "UiUiUi", "nc") BUILTIN(__builtin_arm_usub8, "UiUiUi", "nc") // Sum of 8-bit absolute differences BUILTIN(__builtin_arm_usad8, "UiUiUi", "nc") BUILTIN(__builtin_arm_usada8, "UiUiUiUi", "nc") // Parallel 16-bit addition and subtraction BUILTIN(__builtin_arm_qadd16, "iii", "nc") BUILTIN(__builtin_arm_qasx, "iii", "nc") BUILTIN(__builtin_arm_qsax, "iii", "nc") BUILTIN(__builtin_arm_qsub16, "iii", "nc") BUILTIN(__builtin_arm_sadd16, "iii", "nc") BUILTIN(__builtin_arm_sasx, "iii", "nc") BUILTIN(__builtin_arm_shadd16, "iii", "nc") BUILTIN(__builtin_arm_shasx, "iii", "nc") BUILTIN(__builtin_arm_shsax, "iii", "nc") BUILTIN(__builtin_arm_shsub16, "iii", "nc") BUILTIN(__builtin_arm_ssax, "iii", "nc") BUILTIN(__builtin_arm_ssub16, "iii", "nc") BUILTIN(__builtin_arm_uadd16, "UiUiUi", "nc") BUILTIN(__builtin_arm_uasx, "UiUiUi", "nc") BUILTIN(__builtin_arm_uhadd16, "UiUiUi", "nc") BUILTIN(__builtin_arm_uhasx, "UiUiUi", "nc") BUILTIN(__builtin_arm_uhsax, "UiUiUi", "nc") BUILTIN(__builtin_arm_uhsub16, "UiUiUi", "nc") BUILTIN(__builtin_arm_uqadd16, "UiUiUi", "nc") BUILTIN(__builtin_arm_uqasx, "UiUiUi", "nc") BUILTIN(__builtin_arm_uqsax, "UiUiUi", "nc") BUILTIN(__builtin_arm_uqsub16, "UiUiUi", "nc") BUILTIN(__builtin_arm_usax, "UiUiUi", "nc") BUILTIN(__builtin_arm_usub16, "UiUiUi", "nc") // Parallel 16-bit multiplication BUILTIN(__builtin_arm_smlad, "iiii", "nc") BUILTIN(__builtin_arm_smladx, "iiii", "nc") BUILTIN(__builtin_arm_smlald, "LLiiiLLi", "nc") BUILTIN(__builtin_arm_smlaldx, "LLiiiLLi", "nc") BUILTIN(__builtin_arm_smlsd, "iiii", "nc") BUILTIN(__builtin_arm_smlsdx, "iiii", "nc") BUILTIN(__builtin_arm_smlsld, "LLiiiLLi", "nc") BUILTIN(__builtin_arm_smlsldx, "LLiiiLLi", "nc") BUILTIN(__builtin_arm_smuad, "iii", "nc") BUILTIN(__builtin_arm_smuadx, "iii", "nc") BUILTIN(__builtin_arm_smusd, "iii", "nc") BUILTIN(__builtin_arm_smusdx, "iii", "nc") // Bit manipulation BUILTIN(__builtin_arm_rbit, "UiUi", "nc") BUILTIN(__builtin_arm_cls, "UiZUi", "nc") BUILTIN(__builtin_arm_cls64, "UiWUi", "nc") // Store and load exclusive BUILTIN(__builtin_arm_ldrexd, "LLUiv*", "") BUILTIN(__builtin_arm_strexd, "iLLUiv*", "") BUILTIN(__builtin_arm_ldrex, "v.", "t") BUILTIN(__builtin_arm_ldaex, "v.", "t") BUILTIN(__builtin_arm_strex, "i.", "t") BUILTIN(__builtin_arm_stlex, "i.", "t") BUILTIN(__builtin_arm_clrex, "v", "") // VFP BUILTIN(__builtin_arm_get_fpscr, "Ui", "nc") BUILTIN(__builtin_arm_set_fpscr, "vUi", "nc") BUILTIN(__builtin_arm_vcvtr_f, "ffi", "nc") BUILTIN(__builtin_arm_vcvtr_d, "fdi", "nc") // Coprocessor BUILTIN(__builtin_arm_ldc, "vUIiUIivC*", "") BUILTIN(__builtin_arm_ldcl, "vUIiUIivC*", "") BUILTIN(__builtin_arm_ldc2, "vUIiUIivC*", "") BUILTIN(__builtin_arm_ldc2l, "vUIiUIivC*", "") BUILTIN(__builtin_arm_stc, "vUIiUIiv*", "") BUILTIN(__builtin_arm_stcl, "vUIiUIiv*", "") BUILTIN(__builtin_arm_stc2, "vUIiUIiv*", "") BUILTIN(__builtin_arm_stc2l, "vUIiUIiv*", "") BUILTIN(__builtin_arm_cdp, "vUIiUIiUIiUIiUIiUIi", "") BUILTIN(__builtin_arm_cdp2, "vUIiUIiUIiUIiUIiUIi", "") BUILTIN(__builtin_arm_mcr, "vUIiUIiUiUIiUIiUIi", "") BUILTIN(__builtin_arm_mcr2, "vUIiUIiUiUIiUIiUIi", "") BUILTIN(__builtin_arm_mrc, "UiUIiUIiUIiUIiUIi", "") BUILTIN(__builtin_arm_mrc2, "UiUIiUIiUIiUIiUIi", "") BUILTIN(__builtin_arm_mcrr, "vUIiUIiLLUiUIi", "") BUILTIN(__builtin_arm_mcrr2, "vUIiUIiLLUiUIi", "") BUILTIN(__builtin_arm_mrrc, "LLUiUIiUIiUIi", "") BUILTIN(__builtin_arm_mrrc2, "LLUiUIiUIiUIi", "") // CRC32 -BUILTIN(__builtin_arm_crc32b, "UiUiUc", "nc") -BUILTIN(__builtin_arm_crc32cb, "UiUiUc", "nc") -BUILTIN(__builtin_arm_crc32h, "UiUiUs", "nc") -BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc") -BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc") -BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc") -BUILTIN(__builtin_arm_crc32d, "UiUiLLUi", "nc") -BUILTIN(__builtin_arm_crc32cd, "UiUiLLUi", "nc") +TARGET_BUILTIN(__builtin_arm_crc32b, "UiUiUc", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32cb, "UiUiUc", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32h, "UiUiUs", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32d, "UiUiLLUi", "nc", "crc") +TARGET_BUILTIN(__builtin_arm_crc32cd, "UiUiLLUi", "nc", "crc") // ARMv8-M Security Extensions a.k.a CMSE BUILTIN(__builtin_arm_cmse_TT, "Uiv*", "n") BUILTIN(__builtin_arm_cmse_TTT, "Uiv*", "n") BUILTIN(__builtin_arm_cmse_TTA, "Uiv*", "n") BUILTIN(__builtin_arm_cmse_TTAT, "Uiv*", "n") // HINT BUILTIN(__builtin_arm_nop, "v", "") BUILTIN(__builtin_arm_yield, "v", "") BUILTIN(__builtin_arm_wfe, "v", "") BUILTIN(__builtin_arm_wfi, "v", "") BUILTIN(__builtin_arm_sev, "v", "") BUILTIN(__builtin_arm_sevl, "v", "") BUILTIN(__builtin_arm_dbg, "vUi", "") // Data barrier BUILTIN(__builtin_arm_dmb, "vUi", "nc") BUILTIN(__builtin_arm_dsb, "vUi", "nc") BUILTIN(__builtin_arm_isb, "vUi", "nc") // Prefetch BUILTIN(__builtin_arm_prefetch, "vvC*UiUi", "nc") // System registers (ACLE) BUILTIN(__builtin_arm_rsr, "UicC*", "nc") BUILTIN(__builtin_arm_rsr64, "LLUicC*", "nc") BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc") BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc") BUILTIN(__builtin_arm_wsr64, "vcC*LLUi", "nc") BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc") // Builtins for implementing ACLE MVE intrinsics. (Unlike NEON, these // don't need to live in a separate BuiltinsMVE.def, because they // aren't included from both here and BuiltinsAArch64.def.) #include "clang/Basic/arm_mve_builtins.inc" #include "clang/Basic/arm_cde_builtins.inc" // MSVC LANGBUILTIN(__emit, "vIUiC", "", ALL_MS_LANGUAGES) LANGBUILTIN(__yield, "v", "", ALL_MS_LANGUAGES) LANGBUILTIN(__wfe, "v", "", ALL_MS_LANGUAGES) LANGBUILTIN(__wfi, "v", "", ALL_MS_LANGUAGES) LANGBUILTIN(__sev, "v", "", ALL_MS_LANGUAGES) LANGBUILTIN(__sevl, "v", "", ALL_MS_LANGUAGES) LANGBUILTIN(__dmb, "vUi", "nc", ALL_MS_LANGUAGES) LANGBUILTIN(__dsb, "vUi", "nc", ALL_MS_LANGUAGES) LANGBUILTIN(__isb, "vUi", "nc", ALL_MS_LANGUAGES) LANGBUILTIN(__ldrexd, "WiWiCD*", "", ALL_MS_LANGUAGES) LANGBUILTIN(_MoveFromCoprocessor, "UiIUiIUiIUiIUiIUi", "", ALL_MS_LANGUAGES) LANGBUILTIN(_MoveFromCoprocessor2, "UiIUiIUiIUiIUiIUi", "", ALL_MS_LANGUAGES) LANGBUILTIN(_MoveToCoprocessor, "vUiIUiIUiIUiIUiIUi", "", ALL_MS_LANGUAGES) LANGBUILTIN(_MoveToCoprocessor2, "vUiIUiIUiIUiIUiIUi", "", ALL_MS_LANGUAGES) TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_BitScanForward64, "UcUNi*ULLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_BitScanReverse64, "UcUNi*ULLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement64, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeSub64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement64, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd_acq, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd_rel, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd_nf, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd16_acq, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd16_rel, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd16_nf, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange16_acq, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange16_nf, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange16_rel, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange_acq, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange_nf, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange_rel, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedExchange64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange8_acq, "ccD*cc", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange8_nf, "ccD*cc", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange8_rel, "ccD*cc", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange16_acq, "ssD*ss", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange16_nf, "ssD*ss", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange16_rel, "ssD*ss", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange_acq, "NiNiD*NiNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange_nf, "NiNiD*NiNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange_rel, "NiNiD*NiNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_acq, "LLiLLiD*LLiLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_nf, "LLiLLiD*LLiLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_rel, "LLiLLiD*LLiLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr16_acq, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr16_nf, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr16_rel, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr_acq, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr_nf, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr_rel, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor16_acq, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor16_nf, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor16_rel, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor_acq, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor_nf, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor_rel, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd16_acq, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd16_nf, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd16_rel, "ssD*s", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd_acq, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd_nf, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd_rel, "NiNiD*Ni", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedAnd64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement16_acq, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement16_nf, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement16_rel, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement_acq, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement_nf, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement_rel, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement64_acq, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement64_nf, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedIncrement64_rel, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement16_acq, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement16_nf, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement16_rel, "ssD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement_acq, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement_nf, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement_rel, "NiNiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement64_acq, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement64_nf, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedDecrement64_rel, "LLiLLiD*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") #undef BUILTIN #undef LANGBUILTIN #undef TARGET_HEADER_BUILTIN diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.cpp index e163ebfa2348..c4ab1bc961af 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.cpp @@ -1,969 +1,971 @@ //===--- AArch64.cpp - Implement AArch64 target feature support -----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file implements AArch64 TargetInfo objects. // //===----------------------------------------------------------------------===// #include "AArch64.h" #include "clang/Basic/LangOptions.h" #include "clang/Basic/TargetBuiltins.h" #include "clang/Basic/TargetInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/Support/AArch64TargetParser.h" using namespace clang; using namespace clang::targets; const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, #include "clang/Basic/BuiltinsNEON.def" #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, #include "clang/Basic/BuiltinsSVE.def" #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ {#ID, TYPE, ATTRS, nullptr, LANG, nullptr}, +#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ + {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, #include "clang/Basic/BuiltinsAArch64.def" }; AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : TargetInfo(Triple), ABI("aapcs") { if (getTriple().isOSOpenBSD()) { Int64Type = SignedLongLong; IntMaxType = SignedLongLong; } else { if (!getTriple().isOSDarwin() && !getTriple().isOSNetBSD()) WCharType = UnsignedInt; Int64Type = SignedLong; IntMaxType = SignedLong; } // All AArch64 implementations support ARMv8 FP, which makes half a legal type. HasLegalHalfType = true; HasFloat16 = true; if (Triple.isArch64Bit()) LongWidth = LongAlign = PointerWidth = PointerAlign = 64; else LongWidth = LongAlign = PointerWidth = PointerAlign = 32; MaxVectorAlign = 128; MaxAtomicInlineWidth = 128; MaxAtomicPromoteWidth = 128; LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; LongDoubleFormat = &llvm::APFloat::IEEEquad(); BFloat16Width = BFloat16Align = 16; BFloat16Format = &llvm::APFloat::BFloat(); // Make __builtin_ms_va_list available. HasBuiltinMSVaList = true; // Make the SVE types available. Note that this deliberately doesn't // depend on SveMode, since in principle it should be possible to turn // SVE on and off within a translation unit. It should also be possible // to compile the global declaration: // // __SVInt8_t *ptr; // // even without SVE. HasAArch64SVETypes = true; // {} in inline assembly are neon specifiers, not assembly variant // specifiers. NoAsmVariants = true; // AAPCS gives rules for bitfields. 7.1.7 says: "The container type // contributes to the alignment of the containing aggregate in the same way // a plain (non bit-field) member of that type would, without exception for // zero-sized or anonymous bit-fields." assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); UseZeroLengthBitfieldAlignment = true; // AArch64 targets default to using the ARM C++ ABI. TheCXXABI.set(TargetCXXABI::GenericAArch64); if (Triple.getOS() == llvm::Triple::Linux) this->MCountName = "\01_mcount"; else if (Triple.getOS() == llvm::Triple::UnknownOS) this->MCountName = Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount"; } StringRef AArch64TargetInfo::getABI() const { return ABI; } bool AArch64TargetInfo::setABI(const std::string &Name) { if (Name != "aapcs" && Name != "darwinpcs") return false; ABI = Name; return true; } bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, BranchProtectionInfo &BPI, StringRef &Err) const { llvm::AArch64::ParsedBranchProtection PBP; if (!llvm::AArch64::parseBranchProtection(Spec, PBP, Err)) return false; BPI.SignReturnAddr = llvm::StringSwitch(PBP.Scope) .Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf) .Case("all", LangOptions::SignReturnAddressScopeKind::All) .Default(LangOptions::SignReturnAddressScopeKind::None); if (PBP.Key == "a_key") BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey; else BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey; BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement; return true; } bool AArch64TargetInfo::isValidCPUName(StringRef Name) const { return Name == "generic" || llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID; } bool AArch64TargetInfo::setCPU(const std::string &Name) { return isValidCPUName(Name); } void AArch64TargetInfo::fillValidCPUList( SmallVectorImpl &Values) const { llvm::AArch64::fillValidCPUArchList(Values); } void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1"); Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); } void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts, MacroBuilder &Builder) const { // Also include the ARMv8.1 defines getTargetDefinesARMV81A(Opts, Builder); } void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1"); Builder.defineMacro("__ARM_FEATURE_JCVT", "1"); // Also include the Armv8.2 defines getTargetDefinesARMV82A(Opts, Builder); } void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts, MacroBuilder &Builder) const { // Also include the Armv8.3 defines getTargetDefinesARMV83A(Opts, Builder); } void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__ARM_FEATURE_FRINT", "1"); // Also include the Armv8.4 defines getTargetDefinesARMV84A(Opts, Builder); } void AArch64TargetInfo::getTargetDefinesARMV86A(const LangOptions &Opts, MacroBuilder &Builder) const { // Also include the Armv8.5 defines // FIXME: Armv8.6 makes the following extensions mandatory: // - __ARM_FEATURE_BF16 // - __ARM_FEATURE_MATMUL_INT8 // Handle them here. getTargetDefinesARMV85A(Opts, Builder); } void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts, MacroBuilder &Builder) const { // Also include the Armv8.6 defines getTargetDefinesARMV86A(Opts, Builder); } void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { // Target identification. Builder.defineMacro("__aarch64__"); // For bare-metal. if (getTriple().getOS() == llvm::Triple::UnknownOS && getTriple().isOSBinFormatELF()) Builder.defineMacro("__ELF__"); // Target properties. if (!getTriple().isOSWindows() && getTriple().isArch64Bit()) { Builder.defineMacro("_LP64"); Builder.defineMacro("__LP64__"); } std::string CodeModel = getTargetOpts().CodeModel; if (CodeModel == "default") CodeModel = "small"; for (char &c : CodeModel) c = toupper(c); Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__"); // ACLE predefines. Many can only have one possible value on v8 AArch64. Builder.defineMacro("__ARM_ACLE", "200"); Builder.defineMacro("__ARM_ARCH", "8"); Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); Builder.defineMacro("__ARM_64BIT_STATE", "1"); Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); Builder.defineMacro("__ARM_FEATURE_FMA", "1"); Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); // 0xe implies support for half, single and double precision operations. Builder.defineMacro("__ARM_FP", "0xE"); // PCS specifies this for SysV variants, which is all we support. Other ABIs // may choose __ARM_FP16_FORMAT_ALTERNATIVE. Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); Builder.defineMacro("__ARM_FP16_ARGS", "1"); if (Opts.UnsafeFPMath) Builder.defineMacro("__ARM_FP_FAST", "1"); Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Twine(Opts.WCharSize ? Opts.WCharSize : 4)); Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4"); if (FPU & NeonMode) { Builder.defineMacro("__ARM_NEON", "1"); // 64-bit NEON supports half, single and double precision operations. Builder.defineMacro("__ARM_NEON_FP", "0xE"); } if (FPU & SveMode) Builder.defineMacro("__ARM_FEATURE_SVE", "1"); if (HasSVE2) Builder.defineMacro("__ARM_FEATURE_SVE2", "1"); if (HasSVE2 && HasSVE2AES) Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1"); if (HasSVE2 && HasSVE2BitPerm) Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1"); if (HasSVE2 && HasSVE2SHA3) Builder.defineMacro("__ARM_FEATURE_SVE2_SHA3", "1"); if (HasSVE2 && HasSVE2SM4) Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1"); if (HasCRC) Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained feature // macros for AES, SHA2, SHA3 and SM4 if (HasAES && HasSHA2) Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); if (HasAES) Builder.defineMacro("__ARM_FEATURE_AES", "1"); if (HasSHA2) Builder.defineMacro("__ARM_FEATURE_SHA2", "1"); if (HasSHA3) { Builder.defineMacro("__ARM_FEATURE_SHA3", "1"); Builder.defineMacro("__ARM_FEATURE_SHA512", "1"); } if (HasSM4) { Builder.defineMacro("__ARM_FEATURE_SM3", "1"); Builder.defineMacro("__ARM_FEATURE_SM4", "1"); } if (HasUnaligned) Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); if ((FPU & NeonMode) && HasFullFP16) Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1"); if (HasFullFP16) Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1"); if (HasDotProd) Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1"); if (HasMTE) Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1"); if (HasTME) Builder.defineMacro("__ARM_FEATURE_TME", "1"); if (HasMatMul) Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1"); if (HasLSE) Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1"); if (HasBFloat16) { Builder.defineMacro("__ARM_FEATURE_BF16", "1"); Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1"); Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1"); Builder.defineMacro("__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", "1"); } if ((FPU & SveMode) && HasBFloat16) { Builder.defineMacro("__ARM_FEATURE_SVE_BF16", "1"); } if ((FPU & SveMode) && HasMatmulFP64) Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP64", "1"); if ((FPU & SveMode) && HasMatmulFP32) Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP32", "1"); if ((FPU & SveMode) && HasMatMul) Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_INT8", "1"); if ((FPU & NeonMode) && HasFP16FML) Builder.defineMacro("__ARM_FEATURE_FP16_FML", "1"); if (Opts.hasSignReturnAddress()) { // Bitmask: // 0: Protection using the A key // 1: Protection using the B key // 2: Protection including leaf functions unsigned Value = 0; if (Opts.isSignReturnAddressWithAKey()) Value |= (1 << 0); else Value |= (1 << 1); if (Opts.isSignReturnAddressScopeAll()) Value |= (1 << 2); Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value)); } if (Opts.BranchTargetEnforcement) Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1"); if (HasLS64) Builder.defineMacro("__ARM_FEATURE_LS64", "1"); if (HasRandGen) Builder.defineMacro("__ARM_FEATURE_RNG", "1"); switch (ArchKind) { default: break; case llvm::AArch64::ArchKind::ARMV8_1A: getTargetDefinesARMV81A(Opts, Builder); break; case llvm::AArch64::ArchKind::ARMV8_2A: getTargetDefinesARMV82A(Opts, Builder); break; case llvm::AArch64::ArchKind::ARMV8_3A: getTargetDefinesARMV83A(Opts, Builder); break; case llvm::AArch64::ArchKind::ARMV8_4A: getTargetDefinesARMV84A(Opts, Builder); break; case llvm::AArch64::ArchKind::ARMV8_5A: getTargetDefinesARMV85A(Opts, Builder); break; case llvm::AArch64::ArchKind::ARMV8_6A: getTargetDefinesARMV86A(Opts, Builder); break; case llvm::AArch64::ArchKind::ARMV8_7A: getTargetDefinesARMV87A(Opts, Builder); break; } // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); if (Opts.ArmSveVectorBits) { Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.ArmSveVectorBits)); Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS"); } } ArrayRef AArch64TargetInfo::getTargetBuiltins() const { return llvm::makeArrayRef(BuiltinInfo, clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); } bool AArch64TargetInfo::hasFeature(StringRef Feature) const { return Feature == "aarch64" || Feature == "arm64" || Feature == "arm" || (Feature == "neon" && (FPU & NeonMode)) || ((Feature == "sve" || Feature == "sve2" || Feature == "sve2-bitperm" || Feature == "sve2-aes" || Feature == "sve2-sha3" || Feature == "sve2-sm4" || Feature == "f64mm" || Feature == "f32mm" || Feature == "i8mm" || Feature == "bf16") && (FPU & SveMode)) || (Feature == "ls64" && HasLS64); } bool AArch64TargetInfo::handleTargetFeatures(std::vector &Features, DiagnosticsEngine &Diags) { FPU = FPUMode; HasCRC = false; HasCrypto = false; HasAES = false; HasSHA2 = false; HasSHA3 = false; HasSM4 = false; HasUnaligned = true; HasFullFP16 = false; HasDotProd = false; HasFP16FML = false; HasMTE = false; HasTME = false; HasLS64 = false; HasRandGen = false; HasMatMul = false; HasBFloat16 = false; HasSVE2 = false; HasSVE2AES = false; HasSVE2SHA3 = false; HasSVE2SM4 = false; HasSVE2BitPerm = false; HasMatmulFP64 = false; HasMatmulFP32 = false; HasLSE = false; ArchKind = llvm::AArch64::ArchKind::ARMV8A; for (const auto &Feature : Features) { if (Feature == "+neon") FPU |= NeonMode; if (Feature == "+sve") { FPU |= SveMode; HasFullFP16 = 1; } if (Feature == "+sve2") { FPU |= SveMode; HasFullFP16 = 1; HasSVE2 = 1; } if (Feature == "+sve2-aes") { FPU |= SveMode; HasFullFP16 = 1; HasSVE2 = 1; HasSVE2AES = 1; } if (Feature == "+sve2-sha3") { FPU |= SveMode; HasFullFP16 = 1; HasSVE2 = 1; HasSVE2SHA3 = 1; } if (Feature == "+sve2-sm4") { FPU |= SveMode; HasFullFP16 = 1; HasSVE2 = 1; HasSVE2SM4 = 1; } if (Feature == "+sve2-bitperm") { FPU |= SveMode; HasFullFP16 = 1; HasSVE2 = 1; HasSVE2BitPerm = 1; } if (Feature == "+f32mm") { FPU |= SveMode; HasMatmulFP32 = true; } if (Feature == "+f64mm") { FPU |= SveMode; HasMatmulFP64 = true; } if (Feature == "+crc") HasCRC = true; if (Feature == "+crypto") HasCrypto = true; if (Feature == "+aes") HasAES = true; if (Feature == "+sha2") HasSHA2 = true; if (Feature == "+sha3") { HasSHA2 = true; HasSHA3 = true; } if (Feature == "+sm4") HasSM4 = true; if (Feature == "+strict-align") HasUnaligned = false; if (Feature == "+v8.1a") ArchKind = llvm::AArch64::ArchKind::ARMV8_1A; if (Feature == "+v8.2a") ArchKind = llvm::AArch64::ArchKind::ARMV8_2A; if (Feature == "+v8.3a") ArchKind = llvm::AArch64::ArchKind::ARMV8_3A; if (Feature == "+v8.4a") ArchKind = llvm::AArch64::ArchKind::ARMV8_4A; if (Feature == "+v8.5a") ArchKind = llvm::AArch64::ArchKind::ARMV8_5A; if (Feature == "+v8.6a") ArchKind = llvm::AArch64::ArchKind::ARMV8_6A; if (Feature == "+v8.7a") ArchKind = llvm::AArch64::ArchKind::ARMV8_7A; if (Feature == "+v8r") ArchKind = llvm::AArch64::ArchKind::ARMV8R; if (Feature == "+fullfp16") HasFullFP16 = true; if (Feature == "+dotprod") HasDotProd = true; if (Feature == "+fp16fml") HasFP16FML = true; if (Feature == "+mte") HasMTE = true; if (Feature == "+tme") HasTME = true; if (Feature == "+pauth") HasPAuth = true; if (Feature == "+i8mm") HasMatMul = true; if (Feature == "+bf16") HasBFloat16 = true; if (Feature == "+lse") HasLSE = true; if (Feature == "+ls64") HasLS64 = true; if (Feature == "+rand") HasRandGen = true; if (Feature == "+flagm") HasFlagM = true; } setDataLayout(); return true; } TargetInfo::CallingConvCheckResult AArch64TargetInfo::checkCallingConvention(CallingConv CC) const { switch (CC) { case CC_C: case CC_Swift: case CC_SwiftAsync: case CC_PreserveMost: case CC_PreserveAll: case CC_OpenCLKernel: case CC_AArch64VectorCall: case CC_Win64: return CCCR_OK; default: return CCCR_Warning; } } bool AArch64TargetInfo::isCLZForZeroUndef() const { return false; } TargetInfo::BuiltinVaListKind AArch64TargetInfo::getBuiltinVaListKind() const { return TargetInfo::AArch64ABIBuiltinVaList; } const char *const AArch64TargetInfo::GCCRegNames[] = { // 32-bit Integer registers "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", // 64-bit Integer registers "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", // 32-bit floating point regsisters "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", // 64-bit floating point regsisters "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", // Neon vector registers "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", // SVE vector registers "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", // SVE predicate registers "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15" }; ArrayRef AArch64TargetInfo::getGCCRegNames() const { return llvm::makeArrayRef(GCCRegNames); } const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { {{"w31"}, "wsp"}, {{"x31"}, "sp"}, // GCC rN registers are aliases of xN registers. {{"r0"}, "x0"}, {{"r1"}, "x1"}, {{"r2"}, "x2"}, {{"r3"}, "x3"}, {{"r4"}, "x4"}, {{"r5"}, "x5"}, {{"r6"}, "x6"}, {{"r7"}, "x7"}, {{"r8"}, "x8"}, {{"r9"}, "x9"}, {{"r10"}, "x10"}, {{"r11"}, "x11"}, {{"r12"}, "x12"}, {{"r13"}, "x13"}, {{"r14"}, "x14"}, {{"r15"}, "x15"}, {{"r16"}, "x16"}, {{"r17"}, "x17"}, {{"r18"}, "x18"}, {{"r19"}, "x19"}, {{"r20"}, "x20"}, {{"r21"}, "x21"}, {{"r22"}, "x22"}, {{"r23"}, "x23"}, {{"r24"}, "x24"}, {{"r25"}, "x25"}, {{"r26"}, "x26"}, {{"r27"}, "x27"}, {{"r28"}, "x28"}, {{"r29", "x29"}, "fp"}, {{"r30", "x30"}, "lr"}, // The S/D/Q and W/X registers overlap, but aren't really aliases; we // don't want to substitute one of these for a different-sized one. }; ArrayRef AArch64TargetInfo::getGCCRegAliases() const { return llvm::makeArrayRef(GCCRegAliases); } bool AArch64TargetInfo::validateAsmConstraint( const char *&Name, TargetInfo::ConstraintInfo &Info) const { switch (*Name) { default: return false; case 'w': // Floating point and SIMD registers (V0-V31) Info.setAllowsRegister(); return true; case 'I': // Constant that can be used with an ADD instruction case 'J': // Constant that can be used with a SUB instruction case 'K': // Constant that can be used with a 32-bit logical instruction case 'L': // Constant that can be used with a 64-bit logical instruction case 'M': // Constant that can be used as a 32-bit MOV immediate case 'N': // Constant that can be used as a 64-bit MOV immediate case 'Y': // Floating point constant zero case 'Z': // Integer constant zero return true; case 'Q': // A memory reference with base register and no offset Info.setAllowsMemory(); return true; case 'S': // A symbolic address Info.setAllowsRegister(); return true; case 'U': if (Name[1] == 'p' && (Name[2] == 'l' || Name[2] == 'a')) { // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7) Info.setAllowsRegister(); Name += 2; return true; } // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. // Utf: A memory address suitable for ldp/stp in TF mode. // Usa: An absolute symbolic address. // Ush: The high part (bits 32:12) of a pc-relative symbolic address. // Better to return an error saying that it's an unrecognised constraint // even if this is a valid constraint in gcc. return false; case 'z': // Zero register, wzr or xzr Info.setAllowsRegister(); return true; case 'x': // Floating point and SIMD registers (V0-V15) Info.setAllowsRegister(); return true; case 'y': // SVE registers (V0-V7) Info.setAllowsRegister(); return true; } return false; } bool AArch64TargetInfo::validateConstraintModifier( StringRef Constraint, char Modifier, unsigned Size, std::string &SuggestedModifier) const { // Strip off constraint modifiers. while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') Constraint = Constraint.substr(1); switch (Constraint[0]) { default: return true; case 'z': case 'r': { switch (Modifier) { case 'x': case 'w': // For now assume that the person knows what they're // doing with the modifier. return true; default: // By default an 'r' constraint will be in the 'x' // registers. if (Size == 64) return true; if (Size == 512) return HasLS64; SuggestedModifier = "w"; return false; } } } } const char *AArch64TargetInfo::getClobbers() const { return ""; } int AArch64TargetInfo::getEHDataRegisterNumber(unsigned RegNo) const { if (RegNo == 0) return 0; if (RegNo == 1) return 1; return -1; } bool AArch64TargetInfo::hasInt128Type() const { return true; } AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : AArch64TargetInfo(Triple, Opts) {} void AArch64leTargetInfo::setDataLayout() { if (getTriple().isOSBinFormatMachO()) { if(getTriple().isArch32Bit()) resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128", "_"); else resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128", "_"); } else resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); } void AArch64leTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__AARCH64EL__"); AArch64TargetInfo::getTargetDefines(Opts, Builder); } AArch64beTargetInfo::AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : AArch64TargetInfo(Triple, Opts) {} void AArch64beTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__AARCH64EB__"); Builder.defineMacro("__AARCH_BIG_ENDIAN"); Builder.defineMacro("__ARM_BIG_ENDIAN"); AArch64TargetInfo::getTargetDefines(Opts, Builder); } void AArch64beTargetInfo::setDataLayout() { assert(!getTriple().isOSBinFormatMachO()); resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); } WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : WindowsTargetInfo(Triple, Opts), Triple(Triple) { // This is an LLP64 platform. // int:4, long:4, long long:8, long double:8. IntWidth = IntAlign = 32; LongWidth = LongAlign = 32; DoubleAlign = LongLongAlign = 64; LongDoubleWidth = LongDoubleAlign = 64; LongDoubleFormat = &llvm::APFloat::IEEEdouble(); IntMaxType = SignedLongLong; Int64Type = SignedLongLong; SizeType = UnsignedLongLong; PtrDiffType = SignedLongLong; IntPtrType = SignedLongLong; } void WindowsARM64TargetInfo::setDataLayout() { resetDataLayout(Triple.isOSBinFormatMachO() ? "e-m:o-i64:64-i128:128-n32:64-S128" : "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128", Triple.isOSBinFormatMachO() ? "_" : ""); } TargetInfo::BuiltinVaListKind WindowsARM64TargetInfo::getBuiltinVaListKind() const { return TargetInfo::CharPtrBuiltinVaList; } TargetInfo::CallingConvCheckResult WindowsARM64TargetInfo::checkCallingConvention(CallingConv CC) const { switch (CC) { case CC_X86StdCall: case CC_X86ThisCall: case CC_X86FastCall: case CC_X86VectorCall: return CCCR_Ignore; case CC_C: case CC_OpenCLKernel: case CC_PreserveMost: case CC_PreserveAll: case CC_Swift: case CC_SwiftAsync: case CC_Win64: return CCCR_OK; default: return CCCR_Warning; } } MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : WindowsARM64TargetInfo(Triple, Opts) { TheCXXABI.set(TargetCXXABI::Microsoft); } void MicrosoftARM64TargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { WindowsARM64TargetInfo::getTargetDefines(Opts, Builder); Builder.defineMacro("_M_ARM64", "1"); } TargetInfo::CallingConvKind MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const { return CCK_MicrosoftWin64; } unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const { unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize); // MSVC does size based alignment for arm64 based on alignment section in // below document, replicate that to keep alignment consistent with object // files compiled by MSVC. // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions if (TypeSize >= 512) { // TypeSize >= 64 bytes Align = std::max(Align, 128u); // align type at least 16 bytes } else if (TypeSize >= 64) { // TypeSize >= 8 bytes Align = std::max(Align, 64u); // align type at least 8 butes } else if (TypeSize >= 16) { // TypeSize >= 2 bytes Align = std::max(Align, 32u); // align type at least 4 bytes } return Align; } MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : WindowsARM64TargetInfo(Triple, Opts) { TheCXXABI.set(TargetCXXABI::GenericAArch64); } DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : DarwinTargetInfo(Triple, Opts) { Int64Type = SignedLongLong; if (getTriple().isArch32Bit()) IntMaxType = SignedLongLong; WCharType = SignedInt; UseSignedCharForObjCBool = false; LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; LongDoubleFormat = &llvm::APFloat::IEEEdouble(); UseZeroLengthBitfieldAlignment = false; if (getTriple().isArch32Bit()) { UseBitFieldTypeAlignment = false; ZeroLengthBitfieldBoundary = 32; UseZeroLengthBitfieldAlignment = true; TheCXXABI.set(TargetCXXABI::WatchOS); } else TheCXXABI.set(TargetCXXABI::AppleARM64); } void DarwinAArch64TargetInfo::getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, MacroBuilder &Builder) const { Builder.defineMacro("__AARCH64_SIMD__"); if (Triple.isArch32Bit()) Builder.defineMacro("__ARM64_ARCH_8_32__"); else Builder.defineMacro("__ARM64_ARCH_8__"); Builder.defineMacro("__ARM_NEON__"); Builder.defineMacro("__LITTLE_ENDIAN__"); Builder.defineMacro("__REGISTER_PREFIX__", ""); Builder.defineMacro("__arm64", "1"); Builder.defineMacro("__arm64__", "1"); if (Triple.isArm64e()) Builder.defineMacro("__arm64e__", "1"); getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); } TargetInfo::BuiltinVaListKind DarwinAArch64TargetInfo::getBuiltinVaListKind() const { return TargetInfo::CharPtrBuiltinVaList; } // 64-bit RenderScript is aarch64 RenderScript64TargetInfo::RenderScript64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), Triple.getOSName(), Triple.getEnvironmentName()), Opts) { IsRenderScriptTarget = true; } void RenderScript64TargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__RENDERSCRIPT__"); AArch64leTargetInfo::getTargetDefines(Opts, Builder); } diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/ARM.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/ARM.cpp index 0e4048f8d5ff..36d3b34a897a 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/ARM.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/ARM.cpp @@ -1,1327 +1,1329 @@ //===--- ARM.cpp - Implement ARM target feature support -------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file implements ARM TargetInfo objects. // //===----------------------------------------------------------------------===// #include "ARM.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/Diagnostic.h" #include "clang/Basic/TargetBuiltins.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSwitch.h" using namespace clang; using namespace clang::targets; void ARMTargetInfo::setABIAAPCS() { IsAAPCS = true; DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; BFloat16Width = BFloat16Align = 16; BFloat16Format = &llvm::APFloat::BFloat(); const llvm::Triple &T = getTriple(); bool IsNetBSD = T.isOSNetBSD(); bool IsOpenBSD = T.isOSOpenBSD(); if (!T.isOSWindows() && !IsNetBSD && !IsOpenBSD) WCharType = UnsignedInt; UseBitFieldTypeAlignment = true; ZeroLengthBitfieldBoundary = 0; // Thumb1 add sp, #imm requires the immediate value be multiple of 4, // so set preferred for small types to 32. if (T.isOSBinFormatMachO()) { resetDataLayout(BigEndian ? "E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64", "_"); } else if (T.isOSWindows()) { assert(!BigEndian && "Windows on ARM does not support big endian"); resetDataLayout("e" "-m:w" "-p:32:32" "-Fi8" "-i64:64" "-v128:64:128" "-a:0:32" "-n32" "-S64"); } else if (T.isOSNaCl()) { assert(!BigEndian && "NaCl on ARM does not support big endian"); resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128"); } else { resetDataLayout(BigEndian ? "E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" : "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"); } // FIXME: Enumerated types are variable width in straight AAPCS. } void ARMTargetInfo::setABIAPCS(bool IsAAPCS16) { const llvm::Triple &T = getTriple(); IsAAPCS = false; if (IsAAPCS16) DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; else DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; BFloat16Width = BFloat16Align = 16; BFloat16Format = &llvm::APFloat::BFloat(); WCharType = SignedInt; // Do not respect the alignment of bit-field types when laying out // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. UseBitFieldTypeAlignment = false; /// gcc forces the alignment to 4 bytes, regardless of the type of the /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in /// gcc. ZeroLengthBitfieldBoundary = 32; if (T.isOSBinFormatMachO() && IsAAPCS16) { assert(!BigEndian && "AAPCS16 does not support big-endian"); resetDataLayout("e-m:o-p:32:32-Fi8-i64:64-a:0:32-n32-S128", "_"); } else if (T.isOSBinFormatMachO()) resetDataLayout( BigEndian ? "E-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32", "_"); else resetDataLayout( BigEndian ? "E-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); // FIXME: Override "preferred align" for double and long long. } void ARMTargetInfo::setArchInfo() { StringRef ArchName = getTriple().getArchName(); ArchISA = llvm::ARM::parseArchISA(ArchName); CPU = std::string(llvm::ARM::getDefaultCPU(ArchName)); llvm::ARM::ArchKind AK = llvm::ARM::parseArch(ArchName); if (AK != llvm::ARM::ArchKind::INVALID) ArchKind = AK; setArchInfo(ArchKind); } void ARMTargetInfo::setArchInfo(llvm::ARM::ArchKind Kind) { StringRef SubArch; // cache TargetParser info ArchKind = Kind; SubArch = llvm::ARM::getSubArch(ArchKind); ArchProfile = llvm::ARM::parseArchProfile(SubArch); ArchVersion = llvm::ARM::parseArchVersion(SubArch); // cache CPU related strings CPUAttr = getCPUAttr(); CPUProfile = getCPUProfile(); } void ARMTargetInfo::setAtomic() { // when triple does not specify a sub arch, // then we are not using inline atomics bool ShouldUseInlineAtomic = (ArchISA == llvm::ARM::ISAKind::ARM && ArchVersion >= 6) || (ArchISA == llvm::ARM::ISAKind::THUMB && ArchVersion >= 7); // Cortex M does not support 8 byte atomics, while general Thumb2 does. if (ArchProfile == llvm::ARM::ProfileKind::M) { MaxAtomicPromoteWidth = 32; if (ShouldUseInlineAtomic) MaxAtomicInlineWidth = 32; } else { MaxAtomicPromoteWidth = 64; if (ShouldUseInlineAtomic) MaxAtomicInlineWidth = 64; } } bool ARMTargetInfo::hasMVE() const { return ArchKind == llvm::ARM::ArchKind::ARMV8_1MMainline && MVE != 0; } bool ARMTargetInfo::hasMVEFloat() const { return hasMVE() && (MVE & MVE_FP); } bool ARMTargetInfo::hasCDE() const { return getARMCDECoprocMask() != 0; } bool ARMTargetInfo::isThumb() const { return ArchISA == llvm::ARM::ISAKind::THUMB; } bool ARMTargetInfo::supportsThumb() const { return CPUAttr.count('T') || ArchVersion >= 6; } bool ARMTargetInfo::supportsThumb2() const { return CPUAttr.equals("6T2") || (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); } StringRef ARMTargetInfo::getCPUAttr() const { // For most sub-arches, the build attribute CPU name is enough. // For Cortex variants, it's slightly different. switch (ArchKind) { default: return llvm::ARM::getCPUAttr(ArchKind); case llvm::ARM::ArchKind::ARMV6M: return "6M"; case llvm::ARM::ArchKind::ARMV7S: return "7S"; case llvm::ARM::ArchKind::ARMV7A: return "7A"; case llvm::ARM::ArchKind::ARMV7R: return "7R"; case llvm::ARM::ArchKind::ARMV7M: return "7M"; case llvm::ARM::ArchKind::ARMV7EM: return "7EM"; case llvm::ARM::ArchKind::ARMV7VE: return "7VE"; case llvm::ARM::ArchKind::ARMV8A: return "8A"; case llvm::ARM::ArchKind::ARMV8_1A: return "8_1A"; case llvm::ARM::ArchKind::ARMV8_2A: return "8_2A"; case llvm::ARM::ArchKind::ARMV8_3A: return "8_3A"; case llvm::ARM::ArchKind::ARMV8_4A: return "8_4A"; case llvm::ARM::ArchKind::ARMV8_5A: return "8_5A"; case llvm::ARM::ArchKind::ARMV8_6A: return "8_6A"; case llvm::ARM::ArchKind::ARMV8_7A: return "8_7A"; case llvm::ARM::ArchKind::ARMV8MBaseline: return "8M_BASE"; case llvm::ARM::ArchKind::ARMV8MMainline: return "8M_MAIN"; case llvm::ARM::ArchKind::ARMV8R: return "8R"; case llvm::ARM::ArchKind::ARMV8_1MMainline: return "8_1M_MAIN"; } } StringRef ARMTargetInfo::getCPUProfile() const { switch (ArchProfile) { case llvm::ARM::ProfileKind::A: return "A"; case llvm::ARM::ProfileKind::R: return "R"; case llvm::ARM::ProfileKind::M: return "M"; default: return ""; } } ARMTargetInfo::ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), HW_FP(0) { bool IsOpenBSD = Triple.isOSOpenBSD(); bool IsNetBSD = Triple.isOSNetBSD(); // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like // environment where size_t is `unsigned long` rather than `unsigned int` PtrDiffType = IntPtrType = (Triple.isOSDarwin() || Triple.isOSBinFormatMachO() || IsOpenBSD || IsNetBSD) ? SignedLong : SignedInt; SizeType = (Triple.isOSDarwin() || Triple.isOSBinFormatMachO() || IsOpenBSD || IsNetBSD) ? UnsignedLong : UnsignedInt; // ptrdiff_t is inconsistent on Darwin if ((Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) && !Triple.isWatchABI()) PtrDiffType = SignedInt; // Cache arch related info. setArchInfo(); // {} in inline assembly are neon specifiers, not assembly variant // specifiers. NoAsmVariants = true; // FIXME: This duplicates code from the driver that sets the -target-abi // option - this code is used if -target-abi isn't passed and should // be unified in some way. if (Triple.isOSBinFormatMachO()) { // The backend is hardwired to assume AAPCS for M-class processors, ensure // the frontend matches that. if (Triple.getEnvironment() == llvm::Triple::EABI || Triple.getOS() == llvm::Triple::UnknownOS || ArchProfile == llvm::ARM::ProfileKind::M) { setABI("aapcs"); } else if (Triple.isWatchABI()) { setABI("aapcs16"); } else { setABI("apcs-gnu"); } } else if (Triple.isOSWindows()) { // FIXME: this is invalid for WindowsCE setABI("aapcs"); } else { // Select the default based on the platform. switch (Triple.getEnvironment()) { case llvm::Triple::Android: case llvm::Triple::GNUEABI: case llvm::Triple::GNUEABIHF: case llvm::Triple::MuslEABI: case llvm::Triple::MuslEABIHF: setABI("aapcs-linux"); break; case llvm::Triple::EABIHF: case llvm::Triple::EABI: setABI("aapcs"); break; case llvm::Triple::GNU: setABI("apcs-gnu"); break; default: if (IsNetBSD) setABI("apcs-gnu"); else if (IsOpenBSD) setABI("aapcs-linux"); else setABI("aapcs"); break; } } // ARM targets default to using the ARM C++ ABI. TheCXXABI.set(TargetCXXABI::GenericARM); // ARM has atomics up to 8 bytes setAtomic(); // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) // as well the default alignment if (IsAAPCS && !Triple.isAndroid()) DefaultAlignForAttributeAligned = MaxVectorAlign = 64; // Do force alignment of members that follow zero length bitfields. If // the alignment of the zero-length bitfield is greater than the member // that follows it, `bar', `bar' will be aligned as the type of the // zero length bitfield. UseZeroLengthBitfieldAlignment = true; if (Triple.getOS() == llvm::Triple::Linux || Triple.getOS() == llvm::Triple::UnknownOS) this->MCountName = Opts.EABIVersion == llvm::EABI::GNU ? "llvm.arm.gnu.eabi.mcount" : "\01mcount"; SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi"); } StringRef ARMTargetInfo::getABI() const { return ABI; } bool ARMTargetInfo::setABI(const std::string &Name) { ABI = Name; // The defaults (above) are for AAPCS, check if we need to change them. // // FIXME: We need support for -meabi... we could just mangle it into the // name. if (Name == "apcs-gnu" || Name == "aapcs16") { setABIAPCS(Name == "aapcs16"); return true; } if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { setABIAAPCS(); return true; } return false; } // FIXME: This should be based on Arch attributes, not CPU names. bool ARMTargetInfo::initFeatureMap( llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector &FeaturesVec) const { std::string ArchFeature; std::vector TargetFeatures; llvm::ARM::ArchKind Arch = llvm::ARM::parseArch(getTriple().getArchName()); // Map the base architecture to an appropriate target feature, so we don't // rely on the target triple. llvm::ARM::ArchKind CPUArch = llvm::ARM::parseCPUArch(CPU); if (CPUArch == llvm::ARM::ArchKind::INVALID) CPUArch = Arch; if (CPUArch != llvm::ARM::ArchKind::INVALID) { ArchFeature = ("+" + llvm::ARM::getArchName(CPUArch)).str(); TargetFeatures.push_back(ArchFeature); } // get default FPU features unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); // get default Extension features uint64_t Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); for (auto Feature : TargetFeatures) if (Feature[0] == '+') Features[Feature.drop_front(1)] = true; // Enable or disable thumb-mode explicitly per function to enable mixed // ARM and Thumb code generation. if (isThumb()) Features["thumb-mode"] = true; else Features["thumb-mode"] = false; // Convert user-provided arm and thumb GNU target attributes to // [-|+]thumb-mode target features respectively. std::vector UpdatedFeaturesVec; for (const auto &Feature : FeaturesVec) { // Skip soft-float-abi; it's something we only use to initialize a bit of // class state, and is otherwise unrecognized. if (Feature == "+soft-float-abi") continue; StringRef FixedFeature; if (Feature == "+arm") FixedFeature = "-thumb-mode"; else if (Feature == "+thumb") FixedFeature = "+thumb-mode"; else FixedFeature = Feature; UpdatedFeaturesVec.push_back(FixedFeature.str()); } return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); } bool ARMTargetInfo::handleTargetFeatures(std::vector &Features, DiagnosticsEngine &Diags) { FPU = 0; MVE = 0; CRC = 0; Crypto = 0; SHA2 = 0; AES = 0; DSP = 0; Unaligned = 1; SoftFloat = false; // Note that SoftFloatABI is initialized in our constructor. HWDiv = 0; DotProd = 0; HasMatMul = 0; HasFloat16 = true; ARMCDECoprocMask = 0; HasBFloat16 = false; // This does not diagnose illegal cases like having both // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64". for (const auto &Feature : Features) { if (Feature == "+soft-float") { SoftFloat = true; } else if (Feature == "+vfp2sp" || Feature == "+vfp2") { FPU |= VFP2FPU; HW_FP |= HW_FP_SP; if (Feature == "+vfp2") HW_FP |= HW_FP_DP; } else if (Feature == "+vfp3sp" || Feature == "+vfp3d16sp" || Feature == "+vfp3" || Feature == "+vfp3d16") { FPU |= VFP3FPU; HW_FP |= HW_FP_SP; if (Feature == "+vfp3" || Feature == "+vfp3d16") HW_FP |= HW_FP_DP; } else if (Feature == "+vfp4sp" || Feature == "+vfp4d16sp" || Feature == "+vfp4" || Feature == "+vfp4d16") { FPU |= VFP4FPU; HW_FP |= HW_FP_SP | HW_FP_HP; if (Feature == "+vfp4" || Feature == "+vfp4d16") HW_FP |= HW_FP_DP; } else if (Feature == "+fp-armv8sp" || Feature == "+fp-armv8d16sp" || Feature == "+fp-armv8" || Feature == "+fp-armv8d16") { FPU |= FPARMV8; HW_FP |= HW_FP_SP | HW_FP_HP; if (Feature == "+fp-armv8" || Feature == "+fp-armv8d16") HW_FP |= HW_FP_DP; } else if (Feature == "+neon") { FPU |= NeonFPU; HW_FP |= HW_FP_SP; } else if (Feature == "+hwdiv") { HWDiv |= HWDivThumb; } else if (Feature == "+hwdiv-arm") { HWDiv |= HWDivARM; } else if (Feature == "+crc") { CRC = 1; } else if (Feature == "+crypto") { Crypto = 1; } else if (Feature == "+sha2") { SHA2 = 1; } else if (Feature == "+aes") { AES = 1; } else if (Feature == "+dsp") { DSP = 1; } else if (Feature == "+fp64") { HW_FP |= HW_FP_DP; } else if (Feature == "+8msecext") { if (CPUProfile != "M" || ArchVersion != 8) { Diags.Report(diag::err_target_unsupported_mcmse) << CPU; return false; } } else if (Feature == "+strict-align") { Unaligned = 0; } else if (Feature == "+fp16") { HW_FP |= HW_FP_HP; } else if (Feature == "+fullfp16") { HasLegalHalfType = true; } else if (Feature == "+dotprod") { DotProd = true; } else if (Feature == "+mve") { MVE |= MVE_INT; } else if (Feature == "+mve.fp") { HasLegalHalfType = true; FPU |= FPARMV8; MVE |= MVE_INT | MVE_FP; HW_FP |= HW_FP_SP | HW_FP_HP; } else if (Feature == "+i8mm") { HasMatMul = 1; } else if (Feature.size() == strlen("+cdecp0") && Feature >= "+cdecp0" && Feature <= "+cdecp7") { unsigned Coproc = Feature.back() - '0'; ARMCDECoprocMask |= (1U << Coproc); } else if (Feature == "+bf16") { HasBFloat16 = true; } } switch (ArchVersion) { case 6: if (ArchProfile == llvm::ARM::ProfileKind::M) LDREX = 0; else if (ArchKind == llvm::ARM::ArchKind::ARMV6K) LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; else LDREX = LDREX_W; break; case 7: if (ArchProfile == llvm::ARM::ProfileKind::M) LDREX = LDREX_W | LDREX_H | LDREX_B; else LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; break; case 8: LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; } if (!(FPU & NeonFPU) && FPMath == FP_Neon) { Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; return false; } if (FPMath == FP_Neon) Features.push_back("+neonfp"); else if (FPMath == FP_VFP) Features.push_back("-neonfp"); return true; } bool ARMTargetInfo::hasFeature(StringRef Feature) const { return llvm::StringSwitch(Feature) .Case("arm", true) .Case("aarch32", true) .Case("softfloat", SoftFloat) .Case("thumb", isThumb()) .Case("neon", (FPU & NeonFPU) && !SoftFloat) .Case("vfp", FPU && !SoftFloat) .Case("hwdiv", HWDiv & HWDivThumb) .Case("hwdiv-arm", HWDiv & HWDivARM) .Case("mve", hasMVE()) .Default(false); } bool ARMTargetInfo::hasBFloat16Type() const { return HasBFloat16 && !SoftFloat; } bool ARMTargetInfo::isValidCPUName(StringRef Name) const { return Name == "generic" || llvm::ARM::parseCPUArch(Name) != llvm::ARM::ArchKind::INVALID; } void ARMTargetInfo::fillValidCPUList(SmallVectorImpl &Values) const { llvm::ARM::fillValidCPUArchList(Values); } bool ARMTargetInfo::setCPU(const std::string &Name) { if (Name != "generic") setArchInfo(llvm::ARM::parseCPUArch(Name)); if (ArchKind == llvm::ARM::ArchKind::INVALID) return false; setAtomic(); CPU = Name; return true; } bool ARMTargetInfo::setFPMath(StringRef Name) { if (Name == "neon") { FPMath = FP_Neon; return true; } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || Name == "vfp4") { FPMath = FP_VFP; return true; } return false; } void ARMTargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); } void ARMTargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts, MacroBuilder &Builder) const { // Also include the ARMv8.1-A defines getTargetDefinesARMV81A(Opts, Builder); } void ARMTargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts, MacroBuilder &Builder) const { // Also include the ARMv8.2-A defines Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1"); getTargetDefinesARMV82A(Opts, Builder); } void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { // Target identification. Builder.defineMacro("__arm"); Builder.defineMacro("__arm__"); // For bare-metal none-eabi. if (getTriple().getOS() == llvm::Triple::UnknownOS && (getTriple().getEnvironment() == llvm::Triple::EABI || getTriple().getEnvironment() == llvm::Triple::EABIHF)) Builder.defineMacro("__ELF__"); // Target properties. Builder.defineMacro("__REGISTER_PREFIX__", ""); // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. if (getTriple().isWatchABI()) Builder.defineMacro("__ARM_ARCH_7K__", "2"); if (!CPUAttr.empty()) Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); // ACLE 6.4.1 ARM/Thumb instruction set architecture // __ARM_ARCH is defined as an integer value indicating the current ARM ISA Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); if (ArchVersion >= 8) { // ACLE 6.5.7 Crypto Extension // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained // feature macros for AES and SHA2 if (SHA2 && AES) Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); if (SHA2) Builder.defineMacro("__ARM_FEATURE_SHA2", "1"); if (AES) Builder.defineMacro("__ARM_FEATURE_AES", "1"); // ACLE 6.5.8 CRC32 Extension if (CRC) Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); // ACLE 6.5.10 Numeric Maximum and Minimum Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); // ACLE 6.5.9 Directed Rounding Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); } // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It // is not defined for the M-profile. // NOTE that the default profile is assumed to be 'A' if (CPUProfile.empty() || ArchProfile != llvm::ARM::ProfileKind::M) Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the // core supports the Thumb-2 ISA as found in the v6T2 architecture and all // v7 and v8 architectures excluding v8-M Baseline. if (supportsThumb2()) Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); else if (supportsThumb()) Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit // instruction set such as ARM or Thumb. Builder.defineMacro("__ARM_32BIT_STATE", "1"); // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. if (!CPUProfile.empty()) Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); // ACLE 6.4.3 Unaligned access supported in hardware if (Unaligned) Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); // ACLE 6.4.4 LDREX/STREX if (LDREX) Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + Twine::utohexstr(LDREX)); // ACLE 6.4.5 CLZ if (ArchVersion == 5 || (ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6) Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); // ACLE 6.5.1 Hardware Floating Point if (HW_FP) Builder.defineMacro("__ARM_FP", "0x" + Twine::utohexstr(HW_FP)); // ACLE predefines. Builder.defineMacro("__ARM_ACLE", "200"); // FP16 support (we currently only support IEEE format). Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); Builder.defineMacro("__ARM_FP16_ARGS", "1"); // ACLE 6.5.3 Fused multiply-accumulate (FMA) if (ArchVersion >= 7 && (FPU & VFP4FPU)) Builder.defineMacro("__ARM_FEATURE_FMA", "1"); // Subtarget options. // FIXME: It's more complicated than this and we don't really support // interworking. // Windows on ARM does not "support" interworking if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) Builder.defineMacro("__THUMB_INTERWORK__"); if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { // Embedded targets on Darwin follow AAPCS, but not EABI. // Windows on ARM follows AAPCS VFP, but does not conform to EABI. if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) Builder.defineMacro("__ARM_EABI__"); Builder.defineMacro("__ARM_PCS", "1"); } if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || ABI == "aapcs16") Builder.defineMacro("__ARM_PCS_VFP", "1"); if (SoftFloat) Builder.defineMacro("__SOFTFP__"); // ACLE position independent code macros. if (Opts.ROPI) Builder.defineMacro("__ARM_ROPI", "1"); if (Opts.RWPI) Builder.defineMacro("__ARM_RWPI", "1"); if (ArchKind == llvm::ARM::ArchKind::XSCALE) Builder.defineMacro("__XSCALE__"); if (isThumb()) { Builder.defineMacro("__THUMBEL__"); Builder.defineMacro("__thumb__"); if (supportsThumb2()) Builder.defineMacro("__thumb2__"); } // ACLE 6.4.9 32-bit SIMD instructions if ((CPUProfile != "M" && ArchVersion >= 6) || (CPUProfile == "M" && DSP)) Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); // ACLE 6.4.10 Hardware Integer Divide if (((HWDiv & HWDivThumb) && isThumb()) || ((HWDiv & HWDivARM) && !isThumb())) { Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); } // Note, this is always on in gcc, even though it doesn't make sense. Builder.defineMacro("__APCS_32__"); // __VFP_FP__ means that the floating-point format is VFP, not that a hardware // FPU is present. Moreover, the VFP format is the only one supported by // clang. For these reasons, this macro is always defined. Builder.defineMacro("__VFP_FP__"); if (FPUModeIsVFP((FPUMode)FPU)) { if (FPU & VFP2FPU) Builder.defineMacro("__ARM_VFPV2__"); if (FPU & VFP3FPU) Builder.defineMacro("__ARM_VFPV3__"); if (FPU & VFP4FPU) Builder.defineMacro("__ARM_VFPV4__"); if (FPU & FPARMV8) Builder.defineMacro("__ARM_FPV5__"); } // This only gets set when Neon instructions are actually available, unlike // the VFP define, hence the soft float and arch check. This is subtly // different from gcc, we follow the intent which was that it should be set // when Neon instructions are actually available. if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { Builder.defineMacro("__ARM_NEON", "1"); Builder.defineMacro("__ARM_NEON__"); // current AArch32 NEON implementations do not support double-precision // floating-point even when it is present in VFP. Builder.defineMacro("__ARM_NEON_FP", "0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP)); } if (hasMVE()) { Builder.defineMacro("__ARM_FEATURE_MVE", hasMVEFloat() ? "3" : "1"); } if (hasCDE()) { Builder.defineMacro("__ARM_FEATURE_CDE", "1"); Builder.defineMacro("__ARM_FEATURE_CDE_COPROC", "0x" + Twine::utohexstr(getARMCDECoprocMask())); } Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Twine(Opts.WCharSize ? Opts.WCharSize : 4)); Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4"); // CMSE if (ArchVersion == 8 && ArchProfile == llvm::ARM::ProfileKind::M) Builder.defineMacro("__ARM_FEATURE_CMSE", Opts.Cmse ? "3" : "1"); if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); } // ACLE 6.4.7 DSP instructions if (DSP) { Builder.defineMacro("__ARM_FEATURE_DSP", "1"); } // ACLE 6.4.8 Saturation instructions bool SAT = false; if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6) { Builder.defineMacro("__ARM_FEATURE_SAT", "1"); SAT = true; } // ACLE 6.4.6 Q (saturation) flag if (DSP || SAT) Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); if (Opts.UnsafeFPMath) Builder.defineMacro("__ARM_FP_FAST", "1"); // Armv8.2-A FP16 vector intrinsic if ((FPU & NeonFPU) && HasLegalHalfType) Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1"); // Armv8.2-A FP16 scalar intrinsics if (HasLegalHalfType) Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1"); // Armv8.2-A dot product intrinsics if (DotProd) Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1"); if (HasMatMul) Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1"); if (HasBFloat16) { Builder.defineMacro("__ARM_FEATURE_BF16", "1"); Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1"); Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1"); } switch (ArchKind) { default: break; case llvm::ARM::ArchKind::ARMV8_1A: getTargetDefinesARMV81A(Opts, Builder); break; case llvm::ARM::ArchKind::ARMV8_2A: getTargetDefinesARMV82A(Opts, Builder); break; case llvm::ARM::ArchKind::ARMV8_3A: case llvm::ARM::ArchKind::ARMV8_4A: case llvm::ARM::ArchKind::ARMV8_5A: case llvm::ARM::ArchKind::ARMV8_6A: getTargetDefinesARMV83A(Opts, Builder); break; } } const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr}, #include "clang/Basic/BuiltinsNEON.def" #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ {#ID, TYPE, ATTRS, nullptr, LANG, nullptr}, #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr}, +#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ + {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, #include "clang/Basic/BuiltinsARM.def" }; ArrayRef ARMTargetInfo::getTargetBuiltins() const { return llvm::makeArrayRef(BuiltinInfo, clang::ARM::LastTSBuiltin - Builtin::FirstTSBuiltin); } bool ARMTargetInfo::isCLZForZeroUndef() const { return false; } TargetInfo::BuiltinVaListKind ARMTargetInfo::getBuiltinVaListKind() const { return IsAAPCS ? AAPCSABIBuiltinVaList : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList); } const char *const ARMTargetInfo::GCCRegNames[] = { // Integer registers "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", // Float registers "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", // Double registers "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", // Quad registers "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"}; ArrayRef ARMTargetInfo::getGCCRegNames() const { return llvm::makeArrayRef(GCCRegNames); } const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { {{"a1"}, "r0"}, {{"a2"}, "r1"}, {{"a3"}, "r2"}, {{"a4"}, "r3"}, {{"v1"}, "r4"}, {{"v2"}, "r5"}, {{"v3"}, "r6"}, {{"v4"}, "r7"}, {{"v5"}, "r8"}, {{"v6", "rfp"}, "r9"}, {{"sl"}, "r10"}, {{"fp"}, "r11"}, {{"ip"}, "r12"}, {{"r13"}, "sp"}, {{"r14"}, "lr"}, {{"r15"}, "pc"}, // The S, D and Q registers overlap, but aren't really aliases; we // don't want to substitute one of these for a different-sized one. }; ArrayRef ARMTargetInfo::getGCCRegAliases() const { return llvm::makeArrayRef(GCCRegAliases); } bool ARMTargetInfo::validateAsmConstraint( const char *&Name, TargetInfo::ConstraintInfo &Info) const { switch (*Name) { default: break; case 'l': // r0-r7 if thumb, r0-r15 if ARM Info.setAllowsRegister(); return true; case 'h': // r8-r15, thumb only if (isThumb()) { Info.setAllowsRegister(); return true; } break; case 's': // An integer constant, but allowing only relocatable values. return true; case 't': // s0-s31, d0-d31, or q0-q15 case 'w': // s0-s15, d0-d7, or q0-q3 case 'x': // s0-s31, d0-d15, or q0-q7 Info.setAllowsRegister(); return true; case 'j': // An immediate integer between 0 and 65535 (valid for MOVW) // only available in ARMv6T2 and above if (CPUAttr.equals("6T2") || ArchVersion >= 7) { Info.setRequiresImmediate(0, 65535); return true; } break; case 'I': if (isThumb()) { if (!supportsThumb2()) Info.setRequiresImmediate(0, 255); else // FIXME: should check if immediate value would be valid for a Thumb2 // data-processing instruction Info.setRequiresImmediate(); } else // FIXME: should check if immediate value would be valid for an ARM // data-processing instruction Info.setRequiresImmediate(); return true; case 'J': if (isThumb() && !supportsThumb2()) Info.setRequiresImmediate(-255, -1); else Info.setRequiresImmediate(-4095, 4095); return true; case 'K': if (isThumb()) { if (!supportsThumb2()) // FIXME: should check if immediate value can be obtained from shifting // a value between 0 and 255 left by any amount Info.setRequiresImmediate(); else // FIXME: should check if immediate value would be valid for a Thumb2 // data-processing instruction when inverted Info.setRequiresImmediate(); } else // FIXME: should check if immediate value would be valid for an ARM // data-processing instruction when inverted Info.setRequiresImmediate(); return true; case 'L': if (isThumb()) { if (!supportsThumb2()) Info.setRequiresImmediate(-7, 7); else // FIXME: should check if immediate value would be valid for a Thumb2 // data-processing instruction when negated Info.setRequiresImmediate(); } else // FIXME: should check if immediate value would be valid for an ARM // data-processing instruction when negated Info.setRequiresImmediate(); return true; case 'M': if (isThumb() && !supportsThumb2()) // FIXME: should check if immediate value is a multiple of 4 between 0 and // 1020 Info.setRequiresImmediate(); else // FIXME: should check if immediate value is a power of two or a integer // between 0 and 32 Info.setRequiresImmediate(); return true; case 'N': // Thumb1 only if (isThumb() && !supportsThumb2()) { Info.setRequiresImmediate(0, 31); return true; } break; case 'O': // Thumb1 only if (isThumb() && !supportsThumb2()) { // FIXME: should check if immediate value is a multiple of 4 between -508 // and 508 Info.setRequiresImmediate(); return true; } break; case 'Q': // A memory address that is a single base register. Info.setAllowsMemory(); return true; case 'T': switch (Name[1]) { default: break; case 'e': // Even general-purpose register case 'o': // Odd general-purpose register Info.setAllowsRegister(); Name++; return true; } break; case 'U': // a memory reference... switch (Name[1]) { case 'q': // ...ARMV4 ldrsb case 'v': // ...VFP load/store (reg+constant offset) case 'y': // ...iWMMXt load/store case 't': // address valid for load/store opaque types wider // than 128-bits case 'n': // valid address for Neon doubleword vector load/store case 'm': // valid address for Neon element and structure load/store case 's': // valid address for non-offset loads/stores of quad-word // values in four ARM registers Info.setAllowsMemory(); Name++; return true; } break; } return false; } std::string ARMTargetInfo::convertConstraint(const char *&Constraint) const { std::string R; switch (*Constraint) { case 'U': // Two-character constraint; add "^" hint for later parsing. case 'T': R = std::string("^") + std::string(Constraint, 2); Constraint++; break; case 'p': // 'p' should be translated to 'r' by default. R = std::string("r"); break; default: return std::string(1, *Constraint); } return R; } bool ARMTargetInfo::validateConstraintModifier( StringRef Constraint, char Modifier, unsigned Size, std::string &SuggestedModifier) const { bool isOutput = (Constraint[0] == '='); bool isInOut = (Constraint[0] == '+'); // Strip off constraint modifiers. while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') Constraint = Constraint.substr(1); switch (Constraint[0]) { default: break; case 'r': { switch (Modifier) { default: return (isInOut || isOutput || Size <= 64); case 'q': // A register of size 32 cannot fit a vector type. return false; } } } return true; } const char *ARMTargetInfo::getClobbers() const { // FIXME: Is this really right? return ""; } TargetInfo::CallingConvCheckResult ARMTargetInfo::checkCallingConvention(CallingConv CC) const { switch (CC) { case CC_AAPCS: case CC_AAPCS_VFP: case CC_Swift: case CC_SwiftAsync: case CC_OpenCLKernel: return CCCR_OK; default: return CCCR_Warning; } } int ARMTargetInfo::getEHDataRegisterNumber(unsigned RegNo) const { if (RegNo == 0) return 0; if (RegNo == 1) return 1; return -1; } bool ARMTargetInfo::hasSjLjLowering() const { return true; } ARMleTargetInfo::ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : ARMTargetInfo(Triple, Opts) {} void ARMleTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__ARMEL__"); ARMTargetInfo::getTargetDefines(Opts, Builder); } ARMbeTargetInfo::ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : ARMTargetInfo(Triple, Opts) {} void ARMbeTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__ARMEB__"); Builder.defineMacro("__ARM_BIG_ENDIAN"); ARMTargetInfo::getTargetDefines(Opts, Builder); } WindowsARMTargetInfo::WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : WindowsTargetInfo(Triple, Opts), Triple(Triple) { } void WindowsARMTargetInfo::getVisualStudioDefines(const LangOptions &Opts, MacroBuilder &Builder) const { // FIXME: this is invalid for WindowsCE Builder.defineMacro("_M_ARM_NT", "1"); Builder.defineMacro("_M_ARMT", "_M_ARM"); Builder.defineMacro("_M_THUMB", "_M_ARM"); assert((Triple.getArch() == llvm::Triple::arm || Triple.getArch() == llvm::Triple::thumb) && "invalid architecture for Windows ARM target info"); unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); // TODO map the complete set of values // 31: VFPv3 40: VFPv4 Builder.defineMacro("_M_ARM_FP", "31"); } TargetInfo::BuiltinVaListKind WindowsARMTargetInfo::getBuiltinVaListKind() const { return TargetInfo::CharPtrBuiltinVaList; } TargetInfo::CallingConvCheckResult WindowsARMTargetInfo::checkCallingConvention(CallingConv CC) const { switch (CC) { case CC_X86StdCall: case CC_X86ThisCall: case CC_X86FastCall: case CC_X86VectorCall: return CCCR_Ignore; case CC_C: case CC_OpenCLKernel: case CC_PreserveMost: case CC_PreserveAll: case CC_Swift: case CC_SwiftAsync: return CCCR_OK; default: return CCCR_Warning; } } // Windows ARM + Itanium C++ ABI Target ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo( const llvm::Triple &Triple, const TargetOptions &Opts) : WindowsARMTargetInfo(Triple, Opts) { TheCXXABI.set(TargetCXXABI::GenericARM); } void ItaniumWindowsARMleTargetInfo::getTargetDefines( const LangOptions &Opts, MacroBuilder &Builder) const { WindowsARMTargetInfo::getTargetDefines(Opts, Builder); if (Opts.MSVCCompat) WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); } // Windows ARM, MS (C++) ABI MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : WindowsARMTargetInfo(Triple, Opts) { TheCXXABI.set(TargetCXXABI::Microsoft); } void MicrosoftARMleTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { WindowsARMTargetInfo::getTargetDefines(Opts, Builder); WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); } MinGWARMTargetInfo::MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : WindowsARMTargetInfo(Triple, Opts) { TheCXXABI.set(TargetCXXABI::GenericARM); } void MinGWARMTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { WindowsARMTargetInfo::getTargetDefines(Opts, Builder); Builder.defineMacro("_ARM_"); } CygwinARMTargetInfo::CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : ARMleTargetInfo(Triple, Opts) { this->WCharType = TargetInfo::UnsignedShort; TLSSupported = false; DoubleAlign = LongLongAlign = 64; resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"); } void CygwinARMTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { ARMleTargetInfo::getTargetDefines(Opts, Builder); Builder.defineMacro("_ARM_"); Builder.defineMacro("__CYGWIN__"); Builder.defineMacro("__CYGWIN32__"); DefineStd(Builder, "unix", Opts); if (Opts.CPlusPlus) Builder.defineMacro("_GNU_SOURCE"); } DarwinARMTargetInfo::DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : DarwinTargetInfo(Triple, Opts) { HasAlignMac68kSupport = true; // iOS always has 64-bit atomic instructions. // FIXME: This should be based off of the target features in // ARMleTargetInfo. MaxAtomicInlineWidth = 64; if (Triple.isWatchABI()) { // Darwin on iOS uses a variant of the ARM C++ ABI. TheCXXABI.set(TargetCXXABI::WatchOS); // BOOL should be a real boolean on the new ABI UseSignedCharForObjCBool = false; } else TheCXXABI.set(TargetCXXABI::iOS); } void DarwinARMTargetInfo::getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, MacroBuilder &Builder) const { getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); } RenderScript32TargetInfo::RenderScript32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), Triple.getOSName(), Triple.getEnvironmentName()), Opts) { IsRenderScriptTarget = true; LongWidth = LongAlign = 64; } void RenderScript32TargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__RENDERSCRIPT__"); ARMleTargetInfo::getTargetDefines(Opts, Builder); }