riscv: Vector Extension (RVV) support.

RVV is a scalable SIMD (Single Instruction, Multiple Data) extension
designed to accelerate data-intensive workload such as AI, machine-learning
and DSP.

RVV exposes vector-length agnostic (VLA) execution and programming model,
with implementation defined vector register file size, dynamic vector
length selection, flexible register grouping, and rich instruction
semantics, serving as the foundation for portable, high-throughput
data-parallel acceleration.

Spec: https://github.com/riscvarchive/riscv-v-spec

RVV extends a base scalar RISC-V ISA with 32 vector registers and seven
unprivileged control-status registers (CSRs) to control the engine. Each
vector register could be up to 2^16 bits in length, depending on
implementation.

• Detect the extension during boot time ("v" letter in the ISA string)
• Implement RVV management code in the machine-dependent interfaces that handle CPU and thread state
• Add memory-management code for vector state save area. The allocation for save area in thread's PCBs has to be dynamic as the length of registers varies across implementations
• Save and restore RVV state on context-switch, fork(), scheduler entry
• Enable the extension usage on the first instruction trap from userspace ("lazy" enable)
• Implement ucontext.h POSIX API

Differential Revision: https://reviews.freebsd.org/D56414