diff --git a/sys/dev/uart/uart_core.c b/sys/dev/uart/uart_core.c index 17dabd7d8017..08ac57657c2c 100644 --- a/sys/dev/uart/uart_core.c +++ b/sys/dev/uart/uart_core.c @@ -1,619 +1,646 @@ /*- * Copyright (c) 2003 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "uart_if.h" devclass_t uart_devclass; char uart_driver_name[] = "uart"; SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs = SLIST_HEAD_INITIALIZER(uart_sysdevs); static MALLOC_DEFINE(M_UART, "UART", "UART driver"); #ifndef UART_POLL_FREQ #define UART_POLL_FREQ 50 #endif static int uart_poll_freq = UART_POLL_FREQ; TUNABLE_INT("debug.uart_poll_freq", &uart_poll_freq); void uart_add_sysdev(struct uart_devinfo *di) { SLIST_INSERT_HEAD(&uart_sysdevs, di, next); } const char * uart_getname(struct uart_class *uc) { return ((uc != NULL) ? uc->name : NULL); } struct uart_ops * uart_getops(struct uart_class *uc) { return ((uc != NULL) ? uc->uc_ops : NULL); } int uart_getrange(struct uart_class *uc) { return ((uc != NULL) ? uc->uc_range : 0); } /* * Schedule a soft interrupt. We do this on the 0 to !0 transition * of the TTY pending interrupt status. */ void uart_sched_softih(struct uart_softc *sc, uint32_t ipend) { uint32_t new, old; do { old = sc->sc_ttypend; new = old | ipend; } while (!atomic_cmpset_32(&sc->sc_ttypend, old, new)); if ((old & SER_INT_MASK) == 0) swi_sched(sc->sc_softih, 0); } /* * A break condition has been detected. We treat the break condition as * a special case that should not happen during normal operation. When * the break condition is to be passed to higher levels in the form of * a NUL character, we really want the break to be in the right place in * the input stream. The overhead to achieve that is not in relation to * the exceptional nature of the break condition, so we permit ourselves * to be sloppy. */ static __inline int uart_intr_break(void *arg) { struct uart_softc *sc = arg; #if defined(KDB) if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { if (kdb_break()) return (0); } #endif if (sc->sc_opened) uart_sched_softih(sc, SER_INT_BREAK); return (0); } /* * Handle a receiver overrun situation. We lost at least 1 byte in the * input stream and it's our job to contain the situation. We grab as * much of the data we can, but otherwise flush the receiver FIFO to * create some breathing room. The net effect is that we avoid the * overrun condition to happen for the next X characters, where X is * related to the FIFO size at the cost of losing data right away. * So, instead of having multiple overrun interrupts in close proximity * to each other and possibly pessimizing UART interrupt latency for * other UARTs in a multiport configuration, we create a longer segment * of missing characters by freeing up the FIFO. * Each overrun condition is marked in the input buffer by a token. The * token represents the loss of at least one, but possible more bytes in * the input stream. */ static __inline int uart_intr_overrun(void *arg) { struct uart_softc *sc = arg; if (sc->sc_opened) { UART_RECEIVE(sc); if (uart_rx_put(sc, UART_STAT_OVERRUN)) sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; uart_sched_softih(sc, SER_INT_RXREADY); } UART_FLUSH(sc, UART_FLUSH_RECEIVER); return (0); } /* * Received data ready. */ static __inline int uart_intr_rxready(void *arg) { struct uart_softc *sc = arg; int rxp; rxp = sc->sc_rxput; UART_RECEIVE(sc); #if defined(KDB) if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { while (rxp != sc->sc_rxput) { kdb_alt_break(sc->sc_rxbuf[rxp++], &sc->sc_altbrk); if (rxp == sc->sc_rxbufsz) rxp = 0; } } #endif if (sc->sc_opened) uart_sched_softih(sc, SER_INT_RXREADY); else sc->sc_rxput = sc->sc_rxget; /* Ignore received data. */ return (1); } /* * Line or modem status change (OOB signalling). * We pass the signals to the software interrupt handler for further * processing. Note that we merge the delta bits, but set the state * bits. This is to avoid losing state transitions due to having more * than 1 hardware interrupt between software interrupts. */ static __inline int uart_intr_sigchg(void *arg) { struct uart_softc *sc = arg; int new, old, sig; sig = UART_GETSIG(sc); if (sc->sc_pps.ppsparam.mode & PPS_CAPTUREBOTH) { if (sig & UART_SIG_DPPS) { pps_capture(&sc->sc_pps); pps_event(&sc->sc_pps, (sig & UART_SIG_PPS) ? PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); } } /* * Keep track of signal changes, even when the device is not * opened. This allows us to inform upper layers about a * possible loss of DCD and thus the existence of a (possibly) * different connection when we have DCD back, during the time * that the device was closed. */ do { old = sc->sc_ttypend; new = old & ~SER_MASK_STATE; new |= sig & SER_INT_SIGMASK; } while (!atomic_cmpset_32(&sc->sc_ttypend, old, new)); if (sc->sc_opened) uart_sched_softih(sc, SER_INT_SIGCHG); return (1); } /* * The transmitter can accept more data. */ static __inline int uart_intr_txidle(void *arg) { struct uart_softc *sc = arg; if (sc->sc_txbusy) { sc->sc_txbusy = 0; uart_sched_softih(sc, SER_INT_TXIDLE); } return (0); } static int uart_intr(void *arg) { struct uart_softc *sc = arg; int cnt, ipend; if (sc->sc_leaving) return (FILTER_STRAY); cnt = 0; while (cnt < 20 && (ipend = UART_IPEND(sc)) != 0) { cnt++; if (ipend & SER_INT_OVERRUN) uart_intr_overrun(sc); if (ipend & SER_INT_BREAK) uart_intr_break(sc); if (ipend & SER_INT_RXREADY) uart_intr_rxready(sc); if (ipend & SER_INT_SIGCHG) uart_intr_sigchg(sc); if (ipend & SER_INT_TXIDLE) uart_intr_txidle(sc); } if (sc->sc_polled) { callout_reset(&sc->sc_timer, hz / uart_poll_freq, (timeout_t *)uart_intr, sc); } return ((cnt == 0) ? FILTER_STRAY : ((cnt == 20) ? FILTER_SCHEDULE_THREAD : FILTER_HANDLED)); } serdev_intr_t * uart_bus_ihand(device_t dev, int ipend) { switch (ipend) { case SER_INT_BREAK: return (uart_intr_break); case SER_INT_OVERRUN: return (uart_intr_overrun); case SER_INT_RXREADY: return (uart_intr_rxready); case SER_INT_SIGCHG: return (uart_intr_sigchg); case SER_INT_TXIDLE: return (uart_intr_txidle); } return (NULL); } int uart_bus_ipend(device_t dev) { struct uart_softc *sc; sc = device_get_softc(dev); return (UART_IPEND(sc)); } int uart_bus_sysdev(device_t dev) { struct uart_softc *sc; sc = device_get_softc(dev); return ((sc->sc_sysdev != NULL) ? 1 : 0); } int uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan) { struct uart_softc *sc; struct uart_devinfo *sysdev; int error; sc = device_get_softc(dev); /* * All uart_class references are weak. Check that the needed * class has been compiled-in. Fail if not. */ if (sc->sc_class == NULL) return (ENXIO); /* * Initialize the instance. Note that the instance (=softc) does * not necessarily match the hardware specific softc. We can't do * anything about it now, because we may not attach to the device. * Hardware drivers cannot use any of the class specific fields * while probing. */ kobj_init((kobj_t)sc, (kobj_class_t)sc->sc_class); sc->sc_dev = dev; if (device_get_desc(dev) == NULL) device_set_desc(dev, uart_getname(sc->sc_class)); /* * Allocate the register resource. We assume that all UARTs have * a single register window in either I/O port space or memory * mapped I/O space. Any UART that needs multiple windows will * consequently not be supported by this driver as-is. We try I/O * port space first because that's the common case. */ sc->sc_rrid = rid; sc->sc_rtype = SYS_RES_IOPORT; sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid, 0, ~0, uart_getrange(sc->sc_class), RF_ACTIVE); if (sc->sc_rres == NULL) { sc->sc_rrid = rid; sc->sc_rtype = SYS_RES_MEMORY; sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid, 0, ~0, uart_getrange(sc->sc_class), RF_ACTIVE); if (sc->sc_rres == NULL) return (ENXIO); } /* * Fill in the bus access structure and compare this device with * a possible console device and/or a debug port. We set the flags * in the softc so that the hardware dependent probe can adjust * accordingly. In general, you don't want to permanently disrupt * console I/O. */ sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); sc->sc_bas.bst = rman_get_bustag(sc->sc_rres); sc->sc_bas.chan = chan; sc->sc_bas.regshft = regshft; sc->sc_bas.rclk = (rclk == 0) ? sc->sc_class->uc_rclk : rclk; SLIST_FOREACH(sysdev, &uart_sysdevs, next) { if (chan == sysdev->bas.chan && uart_cpu_eqres(&sc->sc_bas, &sysdev->bas)) { /* XXX check if ops matches class. */ sc->sc_sysdev = sysdev; sysdev->bas.rclk = sc->sc_bas.rclk; } } error = UART_PROBE(sc); bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); return ((error) ? error : BUS_PROBE_DEFAULT); } int uart_bus_attach(device_t dev) { struct uart_softc *sc, *sc0; const char *sep; int error, filt; /* * The sc_class field defines the type of UART we're going to work * with and thus the size of the softc. Replace the generic softc * with one that matches the UART now that we're certain we handle * the device. */ sc0 = device_get_softc(dev); if (sc0->sc_class->size > sizeof(*sc)) { sc = malloc(sc0->sc_class->size, M_UART, M_WAITOK|M_ZERO); bcopy(sc0, sc, sizeof(*sc)); device_set_softc(dev, sc); } else sc = sc0; + /* + * Now that we know the softc for this device, connect the back + * pointer from the sysdev for this device, if any + */ + if (sc->sc_sysdev != NULL) + sc->sc_sysdev->sc = sc; + /* * Protect ourselves against interrupts while we're not completely * finished attaching and initializing. We don't expect interrupts * until after UART_ATTACH() though. */ sc->sc_leaving = 1; mtx_init(&sc->sc_hwmtx_s, "uart_hwmtx", NULL, MTX_SPIN); if (sc->sc_hwmtx == NULL) sc->sc_hwmtx = &sc->sc_hwmtx_s; /* * Re-allocate. We expect that the softc contains the information * collected by uart_bus_probe() intact. */ sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid, 0, ~0, uart_getrange(sc->sc_class), RF_ACTIVE); if (sc->sc_rres == NULL) { mtx_destroy(&sc->sc_hwmtx_s); return (ENXIO); } sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); sc->sc_bas.bst = rman_get_bustag(sc->sc_rres); /* * Ensure there is room for at least three full FIFOs of data in the * receive buffer (handles the case of low-level drivers with huge * FIFOs), and also ensure that there is no less than the historical * size of 384 bytes (handles the typical small-FIFO case). */ sc->sc_rxbufsz = MAX(384, sc->sc_rxfifosz * 3); sc->sc_rxbuf = malloc(sc->sc_rxbufsz * sizeof(*sc->sc_rxbuf), M_UART, M_WAITOK); sc->sc_txbuf = malloc(sc->sc_txfifosz * sizeof(*sc->sc_txbuf), M_UART, M_WAITOK); error = UART_ATTACH(sc); if (error) goto fail; if (sc->sc_hwiflow || sc->sc_hwoflow) { sep = ""; device_print_prettyname(dev); if (sc->sc_hwiflow) { printf("%sRTS iflow", sep); sep = ", "; } if (sc->sc_hwoflow) { printf("%sCTS oflow", sep); sep = ", "; } printf("\n"); } if (sc->sc_sysdev != NULL) { if (sc->sc_sysdev->baudrate == 0) { if (UART_IOCTL(sc, UART_IOCTL_BAUD, (intptr_t)&sc->sc_sysdev->baudrate) != 0) sc->sc_sysdev->baudrate = -1; } switch (sc->sc_sysdev->type) { case UART_DEV_CONSOLE: device_printf(dev, "console"); break; case UART_DEV_DBGPORT: device_printf(dev, "debug port"); break; case UART_DEV_KEYBOARD: device_printf(dev, "keyboard"); break; default: device_printf(dev, "unknown system device"); break; } printf(" (%d,%c,%d,%d)\n", sc->sc_sysdev->baudrate, "noems"[sc->sc_sysdev->parity], sc->sc_sysdev->databits, sc->sc_sysdev->stopbits); } sc->sc_pps.ppscap = PPS_CAPTUREBOTH; pps_init(&sc->sc_pps); sc->sc_leaving = 0; filt = uart_intr(sc); /* * Don't use interrupts if we couldn't clear any pending interrupt * conditions. We may have broken H/W and polling is probably the * safest thing to do. */ if (filt != FILTER_SCHEDULE_THREAD) { sc->sc_irid = 0; sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid, RF_ACTIVE | RF_SHAREABLE); } if (sc->sc_ires != NULL) { error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_TTY, uart_intr, NULL, sc, &sc->sc_icookie); sc->sc_fastintr = (error == 0) ? 1 : 0; if (!sc->sc_fastintr) error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_TTY | INTR_MPSAFE, NULL, (driver_intr_t *)uart_intr, sc, &sc->sc_icookie); if (error) { device_printf(dev, "could not activate interrupt\n"); bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, sc->sc_ires); sc->sc_ires = NULL; } } if (sc->sc_ires == NULL) { /* No interrupt resource. Force polled mode. */ sc->sc_polled = 1; callout_init(&sc->sc_timer, 1); } if (bootverbose && (sc->sc_fastintr || sc->sc_polled)) { sep = ""; device_print_prettyname(dev); if (sc->sc_fastintr) { printf("%sfast interrupt", sep); sep = ", "; } if (sc->sc_polled) { printf("%spolled mode (%dHz)", sep, uart_poll_freq); sep = ", "; } printf("\n"); } error = (sc->sc_sysdev != NULL && sc->sc_sysdev->attach != NULL) ? (*sc->sc_sysdev->attach)(sc) : uart_tty_attach(sc); if (error) goto fail; if (sc->sc_sysdev != NULL) sc->sc_sysdev->hwmtx = sc->sc_hwmtx; return (0); fail: free(sc->sc_txbuf, M_UART); free(sc->sc_rxbuf, M_UART); if (sc->sc_ires != NULL) { bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie); bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, sc->sc_ires); } bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); mtx_destroy(&sc->sc_hwmtx_s); return (error); } int uart_bus_detach(device_t dev) { struct uart_softc *sc; sc = device_get_softc(dev); sc->sc_leaving = 1; if (sc->sc_sysdev != NULL) sc->sc_sysdev->hwmtx = NULL; UART_DETACH(sc); if (sc->sc_sysdev != NULL && sc->sc_sysdev->detach != NULL) (*sc->sc_sysdev->detach)(sc); else uart_tty_detach(sc); free(sc->sc_txbuf, M_UART); free(sc->sc_rxbuf, M_UART); if (sc->sc_ires != NULL) { bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie); bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, sc->sc_ires); } bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); mtx_destroy(&sc->sc_hwmtx_s); if (sc->sc_class->size > sizeof(*sc)) { device_set_softc(dev, NULL); free(sc, M_UART); } else device_set_softc(dev, NULL); return (0); } int uart_bus_resume(device_t dev) { struct uart_softc *sc; sc = device_get_softc(dev); return (UART_ATTACH(sc)); } + +void +uart_grab(struct uart_devinfo *di) +{ + + uart_lock(di->hwmtx); + if (di->sc) + UART_GRAB(di->sc); + uart_unlock(di->hwmtx); +} + +void +uart_ungrab(struct uart_devinfo *di) +{ + + uart_lock(di->hwmtx); + if (di->sc) + UART_UNGRAB(di->sc); + uart_unlock(di->hwmtx); +} diff --git a/sys/dev/uart/uart_cpu.h b/sys/dev/uart/uart_cpu.h index 99ced1a2c0c3..2db04123ad0e 100644 --- a/sys/dev/uart/uart_cpu.h +++ b/sys/dev/uart/uart_cpu.h @@ -1,193 +1,175 @@ /*- * Copyright (c) 2003, 2004 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV_UART_CPU_H_ #define _DEV_UART_CPU_H_ #include #include #include +struct uart_softc; + /* * Low-level operations for use by console and/or debug port support. */ struct uart_ops { int (*probe)(struct uart_bas *); void (*init)(struct uart_bas *, int, int, int, int); void (*term)(struct uart_bas *); void (*putc)(struct uart_bas *, int); int (*rxready)(struct uart_bas *); int (*getc)(struct uart_bas *, struct mtx *); - void (*grab)(struct uart_bas *); - void (*ungrab)(struct uart_bas *); }; extern bus_space_tag_t uart_bus_space_io; extern bus_space_tag_t uart_bus_space_mem; /* * Console and debug port device info. */ -struct uart_softc; struct uart_devinfo { SLIST_ENTRY(uart_devinfo) next; struct uart_ops *ops; struct uart_bas bas; int baudrate; int databits; int stopbits; int parity; int type; #define UART_DEV_CONSOLE 0 #define UART_DEV_DBGPORT 1 #define UART_DEV_KEYBOARD 2 int (*attach)(struct uart_softc*); int (*detach)(struct uart_softc*); void *cookie; /* Type dependent use. */ struct mtx *hwmtx; + struct uart_softc *sc; /* valid only from start of attach */ }; int uart_cpu_eqres(struct uart_bas *, struct uart_bas *); int uart_cpu_getdev(int, struct uart_devinfo *); int uart_getenv(int, struct uart_devinfo *, struct uart_class *); const char *uart_getname(struct uart_class *); struct uart_ops *uart_getops(struct uart_class *); int uart_getrange(struct uart_class *); void uart_add_sysdev(struct uart_devinfo *); /* * Operations for low-level access to the UART. Primarily for use * by console and debug port logic. */ static __inline void uart_lock(struct mtx *hwmtx) { if (!kdb_active && hwmtx != NULL) mtx_lock_spin(hwmtx); } static __inline void uart_unlock(struct mtx *hwmtx) { if (!kdb_active && hwmtx != NULL) mtx_unlock_spin(hwmtx); } static __inline int uart_probe(struct uart_devinfo *di) { int res; uart_lock(di->hwmtx); res = di->ops->probe(&di->bas); uart_unlock(di->hwmtx); return (res); } static __inline void uart_init(struct uart_devinfo *di) { uart_lock(di->hwmtx); di->ops->init(&di->bas, di->baudrate, di->databits, di->stopbits, di->parity); uart_unlock(di->hwmtx); } static __inline void uart_term(struct uart_devinfo *di) { uart_lock(di->hwmtx); di->ops->term(&di->bas); uart_unlock(di->hwmtx); } static __inline void uart_putc(struct uart_devinfo *di, int c) { uart_lock(di->hwmtx); di->ops->putc(&di->bas, c); uart_unlock(di->hwmtx); } -static __inline void -uart_grab(struct uart_devinfo *di) -{ - - uart_lock(di->hwmtx); - if (di->ops->grab) - di->ops->grab(&di->bas); - uart_unlock(di->hwmtx); -} - -static __inline void -uart_ungrab(struct uart_devinfo *di) -{ - - uart_lock(di->hwmtx); - if (di->ops->ungrab) - di->ops->ungrab(&di->bas); - uart_unlock(di->hwmtx); -} - - static __inline int uart_rxready(struct uart_devinfo *di) { int res; uart_lock(di->hwmtx); res = di->ops->rxready(&di->bas); uart_unlock(di->hwmtx); return (res); } static __inline int uart_poll(struct uart_devinfo *di) { int res; uart_lock(di->hwmtx); if (di->ops->rxready(&di->bas)) res = di->ops->getc(&di->bas, NULL); else res = -1; uart_unlock(di->hwmtx); return (res); } static __inline int uart_getc(struct uart_devinfo *di) { return (di->ops->getc(&di->bas, di->hwmtx)); } +void uart_grab(struct uart_devinfo *di); +void uart_ungrab(struct uart_devinfo *di); + #endif /* _DEV_UART_CPU_H_ */ diff --git a/sys/dev/uart/uart_dev_imx.c b/sys/dev/uart/uart_dev_imx.c index 22ee8ccc83de..e99cf774e3d5 100644 --- a/sys/dev/uart/uart_dev_imx.c +++ b/sys/dev/uart/uart_dev_imx.c @@ -1,436 +1,450 @@ /*- * Copyright (c) 2012 The FreeBSD Foundation * All rights reserved. * * This software was developed by Oleksandr Rybalko under sponsorship * from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #include #include #include #include #include #include #include #include #include #include #include #include "uart_if.h" /* * Low-level UART interface. */ static int imx_uart_probe(struct uart_bas *bas); static void imx_uart_init(struct uart_bas *bas, int, int, int, int); static void imx_uart_term(struct uart_bas *bas); static void imx_uart_putc(struct uart_bas *bas, int); static int imx_uart_rxready(struct uart_bas *bas); static int imx_uart_getc(struct uart_bas *bas, struct mtx *); static struct uart_ops uart_imx_uart_ops = { .probe = imx_uart_probe, .init = imx_uart_init, .term = imx_uart_term, .putc = imx_uart_putc, .rxready = imx_uart_rxready, .getc = imx_uart_getc, }; static int imx_uart_probe(struct uart_bas *bas) { return (0); } static void imx_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { } static void imx_uart_term(struct uart_bas *bas) { } static void imx_uart_putc(struct uart_bas *bas, int c) { while (!(IS(bas, USR2, TXFE))) ; SETREG(bas, REG(UTXD), c); } static int imx_uart_rxready(struct uart_bas *bas) { return ((IS(bas, USR2, RDR)) ? 1 : 0); } static int imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx) { int c; uart_lock(hwmtx); while (!(IS(bas, USR2, RDR))) ; c = GETREG(bas, REG(URXD)); uart_unlock(hwmtx); #if defined(KDB) if (c & FLD(URXD, BRK)) { if (kdb_break()) return (0); } #endif return (c & 0xff); } /* * High-level UART interface. */ struct imx_uart_softc { struct uart_softc base; }; static int imx_uart_bus_attach(struct uart_softc *); static int imx_uart_bus_detach(struct uart_softc *); static int imx_uart_bus_flush(struct uart_softc *, int); static int imx_uart_bus_getsig(struct uart_softc *); static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t); static int imx_uart_bus_ipend(struct uart_softc *); static int imx_uart_bus_param(struct uart_softc *, int, int, int, int); static int imx_uart_bus_probe(struct uart_softc *); static int imx_uart_bus_receive(struct uart_softc *); static int imx_uart_bus_setsig(struct uart_softc *, int); static int imx_uart_bus_transmit(struct uart_softc *); +static void imx_uart_bus_grab(struct uart_softc *); +static void imx_uart_bus_ungrab(struct uart_softc *); static kobj_method_t imx_uart_methods[] = { KOBJMETHOD(uart_attach, imx_uart_bus_attach), KOBJMETHOD(uart_detach, imx_uart_bus_detach), KOBJMETHOD(uart_flush, imx_uart_bus_flush), KOBJMETHOD(uart_getsig, imx_uart_bus_getsig), KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl), KOBJMETHOD(uart_ipend, imx_uart_bus_ipend), KOBJMETHOD(uart_param, imx_uart_bus_param), KOBJMETHOD(uart_probe, imx_uart_bus_probe), KOBJMETHOD(uart_receive, imx_uart_bus_receive), KOBJMETHOD(uart_setsig, imx_uart_bus_setsig), KOBJMETHOD(uart_transmit, imx_uart_bus_transmit), + KOBJMETHOD(uart_grab, imx_uart_bus_grab), + KOBJMETHOD(uart_ungrab, imx_uart_bus_ungrab), { 0, 0 } }; struct uart_class uart_imx_class = { "imx", imx_uart_methods, sizeof(struct imx_uart_softc), .uc_ops = &uart_imx_uart_ops, .uc_range = 0x100, .uc_rclk = 24000000 /* TODO: get value from CCM */ }; #define SIGCHG(c, i, s, d) \ if (c) { \ i |= (i & s) ? s : s | d; \ } else { \ i = (i & s) ? (i & ~s) | d : i; \ } static int imx_uart_bus_attach(struct uart_softc *sc) { struct uart_bas *bas; struct uart_devinfo *di; bas = &sc->sc_bas; if (sc->sc_sysdev != NULL) { di = sc->sc_sysdev; imx_uart_init(bas, di->baudrate, di->databits, di->stopbits, di->parity); } else { imx_uart_init(bas, 115200, 8, 1, 0); } (void)imx_uart_bus_getsig(sc); - /* XXX workaround to have working console on mount prompt */ - if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE){ - DIS(bas, UCR4, DREN); - } else { - ENA(bas, UCR4, DREN); - } + ENA(bas, UCR4, DREN); DIS(bas, UCR1, RRDYEN); DIS(bas, UCR1, IDEN); DIS(bas, UCR3, RXDSEN); DIS(bas, UCR2, ATEN); DIS(bas, UCR1, TXMPTYEN); DIS(bas, UCR1, TRDYEN); DIS(bas, UCR4, TCEN); DIS(bas, UCR4, OREN); ENA(bas, UCR4, BKEN); DIS(bas, UCR4, WKEN); DIS(bas, UCR1, ADEN); DIS(bas, UCR3, ACIEN); DIS(bas, UCR2, ESCI); DIS(bas, UCR4, ENIRI); DIS(bas, UCR3, AIRINTEN); DIS(bas, UCR3, AWAKEN); DIS(bas, UCR3, FRAERREN); DIS(bas, UCR3, PARERREN); DIS(bas, UCR1, RTSDEN); DIS(bas, UCR2, RTSEN); DIS(bas, UCR3, DTREN); DIS(bas, UCR3, RI); DIS(bas, UCR3, DCD); DIS(bas, UCR3, DTRDEN); /* ACK all interrupts */ SETREG(bas, REG(USR1), 0xffff); SETREG(bas, REG(USR2), 0xffff); return (0); } static int imx_uart_bus_detach(struct uart_softc *sc) { SETREG(&sc->sc_bas, REG(UCR4), 0); return (0); } static int imx_uart_bus_flush(struct uart_softc *sc, int what) { /* TODO */ return (0); } static int imx_uart_bus_getsig(struct uart_softc *sc) { uint32_t new, old, sig; uint8_t bes; do { old = sc->sc_hwsig; sig = old; uart_lock(sc->sc_hwmtx); bes = GETREG(&sc->sc_bas, REG(USR2)); uart_unlock(sc->sc_hwmtx); /* XXX: chip can show delta */ SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD); new = sig & ~SER_MASK_DELTA; } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); return (sig); } static int imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) { struct uart_bas *bas; int error; bas = &sc->sc_bas; error = 0; uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: /* TODO */ break; case UART_IOCTL_BAUD: /* TODO */ *(int*)data = 115200; break; default: error = EINVAL; break; } uart_unlock(sc->sc_hwmtx); return (error); } static int imx_uart_bus_ipend(struct uart_softc *sc) { struct uart_bas *bas; int ipend; uint32_t usr1, usr2; uint32_t ucr1, ucr4; bas = &sc->sc_bas; ipend = 0; uart_lock(sc->sc_hwmtx); /* Read pending interrupts */ usr1 = GETREG(bas, REG(USR1)); usr2 = GETREG(bas, REG(USR2)); /* ACK interrupts */ SETREG(bas, REG(USR1), usr1); SETREG(bas, REG(USR2), usr2); ucr1 = GETREG(bas, REG(UCR1)); ucr4 = GETREG(bas, REG(UCR4)); if ((usr2 & FLD(USR2, TXFE)) && (ucr1 & FLD(UCR1, TXMPTYEN))) { DIS(bas, UCR1, TXMPTYEN); /* Continue TXing */ ipend |= SER_INT_TXIDLE; } if ((usr2 & FLD(USR2, RDR)) && (ucr4 & FLD(UCR4, DREN))) { DIS(bas, UCR4, DREN); /* Wow, new char on input */ ipend |= SER_INT_RXREADY; } if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN))) ipend |= SER_INT_BREAK; uart_unlock(sc->sc_hwmtx); return (ipend); } static int imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits, int stopbits, int parity) { uart_lock(sc->sc_hwmtx); imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity); uart_unlock(sc->sc_hwmtx); return (0); } static int imx_uart_bus_probe(struct uart_softc *sc) { int error; error = imx_uart_probe(&sc->sc_bas); if (error) return (error); sc->sc_rxfifosz = 1; sc->sc_txfifosz = 1; device_set_desc(sc->sc_dev, "imx_uart"); return (0); } static int imx_uart_bus_receive(struct uart_softc *sc) { struct uart_bas *bas; int xc, out; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); /* Read while we have anything in FIFO */ while (IS(bas, USR2, RDR)) { if (uart_rx_full(sc)) { /* No space left in input buffer */ sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; } out = 0; xc = GETREG(bas, REG(URXD)); /* We have valid char */ if (xc & FLD(URXD, CHARRDY)) out = xc & 0x000000ff; if (xc & FLD(URXD, FRMERR)) out |= UART_STAT_FRAMERR; if (xc & FLD(URXD, PRERR)) out |= UART_STAT_PARERR; if (xc & FLD(URXD, OVRRUN)) out |= UART_STAT_OVERRUN; if (xc & FLD(URXD, BRK)) out |= UART_STAT_BREAK; uart_rx_put(sc, out); } /* Reenable Data Ready interrupt */ ENA(bas, UCR4, DREN); uart_unlock(sc->sc_hwmtx); return (0); } static int imx_uart_bus_setsig(struct uart_softc *sc, int sig) { - /* TODO: implement (?) */ - - /* XXX workaround to have working console on mount prompt */ - /* Enable RX interrupt */ - if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) - if (!IS(&sc->sc_bas, UCR4, DREN)) - ENA(&sc->sc_bas, UCR4, DREN); return (0); } static int imx_uart_bus_transmit(struct uart_softc *sc) { struct uart_bas *bas = &sc->sc_bas; int i; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); /* Fill TX FIFO */ for (i = 0; i < sc->sc_txdatasz; i++) { SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff); } sc->sc_txbusy = 1; /* Call me when ready */ ENA(bas, UCR1, TXMPTYEN); uart_unlock(sc->sc_hwmtx); return (0); } + +static void +imx_uart_bus_grab(struct uart_softc *sc) +{ + struct uart_bas *bas = &sc->sc_bas; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + DIS(bas, UCR4, DREN); + uart_unlock(sc->sc_hwmtx); +} + +static void +imx_uart_bus_ungrab(struct uart_softc *sc) +{ + struct uart_bas *bas = &sc->sc_bas; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + ENA(bas, UCR4, DREN); + uart_unlock(sc->sc_hwmtx); +} diff --git a/sys/dev/uart/uart_dev_lpc.c b/sys/dev/uart/uart_dev_lpc.c index 708d343b76f4..08cebc9cdff0 100644 --- a/sys/dev/uart/uart_dev_lpc.c +++ b/sys/dev/uart/uart_dev_lpc.c @@ -1,892 +1,927 @@ /*- * Copyright (c) 2003 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include "uart_if.h" #define DEFAULT_RCLK (13 * 1000 * 1000) static bus_space_handle_t bsh_clkpwr; #define lpc_ns8250_get_clkreg(_bas, _reg) \ bus_space_read_4(fdtbus_bs_tag, bsh_clkpwr, (_reg)) #define lpc_ns8250_set_clkreg(_bas, _reg, _val) \ bus_space_write_4(fdtbus_bs_tag, bsh_clkpwr, (_reg), (_val)) /* * Clear pending interrupts. THRE is cleared by reading IIR. Data * that may have been received gets lost here. */ static void lpc_ns8250_clrint(struct uart_bas *bas) { uint8_t iir, lsr; iir = uart_getreg(bas, REG_IIR); while ((iir & IIR_NOPEND) == 0) { iir &= IIR_IMASK; if (iir == IIR_RLS) { lsr = uart_getreg(bas, REG_LSR); if (lsr & (LSR_BI|LSR_FE|LSR_PE)) (void)uart_getreg(bas, REG_DATA); } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) (void)uart_getreg(bas, REG_DATA); else if (iir == IIR_MLSC) (void)uart_getreg(bas, REG_MSR); uart_barrier(bas); iir = uart_getreg(bas, REG_IIR); } } static int lpc_ns8250_delay(struct uart_bas *bas) { uint32_t uclk; int x, y; uclk = lpc_ns8250_get_clkreg(bas, LPC_CLKPWR_UART_U5CLK); x = (uclk >> 8) & 0xff; y = uclk & 0xff; return (16000000 / (bas->rclk * x / y)); } static void lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y) { switch (baudrate) { case 2400: *x = 1; *y = 255; return; case 4800: *x = 1; *y = 169; return; case 9600: *x = 3; *y = 254; return; case 19200: *x = 3; *y = 127; return; case 38400: *x = 6; *y = 127; return; case 57600: *x = 9; *y = 127; return; default: case 115200: *x = 19; *y = 134; return; case 230400: *x = 19; *y = 67; return; case 460800: *x = 38; *y = 67; return; } } static int lpc_ns8250_drain(struct uart_bas *bas, int what) { int delay, limit; delay = lpc_ns8250_delay(bas); if (what & UART_DRAIN_TRANSMITTER) { /* * Pick an arbitrary high limit to avoid getting stuck in * an infinite loop when the hardware is broken. Make the * limit high enough to handle large FIFOs. */ limit = 10*1024; while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) DELAY(delay); if (limit == 0) { /* printf("lpc_ns8250: transmitter appears stuck... "); */ return (EIO); } } if (what & UART_DRAIN_RECEIVER) { /* * Pick an arbitrary high limit to avoid getting stuck in * an infinite loop when the hardware is broken. Make the * limit high enough to handle large FIFOs and integrated * UARTs. The HP rx2600 for example has 3 UARTs on the * management board that tend to get a lot of data send * to it when the UART is first activated. */ limit=10*4096; while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { (void)uart_getreg(bas, REG_DATA); uart_barrier(bas); DELAY(delay << 2); } if (limit == 0) { /* printf("lpc_ns8250: receiver appears broken... "); */ return (EIO); } } return (0); } /* * We can only flush UARTs with FIFOs. UARTs without FIFOs should be * drained. WARNING: this function clobbers the FIFO setting! */ static void lpc_ns8250_flush(struct uart_bas *bas, int what) { uint8_t fcr; fcr = FCR_ENABLE; if (what & UART_FLUSH_TRANSMITTER) fcr |= FCR_XMT_RST; if (what & UART_FLUSH_RECEIVER) fcr |= FCR_RCV_RST; uart_setreg(bas, REG_FCR, fcr); uart_barrier(bas); } static int lpc_ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { int xdiv, ydiv; uint8_t lcr; lcr = 0; if (databits >= 8) lcr |= LCR_8BITS; else if (databits == 7) lcr |= LCR_7BITS; else if (databits == 6) lcr |= LCR_6BITS; else lcr |= LCR_5BITS; if (stopbits > 1) lcr |= LCR_STOPB; lcr |= parity << 3; /* Set baudrate. */ if (baudrate > 0) { uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); uart_barrier(bas); uart_setreg(bas, REG_DLL, 0x00); uart_setreg(bas, REG_DLH, 0x00); uart_barrier(bas); lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv); lpc_ns8250_set_clkreg(bas, LPC_CLKPWR_UART_U5CLK, LPC_CLKPWR_UART_UCLK_X(xdiv) | LPC_CLKPWR_UART_UCLK_Y(ydiv)); } /* Set LCR and clear DLAB. */ uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); return (0); } /* * Low-level UART interface. */ static int lpc_ns8250_probe(struct uart_bas *bas); static void lpc_ns8250_init(struct uart_bas *bas, int, int, int, int); static void lpc_ns8250_term(struct uart_bas *bas); static void lpc_ns8250_putc(struct uart_bas *bas, int); static int lpc_ns8250_rxready(struct uart_bas *bas); static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *); static struct uart_ops uart_lpc_ns8250_ops = { .probe = lpc_ns8250_probe, .init = lpc_ns8250_init, .term = lpc_ns8250_term, .putc = lpc_ns8250_putc, .rxready = lpc_ns8250_rxready, .getc = lpc_ns8250_getc, }; static int lpc_ns8250_probe(struct uart_bas *bas) { #if 0 u_char val; /* Check known 0 bits that don't depend on DLAB. */ val = uart_getreg(bas, REG_IIR); if (val & 0x30) return (ENXIO); /* * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 * chip, but otherwise doesn't seem to have a function. In * other words, uart(4) works regardless. Ignore that bit so * the probe succeeds. */ val = uart_getreg(bas, REG_MCR); if (val & 0xa0) return (ENXIO); #endif return (0); } static void lpc_ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { u_char ier; u_long clkmode; /* Enable UART clock */ bus_space_map(fdtbus_bs_tag, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0, &bsh_clkpwr); clkmode = lpc_ns8250_get_clkreg(bas, LPC_UART_CLKMODE); lpc_ns8250_set_clkreg(bas, LPC_UART_CLKMODE, clkmode | LPC_UART_CLKMODE_UART5(1)); #if 0 /* Work around H/W bug */ uart_setreg(bas, REG_DATA, 0x00); #endif if (bas->rclk == 0) bas->rclk = DEFAULT_RCLK; lpc_ns8250_param(bas, baudrate, databits, stopbits, parity); /* Disable all interrupt sources. */ /* * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA * UARTs split the receive time-out interrupt bit out separately as * 0x10. This gets handled by ier_mask and ier_rxbits below. */ ier = uart_getreg(bas, REG_IER) & 0xe0; uart_setreg(bas, REG_IER, ier); uart_barrier(bas); /* Disable the FIFO (if present). */ uart_setreg(bas, REG_FCR, 0); uart_barrier(bas); /* Set RTS & DTR. */ uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); uart_barrier(bas); lpc_ns8250_clrint(bas); } static void lpc_ns8250_term(struct uart_bas *bas) { /* Clear RTS & DTR. */ uart_setreg(bas, REG_MCR, MCR_IE); uart_barrier(bas); } static void lpc_ns8250_putc(struct uart_bas *bas, int c) { int limit; limit = 250000; while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) DELAY(4); uart_setreg(bas, REG_DATA, c); uart_barrier(bas); limit = 250000; while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) DELAY(4); } static int lpc_ns8250_rxready(struct uart_bas *bas) { return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); } static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) { int c; uart_lock(hwmtx); while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { uart_unlock(hwmtx); DELAY(4); uart_lock(hwmtx); } c = uart_getreg(bas, REG_DATA); uart_unlock(hwmtx); return (c); } /* * High-level UART interface. */ struct lpc_ns8250_softc { struct uart_softc base; uint8_t fcr; uint8_t ier; uint8_t mcr; uint8_t ier_mask; uint8_t ier_rxbits; }; static int lpc_ns8250_bus_attach(struct uart_softc *); static int lpc_ns8250_bus_detach(struct uart_softc *); static int lpc_ns8250_bus_flush(struct uart_softc *, int); static int lpc_ns8250_bus_getsig(struct uart_softc *); static int lpc_ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); static int lpc_ns8250_bus_ipend(struct uart_softc *); static int lpc_ns8250_bus_param(struct uart_softc *, int, int, int, int); static int lpc_ns8250_bus_probe(struct uart_softc *); static int lpc_ns8250_bus_receive(struct uart_softc *); static int lpc_ns8250_bus_setsig(struct uart_softc *, int); static int lpc_ns8250_bus_transmit(struct uart_softc *); +static void lpc_ns8250_bus_grab(struct uart_softc *); +static void lpc_ns8250_bus_ungrab(struct uart_softc *); static kobj_method_t lpc_ns8250_methods[] = { KOBJMETHOD(uart_attach, lpc_ns8250_bus_attach), KOBJMETHOD(uart_detach, lpc_ns8250_bus_detach), KOBJMETHOD(uart_flush, lpc_ns8250_bus_flush), KOBJMETHOD(uart_getsig, lpc_ns8250_bus_getsig), KOBJMETHOD(uart_ioctl, lpc_ns8250_bus_ioctl), KOBJMETHOD(uart_ipend, lpc_ns8250_bus_ipend), KOBJMETHOD(uart_param, lpc_ns8250_bus_param), KOBJMETHOD(uart_probe, lpc_ns8250_bus_probe), KOBJMETHOD(uart_receive, lpc_ns8250_bus_receive), KOBJMETHOD(uart_setsig, lpc_ns8250_bus_setsig), KOBJMETHOD(uart_transmit, lpc_ns8250_bus_transmit), + KOBJMETHOD(uart_grab, lpc_ns8250_bus_grab), + KOBJMETHOD(uart_ungrab, lpc_ns8250_bus_ungrab), { 0, 0 } }; struct uart_class uart_lpc_class = { "lpc_ns8250", lpc_ns8250_methods, sizeof(struct lpc_ns8250_softc), .uc_ops = &uart_lpc_ns8250_ops, .uc_range = 8, .uc_rclk = DEFAULT_RCLK }; #define SIGCHG(c, i, s, d) \ if (c) { \ i |= (i & s) ? s : s | d; \ } else { \ i = (i & s) ? (i & ~s) | d : i; \ } static int lpc_ns8250_bus_attach(struct uart_softc *sc) { struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; struct uart_bas *bas; unsigned int ivar; bas = &sc->sc_bas; lpc_ns8250->mcr = uart_getreg(bas, REG_MCR); lpc_ns8250->fcr = FCR_ENABLE | FCR_DMA; if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", &ivar)) { if (UART_FLAGS_FCR_RX_LOW(ivar)) lpc_ns8250->fcr |= FCR_RX_LOW; else if (UART_FLAGS_FCR_RX_MEDL(ivar)) lpc_ns8250->fcr |= FCR_RX_MEDL; else if (UART_FLAGS_FCR_RX_HIGH(ivar)) lpc_ns8250->fcr |= FCR_RX_HIGH; else lpc_ns8250->fcr |= FCR_RX_MEDH; } else lpc_ns8250->fcr |= FCR_RX_HIGH; /* Get IER mask */ ivar = 0xf0; resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", &ivar); lpc_ns8250->ier_mask = (uint8_t)(ivar & 0xff); /* Get IER RX interrupt bits */ ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", &ivar); lpc_ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); uart_setreg(bas, REG_FCR, lpc_ns8250->fcr); uart_barrier(bas); lpc_ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); if (lpc_ns8250->mcr & MCR_DTR) sc->sc_hwsig |= SER_DTR; if (lpc_ns8250->mcr & MCR_RTS) sc->sc_hwsig |= SER_RTS; lpc_ns8250_bus_getsig(sc); lpc_ns8250_clrint(bas); lpc_ns8250->ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; lpc_ns8250->ier |= lpc_ns8250->ier_rxbits; uart_setreg(bas, REG_IER, lpc_ns8250->ier); uart_barrier(bas); return (0); } static int lpc_ns8250_bus_detach(struct uart_softc *sc) { struct lpc_ns8250_softc *lpc_ns8250; struct uart_bas *bas; u_char ier; lpc_ns8250 = (struct lpc_ns8250_softc *)sc; bas = &sc->sc_bas; ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; uart_setreg(bas, REG_IER, ier); uart_barrier(bas); lpc_ns8250_clrint(bas); return (0); } static int lpc_ns8250_bus_flush(struct uart_softc *sc, int what) { struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; struct uart_bas *bas; int error; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); if (sc->sc_rxfifosz > 1) { lpc_ns8250_flush(bas, what); uart_setreg(bas, REG_FCR, lpc_ns8250->fcr); uart_barrier(bas); error = 0; } else error = lpc_ns8250_drain(bas, what); uart_unlock(sc->sc_hwmtx); return (error); } static int lpc_ns8250_bus_getsig(struct uart_softc *sc) { uint32_t new, old, sig; uint8_t msr; do { old = sc->sc_hwsig; sig = old; uart_lock(sc->sc_hwmtx); msr = uart_getreg(&sc->sc_bas, REG_MSR); uart_unlock(sc->sc_hwmtx); SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); new = sig & ~SER_MASK_DELTA; } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); return (sig); } static int lpc_ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) { struct uart_bas *bas; int baudrate, divisor, error; uint8_t efr, lcr; bas = &sc->sc_bas; error = 0; uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: lcr = uart_getreg(bas, REG_LCR); if (data) lcr |= LCR_SBREAK; else lcr &= ~LCR_SBREAK; uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); break; case UART_IOCTL_IFLOW: lcr = uart_getreg(bas, REG_LCR); uart_barrier(bas); uart_setreg(bas, REG_LCR, 0xbf); uart_barrier(bas); efr = uart_getreg(bas, REG_EFR); if (data) efr |= EFR_RTS; else efr &= ~EFR_RTS; uart_setreg(bas, REG_EFR, efr); uart_barrier(bas); uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); break; case UART_IOCTL_OFLOW: lcr = uart_getreg(bas, REG_LCR); uart_barrier(bas); uart_setreg(bas, REG_LCR, 0xbf); uart_barrier(bas); efr = uart_getreg(bas, REG_EFR); if (data) efr |= EFR_CTS; else efr &= ~EFR_CTS; uart_setreg(bas, REG_EFR, efr); uart_barrier(bas); uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); break; case UART_IOCTL_BAUD: lcr = uart_getreg(bas, REG_LCR); uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); uart_barrier(bas); divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); uart_barrier(bas); uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; if (baudrate > 0) *(int*)data = baudrate; else error = ENXIO; break; default: error = EINVAL; break; } uart_unlock(sc->sc_hwmtx); return (error); } static int lpc_ns8250_bus_ipend(struct uart_softc *sc) { struct uart_bas *bas; struct lpc_ns8250_softc *lpc_ns8250; int ipend; uint8_t iir, lsr; lpc_ns8250 = (struct lpc_ns8250_softc *)sc; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); iir = uart_getreg(bas, REG_IIR); if (iir & IIR_NOPEND) { uart_unlock(sc->sc_hwmtx); return (0); } ipend = 0; if (iir & IIR_RXRDY) { lsr = uart_getreg(bas, REG_LSR); if (lsr & LSR_OE) ipend |= SER_INT_OVERRUN; if (lsr & LSR_BI) ipend |= SER_INT_BREAK; if (lsr & LSR_RXRDY) ipend |= SER_INT_RXREADY; } else { if (iir & IIR_TXRDY) { ipend |= SER_INT_TXIDLE; uart_setreg(bas, REG_IER, lpc_ns8250->ier); } else ipend |= SER_INT_SIGCHG; } if (ipend == 0) lpc_ns8250_clrint(bas); uart_unlock(sc->sc_hwmtx); return (ipend); } static int lpc_ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, int stopbits, int parity) { struct uart_bas *bas; int error; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); error = lpc_ns8250_param(bas, baudrate, databits, stopbits, parity); uart_unlock(sc->sc_hwmtx); return (error); } static int lpc_ns8250_bus_probe(struct uart_softc *sc) { struct lpc_ns8250_softc *lpc_ns8250; struct uart_bas *bas; int count, delay, error, limit; uint8_t lsr, mcr, ier; lpc_ns8250 = (struct lpc_ns8250_softc *)sc; bas = &sc->sc_bas; error = lpc_ns8250_probe(bas); if (error) return (error); mcr = MCR_IE; if (sc->sc_sysdev == NULL) { /* By using lpc_ns8250_init() we also set DTR and RTS. */ lpc_ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); } else mcr |= MCR_DTR | MCR_RTS; error = lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER); if (error) return (error); /* * Set loopback mode. This avoids having garbage on the wire and * also allows us send and receive data. We set DTR and RTS to * avoid the possibility that automatic flow-control prevents * any data from being sent. */ uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); uart_barrier(bas); /* * Enable FIFOs. And check that the UART has them. If not, we're * done. Since this is the first time we enable the FIFOs, we reset * them. */ uart_setreg(bas, REG_FCR, FCR_ENABLE); uart_barrier(bas); if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { /* * NS16450 or INS8250. We don't bother to differentiate * between them. They're too old to be interesting. */ uart_setreg(bas, REG_MCR, mcr); uart_barrier(bas); sc->sc_rxfifosz = sc->sc_txfifosz = 1; device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); return (0); } uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); uart_barrier(bas); count = 0; delay = lpc_ns8250_delay(bas); /* We have FIFOs. Drain the transmitter and receiver. */ error = lpc_ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); if (error) { uart_setreg(bas, REG_MCR, mcr); uart_setreg(bas, REG_FCR, 0); uart_barrier(bas); goto done; } /* * We should have a sufficiently clean "pipe" to determine the * size of the FIFOs. We send as much characters as is reasonable * and wait for the overflow bit in the LSR register to be * asserted, counting the characters as we send them. Based on * that count we know the FIFO size. */ do { uart_setreg(bas, REG_DATA, 0); uart_barrier(bas); count++; limit = 30; lsr = 0; /* * LSR bits are cleared upon read, so we must accumulate * them to be able to test LSR_OE below. */ while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && --limit) DELAY(delay); if (limit == 0) { ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; uart_setreg(bas, REG_IER, ier); uart_setreg(bas, REG_MCR, mcr); uart_setreg(bas, REG_FCR, 0); uart_barrier(bas); count = 0; goto done; } } while ((lsr & LSR_OE) == 0 && count < 130); count--; uart_setreg(bas, REG_MCR, mcr); /* Reset FIFOs. */ lpc_ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); done: sc->sc_rxfifosz = 64; device_set_desc(sc->sc_dev, "LPC32x0 UART with FIFOs"); /* * Force the Tx FIFO size to 16 bytes for now. We don't program the * Tx trigger. Also, we assume that all data has been sent when the * interrupt happens. */ sc->sc_txfifosz = 16; #if 0 /* * XXX there are some issues related to hardware flow control and * it's likely that uart(4) is the cause. This basicly needs more * investigation, but we avoid using for hardware flow control * until then. */ /* 16650s or higher have automatic flow control. */ if (sc->sc_rxfifosz > 16) { sc->sc_hwiflow = 1; sc->sc_hwoflow = 1; } #endif return (0); } static int lpc_ns8250_bus_receive(struct uart_softc *sc) { struct uart_bas *bas; int xc; uint8_t lsr; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); lsr = uart_getreg(bas, REG_LSR); while (lsr & LSR_RXRDY) { if (uart_rx_full(sc)) { sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; } xc = uart_getreg(bas, REG_DATA); if (lsr & LSR_FE) xc |= UART_STAT_FRAMERR; if (lsr & LSR_PE) xc |= UART_STAT_PARERR; uart_rx_put(sc, xc); lsr = uart_getreg(bas, REG_LSR); } /* Discard everything left in the Rx FIFO. */ while (lsr & LSR_RXRDY) { (void)uart_getreg(bas, REG_DATA); uart_barrier(bas); lsr = uart_getreg(bas, REG_LSR); } uart_unlock(sc->sc_hwmtx); return (0); } static int lpc_ns8250_bus_setsig(struct uart_softc *sc, int sig) { struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; struct uart_bas *bas; uint32_t new, old; bas = &sc->sc_bas; do { old = sc->sc_hwsig; new = old; if (sig & SER_DDTR) { SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); } if (sig & SER_DRTS) { SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); } } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); uart_lock(sc->sc_hwmtx); lpc_ns8250->mcr &= ~(MCR_DTR|MCR_RTS); if (new & SER_DTR) lpc_ns8250->mcr |= MCR_DTR; if (new & SER_RTS) lpc_ns8250->mcr |= MCR_RTS; uart_setreg(bas, REG_MCR, lpc_ns8250->mcr); uart_barrier(bas); uart_unlock(sc->sc_hwmtx); return (0); } static int lpc_ns8250_bus_transmit(struct uart_softc *sc) { struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; struct uart_bas *bas; int i; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) ; uart_setreg(bas, REG_IER, lpc_ns8250->ier | IER_ETXRDY); uart_barrier(bas); for (i = 0; i < sc->sc_txdatasz; i++) { uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); uart_barrier(bas); } sc->sc_txbusy = 1; uart_unlock(sc->sc_hwmtx); return (0); } + +void +lpc_ns8250_bus_grab(struct uart_softc *sc) +{ + struct uart_bas *bas = &sc->sc_bas; + + /* + * turn off all interrupts to enter polling mode. Leave the + * saved mask alone. We'll restore whatever it was in ungrab. + * All pending interupt signals are reset when IER is set to 0. + */ + uart_lock(sc->sc_hwmtx); + uart_setreg(bas, REG_IER, 0); + uart_barrier(bas); + uart_unlock(sc->sc_hwmtx); +} + +void +lpc_ns8250_bus_ungrab(struct uart_softc *sc) +{ + struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; + struct uart_bas *bas = &sc->sc_bas; + + /* + * Restore previous interrupt mask + */ + uart_lock(sc->sc_hwmtx); + uart_setreg(bas, REG_IER, lpc_ns8250->ier); + uart_barrier(bas); + uart_unlock(sc->sc_hwmtx); +} diff --git a/sys/dev/uart/uart_dev_ns8250.c b/sys/dev/uart/uart_dev_ns8250.c index 249be4ce0e33..47a61bfa6014 100644 --- a/sys/dev/uart/uart_dev_ns8250.c +++ b/sys/dev/uart/uart_dev_ns8250.c @@ -1,924 +1,957 @@ /*- * Copyright (c) 2003 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #ifdef FDT #include #include #include #endif #include #include #include #include #include #include "uart_if.h" #define DEFAULT_RCLK 1843200 static int broken_txfifo = 0; SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN, &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); TUNABLE_INT("hw.broken_txfifo", &broken_txfifo); /* * Clear pending interrupts. THRE is cleared by reading IIR. Data * that may have been received gets lost here. */ static void ns8250_clrint(struct uart_bas *bas) { uint8_t iir, lsr; iir = uart_getreg(bas, REG_IIR); while ((iir & IIR_NOPEND) == 0) { iir &= IIR_IMASK; if (iir == IIR_RLS) { lsr = uart_getreg(bas, REG_LSR); if (lsr & (LSR_BI|LSR_FE|LSR_PE)) (void)uart_getreg(bas, REG_DATA); } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) (void)uart_getreg(bas, REG_DATA); else if (iir == IIR_MLSC) (void)uart_getreg(bas, REG_MSR); uart_barrier(bas); iir = uart_getreg(bas, REG_IIR); } } static int ns8250_delay(struct uart_bas *bas) { int divisor; u_char lcr; lcr = uart_getreg(bas, REG_LCR); uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); uart_barrier(bas); divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); uart_barrier(bas); uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); /* 1/10th the time to transmit 1 character (estimate). */ if (divisor <= 134) return (16000000 * divisor / bas->rclk); return (16000 * divisor / (bas->rclk / 1000)); } static int ns8250_divisor(int rclk, int baudrate) { int actual_baud, divisor; int error; if (baudrate == 0) return (0); divisor = (rclk / (baudrate << 3) + 1) >> 1; if (divisor == 0 || divisor >= 65536) return (0); actual_baud = rclk / (divisor << 4); /* 10 times error in percent: */ error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; /* 3.0% maximum error tolerance: */ if (error < -30 || error > 30) return (0); return (divisor); } static int ns8250_drain(struct uart_bas *bas, int what) { int delay, limit; delay = ns8250_delay(bas); if (what & UART_DRAIN_TRANSMITTER) { /* * Pick an arbitrary high limit to avoid getting stuck in * an infinite loop when the hardware is broken. Make the * limit high enough to handle large FIFOs. */ limit = 10*1024; while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) DELAY(delay); if (limit == 0) { /* printf("ns8250: transmitter appears stuck... "); */ return (EIO); } } if (what & UART_DRAIN_RECEIVER) { /* * Pick an arbitrary high limit to avoid getting stuck in * an infinite loop when the hardware is broken. Make the * limit high enough to handle large FIFOs and integrated * UARTs. The HP rx2600 for example has 3 UARTs on the * management board that tend to get a lot of data send * to it when the UART is first activated. */ limit=10*4096; while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { (void)uart_getreg(bas, REG_DATA); uart_barrier(bas); DELAY(delay << 2); } if (limit == 0) { /* printf("ns8250: receiver appears broken... "); */ return (EIO); } } return (0); } /* * We can only flush UARTs with FIFOs. UARTs without FIFOs should be * drained. WARNING: this function clobbers the FIFO setting! */ static void ns8250_flush(struct uart_bas *bas, int what) { uint8_t fcr; fcr = FCR_ENABLE; if (what & UART_FLUSH_TRANSMITTER) fcr |= FCR_XMT_RST; if (what & UART_FLUSH_RECEIVER) fcr |= FCR_RCV_RST; uart_setreg(bas, REG_FCR, fcr); uart_barrier(bas); } static int ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { int divisor; uint8_t lcr; lcr = 0; if (databits >= 8) lcr |= LCR_8BITS; else if (databits == 7) lcr |= LCR_7BITS; else if (databits == 6) lcr |= LCR_6BITS; else lcr |= LCR_5BITS; if (stopbits > 1) lcr |= LCR_STOPB; lcr |= parity << 3; /* Set baudrate. */ if (baudrate > 0) { divisor = ns8250_divisor(bas->rclk, baudrate); if (divisor == 0) return (EINVAL); uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); uart_barrier(bas); uart_setreg(bas, REG_DLL, divisor & 0xff); uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); uart_barrier(bas); } /* Set LCR and clear DLAB. */ uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); return (0); } /* * Low-level UART interface. */ static int ns8250_probe(struct uart_bas *bas); static void ns8250_init(struct uart_bas *bas, int, int, int, int); static void ns8250_term(struct uart_bas *bas); static void ns8250_putc(struct uart_bas *bas, int); static int ns8250_rxready(struct uart_bas *bas); static int ns8250_getc(struct uart_bas *bas, struct mtx *); struct uart_ops uart_ns8250_ops = { .probe = ns8250_probe, .init = ns8250_init, .term = ns8250_term, .putc = ns8250_putc, .rxready = ns8250_rxready, .getc = ns8250_getc, }; static int ns8250_probe(struct uart_bas *bas) { u_char val; /* Check known 0 bits that don't depend on DLAB. */ val = uart_getreg(bas, REG_IIR); if (val & 0x30) return (ENXIO); /* * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 * chip, but otherwise doesn't seem to have a function. In * other words, uart(4) works regardless. Ignore that bit so * the probe succeeds. */ val = uart_getreg(bas, REG_MCR); if (val & 0xa0) return (ENXIO); return (0); } static void ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { u_char ier; if (bas->rclk == 0) bas->rclk = DEFAULT_RCLK; ns8250_param(bas, baudrate, databits, stopbits, parity); /* Disable all interrupt sources. */ /* * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA * UARTs split the receive time-out interrupt bit out separately as * 0x10. This gets handled by ier_mask and ier_rxbits below. */ ier = uart_getreg(bas, REG_IER) & 0xe0; uart_setreg(bas, REG_IER, ier); uart_barrier(bas); /* Disable the FIFO (if present). */ uart_setreg(bas, REG_FCR, 0); uart_barrier(bas); /* Set RTS & DTR. */ uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); uart_barrier(bas); ns8250_clrint(bas); } static void ns8250_term(struct uart_bas *bas) { /* Clear RTS & DTR. */ uart_setreg(bas, REG_MCR, MCR_IE); uart_barrier(bas); } static void ns8250_putc(struct uart_bas *bas, int c) { int limit; limit = 250000; while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) DELAY(4); uart_setreg(bas, REG_DATA, c); uart_barrier(bas); limit = 250000; while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) DELAY(4); } static int ns8250_rxready(struct uart_bas *bas) { return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); } static int ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) { int c; uart_lock(hwmtx); while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { uart_unlock(hwmtx); DELAY(4); uart_lock(hwmtx); } c = uart_getreg(bas, REG_DATA); uart_unlock(hwmtx); return (c); } static kobj_method_t ns8250_methods[] = { KOBJMETHOD(uart_attach, ns8250_bus_attach), KOBJMETHOD(uart_detach, ns8250_bus_detach), KOBJMETHOD(uart_flush, ns8250_bus_flush), KOBJMETHOD(uart_getsig, ns8250_bus_getsig), KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), KOBJMETHOD(uart_ipend, ns8250_bus_ipend), KOBJMETHOD(uart_param, ns8250_bus_param), KOBJMETHOD(uart_probe, ns8250_bus_probe), KOBJMETHOD(uart_receive, ns8250_bus_receive), KOBJMETHOD(uart_setsig, ns8250_bus_setsig), KOBJMETHOD(uart_transmit, ns8250_bus_transmit), + KOBJMETHOD(uart_grab, ns8250_bus_grab), + KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), { 0, 0 } }; struct uart_class uart_ns8250_class = { "ns8250", ns8250_methods, sizeof(struct ns8250_softc), .uc_ops = &uart_ns8250_ops, .uc_range = 8, .uc_rclk = DEFAULT_RCLK }; #define SIGCHG(c, i, s, d) \ if (c) { \ i |= (i & s) ? s : s | d; \ } else { \ i = (i & s) ? (i & ~s) | d : i; \ } int ns8250_bus_attach(struct uart_softc *sc) { struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; struct uart_bas *bas; unsigned int ivar; #ifdef FDT phandle_t node; pcell_t cell; #endif ns8250->busy_detect = 0; #ifdef FDT /* * Check whether uart requires to read USR reg when IIR_BUSY and * has broken txfifo. */ node = ofw_bus_get_node(sc->sc_dev); if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) ns8250->busy_detect = 1; if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) broken_txfifo = 1; #endif bas = &sc->sc_bas; ns8250->mcr = uart_getreg(bas, REG_MCR); ns8250->fcr = FCR_ENABLE; if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", &ivar)) { if (UART_FLAGS_FCR_RX_LOW(ivar)) ns8250->fcr |= FCR_RX_LOW; else if (UART_FLAGS_FCR_RX_MEDL(ivar)) ns8250->fcr |= FCR_RX_MEDL; else if (UART_FLAGS_FCR_RX_HIGH(ivar)) ns8250->fcr |= FCR_RX_HIGH; else ns8250->fcr |= FCR_RX_MEDH; } else ns8250->fcr |= FCR_RX_MEDH; /* Get IER mask */ ivar = 0xf0; resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", &ivar); ns8250->ier_mask = (uint8_t)(ivar & 0xff); /* Get IER RX interrupt bits */ ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", &ivar); ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); uart_setreg(bas, REG_FCR, ns8250->fcr); uart_barrier(bas); ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); if (ns8250->mcr & MCR_DTR) sc->sc_hwsig |= SER_DTR; if (ns8250->mcr & MCR_RTS) sc->sc_hwsig |= SER_RTS; ns8250_bus_getsig(sc); ns8250_clrint(bas); ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; ns8250->ier |= ns8250->ier_rxbits; uart_setreg(bas, REG_IER, ns8250->ier); uart_barrier(bas); /* * Timing of the H/W access was changed with r253161 of uart_core.c * It has been observed that an ITE IT8513E would signal a break * condition with pretty much every character it received, unless * it had enough time to settle between ns8250_bus_attach() and * ns8250_bus_ipend() -- which it accidentally had before r253161. * It's not understood why the UART chip behaves this way and it * could very well be that the DELAY make the H/W work in the same * accidental manner as before. More analysis is warranted, but * at least now we fixed a known regression. */ DELAY(200); return (0); } int ns8250_bus_detach(struct uart_softc *sc) { struct ns8250_softc *ns8250; struct uart_bas *bas; u_char ier; ns8250 = (struct ns8250_softc *)sc; bas = &sc->sc_bas; ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; uart_setreg(bas, REG_IER, ier); uart_barrier(bas); ns8250_clrint(bas); return (0); } int ns8250_bus_flush(struct uart_softc *sc, int what) { struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; struct uart_bas *bas; int error; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); if (sc->sc_rxfifosz > 1) { ns8250_flush(bas, what); uart_setreg(bas, REG_FCR, ns8250->fcr); uart_barrier(bas); error = 0; } else error = ns8250_drain(bas, what); uart_unlock(sc->sc_hwmtx); return (error); } int ns8250_bus_getsig(struct uart_softc *sc) { uint32_t new, old, sig; uint8_t msr; do { old = sc->sc_hwsig; sig = old; uart_lock(sc->sc_hwmtx); msr = uart_getreg(&sc->sc_bas, REG_MSR); uart_unlock(sc->sc_hwmtx); SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); new = sig & ~SER_MASK_DELTA; } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); return (sig); } int ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) { struct uart_bas *bas; int baudrate, divisor, error; uint8_t efr, lcr; bas = &sc->sc_bas; error = 0; uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: lcr = uart_getreg(bas, REG_LCR); if (data) lcr |= LCR_SBREAK; else lcr &= ~LCR_SBREAK; uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); break; case UART_IOCTL_IFLOW: lcr = uart_getreg(bas, REG_LCR); uart_barrier(bas); uart_setreg(bas, REG_LCR, 0xbf); uart_barrier(bas); efr = uart_getreg(bas, REG_EFR); if (data) efr |= EFR_RTS; else efr &= ~EFR_RTS; uart_setreg(bas, REG_EFR, efr); uart_barrier(bas); uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); break; case UART_IOCTL_OFLOW: lcr = uart_getreg(bas, REG_LCR); uart_barrier(bas); uart_setreg(bas, REG_LCR, 0xbf); uart_barrier(bas); efr = uart_getreg(bas, REG_EFR); if (data) efr |= EFR_CTS; else efr &= ~EFR_CTS; uart_setreg(bas, REG_EFR, efr); uart_barrier(bas); uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); break; case UART_IOCTL_BAUD: lcr = uart_getreg(bas, REG_LCR); uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); uart_barrier(bas); divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); uart_barrier(bas); uart_setreg(bas, REG_LCR, lcr); uart_barrier(bas); baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; if (baudrate > 0) *(int*)data = baudrate; else error = ENXIO; break; default: error = EINVAL; break; } uart_unlock(sc->sc_hwmtx); return (error); } int ns8250_bus_ipend(struct uart_softc *sc) { struct uart_bas *bas; struct ns8250_softc *ns8250; int ipend; uint8_t iir, lsr; ns8250 = (struct ns8250_softc *)sc; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); iir = uart_getreg(bas, REG_IIR); if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { (void)uart_getreg(bas, DW_REG_USR); uart_unlock(sc->sc_hwmtx); return (0); } if (iir & IIR_NOPEND) { uart_unlock(sc->sc_hwmtx); return (0); } ipend = 0; if (iir & IIR_RXRDY) { lsr = uart_getreg(bas, REG_LSR); if (lsr & LSR_OE) ipend |= SER_INT_OVERRUN; if (lsr & LSR_BI) ipend |= SER_INT_BREAK; if (lsr & LSR_RXRDY) ipend |= SER_INT_RXREADY; } else { if (iir & IIR_TXRDY) { ipend |= SER_INT_TXIDLE; uart_setreg(bas, REG_IER, ns8250->ier); } else ipend |= SER_INT_SIGCHG; } if (ipend == 0) ns8250_clrint(bas); uart_unlock(sc->sc_hwmtx); return (ipend); } int ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, int stopbits, int parity) { struct ns8250_softc *ns8250; struct uart_bas *bas; int error, limit; ns8250 = (struct ns8250_softc*)sc; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); /* * When using DW UART with BUSY detection it is necessary to wait * until all serial transfers are finished before manipulating the * line control. LCR will not be affected when UART is busy. */ if (ns8250->busy_detect != 0) { /* * Pick an arbitrary high limit to avoid getting stuck in * an infinite loop in case when the hardware is broken. */ limit = 10 * 1024; while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && --limit) DELAY(4); if (limit <= 0) { /* UART appears to be stuck */ uart_unlock(sc->sc_hwmtx); return (EIO); } } error = ns8250_param(bas, baudrate, databits, stopbits, parity); uart_unlock(sc->sc_hwmtx); return (error); } int ns8250_bus_probe(struct uart_softc *sc) { struct ns8250_softc *ns8250; struct uart_bas *bas; int count, delay, error, limit; uint8_t lsr, mcr, ier; ns8250 = (struct ns8250_softc *)sc; bas = &sc->sc_bas; error = ns8250_probe(bas); if (error) return (error); mcr = MCR_IE; if (sc->sc_sysdev == NULL) { /* By using ns8250_init() we also set DTR and RTS. */ ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); } else mcr |= MCR_DTR | MCR_RTS; error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); if (error) return (error); /* * Set loopback mode. This avoids having garbage on the wire and * also allows us send and receive data. We set DTR and RTS to * avoid the possibility that automatic flow-control prevents * any data from being sent. */ uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); uart_barrier(bas); /* * Enable FIFOs. And check that the UART has them. If not, we're * done. Since this is the first time we enable the FIFOs, we reset * them. */ uart_setreg(bas, REG_FCR, FCR_ENABLE); uart_barrier(bas); if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { /* * NS16450 or INS8250. We don't bother to differentiate * between them. They're too old to be interesting. */ uart_setreg(bas, REG_MCR, mcr); uart_barrier(bas); sc->sc_rxfifosz = sc->sc_txfifosz = 1; device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); return (0); } uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); uart_barrier(bas); count = 0; delay = ns8250_delay(bas); /* We have FIFOs. Drain the transmitter and receiver. */ error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); if (error) { uart_setreg(bas, REG_MCR, mcr); uart_setreg(bas, REG_FCR, 0); uart_barrier(bas); goto describe; } /* * We should have a sufficiently clean "pipe" to determine the * size of the FIFOs. We send as much characters as is reasonable * and wait for the overflow bit in the LSR register to be * asserted, counting the characters as we send them. Based on * that count we know the FIFO size. */ do { uart_setreg(bas, REG_DATA, 0); uart_barrier(bas); count++; limit = 30; lsr = 0; /* * LSR bits are cleared upon read, so we must accumulate * them to be able to test LSR_OE below. */ while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && --limit) DELAY(delay); if (limit == 0) { ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; uart_setreg(bas, REG_IER, ier); uart_setreg(bas, REG_MCR, mcr); uart_setreg(bas, REG_FCR, 0); uart_barrier(bas); count = 0; goto describe; } } while ((lsr & LSR_OE) == 0 && count < 130); count--; uart_setreg(bas, REG_MCR, mcr); /* Reset FIFOs. */ ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); describe: if (count >= 14 && count <= 16) { sc->sc_rxfifosz = 16; device_set_desc(sc->sc_dev, "16550 or compatible"); } else if (count >= 28 && count <= 32) { sc->sc_rxfifosz = 32; device_set_desc(sc->sc_dev, "16650 or compatible"); } else if (count >= 56 && count <= 64) { sc->sc_rxfifosz = 64; device_set_desc(sc->sc_dev, "16750 or compatible"); } else if (count >= 112 && count <= 128) { sc->sc_rxfifosz = 128; device_set_desc(sc->sc_dev, "16950 or compatible"); } else { sc->sc_rxfifosz = 16; device_set_desc(sc->sc_dev, "Non-standard ns8250 class UART with FIFOs"); } /* * Force the Tx FIFO size to 16 bytes for now. We don't program the * Tx trigger. Also, we assume that all data has been sent when the * interrupt happens. */ sc->sc_txfifosz = 16; #if 0 /* * XXX there are some issues related to hardware flow control and * it's likely that uart(4) is the cause. This basicly needs more * investigation, but we avoid using for hardware flow control * until then. */ /* 16650s or higher have automatic flow control. */ if (sc->sc_rxfifosz > 16) { sc->sc_hwiflow = 1; sc->sc_hwoflow = 1; } #endif return (0); } int ns8250_bus_receive(struct uart_softc *sc) { struct uart_bas *bas; int xc; uint8_t lsr; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); lsr = uart_getreg(bas, REG_LSR); while (lsr & LSR_RXRDY) { if (uart_rx_full(sc)) { sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; } xc = uart_getreg(bas, REG_DATA); if (lsr & LSR_FE) xc |= UART_STAT_FRAMERR; if (lsr & LSR_PE) xc |= UART_STAT_PARERR; uart_rx_put(sc, xc); lsr = uart_getreg(bas, REG_LSR); } /* Discard everything left in the Rx FIFO. */ while (lsr & LSR_RXRDY) { (void)uart_getreg(bas, REG_DATA); uart_barrier(bas); lsr = uart_getreg(bas, REG_LSR); } uart_unlock(sc->sc_hwmtx); return (0); } int ns8250_bus_setsig(struct uart_softc *sc, int sig) { struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; struct uart_bas *bas; uint32_t new, old; bas = &sc->sc_bas; do { old = sc->sc_hwsig; new = old; if (sig & SER_DDTR) { SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); } if (sig & SER_DRTS) { SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); } } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); uart_lock(sc->sc_hwmtx); ns8250->mcr &= ~(MCR_DTR|MCR_RTS); if (new & SER_DTR) ns8250->mcr |= MCR_DTR; if (new & SER_RTS) ns8250->mcr |= MCR_RTS; uart_setreg(bas, REG_MCR, ns8250->mcr); uart_barrier(bas); uart_unlock(sc->sc_hwmtx); return (0); } int ns8250_bus_transmit(struct uart_softc *sc) { struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; struct uart_bas *bas; int i; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) ; uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); uart_barrier(bas); for (i = 0; i < sc->sc_txdatasz; i++) { uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); uart_barrier(bas); } if (broken_txfifo) ns8250_drain(bas, UART_DRAIN_TRANSMITTER); else sc->sc_txbusy = 1; uart_unlock(sc->sc_hwmtx); if (broken_txfifo) uart_sched_softih(sc, SER_INT_TXIDLE); return (0); } + +void +ns8250_bus_grab(struct uart_softc *sc) +{ + struct uart_bas *bas = &sc->sc_bas; + + /* + * turn off all interrupts to enter polling mode. Leave the + * saved mask alone. We'll restore whatever it was in ungrab. + * All pending interupt signals are reset when IER is set to 0. + */ + uart_lock(sc->sc_hwmtx); + uart_setreg(bas, REG_IER, 0); + uart_barrier(bas); + uart_unlock(sc->sc_hwmtx); +} + +void +ns8250_bus_ungrab(struct uart_softc *sc) +{ + struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; + struct uart_bas *bas = &sc->sc_bas; + + /* + * Restore previous interrupt mask + */ + uart_lock(sc->sc_hwmtx); + uart_setreg(bas, REG_IER, ns8250->ier); + uart_barrier(bas); + uart_unlock(sc->sc_hwmtx); +} diff --git a/sys/dev/uart/uart_dev_ns8250.h b/sys/dev/uart/uart_dev_ns8250.h index 39f4a0f27803..0046dfefd875 100644 --- a/sys/dev/uart/uart_dev_ns8250.h +++ b/sys/dev/uart/uart_dev_ns8250.h @@ -1,60 +1,62 @@ /*- * Copyright (c) 2003 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV_UART_DEV_NS8250_H_ #define _DEV_UART_DEV_NS8250_H_ /* * High-level UART interface. */ struct ns8250_softc { struct uart_softc base; uint8_t fcr; uint8_t ier; uint8_t mcr; uint8_t ier_mask; uint8_t ier_rxbits; uint8_t busy_detect; }; extern struct uart_ops uart_ns8250_ops; int ns8250_bus_attach(struct uart_softc *); int ns8250_bus_detach(struct uart_softc *); int ns8250_bus_flush(struct uart_softc *, int); int ns8250_bus_getsig(struct uart_softc *); int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); int ns8250_bus_ipend(struct uart_softc *); int ns8250_bus_param(struct uart_softc *, int, int, int, int); int ns8250_bus_probe(struct uart_softc *); int ns8250_bus_receive(struct uart_softc *); int ns8250_bus_setsig(struct uart_softc *, int); int ns8250_bus_transmit(struct uart_softc *); +void ns8250_bus_grab(struct uart_softc *); +void ns8250_bus_ungrab(struct uart_softc *); #endif /* _DEV_UART_DEV_NS8250_H_ */ diff --git a/sys/dev/uart/uart_dev_pl011.c b/sys/dev/uart/uart_dev_pl011.c index 82e8b03654d0..3253cd14a2e0 100644 --- a/sys/dev/uart/uart_dev_pl011.c +++ b/sys/dev/uart/uart_dev_pl011.c @@ -1,443 +1,472 @@ /*- * Copyright (c) 2012 Semihalf. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include "uart_if.h" #include /* PL011 UART registers and masks*/ #define UART_DR 0x00 /* Data register */ #define DR_FE (1 << 8) /* Framing error */ #define DR_PE (1 << 9) /* Parity error */ #define DR_BE (1 << 10) /* Break error */ #define DR_OE (1 << 11) /* Overrun error */ #define UART_FR 0x06 /* Flag register */ #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ #define UART_IBRD 0x09 /* Integer baud rate register */ #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ #define UART_FBRD 0x0a /* Fractional baud rate register */ #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ #define UART_LCR_H 0x0b /* Line control register */ #define LCR_H_WLEN8 (0x3 << 5) #define LCR_H_WLEN7 (0x2 << 5) #define LCR_H_WLEN6 (0x1 << 5) #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ #define LCR_H_EPS (1 << 2) /* Even parity select */ #define LCR_H_PEN (1 << 1) /* Parity enable */ #define UART_CR 0x0c /* Control register */ #define CR_RXE (1 << 9) /* Receive enable */ #define CR_TXE (1 << 8) /* Transmit enable */ #define CR_UARTEN (1 << 0) /* UART enable */ #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ #define UART_RIS 0x0f /* Raw interrupt status register */ #define UART_RXREADY (1 << 4) /* RX buffer full */ #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ #define RIS_FE (1 << 7) /* Framing error interrupt status */ #define RIS_PE (1 << 8) /* Parity error interrupt status */ #define RIS_BE (1 << 9) /* Break error interrupt status */ #define RIS_OE (1 << 10) /* Overrun interrupt status */ #define UART_MIS 0x10 /* Masked interrupt status register */ #define UART_ICR 0x11 /* Interrupt clear register */ /* * FIXME: actual register size is SoC-dependent, we need to handle it */ #define __uart_getreg(bas, reg) \ bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) #define __uart_setreg(bas, reg, value) \ bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) /* * Low-level UART interface. */ static int uart_pl011_probe(struct uart_bas *bas); static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); static void uart_pl011_term(struct uart_bas *bas); static void uart_pl011_putc(struct uart_bas *bas, int); static int uart_pl011_rxready(struct uart_bas *bas); static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); static struct uart_ops uart_pl011_ops = { .probe = uart_pl011_probe, .init = uart_pl011_init, .term = uart_pl011_term, .putc = uart_pl011_putc, .rxready = uart_pl011_rxready, .getc = uart_pl011_getc, }; static int uart_pl011_probe(struct uart_bas *bas) { return (0); } static void uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { uint32_t ctrl, line; uint32_t baud; /* * Zero all settings to make sure * UART is disabled and not configured */ ctrl = line = 0x0; __uart_setreg(bas, UART_CR, ctrl); /* As we know UART is disabled we may setup the line */ switch (databits) { case 7: line |= LCR_H_WLEN7; break; case 6: line |= LCR_H_WLEN6; break; case 8: default: line |= LCR_H_WLEN8; break; } if (stopbits == 2) line |= LCR_H_STP2; else line &= ~LCR_H_STP2; if (parity) line |= LCR_H_PEN; else line &= ~LCR_H_PEN; /* Configure the rest */ line &= ~LCR_H_FEN; ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); if (bas->rclk != 0 && baudrate != 0) { baud = bas->rclk * 4 / baudrate; __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); } /* Add config. to line before reenabling UART */ __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & ~0xff) | line); __uart_setreg(bas, UART_CR, ctrl); } static void uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { /* Mask all interrupts */ __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & ~IMSC_MASK_ALL); uart_pl011_param(bas, baudrate, databits, stopbits, parity); } static void uart_pl011_term(struct uart_bas *bas) { } static void uart_pl011_putc(struct uart_bas *bas, int c) { while (!(__uart_getreg(bas, UART_FR) & FR_TXFE)) ; __uart_setreg(bas, UART_DR, c & 0xff); } static int uart_pl011_rxready(struct uart_bas *bas) { return (__uart_getreg(bas, UART_FR) & FR_RXFF); } static int uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) { int c; while (!uart_pl011_rxready(bas)) ; c = __uart_getreg(bas, UART_DR) & 0xff; return (c); } /* * High-level UART interface. */ struct uart_pl011_softc { struct uart_softc base; uint8_t fcr; uint8_t ier; uint8_t mcr; uint8_t ier_mask; uint8_t ier_rxbits; }; static int uart_pl011_bus_attach(struct uart_softc *); static int uart_pl011_bus_detach(struct uart_softc *); static int uart_pl011_bus_flush(struct uart_softc *, int); static int uart_pl011_bus_getsig(struct uart_softc *); static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); static int uart_pl011_bus_ipend(struct uart_softc *); static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); static int uart_pl011_bus_probe(struct uart_softc *); static int uart_pl011_bus_receive(struct uart_softc *); static int uart_pl011_bus_setsig(struct uart_softc *, int); static int uart_pl011_bus_transmit(struct uart_softc *); +static void uart_pl011_bus_grab(struct uart_softc *); +static void uart_pl011_bus_ungrab(struct uart_softc *); static kobj_method_t uart_pl011_methods[] = { KOBJMETHOD(uart_attach, uart_pl011_bus_attach), KOBJMETHOD(uart_detach, uart_pl011_bus_detach), KOBJMETHOD(uart_flush, uart_pl011_bus_flush), KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), KOBJMETHOD(uart_param, uart_pl011_bus_param), KOBJMETHOD(uart_probe, uart_pl011_bus_probe), KOBJMETHOD(uart_receive, uart_pl011_bus_receive), KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), + KOBJMETHOD(uart_grab, uart_pl011_bus_grab), + KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), + { 0, 0 } }; struct uart_class uart_pl011_class = { "uart_pl011", uart_pl011_methods, sizeof(struct uart_pl011_softc), .uc_ops = &uart_pl011_ops, .uc_range = 0x48, .uc_rclk = 0 }; static int uart_pl011_bus_attach(struct uart_softc *sc) { struct uart_bas *bas; bas = &sc->sc_bas; /* Enable RX & TX interrupts */ __uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY)); /* Clear RX & TX interrupts */ __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); return (0); } static int uart_pl011_bus_detach(struct uart_softc *sc) { return (0); } static int uart_pl011_bus_flush(struct uart_softc *sc, int what) { return (0); } static int uart_pl011_bus_getsig(struct uart_softc *sc) { return (0); } static int uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) { struct uart_bas *bas; int error; bas = &sc->sc_bas; error = 0; uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: break; case UART_IOCTL_BAUD: *(int*)data = 115200; break; default: error = EINVAL; break; } uart_unlock(sc->sc_hwmtx); return (error); } static int uart_pl011_bus_ipend(struct uart_softc *sc) { struct uart_bas *bas; int ipend; uint32_t ints; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); ints = __uart_getreg(bas, UART_MIS); ipend = 0; if (ints & UART_RXREADY) ipend |= SER_INT_RXREADY; if (ints & RIS_BE) ipend |= SER_INT_BREAK; if (ints & RIS_OE) ipend |= SER_INT_OVERRUN; if (ints & UART_TXEMPTY) { if (sc->sc_txbusy) ipend |= SER_INT_TXIDLE; __uart_setreg(bas, UART_IMSC, UART_RXREADY); } uart_unlock(sc->sc_hwmtx); return (ipend); } static int uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, int stopbits, int parity) { uart_lock(sc->sc_hwmtx); uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); uart_unlock(sc->sc_hwmtx); return (0); } static int uart_pl011_bus_probe(struct uart_softc *sc) { device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); sc->sc_rxfifosz = 1; sc->sc_txfifosz = 1; return (0); } static int uart_pl011_bus_receive(struct uart_softc *sc) { struct uart_bas *bas; int rx; uint32_t ints, xc; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); ints = __uart_getreg(bas, UART_MIS); while (ints & UART_RXREADY) { if (uart_rx_full(sc)) { sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; } xc = __uart_getreg(bas, UART_DR); rx = xc & 0xff; if (xc & DR_FE) rx |= UART_STAT_FRAMERR; if (xc & DR_PE) rx |= UART_STAT_PARERR; __uart_setreg(bas, UART_ICR, UART_RXREADY); uart_rx_put(sc, rx); ints = __uart_getreg(bas, UART_MIS); } uart_unlock(sc->sc_hwmtx); return (0); } static int uart_pl011_bus_setsig(struct uart_softc *sc, int sig) { return (0); } static int uart_pl011_bus_transmit(struct uart_softc *sc) { struct uart_bas *bas; int i; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); for (i = 0; i < sc->sc_txdatasz; i++) { __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); uart_barrier(bas); } sc->sc_txbusy = 1; __uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY)); uart_unlock(sc->sc_hwmtx); return (0); } + +static void +uart_pl011_bus_grab(struct uart_softc *sc) +{ + struct uart_bas *bas; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + __uart_setreg(bas, UART_IMSC, /* Switch to RX polling while grabbed */ + ~UART_RXREADY & __uart_getreg(bas, UART_IMSC)); + uart_unlock(sc->sc_hwmtx); +} + +static void +uart_pl011_bus_ungrab(struct uart_softc *sc) +{ + struct uart_bas *bas; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + __uart_setreg(bas, UART_IMSC, /* Switch to RX interrupts while not grabbed */ + UART_RXREADY | __uart_getreg(bas, UART_IMSC)); + uart_unlock(sc->sc_hwmtx); +} diff --git a/sys/dev/uart/uart_dev_quicc.c b/sys/dev/uart/uart_dev_quicc.c index 337591e8ec90..bbbc3bd0f5df 100644 --- a/sys/dev/uart/uart_dev_quicc.c +++ b/sys/dev/uart/uart_dev_quicc.c @@ -1,487 +1,522 @@ /*- * Copyright (c) 2006 Juniper Networks * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include "uart_if.h" #define DEFAULT_RCLK ((266000000 * 2) / 16) #define quicc_read2(bas, reg) \ bus_space_read_2((bas)->bst, (bas)->bsh, reg) #define quicc_read4(bas, reg) \ bus_space_read_4((bas)->bst, (bas)->bsh, reg) #define quicc_write2(bas, reg, val) \ bus_space_write_2((bas)->bst, (bas)->bsh, reg, val) #define quicc_write4(bas, reg, val) \ bus_space_write_4((bas)->bst, (bas)->bsh, reg, val) static int quicc_divisor(int rclk, int baudrate) { int act_baud, divisor, error; if (baudrate == 0) return (-1); divisor = rclk / baudrate / 16; if (divisor > 4096) divisor = ((divisor >> 3) - 2) | 1; else if (divisor >= 0) divisor = (divisor - 1) << 1; if (divisor < 0 || divisor >= 8192) return (-1); act_baud = rclk / (((divisor >> 1) + 1) << ((divisor & 1) ? 8 : 4)); /* 10 times error in percent: */ error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; /* 3.0% maximum error tolerance: */ if (error < -30 || error > 30) return (-1); return (divisor); } static int quicc_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { int divisor; uint16_t psmr; if (baudrate > 0) { divisor = quicc_divisor(bas->rclk, baudrate); if (divisor == -1) return (EINVAL); quicc_write4(bas, QUICC_REG_BRG(bas->chan - 1), divisor | 0x10000); } psmr = 0; switch (databits) { case 5: psmr |= 0x0000; break; case 6: psmr |= 0x1000; break; case 7: psmr |= 0x2000; break; case 8: psmr |= 0x3000; break; default: return (EINVAL); } switch (stopbits) { case 1: psmr |= 0x0000; break; case 2: psmr |= 0x4000; break; default: return (EINVAL); } switch (parity) { case UART_PARITY_EVEN: psmr |= 0x1a; break; case UART_PARITY_MARK: psmr |= 0x1f; break; case UART_PARITY_NONE: psmr |= 0x00; break; case UART_PARITY_ODD: psmr |= 0x10; break; case UART_PARITY_SPACE: psmr |= 0x15; break; default: return (EINVAL); } quicc_write2(bas, QUICC_REG_SCC_PSMR(bas->chan - 1), psmr); return (0); } static void quicc_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { if (bas->rclk == 0) bas->rclk = DEFAULT_RCLK; /* * GSMR_L = 0x00028034 * GSMR_H = 0x00000020 */ quicc_param(bas, baudrate, databits, stopbits, parity); quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0); quicc_write2(bas, QUICC_REG_SCC_SCCM(bas->chan - 1), 0x0027); } /* * Low-level UART interface. */ static int quicc_probe(struct uart_bas *bas); static void quicc_init(struct uart_bas *bas, int, int, int, int); static void quicc_term(struct uart_bas *bas); static void quicc_putc(struct uart_bas *bas, int); static int quicc_rxready(struct uart_bas *bas); static int quicc_getc(struct uart_bas *bas, struct mtx *); static struct uart_ops uart_quicc_ops = { .probe = quicc_probe, .init = quicc_init, .term = quicc_term, .putc = quicc_putc, .rxready = quicc_rxready, .getc = quicc_getc, }; static int quicc_probe(struct uart_bas *bas) { return (0); } static void quicc_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { quicc_setup(bas, baudrate, databits, stopbits, parity); } static void quicc_term(struct uart_bas *bas) { } static void quicc_putc(struct uart_bas *bas, int c) { int unit; uint16_t toseq; unit = bas->chan - 1; while (quicc_read2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit)) & 0x2000) DELAY(10); toseq = 0x2000 | (c & 0xff); quicc_write2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit), toseq); } static int quicc_rxready(struct uart_bas *bas) { uint16_t rb; rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); return ((quicc_read2(bas, rb) & 0x8000) ? 0 : 1); } static int quicc_getc(struct uart_bas *bas, struct mtx *hwmtx) { volatile char *buf; int c; uint16_t rb, sc; uart_lock(hwmtx); rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); while ((sc = quicc_read2(bas, rb)) & 0x8000) { uart_unlock(hwmtx); DELAY(4); uart_lock(hwmtx); } buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4); c = *buf; quicc_write2(bas, rb, sc | 0x8000); uart_unlock(hwmtx); return (c); } /* * High-level UART interface. */ struct quicc_softc { struct uart_softc base; }; static int quicc_bus_attach(struct uart_softc *); static int quicc_bus_detach(struct uart_softc *); static int quicc_bus_flush(struct uart_softc *, int); static int quicc_bus_getsig(struct uart_softc *); static int quicc_bus_ioctl(struct uart_softc *, int, intptr_t); static int quicc_bus_ipend(struct uart_softc *); static int quicc_bus_param(struct uart_softc *, int, int, int, int); static int quicc_bus_probe(struct uart_softc *); static int quicc_bus_receive(struct uart_softc *); static int quicc_bus_setsig(struct uart_softc *, int); static int quicc_bus_transmit(struct uart_softc *); +static void quicc_bus_grab(struct uart_softc *); +static void quicc_bus_ungrab(struct uart_softc *); static kobj_method_t quicc_methods[] = { KOBJMETHOD(uart_attach, quicc_bus_attach), KOBJMETHOD(uart_detach, quicc_bus_detach), KOBJMETHOD(uart_flush, quicc_bus_flush), KOBJMETHOD(uart_getsig, quicc_bus_getsig), KOBJMETHOD(uart_ioctl, quicc_bus_ioctl), KOBJMETHOD(uart_ipend, quicc_bus_ipend), KOBJMETHOD(uart_param, quicc_bus_param), KOBJMETHOD(uart_probe, quicc_bus_probe), KOBJMETHOD(uart_receive, quicc_bus_receive), KOBJMETHOD(uart_setsig, quicc_bus_setsig), KOBJMETHOD(uart_transmit, quicc_bus_transmit), + KOBJMETHOD(uart_grab, quicc_bus_grab), + KOBJMETHOD(uart_ungrab, quicc_bus_ungrab), { 0, 0 } }; struct uart_class uart_quicc_class = { "quicc", quicc_methods, sizeof(struct quicc_softc), .uc_ops = &uart_quicc_ops, .uc_range = 2, .uc_rclk = DEFAULT_RCLK }; #define SIGCHG(c, i, s, d) \ if (c) { \ i |= (i & s) ? s : s | d; \ } else { \ i = (i & s) ? (i & ~s) | d : i; \ } static int quicc_bus_attach(struct uart_softc *sc) { struct uart_bas *bas; struct uart_devinfo *di; uint16_t st, rb; bas = &sc->sc_bas; if (sc->sc_sysdev != NULL) { di = sc->sc_sysdev; quicc_param(bas, di->baudrate, di->databits, di->stopbits, di->parity); } else { quicc_setup(bas, 9600, 8, 1, UART_PARITY_NONE); } /* Enable interrupts on the receive buffer. */ rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); st = quicc_read2(bas, rb); quicc_write2(bas, rb, st | 0x9000); (void)quicc_bus_getsig(sc); return (0); } static int quicc_bus_detach(struct uart_softc *sc) { return (0); } static int quicc_bus_flush(struct uart_softc *sc, int what) { return (0); } static int quicc_bus_getsig(struct uart_softc *sc) { uint32_t new, old, sig; uint32_t dummy; do { old = sc->sc_hwsig; sig = old; uart_lock(sc->sc_hwmtx); /* XXX SIGNALS */ dummy = 0; uart_unlock(sc->sc_hwmtx); SIGCHG(dummy, sig, SER_CTS, SER_DCTS); SIGCHG(dummy, sig, SER_DCD, SER_DDCD); SIGCHG(dummy, sig, SER_DSR, SER_DDSR); new = sig & ~SER_MASK_DELTA; } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); return (sig); } static int quicc_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) { struct uart_bas *bas; uint32_t brg; int baudrate, error; bas = &sc->sc_bas; error = 0; uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: break; case UART_IOCTL_BAUD: brg = quicc_read4(bas, QUICC_REG_BRG(bas->chan - 1)) & 0x1fff; brg = (brg & 1) ? (brg + 1) << 3 : (brg + 2) >> 1; baudrate = bas->rclk / (brg * 16); *(int*)data = baudrate; break; default: error = EINVAL; break; } uart_unlock(sc->sc_hwmtx); return (error); } static int quicc_bus_ipend(struct uart_softc *sc) { struct uart_bas *bas; int ipend; uint16_t scce; bas = &sc->sc_bas; ipend = 0; uart_lock(sc->sc_hwmtx); scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1)); quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0); uart_unlock(sc->sc_hwmtx); if (scce & 0x0001) ipend |= SER_INT_RXREADY; if (scce & 0x0002) ipend |= SER_INT_TXIDLE; if (scce & 0x0004) ipend |= SER_INT_OVERRUN; if (scce & 0x0020) ipend |= SER_INT_BREAK; /* XXX SIGNALS */ return (ipend); } static int quicc_bus_param(struct uart_softc *sc, int baudrate, int databits, int stopbits, int parity) { int error; uart_lock(sc->sc_hwmtx); error = quicc_param(&sc->sc_bas, baudrate, databits, stopbits, parity); uart_unlock(sc->sc_hwmtx); return (error); } static int quicc_bus_probe(struct uart_softc *sc) { char buf[80]; int error; error = quicc_probe(&sc->sc_bas); if (error) return (error); sc->sc_rxfifosz = 1; sc->sc_txfifosz = 1; snprintf(buf, sizeof(buf), "quicc, channel %d", sc->sc_bas.chan); device_set_desc_copy(sc->sc_dev, buf); return (0); } static int quicc_bus_receive(struct uart_softc *sc) { struct uart_bas *bas; volatile char *buf; uint16_t st, rb; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); st = quicc_read2(bas, rb); buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4); uart_rx_put(sc, *buf); quicc_write2(bas, rb, st | 0x9000); uart_unlock(sc->sc_hwmtx); return (0); } static int quicc_bus_setsig(struct uart_softc *sc, int sig) { struct uart_bas *bas; uint32_t new, old; bas = &sc->sc_bas; do { old = sc->sc_hwsig; new = old; if (sig & SER_DDTR) { SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); } if (sig & SER_DRTS) { SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); } } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); uart_lock(sc->sc_hwmtx); /* XXX SIGNALS */ uart_unlock(sc->sc_hwmtx); return (0); } static int quicc_bus_transmit(struct uart_softc *sc) { volatile char *buf; struct uart_bas *bas; uint16_t st, tb; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); tb = quicc_read2(bas, QUICC_PRAM_SCC_TBASE(bas->chan - 1)); st = quicc_read2(bas, tb); buf = (void *)(uintptr_t)quicc_read4(bas, tb + 4); *buf = sc->sc_txbuf[0]; quicc_write2(bas, tb + 2, 1); quicc_write2(bas, tb, st | 0x9000); sc->sc_txbusy = 1; uart_unlock(sc->sc_hwmtx); return (0); } + +static void +quicc_bus_grab(struct uart_softc *sc) +{ + struct uart_bas *bas; + uint16_t st, rb; + + /* Disable interrupts on the receive buffer. */ + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); + st = quicc_read2(bas, rb); + quicc_write2(bas, rb, st & ~0x9000); + uart_unlock(sc->sc_hwmtx); +} + +static void +quicc_bus_ungrab(struct uart_softc *sc) +{ + struct uart_bas *bas; + uint16_t st, rb; + + /* Enable interrupts on the receive buffer. */ + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); + st = quicc_read2(bas, rb); + quicc_write2(bas, rb, st | 0x9000); + uart_unlock(sc->sc_hwmtx); +} + diff --git a/sys/dev/uart/uart_dev_sab82532.c b/sys/dev/uart/uart_dev_sab82532.c index e2ec22766eac..8caa7a7f1234 100644 --- a/sys/dev/uart/uart_dev_sab82532.c +++ b/sys/dev/uart/uart_dev_sab82532.c @@ -1,726 +1,759 @@ /*- * Copyright (c) 2003 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include "uart_if.h" #define DEFAULT_RCLK 29491200 /* * NOTE: To allow us to read the baudrate divisor from the chip, we * copy the value written to the write-only BGR register to an unused * read-write register. We use TCR for that. */ static int sab82532_delay(struct uart_bas *bas) { int divisor, m, n; uint8_t bgr, ccr2; bgr = uart_getreg(bas, SAB_TCR); ccr2 = uart_getreg(bas, SAB_CCR2); n = (bgr & 0x3f) + 1; m = (bgr >> 6) | ((ccr2 >> 4) & 0xC); divisor = n * (1<rclk); } static int sab82532_divisor(int rclk, int baudrate) { int act_baud, act_div, divisor; int error, m, n; if (baudrate == 0) return (0); divisor = (rclk / (baudrate << 3) + 1) >> 1; if (divisor < 2 || divisor >= 1048576) return (0); /* Find the best (N+1,M) pair. */ for (m = 1; m < 15; m++) { n = divisor / (1< 63) continue; act_div = n * (1<> 1; /* 3.0% maximum error tolerance: */ if (error < -30 || error > 30) continue; /* Got it. */ return ((n - 1) | (m << 6)); } return (0); } static void sab82532_flush(struct uart_bas *bas, int what) { if (what & UART_FLUSH_TRANSMITTER) { while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) ; uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES); uart_barrier(bas); } if (what & UART_FLUSH_RECEIVER) { while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) ; uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES); uart_barrier(bas); } } static int sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { int divisor; uint8_t ccr2, dafo; if (databits >= 8) dafo = SAB_DAFO_CHL_CS8; else if (databits == 7) dafo = SAB_DAFO_CHL_CS7; else if (databits == 6) dafo = SAB_DAFO_CHL_CS6; else dafo = SAB_DAFO_CHL_CS5; if (stopbits > 1) dafo |= SAB_DAFO_STOP; switch (parity) { case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break; case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break; case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break; case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break; case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break; default: return (EINVAL); } /* Set baudrate. */ if (baudrate > 0) { divisor = sab82532_divisor(bas->rclk, baudrate); if (divisor == 0) return (EINVAL); uart_setreg(bas, SAB_BGR, divisor & 0xff); uart_barrier(bas); /* Allow reading the (n-1,m) tuple from the chip. */ uart_setreg(bas, SAB_TCR, divisor & 0xff); uart_barrier(bas); ccr2 = uart_getreg(bas, SAB_CCR2); ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8); ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8); uart_setreg(bas, SAB_CCR2, ccr2); uart_barrier(bas); } uart_setreg(bas, SAB_DAFO, dafo); uart_barrier(bas); return (0); } /* * Low-level UART interface. */ static int sab82532_probe(struct uart_bas *bas); static void sab82532_init(struct uart_bas *bas, int, int, int, int); static void sab82532_term(struct uart_bas *bas); static void sab82532_putc(struct uart_bas *bas, int); static int sab82532_rxready(struct uart_bas *bas); static int sab82532_getc(struct uart_bas *bas, struct mtx *); static struct uart_ops uart_sab82532_ops = { .probe = sab82532_probe, .init = sab82532_init, .term = sab82532_term, .putc = sab82532_putc, .rxready = sab82532_rxready, .getc = sab82532_getc, }; static int sab82532_probe(struct uart_bas *bas) { return (0); } static void sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { uint8_t ccr0, pvr; if (bas->rclk == 0) bas->rclk = DEFAULT_RCLK; /* * Set all pins, except the DTR pins (pin 1 and 2) to be inputs. * Pin 4 is magical, meaning that I don't know what it does, but * it too has to be set to output. */ uart_setreg(bas, SAB_PCR, ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC)); uart_barrier(bas); /* Disable port interrupts. */ uart_setreg(bas, SAB_PIM, 0xff); uart_barrier(bas); /* Interrupts are active low. */ uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL); uart_barrier(bas); /* Set DTR. */ pvr = uart_getreg(bas, SAB_PVR); switch (bas->chan) { case 1: pvr &= ~SAB_PVR_DTR_A; break; case 2: pvr &= ~SAB_PVR_DTR_B; break; } uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC); uart_barrier(bas); /* power down */ uart_setreg(bas, SAB_CCR0, 0); uart_barrier(bas); /* set basic configuration */ ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC; uart_setreg(bas, SAB_CCR0, ccr0); uart_barrier(bas); uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7); uart_barrier(bas); uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE); uart_barrier(bas); uart_setreg(bas, SAB_CCR3, 0); uart_barrier(bas); uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD); uart_barrier(bas); uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC); uart_barrier(bas); uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF| SAB_RFC_RFTH_32CHAR); uart_barrier(bas); sab82532_param(bas, baudrate, databits, stopbits, parity); /* Clear interrupts. */ uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD); uart_setreg(bas, SAB_IMR1, 0xff); uart_barrier(bas); uart_getreg(bas, SAB_ISR0); uart_getreg(bas, SAB_ISR1); uart_barrier(bas); sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER); /* Power up. */ uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU); uart_barrier(bas); } static void sab82532_term(struct uart_bas *bas) { uint8_t pvr; pvr = uart_getreg(bas, SAB_PVR); switch (bas->chan) { case 1: pvr |= SAB_PVR_DTR_A; break; case 2: pvr |= SAB_PVR_DTR_B; break; } uart_setreg(bas, SAB_PVR, pvr); uart_barrier(bas); } static void sab82532_putc(struct uart_bas *bas, int c) { int delay, limit; /* 1/10th the time to transmit 1 character (estimate). */ delay = sab82532_delay(bas); limit = 20; while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit) DELAY(delay); uart_setreg(bas, SAB_TIC, c); limit = 20; while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit) DELAY(delay); } static int sab82532_rxready(struct uart_bas *bas) { return ((uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) != 0 ? 1 : 0); } static int sab82532_getc(struct uart_bas *bas, struct mtx *hwmtx) { int c, delay; uart_lock(hwmtx); /* 1/10th the time to transmit 1 character (estimate). */ delay = sab82532_delay(bas); while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)) { uart_unlock(hwmtx); DELAY(delay); uart_lock(hwmtx); } while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) ; uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD); uart_barrier(bas); while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD)) DELAY(delay); c = uart_getreg(bas, SAB_RFIFO); uart_barrier(bas); /* Blow away everything left in the FIFO... */ while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) ; uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC); uart_barrier(bas); uart_unlock(hwmtx); return (c); } /* * High-level UART interface. */ struct sab82532_softc { struct uart_softc base; }; static int sab82532_bus_attach(struct uart_softc *); static int sab82532_bus_detach(struct uart_softc *); static int sab82532_bus_flush(struct uart_softc *, int); static int sab82532_bus_getsig(struct uart_softc *); static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t); static int sab82532_bus_ipend(struct uart_softc *); static int sab82532_bus_param(struct uart_softc *, int, int, int, int); static int sab82532_bus_probe(struct uart_softc *); static int sab82532_bus_receive(struct uart_softc *); static int sab82532_bus_setsig(struct uart_softc *, int); static int sab82532_bus_transmit(struct uart_softc *); +static void sab82532_bus_grab(struct uart_softc *); +static void sab82532_bus_ungrab(struct uart_softc *); static kobj_method_t sab82532_methods[] = { KOBJMETHOD(uart_attach, sab82532_bus_attach), KOBJMETHOD(uart_detach, sab82532_bus_detach), KOBJMETHOD(uart_flush, sab82532_bus_flush), KOBJMETHOD(uart_getsig, sab82532_bus_getsig), KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl), KOBJMETHOD(uart_ipend, sab82532_bus_ipend), KOBJMETHOD(uart_param, sab82532_bus_param), KOBJMETHOD(uart_probe, sab82532_bus_probe), KOBJMETHOD(uart_receive, sab82532_bus_receive), KOBJMETHOD(uart_setsig, sab82532_bus_setsig), KOBJMETHOD(uart_transmit, sab82532_bus_transmit), + KOBJMETHOD(uart_grab, sab82532_bus_grab), + KOBJMETHOD(uart_ungrab, sab82532_bus_ungrab), { 0, 0 } }; struct uart_class uart_sab82532_class = { "sab82532", sab82532_methods, sizeof(struct sab82532_softc), .uc_ops = &uart_sab82532_ops, .uc_range = 64, .uc_rclk = DEFAULT_RCLK }; #define SIGCHG(c, i, s, d) \ if (c) { \ i |= (i & s) ? s : s | d; \ } else { \ i = (i & s) ? (i & ~s) | d : i; \ } static int sab82532_bus_attach(struct uart_softc *sc) { struct uart_bas *bas; uint8_t imr0, imr1; bas = &sc->sc_bas; if (sc->sc_sysdev == NULL) sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE); imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO| SAB_IMR0_RPF; uart_setreg(bas, SAB_IMR0, 0xff & ~imr0); imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC; uart_setreg(bas, SAB_IMR1, 0xff & ~imr1); uart_barrier(bas); if (sc->sc_sysdev == NULL) sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS); (void)sab82532_bus_getsig(sc); return (0); } static int sab82532_bus_detach(struct uart_softc *sc) { struct uart_bas *bas; bas = &sc->sc_bas; uart_setreg(bas, SAB_IMR0, 0xff); uart_setreg(bas, SAB_IMR1, 0xff); uart_barrier(bas); uart_getreg(bas, SAB_ISR0); uart_getreg(bas, SAB_ISR1); uart_barrier(bas); uart_setreg(bas, SAB_CCR0, 0); uart_barrier(bas); return (0); } static int sab82532_bus_flush(struct uart_softc *sc, int what) { uart_lock(sc->sc_hwmtx); sab82532_flush(&sc->sc_bas, what); uart_unlock(sc->sc_hwmtx); return (0); } static int sab82532_bus_getsig(struct uart_softc *sc) { struct uart_bas *bas; uint32_t new, old, sig; uint8_t pvr, star, vstr; bas = &sc->sc_bas; do { old = sc->sc_hwsig; sig = old; uart_lock(sc->sc_hwmtx); star = uart_getreg(bas, SAB_STAR); SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS); vstr = uart_getreg(bas, SAB_VSTR); SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD); pvr = ~uart_getreg(bas, SAB_PVR); switch (bas->chan) { case 1: pvr &= SAB_PVR_DSR_A; break; case 2: pvr &= SAB_PVR_DSR_B; break; } SIGCHG(pvr, sig, SER_DSR, SER_DDSR); uart_unlock(sc->sc_hwmtx); new = sig & ~SER_MASK_DELTA; } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); return (sig); } static int sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) { struct uart_bas *bas; uint8_t dafo, mode; int error; bas = &sc->sc_bas; error = 0; uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: dafo = uart_getreg(bas, SAB_DAFO); if (data) dafo |= SAB_DAFO_XBRK; else dafo &= ~SAB_DAFO_XBRK; uart_setreg(bas, SAB_DAFO, dafo); uart_barrier(bas); break; case UART_IOCTL_IFLOW: mode = uart_getreg(bas, SAB_MODE); if (data) { mode &= ~SAB_MODE_RTS; mode |= SAB_MODE_FRTS; } else { mode |= SAB_MODE_RTS; mode &= ~SAB_MODE_FRTS; } uart_setreg(bas, SAB_MODE, mode); uart_barrier(bas); break; case UART_IOCTL_OFLOW: mode = uart_getreg(bas, SAB_MODE); if (data) mode &= ~SAB_MODE_FCTS; else mode |= SAB_MODE_FCTS; uart_setreg(bas, SAB_MODE, mode); uart_barrier(bas); break; default: error = EINVAL; break; } uart_unlock(sc->sc_hwmtx); return (error); } static int sab82532_bus_ipend(struct uart_softc *sc) { struct uart_bas *bas; int ipend; uint8_t isr0, isr1; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); isr0 = uart_getreg(bas, SAB_ISR0); isr1 = uart_getreg(bas, SAB_ISR1); uart_barrier(bas); if (isr0 & SAB_ISR0_TIME) { while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) ; uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD); uart_barrier(bas); } uart_unlock(sc->sc_hwmtx); ipend = 0; if (isr1 & SAB_ISR1_BRKT) ipend |= SER_INT_BREAK; if (isr0 & SAB_ISR0_RFO) ipend |= SER_INT_OVERRUN; if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF)) ipend |= SER_INT_RXREADY; if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC)) ipend |= SER_INT_SIGCHG; if (isr1 & SAB_ISR1_ALLS) ipend |= SER_INT_TXIDLE; return (ipend); } static int sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits, int stopbits, int parity) { struct uart_bas *bas; int error; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); error = sab82532_param(bas, baudrate, databits, stopbits, parity); uart_unlock(sc->sc_hwmtx); return (error); } static int sab82532_bus_probe(struct uart_softc *sc) { char buf[80]; const char *vstr; int error; char ch; error = sab82532_probe(&sc->sc_bas); if (error) return (error); sc->sc_rxfifosz = 32; sc->sc_txfifosz = 32; ch = sc->sc_bas.chan - 1 + 'A'; switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) { case SAB_VSTR_V_1: vstr = "v1"; break; case SAB_VSTR_V_2: vstr = "v2"; break; case SAB_VSTR_V_32: vstr = "v3.2"; sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */ sc->sc_hwoflow = 1; break; default: vstr = "v4?"; break; } snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch); device_set_desc_copy(sc->sc_dev, buf); return (0); } static int sab82532_bus_receive(struct uart_softc *sc) { struct uart_bas *bas; int i, rbcl, xc; uint8_t s; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) { rbcl = uart_getreg(bas, SAB_RBCL) & 31; if (rbcl == 0) rbcl = 32; for (i = 0; i < rbcl; i += 2) { if (uart_rx_full(sc)) { sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; } xc = uart_getreg(bas, SAB_RFIFO); s = uart_getreg(bas, SAB_RFIFO + 1); if (s & SAB_RSTAT_FE) xc |= UART_STAT_FRAMERR; if (s & SAB_RSTAT_PE) xc |= UART_STAT_PARERR; uart_rx_put(sc, xc); } } while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) ; uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC); uart_barrier(bas); uart_unlock(sc->sc_hwmtx); return (0); } static int sab82532_bus_setsig(struct uart_softc *sc, int sig) { struct uart_bas *bas; uint32_t new, old; uint8_t mode, pvr; bas = &sc->sc_bas; do { old = sc->sc_hwsig; new = old; if (sig & SER_DDTR) { SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); } if (sig & SER_DRTS) { SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); } } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); uart_lock(sc->sc_hwmtx); /* Set DTR pin. */ pvr = uart_getreg(bas, SAB_PVR); switch (bas->chan) { case 1: if (new & SER_DTR) pvr &= ~SAB_PVR_DTR_A; else pvr |= SAB_PVR_DTR_A; break; case 2: if (new & SER_DTR) pvr &= ~SAB_PVR_DTR_B; else pvr |= SAB_PVR_DTR_B; break; } uart_setreg(bas, SAB_PVR, pvr); /* Set RTS pin. */ mode = uart_getreg(bas, SAB_MODE); if (new & SER_RTS) mode &= ~SAB_MODE_FRTS; else mode |= SAB_MODE_FRTS; uart_setreg(bas, SAB_MODE, mode); uart_barrier(bas); uart_unlock(sc->sc_hwmtx); return (0); } static int sab82532_bus_transmit(struct uart_softc *sc) { struct uart_bas *bas; int i; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW)) ; for (i = 0; i < sc->sc_txdatasz; i++) uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]); uart_barrier(bas); while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) ; uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF); sc->sc_txbusy = 1; uart_unlock(sc->sc_hwmtx); return (0); } + +static void +sab82532_bus_grab(struct uart_softc *sc) +{ + struct uart_bas *bas; + uint8_t imr0; + + bas = &sc->sc_bas; + imr0 = SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO; /* No TCD or RPF */ + uart_lock(sc->sc_hwmtx); + uart_setreg(bas, SAB_IMR0, 0xff & ~imr0); + uart_barrier(bas); + uart_unlock(sc->sc_hwmtx); +} + +static void +sab82532_bus_ungrab(struct uart_softc *sc) +{ + struct uart_bas *bas; + uint8_t imr0; + + bas = &sc->sc_bas; + imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO| + SAB_IMR0_RPF; + uart_lock(sc->sc_hwmtx); + uart_setreg(bas, SAB_IMR0, 0xff & ~imr0); + uart_barrier(bas); + uart_unlock(sc->sc_hwmtx); +} diff --git a/sys/dev/uart/uart_dev_z8530.c b/sys/dev/uart/uart_dev_z8530.c index f948b26fa2fa..5cc24a80bd62 100644 --- a/sys/dev/uart/uart_dev_z8530.c +++ b/sys/dev/uart/uart_dev_z8530.c @@ -1,623 +1,651 @@ /*- * Copyright (c) 2003 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include "uart_if.h" #define DEFAULT_RCLK 307200 /* Hack! */ #ifdef __powerpc__ #define UART_PCLK 0 #else #define UART_PCLK MCB2_PCLK #endif /* Multiplexed I/O. */ static __inline void uart_setmreg(struct uart_bas *bas, int reg, int val) { uart_setreg(bas, REG_CTRL, reg); uart_barrier(bas); uart_setreg(bas, REG_CTRL, val); } static __inline uint8_t uart_getmreg(struct uart_bas *bas, int reg) { uart_setreg(bas, REG_CTRL, reg); uart_barrier(bas); return (uart_getreg(bas, REG_CTRL)); } static int z8530_divisor(int rclk, int baudrate) { int act_baud, divisor, error; if (baudrate == 0) return (-1); divisor = (rclk + baudrate) / (baudrate << 1) - 2; if (divisor < 0 || divisor >= 65536) return (-1); act_baud = rclk / 2 / (divisor + 2); /* 10 times error in percent: */ error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; /* 3.0% maximum error tolerance: */ if (error < -30 || error > 30) return (-1); return (divisor); } static int z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity, uint8_t *tpcp) { int divisor; uint8_t mpm, rpc, tpc; rpc = RPC_RXE; mpm = MPM_CM16; tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS)); if (databits >= 8) { rpc |= RPC_RB8; tpc |= TPC_TB8; } else if (databits == 7) { rpc |= RPC_RB7; tpc |= TPC_TB7; } else if (databits == 6) { rpc |= RPC_RB6; tpc |= TPC_TB6; } else { rpc |= RPC_RB5; tpc |= TPC_TB5; } mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1; switch (parity) { case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break; case UART_PARITY_NONE: break; case UART_PARITY_ODD: mpm |= MPM_PE; break; default: return (EINVAL); } if (baudrate > 0) { divisor = z8530_divisor(bas->rclk, baudrate); if (divisor == -1) return (EINVAL); } else divisor = -1; uart_setmreg(bas, WR_MCB2, UART_PCLK); uart_barrier(bas); if (divisor >= 0) { uart_setmreg(bas, WR_TCL, divisor & 0xff); uart_barrier(bas); uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff); uart_barrier(bas); } uart_setmreg(bas, WR_RPC, rpc); uart_barrier(bas); uart_setmreg(bas, WR_MPM, mpm); uart_barrier(bas); uart_setmreg(bas, WR_TPC, tpc); uart_barrier(bas); uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE); uart_barrier(bas); *tpcp = tpc; return (0); } static int z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { uint8_t tpc; if (bas->rclk == 0) bas->rclk = DEFAULT_RCLK; /* Assume we don't need to perform a full hardware reset. */ switch (bas->chan) { case 1: uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA); break; case 2: uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB); break; } uart_barrier(bas); /* Set clock sources. */ uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); uart_setmreg(bas, WR_MCB2, UART_PCLK); uart_barrier(bas); /* Set data encoding. */ uart_setmreg(bas, WR_MCB1, MCB1_NRZ); uart_barrier(bas); tpc = TPC_DTR | TPC_RTS; z8530_param(bas, baudrate, databits, stopbits, parity, &tpc); return (int)tpc; } /* * Low-level UART interface. */ static int z8530_probe(struct uart_bas *bas); static void z8530_init(struct uart_bas *bas, int, int, int, int); static void z8530_term(struct uart_bas *bas); static void z8530_putc(struct uart_bas *bas, int); static int z8530_rxready(struct uart_bas *bas); static int z8530_getc(struct uart_bas *bas, struct mtx *); static struct uart_ops uart_z8530_ops = { .probe = z8530_probe, .init = z8530_init, .term = z8530_term, .putc = z8530_putc, .rxready = z8530_rxready, .getc = z8530_getc, }; static int z8530_probe(struct uart_bas *bas) { return (0); } static void z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { z8530_setup(bas, baudrate, databits, stopbits, parity); } static void z8530_term(struct uart_bas *bas) { } static void z8530_putc(struct uart_bas *bas, int c) { while (!(uart_getreg(bas, REG_CTRL) & BES_TXE)) ; uart_setreg(bas, REG_DATA, c); uart_barrier(bas); } static int z8530_rxready(struct uart_bas *bas) { return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0); } static int z8530_getc(struct uart_bas *bas, struct mtx *hwmtx) { int c; uart_lock(hwmtx); while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) { uart_unlock(hwmtx); DELAY(10); uart_lock(hwmtx); } c = uart_getreg(bas, REG_DATA); uart_unlock(hwmtx); return (c); } /* * High-level UART interface. */ struct z8530_softc { struct uart_softc base; uint8_t tpc; uint8_t txidle; }; static int z8530_bus_attach(struct uart_softc *); static int z8530_bus_detach(struct uart_softc *); static int z8530_bus_flush(struct uart_softc *, int); static int z8530_bus_getsig(struct uart_softc *); static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t); static int z8530_bus_ipend(struct uart_softc *); static int z8530_bus_param(struct uart_softc *, int, int, int, int); static int z8530_bus_probe(struct uart_softc *); static int z8530_bus_receive(struct uart_softc *); static int z8530_bus_setsig(struct uart_softc *, int); static int z8530_bus_transmit(struct uart_softc *); +static void z8530_bus_grab(struct uart_softc *); +static void z8530_bus_ungrab(struct uart_softc *); static kobj_method_t z8530_methods[] = { KOBJMETHOD(uart_attach, z8530_bus_attach), KOBJMETHOD(uart_detach, z8530_bus_detach), KOBJMETHOD(uart_flush, z8530_bus_flush), KOBJMETHOD(uart_getsig, z8530_bus_getsig), KOBJMETHOD(uart_ioctl, z8530_bus_ioctl), KOBJMETHOD(uart_ipend, z8530_bus_ipend), KOBJMETHOD(uart_param, z8530_bus_param), KOBJMETHOD(uart_probe, z8530_bus_probe), KOBJMETHOD(uart_receive, z8530_bus_receive), KOBJMETHOD(uart_setsig, z8530_bus_setsig), KOBJMETHOD(uart_transmit, z8530_bus_transmit), + KOBJMETHOD(uart_grab, z8530_bus_grab), + KOBJMETHOD(uart_ungrab, z8530_bus_ungrab), { 0, 0 } }; struct uart_class uart_z8530_class = { "z8530", z8530_methods, sizeof(struct z8530_softc), .uc_ops = &uart_z8530_ops, .uc_range = 2, .uc_rclk = DEFAULT_RCLK }; #define SIGCHG(c, i, s, d) \ if (c) { \ i |= (i & s) ? s : s | d; \ } else { \ i = (i & s) ? (i & ~s) | d : i; \ } static int z8530_bus_attach(struct uart_softc *sc) { struct z8530_softc *z8530 = (struct z8530_softc*)sc; struct uart_bas *bas; struct uart_devinfo *di; bas = &sc->sc_bas; if (sc->sc_sysdev != NULL) { di = sc->sc_sysdev; z8530->tpc = TPC_DTR|TPC_RTS; z8530_param(bas, di->baudrate, di->databits, di->stopbits, di->parity, &z8530->tpc); } else { z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE); z8530->tpc &= ~(TPC_DTR|TPC_RTS); } z8530->txidle = 1; /* Report SER_INT_TXIDLE. */ (void)z8530_bus_getsig(sc); uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD); uart_barrier(bas); uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA); uart_barrier(bas); uart_setmreg(bas, WR_IV, 0); uart_barrier(bas); uart_setmreg(bas, WR_TPC, z8530->tpc); uart_barrier(bas); uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE); uart_barrier(bas); return (0); } static int z8530_bus_detach(struct uart_softc *sc) { return (0); } static int z8530_bus_flush(struct uart_softc *sc, int what) { return (0); } static int z8530_bus_getsig(struct uart_softc *sc) { uint32_t new, old, sig; uint8_t bes; do { old = sc->sc_hwsig; sig = old; uart_lock(sc->sc_hwmtx); bes = uart_getmreg(&sc->sc_bas, RR_BES); uart_unlock(sc->sc_hwmtx); SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); new = sig & ~SER_MASK_DELTA; } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); return (sig); } static int z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) { struct z8530_softc *z8530 = (struct z8530_softc*)sc; struct uart_bas *bas; int baudrate, divisor, error; bas = &sc->sc_bas; error = 0; uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: if (data) z8530->tpc |= TPC_BRK; else z8530->tpc &= ~TPC_BRK; uart_setmreg(bas, WR_TPC, z8530->tpc); uart_barrier(bas); break; case UART_IOCTL_BAUD: divisor = uart_getmreg(bas, RR_TCH); divisor = (divisor << 8) | uart_getmreg(bas, RR_TCL); baudrate = bas->rclk / 2 / (divisor + 2); *(int*)data = baudrate; break; default: error = EINVAL; break; } uart_unlock(sc->sc_hwmtx); return (error); } static int z8530_bus_ipend(struct uart_softc *sc) { struct z8530_softc *z8530 = (struct z8530_softc*)sc; struct uart_bas *bas; int ipend; uint32_t sig; uint8_t bes, ip, iv, src; bas = &sc->sc_bas; ipend = 0; uart_lock(sc->sc_hwmtx); switch (bas->chan) { case 1: ip = uart_getmreg(bas, RR_IP); break; case 2: /* XXX hack!!! */ iv = uart_getmreg(bas, RR_IV) & 0x0E; switch (iv) { case IV_TEB: ip = IP_TIA; break; case IV_XSB: ip = IP_SIA; break; case IV_RAB: ip = IP_RIA; break; default: ip = 0; break; } break; default: ip = 0; break; } if (ip & IP_RIA) ipend |= SER_INT_RXREADY; if (ip & IP_TIA) { uart_setreg(bas, REG_CTRL, CR_RSTTXI); uart_barrier(bas); if (z8530->txidle) { ipend |= SER_INT_TXIDLE; z8530->txidle = 0; /* Mask SER_INT_TXIDLE. */ } } if (ip & IP_SIA) { uart_setreg(bas, REG_CTRL, CR_RSTXSI); uart_barrier(bas); bes = uart_getmreg(bas, RR_BES); if (bes & BES_BRK) ipend |= SER_INT_BREAK; sig = sc->sc_hwsig; SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); if (sig & SER_MASK_DELTA) ipend |= SER_INT_SIGCHG; src = uart_getmreg(bas, RR_SRC); if (src & SRC_OVR) { uart_setreg(bas, REG_CTRL, CR_RSTERR); uart_barrier(bas); ipend |= SER_INT_OVERRUN; } } if (ipend) { uart_setreg(bas, REG_CTRL, CR_RSTIUS); uart_barrier(bas); } uart_unlock(sc->sc_hwmtx); return (ipend); } static int z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, int stopbits, int parity) { struct z8530_softc *z8530 = (struct z8530_softc*)sc; int error; uart_lock(sc->sc_hwmtx); error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, &z8530->tpc); uart_unlock(sc->sc_hwmtx); return (error); } static int z8530_bus_probe(struct uart_softc *sc) { char buf[80]; int error; char ch; error = z8530_probe(&sc->sc_bas); if (error) return (error); sc->sc_rxfifosz = 3; sc->sc_txfifosz = 1; ch = sc->sc_bas.chan - 1 + 'A'; snprintf(buf, sizeof(buf), "z8530, channel %c", ch); device_set_desc_copy(sc->sc_dev, buf); return (0); } static int z8530_bus_receive(struct uart_softc *sc) { struct uart_bas *bas; int xc; uint8_t bes, src; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); bes = uart_getmreg(bas, RR_BES); while (bes & BES_RXA) { if (uart_rx_full(sc)) { sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; } xc = uart_getreg(bas, REG_DATA); uart_barrier(bas); src = uart_getmreg(bas, RR_SRC); if (src & SRC_FE) xc |= UART_STAT_FRAMERR; if (src & SRC_PE) xc |= UART_STAT_PARERR; if (src & SRC_OVR) xc |= UART_STAT_OVERRUN; uart_rx_put(sc, xc); if (src & (SRC_FE | SRC_PE | SRC_OVR)) { uart_setreg(bas, REG_CTRL, CR_RSTERR); uart_barrier(bas); } bes = uart_getmreg(bas, RR_BES); } /* Discard everything left in the Rx FIFO. */ while (bes & BES_RXA) { (void)uart_getreg(bas, REG_DATA); uart_barrier(bas); src = uart_getmreg(bas, RR_SRC); if (src & (SRC_FE | SRC_PE | SRC_OVR)) { uart_setreg(bas, REG_CTRL, CR_RSTERR); uart_barrier(bas); } bes = uart_getmreg(bas, RR_BES); } uart_unlock(sc->sc_hwmtx); return (0); } static int z8530_bus_setsig(struct uart_softc *sc, int sig) { struct z8530_softc *z8530 = (struct z8530_softc*)sc; struct uart_bas *bas; uint32_t new, old; bas = &sc->sc_bas; do { old = sc->sc_hwsig; new = old; if (sig & SER_DDTR) { SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); } if (sig & SER_DRTS) { SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); } } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); uart_lock(sc->sc_hwmtx); if (new & SER_DTR) z8530->tpc |= TPC_DTR; else z8530->tpc &= ~TPC_DTR; if (new & SER_RTS) z8530->tpc |= TPC_RTS; else z8530->tpc &= ~TPC_RTS; uart_setmreg(bas, WR_TPC, z8530->tpc); uart_barrier(bas); uart_unlock(sc->sc_hwmtx); return (0); } static int z8530_bus_transmit(struct uart_softc *sc) { struct z8530_softc *z8530 = (struct z8530_softc*)sc; struct uart_bas *bas; bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) ; uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); uart_barrier(bas); sc->sc_txbusy = 1; z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */ uart_unlock(sc->sc_hwmtx); return (0); } + +static void +z8530_bus_grab(struct uart_softc *sc) +{ + struct uart_bas *bas; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE); + uart_barrier(bas); + uart_unlock(sc->sc_hwmtx); +} + +static void +z8530_bus_ungrab(struct uart_softc *sc) +{ + struct uart_bas *bas; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA); + uart_barrier(bas); + uart_unlock(sc->sc_hwmtx); +} diff --git a/sys/dev/uart/uart_if.m b/sys/dev/uart/uart_if.m index bfac07134486..aab777172fb0 100644 --- a/sys/dev/uart/uart_if.m +++ b/sys/dev/uart/uart_if.m @@ -1,143 +1,159 @@ #- # Copyright (c) 2003 Marcel Moolenaar # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # $FreeBSD$ #include #include #include #include #include #include #include #include # The UART hardware interface. The core UART code is hardware independent. # The details of the hardware are abstracted by the UART hardware interface. INTERFACE uart; # attach() - attach hardware. # This method is called when the device is being attached. All resources # have been allocated. The transmit and receive buffers exist, but no # high-level (ie tty) initialization has been done yet. # The intend of this method is to setup the hardware for normal operation. METHOD int attach { struct uart_softc *this; }; # detach() - detach hardware. # This method is called when a device is being detached from its bus. It # is the first action performed, so even the high-level (ie tty) interface # is still operational. # The intend of this method is to disable the hardware. METHOD int detach { struct uart_softc *this; }; # flush() - flush FIFOs. # This method is called to flush the transmitter and/or the receiver as # specified by the what argument. Characters are expected to be lost. METHOD int flush { struct uart_softc *this; int what; }; # getsig() - get line and modem signals. # This method retrieves the DTE and DCE signals and their corresponding # delta bits. The delta bits include those corresponding to DTE signals # when they were changed by a call to setsig. The delta bits maintained # by the hardware driver are cleared as a side-effect. A second call to # this function will not have any delta bits set, unless there was a # change in the signals in the mean time. METHOD int getsig { struct uart_softc *this; }; # ioctl() - get or set miscellaneous parameters. # This method is the bitbucket method. It can (and will) be used when there's # something we need to set or get for which a new method is overkill. It's # used for example to set HW or SW flow-control. METHOD int ioctl { struct uart_softc *this; int request; intptr_t data; }; # ipend() - query UART for pending interrupts. # When an interrupt is signalled, the handler will call this method to find # out which of the interrupt sources needs attention. The handler will use # this information to dispatch service routines that deal with each of the # interrupt sources. An advantage of this approach is that it allows multi- # port drivers (like puc(4)) to query multiple devices concurrently and # service them on an interrupt priority basis. If the hardware cannot provide # the information reliably, it is free to service the interrupt and return 0, # meaning that no attention is required. METHOD int ipend { struct uart_softc *this; } # param() - set communication parameters. # This method is called to change the communication parameters. METHOD int param { struct uart_softc *this; int baudrate; int databits; int stopbits; int parity; }; # probe() - detect hardware. # This method is called as part of the bus probe to make sure the # hardware exists. This function should also set the device description # to something that represents the hardware. METHOD int probe { struct uart_softc *this; }; # receive() - move data from the receive FIFO to the receive buffer. # This method is called to move received data to the receive buffer and # additionally should make sure the receive interrupt should be cleared. METHOD int receive { struct uart_softc *this; }; # setsig() - set line and modem signals. # This method allows changing DTE signals. The DTE delta bits indicate which # signals are to be changed and the DTE bits themselves indicate whether to # set or clear the signals. A subsequent call to getsig will return with the # DTE delta bits set of those DTE signals that did change by this method. METHOD int setsig { struct uart_softc *this; int sig; }; # transmit() - move data from the transmit buffer to the transmit FIFO. # This method is responsible for writing the Tx buffer to the UART and # additionally should make sure that a transmit interrupt is generated # when transmission is complete. METHOD int transmit { struct uart_softc *this; }; + +# grab() - Up call from the console to the upper layers of the driver when +# the kernel asks to grab the console. This is valid only for console +# drivers. This method is responsible for transitioning the hardware +# from an interrupt driven state to a polled state that works with the +# low-level console interface defined for this device. The kernel +# currently only calls this when it wants to grab input from the +# console. Output can still happen asyncrhonously to these calls. +METHOD void grab { + struct uart_softc *this; +}; + +# ungrab() - Undoes the effects of grab(). +METHOD void ungrab { + struct uart_softc *this; +};