diff --git a/include/Makefile b/include/Makefile index 922337a87772..ce8c49d3a7cd 100644 --- a/include/Makefile +++ b/include/Makefile @@ -1,506 +1,511 @@ # @(#)Makefile 8.2 (Berkeley) 1/4/94 # $FreeBSD$ # # Doing a "make install" builds /usr/include. .include PACKAGE=runtime CLEANFILES= osreldate.h version SUBDIR= arpa protocols rpcsvc rpc xlocale .if ${MACHINE_CPUARCH} == "amd64" -SUBDIR+= i386 +SUBDIR+= i386 +INCLUDE_SUBDIRS+= i386 +.endif +.if ${MACHINE_CPUARCH} == "aarch64" +SUBDIR+= arm +INCLUDE_SUBDIRS+= arm .endif SUBDIR_PARALLEL= INCS= a.out.h ar.h assert.h bitstring.h byteswap.h \ complex.h cpio.h _ctype.h ctype.h \ db.h \ dirent.h dlfcn.h elf.h elf-hints.h endian.h err.h fmtmsg.h fnmatch.h \ fstab.h fts.h ftw.h getopt.h glob.h grp.h \ ieeefp.h ifaddrs.h \ inttypes.h iso646.h kenv.h langinfo.h libgen.h limits.h link.h \ locale.h malloc.h malloc_np.h memory.h monetary.h mpool.h mqueue.h \ ndbm.h netconfig.h \ netdb.h nl_types.h nlist.h nss.h nsswitch.h paths.h \ printf.h proc_service.h pthread.h \ pthread_np.h pwd.h ranlib.h readpassphrase.h regex.h \ res_update.h resolv.h runetype.h sched.h \ search.h semaphore.h setjmp.h \ signal.h spawn.h stab.h stdalign.h stdbool.h stddef.h \ stdnoreturn.h stdio.h stdlib.h string.h stringlist.h \ strings.h sysexits.h tar.h termios.h tgmath.h \ time.h timeconv.h timers.h ttyent.h \ uchar.h ulimit.h unistd.h utime.h utmpx.h uuid.h varargs.h \ wchar.h wctype.h wordexp.h xlocale.h .PATH: ${SRCTOP}/contrib/libc-vis INCS+= vis.h MHDRS= float.h floatingpoint.h stdarg.h PHDRS= _semaphore.h LHDRS= aio.h errno.h fcntl.h linker_set.h poll.h stdatomic.h stdint.h \ syslog.h ucontext.h LDIRS= geom net net80211 netgraph netinet netinet6 \ netipsec netlink netsmb nfs nfsclient nfsserver sys vm LSUBDIRS= dev/acpica dev/agp dev/ciss dev/filemon dev/firewire \ dev/hwpmc dev/hyperv \ dev/ic dev/iicbus dev/io dev/mfi dev/mmc \ dev/ofw dev/pbio dev/pci ${_dev_powermac_nvram} dev/ppbus dev/pwm \ dev/smbus dev/speaker dev/tcp_log dev/veriexec dev/vkbd dev/wg \ fs/devfs fs/fdescfs fs/msdosfs fs/nfs fs/nullfs \ fs/procfs fs/smbfs fs/udf fs/unionfs \ geom/cache geom/concat geom/eli geom/gate geom/journal geom/label \ geom/mirror geom/mountver geom/multipath geom/nop \ geom/raid geom/raid3 geom/shsec geom/stripe geom/union geom/virstor \ net/altq \ net/route \ netgraph/netflow \ netinet/cc \ netinet/netdump \ netinet/tcp_stacks \ netlink/route \ security/mac_biba security/mac_bsdextended security/mac_lomac \ security/mac_mls security/mac_partition \ security/mac_veriexec \ sys/disk \ ufs/ffs ufs/ufs LSUBSUBDIRS= dev/mpt/mpilib .PATH: ${SRCTOP}/sys/dev/acpica ACPICA= acpi_hpet.h \ acpiio.h ACPICADIR= ${INCLUDEDIR}/dev/acpica .PATH: ${SRCTOP}/sys/dev/agp AGP= agpreg.h AGPDIR= ${INCLUDEDIR}/dev/agp .PATH: ${SRCTOP}/sys/bsm BSM= audit.h \ audit_errno.h \ audit_internal.h \ audit_record.h \ audit_domain.h \ audit_fcntl.h \ audit_kevents.h \ audit_socket_type.h BSMPACKAGE= libbsm BSMDIR= ${INCLUDEDIR}/bsm .PATH: ${SRCTOP}/sys/security/audit SECAUDIT= audit.h \ audit_ioctl.h \ audit_private.h SECAUDITPACKAGE= libbsm SECAUDITDIR= ${INCLUDEDIR}/security/audit .PATH: ${SRCTOP}/sys/cam CAM= cam.h \ cam_ccb.h \ cam_compat.h \ cam_debug.h \ cam_iosched.h \ cam_periph.h \ cam_queue.h \ cam_sim.h \ cam_xpt.h \ cam_xpt_internal.h \ cam_xpt_periph.h \ cam_xpt_sim.h CAMDIR= ${INCLUDEDIR}/cam .PATH: ${SRCTOP}/sys/cam/ata CAMATA= ata_all.h CAMATADIR= ${INCLUDEDIR}/cam/ata .PATH: ${SRCTOP}/sys/cam/mmc CAMMMC= mmc.h \ mmc_bus.h \ mmc_all.h CAMMMCDIR= ${INCLUDEDIR}/cam/mmc .PATH: ${SRCTOP}/sys/cam/nvme CAMNVME= nvme_all.h CAMNVMEDIR= ${INCLUDEDIR}/cam/nvme .PATH: ${SRCTOP}/sys/cam/scsi CAMSCSI= scsi_all.h \ scsi_cd.h \ scsi_ch.h \ scsi_da.h \ scsi_enc.h \ scsi_enc_internal.h \ scsi_iu.h \ scsi_message.h \ scsi_pass.h \ scsi_pt.h \ scsi_sa.h \ scsi_ses.h \ scsi_sg.h \ scsi_targetio.h \ smp_all.h CAMSCSIDIR= ${INCLUDEDIR}/cam/scsi .PATH: ${SRCTOP}/sys/fs/cd9660 FS9660= cd9660_mount.h \ cd9660_node.h \ cd9660_rrip.h \ iso.h \ iso_rrip.h FS9660DIR= ${INCLUDEDIR}/isofs/cd9660 .PATH: ${SRCTOP}/sys/dev/evdev EVDEV= input.h \ input-event-codes.h \ uinput.h EVDEVDIR= ${INCLUDEDIR}/dev/evdev .PATH: ${SRCTOP}/sys/dev/hid HID= hid.h \ hidraw.h HIDDIR= ${INCLUDEDIR}/dev/hid .PATH: ${SRCTOP}/sys/dev/hyperv/include ${SRCTOP}/sys/dev/hyperv/utilities HYPERV= hv_snapshot.h \ hyperv.h HYPERVDIR= ${INCLUDEDIR}/dev/hyperv .PATH: ${SRCTOP}/sys/opencrypto OPENCRYPTO= cryptodev.h OPENCRYPTODIR= ${INCLUDEDIR}/crypto .PATH: ${SRCTOP}/sys/dev/nvme NVME= nvme.h NVMEDIR= ${INCLUDEDIR}/dev/nvme .PATH: ${SRCTOP}/sys/dev/pci PCI= pcireg.h PCIDIR= ${INCLUDEDIR}/dev/pci .PATH: ${SRCTOP}/sys/dev/veriexec VERIEXEC= veriexec_ioctl.h VERIEXECDIR= ${INCLUDEDIR}/dev/veriexec .PATH: ${SRCTOP}/sys/netpfil/ipfilter/netinet IPFILTER= ip_auth.h \ ip_compat.h \ ip_dstlist.h \ ip_fil.h \ ip_frag.h \ ip_htable.h \ ip_lookup.h \ ip_nat.h \ ip_pool.h \ ip_proxy.h \ ip_rules.h \ ip_scan.h \ ip_state.h \ ip_sync.h \ ipf_rb.h \ ipl.h \ radix_ipf.h IPFILTERDIR= ${INCLUDEDIR}/netinet .PATH: ${SRCTOP}/sys/netpfil/pf PF= pf.h \ pf_altq.h \ pf_mtag.h PFPACKAGE= pf PFDIR= ${INCLUDEDIR}/netpfil/pf .PATH: ${SRCTOP}/sys/rpc RPC= rpcsec_tls.h \ types.h RPCDIR= ${INCLUDEDIR}/rpc .PATH: ${SRCTOP}/sys/teken TEKEN= teken.h TEKENDIR= ${INCLUDEDIR}/teken .PATH: ${SRCTOP}/sys/contrib/openzfs/include/sys NVPAIR= nvpair.h NVPAIRDIR= ${INCLUDEDIR}/sys .PATH: ${SRCTOP}/sys/dev/mlx5 MLX5= mlx5io.h MLX5DIR= ${INCLUDEDIR}/dev/mlx5 .PATH: ${SRCTOP}/sys/dev/wg WG= if_wg.h WGDIR= ${INCLUDEDIR}/dev/wg INCSGROUPS= INCS \ ACPICA \ AGP \ BSM \ CAM \ CAMATA \ CAMMMC \ CAMNVME \ CAMSCSI \ CRYPTO \ EVDEV \ FS9660 \ HID \ HYPERV \ OPENCRYPTO \ NVME \ PCI \ RPC \ SECAUDIT \ TEKEN \ VERIEXEC \ WG .if ${MK_IPFILTER} != "no" INCSGROUPS+= IPFILTER .endif .if ${MK_PF} != "no" INCSGROUPS+= PF .endif .if ${MK_CDDL} != "no" INCSGROUPS+= NVPAIR .endif .if ${MK_MLX5TOOL} != "no" INCSGROUPS+= MLX5 .endif .if ${MK_BLUETOOTH} != "no" LSUBSUBDIRS+= netgraph/bluetooth/include .endif .if ${MK_CUSE} != "no" LSUBDIRS+= fs/cuse .endif .if ${MK_GSSAPI} != "no" SUBDIR+= gssapi INCS+= gssapi.h .endif .if ${MK_HESIOD} != "no" INCS+= hesiod.h .endif # Handle the #define aliases for libiconv .if ${MK_ICONV} == "yes" INCS+= iconv.h .endif .if ${MK_USB} != "no" LSUBDIRS+= dev/usb .endif .if ${MACHINE_CPUARCH} == "powerpc" && ${MACHINE_ARCH} != "powerpcspe" _dev_powermac_nvram= dev/powermac_nvram .endif # Define SHARED to indicate whether you want symbolic links to the system # source (``symlinks''), or a separate copy (``copies''). ``symlinks'' is # probably only useful for developers and should be avoided if you do not # wish to tie your /usr/include and /usr/src together. #SHARED= symlinks SHARED?= copies INCS+= osreldate.h SYSDIR= ${SRCTOP}/sys NEWVERS_SH= ${SYSDIR}/conf/newvers.sh PARAM_H= ${SYSDIR}/sys/param.h MK_OSRELDATE_SH= ${.CURDIR}/mk-osreldate.sh SYMLINKS+= ${LIBDIR:C,[^/]+,..,g:C,^/,,}${INCLUDEDIR} ${LIBDIR}/include osreldate.h: ${NEWVERS_SH} ${PARAM_H} ${MK_OSRELDATE_SH} env NEWVERS_SH=${NEWVERS_SH} PARAMFILE=${PARAM_H} SYSDIR=${SYSDIR} \ sh ${MK_OSRELDATE_SH} .for i in ${LHDRS} INCSLINKS+= sys/$i ${INCLUDEDIR}/$i .endfor .for i in ${MHDRS} INCSLINKS+= machine/$i ${INCLUDEDIR}/$i .endfor .for i in ${PHDRS} INCSLINKS+= sys/$i ${INCLUDEDIR}/$i .endfor .if ${MACHINE} != ${MACHINE_CPUARCH} _MARCHS= ${MACHINE_CPUARCH} .endif .if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" _MARCHS+= x86 .endif META_TARGETS+= compat stage_includes: ${SHARED} SDESTDIR= ${SYSROOT:U${DESTDIR}} # Take care of stale directory-level symlinks. # Note: The "|| true" after find is needed in case one of the directories does # not exist (yet). compat: cd ${SDESTDIR}${INCLUDEDIR}; find ${LDIRS} ${LSUBDIRS} machine ${_MARCHS} \ crypto -maxdepth 0 -mindepth 0 -type l -print -delete || true mtree -deU ${NO_ROOT:D-W} ${MTREE_FOLLOWS_SYMLINKS} \ -f ${SRCTOP}/etc/mtree/BSD.include.dist \ -p ${SDESTDIR}${INCLUDEDIR} > /dev/null -.if ${MACHINE_CPUARCH} == "amd64" +.for d in ${INCLUDE_SUBDIRS} ${INSTALL} -d ${TAG_ARGS} -o ${BINOWN} -g ${BINGRP} -m 755 \ - ${SDESTDIR}${INCLUDEDIR}/i386 -.endif + ${SDESTDIR}${INCLUDEDIR}/${d} +.endfor copies: .PHONY .META cd ${SDESTDIR}${INCLUDEDIR}; find ${LDIRS} ${LSUBDIRS} ${LSUBSUBDIRS} crypto \ machine machine/pc ${_MARCHS} -maxdepth 1 -mindepth 1 -type l \ -name "*.h" -print -delete || true .for i in ${LDIRS} ${LSUBDIRS:Ndev/agp:Ndev/acpica:Ndev/evdev:Ndev/hid:Ndev/hyperv:Ndev/pci:Ndev/veriexec:Ndev/wg} ${LSUBSUBDIRS} cd ${SRCTOP}/sys; \ ${INSTALL} -C ${TAG_ARGS:D${TAG_ARGS},dev} -o ${BINOWN} -g ${BINGRP} -m 444 $i/*.h \ ${SDESTDIR}${INCLUDEDIR}/$i .endfor cd ${SRCTOP}/sys/${MACHINE}/include; \ ${INSTALL} -C ${TAG_ARGS:D${TAG_ARGS},dev} -o ${BINOWN} -g ${BINGRP} -m 444 *.h \ ${SDESTDIR}${INCLUDEDIR}/machine .if exists(${SRCTOP}/sys/${MACHINE}/include/pc) cd ${SRCTOP}/sys/${MACHINE}/include/pc; \ ${INSTALL} -C ${TAG_ARGS:D${TAG_ARGS},dev} -o ${BINOWN} -g ${BINGRP} -m 444 *.h \ ${SDESTDIR}${INCLUDEDIR}/machine/pc .endif .for _MARCH in ${_MARCHS} .if exists(${SRCTOP}/sys/${_MARCH}/include) ${INSTALL} -d ${TAG_ARGS:D${TAG_ARGS},dev} -o ${BINOWN} -g ${BINGRP} -m 755 \ ${SDESTDIR}${INCLUDEDIR}/${_MARCH}; \ cd ${SRCTOP}/sys/${_MARCH}/include; \ ${INSTALL} -C ${TAG_ARGS:D${TAG_ARGS},dev} -o ${BINOWN} -g ${BINGRP} -m 444 *.h \ ${SDESTDIR}${INCLUDEDIR}/${_MARCH} .if exists(${SRCTOP}/sys/${_MARCH}/include/pc) ${INSTALL} -d ${TAG_ARGS:D${TAG_ARGS},dev} -o ${BINOWN} -g ${BINGRP} -m 755 \ ${SDESTDIR}${INCLUDEDIR}/${_MARCH}/pc; \ cd ${SRCTOP}/sys/${_MARCH}/include/pc; \ ${INSTALL} -C ${TAG_ARGS:D${TAG_ARGS},dev} -o ${BINOWN} -g ${BINGRP} -m 444 *.h \ ${SDESTDIR}${INCLUDEDIR}/${_MARCH}/pc .endif .endif .endfor symlinks: .PHONY .META @${ECHO} "Setting up symlinks to kernel source tree..." .for i in ${LDIRS} cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../%s ' sys/$i/*.h) ${SDESTDIR}${INCLUDEDIR}/$i .endfor .for i in ${LSUBDIRS:Ndev/agp:Ndev/acpica:Ndev/evdev:Ndev/hid:Ndev/hyperv:Ndev/pci:Ndev/veriexec:Ndev/wg} cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../../%s ' sys/$i/*.h) ${SDESTDIR}${INCLUDEDIR}/$i .endfor ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../../sys/dev/acpica/%s ' acpiio.h acpi_hpet.h) \ ${SDESTDIR}${INCLUDEDIR}/dev/acpica; \ ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} ../../../../sys/dev/agp/agpreg.h \ ${SDESTDIR}${INCLUDEDIR}/dev/agp; \ ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../../sys/dev/evdev/%s ' input.h input-event-codes.h uinput.h) \ ${SDESTDIR}${INCLUDEDIR}/dev/evdev; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../../sys/dev/hid/%s ' hid.h hidraw.h) \ ${SDESTDIR}${INCLUDEDIR}/dev/hid; \ ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} ../../../../sys/dev/hyperv/include/hyperv.h \ ${SDESTDIR}${INCLUDEDIR}/dev/hyperv; \ ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} ../../../../sys/dev/hyperv/utilities/hv_snapshot.h \ ${SDESTDIR}${INCLUDEDIR}/dev/hyperv; \ ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} ../../../../sys/dev/pci/pcireg.h \ ${SDESTDIR}${INCLUDEDIR}/dev/pci; \ ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} ../../../../sys/dev/veriexec/veriexec_ioctl.h \ ${SDESTDIR}${INCLUDEDIR}/dev/veriexec; .for i in ${LSUBSUBDIRS} cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../../../%s ' sys/$i/*.h) ${SDESTDIR}${INCLUDEDIR}/$i .endfor .if ${MK_IPFILTER} != "no" cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../%s ' sys/netpfil/ipfilter/netinet/*.h) \ ${SDESTDIR}${INCLUDEDIR}/netinet; .endif .if ${MK_PF} != "no" cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../../%s ' sys/netpfil/pf/*.h) \ ${SDESTDIR}${INCLUDEDIR}/netpfil/pf; .endif ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} ../../../sys/opencrypto/cryptodev.h \ ${SDESTDIR}${INCLUDEDIR}/crypto; \ cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../%s ' sys/${MACHINE}/include/*.h) \ ${SDESTDIR}${INCLUDEDIR}/machine; .if exists(${SRCTOP}/sys/${MACHINE}/include/pc) cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../../%s ' sys/${MACHINE}/include/pc/*.h) \ ${SDESTDIR}${INCLUDEDIR}/machine/pc; .endif .for _MARCH in ${_MARCHS} .if exists(${SRCTOP}/sys/${_MARCH}/include) ${INSTALL} -d ${TAG_ARGS:D${TAG_ARGS},dev} -o ${BINOWN} -g ${BINGRP} -m 755 \ ${SDESTDIR}${INCLUDEDIR}/${_MARCH}; \ cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../%s ' sys/${_MARCH}/include/*.h) \ ${SDESTDIR}${INCLUDEDIR}/${_MARCH}; .if exists(${SRCTOP}/sys/${_MARCH}/include/pc) ${INSTALL} -d ${TAG_ARGS:D${TAG_ARGS},dev} -o ${BINOWN} -g ${BINGRP} -m 755 \ ${SDESTDIR}${INCLUDEDIR}/${_MARCH}/pc; \ cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../../%s ' sys/${_MARCH}/include/pc/*.h) \ ${SDESTDIR}${INCLUDEDIR}/${_MARCH}/pc; .endif .endif .endfor cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../../%s ' sys/fs/cd9660/*.h) \ ${SDESTDIR}${INCLUDEDIR}/isofs/cd9660; \ cd ${SRCTOP}; ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ $$(printf '../../../sys/rpc/%s ' rpcsec_tls.h types.h) \ ${SDESTDIR}${INCLUDEDIR}/rpc; cd ${SRCTOP}/sys/rpc; .if ${MK_CDDL} != "no" ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} \ ../../../sys/contrib/openzfs/include/sys/nvpair.h \ ${SDESTDIR}${INCLUDEDIR}/sys .endif .if ${MK_MLX5TOOL} != "no" ${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},dev} ../../../../sys/dev/mlx5/mlx5io.h \ ${SDESTDIR}${INCLUDEDIR}/dev/mlx5 .endif .include installincludes: ${SHARED} ${SHARED}: compat .if ${MACHINE} == "host" && !defined(_SKIP_BUILD) # we're here because we are building a sysroot... # we need MACHINE et al set correctly HOST_MACHINE!= uname -m HOST_MACHINE_ARCH!= uname -p MACHINE:= ${HOST_MACHINE} MACHINE_ARCH:= ${HOST_MACHINE_ARCH} .endif check-ldirs: missing_dirs=""; \ for dir in ${LDIRS} ${LSUBDIRS} ${LSUBSUBDIRS}; do \ if [ ! -d ${SRCTOP}/sys/$$dir ]; then \ echo "${SRCTOP}/sys/$$dir"; \ missing_dirs="$$missing_dirs $$dir"; \ fi; \ done; \ if [ -n "$$missing_dirs" ]; then \ echo "Nonexistant directories:" $$missing_dirs; \ false; \ fi diff --git a/include/arm/Makefile b/include/arm/Makefile new file mode 100644 index 000000000000..1f596763df77 --- /dev/null +++ b/include/arm/Makefile @@ -0,0 +1,60 @@ +# arm headers installed on arm64 + +.PATH: ${SRCTOP}/sys/arm/include ${SRCTOP}/lib/msun/arm + +INCS= _align.h \ + _inttypes.h \ + _limits.h \ + _stdint.h \ + _types.h \ + acle-compat.h \ + armreg.h \ + asm.h \ + atomic.h \ + bus.h \ + counter.h \ + cpu.h \ + cpufunc.h \ + cpuinfo.h \ + efi.h \ + elf.h \ + exec.h \ + float.h \ + frame.h \ + ieeefp.h \ + param.h \ + pcb.h \ + pcpu.h \ + pmap.h \ + proc.h \ + profile.h \ + pte.h \ + reg.h \ + reloc.h \ + resource.h \ + runq.h \ + setjmp.h \ + signal.h \ + sysarch.h \ + sysreg.h \ + tls.h \ + ucontext.h \ + vdso.h \ + vfp.h \ + vmparam.h +# These kernel-only headers are used by procstat's ZFS support. +# This should be fixed. +INCS+= pcpu_aux.h \ + sf_buf.h +# from lib/msun/arm +INCS+= fenv.h +INCSDIR= ${INCLUDEDIR}/arm + +beforeinstall: armdir +META_TARGETS+= armdir + +armdir: + ${INSTALL} -d ${TAG_ARGS} -o ${BINOWN} -g ${BINGRP} -m 755 \ + ${DESTDIR}${INCLUDEDIR}/arm + +.include diff --git a/lib/msun/aarch64/fenv.h b/lib/msun/aarch64/fenv.h index 2a55db3a9545..80b3fdf4cc1b 100644 --- a/lib/msun/aarch64/fenv.h +++ b/lib/msun/aarch64/fenv.h @@ -1,246 +1,252 @@ /*- * Copyright (c) 2004-2005 David Schultz * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* __arm__ */ + #ifndef _FENV_H_ #define _FENV_H_ #include #ifndef __fenv_static #define __fenv_static static #endif /* The high 32 bits contain fpcr, low 32 contain fpsr. */ typedef __uint64_t fenv_t; typedef __uint64_t fexcept_t; /* Exception flags */ #define FE_INVALID 0x00000001 #define FE_DIVBYZERO 0x00000002 #define FE_OVERFLOW 0x00000004 #define FE_UNDERFLOW 0x00000008 #define FE_INEXACT 0x00000010 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) /* * Rounding modes * * We can't just use the hardware bit values here, because that would * make FE_UPWARD and FE_DOWNWARD negative, which is not allowed. */ #define FE_TONEAREST 0x0 #define FE_UPWARD 0x1 #define FE_DOWNWARD 0x2 #define FE_TOWARDZERO 0x3 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ FE_UPWARD | FE_TOWARDZERO) #define _ROUND_SHIFT 22 __BEGIN_DECLS /* Default floating-point environment */ extern const fenv_t __fe_dfl_env; #define FE_DFL_ENV (&__fe_dfl_env) /* We need to be able to map status flag positions to mask flag positions */ #define _FPUSW_SHIFT 8 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) #define __mrs_fpcr(__r) __asm __volatile("mrs %0, fpcr" : "=r" (__r)) #define __msr_fpcr(__r) __asm __volatile("msr fpcr, %0" : : "r" (__r)) #define __mrs_fpsr(__r) __asm __volatile("mrs %0, fpsr" : "=r" (__r)) #define __msr_fpsr(__r) __asm __volatile("msr fpsr, %0" : : "r" (__r)) __fenv_static __inline int feclearexcept(int __excepts) { fexcept_t __r; __mrs_fpsr(__r); __r &= ~__excepts; __msr_fpsr(__r); return (0); } __fenv_static inline int fegetexceptflag(fexcept_t *__flagp, int __excepts) { fexcept_t __r; __mrs_fpsr(__r); *__flagp = __r & __excepts; return (0); } __fenv_static inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts) { fexcept_t __r; __mrs_fpsr(__r); __r &= ~__excepts; __r |= *__flagp & __excepts; __msr_fpsr(__r); return (0); } __fenv_static inline int feraiseexcept(int __excepts) { fexcept_t __r; __mrs_fpsr(__r); __r |= __excepts; __msr_fpsr(__r); return (0); } __fenv_static inline int fetestexcept(int __excepts) { fexcept_t __r; __mrs_fpsr(__r); return (__r & __excepts); } __fenv_static inline int fegetround(void) { fenv_t __r; __mrs_fpcr(__r); return ((__r >> _ROUND_SHIFT) & _ROUND_MASK); } __fenv_static inline int fesetround(int __round) { fenv_t __r; if (__round & ~_ROUND_MASK) return (-1); __mrs_fpcr(__r); __r &= ~(_ROUND_MASK << _ROUND_SHIFT); __r |= __round << _ROUND_SHIFT; __msr_fpcr(__r); return (0); } __fenv_static inline int fegetenv(fenv_t *__envp) { __uint64_t fpcr; __uint64_t fpsr; __mrs_fpcr(fpcr); __mrs_fpsr(fpsr); *__envp = fpsr | (fpcr << 32); return (0); } __fenv_static inline int feholdexcept(fenv_t *__envp) { fenv_t __r; __mrs_fpcr(__r); *__envp = __r << 32; __r &= ~(_ENABLE_MASK); __msr_fpcr(__r); __mrs_fpsr(__r); *__envp |= (__uint32_t)__r; __r &= ~(_ENABLE_MASK); __msr_fpsr(__r); return (0); } __fenv_static inline int fesetenv(const fenv_t *__envp) { __msr_fpcr((*__envp) >> 32); __msr_fpsr((fenv_t)(__uint32_t)*__envp); return (0); } __fenv_static inline int feupdateenv(const fenv_t *__envp) { fexcept_t __r; __mrs_fpsr(__r); fesetenv(__envp); feraiseexcept(__r & FE_ALL_EXCEPT); return (0); } #if __BSD_VISIBLE /* We currently provide no external definitions of the functions below. */ static inline int feenableexcept(int __mask) { fenv_t __old_r, __new_r; __mrs_fpcr(__old_r); __new_r = __old_r | ((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT); __msr_fpcr(__new_r); return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); } static inline int fedisableexcept(int __mask) { fenv_t __old_r, __new_r; __mrs_fpcr(__old_r); __new_r = __old_r & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT); __msr_fpcr(__new_r); return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); } static inline int fegetexcept(void) { fenv_t __r; __mrs_fpcr(__r); return ((__r & _ENABLE_MASK) >> _FPUSW_SHIFT); } #endif /* __BSD_VISIBLE */ __END_DECLS #endif /* !_FENV_H_ */ + +#endif /* __arm__ */ diff --git a/sys/arm64/include/_align.h b/sys/arm64/include/_align.h index 3844133ffb68..5c153779aca3 100644 --- a/sys/arm64/include/_align.h +++ b/sys/arm64/include/_align.h @@ -1,44 +1,50 @@ /*- * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)param.h 5.8 (Berkeley) 6/28/91 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE__ALIGN_H_ #define _MACHINE__ALIGN_H_ /* * Round p (pointer or byte index) up to a correctly-aligned value * for all data types (int, long, ...). The result is unsigned int * and must be cast to any desired pointer type. */ #define _ALIGNBYTES (sizeof(long long) - 1) #define _ALIGN(p) (((u_long)(p) + _ALIGNBYTES) & ~_ALIGNBYTES) #endif /* !_MACHINE__ALIGN_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/_inttypes.h b/sys/arm64/include/_inttypes.h index df1af0b25df0..4c21d47f6c51 100644 --- a/sys/arm64/include/_inttypes.h +++ b/sys/arm64/include/_inttypes.h @@ -1,213 +1,219 @@ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Klaus Klein. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * From: $NetBSD: int_fmtio.h,v 1.4 2008/04/28 20:23:36 martin Exp $ * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE__INTTYPES_H_ #define _MACHINE__INTTYPES_H_ /* * Macros for format specifiers. */ /* fprintf(3) macros for signed integers. */ #define PRId8 "d" /* int8_t */ #define PRId16 "d" /* int16_t */ #define PRId32 "d" /* int32_t */ #define PRId64 "ld" /* int64_t */ #define PRIdLEAST8 "d" /* int_least8_t */ #define PRIdLEAST16 "d" /* int_least16_t */ #define PRIdLEAST32 "d" /* int_least32_t */ #define PRIdLEAST64 "ld" /* int_least64_t */ #define PRIdFAST8 "d" /* int_fast8_t */ #define PRIdFAST16 "d" /* int_fast16_t */ #define PRIdFAST32 "d" /* int_fast32_t */ #define PRIdFAST64 "ld" /* int_fast64_t */ #define PRIdMAX "jd" /* intmax_t */ #define PRIdPTR "ld" /* intptr_t */ #define PRIi8 "i" /* int8_t */ #define PRIi16 "i" /* int16_t */ #define PRIi32 "i" /* int32_t */ #define PRIi64 "li" /* int64_t */ #define PRIiLEAST8 "i" /* int_least8_t */ #define PRIiLEAST16 "i" /* int_least16_t */ #define PRIiLEAST32 "i" /* int_least32_t */ #define PRIiLEAST64 "li" /* int_least64_t */ #define PRIiFAST8 "i" /* int_fast8_t */ #define PRIiFAST16 "i" /* int_fast16_t */ #define PRIiFAST32 "i" /* int_fast32_t */ #define PRIiFAST64 "li" /* int_fast64_t */ #define PRIiMAX "ji" /* intmax_t */ #define PRIiPTR "li" /* intptr_t */ /* fprintf(3) macros for unsigned integers. */ #define PRIo8 "o" /* uint8_t */ #define PRIo16 "o" /* uint16_t */ #define PRIo32 "o" /* uint32_t */ #define PRIo64 "lo" /* uint64_t */ #define PRIoLEAST8 "o" /* uint_least8_t */ #define PRIoLEAST16 "o" /* uint_least16_t */ #define PRIoLEAST32 "o" /* uint_least32_t */ #define PRIoLEAST64 "lo" /* uint_least64_t */ #define PRIoFAST8 "o" /* uint_fast8_t */ #define PRIoFAST16 "o" /* uint_fast16_t */ #define PRIoFAST32 "o" /* uint_fast32_t */ #define PRIoFAST64 "lo" /* uint_fast64_t */ #define PRIoMAX "jo" /* uintmax_t */ #define PRIoPTR "lo" /* uintptr_t */ #define PRIu8 "u" /* uint8_t */ #define PRIu16 "u" /* uint16_t */ #define PRIu32 "u" /* uint32_t */ #define PRIu64 "lu" /* uint64_t */ #define PRIuLEAST8 "u" /* uint_least8_t */ #define PRIuLEAST16 "u" /* uint_least16_t */ #define PRIuLEAST32 "u" /* uint_least32_t */ #define PRIuLEAST64 "lu" /* uint_least64_t */ #define PRIuFAST8 "u" /* uint_fast8_t */ #define PRIuFAST16 "u" /* uint_fast16_t */ #define PRIuFAST32 "u" /* uint_fast32_t */ #define PRIuFAST64 "lu" /* uint_fast64_t */ #define PRIuMAX "ju" /* uintmax_t */ #define PRIuPTR "lu" /* uintptr_t */ #define PRIx8 "x" /* uint8_t */ #define PRIx16 "x" /* uint16_t */ #define PRIx32 "x" /* uint32_t */ #define PRIx64 "lx" /* uint64_t */ #define PRIxLEAST8 "x" /* uint_least8_t */ #define PRIxLEAST16 "x" /* uint_least16_t */ #define PRIxLEAST32 "x" /* uint_least32_t */ #define PRIxLEAST64 "lx" /* uint_least64_t */ #define PRIxFAST8 "x" /* uint_fast8_t */ #define PRIxFAST16 "x" /* uint_fast16_t */ #define PRIxFAST32 "x" /* uint_fast32_t */ #define PRIxFAST64 "lx" /* uint_fast64_t */ #define PRIxMAX "jx" /* uintmax_t */ #define PRIxPTR "lx" /* uintptr_t */ #define PRIX8 "X" /* uint8_t */ #define PRIX16 "X" /* uint16_t */ #define PRIX32 "X" /* uint32_t */ #define PRIX64 "lX" /* uint64_t */ #define PRIXLEAST8 "X" /* uint_least8_t */ #define PRIXLEAST16 "X" /* uint_least16_t */ #define PRIXLEAST32 "X" /* uint_least32_t */ #define PRIXLEAST64 "lX" /* uint_least64_t */ #define PRIXFAST8 "X" /* uint_fast8_t */ #define PRIXFAST16 "X" /* uint_fast16_t */ #define PRIXFAST32 "X" /* uint_fast32_t */ #define PRIXFAST64 "lX" /* uint_fast64_t */ #define PRIXMAX "jX" /* uintmax_t */ #define PRIXPTR "lX" /* uintptr_t */ /* fscanf(3) macros for signed integers. */ #define SCNd8 "hhd" /* int8_t */ #define SCNd16 "hd" /* int16_t */ #define SCNd32 "d" /* int32_t */ #define SCNd64 "ld" /* int64_t */ #define SCNdLEAST8 "hhd" /* int_least8_t */ #define SCNdLEAST16 "hd" /* int_least16_t */ #define SCNdLEAST32 "d" /* int_least32_t */ #define SCNdLEAST64 "ld" /* int_least64_t */ #define SCNdFAST8 "d" /* int_fast8_t */ #define SCNdFAST16 "d" /* int_fast16_t */ #define SCNdFAST32 "d" /* int_fast32_t */ #define SCNdFAST64 "ld" /* int_fast64_t */ #define SCNdMAX "jd" /* intmax_t */ #define SCNdPTR "ld" /* intptr_t */ #define SCNi8 "hhi" /* int8_t */ #define SCNi16 "hi" /* int16_t */ #define SCNi32 "i" /* int32_t */ #define SCNi64 "li" /* int64_t */ #define SCNiLEAST8 "hhi" /* int_least8_t */ #define SCNiLEAST16 "hi" /* int_least16_t */ #define SCNiLEAST32 "i" /* int_least32_t */ #define SCNiLEAST64 "li" /* int_least64_t */ #define SCNiFAST8 "i" /* int_fast8_t */ #define SCNiFAST16 "i" /* int_fast16_t */ #define SCNiFAST32 "i" /* int_fast32_t */ #define SCNiFAST64 "li" /* int_fast64_t */ #define SCNiMAX "ji" /* intmax_t */ #define SCNiPTR "li" /* intptr_t */ /* fscanf(3) macros for unsigned integers. */ #define SCNo8 "hho" /* uint8_t */ #define SCNo16 "ho" /* uint16_t */ #define SCNo32 "o" /* uint32_t */ #define SCNo64 "lo" /* uint64_t */ #define SCNoLEAST8 "hho" /* uint_least8_t */ #define SCNoLEAST16 "ho" /* uint_least16_t */ #define SCNoLEAST32 "o" /* uint_least32_t */ #define SCNoLEAST64 "lo" /* uint_least64_t */ #define SCNoFAST8 "o" /* uint_fast8_t */ #define SCNoFAST16 "o" /* uint_fast16_t */ #define SCNoFAST32 "o" /* uint_fast32_t */ #define SCNoFAST64 "lo" /* uint_fast64_t */ #define SCNoMAX "jo" /* uintmax_t */ #define SCNoPTR "lo" /* uintptr_t */ #define SCNu8 "hhu" /* uint8_t */ #define SCNu16 "hu" /* uint16_t */ #define SCNu32 "u" /* uint32_t */ #define SCNu64 "lu" /* uint64_t */ #define SCNuLEAST8 "hhu" /* uint_least8_t */ #define SCNuLEAST16 "hu" /* uint_least16_t */ #define SCNuLEAST32 "u" /* uint_least32_t */ #define SCNuLEAST64 "lu" /* uint_least64_t */ #define SCNuFAST8 "u" /* uint_fast8_t */ #define SCNuFAST16 "u" /* uint_fast16_t */ #define SCNuFAST32 "u" /* uint_fast32_t */ #define SCNuFAST64 "lu" /* uint_fast64_t */ #define SCNuMAX "ju" /* uintmax_t */ #define SCNuPTR "lu" /* uintptr_t */ #define SCNx8 "hhx" /* uint8_t */ #define SCNx16 "hx" /* uint16_t */ #define SCNx32 "x" /* uint32_t */ #define SCNx64 "lx" /* uint64_t */ #define SCNxLEAST8 "hhx" /* uint_least8_t */ #define SCNxLEAST16 "hx" /* uint_least16_t */ #define SCNxLEAST32 "x" /* uint_least32_t */ #define SCNxLEAST64 "lx" /* uint_least64_t */ #define SCNxFAST8 "x" /* uint_fast8_t */ #define SCNxFAST16 "x" /* uint_fast16_t */ #define SCNxFAST32 "x" /* uint_fast32_t */ #define SCNxFAST64 "lx" /* uint_fast64_t */ #define SCNxMAX "jx" /* uintmax_t */ #define SCNxPTR "lx" /* uintptr_t */ #endif /* !_MACHINE__INTTYPES_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/_limits.h b/sys/arm64/include/_limits.h index 39f0bcf0f5b2..d64a9afe1a1c 100644 --- a/sys/arm64/include/_limits.h +++ b/sys/arm64/include/_limits.h @@ -1,85 +1,91 @@ /*- * Copyright (c) 1988, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)limits.h 8.3 (Berkeley) 1/4/94 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE__LIMITS_H_ #define _MACHINE__LIMITS_H_ /* * According to ANSI (section 2.2.4.2), the values below must be usable by * #if preprocessing directives. Additionally, the expression must have the * same type as would an expression that is an object of the corresponding * type converted according to the integral promotions. The subtraction for * INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2). */ #define __CHAR_BIT 8 /* number of bits in a char */ #define __SCHAR_MAX 0x7f /* max value for a signed char */ #define __SCHAR_MIN (-0x7f - 1) /* min value for a signed char */ #define __UCHAR_MAX 0xff /* max value for an unsigned char */ #define __USHRT_MAX 0xffff /* max value for an unsigned short */ #define __SHRT_MAX 0x7fff /* max value for a short */ #define __SHRT_MIN (-0x7fff - 1) /* min value for a short */ #define __UINT_MAX 0xffffffff /* max value for an unsigned int */ #define __INT_MAX 0x7fffffff /* max value for an int */ #define __INT_MIN (-0x7fffffff - 1) /* min value for an int */ #define __ULONG_MAX 0xffffffffffffffffUL /* max for an unsigned long */ #define __LONG_MAX 0x7fffffffffffffffL /* max for a long */ #define __LONG_MIN (-0x7fffffffffffffffL - 1) /* min for a long */ /* Long longs have the same size but not the same type as longs. */ /* max for an unsigned long long */ #define __ULLONG_MAX 0xffffffffffffffffULL #define __LLONG_MAX 0x7fffffffffffffffLL /* max for a long long */ #define __LLONG_MIN (-0x7fffffffffffffffLL - 1) /* min for a long long */ #define __SSIZE_MAX __LONG_MAX /* max value for a ssize_t */ #define __SIZE_T_MAX __ULONG_MAX /* max value for a size_t */ #define __OFF_MAX __LONG_MAX /* max value for an off_t */ #define __OFF_MIN __LONG_MIN /* min value for an off_t */ /* Quads and longs are the same size. Ensure they stay in sync. */ #define __UQUAD_MAX (__ULONG_MAX) /* max value for a uquad_t */ #define __QUAD_MAX (__LONG_MAX) /* max value for a quad_t */ #define __QUAD_MIN (__LONG_MIN) /* min value for a quad_t */ #define __LONG_BIT 64 #define __WORD_BIT 32 /* Minimum signal stack size. */ #define __MINSIGSTKSZ (1024 * 4) #endif /* !_MACHINE__LIMITS_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/_stdint.h b/sys/arm64/include/_stdint.h index d73a9c088b59..6c978befc8b2 100644 --- a/sys/arm64/include/_stdint.h +++ b/sys/arm64/include/_stdint.h @@ -1,158 +1,164 @@ /*- * Copyright (c) 2001, 2002 Mike Barcroft * Copyright (c) 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Klaus Klein. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE__STDINT_H_ #define _MACHINE__STDINT_H_ #if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) #define INT8_C(c) (c) #define INT16_C(c) (c) #define INT32_C(c) (c) #define INT64_C(c) (c ## L) #define UINT8_C(c) (c) #define UINT16_C(c) (c) #define UINT32_C(c) (c ## U) #define UINT64_C(c) (c ## UL) #define INTMAX_C(c) INT64_C(c) #define UINTMAX_C(c) UINT64_C(c) #endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ #if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) /* * ISO/IEC 9899:1999 * 7.18.2.1 Limits of exact-width integer types */ /* Minimum values of exact-width signed integer types. */ #define INT8_MIN (-0x7f-1) #define INT16_MIN (-0x7fff-1) #define INT32_MIN (-0x7fffffff-1) #define INT64_MIN (-0x7fffffffffffffffL-1) /* Maximum values of exact-width signed integer types. */ #define INT8_MAX 0x7f #define INT16_MAX 0x7fff #define INT32_MAX 0x7fffffff #define INT64_MAX 0x7fffffffffffffffL /* Maximum values of exact-width unsigned integer types. */ #define UINT8_MAX 0xff #define UINT16_MAX 0xffff #define UINT32_MAX 0xffffffffU #define UINT64_MAX 0xffffffffffffffffUL /* * ISO/IEC 9899:1999 * 7.18.2.2 Limits of minimum-width integer types */ /* Minimum values of minimum-width signed integer types. */ #define INT_LEAST8_MIN INT8_MIN #define INT_LEAST16_MIN INT16_MIN #define INT_LEAST32_MIN INT32_MIN #define INT_LEAST64_MIN INT64_MIN /* Maximum values of minimum-width signed integer types. */ #define INT_LEAST8_MAX INT8_MAX #define INT_LEAST16_MAX INT16_MAX #define INT_LEAST32_MAX INT32_MAX #define INT_LEAST64_MAX INT64_MAX /* Maximum values of minimum-width unsigned integer types. */ #define UINT_LEAST8_MAX UINT8_MAX #define UINT_LEAST16_MAX UINT16_MAX #define UINT_LEAST32_MAX UINT32_MAX #define UINT_LEAST64_MAX UINT64_MAX /* * ISO/IEC 9899:1999 * 7.18.2.3 Limits of fastest minimum-width integer types */ /* Minimum values of fastest minimum-width signed integer types. */ #define INT_FAST8_MIN INT32_MIN #define INT_FAST16_MIN INT32_MIN #define INT_FAST32_MIN INT32_MIN #define INT_FAST64_MIN INT64_MIN /* Maximum values of fastest minimum-width signed integer types. */ #define INT_FAST8_MAX INT32_MAX #define INT_FAST16_MAX INT32_MAX #define INT_FAST32_MAX INT32_MAX #define INT_FAST64_MAX INT64_MAX /* Maximum values of fastest minimum-width unsigned integer types. */ #define UINT_FAST8_MAX UINT32_MAX #define UINT_FAST16_MAX UINT32_MAX #define UINT_FAST32_MAX UINT32_MAX #define UINT_FAST64_MAX UINT64_MAX /* * ISO/IEC 9899:1999 * 7.18.2.4 Limits of integer types capable of holding object pointers */ #define INTPTR_MIN INT64_MIN #define INTPTR_MAX INT64_MAX #define UINTPTR_MAX UINT64_MAX /* * ISO/IEC 9899:1999 * 7.18.2.5 Limits of greatest-width integer types */ #define INTMAX_MIN INT64_MIN #define INTMAX_MAX INT64_MAX #define UINTMAX_MAX UINT64_MAX /* * ISO/IEC 9899:1999 * 7.18.3 Limits of other integer types */ /* Limits of ptrdiff_t. */ #define PTRDIFF_MIN INT64_MIN #define PTRDIFF_MAX INT64_MAX /* Limits of sig_atomic_t. */ #define SIG_ATOMIC_MIN INT64_MIN #define SIG_ATOMIC_MAX INT64_MAX /* Limit of size_t. */ #define SIZE_MAX UINT64_MAX /* Limits of wint_t. */ #define WINT_MIN INT32_MIN #define WINT_MAX INT32_MAX #endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ #endif /* !_MACHINE__STDINT_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/_types.h b/sys/arm64/include/_types.h index 720900a270d4..69610b96fa3b 100644 --- a/sys/arm64/include/_types.h +++ b/sys/arm64/include/_types.h @@ -1,69 +1,75 @@ /*- * Copyright (c) 2002 Mike Barcroft * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 * From: @(#)types.h 8.3 (Berkeley) 1/5/94 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE__TYPES_H_ #define _MACHINE__TYPES_H_ #ifndef _SYS__TYPES_H_ #error do not include this header, use sys/_types.h #endif /* * Standard type definitions. */ typedef __int32_t __clock_t; /* clock()... */ typedef __int64_t __critical_t; #ifndef _STANDALONE typedef double __double_t; typedef float __float_t; #endif typedef __int32_t __int_fast8_t; typedef __int32_t __int_fast16_t; typedef __int32_t __int_fast32_t; typedef __int64_t __int_fast64_t; typedef __int64_t __register_t; typedef __int64_t __segsz_t; /* segment size (in pages) */ typedef __int64_t __time_t; /* time()... */ typedef __uint32_t __uint_fast8_t; typedef __uint32_t __uint_fast16_t; typedef __uint32_t __uint_fast32_t; typedef __uint64_t __uint_fast64_t; typedef __uint64_t __u_register_t; typedef __uint64_t __vm_paddr_t; typedef unsigned int ___wchar_t; #define __WCHAR_MIN 0 /* min value for a wchar_t */ #define __WCHAR_MAX __UINT_MAX /* max value for a wchar_t */ #endif /* !_MACHINE__TYPES_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/acle-compat.h b/sys/arm64/include/acle-compat.h new file mode 100644 index 000000000000..9954f27fd424 --- /dev/null +++ b/sys/arm64/include/acle-compat.h @@ -0,0 +1,5 @@ +#ifdef __arm__ +#include +#else /* !__arm__ */ +#error Do not include this header, used only for 32-bit compatibility +#endif /* !__arm__ */ diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index b40dfb206f99..f20b7a8c710e 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -1,1996 +1,2002 @@ /*- * Copyright (c) 2013, 2014 Andrew Turner * Copyright (c) 2015,2021 The FreeBSD Foundation * * Portions of this software were developed by Andrew Turner * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_ARMREG_H_ #define _MACHINE_ARMREG_H_ #define INSN_SIZE 4 #define MRS_MASK 0xfff00000 #define MRS_VALUE 0xd5300000 #define MRS_SPECIAL(insn) ((insn) & 0x000fffe0) #define MRS_REGISTER(insn) ((insn) & 0x0000001f) #define MRS_Op0_SHIFT 19 #define MRS_Op0_MASK 0x00080000 #define MRS_Op1_SHIFT 16 #define MRS_Op1_MASK 0x00070000 #define MRS_CRn_SHIFT 12 #define MRS_CRn_MASK 0x0000f000 #define MRS_CRm_SHIFT 8 #define MRS_CRm_MASK 0x00000f00 #define MRS_Op2_SHIFT 5 #define MRS_Op2_MASK 0x000000e0 #define MRS_Rt_SHIFT 0 #define MRS_Rt_MASK 0x0000001f #define __MRS_REG(op0, op1, crn, crm, op2) \ (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) | \ ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) | \ ((op2) << MRS_Op2_SHIFT)) #define MRS_REG(reg) \ __MRS_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) #define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ S##op0##_##op1##_C##crn##_C##crm##_##op2 #define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) #define MRS_REG_ALT_NAME(reg) \ _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) #define READ_SPECIALREG(reg) \ ({ uint64_t _val; \ __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ _val; \ }) #define WRITE_SPECIALREG(reg, _val) \ __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) #define UL(x) UINT64_C(x) /* CCSIDR_EL1 - Cache Size ID Register */ #define CCSIDR_NumSets_MASK 0x0FFFE000 #define CCSIDR_NumSets64_MASK 0x00FFFFFF00000000 #define CCSIDR_NumSets_SHIFT 13 #define CCSIDR_NumSets64_SHIFT 32 #define CCSIDR_Assoc_MASK 0x00001FF8 #define CCSIDR_Assoc64_MASK 0x0000000000FFFFF8 #define CCSIDR_Assoc_SHIFT 3 #define CCSIDR_Assoc64_SHIFT 3 #define CCSIDR_LineSize_MASK 0x7 #define CCSIDR_NSETS(idr) \ (((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT) #define CCSIDR_ASSOC(idr) \ (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT) #define CCSIDR_NSETS_64(idr) \ (((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT) #define CCSIDR_ASSOC_64(idr) \ (((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT) /* CLIDR_EL1 - Cache level ID register */ #define CLIDR_CTYPE_MASK 0x7 /* Cache type mask bits */ #define CLIDR_CTYPE_IO 0x1 /* Instruction only */ #define CLIDR_CTYPE_DO 0x2 /* Data only */ #define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */ #define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */ /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */ #define CNTP_CTL_EL0 MRS_REG(CNTP_CTL_EL0) #define CNTP_CTL_EL0_op0 3 #define CNTP_CTL_EL0_op1 3 #define CNTP_CTL_EL0_CRn 14 #define CNTP_CTL_EL0_CRm 2 #define CNTP_CTL_EL0_op2 1 #define CNTP_CTL_ENABLE (1 << 0) #define CNTP_CTL_IMASK (1 << 1) #define CNTP_CTL_ISTATUS (1 << 2) /* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */ #define CNTP_CVAL_EL0 MRS_REG(CNTP_CVAL_EL0) #define CNTP_CVAL_EL0_op0 3 #define CNTP_CVAL_EL0_op1 3 #define CNTP_CVAL_EL0_CRn 14 #define CNTP_CVAL_EL0_CRm 2 #define CNTP_CVAL_EL0_op2 2 /* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */ #define CNTP_TVAL_EL0 MRS_REG(CNTP_TVAL_EL0) #define CNTP_TVAL_EL0_op0 3 #define CNTP_TVAL_EL0_op1 3 #define CNTP_TVAL_EL0_CRn 14 #define CNTP_TVAL_EL0_CRm 2 #define CNTP_TVAL_EL0_op2 0 /* CNTPCT_EL0 - Counter-timer Physical Count register */ #define CNTPCT_EL0 MRS_REG(CNTPCT_EL0) #define CNTPCT_EL0_op0 3 #define CNTPCT_EL0_op1 3 #define CNTPCT_EL0_CRn 14 #define CNTPCT_EL0_CRm 0 #define CNTPCT_EL0_op2 1 /* CPACR_EL1 */ #define CPACR_ZEN_MASK (0x3 << 16) #define CPACR_ZEN_TRAP_ALL1 (0x0 << 16) /* Traps from EL0 and EL1 */ #define CPACR_ZEN_TRAP_EL0 (0x1 << 16) /* Traps from EL0 */ #define CPACR_ZEN_TRAP_ALL2 (0x2 << 16) /* Traps from EL0 and EL1 */ #define CPACR_ZEN_TRAP_NONE (0x3 << 16) /* No traps */ #define CPACR_FPEN_MASK (0x3 << 20) #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ #define CPACR_TTA (0x1 << 28) /* CSSELR_EL1 - Cache size selection register */ #define CSSELR_Level(i) (i << 1) #define CSSELR_InD 0x00000001 /* CTR_EL0 - Cache Type Register */ #define CTR_RES1 (1 << 31) #define CTR_TminLine_SHIFT 32 #define CTR_TminLine_MASK (UL(0x3f) << CTR_TminLine_SHIFT) #define CTR_TminLine_VAL(reg) ((reg) & CTR_TminLine_MASK) #define CTR_DIC_SHIFT 29 #define CTR_DIC_MASK (0x1 << CTR_DIC_SHIFT) #define CTR_DIC_VAL(reg) ((reg) & CTR_DIC_MASK) #define CTR_IDC_SHIFT 28 #define CTR_IDC_MASK (0x1 << CTR_IDC_SHIFT) #define CTR_IDC_VAL(reg) ((reg) & CTR_IDC_MASK) #define CTR_CWG_SHIFT 24 #define CTR_CWG_MASK (0xf << CTR_CWG_SHIFT) #define CTR_CWG_VAL(reg) ((reg) & CTR_CWG_MASK) #define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT)) #define CTR_ERG_SHIFT 20 #define CTR_ERG_MASK (0xf << CTR_ERG_SHIFT) #define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK) #define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT)) #define CTR_DLINE_SHIFT 16 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) #define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK) #define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT)) #define CTR_L1IP_SHIFT 14 #define CTR_L1IP_MASK (0x3 << CTR_L1IP_SHIFT) #define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK) #define CTR_L1IP_VPIPT (0 << CTR_L1IP_SHIFT) #define CTR_L1IP_AIVIVT (1 << CTR_L1IP_SHIFT) #define CTR_L1IP_VIPT (2 << CTR_L1IP_SHIFT) #define CTR_L1IP_PIPT (3 << CTR_L1IP_SHIFT) #define CTR_ILINE_SHIFT 0 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) #define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK) #define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT)) /* DAIFSet/DAIFClear */ #define DAIF_D (1 << 3) #define DAIF_A (1 << 2) #define DAIF_I (1 << 1) #define DAIF_F (1 << 0) #define DAIF_ALL (DAIF_D | DAIF_A | DAIF_I | DAIF_F) #define DAIF_INTR (DAIF_I) /* All exceptions that pass */ /* through the intr framework */ /* DBGBCR_EL1 - Debug Breakpoint Control Registers */ #define DBGBCR_EL1_op0 2 #define DBGBCR_EL1_op1 0 #define DBGBCR_EL1_CRn 0 /* DBGBCR_EL1_CRm indicates which watchpoint this register is for */ #define DBGBCR_EL1_op2 5 #define DBGBCR_EN 0x1 #define DBGBCR_PMC_SHIFT 1 #define DBGBCR_PMC (0x3 << DBGBCR_PMC_SHIFT) #define DBGBCR_PMC_EL1 (0x1 << DBGBCR_PMC_SHIFT) #define DBGBCR_PMC_EL0 (0x2 << DBGBCR_PMC_SHIFT) #define DBGBCR_BAS_SHIFT 5 #define DBGBCR_BAS (0xf << DBGBCR_BAS_SHIFT) #define DBGBCR_HMC_SHIFT 13 #define DBGBCR_HMC (0x1 << DBGBCR_HMC_SHIFT) #define DBGBCR_SSC_SHIFT 14 #define DBGBCR_SSC (0x3 << DBGBCR_SSC_SHIFT) #define DBGBCR_LBN_SHIFT 16 #define DBGBCR_LBN (0xf << DBGBCR_LBN_SHIFT) #define DBGBCR_BT_SHIFT 20 #define DBGBCR_BT (0xf << DBGBCR_BT_SHIFT) /* DBGBVR_EL1 - Debug Breakpoint Value Registers */ #define DBGBVR_EL1_op0 2 #define DBGBVR_EL1_op1 0 #define DBGBVR_EL1_CRn 0 /* DBGBVR_EL1_CRm indicates which watchpoint this register is for */ #define DBGBVR_EL1_op2 4 /* DBGWCR_EL1 - Debug Watchpoint Control Registers */ #define DBGWCR_EL1_op0 2 #define DBGWCR_EL1_op1 0 #define DBGWCR_EL1_CRn 0 /* DBGWCR_EL1_CRm indicates which watchpoint this register is for */ #define DBGWCR_EL1_op2 7 #define DBGWCR_EN 0x1 #define DBGWCR_PAC_SHIFT 1 #define DBGWCR_PAC (0x3 << DBGWCR_PAC_SHIFT) #define DBGWCR_PAC_EL1 (0x1 << DBGWCR_PAC_SHIFT) #define DBGWCR_PAC_EL0 (0x2 << DBGWCR_PAC_SHIFT) #define DBGWCR_LSC_SHIFT 3 #define DBGWCR_LSC (0x3 << DBGWCR_LSC_SHIFT) #define DBGWCR_BAS_SHIFT 5 #define DBGWCR_BAS (0xff << DBGWCR_BAS_SHIFT) #define DBGWCR_HMC_SHIFT 13 #define DBGWCR_HMC (0x1 << DBGWCR_HMC_SHIFT) #define DBGWCR_SSC_SHIFT 14 #define DBGWCR_SSC (0x3 << DBGWCR_SSC_SHIFT) #define DBGWCR_LBN_SHIFT 16 #define DBGWCR_LBN (0xf << DBGWCR_LBN_SHIFT) #define DBGWCR_WT_SHIFT 20 #define DBGWCR_WT (0x1 << DBGWCR_WT_SHIFT) #define DBGWCR_MASK_SHIFT 24 #define DBGWCR_MASK (0x1f << DBGWCR_MASK_SHIFT) /* DBGWVR_EL1 - Debug Watchpoint Value Registers */ #define DBGWVR_EL1_op0 2 #define DBGWVR_EL1_op1 0 #define DBGWVR_EL1_CRn 0 /* DBGWVR_EL1_CRm indicates which watchpoint this register is for */ #define DBGWVR_EL1_op2 6 /* DCZID_EL0 - Data Cache Zero ID register */ #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ #define DCZID_BS_SHIFT 0 #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) /* DBGAUTHSTATUS_EL1 */ #define DBGAUTHSTATUS_EL1 MRS_REG(DBGAUTHSTATUS_EL1) #define DBGAUTHSTATUS_EL1_op0 2 #define DBGAUTHSTATUS_EL1_op1 0 #define DBGAUTHSTATUS_EL1_CRn 7 #define DBGAUTHSTATUS_EL1_CRm 14 #define DBGAUTHSTATUS_EL1_op2 6 /* DBGCLAIMCLR_EL1 */ #define DBGCLAIMCLR_EL1 MRS_REG(DBGCLAIMCLR_EL1) #define DBGCLAIMCLR_EL1_op0 2 #define DBGCLAIMCLR_EL1_op1 0 #define DBGCLAIMCLR_EL1_CRn 7 #define DBGCLAIMCLR_EL1_CRm 9 #define DBGCLAIMCLR_EL1_op2 6 /* DBGCLAIMSET_EL1 */ #define DBGCLAIMSET_EL1 MRS_REG(DBGCLAIMSET_EL1) #define DBGCLAIMSET_EL1_op0 2 #define DBGCLAIMSET_EL1_op1 0 #define DBGCLAIMSET_EL1_CRn 7 #define DBGCLAIMSET_EL1_CRm 8 #define DBGCLAIMSET_EL1_op2 6 /* DBGPRCR_EL1 */ #define DBGPRCR_EL1 MRS_REG(DBGPRCR_EL1) #define DBGPRCR_EL1_op0 2 #define DBGPRCR_EL1_op1 0 #define DBGPRCR_EL1_CRn 1 #define DBGPRCR_EL1_CRm 4 #define DBGPRCR_EL1_op2 4 /* ESR_ELx */ #define ESR_ELx_ISS_MASK 0x01ffffff #define ISS_FP_TFV_SHIFT 23 #define ISS_FP_TFV (0x01 << ISS_FP_TFV_SHIFT) #define ISS_FP_IOF 0x01 #define ISS_FP_DZF 0x02 #define ISS_FP_OFF 0x04 #define ISS_FP_UFF 0x08 #define ISS_FP_IXF 0x10 #define ISS_FP_IDF 0x80 #define ISS_INSN_FnV (0x01 << 10) #define ISS_INSN_EA (0x01 << 9) #define ISS_INSN_S1PTW (0x01 << 7) #define ISS_INSN_IFSC_MASK (0x1f << 0) #define ISS_MSR_DIR_SHIFT 0 #define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT) #define ISS_MSR_Rt_SHIFT 5 #define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT) #define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) #define ISS_MSR_CRm_SHIFT 1 #define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT) #define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) #define ISS_MSR_CRn_SHIFT 10 #define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT) #define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) #define ISS_MSR_OP1_SHIFT 14 #define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT) #define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) #define ISS_MSR_OP2_SHIFT 17 #define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT) #define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) #define ISS_MSR_OP0_SHIFT 20 #define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT) #define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) #define ISS_MSR_REG_MASK \ (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK | \ ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK) #define ISS_DATA_ISV_SHIFT 24 #define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT) #define ISS_DATA_SAS_SHIFT 22 #define ISS_DATA_SAS_MASK (0x03 << ISS_DATA_SAS_SHIFT) #define ISS_DATA_SSE_SHIFT 21 #define ISS_DATA_SSE (0x01 << ISS_DATA_SSE_SHIFT) #define ISS_DATA_SRT_SHIFT 16 #define ISS_DATA_SRT_MASK (0x1f << ISS_DATA_SRT_SHIFT) #define ISS_DATA_SF (0x01 << 15) #define ISS_DATA_AR (0x01 << 14) #define ISS_DATA_FnV (0x01 << 10) #define ISS_DATA_EA (0x01 << 9) #define ISS_DATA_CM (0x01 << 8) #define ISS_DATA_S1PTW (0x01 << 7) #define ISS_DATA_WnR_SHIFT 6 #define ISS_DATA_WnR (0x01 << ISS_DATA_WnR_SHIFT) #define ISS_DATA_DFSC_MASK (0x3f << 0) #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) #define ISS_DATA_DFSC_TF_L0 (0x04 << 0) #define ISS_DATA_DFSC_TF_L1 (0x05 << 0) #define ISS_DATA_DFSC_TF_L2 (0x06 << 0) #define ISS_DATA_DFSC_TF_L3 (0x07 << 0) #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) #define ISS_DATA_DFSC_PF_L1 (0x0d << 0) #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) #define ISS_DATA_DFSC_EXT (0x10 << 0) #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) #define ISS_DATA_DFSC_ECC (0x18 << 0) #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) #define ISS_DATA_DFSC_ALIGN (0x21 << 0) #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) #define ESR_ELx_IL (0x01 << 25) #define ESR_ELx_EC_SHIFT 26 #define ESR_ELx_EC_MASK (0x3f << 26) #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ #define EXCP_TRAP_WFI_WFE 0x01 /* Trapped WFI or WFE */ #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ #define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ #define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ #define EXCP_HVC 0x16 /* HVC trap */ #define EXCP_MSR 0x18 /* MSR/MRS trap */ #define EXCP_SVE 0x19 /* SVE trap */ #define EXCP_FPAC 0x1c /* Faulting PAC trap */ #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ #define EXCP_SERROR 0x2f /* SError interrupt */ #define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */ #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ #define EXCP_WATCHPT_EL0 0x34 /* Watchpoint, from lower EL */ #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ #define EXCP_BRKPT_32 0x38 /* 32bits breakpoint */ #define EXCP_BRK 0x3c /* Breakpoint */ /* ICC_CTLR_EL1 */ #define ICC_CTLR_EL1_EOIMODE (1U << 1) /* ICC_IAR1_EL1 */ #define ICC_IAR1_EL1_SPUR (0x03ff) /* ICC_IGRPEN0_EL1 */ #define ICC_IGRPEN0_EL1_EN (1U << 0) /* ICC_PMR_EL1 */ #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) /* ICC_SGI1R_EL1 */ #define ICC_SGI1R_EL1 MRS_REG(ICC_SGI1R_EL1) #define ICC_SGI1R_EL1_op0 3 #define ICC_SGI1R_EL1_op1 0 #define ICC_SGI1R_EL1_CRn 12 #define ICC_SGI1R_EL1_CRm 11 #define ICC_SGI1R_EL1_op2 5 #define ICC_SGI1R_EL1_TL_SHIFT 0 #define ICC_SGI1R_EL1_TL_MASK (0xffffUL << ICC_SGI1R_EL1_TL_SHIFT) #define ICC_SGI1R_EL1_TL_VAL(x) ((x) & ICC_SGI1R_EL1_TL_MASK) #define ICC_SGI1R_EL1_AFF1_SHIFT 16 #define ICC_SGI1R_EL1_AFF1_MASK (0xfful << ICC_SGI1R_EL1_AFF1_SHIFT) #define ICC_SGI1R_EL1_AFF1_VAL(x) ((x) & ICC_SGI1R_EL1_AFF1_MASK) #define ICC_SGI1R_EL1_SGIID_SHIFT 24 #define ICC_SGI1R_EL1_SGIID_MASK (0xfUL << ICC_SGI1R_EL1_SGIID_SHIFT) #define ICC_SGI1R_EL1_SGIID_VAL(x) ((x) & ICC_SGI1R_EL1_SGIID_MASK) #define ICC_SGI1R_EL1_AFF2_SHIFT 32 #define ICC_SGI1R_EL1_AFF2_MASK (0xfful << ICC_SGI1R_EL1_AFF2_SHIFT) #define ICC_SGI1R_EL1_AFF2_VAL(x) ((x) & ICC_SGI1R_EL1_AFF2_MASK) #define ICC_SGI1R_EL1_RS_SHIFT 44 #define ICC_SGI1R_EL1_RS_MASK (0xful << ICC_SGI1R_EL1_RS_SHIFT) #define ICC_SGI1R_EL1_RS_VAL(x) ((x) & ICC_SGI1R_EL1_RS_MASK) #define ICC_SGI1R_EL1_AFF3_SHIFT 48 #define ICC_SGI1R_EL1_AFF3_MASK (0xfful << ICC_SGI1R_EL1_AFF3_SHIFT) #define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK) #define ICC_SGI1R_EL1_IRM (0x1UL << 40) /* ICC_SRE_EL1 */ #define ICC_SRE_EL1_SRE (1U << 0) /* ID_AA64AFR0_EL1 */ #define ID_AA64AFR0_EL1 MRS_REG(ID_AA64AFR0_EL1) #define ID_AA64AFR0_EL1_op0 3 #define ID_AA64AFR0_EL1_op1 0 #define ID_AA64AFR0_EL1_CRn 0 #define ID_AA64AFR0_EL1_CRm 5 #define ID_AA64AFR0_EL1_op2 4 /* ID_AA64AFR1_EL1 */ #define ID_AA64AFR1_EL1 MRS_REG(ID_AA64AFR1_EL1) #define ID_AA64AFR1_EL1_op0 3 #define ID_AA64AFR1_EL1_op1 0 #define ID_AA64AFR1_EL1_CRn 0 #define ID_AA64AFR1_EL1_CRm 5 #define ID_AA64AFR1_EL1_op2 5 /* ID_AA64DFR0_EL1 */ #define ID_AA64DFR0_EL1 MRS_REG(ID_AA64DFR0_EL1) #define ID_AA64DFR0_EL1_op0 0x3 #define ID_AA64DFR0_EL1_op1 0x0 #define ID_AA64DFR0_EL1_CRn 0x0 #define ID_AA64DFR0_EL1_CRm 0x5 #define ID_AA64DFR0_EL1_op2 0x0 #define ID_AA64DFR0_DebugVer_SHIFT 0 #define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT) #define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK) #define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT) #define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT) #define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT) #define ID_AA64DFR0_DebugVer_8_4 (UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT) #define ID_AA64DFR0_TraceVer_SHIFT 4 #define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT) #define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK) #define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT) #define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT) #define ID_AA64DFR0_PMUVer_SHIFT 8 #define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) #define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK) #define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT) #define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT) #define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT) #define ID_AA64DFR0_PMUVer_3_4 (UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT) #define ID_AA64DFR0_PMUVer_3_5 (UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT) #define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) #define ID_AA64DFR0_BRPs_SHIFT 12 #define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT) #define ID_AA64DFR0_BRPs_VAL(x) \ ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1) #define ID_AA64DFR0_WRPs_SHIFT 20 #define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT) #define ID_AA64DFR0_WRPs_VAL(x) \ ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1) #define ID_AA64DFR0_CTX_CMPs_SHIFT 28 #define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT) #define ID_AA64DFR0_CTX_CMPs_VAL(x) \ ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1) #define ID_AA64DFR0_PMSVer_SHIFT 32 #define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT) #define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK) #define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT) #define ID_AA64DFR0_PMSVer_SPE (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT) #define ID_AA64DFR0_PMSVer_SPE_8_3 (UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT) #define ID_AA64DFR0_DoubleLock_SHIFT 36 #define ID_AA64DFR0_DoubleLock_MASK (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) #define ID_AA64DFR0_DoubleLock_VAL(x) ((x) & ID_AA64DFR0_DoubleLock_MASK) #define ID_AA64DFR0_DoubleLock_IMPL (UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT) #define ID_AA64DFR0_DoubleLock_NONE (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) #define ID_AA64DFR0_TraceFilt_SHIFT 40 #define ID_AA64DFR0_TraceFilt_MASK (UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT) #define ID_AA64DFR0_TraceFilt_VAL(x) ((x) & ID_AA64DFR0_TraceFilt_MASK) #define ID_AA64DFR0_TraceFilt_NONE (UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT) #define ID_AA64DFR0_TraceFilt_8_4 (UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT) /* ID_AA64DFR1_EL1 */ #define ID_AA64DFR1_EL1 MRS_REG(ID_AA64DFR1_EL1) #define ID_AA64DFR1_EL1_op0 3 #define ID_AA64DFR1_EL1_op1 0 #define ID_AA64DFR1_EL1_CRn 0 #define ID_AA64DFR1_EL1_CRm 5 #define ID_AA64DFR1_EL1_op2 1 /* ID_AA64ISAR0_EL1 */ #define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1) #define ID_AA64ISAR0_EL1_op0 0x3 #define ID_AA64ISAR0_EL1_op1 0x0 #define ID_AA64ISAR0_EL1_CRn 0x0 #define ID_AA64ISAR0_EL1_CRm 0x6 #define ID_AA64ISAR0_EL1_op2 0x0 #define ID_AA64ISAR0_AES_SHIFT 4 #define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT) #define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK) #define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT) #define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT) #define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT) #define ID_AA64ISAR0_SHA1_SHIFT 8 #define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT) #define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK) #define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT) #define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT) #define ID_AA64ISAR0_SHA2_SHIFT 12 #define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT) #define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK) #define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT) #define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT) #define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT) #define ID_AA64ISAR0_CRC32_SHIFT 16 #define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT) #define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK) #define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT) #define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT) #define ID_AA64ISAR0_Atomic_SHIFT 20 #define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT) #define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK) #define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT) #define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT) #define ID_AA64ISAR0_RDM_SHIFT 28 #define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT) #define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK) #define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT) #define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT) #define ID_AA64ISAR0_SHA3_SHIFT 32 #define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT) #define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK) #define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT) #define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT) #define ID_AA64ISAR0_SM3_SHIFT 36 #define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT) #define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK) #define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT) #define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT) #define ID_AA64ISAR0_SM4_SHIFT 40 #define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT) #define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK) #define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT) #define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT) #define ID_AA64ISAR0_DP_SHIFT 44 #define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT) #define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK) #define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT) #define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT) #define ID_AA64ISAR0_FHM_SHIFT 48 #define ID_AA64ISAR0_FHM_MASK (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT) #define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK) #define ID_AA64ISAR0_FHM_NONE (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT) #define ID_AA64ISAR0_FHM_IMPL (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT) #define ID_AA64ISAR0_TS_SHIFT 52 #define ID_AA64ISAR0_TS_MASK (UL(0xf) << ID_AA64ISAR0_TS_SHIFT) #define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK) #define ID_AA64ISAR0_TS_NONE (UL(0x0) << ID_AA64ISAR0_TS_SHIFT) #define ID_AA64ISAR0_TS_CondM_8_4 (UL(0x1) << ID_AA64ISAR0_TS_SHIFT) #define ID_AA64ISAR0_TS_CondM_8_5 (UL(0x2) << ID_AA64ISAR0_TS_SHIFT) #define ID_AA64ISAR0_TLB_SHIFT 56 #define ID_AA64ISAR0_TLB_MASK (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT) #define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK) #define ID_AA64ISAR0_TLB_NONE (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT) #define ID_AA64ISAR0_TLB_TLBIOS (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT) #define ID_AA64ISAR0_TLB_TLBIOSR (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT) #define ID_AA64ISAR0_RNDR_SHIFT 60 #define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT) #define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK) #define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT) #define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT) /* ID_AA64ISAR1_EL1 */ #define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1) #define ID_AA64ISAR1_EL1_op0 0x3 #define ID_AA64ISAR1_EL1_op1 0x0 #define ID_AA64ISAR1_EL1_CRn 0x0 #define ID_AA64ISAR1_EL1_CRm 0x6 #define ID_AA64ISAR1_EL1_op2 0x1 #define ID_AA64ISAR1_DPB_SHIFT 0 #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) #define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT) #define ID_AA64ISAR1_DPB_DCCVAP (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT) #define ID_AA64ISAR1_DPB_DCCVADP (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT) #define ID_AA64ISAR1_APA_SHIFT 4 #define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT) #define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK) #define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT) #define ID_AA64ISAR1_APA_PAC (UL(0x1) << ID_AA64ISAR1_APA_SHIFT) #define ID_AA64ISAR1_APA_EPAC (UL(0x2) << ID_AA64ISAR1_APA_SHIFT) #define ID_AA64ISAR1_APA_EPAC2 (UL(0x3) << ID_AA64ISAR1_APA_SHIFT) #define ID_AA64ISAR1_APA_FPAC (UL(0x4) << ID_AA64ISAR1_APA_SHIFT) #define ID_AA64ISAR1_APA_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_APA_SHIFT) #define ID_AA64ISAR1_API_SHIFT 8 #define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT) #define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK) #define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT) #define ID_AA64ISAR1_API_PAC (UL(0x1) << ID_AA64ISAR1_API_SHIFT) #define ID_AA64ISAR1_API_EPAC (UL(0x2) << ID_AA64ISAR1_API_SHIFT) #define ID_AA64ISAR1_API_EPAC2 (UL(0x3) << ID_AA64ISAR1_API_SHIFT) #define ID_AA64ISAR1_API_FPAC (UL(0x4) << ID_AA64ISAR1_API_SHIFT) #define ID_AA64ISAR1_API_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_API_SHIFT) #define ID_AA64ISAR1_JSCVT_SHIFT 12 #define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT) #define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) #define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT) #define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT) #define ID_AA64ISAR1_FCMA_SHIFT 16 #define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT) #define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK) #define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT) #define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT) #define ID_AA64ISAR1_LRCPC_SHIFT 20 #define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT) #define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) #define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT) #define ID_AA64ISAR1_LRCPC_RCPC_8_3 (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT) #define ID_AA64ISAR1_LRCPC_RCPC_8_4 (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT) #define ID_AA64ISAR1_GPA_SHIFT 24 #define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT) #define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK) #define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT) #define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT) #define ID_AA64ISAR1_GPI_SHIFT 28 #define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT) #define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK) #define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT) #define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT) #define ID_AA64ISAR1_FRINTTS_SHIFT 32 #define ID_AA64ISAR1_FRINTTS_MASK (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT) #define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) #define ID_AA64ISAR1_FRINTTS_NONE (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT) #define ID_AA64ISAR1_FRINTTS_IMPL (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT) #define ID_AA64ISAR1_SB_SHIFT 36 #define ID_AA64ISAR1_SB_MASK (UL(0xf) << ID_AA64ISAR1_SB_SHIFT) #define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK) #define ID_AA64ISAR1_SB_NONE (UL(0x0) << ID_AA64ISAR1_SB_SHIFT) #define ID_AA64ISAR1_SB_IMPL (UL(0x1) << ID_AA64ISAR1_SB_SHIFT) #define ID_AA64ISAR1_SPECRES_SHIFT 40 #define ID_AA64ISAR1_SPECRES_MASK (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT) #define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) #define ID_AA64ISAR1_SPECRES_NONE (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT) #define ID_AA64ISAR1_SPECRES_IMPL (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT) #define ID_AA64ISAR1_BF16_SHIFT 44 #define ID_AA64ISAR1_BF16_MASK (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT) #define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) #define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT) #define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT) #define ID_AA64ISAR1_DGH_SHIFT 48 #define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT) #define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) #define ID_AA64ISAR1_DGH_NONE (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT) #define ID_AA64ISAR1_DGH_IMPL (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT) #define ID_AA64ISAR1_I8MM_SHIFT 52 #define ID_AA64ISAR1_I8MM_MASK (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT) #define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) #define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT) #define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT) /* ID_AA64ISAR2_EL1 */ #define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1) #define ID_AA64ISAR2_EL1_op0 3 #define ID_AA64ISAR2_EL1_op1 0 #define ID_AA64ISAR2_EL1_CRn 0 #define ID_AA64ISAR2_EL1_CRm 6 #define ID_AA64ISAR2_EL1_op2 2 #define ID_AA64ISAR2_WFxT_SHIFT 0 #define ID_AA64ISAR2_WFxT_MASK (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT) #define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK) #define ID_AA64ISAR2_WFxT_NONE (UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT) #define ID_AA64ISAR2_WFxT_IMPL (UL(0x1) << ID_AA64ISAR2_WFxT_SHIFT) #define ID_AA64ISAR2_RPRES_SHIFT 4 #define ID_AA64ISAR2_RPRES_MASK (UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT) #define ID_AA64ISAR2_RPRES_VAL(x) ((x) & ID_AA64ISAR2_RPRES_MASK) #define ID_AA64ISAR2_RPRES_NONE (UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT) #define ID_AA64ISAR2_RPRES_IMPL (UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT) #define ID_AA64ISAR2_GPA3_SHIFT 8 #define ID_AA64ISAR2_GPA3_MASK (UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT) #define ID_AA64ISAR2_GPA3_VAL(x) ((x) & ID_AA64ISAR2_GPA3_MASK) #define ID_AA64ISAR2_GPA3_NONE (UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT) #define ID_AA64ISAR2_GPA3_IMPL (UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT) #define ID_AA64ISAR2_APA3_SHIFT 12 #define ID_AA64ISAR2_APA3_MASK (UL(0xf) << ID_AA64ISAR2_APA3_SHIFT) #define ID_AA64ISAR2_APA3_VAL(x) ((x) & ID_AA64ISAR2_APA3_MASK) #define ID_AA64ISAR2_APA3_NONE (UL(0x0) << ID_AA64ISAR2_APA3_SHIFT) #define ID_AA64ISAR2_APA3_PAC (UL(0x1) << ID_AA64ISAR2_APA3_SHIFT) #define ID_AA64ISAR2_APA3_EPAC (UL(0x2) << ID_AA64ISAR2_APA3_SHIFT) #define ID_AA64ISAR2_APA3_EPAC2 (UL(0x3) << ID_AA64ISAR2_APA3_SHIFT) #define ID_AA64ISAR2_APA3_FPAC (UL(0x4) << ID_AA64ISAR2_APA3_SHIFT) #define ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT) #define ID_AA64ISAR2_MOPS_SHIFT 16 #define ID_AA64ISAR2_MOPS_MASK (UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT) #define ID_AA64ISAR2_MOPS_VAL(x) ((x) & ID_AA64ISAR2_MOPS_MASK) #define ID_AA64ISAR2_MOPS_NONE (UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT) #define ID_AA64ISAR2_MOPS_IMPL (UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT) #define ID_AA64ISAR2_BC_SHIFT 20 #define ID_AA64ISAR2_BC_MASK (UL(0xf) << ID_AA64ISAR2_BC_SHIFT) #define ID_AA64ISAR2_BC_VAL(x) ((x) & ID_AA64ISAR2_BC_MASK) #define ID_AA64ISAR2_BC_NONE (UL(0x0) << ID_AA64ISAR2_BC_SHIFT) #define ID_AA64ISAR2_BC_IMPL (UL(0x1) << ID_AA64ISAR2_BC_SHIFT) #define ID_AA64ISAR2_PAC_frac_SHIFT 28 #define ID_AA64ISAR2_PAC_frac_MASK (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT) #define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK) #define ID_AA64ISAR2_PAC_frac_NONE (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT) #define ID_AA64ISAR2_PAC_frac_IMPL (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT) /* ID_AA64MMFR0_EL1 */ #define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1) #define ID_AA64MMFR0_EL1_op0 0x3 #define ID_AA64MMFR0_EL1_op1 0x0 #define ID_AA64MMFR0_EL1_CRn 0x0 #define ID_AA64MMFR0_EL1_CRm 0x7 #define ID_AA64MMFR0_EL1_op2 0x0 #define ID_AA64MMFR0_PARange_SHIFT 0 #define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) #define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) #define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT) #define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT) #define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT) #define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT) #define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT) #define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT) #define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT) #define ID_AA64MMFR0_ASIDBits_SHIFT 4 #define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT) #define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) #define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT) #define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT) #define ID_AA64MMFR0_BigEnd_SHIFT 8 #define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT) #define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) #define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT) #define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT) #define ID_AA64MMFR0_SNSMem_SHIFT 12 #define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT) #define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) #define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT) #define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT) #define ID_AA64MMFR0_BigEndEL0_SHIFT 16 #define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT) #define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) #define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT) #define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT) #define ID_AA64MMFR0_TGran16_SHIFT 20 #define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT) #define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) #define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT) #define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT) #define ID_AA64MMFR0_TGran64_SHIFT 24 #define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) #define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) #define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT) #define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) #define ID_AA64MMFR0_TGran4_SHIFT 28 #define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) #define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) #define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT) #define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) #define ID_AA64MMFR0_TGran16_2_SHIFT 32 #define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT) #define ID_AA64MMFR0_TGran16_2_VAL(x) ((x) & ID_AA64MMFR0_TGran16_2_MASK) #define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT) #define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT) #define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT) #define ID_AA64MMFR0_TGran64_2_SHIFT 36 #define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT) #define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK) #define ID_AA64MMFR0_TGran64_2_TGran64 (UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT) #define ID_AA64MMFR0_TGran64_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT) #define ID_AA64MMFR0_TGran64_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT) #define ID_AA64MMFR0_TGran4_2_SHIFT 40 #define ID_AA64MMFR0_TGran4_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT) #define ID_AA64MMFR0_TGran4_2_VAL(x) ((x) & ID_AA64MMFR0_TGran4_2_MASK) #define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT) #define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT) #define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT) #define ID_AA64MMFR0_ExS_SHIFT 44 #define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT) #define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK) #define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT) #define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT) /* ID_AA64MMFR1_EL1 */ #define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1) #define ID_AA64MMFR1_EL1_op0 0x3 #define ID_AA64MMFR1_EL1_op1 0x0 #define ID_AA64MMFR1_EL1_CRn 0x0 #define ID_AA64MMFR1_EL1_CRm 0x7 #define ID_AA64MMFR1_EL1_op2 0x1 #define ID_AA64MMFR1_HAFDBS_SHIFT 0 #define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) #define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) #define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT) #define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT) #define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT) #define ID_AA64MMFR1_VMIDBits_SHIFT 4 #define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT) #define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) #define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT) #define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT) #define ID_AA64MMFR1_VH_SHIFT 8 #define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT) #define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK) #define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT) #define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT) #define ID_AA64MMFR1_HPDS_SHIFT 12 #define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT) #define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK) #define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT) #define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT) #define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT) #define ID_AA64MMFR1_LO_SHIFT 16 #define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT) #define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK) #define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT) #define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT) #define ID_AA64MMFR1_PAN_SHIFT 20 #define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT) #define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK) #define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT) #define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT) #define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) #define ID_AA64MMFR1_SpecSEI_SHIFT 24 #define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT) #define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) #define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT) #define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT) #define ID_AA64MMFR1_XNX_SHIFT 28 #define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT) #define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK) #define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT) #define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT) /* ID_AA64MMFR2_EL1 */ #define ID_AA64MMFR2_EL1 MRS_REG(ID_AA64MMFR2_EL1) #define ID_AA64MMFR2_EL1_op0 0x3 #define ID_AA64MMFR2_EL1_op1 0x0 #define ID_AA64MMFR2_EL1_CRn 0x0 #define ID_AA64MMFR2_EL1_CRm 0x7 #define ID_AA64MMFR2_EL1_op2 0x2 #define ID_AA64MMFR2_CnP_SHIFT 0 #define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT) #define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK) #define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT) #define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT) #define ID_AA64MMFR2_UAO_SHIFT 4 #define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT) #define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK) #define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT) #define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT) #define ID_AA64MMFR2_LSM_SHIFT 8 #define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT) #define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK) #define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT) #define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT) #define ID_AA64MMFR2_IESB_SHIFT 12 #define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT) #define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK) #define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT) #define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT) #define ID_AA64MMFR2_VARange_SHIFT 16 #define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT) #define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK) #define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT) #define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT) #define ID_AA64MMFR2_CCIDX_SHIFT 20 #define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT) #define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) #define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT) #define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT) #define ID_AA64MMFR2_NV_SHIFT 24 #define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT) #define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK) #define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT) #define ID_AA64MMFR2_NV_8_3 (UL(0x1) << ID_AA64MMFR2_NV_SHIFT) #define ID_AA64MMFR2_NV_8_4 (UL(0x2) << ID_AA64MMFR2_NV_SHIFT) #define ID_AA64MMFR2_ST_SHIFT 28 #define ID_AA64MMFR2_ST_MASK (UL(0xf) << ID_AA64MMFR2_ST_SHIFT) #define ID_AA64MMFR2_ST_VAL(x) ((x) & ID_AA64MMFR2_ST_MASK) #define ID_AA64MMFR2_ST_NONE (UL(0x0) << ID_AA64MMFR2_ST_SHIFT) #define ID_AA64MMFR2_ST_IMPL (UL(0x1) << ID_AA64MMFR2_ST_SHIFT) #define ID_AA64MMFR2_AT_SHIFT 32 #define ID_AA64MMFR2_AT_MASK (UL(0xf) << ID_AA64MMFR2_AT_SHIFT) #define ID_AA64MMFR2_AT_VAL(x) ((x) & ID_AA64MMFR2_AT_MASK) #define ID_AA64MMFR2_AT_NONE (UL(0x0) << ID_AA64MMFR2_AT_SHIFT) #define ID_AA64MMFR2_AT_IMPL (UL(0x1) << ID_AA64MMFR2_AT_SHIFT) #define ID_AA64MMFR2_IDS_SHIFT 36 #define ID_AA64MMFR2_IDS_MASK (UL(0xf) << ID_AA64MMFR2_IDS_SHIFT) #define ID_AA64MMFR2_IDS_VAL(x) ((x) & ID_AA64MMFR2_IDS_MASK) #define ID_AA64MMFR2_IDS_NONE (UL(0x0) << ID_AA64MMFR2_IDS_SHIFT) #define ID_AA64MMFR2_IDS_IMPL (UL(0x1) << ID_AA64MMFR2_IDS_SHIFT) #define ID_AA64MMFR2_FWB_SHIFT 40 #define ID_AA64MMFR2_FWB_MASK (UL(0xf) << ID_AA64MMFR2_FWB_SHIFT) #define ID_AA64MMFR2_FWB_VAL(x) ((x) & ID_AA64MMFR2_FWB_MASK) #define ID_AA64MMFR2_FWB_NONE (UL(0x0) << ID_AA64MMFR2_FWB_SHIFT) #define ID_AA64MMFR2_FWB_IMPL (UL(0x1) << ID_AA64MMFR2_FWB_SHIFT) #define ID_AA64MMFR2_TTL_SHIFT 48 #define ID_AA64MMFR2_TTL_MASK (UL(0xf) << ID_AA64MMFR2_TTL_SHIFT) #define ID_AA64MMFR2_TTL_VAL(x) ((x) & ID_AA64MMFR2_TTL_MASK) #define ID_AA64MMFR2_TTL_NONE (UL(0x0) << ID_AA64MMFR2_TTL_SHIFT) #define ID_AA64MMFR2_TTL_IMPL (UL(0x1) << ID_AA64MMFR2_TTL_SHIFT) #define ID_AA64MMFR2_BBM_SHIFT 52 #define ID_AA64MMFR2_BBM_MASK (UL(0xf) << ID_AA64MMFR2_BBM_SHIFT) #define ID_AA64MMFR2_BBM_VAL(x) ((x) & ID_AA64MMFR2_BBM_MASK) #define ID_AA64MMFR2_BBM_LEVEL0 (UL(0x0) << ID_AA64MMFR2_BBM_SHIFT) #define ID_AA64MMFR2_BBM_LEVEL1 (UL(0x1) << ID_AA64MMFR2_BBM_SHIFT) #define ID_AA64MMFR2_BBM_LEVEL2 (UL(0x2) << ID_AA64MMFR2_BBM_SHIFT) #define ID_AA64MMFR2_EVT_SHIFT 56 #define ID_AA64MMFR2_EVT_MASK (UL(0xf) << ID_AA64MMFR2_EVT_SHIFT) #define ID_AA64MMFR2_EVT_VAL(x) ((x) & ID_AA64MMFR2_EVT_MASK) #define ID_AA64MMFR2_EVT_NONE (UL(0x0) << ID_AA64MMFR2_EVT_SHIFT) #define ID_AA64MMFR2_EVT_8_2 (UL(0x1) << ID_AA64MMFR2_EVT_SHIFT) #define ID_AA64MMFR2_EVT_8_5 (UL(0x2) << ID_AA64MMFR2_EVT_SHIFT) #define ID_AA64MMFR2_E0PD_SHIFT 60 #define ID_AA64MMFR2_E0PD_MASK (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT) #define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK) #define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT) #define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT) /* ID_AA64PFR0_EL1 */ #define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1) #define ID_AA64PFR0_EL1_op0 0x3 #define ID_AA64PFR0_EL1_op1 0x0 #define ID_AA64PFR0_EL1_CRn 0x0 #define ID_AA64PFR0_EL1_CRm 0x4 #define ID_AA64PFR0_EL1_op2 0x0 #define ID_AA64PFR0_EL0_SHIFT 0 #define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT) #define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK) #define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT) #define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT) #define ID_AA64PFR0_EL1_SHIFT 4 #define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT) #define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK) #define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT) #define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT) #define ID_AA64PFR0_EL2_SHIFT 8 #define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT) #define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK) #define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT) #define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT) #define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT) #define ID_AA64PFR0_EL3_SHIFT 12 #define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT) #define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK) #define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT) #define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT) #define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT) #define ID_AA64PFR0_FP_SHIFT 16 #define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT) #define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK) #define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT) #define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT) #define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT) #define ID_AA64PFR0_AdvSIMD_SHIFT 20 #define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) #define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) #define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT) #define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT) #define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ #define ID_AA64PFR0_GIC_SHIFT 24 #define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT) #define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) #define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT) #define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT) #define ID_AA64PFR0_GIC_CPUIF_4_1 (UL(0x3) << ID_AA64PFR0_GIC_SHIFT) #define ID_AA64PFR0_RAS_SHIFT 28 #define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT) #define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK) #define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT) #define ID_AA64PFR0_RAS_IMPL (UL(0x1) << ID_AA64PFR0_RAS_SHIFT) #define ID_AA64PFR0_RAS_8_4 (UL(0x2) << ID_AA64PFR0_RAS_SHIFT) #define ID_AA64PFR0_SVE_SHIFT 32 #define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT) #define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) #define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT) #define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT) #define ID_AA64PFR0_SEL2_SHIFT 36 #define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT) #define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) #define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT) #define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT) #define ID_AA64PFR0_MPAM_SHIFT 40 #define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT) #define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) #define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT) #define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT) #define ID_AA64PFR0_AMU_SHIFT 44 #define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT) #define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) #define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT) #define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT) #define ID_AA64PFR0_DIT_SHIFT 48 #define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT) #define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) #define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT) #define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT) #define ID_AA64PFR0_CSV2_SHIFT 56 #define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT) #define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) #define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT) #define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT) #define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT) #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT) #define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) #define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT) #define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT) /* ID_AA64PFR1_EL1 */ #define ID_AA64PFR1_EL1 MRS_REG(ID_AA64PFR1_EL1) #define ID_AA64PFR1_EL1_op0 0x3 #define ID_AA64PFR1_EL1_op1 0x0 #define ID_AA64PFR1_EL1_CRn 0x0 #define ID_AA64PFR1_EL1_CRm 0x4 #define ID_AA64PFR1_EL1_op2 0x1 #define ID_AA64PFR1_BT_SHIFT 0 #define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT) #define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) #define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT) #define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT) #define ID_AA64PFR1_SSBS_SHIFT 4 #define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT) #define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) #define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT) #define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT) #define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT) #define ID_AA64PFR1_MTE_SHIFT 8 #define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT) #define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) #define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT) #define ID_AA64PFR1_MTE_IMPL_EL0 (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) #define ID_AA64PFR1_MTE_IMPL (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) #define ID_AA64PFR1_RAS_frac_SHIFT 12 #define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) #define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) #define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) #define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) /* ID_AA64ZFR0_EL1 */ #define ID_AA64ZFR0_EL1 MRS_REG(ID_AA64ZFR0_EL1) #define ID_AA64ZFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1) #define ID_AA64ZFR0_EL1_op0 3 #define ID_AA64ZFR0_EL1_op1 0 #define ID_AA64ZFR0_EL1_CRn 0 #define ID_AA64ZFR0_EL1_CRm 4 #define ID_AA64ZFR0_EL1_op2 4 #define ID_AA64ZFR0_SVEver_SHIFT 0 #define ID_AA64ZFR0_SVEver_MASK (UL(0xf) << ID_AA64ZFR0_SVEver_SHIFT) #define ID_AA64ZFR0_SVEver_VAL(x) ((x) & ID_AA64ZFR0_SVEver_MASK #define ID_AA64ZFR0_SVEver_SVE1 (UL(0x0) << ID_AA64ZFR0_SVEver_SHIFT) #define ID_AA64ZFR0_SVEver_SVE2 (UL(0x1) << ID_AA64ZFR0_SVEver_SHIFT) #define ID_AA64ZFR0_AES_SHIFT 4 #define ID_AA64ZFR0_AES_MASK (UL(0xf) << ID_AA64ZFR0_AES_SHIFT) #define ID_AA64ZFR0_AES_VAL(x) ((x) & ID_AA64ZFR0_AES_MASK #define ID_AA64ZFR0_AES_NONE (UL(0x0) << ID_AA64ZFR0_AES_SHIFT) #define ID_AA64ZFR0_AES_BASE (UL(0x1) << ID_AA64ZFR0_AES_SHIFT) #define ID_AA64ZFR0_AES_PMULL (UL(0x2) << ID_AA64ZFR0_AES_SHIFT) #define ID_AA64ZFR0_BitPerm_SHIFT 16 #define ID_AA64ZFR0_BitPerm_MASK (UL(0xf) << ID_AA64ZFR0_BitPerm_SHIFT) #define ID_AA64ZFR0_BitPerm_VAL(x) ((x) & ID_AA64ZFR0_BitPerm_MASK #define ID_AA64ZFR0_BitPerm_NONE (UL(0x0) << ID_AA64ZFR0_BitPerm_SHIFT) #define ID_AA64ZFR0_BitPerm_IMPL (UL(0x1) << ID_AA64ZFR0_BitPerm_SHIFT) #define ID_AA64ZFR0_BF16_SHIFT 20 #define ID_AA64ZFR0_BF16_MASK (UL(0xf) << ID_AA64ZFR0_BF16_SHIFT) #define ID_AA64ZFR0_BF16_VAL(x) ((x) & ID_AA64ZFR0_BF16_MASK #define ID_AA64ZFR0_BF16_NONE (UL(0x0) << ID_AA64ZFR0_BF16_SHIFT) #define ID_AA64ZFR0_BF16_BASE (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) #define ID_AA64ZFR0_BF16_EBF (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) #define ID_AA64ZFR0_SHA3_SHIFT 32 #define ID_AA64ZFR0_SHA3_MASK (UL(0xf) << ID_AA64ZFR0_SHA3_SHIFT) #define ID_AA64ZFR0_SHA3_VAL(x) ((x) & ID_AA64ZFR0_SHA3_MASK #define ID_AA64ZFR0_SHA3_NONE (UL(0x0) << ID_AA64ZFR0_SHA3_SHIFT) #define ID_AA64ZFR0_SHA3_IMPL (UL(0x1) << ID_AA64ZFR0_SHA3_SHIFT) #define ID_AA64ZFR0_SM4_SHIFT 40 #define ID_AA64ZFR0_SM4_MASK (UL(0xf) << ID_AA64ZFR0_SM4_SHIFT) #define ID_AA64ZFR0_SM4_VAL(x) ((x) & ID_AA64ZFR0_SM4_MASK #define ID_AA64ZFR0_SM4_NONE (UL(0x0) << ID_AA64ZFR0_SM4_SHIFT) #define ID_AA64ZFR0_SM4_IMPL (UL(0x1) << ID_AA64ZFR0_SM4_SHIFT) #define ID_AA64ZFR0_I8MM_SHIFT 44 #define ID_AA64ZFR0_I8MM_MASK (UL(0xf) << ID_AA64ZFR0_I8MM_SHIFT) #define ID_AA64ZFR0_I8MM_VAL(x) ((x) & ID_AA64ZFR0_I8MM_MASK #define ID_AA64ZFR0_I8MM_NONE (UL(0x0) << ID_AA64ZFR0_I8MM_SHIFT) #define ID_AA64ZFR0_I8MM_IMPL (UL(0x1) << ID_AA64ZFR0_I8MM_SHIFT) #define ID_AA64ZFR0_F32MM_SHIFT 52 #define ID_AA64ZFR0_F32MM_MASK (UL(0xf) << ID_AA64ZFR0_F32MM_SHIFT) #define ID_AA64ZFR0_F32MM_VAL(x) ((x) & ID_AA64ZFR0_F32MM_MASK #define ID_AA64ZFR0_F32MM_NONE (UL(0x0) << ID_AA64ZFR0_F32MM_SHIFT) #define ID_AA64ZFR0_F32MM_IMPL (UL(0x1) << ID_AA64ZFR0_F32MM_SHIFT) #define ID_AA64ZFR0_F64MM_SHIFT 56 #define ID_AA64ZFR0_F64MM_MASK (UL(0xf) << ID_AA64ZFR0_F64MM_SHIFT) #define ID_AA64ZFR0_F64MM_VAL(x) ((x) & ID_AA64ZFR0_F64MM_MASK #define ID_AA64ZFR0_F64MM_NONE (UL(0x0) << ID_AA64ZFR0_F64MM_SHIFT) #define ID_AA64ZFR0_F64MM_IMPL (UL(0x1) << ID_AA64ZFR0_F64MM_SHIFT) /* ID_ISAR5_EL1 */ #define ID_ISAR5_EL1 MRS_REG(ID_ISAR5_EL1) #define ID_ISAR5_EL1_op0 0x3 #define ID_ISAR5_EL1_op1 0x0 #define ID_ISAR5_EL1_CRn 0x0 #define ID_ISAR5_EL1_CRm 0x2 #define ID_ISAR5_EL1_op2 0x5 #define ID_ISAR5_SEVL_SHIFT 0 #define ID_ISAR5_SEVL_MASK (UL(0xf) << ID_ISAR5_SEVL_SHIFT) #define ID_ISAR5_SEVL_VAL(x) ((x) & ID_ISAR5_SEVL_MASK) #define ID_ISAR5_SEVL_NOP (UL(0x0) << ID_ISAR5_SEVL_SHIFT) #define ID_ISAR5_SEVL_IMPL (UL(0x1) << ID_ISAR5_SEVL_SHIFT) #define ID_ISAR5_AES_SHIFT 4 #define ID_ISAR5_AES_MASK (UL(0xf) << ID_ISAR5_AES_SHIFT) #define ID_ISAR5_AES_VAL(x) ((x) & ID_ISAR5_AES_MASK) #define ID_ISAR5_AES_NONE (UL(0x0) << ID_ISAR5_AES_SHIFT) #define ID_ISAR5_AES_BASE (UL(0x1) << ID_ISAR5_AES_SHIFT) #define ID_ISAR5_AES_VMULL (UL(0x2) << ID_ISAR5_AES_SHIFT) #define ID_ISAR5_SHA1_SHIFT 8 #define ID_ISAR5_SHA1_MASK (UL(0xf) << ID_ISAR5_SHA1_SHIFT) #define ID_ISAR5_SHA1_VAL(x) ((x) & ID_ISAR5_SHA1_MASK) #define ID_ISAR5_SHA1_NONE (UL(0x0) << ID_ISAR5_SHA1_SHIFT) #define ID_ISAR5_SHA1_IMPL (UL(0x1) << ID_ISAR5_SHA1_SHIFT) #define ID_ISAR5_SHA2_SHIFT 12 #define ID_ISAR5_SHA2_MASK (UL(0xf) << ID_ISAR5_SHA2_SHIFT) #define ID_ISAR5_SHA2_VAL(x) ((x) & ID_ISAR5_SHA2_MASK) #define ID_ISAR5_SHA2_NONE (UL(0x0) << ID_ISAR5_SHA2_SHIFT) #define ID_ISAR5_SHA2_IMPL (UL(0x1) << ID_ISAR5_SHA2_SHIFT) #define ID_ISAR5_CRC32_SHIFT 16 #define ID_ISAR5_CRC32_MASK (UL(0xf) << ID_ISAR5_CRC32_SHIFT) #define ID_ISAR5_CRC32_VAL(x) ((x) & ID_ISAR5_CRC32_MASK) #define ID_ISAR5_CRC32_NONE (UL(0x0) << ID_ISAR5_CRC32_SHIFT) #define ID_ISAR5_CRC32_IMPL (UL(0x1) << ID_ISAR5_CRC32_SHIFT) #define ID_ISAR5_RDM_SHIFT 24 #define ID_ISAR5_RDM_MASK (UL(0xf) << ID_ISAR5_RDM_SHIFT) #define ID_ISAR5_RDM_VAL(x) ((x) & ID_ISAR5_RDM_MASK) #define ID_ISAR5_RDM_NONE (UL(0x0) << ID_ISAR5_RDM_SHIFT) #define ID_ISAR5_RDM_IMPL (UL(0x1) << ID_ISAR5_RDM_SHIFT) #define ID_ISAR5_VCMA_SHIFT 28 #define ID_ISAR5_VCMA_MASK (UL(0xf) << ID_ISAR5_VCMA_SHIFT) #define ID_ISAR5_VCMA_VAL(x) ((x) & ID_ISAR5_VCMA_MASK) #define ID_ISAR5_VCMA_NONE (UL(0x0) << ID_ISAR5_VCMA_SHIFT) #define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT) /* MAIR_EL1 - Memory Attribute Indirection Register */ #define MAIR_ATTR_MASK(idx) (UL(0xff) << ((n)* 8)) #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) #define MAIR_DEVICE_nGnRnE UL(0x00) #define MAIR_DEVICE_nGnRE UL(0x04) #define MAIR_NORMAL_NC UL(0x44) #define MAIR_NORMAL_WT UL(0xbb) #define MAIR_NORMAL_WB UL(0xff) /* MDCCINT_EL1 */ #define MDCCINT_EL1 MRS_REG(MDCCINT_EL1) #define MDCCINT_EL1_op0 2 #define MDCCINT_EL1_op1 0 #define MDCCINT_EL1_CRn 0 #define MDCCINT_EL1_CRm 2 #define MDCCINT_EL1_op2 0 /* MDCCSR_EL0 */ #define MDCCSR_EL0 MRS_REG(MDCCSR_EL0) #define MDCCSR_EL0_op0 2 #define MDCCSR_EL0_op1 3 #define MDCCSR_EL0_CRn 0 #define MDCCSR_EL0_CRm 1 #define MDCCSR_EL0_op2 0 /* MDSCR_EL1 - Monitor Debug System Control Register */ #define MDSCR_EL1 MRS_REG(MDSCR_EL1) #define MDSCR_EL1_op0 2 #define MDSCR_EL1_op1 0 #define MDSCR_EL1_CRn 0 #define MDSCR_EL1_CRm 2 #define MDSCR_EL1_op2 2 #define MDSCR_SS_SHIFT 0 #define MDSCR_SS (UL(0x1) << MDSCR_SS_SHIFT) #define MDSCR_KDE_SHIFT 13 #define MDSCR_KDE (UL(0x1) << MDSCR_KDE_SHIFT) #define MDSCR_MDE_SHIFT 15 #define MDSCR_MDE (UL(0x1) << MDSCR_MDE_SHIFT) /* MIDR_EL1 - Main ID Register */ #define MIDR_EL1 MRS_REG(MIDR_EL1) #define MIDR_EL1_op0 3 #define MIDR_EL1_op1 0 #define MIDR_EL1_CRn 0 #define MIDR_EL1_CRm 0 #define MIDR_EL1_op2 0 /* MPIDR_EL1 - Multiprocessor Affinity Register */ #define MPIDR_EL1 MRS_REG(MPIDR_EL1) #define MPIDR_EL1_op0 3 #define MPIDR_EL1_op1 0 #define MPIDR_EL1_CRn 0 #define MPIDR_EL1_CRm 0 #define MPIDR_EL1_op2 5 #define MPIDR_AFF0_SHIFT 0 #define MPIDR_AFF0_MASK (UL(0xff) << MPIDR_AFF0_SHIFT) #define MPIDR_AFF0_VAL(x) ((x) & MPIDR_AFF0_MASK) #define MPIDR_AFF1_SHIFT 8 #define MPIDR_AFF1_MASK (UL(0xff) << MPIDR_AFF1_SHIFT) #define MPIDR_AFF1_VAL(x) ((x) & MPIDR_AFF1_MASK) #define MPIDR_AFF2_SHIFT 16 #define MPIDR_AFF2_MASK (UL(0xff) << MPIDR_AFF2_SHIFT) #define MPIDR_AFF2_VAL(x) ((x) & MPIDR_AFF2_MASK) #define MPIDR_MT_SHIFT 24 #define MPIDR_MT_MASK (UL(0x1) << MPIDR_MT_SHIFT) #define MPIDR_U_SHIFT 30 #define MPIDR_U_MASK (UL(0x1) << MPIDR_U_SHIFT) #define MPIDR_AFF3_SHIFT 32 #define MPIDR_AFF3_MASK (UL(0xff) << MPIDR_AFF3_SHIFT) #define MPIDR_AFF3_VAL(x) ((x) & MPIDR_AFF3_MASK) /* MVFR0_EL1 */ #define MVFR0_EL1 MRS_REG(MVFR0_EL1) #define MVFR0_EL1_op0 0x3 #define MVFR0_EL1_op1 0x0 #define MVFR0_EL1_CRn 0x0 #define MVFR0_EL1_CRm 0x3 #define MVFR0_EL1_op2 0x0 #define MVFR0_SIMDReg_SHIFT 0 #define MVFR0_SIMDReg_MASK (UL(0xf) << MVFR0_SIMDReg_SHIFT) #define MVFR0_SIMDReg_VAL(x) ((x) & MVFR0_SIMDReg_MASK) #define MVFR0_SIMDReg_NONE (UL(0x0) << MVFR0_SIMDReg_SHIFT) #define MVFR0_SIMDReg_FP (UL(0x1) << MVFR0_SIMDReg_SHIFT) #define MVFR0_SIMDReg_AdvSIMD (UL(0x2) << MVFR0_SIMDReg_SHIFT) #define MVFR0_FPSP_SHIFT 4 #define MVFR0_FPSP_MASK (UL(0xf) << MVFR0_FPSP_SHIFT) #define MVFR0_FPSP_VAL(x) ((x) & MVFR0_FPSP_MASK) #define MVFR0_FPSP_NONE (UL(0x0) << MVFR0_FPSP_SHIFT) #define MVFR0_FPSP_VFP_v2 (UL(0x1) << MVFR0_FPSP_SHIFT) #define MVFR0_FPSP_VFP_v3_v4 (UL(0x2) << MVFR0_FPSP_SHIFT) #define MVFR0_FPDP_SHIFT 8 #define MVFR0_FPDP_MASK (UL(0xf) << MVFR0_FPDP_SHIFT) #define MVFR0_FPDP_VAL(x) ((x) & MVFR0_FPDP_MASK) #define MVFR0_FPDP_NONE (UL(0x0) << MVFR0_FPDP_SHIFT) #define MVFR0_FPDP_VFP_v2 (UL(0x1) << MVFR0_FPDP_SHIFT) #define MVFR0_FPDP_VFP_v3_v4 (UL(0x2) << MVFR0_FPDP_SHIFT) #define MVFR0_FPTrap_SHIFT 12 #define MVFR0_FPTrap_MASK (UL(0xf) << MVFR0_FPTrap_SHIFT) #define MVFR0_FPTrap_VAL(x) ((x) & MVFR0_FPTrap_MASK) #define MVFR0_FPTrap_NONE (UL(0x0) << MVFR0_FPTrap_SHIFT) #define MVFR0_FPTrap_IMPL (UL(0x1) << MVFR0_FPTrap_SHIFT) #define MVFR0_FPDivide_SHIFT 16 #define MVFR0_FPDivide_MASK (UL(0xf) << MVFR0_FPDivide_SHIFT) #define MVFR0_FPDivide_VAL(x) ((x) & MVFR0_FPDivide_MASK) #define MVFR0_FPDivide_NONE (UL(0x0) << MVFR0_FPDivide_SHIFT) #define MVFR0_FPDivide_IMPL (UL(0x1) << MVFR0_FPDivide_SHIFT) #define MVFR0_FPSqrt_SHIFT 20 #define MVFR0_FPSqrt_MASK (UL(0xf) << MVFR0_FPSqrt_SHIFT) #define MVFR0_FPSqrt_VAL(x) ((x) & MVFR0_FPSqrt_MASK) #define MVFR0_FPSqrt_NONE (UL(0x0) << MVFR0_FPSqrt_SHIFT) #define MVFR0_FPSqrt_IMPL (UL(0x1) << MVFR0_FPSqrt_SHIFT) #define MVFR0_FPShVec_SHIFT 24 #define MVFR0_FPShVec_MASK (UL(0xf) << MVFR0_FPShVec_SHIFT) #define MVFR0_FPShVec_VAL(x) ((x) & MVFR0_FPShVec_MASK) #define MVFR0_FPShVec_NONE (UL(0x0) << MVFR0_FPShVec_SHIFT) #define MVFR0_FPShVec_IMPL (UL(0x1) << MVFR0_FPShVec_SHIFT) #define MVFR0_FPRound_SHIFT 28 #define MVFR0_FPRound_MASK (UL(0xf) << MVFR0_FPRound_SHIFT) #define MVFR0_FPRound_VAL(x) ((x) & MVFR0_FPRound_MASK) #define MVFR0_FPRound_NONE (UL(0x0) << MVFR0_FPRound_SHIFT) #define MVFR0_FPRound_IMPL (UL(0x1) << MVFR0_FPRound_SHIFT) /* MVFR1_EL1 */ #define MVFR1_EL1 MRS_REG(MVFR1_EL1) #define MVFR1_EL1_op0 0x3 #define MVFR1_EL1_op1 0x0 #define MVFR1_EL1_CRn 0x0 #define MVFR1_EL1_CRm 0x3 #define MVFR1_EL1_op2 0x1 #define MVFR1_FPFtZ_SHIFT 0 #define MVFR1_FPFtZ_MASK (UL(0xf) << MVFR1_FPFtZ_SHIFT) #define MVFR1_FPFtZ_VAL(x) ((x) & MVFR1_FPFtZ_MASK) #define MVFR1_FPFtZ_NONE (UL(0x0) << MVFR1_FPFtZ_SHIFT) #define MVFR1_FPFtZ_IMPL (UL(0x1) << MVFR1_FPFtZ_SHIFT) #define MVFR1_FPDNaN_SHIFT 4 #define MVFR1_FPDNaN_MASK (UL(0xf) << MVFR1_FPDNaN_SHIFT) #define MVFR1_FPDNaN_VAL(x) ((x) & MVFR1_FPDNaN_MASK) #define MVFR1_FPDNaN_NONE (UL(0x0) << MVFR1_FPDNaN_SHIFT) #define MVFR1_FPDNaN_IMPL (UL(0x1) << MVFR1_FPDNaN_SHIFT) #define MVFR1_SIMDLS_SHIFT 8 #define MVFR1_SIMDLS_MASK (UL(0xf) << MVFR1_SIMDLS_SHIFT) #define MVFR1_SIMDLS_VAL(x) ((x) & MVFR1_SIMDLS_MASK) #define MVFR1_SIMDLS_NONE (UL(0x0) << MVFR1_SIMDLS_SHIFT) #define MVFR1_SIMDLS_IMPL (UL(0x1) << MVFR1_SIMDLS_SHIFT) #define MVFR1_SIMDInt_SHIFT 12 #define MVFR1_SIMDInt_MASK (UL(0xf) << MVFR1_SIMDInt_SHIFT) #define MVFR1_SIMDInt_VAL(x) ((x) & MVFR1_SIMDInt_MASK) #define MVFR1_SIMDInt_NONE (UL(0x0) << MVFR1_SIMDInt_SHIFT) #define MVFR1_SIMDInt_IMPL (UL(0x1) << MVFR1_SIMDInt_SHIFT) #define MVFR1_SIMDSP_SHIFT 16 #define MVFR1_SIMDSP_MASK (UL(0xf) << MVFR1_SIMDSP_SHIFT) #define MVFR1_SIMDSP_VAL(x) ((x) & MVFR1_SIMDSP_MASK) #define MVFR1_SIMDSP_NONE (UL(0x0) << MVFR1_SIMDSP_SHIFT) #define MVFR1_SIMDSP_IMPL (UL(0x1) << MVFR1_SIMDSP_SHIFT) #define MVFR1_SIMDHP_SHIFT 20 #define MVFR1_SIMDHP_MASK (UL(0xf) << MVFR1_SIMDHP_SHIFT) #define MVFR1_SIMDHP_VAL(x) ((x) & MVFR1_SIMDHP_MASK) #define MVFR1_SIMDHP_NONE (UL(0x0) << MVFR1_SIMDHP_SHIFT) #define MVFR1_SIMDHP_CONV_SP (UL(0x1) << MVFR1_SIMDHP_SHIFT) #define MVFR1_SIMDHP_ARITH (UL(0x2) << MVFR1_SIMDHP_SHIFT) #define MVFR1_FPHP_SHIFT 24 #define MVFR1_FPHP_MASK (UL(0xf) << MVFR1_FPHP_SHIFT) #define MVFR1_FPHP_VAL(x) ((x) & MVFR1_FPHP_MASK) #define MVFR1_FPHP_NONE (UL(0x0) << MVFR1_FPHP_SHIFT) #define MVFR1_FPHP_CONV_SP (UL(0x1) << MVFR1_FPHP_SHIFT) #define MVFR1_FPHP_CONV_DP (UL(0x2) << MVFR1_FPHP_SHIFT) #define MVFR1_FPHP_ARITH (UL(0x3) << MVFR1_FPHP_SHIFT) #define MVFR1_SIMDFMAC_SHIFT 28 #define MVFR1_SIMDFMAC_MASK (UL(0xf) << MVFR1_SIMDFMAC_SHIFT) #define MVFR1_SIMDFMAC_VAL(x) ((x) & MVFR1_SIMDFMAC_MASK) #define MVFR1_SIMDFMAC_NONE (UL(0x0) << MVFR1_SIMDFMAC_SHIFT) #define MVFR1_SIMDFMAC_IMPL (UL(0x1) << MVFR1_SIMDFMAC_SHIFT) /* OSDLR_EL1 */ #define OSDLR_EL1 MRS_REG(OSDLR_EL1) #define OSDLR_EL1_op0 2 #define OSDLR_EL1_op1 0 #define OSDLR_EL1_CRn 1 #define OSDLR_EL1_CRm 3 #define OSDLR_EL1_op2 4 /* OSLAR_EL1 */ #define OSLAR_EL1 MRS_REG(OSLAR_EL1) #define OSLAR_EL1_op0 2 #define OSLAR_EL1_op1 0 #define OSLAR_EL1_CRn 1 #define OSLAR_EL1_CRm 0 #define OSLAR_EL1_op2 4 /* OSLSR_EL1 */ #define OSLSR_EL1 MRS_REG(OSLSR_EL1) #define OSLSR_EL1_op0 2 #define OSLSR_EL1_op1 0 #define OSLSR_EL1_CRn 1 #define OSLSR_EL1_CRm 1 #define OSLSR_EL1_op2 4 /* PAR_EL1 - Physical Address Register */ #define PAR_F_SHIFT 0 #define PAR_F (0x1 << PAR_F_SHIFT) #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) /* When PAR_F == 0 (success) */ #define PAR_LOW_MASK 0xfff #define PAR_SH_SHIFT 7 #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) #define PAR_NS_SHIFT 9 #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) #define PAR_PA_SHIFT 12 #define PAR_PA_MASK 0x0000fffffffff000 #define PAR_ATTR_SHIFT 56 #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) /* When PAR_F == 1 (aborted) */ #define PAR_FST_SHIFT 1 #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) #define PAR_PTW_SHIFT 8 #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) #define PAR_S_SHIFT 9 #define PAR_S_MASK (0x1 << PAR_S_SHIFT) /* PMBIDR_EL1 */ #define PMBIDR_EL1 MRS_REG(PMBIDR_EL1) #define PMBIDR_EL1_op0 0x3 #define PMBIDR_EL1_op1 0x0 #define PMBIDR_EL1_CRn 0x9 #define PMBIDR_EL1_CRm 0xa #define PMBIDR_EL1_op2 0x7 #define PMBIDR_Align_SHIFT 0 #define PMBIDR_Align_MASK (UL(0xf) << PMBIDR_Align_SHIFT) #define PMBIDR_P_SHIFT 4 #define PMBIDR_P (UL(0x1) << PMBIDR_P_SHIFT) #define PMBIDR_F_SHIFT 5 #define PMBIDR_F (UL(0x1) << PMBIDR_F_SHIFT) /* PMBLIMITR_EL1 */ #define PMBLIMITR_EL1 MRS_REG(PMBLIMITR_EL1) #define PMBLIMITR_EL1_op0 0x3 #define PMBLIMITR_EL1_op1 0x0 #define PMBLIMITR_EL1_CRn 0x9 #define PMBLIMITR_EL1_CRm 0xa #define PMBLIMITR_EL1_op2 0x0 #define PMBLIMITR_E_SHIFT 0 #define PMBLIMITR_E (UL(0x1) << PMBLIMITR_E_SHIFT) #define PMBLIMITR_FM_SHIFT 1 #define PMBLIMITR_FM_MASK (UL(0x3) << PMBLIMITR_FM_SHIFT) #define PMBLIMITR_PMFZ_SHIFT 5 #define PMBLIMITR_PMFZ (UL(0x1) << PMBLIMITR_PMFZ_SHIFT) #define PMBLIMITR_LIMIT_SHIFT 12 #define PMBLIMITR_LIMIT_MASK \ (UL(0xfffffffffffff) << PMBLIMITR_LIMIT_SHIFT) /* PMBPTR_EL1 */ #define PMBPTR_EL1 MRS_REG(PMBPTR_EL1) #define PMBPTR_EL1_op0 0x3 #define PMBPTR_EL1_op1 0x0 #define PMBPTR_EL1_CRn 0x9 #define PMBPTR_EL1_CRm 0xa #define PMBPTR_EL1_op2 0x1 #define PMBPTR_PTR_SHIFT 0 #define PMBPTR_PTR_MASK \ (UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT) /* PMBSR_EL1 */ #define PMBSR_EL1 MRS_REG(PMBSR_EL1) #define PMBSR_EL1_op0 0x3 #define PMBSR_EL1_op1 0x0 #define PMBSR_EL1_CRn 0x9 #define PMBSR_EL1_CRm 0xa #define PMBSR_EL1_op2 0x3 #define PMBSR_MSS_SHIFT 0 #define PMBSR_MSS_MASK (UL(0xffff) << PMBSR_MSS_SHIFT) #define PMBSR_COLL_SHIFT 16 #define PMBSR_COLL (UL(0x1) << PMBSR_COLL_SHIFT) #define PMBSR_S_SHIFT 17 #define PMBSR_S (UL(0x1) << PMBSR_S_SHIFT) #define PMBSR_EA_SHIFT 18 #define PMBSR_EA (UL(0x1) << PMBSR_EA_SHIFT) #define PMBSR_DL_SHIFT 19 #define PMBSR_DL (UL(0x1) << PMBSR_DL_SHIFT) #define PMBSR_EC_SHIFT 26 #define PMBSR_EC_MASK (UL(0x3f) << PMBSR_EC_SHIFT) /* PMCCFILTR_EL0 */ #define PMCCFILTR_EL0 MRS_REG(PMCCFILTR_EL0) #define PMCCFILTR_EL0_op0 3 #define PMCCFILTR_EL0_op1 3 #define PMCCFILTR_EL0_CRn 14 #define PMCCFILTR_EL0_CRm 15 #define PMCCFILTR_EL0_op2 7 /* PMCCNTR_EL0 */ #define PMCCNTR_EL0 MRS_REG(PMCCNTR_EL0) #define PMCCNTR_EL0_op0 3 #define PMCCNTR_EL0_op1 3 #define PMCCNTR_EL0_CRn 9 #define PMCCNTR_EL0_CRm 13 #define PMCCNTR_EL0_op2 0 /* PMCEID0_EL0 */ #define PMCEID0_EL0 MRS_REG(PMCEID0_EL0) #define PMCEID0_EL0_op0 3 #define PMCEID0_EL0_op1 3 #define PMCEID0_EL0_CRn 9 #define PMCEID0_EL0_CRm 12 #define PMCEID0_EL0_op2 6 /* PMCEID1_EL0 */ #define PMCEID1_EL0 MRS_REG(PMCEID1_EL0) #define PMCEID1_EL0_op0 3 #define PMCEID1_EL0_op1 3 #define PMCEID1_EL0_CRn 9 #define PMCEID1_EL0_CRm 12 #define PMCEID1_EL0_op2 7 /* PMCNTENCLR_EL0 */ #define PMCNTENCLR_EL0 MRS_REG(PMCNTENCLR_EL0) #define PMCNTENCLR_EL0_op0 3 #define PMCNTENCLR_EL0_op1 3 #define PMCNTENCLR_EL0_CRn 9 #define PMCNTENCLR_EL0_CRm 12 #define PMCNTENCLR_EL0_op2 2 /* PMCNTENSET_EL0 */ #define PMCNTENSET_EL0 MRS_REG(PMCNTENSET_EL0) #define PMCNTENSET_EL0_op0 3 #define PMCNTENSET_EL0_op1 3 #define PMCNTENSET_EL0_CRn 9 #define PMCNTENSET_EL0_CRm 12 #define PMCNTENSET_EL0_op2 1 /* PMCR_EL0 - Perfomance Monitoring Counters */ #define PMCR_EL0 MRS_REG(PMCR_EL0) #define PMCR_EL0_op0 3 #define PMCR_EL0_op1 3 #define PMCR_EL0_CRn 9 #define PMCR_EL0_CRm 12 #define PMCR_EL0_op2 0 #define PMCR_E (1 << 0) /* Enable all counters */ #define PMCR_P (1 << 1) /* Reset all counters */ #define PMCR_C (1 << 2) /* Clock counter reset */ #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ #define PMCR_LC (1 << 6) /* Long cycle count enable */ #define PMCR_IMP_SHIFT 24 /* Implementer code */ #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) #define PMCR_IMP_ARM 0x41 #define PMCR_IDCODE_SHIFT 16 /* Identification code */ #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) #define PMCR_IDCODE_CORTEX_A57 0x01 #define PMCR_IDCODE_CORTEX_A72 0x02 #define PMCR_IDCODE_CORTEX_A53 0x03 #define PMCR_IDCODE_CORTEX_A73 0x04 #define PMCR_IDCODE_CORTEX_A35 0x0a #define PMCR_IDCODE_CORTEX_A76 0x0b #define PMCR_IDCODE_NEOVERSE_N1 0x0c #define PMCR_IDCODE_CORTEX_A77 0x10 #define PMCR_IDCODE_CORTEX_A55 0x45 #define PMCR_IDCODE_NEOVERSE_E1 0x46 #define PMCR_IDCODE_CORTEX_A75 0x4a #define PMCR_N_SHIFT 11 /* Number of counters implemented */ #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) /* PMEVCNTR_EL0 */ #define PMEVCNTR_EL0_op0 3 #define PMEVCNTR_EL0_op1 3 #define PMEVCNTR_EL0_CRn 14 #define PMEVCNTR_EL0_CRm 8 /* * PMEVCNTRn_EL0_CRm[1:0] holds the upper 2 bits of 'n' * PMEVCNTRn_EL0_op2 holds the lower 3 bits of 'n' */ /* PMEVTYPER_EL0 - Performance Monitoring Event Type */ #define PMEVTYPER_EL0_op0 3 #define PMEVTYPER_EL0_op1 3 #define PMEVTYPER_EL0_CRn 14 #define PMEVTYPER_EL0_CRm 12 /* * PMEVTYPERn_EL0_CRm[1:0] holds the upper 2 bits of 'n' * PMEVTYPERn_EL0_op2 holds the lower 3 bits of 'n' */ #define PMEVTYPER_EVTCOUNT_MASK 0x000003ff /* ARMv8.0 */ #define PMEVTYPER_EVTCOUNT_8_1_MASK 0x0000ffff /* ARMv8.1+ */ #define PMEVTYPER_MT (1 << 25) /* Multithreading */ #define PMEVTYPER_M (1 << 26) /* Secure EL3 filtering */ #define PMEVTYPER_NSH (1 << 27) /* Non-secure hypervisor filtering */ #define PMEVTYPER_NSU (1 << 28) /* Non-secure user filtering */ #define PMEVTYPER_NSK (1 << 29) /* Non-secure kernel filtering */ #define PMEVTYPER_U (1 << 30) /* User filtering */ #define PMEVTYPER_P (1 << 31) /* Privileged filtering */ /* PMINTENCLR_EL1 */ #define PMINTENCLR_EL1 MRS_REG(PMINTENCLR_EL1) #define PMINTENCLR_EL1_op0 3 #define PMINTENCLR_EL1_op1 0 #define PMINTENCLR_EL1_CRn 9 #define PMINTENCLR_EL1_CRm 14 #define PMINTENCLR_EL1_op2 2 /* PMINTENSET_EL1 */ #define PMINTENSET_EL1 MRS_REG(PMINTENSET_EL1) #define PMINTENSET_EL1_op0 3 #define PMINTENSET_EL1_op1 0 #define PMINTENSET_EL1_CRn 9 #define PMINTENSET_EL1_CRm 14 #define PMINTENSET_EL1_op2 1 /* PMMIR_EL1 */ #define PMMIR_EL1 MRS_REG(PMMIR_EL1) #define PMMIR_EL1_op0 3 #define PMMIR_EL1_op1 0 #define PMMIR_EL1_CRn 9 #define PMMIR_EL1_CRm 14 #define PMMIR_EL1_op2 6 /* PMOVSCLR_EL0 */ #define PMOVSCLR_EL0 MRS_REG(PMOVSCLR_EL0) #define PMOVSCLR_EL0_op0 3 #define PMOVSCLR_EL0_op1 3 #define PMOVSCLR_EL0_CRn 9 #define PMOVSCLR_EL0_CRm 12 #define PMOVSCLR_EL0_op2 3 /* PMOVSSET_EL0 */ #define PMOVSSET_EL0 MRS_REG(PMOVSSET_EL0) #define PMOVSSET_EL0_op0 3 #define PMOVSSET_EL0_op1 3 #define PMOVSSET_EL0_CRn 9 #define PMOVSSET_EL0_CRm 14 #define PMOVSSET_EL0_op2 3 /* PMSCR_EL1 */ #define PMSCR_EL1 MRS_REG(PMSCR_EL1) #define PMSCR_EL1_op0 0x3 #define PMSCR_EL1_op1 0x0 #define PMSCR_EL1_CRn 0x9 #define PMSCR_EL1_CRm 0x9 #define PMSCR_EL1_op2 0x0 #define PMSCR_E0SPE_SHIFT 0 #define PMSCR_E0SPE (UL(0x1) << PMSCR_E0SPE_SHIFT) #define PMSCR_E1SPE_SHIFT 1 #define PMSCR_E1SPE (UL(0x1) << PMSCR_E1SPE_SHIFT) #define PMSCR_CX_SHIFT 3 #define PMSCR_CX (UL(0x1) << PMSCR_CX_SHIFT) #define PMSCR_PA_SHIFT 4 #define PMSCR_PA (UL(0x1) << PMSCR_PA_SHIFT) #define PMSCR_TS_SHIFT 5 #define PMSCR_TS (UL(0x1) << PMSCR_TS_SHIFT) #define PMSCR_PCT_SHIFT 6 #define PMSCR_PCT_MASK (UL(0x3) << PMSCR_PCT_SHIFT) /* PMSELR_EL0 */ #define PMSELR_EL0 MRS_REG(PMSELR_EL0) #define PMSELR_EL0_op0 3 #define PMSELR_EL0_op1 3 #define PMSELR_EL0_CRn 9 #define PMSELR_EL0_CRm 12 #define PMSELR_EL0_op2 5 #define PMSELR_SEL_MASK 0x1f /* PMSEVFR_EL1 */ #define PMSEVFR_EL1 MRS_REG(PMSEVFR_EL1) #define PMSEVFR_EL1_op0 0x3 #define PMSEVFR_EL1_op1 0x0 #define PMSEVFR_EL1_CRn 0x9 #define PMSEVFR_EL1_CRm 0x9 #define PMSEVFR_EL1_op2 0x5 /* PMSFCR_EL1 */ #define PMSFCR_EL1 MRS_REG(PMSFCR_EL1) #define PMSFCR_EL1_op0 0x3 #define PMSFCR_EL1_op1 0x0 #define PMSFCR_EL1_CRn 0x9 #define PMSFCR_EL1_CRm 0x9 #define PMSFCR_EL1_op2 0x4 #define PMSFCR_FE_SHIFT 0 #define PMSFCR_FE (UL(0x1) << PMSFCR_FE_SHIFT) #define PMSFCR_FT_SHIFT 1 #define PMSFCR_FT (UL(0x1) << PMSFCR_FT_SHIFT) #define PMSFCR_FL_SHIFT 2 #define PMSFCR_FL (UL(0x1) << PMSFCR_FL_SHIFT) #define PMSFCR_FnE_SHIFT 3 #define PMSFCR_FnE (UL(0x1) << PMSFCR_FnE_SHIFT) #define PMSFCR_B_SHIFT 16 #define PMSFCR_B (UL(0x1) << PMSFCR_B_SHIFT) #define PMSFCR_LD_SHIFT 17 #define PMSFCR_LD (UL(0x1) << PMSFCR_LD_SHIFT) #define PMSFCR_ST_SHIFT 18 #define PMSFCR_ST (UL(0x1) << PMSFCR_ST_SHIFT) /* PMSICR_EL1 */ #define PMSICR_EL1 MRS_REG(PMSICR_EL1) #define PMSICR_EL1_op0 0x3 #define PMSICR_EL1_op1 0x0 #define PMSICR_EL1_CRn 0x9 #define PMSICR_EL1_CRm 0x9 #define PMSICR_EL1_op2 0x2 #define PMSICR_COUNT_SHIFT 0 #define PMSICR_COUNT_MASK (UL(0xffffffff) << PMSICR_COUNT_SHIFT) #define PMSICR_ECOUNT_SHIFT 56 #define PMSICR_ECOUNT_MASK (UL(0xff) << PMSICR_ECOUNT_SHIFT) /* PMSIDR_EL1 */ #define PMSIDR_EL1 MRS_REG(PMSIDR_EL1) #define PMSIDR_EL1_op0 0x3 #define PMSIDR_EL1_op1 0x0 #define PMSIDR_EL1_CRn 0x9 #define PMSIDR_EL1_CRm 0x9 #define PMSIDR_EL1_op2 0x7 #define PMSIDR_FE_SHIFT 0 #define PMSIDR_FE (UL(0x1) << PMSIDR_FE_SHIFT) #define PMSIDR_FT_SHIFT 1 #define PMSIDR_FT (UL(0x1) << PMSIDR_FT_SHIFT) #define PMSIDR_FL_SHIFT 2 #define PMSIDR_FL (UL(0x1) << PMSIDR_FL_SHIFT) #define PMSIDR_ArchInst_SHIFT 3 #define PMSIDR_ArchInst (UL(0x1) << PMSIDR_ArchInst_SHIFT) #define PMSIDR_LDS_SHIFT 4 #define PMSIDR_LDS (UL(0x1) << PMSIDR_LDS_SHIFT) #define PMSIDR_ERnd_SHIFT 5 #define PMSIDR_ERnd (UL(0x1) << PMSIDR_ERnd_SHIFT) #define PMSIDR_FnE_SHIFT 6 #define PMSIDR_FnE (UL(0x1) << PMSIDR_FnE_SHIFT) #define PMSIDR_Interval_SHIFT 8 #define PMSIDR_Interval_MASK (UL(0xf) << PMSIDR_Interval_SHIFT) #define PMSIDR_MaxSize_SHIFT 12 #define PMSIDR_MaxSize_MASK (UL(0xf) << PMSIDR_MaxSize_SHIFT) #define PMSIDR_CountSize_SHIFT 16 #define PMSIDR_CountSize_MASK (UL(0xf) << PMSIDR_CountSize_SHIFT) #define PMSIDR_Format_SHIFT 20 #define PMSIDR_Format_MASK (UL(0xf) << PMSIDR_Format_SHIFT) #define PMSIDR_PBT_SHIFT 24 #define PMSIDR_PBT (UL(0x1) << PMSIDR_PBT_SHIFT) /* PMSIRR_EL1 */ #define PMSIRR_EL1 MRS_REG(PMSIRR_EL1) #define PMSIRR_EL1_op0 0x3 #define PMSIRR_EL1_op1 0x0 #define PMSIRR_EL1_CRn 0x9 #define PMSIRR_EL1_CRm 0x9 #define PMSIRR_EL1_op2 0x3 #define PMSIRR_RND_SHIFT 0 #define PMSIRR_RND (UL(0x1) << PMSIRR_RND_SHIFT) #define PMSIRR_INTERVAL_SHIFT 8 #define PMSIRR_INTERVAL_MASK (UL(0xffffff) << PMSIRR_INTERVAL_SHIFT) /* PMSLATFR_EL1 */ #define PMSLATFR_EL1 MRS_REG(PMSLATFR_EL1) #define PMSLATFR_EL1_op0 0x3 #define PMSLATFR_EL1_op1 0x0 #define PMSLATFR_EL1_CRn 0x9 #define PMSLATFR_EL1_CRm 0x9 #define PMSLATFR_EL1_op2 0x6 #define PMSLATFR_MINLAT_SHIFT 0 #define PMSLATFR_MINLAT_MASK (UL(0xfff) << PMSLATFR_MINLAT_SHIFT) /* PMSNEVFR_EL1 */ #define PMSNEVFR_EL1 MRS_REG(PMSNEVFR_EL1) #define PMSNEVFR_EL1_op0 0x3 #define PMSNEVFR_EL1_op1 0x0 #define PMSNEVFR_EL1_CRn 0x9 #define PMSNEVFR_EL1_CRm 0x9 #define PMSNEVFR_EL1_op2 0x1 /* PMSWINC_EL0 */ #define PMSWINC_EL0 MRS_REG(PMSWINC_EL0) #define PMSWINC_EL0_op0 3 #define PMSWINC_EL0_op1 3 #define PMSWINC_EL0_CRn 9 #define PMSWINC_EL0_CRm 12 #define PMSWINC_EL0_op2 4 /* PMUSERENR_EL0 */ #define PMUSERENR_EL0 MRS_REG(PMUSERENR_EL0) #define PMUSERENR_EL0_op0 3 #define PMUSERENR_EL0_op1 3 #define PMUSERENR_EL0_CRn 9 #define PMUSERENR_EL0_CRm 14 #define PMUSERENR_EL0_op2 0 /* PMXEVCNTR_EL0 */ #define PMXEVCNTR_EL0 MRS_REG(PMXEVCNTR_EL0) #define PMXEVCNTR_EL0_op0 3 #define PMXEVCNTR_EL0_op1 3 #define PMXEVCNTR_EL0_CRn 9 #define PMXEVCNTR_EL0_CRm 13 #define PMXEVCNTR_EL0_op2 2 /* PMXEVTYPER_EL0 */ #define PMXEVTYPER_EL0 MRS_REG(PMXEVTYPER_EL0) #define PMXEVTYPER_EL0_op0 3 #define PMXEVTYPER_EL0_op1 3 #define PMXEVTYPER_EL0_CRn 9 #define PMXEVTYPER_EL0_CRm 13 #define PMXEVTYPER_EL0_op2 1 /* SCTLR_EL1 - System Control Register */ #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ #define SCTLR_M (UL(0x1) << 0) #define SCTLR_A (UL(0x1) << 1) #define SCTLR_C (UL(0x1) << 2) #define SCTLR_SA (UL(0x1) << 3) #define SCTLR_SA0 (UL(0x1) << 4) #define SCTLR_CP15BEN (UL(0x1) << 5) #define SCTLR_nAA (UL(0x1) << 6) #define SCTLR_ITD (UL(0x1) << 7) #define SCTLR_SED (UL(0x1) << 8) #define SCTLR_UMA (UL(0x1) << 9) #define SCTLR_EnRCTX (UL(0x1) << 10) #define SCTLR_EOS (UL(0x1) << 11) #define SCTLR_I (UL(0x1) << 12) #define SCTLR_EnDB (UL(0x1) << 13) #define SCTLR_DZE (UL(0x1) << 14) #define SCTLR_UCT (UL(0x1) << 15) #define SCTLR_nTWI (UL(0x1) << 16) /* Bit 17 is reserved */ #define SCTLR_nTWE (UL(0x1) << 18) #define SCTLR_WXN (UL(0x1) << 19) #define SCTLR_TSCXT (UL(0x1) << 20) #define SCTLR_IESB (UL(0x1) << 21) #define SCTLR_EIS (UL(0x1) << 22) #define SCTLR_SPAN (UL(0x1) << 23) #define SCTLR_E0E (UL(0x1) << 24) #define SCTLR_EE (UL(0x1) << 25) #define SCTLR_UCI (UL(0x1) << 26) #define SCTLR_EnDA (UL(0x1) << 27) #define SCTLR_nTLSMD (UL(0x1) << 28) #define SCTLR_LSMAOE (UL(0x1) << 29) #define SCTLR_EnIB (UL(0x1) << 30) #define SCTLR_EnIA (UL(0x1) << 31) /* Bits 34:32 are reserved */ #define SCTLR_BT0 (UL(0x1) << 35) #define SCTLR_BT1 (UL(0x1) << 36) #define SCTLR_ITFSB (UL(0x1) << 37) #define SCTLR_TCF0_MASK (UL(0x3) << 38) #define SCTLR_TCF_MASK (UL(0x3) << 40) #define SCTLR_ATA0 (UL(0x1) << 42) #define SCTLR_ATA (UL(0x1) << 43) #define SCTLR_DSSBS (UL(0x1) << 44) #define SCTLR_TWEDEn (UL(0x1) << 45) #define SCTLR_TWEDEL_MASK (UL(0xf) << 46) /* Bits 53:50 are reserved */ #define SCTLR_EnASR (UL(0x1) << 54) #define SCTLR_EnAS0 (UL(0x1) << 55) #define SCTLR_EnALS (UL(0x1) << 56) #define SCTLR_EPAN (UL(0x1) << 57) /* SPSR_EL1 */ /* * When the exception is taken in AArch64: * M[3:2] is the exception level * M[1] is unused * M[0] is the SP select: * 0: always SP0 * 1: current ELs SP */ #define PSR_M_EL0t 0x00000000UL #define PSR_M_EL1t 0x00000004UL #define PSR_M_EL1h 0x00000005UL #define PSR_M_EL2t 0x00000008UL #define PSR_M_EL2h 0x00000009UL #define PSR_M_64 0x00000000UL #define PSR_M_32 0x00000010UL #define PSR_M_MASK 0x0000000fUL #define PSR_T 0x00000020UL #define PSR_AARCH32 0x00000010UL #define PSR_F 0x00000040UL #define PSR_I 0x00000080UL #define PSR_A 0x00000100UL #define PSR_D 0x00000200UL #define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F) /* The default DAIF mask. These bits are valid in spsr_el1 and daif */ #define PSR_DAIF_DEFAULT (PSR_F) #define PSR_IL 0x00100000UL #define PSR_SS 0x00200000UL #define PSR_V 0x10000000UL #define PSR_C 0x20000000UL #define PSR_Z 0x40000000UL #define PSR_N 0x80000000UL #define PSR_FLAGS 0xf0000000UL /* PSR fields that can be set from 32-bit and 64-bit processes */ #define PSR_SETTABLE_32 PSR_FLAGS #define PSR_SETTABLE_64 (PSR_FLAGS | PSR_SS) /* REVIDR_EL1 - Revision ID Register */ #define REVIDR_EL1 MRS_REG(REVIDR_EL1) #define REVIDR_EL1_op0 3 #define REVIDR_EL1_op1 0 #define REVIDR_EL1_CRn 0 #define REVIDR_EL1_CRm 0 #define REVIDR_EL1_op2 6 /* TCR_EL1 - Translation Control Register */ /* Bits 63:59 are reserved */ #define TCR_TCMA1_SHIFT 58 #define TCR_TCMA1 (1UL << TCR_TCMA1_SHIFT) #define TCR_TCMA0_SHIFT 57 #define TCR_TCMA0 (1UL << TCR_TCMA0_SHIFT) #define TCR_E0PD1_SHIFT 56 #define TCR_E0PD1 (1UL << TCR_E0PD1_SHIFT) #define TCR_E0PD0_SHIFT 55 #define TCR_E0PD0 (1UL << TCR_E0PD0_SHIFT) #define TCR_NFD1_SHIFT 54 #define TCR_NFD1 (1UL << TCR_NFD1_SHIFT) #define TCR_NFD0_SHIFT 53 #define TCR_NFD0 (1UL << TCR_NFD0_SHIFT) #define TCR_TBID1_SHIFT 52 #define TCR_TBID1 (1UL << TCR_TBID1_SHIFT) #define TCR_TBID0_SHIFT 51 #define TCR_TBID0 (1UL << TCR_TBID0_SHIFT) #define TCR_HWU162_SHIFT 50 #define TCR_HWU162 (1UL << TCR_HWU162_SHIFT) #define TCR_HWU161_SHIFT 49 #define TCR_HWU161 (1UL << TCR_HWU161_SHIFT) #define TCR_HWU160_SHIFT 48 #define TCR_HWU160 (1UL << TCR_HWU160_SHIFT) #define TCR_HWU159_SHIFT 47 #define TCR_HWU159 (1UL << TCR_HWU159_SHIFT) #define TCR_HWU1 \ (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162) #define TCR_HWU062_SHIFT 46 #define TCR_HWU062 (1UL << TCR_HWU062_SHIFT) #define TCR_HWU061_SHIFT 45 #define TCR_HWU061 (1UL << TCR_HWU061_SHIFT) #define TCR_HWU060_SHIFT 44 #define TCR_HWU060 (1UL << TCR_HWU060_SHIFT) #define TCR_HWU059_SHIFT 43 #define TCR_HWU059 (1UL << TCR_HWU059_SHIFT) #define TCR_HWU0 \ (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062) #define TCR_HPD1_SHIFT 42 #define TCR_HPD1 (1UL << TCR_HPD1_SHIFT) #define TCR_HPD0_SHIFT 41 #define TCR_HPD0 (1UL << TCR_HPD0_SHIFT) #define TCR_HD_SHIFT 40 #define TCR_HD (1UL << TCR_HD_SHIFT) #define TCR_HA_SHIFT 39 #define TCR_HA (1UL << TCR_HA_SHIFT) #define TCR_TBI1_SHIFT 38 #define TCR_TBI1 (1UL << TCR_TBI1_SHIFT) #define TCR_TBI0_SHIFT 37 #define TCR_TBI0 (1U << TCR_TBI0_SHIFT) #define TCR_ASID_SHIFT 36 #define TCR_ASID_WIDTH 1 #define TCR_ASID_16 (1UL << TCR_ASID_SHIFT) /* Bit 35 is reserved */ #define TCR_IPS_SHIFT 32 #define TCR_IPS_WIDTH 3 #define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) #define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) #define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) #define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) #define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) #define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) #define TCR_TG1_SHIFT 30 #define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) #define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) #define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) #define TCR_SH1_SHIFT 28 #define TCR_SH1_IS (3UL << TCR_SH1_SHIFT) #define TCR_ORGN1_SHIFT 26 #define TCR_ORGN1_WBWA (1UL << TCR_ORGN1_SHIFT) #define TCR_IRGN1_SHIFT 24 #define TCR_IRGN1_WBWA (1UL << TCR_IRGN1_SHIFT) #define TCR_EPD1_SHIFT 23 #define TCR_EPD1 (1UL << TCR_EPD1_SHIFT) #define TCR_A1_SHIFT 22 #define TCR_A1 (0x1UL << TCR_A1_SHIFT) #define TCR_T1SZ_SHIFT 16 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) #define TCR_TG0_SHIFT 14 #define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) #define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) #define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) #define TCR_SH0_SHIFT 12 #define TCR_SH0_IS (3UL << TCR_SH0_SHIFT) #define TCR_ORGN0_SHIFT 10 #define TCR_ORGN0_WBWA (1UL << TCR_ORGN0_SHIFT) #define TCR_IRGN0_SHIFT 8 #define TCR_IRGN0_WBWA (1UL << TCR_IRGN0_SHIFT) #define TCR_EPD0_SHIFT 7 #define TCR_EPD0 (1UL << TCR_EPD1_SHIFT) /* Bit 6 is reserved */ #define TCR_T0SZ_SHIFT 0 #define TCR_T0SZ_MASK 0x3f #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) #ifdef SMP #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) #else #define TCR_SMP_ATTRS 0 #endif /* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */ #define TTBR_ASID_SHIFT 48 #define TTBR_ASID_MASK (0xfffful << TTBR_ASID_SHIFT) #define TTBR_BADDR 0x0000fffffffffffeul #define TTBR_CnP_SHIFT 0 #define TTBR_CnP (1ul << TTBR_CnP_SHIFT) /* ZCR_EL1 - SVE Control Register */ #define ZCR_LEN_SHIFT 0 #define ZCR_LEN_MASK (0xf << ZCR_LEN_SHIFT) #define ZCR_LEN_BYTES(x) ((((x) & ZCR_LEN_MASK) + 1) * 16) #endif /* !_MACHINE_ARMREG_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/asm.h b/sys/arm64/include/asm.h index b1d4ba50be9a..fbd09a5607c4 100644 --- a/sys/arm64/include/asm.h +++ b/sys/arm64/include/asm.h @@ -1,115 +1,121 @@ /*- * Copyright (c) 2014 Andrew Turner * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_ASM_H_ #define _MACHINE_ASM_H_ #undef __FBSDID #if !defined(lint) && !defined(STRIP_FBSDID) #define __FBSDID(s) .ident s #else #define __FBSDID(s) /* nothing */ #endif #define _C_LABEL(x) x #ifdef KDTRACE_HOOKS #define DTRACE_NOP nop #else #define DTRACE_NOP #endif #define LENTRY(sym) \ .text; .align 2; .type sym,#function; sym: \ .cfi_startproc; DTRACE_NOP #define ENTRY(sym) \ .globl sym; LENTRY(sym) #define EENTRY(sym) \ .globl sym; .text; .align 2; .type sym,#function; sym: #define LEND(sym) .ltorg; .cfi_endproc; .size sym, . - sym #define END(sym) LEND(sym) #define EEND(sym) #define WEAK_REFERENCE(sym, alias) \ .weak alias; \ .set alias,sym #define UINT64_C(x) (x) #if defined(PIC) #define PIC_SYM(x,y) x ## @ ## y #else #define PIC_SYM(x,y) x #endif /* Alias for link register x30 */ #define lr x30 /* * Sets the trap fault handler. The exception handler will return to the * address in the handler register on a data abort or the xzr register to * clear the handler. The tmp parameter should be a register able to hold * the temporary data. */ #define SET_FAULT_HANDLER(handler, tmp) \ ldr tmp, [x18, #PC_CURTHREAD]; /* Load curthread */ \ ldr tmp, [tmp, #TD_PCB]; /* Load the pcb */ \ str handler, [tmp, #PCB_ONFAULT] /* Set the handler */ #define ENTER_USER_ACCESS(reg, tmp) \ ldr tmp, =has_pan; /* Get the addr of has_pan */ \ ldr reg, [tmp]; /* Read it */ \ cbz reg, 997f; /* If no PAN skip */ \ .inst 0xd500409f | (0 << 8); /* Clear PAN */ \ 997: #define EXIT_USER_ACCESS(reg) \ cbz reg, 998f; /* If no PAN skip */ \ .inst 0xd500409f | (1 << 8); /* Set PAN */ \ 998: #define EXIT_USER_ACCESS_CHECK(reg, tmp) \ ldr tmp, =has_pan; /* Get the addr of has_pan */ \ ldr reg, [tmp]; /* Read it */ \ cbz reg, 999f; /* If no PAN skip */ \ .inst 0xd500409f | (1 << 8); /* Set PAN */ \ 999: /* * Some AArch64 CPUs speculate past an eret instruction. As the user may * control the registers at this point add a speculation barrier usable on * all AArch64 CPUs after the eret instruction. * TODO: ARMv8.5 adds a specific instruction for this, we could use that * if we know we are running on something that supports it. */ #define ERET \ eret; \ dsb sy; \ isb #endif /* _MACHINE_ASM_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/atomic.h b/sys/arm64/include/atomic.h index b14cd303da3a..172bf051edf3 100644 --- a/sys/arm64/include/atomic.h +++ b/sys/arm64/include/atomic.h @@ -1,672 +1,678 @@ /*- * Copyright (c) 2013 Andrew Turner * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_ATOMIC_H_ #define _MACHINE_ATOMIC_H_ #define isb() __asm __volatile("isb" : : : "memory") /* * Options for DMB and DSB: * oshld Outer Shareable, load * oshst Outer Shareable, store * osh Outer Shareable, all * nshld Non-shareable, load * nshst Non-shareable, store * nsh Non-shareable, all * ishld Inner Shareable, load * ishst Inner Shareable, store * ish Inner Shareable, all * ld Full system, load * st Full system, store * sy Full system, all */ #define dsb(opt) __asm __volatile("dsb " __STRING(opt) : : : "memory") #define dmb(opt) __asm __volatile("dmb " __STRING(opt) : : : "memory") #define mb() dmb(sy) /* Full system memory barrier all */ #define wmb() dmb(st) /* Full system memory barrier store */ #define rmb() dmb(ld) /* Full system memory barrier load */ #ifdef _KERNEL extern _Bool lse_supported; #endif #if defined(SAN_NEEDS_INTERCEPTORS) && !defined(SAN_RUNTIME) #include #else #include #ifdef _KERNEL #ifdef LSE_ATOMICS #define _ATOMIC_LSE_SUPPORTED 1 #else #define _ATOMIC_LSE_SUPPORTED lse_supported #endif #else #define _ATOMIC_LSE_SUPPORTED 0 #endif #define _ATOMIC_OP_PROTO(t, op, bar, flav) \ static __inline void \ atomic_##op##_##bar##t##flav(volatile uint##t##_t *p, uint##t##_t val) #define _ATOMIC_OP_IMPL(t, w, s, op, llsc_asm_op, lse_asm_op, pre, bar, a, l) \ _ATOMIC_OP_PROTO(t, op, bar, _llsc) \ { \ uint##t##_t tmp; \ int res; \ \ pre; \ __asm __volatile( \ "1: ld"#a"xr"#s" %"#w"0, [%2]\n" \ " "#llsc_asm_op" %"#w"0, %"#w"0, %"#w"3\n" \ " st"#l"xr"#s" %w1, %"#w"0, [%2]\n" \ " cbnz %w1, 1b\n" \ : "=&r"(tmp), "=&r"(res) \ : "r" (p), "r" (val) \ : "memory" \ ); \ } \ \ _ATOMIC_OP_PROTO(t, op, bar, _lse) \ { \ uint##t##_t tmp; \ \ pre; \ __asm __volatile( \ ".arch_extension lse\n" \ "ld"#lse_asm_op#a#l#s" %"#w"2, %"#w"0, [%1]\n" \ ".arch_extension nolse\n" \ : "=r" (tmp) \ : "r" (p), "r" (val) \ : "memory" \ ); \ } \ \ _ATOMIC_OP_PROTO(t, op, bar, ) \ { \ if (_ATOMIC_LSE_SUPPORTED) \ atomic_##op##_##bar##t##_lse(p, val); \ else \ atomic_##op##_##bar##t##_llsc(p, val); \ } #define __ATOMIC_OP(op, llsc_asm_op, lse_asm_op, pre, bar, a, l) \ _ATOMIC_OP_IMPL(8, w, b, op, llsc_asm_op, lse_asm_op, pre, \ bar, a, l) \ _ATOMIC_OP_IMPL(16, w, h, op, llsc_asm_op, lse_asm_op, pre, \ bar, a, l) \ _ATOMIC_OP_IMPL(32, w, , op, llsc_asm_op, lse_asm_op, pre, \ bar, a, l) \ _ATOMIC_OP_IMPL(64, , , op, llsc_asm_op, lse_asm_op, pre, \ bar, a, l) #define _ATOMIC_OP(op, llsc_asm_op, lse_asm_op, pre) \ __ATOMIC_OP(op, llsc_asm_op, lse_asm_op, pre, , , ) \ __ATOMIC_OP(op, llsc_asm_op, lse_asm_op, pre, acq_, a, ) \ __ATOMIC_OP(op, llsc_asm_op, lse_asm_op, pre, rel_, , l) _ATOMIC_OP(add, add, add, ) _ATOMIC_OP(clear, bic, clr, ) _ATOMIC_OP(set, orr, set, ) _ATOMIC_OP(subtract, add, add, val = -val) #define _ATOMIC_CMPSET_PROTO(t, bar, flav) \ static __inline int \ atomic_cmpset_##bar##t##flav(volatile uint##t##_t *p, \ uint##t##_t cmpval, uint##t##_t newval) #define _ATOMIC_FCMPSET_PROTO(t, bar, flav) \ static __inline int \ atomic_fcmpset_##bar##t##flav(volatile uint##t##_t *p, \ uint##t##_t *cmpval, uint##t##_t newval) #define _ATOMIC_CMPSET_IMPL(t, w, s, bar, a, l) \ _ATOMIC_CMPSET_PROTO(t, bar, _llsc) \ { \ uint##t##_t tmp; \ int res; \ \ __asm __volatile( \ "1: mov %w1, #1\n" \ " ld"#a"xr"#s" %"#w"0, [%2]\n" \ " cmp %"#w"0, %"#w"3\n" \ " b.ne 2f\n" \ " st"#l"xr"#s" %w1, %"#w"4, [%2]\n" \ " cbnz %w1, 1b\n" \ "2:" \ : "=&r"(tmp), "=&r"(res) \ : "r" (p), "r" (cmpval), "r" (newval) \ : "cc", "memory" \ ); \ \ return (!res); \ } \ \ _ATOMIC_CMPSET_PROTO(t, bar, _lse) \ { \ uint##t##_t oldval; \ int res; \ \ oldval = cmpval; \ __asm __volatile( \ ".arch_extension lse\n" \ "cas"#a#l#s" %"#w"1, %"#w"4, [%3]\n" \ "cmp %"#w"1, %"#w"2\n" \ "cset %w0, eq\n" \ ".arch_extension nolse\n" \ : "=r" (res), "+&r" (cmpval) \ : "r" (oldval), "r" (p), "r" (newval) \ : "cc", "memory" \ ); \ \ return (res); \ } \ \ _ATOMIC_CMPSET_PROTO(t, bar, ) \ { \ if (_ATOMIC_LSE_SUPPORTED) \ return (atomic_cmpset_##bar##t##_lse(p, cmpval, \ newval)); \ else \ return (atomic_cmpset_##bar##t##_llsc(p, cmpval, \ newval)); \ } \ \ _ATOMIC_FCMPSET_PROTO(t, bar, _llsc) \ { \ uint##t##_t _cmpval, tmp; \ int res; \ \ _cmpval = *cmpval; \ __asm __volatile( \ " mov %w1, #1\n" \ " ld"#a"xr"#s" %"#w"0, [%2]\n" \ " cmp %"#w"0, %"#w"3\n" \ " b.ne 1f\n" \ " st"#l"xr"#s" %w1, %"#w"4, [%2]\n" \ "1:" \ : "=&r"(tmp), "=&r"(res) \ : "r" (p), "r" (_cmpval), "r" (newval) \ : "cc", "memory" \ ); \ *cmpval = tmp; \ \ return (!res); \ } \ \ _ATOMIC_FCMPSET_PROTO(t, bar, _lse) \ { \ uint##t##_t _cmpval, tmp; \ int res; \ \ _cmpval = tmp = *cmpval; \ __asm __volatile( \ ".arch_extension lse\n" \ "cas"#a#l#s" %"#w"1, %"#w"4, [%3]\n" \ "cmp %"#w"1, %"#w"2\n" \ "cset %w0, eq\n" \ ".arch_extension nolse\n" \ : "=r" (res), "+&r" (tmp) \ : "r" (_cmpval), "r" (p), "r" (newval) \ : "cc", "memory" \ ); \ *cmpval = tmp; \ \ return (res); \ } \ \ _ATOMIC_FCMPSET_PROTO(t, bar, ) \ { \ if (_ATOMIC_LSE_SUPPORTED) \ return (atomic_fcmpset_##bar##t##_lse(p, cmpval, \ newval)); \ else \ return (atomic_fcmpset_##bar##t##_llsc(p, cmpval, \ newval)); \ } #define _ATOMIC_CMPSET(bar, a, l) \ _ATOMIC_CMPSET_IMPL(8, w, b, bar, a, l) \ _ATOMIC_CMPSET_IMPL(16, w, h, bar, a, l) \ _ATOMIC_CMPSET_IMPL(32, w, , bar, a, l) \ _ATOMIC_CMPSET_IMPL(64, , , bar, a, l) #define atomic_cmpset_8 atomic_cmpset_8 #define atomic_fcmpset_8 atomic_fcmpset_8 #define atomic_cmpset_16 atomic_cmpset_16 #define atomic_fcmpset_16 atomic_fcmpset_16 _ATOMIC_CMPSET( , , ) _ATOMIC_CMPSET(acq_, a, ) _ATOMIC_CMPSET(rel_, ,l) #define _ATOMIC_FETCHADD_PROTO(t, flav) \ static __inline uint##t##_t \ atomic_fetchadd_##t##flav(volatile uint##t##_t *p, uint##t##_t val) #define _ATOMIC_FETCHADD_IMPL(t, w) \ _ATOMIC_FETCHADD_PROTO(t, _llsc) \ { \ uint##t##_t ret, tmp; \ int res; \ \ __asm __volatile( \ "1: ldxr %"#w"2, [%3]\n" \ " add %"#w"0, %"#w"2, %"#w"4\n" \ " stxr %w1, %"#w"0, [%3]\n" \ " cbnz %w1, 1b\n" \ : "=&r" (tmp), "=&r" (res), "=&r" (ret) \ : "r" (p), "r" (val) \ : "memory" \ ); \ \ return (ret); \ } \ \ _ATOMIC_FETCHADD_PROTO(t, _lse) \ { \ uint##t##_t ret; \ \ __asm __volatile( \ ".arch_extension lse\n" \ "ldadd %"#w"2, %"#w"0, [%1]\n" \ ".arch_extension nolse\n" \ : "=r" (ret) \ : "r" (p), "r" (val) \ : "memory" \ ); \ \ return (ret); \ } \ \ _ATOMIC_FETCHADD_PROTO(t, ) \ { \ if (_ATOMIC_LSE_SUPPORTED) \ return (atomic_fetchadd_##t##_lse(p, val)); \ else \ return (atomic_fetchadd_##t##_llsc(p, val)); \ } _ATOMIC_FETCHADD_IMPL(32, w) _ATOMIC_FETCHADD_IMPL(64, ) #define _ATOMIC_SWAP_PROTO(t, flav) \ static __inline uint##t##_t \ atomic_swap_##t##flav(volatile uint##t##_t *p, uint##t##_t val) #define _ATOMIC_READANDCLEAR_PROTO(t, flav) \ static __inline uint##t##_t \ atomic_readandclear_##t##flav(volatile uint##t##_t *p) #define _ATOMIC_SWAP_IMPL(t, w, zreg) \ _ATOMIC_SWAP_PROTO(t, _llsc) \ { \ uint##t##_t ret; \ int res; \ \ __asm __volatile( \ "1: ldxr %"#w"1, [%2]\n" \ " stxr %w0, %"#w"3, [%2]\n" \ " cbnz %w0, 1b\n" \ : "=&r" (res), "=&r" (ret) \ : "r" (p), "r" (val) \ : "memory" \ ); \ \ return (ret); \ } \ \ _ATOMIC_SWAP_PROTO(t, _lse) \ { \ uint##t##_t ret; \ \ __asm __volatile( \ ".arch_extension lse\n" \ "swp %"#w"2, %"#w"0, [%1]\n" \ ".arch_extension nolse\n" \ : "=r" (ret) \ : "r" (p), "r" (val) \ : "memory" \ ); \ \ return (ret); \ } \ \ _ATOMIC_SWAP_PROTO(t, ) \ { \ if (_ATOMIC_LSE_SUPPORTED) \ return (atomic_swap_##t##_lse(p, val)); \ else \ return (atomic_swap_##t##_llsc(p, val)); \ } \ \ _ATOMIC_READANDCLEAR_PROTO(t, _llsc) \ { \ uint##t##_t ret; \ int res; \ \ __asm __volatile( \ "1: ldxr %"#w"1, [%2]\n" \ " stxr %w0, "#zreg", [%2]\n" \ " cbnz %w0, 1b\n" \ : "=&r" (res), "=&r" (ret) \ : "r" (p) \ : "memory" \ ); \ \ return (ret); \ } \ \ _ATOMIC_READANDCLEAR_PROTO(t, _lse) \ { \ return (atomic_swap_##t##_lse(p, 0)); \ } \ \ _ATOMIC_READANDCLEAR_PROTO(t, ) \ { \ if (_ATOMIC_LSE_SUPPORTED) \ return (atomic_readandclear_##t##_lse(p)); \ else \ return (atomic_readandclear_##t##_llsc(p)); \ } _ATOMIC_SWAP_IMPL(32, w, wzr) _ATOMIC_SWAP_IMPL(64, , xzr) #define _ATOMIC_TEST_OP_PROTO(t, op, bar, flav) \ static __inline int \ atomic_testand##op##_##bar##t##flav(volatile uint##t##_t *p, u_int val) #define _ATOMIC_TEST_OP_IMPL(t, w, op, llsc_asm_op, lse_asm_op, bar, a) \ _ATOMIC_TEST_OP_PROTO(t, op, bar, _llsc) \ { \ uint##t##_t mask, old, tmp; \ int res; \ \ mask = ((uint##t##_t)1) << (val & (t - 1)); \ __asm __volatile( \ "1: ld"#a"xr %"#w"2, [%3]\n" \ " "#llsc_asm_op" %"#w"0, %"#w"2, %"#w"4\n" \ " stxr %w1, %"#w"0, [%3]\n" \ " cbnz %w1, 1b\n" \ : "=&r" (tmp), "=&r" (res), "=&r" (old) \ : "r" (p), "r" (mask) \ : "memory" \ ); \ \ return ((old & mask) != 0); \ } \ \ _ATOMIC_TEST_OP_PROTO(t, op, bar, _lse) \ { \ uint##t##_t mask, old; \ \ mask = ((uint##t##_t)1) << (val & (t - 1)); \ __asm __volatile( \ ".arch_extension lse\n" \ "ld"#lse_asm_op#a" %"#w"2, %"#w"0, [%1]\n" \ ".arch_extension nolse\n" \ : "=r" (old) \ : "r" (p), "r" (mask) \ : "memory" \ ); \ \ return ((old & mask) != 0); \ } \ \ _ATOMIC_TEST_OP_PROTO(t, op, bar, ) \ { \ if (_ATOMIC_LSE_SUPPORTED) \ return (atomic_testand##op##_##bar##t##_lse(p, val)); \ else \ return (atomic_testand##op##_##bar##t##_llsc(p, val)); \ } #define _ATOMIC_TEST_OP(op, llsc_asm_op, lse_asm_op) \ _ATOMIC_TEST_OP_IMPL(32, w, op, llsc_asm_op, lse_asm_op, , ) \ _ATOMIC_TEST_OP_IMPL(32, w, op, llsc_asm_op, lse_asm_op, acq_, a) \ _ATOMIC_TEST_OP_IMPL(64, , op, llsc_asm_op, lse_asm_op, , ) \ _ATOMIC_TEST_OP_IMPL(64, , op, llsc_asm_op, lse_asm_op, acq_, a) _ATOMIC_TEST_OP(clear, bic, clr) _ATOMIC_TEST_OP(set, orr, set) #define _ATOMIC_LOAD_ACQ_IMPL(t, w, s) \ static __inline uint##t##_t \ atomic_load_acq_##t(volatile uint##t##_t *p) \ { \ uint##t##_t ret; \ \ __asm __volatile( \ "ldar"#s" %"#w"0, [%1]\n" \ : "=&r" (ret) \ : "r" (p) \ : "memory"); \ \ return (ret); \ } #define atomic_load_acq_8 atomic_load_acq_8 #define atomic_load_acq_16 atomic_load_acq_16 _ATOMIC_LOAD_ACQ_IMPL(8, w, b) _ATOMIC_LOAD_ACQ_IMPL(16, w, h) _ATOMIC_LOAD_ACQ_IMPL(32, w, ) _ATOMIC_LOAD_ACQ_IMPL(64, , ) #define _ATOMIC_STORE_REL_IMPL(t, w, s) \ static __inline void \ atomic_store_rel_##t(volatile uint##t##_t *p, uint##t##_t val) \ { \ __asm __volatile( \ "stlr"#s" %"#w"0, [%1]\n" \ : \ : "r" (val), "r" (p) \ : "memory"); \ } _ATOMIC_STORE_REL_IMPL(8, w, b) _ATOMIC_STORE_REL_IMPL(16, w, h) _ATOMIC_STORE_REL_IMPL(32, w, ) _ATOMIC_STORE_REL_IMPL(64, , ) #define atomic_add_char atomic_add_8 #define atomic_fcmpset_char atomic_fcmpset_8 #define atomic_clear_char atomic_clear_8 #define atomic_cmpset_char atomic_cmpset_8 #define atomic_fetchadd_char atomic_fetchadd_8 #define atomic_readandclear_char atomic_readandclear_8 #define atomic_set_char atomic_set_8 #define atomic_swap_char atomic_swap_8 #define atomic_subtract_char atomic_subtract_8 #define atomic_testandclear_char atomic_testandclear_8 #define atomic_testandset_char atomic_testandset_8 #define atomic_add_acq_char atomic_add_acq_8 #define atomic_fcmpset_acq_char atomic_fcmpset_acq_8 #define atomic_clear_acq_char atomic_clear_acq_8 #define atomic_cmpset_acq_char atomic_cmpset_acq_8 #define atomic_load_acq_char atomic_load_acq_8 #define atomic_set_acq_char atomic_set_acq_8 #define atomic_subtract_acq_char atomic_subtract_acq_8 #define atomic_testandset_acq_char atomic_testandset_acq_8 #define atomic_add_rel_char atomic_add_rel_8 #define atomic_fcmpset_rel_char atomic_fcmpset_rel_8 #define atomic_clear_rel_char atomic_clear_rel_8 #define atomic_cmpset_rel_char atomic_cmpset_rel_8 #define atomic_set_rel_char atomic_set_rel_8 #define atomic_subtract_rel_char atomic_subtract_rel_8 #define atomic_store_rel_char atomic_store_rel_8 #define atomic_add_short atomic_add_16 #define atomic_fcmpset_short atomic_fcmpset_16 #define atomic_clear_short atomic_clear_16 #define atomic_cmpset_short atomic_cmpset_16 #define atomic_fetchadd_short atomic_fetchadd_16 #define atomic_readandclear_short atomic_readandclear_16 #define atomic_set_short atomic_set_16 #define atomic_swap_short atomic_swap_16 #define atomic_subtract_short atomic_subtract_16 #define atomic_testandclear_short atomic_testandclear_16 #define atomic_testandset_short atomic_testandset_16 #define atomic_add_acq_short atomic_add_acq_16 #define atomic_fcmpset_acq_short atomic_fcmpset_acq_16 #define atomic_clear_acq_short atomic_clear_acq_16 #define atomic_cmpset_acq_short atomic_cmpset_acq_16 #define atomic_load_acq_short atomic_load_acq_16 #define atomic_set_acq_short atomic_set_acq_16 #define atomic_subtract_acq_short atomic_subtract_acq_16 #define atomic_testandset_acq_short atomic_testandset_acq_16 #define atomic_add_rel_short atomic_add_rel_16 #define atomic_fcmpset_rel_short atomic_fcmpset_rel_16 #define atomic_clear_rel_short atomic_clear_rel_16 #define atomic_cmpset_rel_short atomic_cmpset_rel_16 #define atomic_set_rel_short atomic_set_rel_16 #define atomic_subtract_rel_short atomic_subtract_rel_16 #define atomic_store_rel_short atomic_store_rel_16 #define atomic_add_int atomic_add_32 #define atomic_fcmpset_int atomic_fcmpset_32 #define atomic_clear_int atomic_clear_32 #define atomic_cmpset_int atomic_cmpset_32 #define atomic_fetchadd_int atomic_fetchadd_32 #define atomic_readandclear_int atomic_readandclear_32 #define atomic_set_int atomic_set_32 #define atomic_swap_int atomic_swap_32 #define atomic_subtract_int atomic_subtract_32 #define atomic_testandclear_int atomic_testandclear_32 #define atomic_testandset_int atomic_testandset_32 #define atomic_add_acq_int atomic_add_acq_32 #define atomic_fcmpset_acq_int atomic_fcmpset_acq_32 #define atomic_clear_acq_int atomic_clear_acq_32 #define atomic_cmpset_acq_int atomic_cmpset_acq_32 #define atomic_load_acq_int atomic_load_acq_32 #define atomic_set_acq_int atomic_set_acq_32 #define atomic_subtract_acq_int atomic_subtract_acq_32 #define atomic_testandset_acq_int atomic_testandset_acq_32 #define atomic_add_rel_int atomic_add_rel_32 #define atomic_fcmpset_rel_int atomic_fcmpset_rel_32 #define atomic_clear_rel_int atomic_clear_rel_32 #define atomic_cmpset_rel_int atomic_cmpset_rel_32 #define atomic_set_rel_int atomic_set_rel_32 #define atomic_subtract_rel_int atomic_subtract_rel_32 #define atomic_store_rel_int atomic_store_rel_32 #define atomic_add_long atomic_add_64 #define atomic_fcmpset_long atomic_fcmpset_64 #define atomic_clear_long atomic_clear_64 #define atomic_cmpset_long atomic_cmpset_64 #define atomic_fetchadd_long atomic_fetchadd_64 #define atomic_readandclear_long atomic_readandclear_64 #define atomic_set_long atomic_set_64 #define atomic_swap_long atomic_swap_64 #define atomic_subtract_long atomic_subtract_64 #define atomic_testandclear_long atomic_testandclear_64 #define atomic_testandset_long atomic_testandset_64 #define atomic_add_ptr atomic_add_64 #define atomic_fcmpset_ptr atomic_fcmpset_64 #define atomic_clear_ptr atomic_clear_64 #define atomic_cmpset_ptr atomic_cmpset_64 #define atomic_fetchadd_ptr atomic_fetchadd_64 #define atomic_readandclear_ptr atomic_readandclear_64 #define atomic_set_ptr atomic_set_64 #define atomic_swap_ptr atomic_swap_64 #define atomic_subtract_ptr atomic_subtract_64 #define atomic_add_acq_long atomic_add_acq_64 #define atomic_fcmpset_acq_long atomic_fcmpset_acq_64 #define atomic_clear_acq_long atomic_clear_acq_64 #define atomic_cmpset_acq_long atomic_cmpset_acq_64 #define atomic_load_acq_long atomic_load_acq_64 #define atomic_set_acq_long atomic_set_acq_64 #define atomic_subtract_acq_long atomic_subtract_acq_64 #define atomic_testandset_acq_long atomic_testandset_acq_64 #define atomic_add_acq_ptr atomic_add_acq_64 #define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_64 #define atomic_clear_acq_ptr atomic_clear_acq_64 #define atomic_cmpset_acq_ptr atomic_cmpset_acq_64 #define atomic_load_acq_ptr atomic_load_acq_64 #define atomic_set_acq_ptr atomic_set_acq_64 #define atomic_subtract_acq_ptr atomic_subtract_acq_64 #define atomic_add_rel_long atomic_add_rel_64 #define atomic_fcmpset_rel_long atomic_fcmpset_rel_64 #define atomic_clear_rel_long atomic_clear_rel_64 #define atomic_cmpset_rel_long atomic_cmpset_rel_64 #define atomic_set_rel_long atomic_set_rel_64 #define atomic_subtract_rel_long atomic_subtract_rel_64 #define atomic_store_rel_long atomic_store_rel_64 #define atomic_add_rel_ptr atomic_add_rel_64 #define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_64 #define atomic_clear_rel_ptr atomic_clear_rel_64 #define atomic_cmpset_rel_ptr atomic_cmpset_rel_64 #define atomic_set_rel_ptr atomic_set_rel_64 #define atomic_subtract_rel_ptr atomic_subtract_rel_64 #define atomic_store_rel_ptr atomic_store_rel_64 static __inline void atomic_thread_fence_acq(void) { dmb(ld); } static __inline void atomic_thread_fence_rel(void) { dmb(sy); } static __inline void atomic_thread_fence_acq_rel(void) { dmb(sy); } static __inline void atomic_thread_fence_seq_cst(void) { dmb(sy); } #endif /* KCSAN && !KCSAN_RUNTIME */ #endif /* _MACHINE_ATOMIC_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/bus.h b/sys/arm64/include/bus.h index 902be0db3b62..4a43a8fb94c2 100644 --- a/sys/arm64/include/bus.h +++ b/sys/arm64/include/bus.h @@ -1,523 +1,529 @@ /* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */ /*- * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, * NASA Ames Research Center. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /*- * Copyright (c) 1996 Charles M. Hannum. All rights reserved. * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Christopher G. Demetriou * for the NetBSD Project. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * From: sys/arm/include/bus.h * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_BUS_H_ #define _MACHINE_BUS_H_ #include #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) #define BUS_SPACE_MAXADDR_24BIT 0xFFFFFFUL #define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFFUL #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFUL #define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFFUL #define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFFUL #define BUS_SPACE_MAXSIZE_40BIT 0xFFFFFFFFFFUL #define BUS_SPACE_MAXADDR 0xFFFFFFFFFFFFFFFFUL #define BUS_SPACE_MAXSIZE 0xFFFFFFFFFFFFFFFFUL #define BUS_SPACE_MAP_CACHEABLE 0x01 #define BUS_SPACE_MAP_LINEAR 0x02 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 #define BUS_SPACE_MAP_NONPOSTED 0x08 #define BUS_SPACE_UNRESTRICTED (~0) #define BUS_SPACE_BARRIER_READ 0x01 #define BUS_SPACE_BARRIER_WRITE 0x02 struct bus_space { /* cookie */ void *bs_cookie; /* mapping/unmapping */ int (*bs_map) (void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); void (*bs_unmap) (void *, bus_space_handle_t, bus_size_t); int (*bs_subregion) (void *, bus_space_handle_t, bus_size_t, bus_size_t, bus_space_handle_t *); /* allocation/deallocation */ int (*bs_alloc) (void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *); void (*bs_free) (void *, bus_space_handle_t, bus_size_t); /* get kernel virtual address */ /* barrier */ void (*bs_barrier) (void *, bus_space_handle_t, bus_size_t, bus_size_t, int); /* read single */ u_int8_t (*bs_r_1) (void *, bus_space_handle_t, bus_size_t); u_int16_t (*bs_r_2) (void *, bus_space_handle_t, bus_size_t); u_int32_t (*bs_r_4) (void *, bus_space_handle_t, bus_size_t); u_int64_t (*bs_r_8) (void *, bus_space_handle_t, bus_size_t); /* read multiple */ void (*bs_rm_1) (void *, bus_space_handle_t, bus_size_t, u_int8_t *, bus_size_t); void (*bs_rm_2) (void *, bus_space_handle_t, bus_size_t, u_int16_t *, bus_size_t); void (*bs_rm_4) (void *, bus_space_handle_t, bus_size_t, u_int32_t *, bus_size_t); void (*bs_rm_8) (void *, bus_space_handle_t, bus_size_t, u_int64_t *, bus_size_t); /* read region */ void (*bs_rr_1) (void *, bus_space_handle_t, bus_size_t, u_int8_t *, bus_size_t); void (*bs_rr_2) (void *, bus_space_handle_t, bus_size_t, u_int16_t *, bus_size_t); void (*bs_rr_4) (void *, bus_space_handle_t, bus_size_t, u_int32_t *, bus_size_t); void (*bs_rr_8) (void *, bus_space_handle_t, bus_size_t, u_int64_t *, bus_size_t); /* write single */ void (*bs_w_1) (void *, bus_space_handle_t, bus_size_t, u_int8_t); void (*bs_w_2) (void *, bus_space_handle_t, bus_size_t, u_int16_t); void (*bs_w_4) (void *, bus_space_handle_t, bus_size_t, u_int32_t); void (*bs_w_8) (void *, bus_space_handle_t, bus_size_t, u_int64_t); /* write multiple */ void (*bs_wm_1) (void *, bus_space_handle_t, bus_size_t, const u_int8_t *, bus_size_t); void (*bs_wm_2) (void *, bus_space_handle_t, bus_size_t, const u_int16_t *, bus_size_t); void (*bs_wm_4) (void *, bus_space_handle_t, bus_size_t, const u_int32_t *, bus_size_t); void (*bs_wm_8) (void *, bus_space_handle_t, bus_size_t, const u_int64_t *, bus_size_t); /* write region */ void (*bs_wr_1) (void *, bus_space_handle_t, bus_size_t, const u_int8_t *, bus_size_t); void (*bs_wr_2) (void *, bus_space_handle_t, bus_size_t, const u_int16_t *, bus_size_t); void (*bs_wr_4) (void *, bus_space_handle_t, bus_size_t, const u_int32_t *, bus_size_t); void (*bs_wr_8) (void *, bus_space_handle_t, bus_size_t, const u_int64_t *, bus_size_t); /* set multiple */ void (*bs_sm_1) (void *, bus_space_handle_t, bus_size_t, u_int8_t, bus_size_t); void (*bs_sm_2) (void *, bus_space_handle_t, bus_size_t, u_int16_t, bus_size_t); void (*bs_sm_4) (void *, bus_space_handle_t, bus_size_t, u_int32_t, bus_size_t); void (*bs_sm_8) (void *, bus_space_handle_t, bus_size_t, u_int64_t, bus_size_t); /* set region */ void (*bs_sr_1) (void *, bus_space_handle_t, bus_size_t, u_int8_t, bus_size_t); void (*bs_sr_2) (void *, bus_space_handle_t, bus_size_t, u_int16_t, bus_size_t); void (*bs_sr_4) (void *, bus_space_handle_t, bus_size_t, u_int32_t, bus_size_t); void (*bs_sr_8) (void *, bus_space_handle_t, bus_size_t, u_int64_t, bus_size_t); /* copy */ void (*bs_c_1) (void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); void (*bs_c_2) (void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); void (*bs_c_4) (void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); void (*bs_c_8) (void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); /* read single stream */ u_int8_t (*bs_r_1_s) (void *, bus_space_handle_t, bus_size_t); u_int16_t (*bs_r_2_s) (void *, bus_space_handle_t, bus_size_t); u_int32_t (*bs_r_4_s) (void *, bus_space_handle_t, bus_size_t); u_int64_t (*bs_r_8_s) (void *, bus_space_handle_t, bus_size_t); /* read multiple stream */ void (*bs_rm_1_s) (void *, bus_space_handle_t, bus_size_t, u_int8_t *, bus_size_t); void (*bs_rm_2_s) (void *, bus_space_handle_t, bus_size_t, u_int16_t *, bus_size_t); void (*bs_rm_4_s) (void *, bus_space_handle_t, bus_size_t, u_int32_t *, bus_size_t); void (*bs_rm_8_s) (void *, bus_space_handle_t, bus_size_t, u_int64_t *, bus_size_t); /* read region stream */ void (*bs_rr_1_s) (void *, bus_space_handle_t, bus_size_t, u_int8_t *, bus_size_t); void (*bs_rr_2_s) (void *, bus_space_handle_t, bus_size_t, u_int16_t *, bus_size_t); void (*bs_rr_4_s) (void *, bus_space_handle_t, bus_size_t, u_int32_t *, bus_size_t); void (*bs_rr_8_s) (void *, bus_space_handle_t, bus_size_t, u_int64_t *, bus_size_t); /* write single stream */ void (*bs_w_1_s) (void *, bus_space_handle_t, bus_size_t, u_int8_t); void (*bs_w_2_s) (void *, bus_space_handle_t, bus_size_t, u_int16_t); void (*bs_w_4_s) (void *, bus_space_handle_t, bus_size_t, u_int32_t); void (*bs_w_8_s) (void *, bus_space_handle_t, bus_size_t, u_int64_t); /* write multiple stream */ void (*bs_wm_1_s) (void *, bus_space_handle_t, bus_size_t, const u_int8_t *, bus_size_t); void (*bs_wm_2_s) (void *, bus_space_handle_t, bus_size_t, const u_int16_t *, bus_size_t); void (*bs_wm_4_s) (void *, bus_space_handle_t, bus_size_t, const u_int32_t *, bus_size_t); void (*bs_wm_8_s) (void *, bus_space_handle_t, bus_size_t, const u_int64_t *, bus_size_t); /* write region stream */ void (*bs_wr_1_s) (void *, bus_space_handle_t, bus_size_t, const u_int8_t *, bus_size_t); void (*bs_wr_2_s) (void *, bus_space_handle_t, bus_size_t, const u_int16_t *, bus_size_t); void (*bs_wr_4_s) (void *, bus_space_handle_t, bus_size_t, const u_int32_t *, bus_size_t); void (*bs_wr_8_s) (void *, bus_space_handle_t, bus_size_t, const u_int64_t *, bus_size_t); /* peek */ int (*bs_peek_1)(void *, bus_space_handle_t, bus_size_t , uint8_t *); int (*bs_peek_2)(void *, bus_space_handle_t, bus_size_t , uint16_t *); int (*bs_peek_4)(void *, bus_space_handle_t, bus_size_t , uint32_t *); int (*bs_peek_8)(void *, bus_space_handle_t, bus_size_t , uint64_t *); /* poke */ int (*bs_poke_1)(void *, bus_space_handle_t, bus_size_t, uint8_t); int (*bs_poke_2)(void *, bus_space_handle_t, bus_size_t, uint16_t); int (*bs_poke_4)(void *, bus_space_handle_t, bus_size_t, uint32_t); int (*bs_poke_8)(void *, bus_space_handle_t, bus_size_t, uint64_t); }; #if defined(SAN_NEEDS_INTERCEPTORS) && !defined(SAN_RUNTIME) #include #else /* * Utility macros; INTERNAL USE ONLY. */ #define __bs_c(a,b) __CONCAT(a,b) #define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size) #define __bs_rs(sz, t, h, o) \ (*(t)->__bs_opname(r,sz))((t)->bs_cookie, h, o) #define __bs_ws(sz, t, h, o, v) \ (*(t)->__bs_opname(w,sz))((t)->bs_cookie, h, o, v) #define __bs_nonsingle(type, sz, t, h, o, a, c) \ (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, a, c) #define __bs_set(type, sz, t, h, o, v, c) \ (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, v, c) #define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \ (*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt) #define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s) #define __bs_rs_s(sz, t, h, o) \ (*(t)->__bs_opname_s(r,sz))((t)->bs_cookie, h, o) #define __bs_ws_s(sz, t, h, o, v) \ (*(t)->__bs_opname_s(w,sz))((t)->bs_cookie, h, o, v) #define __bs_peek(sz, t, h, o, vp) \ (*(t)->__bs_opname(peek, sz))((t)->bs_cookie, h, o, vp) #define __bs_poke(sz, t, h, o, v) \ (*(t)->__bs_opname(poke, sz))((t)->bs_cookie, h, o, v) #define __bs_nonsingle_s(type, sz, t, h, o, a, c) \ (*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c) /* * Mapping and unmapping operations. */ #define bus_space_map(t, a, s, c, hp) \ (*(t)->bs_map)((t)->bs_cookie, (a), (s), (c), (hp)) #define bus_space_unmap(t, h, s) \ (*(t)->bs_unmap)((t)->bs_cookie, (h), (s)) #define bus_space_subregion(t, h, o, s, hp) \ (*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp)) /* * Allocation and deallocation operations. */ #define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \ (*(t)->bs_alloc)((t)->bs_cookie, (rs), (re), (s), (a), (b), \ (c), (ap), (hp)) #define bus_space_free(t, h, s) \ (*(t)->bs_free)((t)->bs_cookie, (h), (s)) /* * Bus barrier operations. */ #define bus_space_barrier(t, h, o, l, f) \ (*(t)->bs_barrier)((t)->bs_cookie, (h), (o), (l), (f)) /* * Bus read (single) operations. */ #define bus_space_read_1(t, h, o) __bs_rs(1,(t),(h),(o)) #define bus_space_read_2(t, h, o) __bs_rs(2,(t),(h),(o)) #define bus_space_read_4(t, h, o) __bs_rs(4,(t),(h),(o)) #define bus_space_read_8(t, h, o) __bs_rs(8,(t),(h),(o)) #define bus_space_read_stream_1(t, h, o) __bs_rs_s(1,(t), (h), (o)) #define bus_space_read_stream_2(t, h, o) __bs_rs_s(2,(t), (h), (o)) #define bus_space_read_stream_4(t, h, o) __bs_rs_s(4,(t), (h), (o)) #define bus_space_read_stream_8(t, h, o) __bs_rs_s(8,(t), (h), (o)) /* * Bus read multiple operations. */ #define bus_space_read_multi_1(t, h, o, a, c) \ __bs_nonsingle(rm,1,(t),(h),(o),(a),(c)) #define bus_space_read_multi_2(t, h, o, a, c) \ __bs_nonsingle(rm,2,(t),(h),(o),(a),(c)) #define bus_space_read_multi_4(t, h, o, a, c) \ __bs_nonsingle(rm,4,(t),(h),(o),(a),(c)) #define bus_space_read_multi_8(t, h, o, a, c) \ __bs_nonsingle(rm,8,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c)) /* * Bus read region operations. */ #define bus_space_read_region_1(t, h, o, a, c) \ __bs_nonsingle(rr,1,(t),(h),(o),(a),(c)) #define bus_space_read_region_2(t, h, o, a, c) \ __bs_nonsingle(rr,2,(t),(h),(o),(a),(c)) #define bus_space_read_region_4(t, h, o, a, c) \ __bs_nonsingle(rr,4,(t),(h),(o),(a),(c)) #define bus_space_read_region_8(t, h, o, a, c) \ __bs_nonsingle(rr,8,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c)) /* * Bus write (single) operations. */ #define bus_space_write_1(t, h, o, v) __bs_ws(1,(t),(h),(o),(v)) #define bus_space_write_2(t, h, o, v) __bs_ws(2,(t),(h),(o),(v)) #define bus_space_write_4(t, h, o, v) __bs_ws(4,(t),(h),(o),(v)) #define bus_space_write_8(t, h, o, v) __bs_ws(8,(t),(h),(o),(v)) #define bus_space_write_stream_1(t, h, o, v) __bs_ws_s(1,(t),(h),(o),(v)) #define bus_space_write_stream_2(t, h, o, v) __bs_ws_s(2,(t),(h),(o),(v)) #define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v)) #define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v)) /* * Bus write multiple operations. */ #define bus_space_write_multi_1(t, h, o, a, c) \ __bs_nonsingle(wm,1,(t),(h),(o),(a),(c)) #define bus_space_write_multi_2(t, h, o, a, c) \ __bs_nonsingle(wm,2,(t),(h),(o),(a),(c)) #define bus_space_write_multi_4(t, h, o, a, c) \ __bs_nonsingle(wm,4,(t),(h),(o),(a),(c)) #define bus_space_write_multi_8(t, h, o, a, c) \ __bs_nonsingle(wm,8,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c)) /* * Bus write region operations. */ #define bus_space_write_region_1(t, h, o, a, c) \ __bs_nonsingle(wr,1,(t),(h),(o),(a),(c)) #define bus_space_write_region_2(t, h, o, a, c) \ __bs_nonsingle(wr,2,(t),(h),(o),(a),(c)) #define bus_space_write_region_4(t, h, o, a, c) \ __bs_nonsingle(wr,4,(t),(h),(o),(a),(c)) #define bus_space_write_region_8(t, h, o, a, c) \ __bs_nonsingle(wr,8,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c)) /* * Set multiple operations. */ #define bus_space_set_multi_1(t, h, o, v, c) \ __bs_set(sm,1,(t),(h),(o),(v),(c)) #define bus_space_set_multi_2(t, h, o, v, c) \ __bs_set(sm,2,(t),(h),(o),(v),(c)) #define bus_space_set_multi_4(t, h, o, v, c) \ __bs_set(sm,4,(t),(h),(o),(v),(c)) #define bus_space_set_multi_8(t, h, o, v, c) \ __bs_set(sm,8,(t),(h),(o),(v),(c)) #define bus_space_set_multi_stream_1(t, h, o, v, c) \ bus_space_set_multi_1((t), (h), (o), (v), (c)) #define bus_space_set_multi_stream_2(t, h, o, v, c) \ bus_space_set_multi_2((t), (h), (o), (v), (c)) #define bus_space_set_multi_stream_4(t, h, o, v, c) \ bus_space_set_multi_4((t), (h), (o), (v), (c)) #define bus_space_set_multi_stream_8(t, h, o, v, c) \ bus_space_set_multi_8((t), (h), (o), (v), (c)) /* * Set region operations. */ #define bus_space_set_region_1(t, h, o, v, c) \ __bs_set(sr,1,(t),(h),(o),(v),(c)) #define bus_space_set_region_2(t, h, o, v, c) \ __bs_set(sr,2,(t),(h),(o),(v),(c)) #define bus_space_set_region_4(t, h, o, v, c) \ __bs_set(sr,4,(t),(h),(o),(v),(c)) #define bus_space_set_region_8(t, h, o, v, c) \ __bs_set(sr,8,(t),(h),(o),(v),(c)) #define bus_space_set_region_stream_1(t, h, o, v, c) \ bus_space_set_region_1((t), (h), (o), (v), (c)) #define bus_space_set_region_stream_2(t, h, o, v, c) \ bus_space_set_region_2((t), (h), (o), (v), (c)) #define bus_space_set_region_stream_4(t, h, o, v, c) \ bus_space_set_region_4((t), (h), (o), (v), (c)) #define bus_space_set_region_stream_8(t, h, o, v, c) \ bus_space_set_region_8((t), (h), (o), (v), (c)) /* * Copy operations. */ #define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ __bs_copy(1, t, h1, o1, h2, o2, c) #define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ __bs_copy(2, t, h1, o1, h2, o2, c) #define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ __bs_copy(4, t, h1, o1, h2, o2, c) #define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \ __bs_copy(8, t, h1, o1, h2, o2, c) /* * Poke (checked write) operations. */ #define bus_space_poke_1(t, h, o, v) __bs_poke(1, (t), (h), (o), (v)) #define bus_space_poke_2(t, h, o, v) __bs_poke(2, (t), (h), (o), (v)) #define bus_space_poke_4(t, h, o, v) __bs_poke(4, (t), (h), (o), (v)) #define bus_space_poke_8(t, h, o, v) __bs_poke(8, (t), (h), (o), (v)) /* * Peek (checked read) operations. */ #define bus_space_peek_1(t, h, o, vp) __bs_peek(1, (t), (h), (o), (vp)) #define bus_space_peek_2(t, h, o, vp) __bs_peek(2, (t), (h), (o), (vp)) #define bus_space_peek_4(t, h, o, vp) __bs_peek(4, (t), (h), (o), (vp)) #define bus_space_peek_8(t, h, o, vp) __bs_peek(8, (t), (h), (o), (vp)) #endif /* !SAN_NEEDS_INTERCEPTORS */ #include #endif /* _MACHINE_BUS_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/counter.h b/sys/arm64/include/counter.h index 7f747b525d9c..513f67ac7f90 100644 --- a/sys/arm64/include/counter.h +++ b/sys/arm64/include/counter.h @@ -1,87 +1,93 @@ /*- * Copyright (c) 2012 Konstantin Belousov * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_COUNTER_H_ #define _MACHINE_COUNTER_H_ #include #include #define EARLY_COUNTER &pcpu0.pc_early_dummy_counter #define counter_enter() do {} while (0) #define counter_exit() do {} while (0) #ifdef IN_SUBR_COUNTER_C static inline uint64_t counter_u64_read_one(uint64_t *p, int cpu) { return (*(uint64_t *)((char *)p + UMA_PCPU_ALLOC_SIZE * cpu)); } static inline uint64_t counter_u64_fetch_inline(uint64_t *p) { uint64_t r; int i; r = 0; CPU_FOREACH(i) r += counter_u64_read_one((uint64_t *)p, i); return (r); } static void counter_u64_zero_one_cpu(void *arg) { *((uint64_t *)((char *)arg + UMA_PCPU_ALLOC_SIZE * PCPU_GET(cpuid))) = 0; } static inline void counter_u64_zero_inline(counter_u64_t c) { smp_rendezvous(smp_no_rendezvous_barrier, counter_u64_zero_one_cpu, smp_no_rendezvous_barrier, c); } #endif #define counter_u64_add_protected(c, inc) counter_u64_add(c, inc) static inline void counter_u64_add(counter_u64_t c, int64_t inc) { atomic_add_64((uint64_t *)zpcpu_get(c), inc); } #endif /* ! _MACHINE_COUNTER_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/cpu.h b/sys/arm64/include/cpu.h index 0bb320f2e0a0..6d83ef25793c 100644 --- a/sys/arm64/include/cpu.h +++ b/sys/arm64/include/cpu.h @@ -1,255 +1,261 @@ /*- * Copyright (c) 1990 The Regents of the University of California. * Copyright (c) 2014-2016 The FreeBSD Foundation * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Portions of this software were developed by Andrew Turner * under sponsorship from the FreeBSD Foundation * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)cpu.h 5.4 (Berkeley) 5/9/91 * from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_CPU_H_ #define _MACHINE_CPU_H_ #include #include #include #define TRAPF_PC(tfp) ((tfp)->tf_elr) #define TRAPF_USERMODE(tfp) (((tfp)->tf_spsr & PSR_M_MASK) == PSR_M_EL0t) #define cpu_getstack(td) ((td)->td_frame->tf_sp) #define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) #define cpu_spinwait() __asm __volatile("yield" ::: "memory") #define cpu_lock_delay() DELAY(1) /* Extract CPU affinity levels 0-3 */ #define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff) #define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff) #define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff) #define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff) #define CPU_AFF0_MASK 0xffUL #define CPU_AFF1_MASK 0xff00UL #define CPU_AFF2_MASK 0xff0000UL #define CPU_AFF3_MASK 0xff00000000UL #define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \ CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */ #ifdef _KERNEL #define CPU_IMPL_ARM 0x41 #define CPU_IMPL_BROADCOM 0x42 #define CPU_IMPL_CAVIUM 0x43 #define CPU_IMPL_DEC 0x44 #define CPU_IMPL_FUJITSU 0x46 #define CPU_IMPL_INFINEON 0x49 #define CPU_IMPL_FREESCALE 0x4D #define CPU_IMPL_NVIDIA 0x4E #define CPU_IMPL_APM 0x50 #define CPU_IMPL_QUALCOMM 0x51 #define CPU_IMPL_MARVELL 0x56 #define CPU_IMPL_APPLE 0x61 #define CPU_IMPL_INTEL 0x69 #define CPU_IMPL_AMPERE 0xC0 /* ARM Part numbers */ #define CPU_PART_FOUNDATION 0xD00 #define CPU_PART_CORTEX_A34 0xD02 #define CPU_PART_CORTEX_A53 0xD03 #define CPU_PART_CORTEX_A35 0xD04 #define CPU_PART_CORTEX_A55 0xD05 #define CPU_PART_CORTEX_A65 0xD06 #define CPU_PART_CORTEX_A57 0xD07 #define CPU_PART_CORTEX_A72 0xD08 #define CPU_PART_CORTEX_A73 0xD09 #define CPU_PART_CORTEX_A75 0xD0A #define CPU_PART_CORTEX_A76 0xD0B #define CPU_PART_NEOVERSE_N1 0xD0C #define CPU_PART_CORTEX_A77 0xD0D #define CPU_PART_CORTEX_A76AE 0xD0E #define CPU_PART_AEM_V8 0xD0F #define CPU_PART_NEOVERSE_V1 0xD40 #define CPU_PART_CORTEX_A78 0xD41 #define CPU_PART_CORTEX_A65AE 0xD43 #define CPU_PART_CORTEX_X1 0xD44 #define CPU_PART_CORTEX_A510 0xD46 #define CPU_PART_CORTEX_A710 0xD47 #define CPU_PART_CORTEX_X2 0xD48 #define CPU_PART_NEOVERSE_N2 0xD49 #define CPU_PART_NEOVERSE_E1 0xD4A #define CPU_PART_CORTEX_A78C 0xD4B #define CPU_PART_CORTEX_X1C 0xD4C #define CPU_PART_CORTEX_A715 0xD4D #define CPU_PART_CORTEX_X3 0xD4E #define CPU_PART_NEOVERSE_V2 0xD4F /* Cavium Part numbers */ #define CPU_PART_THUNDERX 0x0A1 #define CPU_PART_THUNDERX_81XX 0x0A2 #define CPU_PART_THUNDERX_83XX 0x0A3 #define CPU_PART_THUNDERX2 0x0AF #define CPU_REV_THUNDERX_1_0 0x00 #define CPU_REV_THUNDERX_1_1 0x01 #define CPU_REV_THUNDERX2_0 0x00 /* APM / Ampere Part Number */ #define CPU_PART_EMAG8180 0x000 /* Qualcomm */ #define CPU_PART_KRYO400_GOLD 0x804 #define CPU_PART_KRYO400_SILVER 0x805 #define CPU_IMPL(midr) (((midr) >> 24) & 0xff) #define CPU_PART(midr) (((midr) >> 4) & 0xfff) #define CPU_VAR(midr) (((midr) >> 20) & 0xf) #define CPU_ARCH(midr) (((midr) >> 16) & 0xf) #define CPU_REV(midr) (((midr) >> 0) & 0xf) #define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24) #define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4) #define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20) #define CPU_ARCH_TO_MIDR(val) (((val) & 0xf) << 16) #define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0) #define CPU_IMPL_MASK (0xff << 24) #define CPU_PART_MASK (0xfff << 4) #define CPU_VAR_MASK (0xf << 20) #define CPU_ARCH_MASK (0xf << 16) #define CPU_REV_MASK (0xf << 0) #define CPU_ID_RAW(impl, part, var, rev) \ (CPU_IMPL_TO_MIDR((impl)) | \ CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \ CPU_REV_TO_MIDR((rev))) #define CPU_MATCH(mask, impl, part, var, rev) \ (((mask) & PCPU_GET(midr)) == \ ((mask) & CPU_ID_RAW((impl), (part), (var), (rev)))) #define CPU_MATCH_RAW(mask, devid) \ (((mask) & PCPU_GET(midr)) == ((mask) & (devid))) /* * Chip-specific errata. This defines are intended to be * booleans used within if statements. When an appropriate * kernel option is disabled, these defines must be defined * as 0 to allow the compiler to remove a dead code thus * produce better optimized kernel image. */ /* * Vendor: Cavium * Chip: ThunderX * Revision(s): Pass 1.0, Pass 1.1 */ #ifdef THUNDERX_PASS_1_1_ERRATA #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \ (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \ CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1)) #else #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0 #endif extern char btext[]; extern char etext[]; extern uint64_t __cpu_affinity[]; struct arm64_addr_mask; extern struct arm64_addr_mask elf64_addr_mask; void cpu_halt(void) __dead2; void cpu_reset(void) __dead2; void fork_trampoline(void); void identify_cache(uint64_t); void identify_cpu(u_int); void install_cpu_errata(void); /* Pointer Authentication Code (PAC) support */ void ptrauth_init(void); void ptrauth_fork(struct thread *, struct thread *); void ptrauth_exec(struct thread *); void ptrauth_copy_thread(struct thread *, struct thread *); void ptrauth_thread_alloc(struct thread *); void ptrauth_thread0(struct thread *); #ifdef SMP void ptrauth_mp_start(uint64_t); #endif /* Functions to read the sanitised view of the special registers */ void update_special_regs(u_int); bool extract_user_id_field(u_int, u_int, uint8_t *); bool get_kernel_reg(u_int, uint64_t *); bool get_kernel_reg_masked(u_int, uint64_t *, uint64_t); void cpu_desc_init(void); #define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)] #define CPU_CURRENT_SOCKET \ (CPU_AFF2(CPU_AFFINITY(PCPU_GET(cpuid)))) static __inline uint64_t get_cyclecount(void) { uint64_t ret; ret = READ_SPECIALREG(cntvct_el0); return (ret); } #define ADDRESS_TRANSLATE_FUNC(stage) \ static inline uint64_t \ arm64_address_translate_ ##stage (uint64_t addr) \ { \ uint64_t ret; \ \ __asm __volatile( \ "at " __STRING(stage) ", %1 \n" \ "isb \n" \ "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \ \ return (ret); \ } ADDRESS_TRANSLATE_FUNC(s1e0r) ADDRESS_TRANSLATE_FUNC(s1e0w) ADDRESS_TRANSLATE_FUNC(s1e1r) ADDRESS_TRANSLATE_FUNC(s1e1w) #endif #endif /* !_MACHINE_CPU_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/cpufunc.h b/sys/arm64/include/cpufunc.h index f2de8a0e560c..b2ec5672aeb8 100644 --- a/sys/arm64/include/cpufunc.h +++ b/sys/arm64/include/cpufunc.h @@ -1,195 +1,201 @@ /*- * Copyright (c) 2014 Andrew Turner * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_CPUFUNC_H_ #define _MACHINE_CPUFUNC_H_ static __inline void breakpoint(void) { __asm("brk #0"); } #ifdef _KERNEL #include void pan_enable(void); static __inline register_t dbg_disable(void) { uint32_t ret; __asm __volatile( "mrs %x0, daif \n" "msr daifset, #(" __XSTRING(DAIF_D) ") \n" : "=&r" (ret)); return (ret); } static __inline void dbg_enable(void) { __asm __volatile("msr daifclr, #(" __XSTRING(DAIF_D) ")"); } static __inline register_t intr_disable(void) { /* DAIF is a 32-bit register */ uint32_t ret; __asm __volatile( "mrs %x0, daif \n" "msr daifset, #(" __XSTRING(DAIF_INTR) ") \n" : "=&r" (ret)); return (ret); } static __inline void intr_restore(register_t s) { WRITE_SPECIALREG(daif, s); } static __inline void intr_enable(void) { __asm __volatile("msr daifclr, #(" __XSTRING(DAIF_INTR) ")"); } static __inline void serror_enable(void) { __asm __volatile("msr daifclr, #(" __XSTRING(DAIF_A) ")"); } static __inline register_t get_midr(void) { uint64_t midr; midr = READ_SPECIALREG(midr_el1); return (midr); } static __inline register_t get_mpidr(void) { uint64_t mpidr; mpidr = READ_SPECIALREG(mpidr_el1); return (mpidr); } static __inline void clrex(void) { /* * Ensure compiler barrier, otherwise the monitor clear might * occur too late for us ? */ __asm __volatile("clrex" : : : "memory"); } static __inline void set_ttbr0(uint64_t ttbr0) { __asm __volatile( "msr ttbr0_el1, %0 \n" "isb \n" : : "r" (ttbr0)); } static __inline void invalidate_icache(void) { __asm __volatile( "ic ialluis \n" "dsb ish \n" "isb \n"); } static __inline void invalidate_local_icache(void) { __asm __volatile( "ic iallu \n" "dsb nsh \n" "isb \n"); } extern bool icache_aliasing; extern bool icache_vmid; extern int64_t dcache_line_size; extern int64_t icache_line_size; extern int64_t idcache_line_size; extern int64_t dczva_line_size; #define cpu_nullop() arm64_nullop() #define cpufunc_nullop() arm64_nullop() #define cpu_tlb_flushID() arm64_tlb_flushID() #define cpu_dcache_wbinv_range(a, s) arm64_dcache_wbinv_range((a), (s)) #define cpu_dcache_inv_range(a, s) arm64_dcache_inv_range((a), (s)) #define cpu_dcache_wb_range(a, s) arm64_dcache_wb_range((a), (s)) extern void (*arm64_icache_sync_range)(vm_offset_t, vm_size_t); #define cpu_icache_sync_range(a, s) arm64_icache_sync_range((a), (s)) #define cpu_icache_sync_range_checked(a, s) arm64_icache_sync_range_checked((a), (s)) void arm64_nullop(void); void arm64_tlb_flushID(void); void arm64_dic_idc_icache_sync_range(vm_offset_t, vm_size_t); void arm64_idc_aliasing_icache_sync_range(vm_offset_t, vm_size_t); void arm64_aliasing_icache_sync_range(vm_offset_t, vm_size_t); int arm64_icache_sync_range_checked(vm_offset_t, vm_size_t); void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t); void arm64_dcache_inv_range(vm_offset_t, vm_size_t); void arm64_dcache_wb_range(vm_offset_t, vm_size_t); bool arm64_get_writable_addr(vm_offset_t, vm_offset_t *); #endif /* _KERNEL */ #endif /* _MACHINE_CPUFUNC_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/cpuinfo.h b/sys/arm64/include/cpuinfo.h new file mode 100644 index 000000000000..004f611ccf80 --- /dev/null +++ b/sys/arm64/include/cpuinfo.h @@ -0,0 +1,5 @@ +#ifdef __arm__ +#include +#else /* !__arm__ */ +#error Do not include this header, used only for 32-bit compatibility +#endif /* !__arm__ */ diff --git a/sys/arm64/include/efi.h b/sys/arm64/include/efi.h index 6db16e5b8291..3494c547362d 100644 --- a/sys/arm64/include/efi.h +++ b/sys/arm64/include/efi.h @@ -1,60 +1,66 @@ /*- * Copyright (c) 2017 Andrew Turner * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef __ARM64_INCLUDE_EFI_H_ #define __ARM64_INCLUDE_EFI_H_ #define EFIABI_ATTR #ifdef _KERNEL #define ARCH_MAY_USE_EFI #define EFI_TIME_LOCK() #define EFI_TIME_UNLOCK() #define EFI_TIME_OWNED() #define EFI_RT_HANDLE_FAULTS_DEFAULT 0 #endif struct efirt_callinfo { const char *ec_name; register_t ec_efi_status; register_t ec_fptr; register_t ec_argcnt; register_t ec_arg1; register_t ec_arg2; register_t ec_arg3; register_t ec_arg4; register_t ec_arg5; }; #endif /* __ARM64_INCLUDE_EFI_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/elf.h b/sys/arm64/include/elf.h index 22e968c632bf..0399392b8fb6 100644 --- a/sys/arm64/include/elf.h +++ b/sys/arm64/include/elf.h @@ -1,182 +1,188 @@ /*- * Copyright (c) 1996-1997 John D. Polstra. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_ELF_H_ #define _MACHINE_ELF_H_ /* * ELF definitions for the AArch64 architecture. */ #include /* Definitions common to all 32 bit architectures. */ #include /* Definitions common to all 64 bit architectures. */ #ifndef __ELF_WORD_SIZE #define __ELF_WORD_SIZE 64 /* Used by */ #endif #include /* * Auxiliary vector entries for passing information to the interpreter. */ typedef struct { /* Auxiliary vector entry on initial stack */ int a_type; /* Entry type. */ union { int a_val; /* Integer value. */ } a_un; } Elf32_Auxinfo; typedef struct { /* Auxiliary vector entry on initial stack */ long a_type; /* Entry type. */ union { long a_val; /* Integer value. */ void *a_ptr; /* Address. */ void (*a_fcn)(void); /* Function pointer (not used). */ } a_un; } Elf64_Auxinfo; __ElfType(Auxinfo); #ifdef _MACHINE_ELF_WANT_32BIT #define ELF_ARCH EM_ARM #else #define ELF_ARCH EM_AARCH64 #endif #define ELF_MACHINE_OK(x) ((x) == (ELF_ARCH)) /* Define "machine" characteristics */ #if __ELF_WORD_SIZE == 64 #define ELF_TARG_CLASS ELFCLASS64 #define ELF_TARG_DATA ELFDATA2LSB #define ELF_TARG_MACH EM_AARCH64 #define ELF_TARG_VER 1 #else #define ELF_TARG_CLASS ELFCLASS32 #define ELF_TARG_DATA ELFDATA2LSB #define ELF_TARG_MACH EM_ARM #define ELF_TARG_VER 1 #endif #if __ELF_WORD_SIZE == 32 #define ET_DYN_LOAD_ADDR 0x01001000 #else #define ET_DYN_LOAD_ADDR 0x100000 #endif /* HWCAP */ #define HWCAP_FP 0x00000001 #define HWCAP_ASIMD 0x00000002 #define HWCAP_EVTSTRM 0x00000004 #define HWCAP_AES 0x00000008 #define HWCAP_PMULL 0x00000010 #define HWCAP_SHA1 0x00000020 #define HWCAP_SHA2 0x00000040 #define HWCAP_CRC32 0x00000080 #define HWCAP_ATOMICS 0x00000100 #define HWCAP_FPHP 0x00000200 #define HWCAP_ASIMDHP 0x00000400 /* * XXX: The following bits (from CPUID to FLAGM) were originally incorrect, * but later changed to match the Linux definitions. No compatibility code is * provided, as the fix was expected to result in near-zero fallout. */ #define HWCAP_CPUID 0x00000800 #define HWCAP_ASIMDRDM 0x00001000 #define HWCAP_JSCVT 0x00002000 #define HWCAP_FCMA 0x00004000 #define HWCAP_LRCPC 0x00008000 #define HWCAP_DCPOP 0x00010000 #define HWCAP_SHA3 0x00020000 #define HWCAP_SM3 0x00040000 #define HWCAP_SM4 0x00080000 #define HWCAP_ASIMDDP 0x00100000 #define HWCAP_SHA512 0x00200000 #define HWCAP_SVE 0x00400000 #define HWCAP_ASIMDFHM 0x00800000 #define HWCAP_DIT 0x01000000 #define HWCAP_USCAT 0x02000000 #define HWCAP_ILRCPC 0x04000000 #define HWCAP_FLAGM 0x08000000 #define HWCAP_SSBS 0x10000000 #define HWCAP_SB 0x20000000 #define HWCAP_PACA 0x40000000 #define HWCAP_PACG 0x80000000 /* HWCAP2 */ #define HWCAP2_DCPODP 0x00000001 #define HWCAP2_SVE2 0x00000002 #define HWCAP2_SVEAES 0x00000004 #define HWCAP2_SVEPMULL 0x00000008 #define HWCAP2_SVEBITPERM 0x00000010 #define HWCAP2_SVESHA3 0x00000020 #define HWCAP2_SVESM4 0x00000040 #define HWCAP2_FLAGM2 0x00000080 #define HWCAP2_FRINT 0x00000100 #define HWCAP2_SVEI8MM 0x00000200 #define HWCAP2_SVEF32MM 0x00000400 #define HWCAP2_SVEF64MM 0x00000800 #define HWCAP2_SVEBF16 0x00001000 #define HWCAP2_I8MM 0x00002000 #define HWCAP2_BF16 0x00004000 #define HWCAP2_DGH 0x00008000 #define HWCAP2_RNG 0x00010000 #define HWCAP2_BTI 0x00020000 #ifdef COMPAT_FREEBSD32 /* ARM HWCAP */ #define HWCAP32_HALF 0x00000002 /* Always set. */ #define HWCAP32_THUMB 0x00000004 /* Always set. */ #define HWCAP32_FAST_MULT 0x00000010 /* Always set. */ #define HWCAP32_VFP 0x00000040 #define HWCAP32_EDSP 0x00000080 /* Always set. */ #define HWCAP32_NEON 0x00001000 #define HWCAP32_VFPv3 0x00002000 #define HWCAP32_TLS 0x00008000 /* Always set. */ #define HWCAP32_VFPv4 0x00010000 #define HWCAP32_IDIVA 0x00020000 /* Always set. */ #define HWCAP32_IDIVT 0x00040000 /* Always set. */ #define HWCAP32_VFPD32 0x00080000 /* Always set. */ #define HWCAP32_LPAE 0x00100000 /* Always set. */ #define HWCAP32_DEFAULT \ (HWCAP32_HALF | HWCAP32_THUMB | HWCAP32_FAST_MULT | HWCAP32_EDSP |\ HWCAP32_TLS | HWCAP32_IDIVA | HWCAP32_IDIVT | HWCAP32_VFPD32 | \ HWCAP32_LPAE) /* ARM HWCAP2 */ #define HWCAP32_2_AES 0x00000001 #define HWCAP32_2_PMULL 0x00000002 #define HWCAP32_2_SHA1 0x00000004 #define HWCAP32_2_SHA2 0x00000008 #define HWCAP32_2_CRC32 0x00000010 #endif #endif /* !_MACHINE_ELF_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/exec.h b/sys/arm64/include/exec.h index da23dbe43a4f..00b6fc25f3a2 100644 --- a/sys/arm64/include/exec.h +++ b/sys/arm64/include/exec.h @@ -1 +1,7 @@ /* $FreeBSD$ */ + +#ifdef __arm__ +#include +#else /* !__arm__ */ +/* empty */ +#endif /* !__arm__ */ diff --git a/sys/arm64/include/float.h b/sys/arm64/include/float.h index 0829f6f52aa9..0fe90637fda1 100644 --- a/sys/arm64/include/float.h +++ b/sys/arm64/include/float.h @@ -1,94 +1,100 @@ /*- * Copyright (c) 1989 Regents of the University of California. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)float.h 7.1 (Berkeley) 5/8/90 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_FLOAT_H_ #define _MACHINE_FLOAT_H_ #include __BEGIN_DECLS extern int __flt_rounds(void); __END_DECLS #define FLT_RADIX 2 /* b */ #define FLT_ROUNDS __flt_rounds() #if __ISO_C_VISIBLE >= 1999 #define FLT_EVAL_METHOD 0 #define DECIMAL_DIG 17 /* max precision in decimal digits */ #endif #define FLT_MANT_DIG 24 /* p */ #define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */ #define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ #define FLT_MIN_EXP (-125) /* emin */ #define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ #define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */ #define FLT_MAX_EXP 128 /* emax */ #define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ #define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ #if __ISO_C_VISIBLE >= 2011 #define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */ #define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */ #define FLT_HAS_SUBNORM 1 #endif /* __ISO_C_VISIBLE >= 2011 */ #define DBL_MANT_DIG 53 #define DBL_EPSILON 2.2204460492503131E-16 #define DBL_DIG 15 #define DBL_MIN_EXP (-1021) #define DBL_MIN 2.2250738585072014E-308 #define DBL_MIN_10_EXP (-307) #define DBL_MAX_EXP 1024 #define DBL_MAX 1.7976931348623157E+308 #define DBL_MAX_10_EXP 308 #if __ISO_C_VISIBLE >= 2011 #define DBL_TRUE_MIN 4.9406564584124654E-324 #define DBL_DECIMAL_DIG 17 #define DBL_HAS_SUBNORM 1 #endif /* __ISO_C_VISIBLE >= 2011 */ #define LDBL_MANT_DIG 113 #define LDBL_EPSILON 1.925929944387235853055977942584927319E-34L #define LDBL_DIG 33 #define LDBL_MIN_EXP (-16381) #define LDBL_MIN 3.362103143112093506262677817321752603E-4932L #define LDBL_MIN_10_EXP (-4931) #define LDBL_MAX_EXP (+16384) #define LDBL_MAX 1.189731495357231765085759326628007016E+4932L #define LDBL_MAX_10_EXP (+4932) #if __ISO_C_VISIBLE >= 2011 #define LDBL_TRUE_MIN 6.475175119438025110924438958227646552E-4966L #define LDBL_DECIMAL_DIG 36 #define LDBL_HAS_SUBNORM 1 #endif /* __ISO_C_VISIBLE >= 2011 */ #endif /* _MACHINE_FLOAT_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/frame.h b/sys/arm64/include/frame.h index c838193bee9e..7a841ff160f1 100644 --- a/sys/arm64/include/frame.h +++ b/sys/arm64/include/frame.h @@ -1,79 +1,85 @@ /*- * Copyright (c) 2014 Andrew Turner * Copyright (c) 2014 The FreeBSD Foundation * All rights reserved. * * This software was developed by Andrew Turner under * sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_FRAME_H_ #define _MACHINE_FRAME_H_ #ifndef LOCORE #include #include /* * NOTE: keep this structure in sync with struct reg and struct mcontext. */ struct trapframe { uint64_t tf_sp; uint64_t tf_lr; uint64_t tf_elr; uint64_t tf_spsr; uint64_t tf_esr; uint64_t tf_far; uint64_t tf_x[30]; }; /* * Signal frame, pushed onto the user stack. */ struct sigframe { siginfo_t sf_si; /* actual saved siginfo */ ucontext_t sf_uc; /* actual saved ucontext */ }; /* * There is no fixed frame layout, other than to be 16-byte aligned. */ struct frame { int dummy; }; #ifdef COMPAT_FREEBSD32 struct sigframe32 { struct siginfo32 sf_si; ucontext32_t sf_uc; mcontext32_vfp_t sf_vfp; }; #endif /* COMPAT_FREEBSD32 */ #endif /* !LOCORE */ #endif /* !_MACHINE_FRAME_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/ieeefp.h b/sys/arm64/include/ieeefp.h index 178721a65b1e..8c7166741c0c 100644 --- a/sys/arm64/include/ieeefp.h +++ b/sys/arm64/include/ieeefp.h @@ -1,43 +1,49 @@ /*- * Based on sys/sparc64/include/ieeefp.h * Public domain. * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_IEEEFP_H_ #define _MACHINE_IEEEFP_H_ /* Deprecated FPU control interface */ /* FP exception codes */ #define FP_EXCEPT_INV 8 #define FP_EXCEPT_DZ 9 #define FP_EXCEPT_OFL 10 #define FP_EXCEPT_UFL 11 #define FP_EXCEPT_IMP 12 #define FP_EXCEPT_DNML 15 typedef int fp_except_t; #define FP_X_INV (1 << FP_EXCEPT_INV) /* invalid operation exception */ #define FP_X_DZ (1 << FP_EXCEPT_DZ) /* divide-by-zero exception */ #define FP_X_OFL (1 << FP_EXCEPT_OFL) /* overflow exception */ #define FP_X_UFL (1 << FP_EXCEPT_UFL) /* underflow exception */ #define FP_X_IMP (1 << FP_EXCEPT_IMP) /* imprecise (loss of precision) */ #define FP_X_DNML (1 << FP_EXCEPT_DNML) /* denormal exception */ typedef enum { FP_RN = (0 << 22), /* round to nearest representable number */ FP_RP = (1 << 22), /* round toward positive infinity */ FP_RM = (2 << 22), /* round toward negative infinity */ FP_RZ = (3 << 22) /* round to zero (truncate) */ } fp_rnd_t; __BEGIN_DECLS extern fp_rnd_t fpgetround(void); extern fp_rnd_t fpsetround(fp_rnd_t); extern fp_except_t fpgetmask(void); extern fp_except_t fpsetmask(fp_except_t); __END_DECLS #endif /* _MACHINE_IEEEFP_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/param.h b/sys/arm64/include/param.h index c94b797f8cca..a44fa3fcd9d2 100644 --- a/sys/arm64/include/param.h +++ b/sys/arm64/include/param.h @@ -1,132 +1,138 @@ /*- * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)param.h 5.8 (Berkeley) 6/28/91 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_PARAM_H_ #define _MACHINE_PARAM_H_ /* * Machine dependent constants for arm64. */ #include #define STACKALIGNBYTES (16 - 1) #define STACKALIGN(p) ((uint64_t)(p) & ~STACKALIGNBYTES) #define __PCI_REROUTE_INTERRUPT #ifndef MACHINE #define MACHINE "arm64" #endif #ifndef MACHINE_ARCH #define MACHINE_ARCH "aarch64" #endif #ifndef MACHINE_ARCH32 #define MACHINE_ARCH32 "armv7" #endif #ifdef SMP #ifndef MAXCPU #define MAXCPU 256 #endif #else #define MAXCPU 1 #endif #ifndef MAXMEMDOM #define MAXMEMDOM 8 #endif #define ALIGNBYTES _ALIGNBYTES #define ALIGN(p) _ALIGN(p) /* * ALIGNED_POINTER is a boolean macro that checks whether an address * is valid to fetch data elements of type t from on this architecture. * This does not reflect the optimal alignment, just the possibility * (within reasonable limits). */ #define ALIGNED_POINTER(p, t) ((((u_long)(p)) & (sizeof(t) - 1)) == 0) /* * CACHE_LINE_SIZE is the compile-time maximum cache line size for an * architecture. It should be used with appropriate caution. */ #define CACHE_LINE_SHIFT 7 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) #define PAGE_SHIFT_4K 12 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) #define PAGE_SHIFT_16K 14 #define PAGE_SIZE_16K (1 << PAGE_SHIFT_16K) #define PAGE_SHIFT_64K 16 #define PAGE_SIZE_64K (1 << PAGE_SHIFT_64K) #define PAGE_SHIFT PAGE_SHIFT_4K #define PAGE_SIZE (1 << PAGE_SHIFT) #define PAGE_MASK (PAGE_SIZE - 1) #define MAXPAGESIZES 3 /* maximum number of supported page sizes */ #ifndef KSTACK_PAGES #if defined(KASAN) || defined(KMSAN) #define KSTACK_PAGES 6 #else #define KSTACK_PAGES 4 /* pages of kernel stack (with pcb) */ #endif #endif #define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */ #define PCPU_PAGES 1 #ifdef PERTHREAD_SSP #define NO_PERTHREAD_SSP __nostackprotector #else #define NO_PERTHREAD_SSP #endif /* * Mach derived conversion macros */ #define round_page(x) (((unsigned long)(x) + PAGE_MASK) & ~PAGE_MASK) #define trunc_page(x) ((unsigned long)(x) & ~PAGE_MASK) #define atop(x) ((unsigned long)(x) >> PAGE_SHIFT) #define ptoa(x) ((unsigned long)(x) << PAGE_SHIFT) #define arm64_btop(x) ((unsigned long)(x) >> PAGE_SHIFT) #define arm64_ptob(x) ((unsigned long)(x) << PAGE_SHIFT) #define pgtok(x) ((unsigned long)(x) * (PAGE_SIZE / 1024)) #endif /* !_MACHINE_PARAM_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/pcb.h b/sys/arm64/include/pcb.h index 85c92727ca43..8eb342ecd0bc 100644 --- a/sys/arm64/include/pcb.h +++ b/sys/arm64/include/pcb.h @@ -1,89 +1,95 @@ /*- * Copyright (c) 2001 Jake Burkholder. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_PCB_H_ #define _MACHINE_PCB_H_ #ifndef LOCORE #include #include struct trapframe; /* The first register in pcb_x is x19 */ #define PCB_X_START 19 #define PCB_X19 0 #define PCB_X20 1 #define PCB_FP 10 #define PCB_LR 11 struct pcb { uint64_t pcb_x[12]; /* These two need to be in order as we access them together */ uint64_t pcb_sp; uint64_t pcb_tpidr_el0; uint64_t pcb_tpidrro_el0; /* Fault handler, the error value is passed in x0 */ vm_offset_t pcb_onfault; u_int pcb_flags; #define PCB_SINGLE_STEP_SHIFT 0 #define PCB_SINGLE_STEP (1 << PCB_SINGLE_STEP_SHIFT) uint32_t pcb_pad1; struct vfpstate *pcb_fpusaved; int pcb_fpflags; #define PCB_FP_STARTED 0x00000001 #define PCB_FP_KERN 0x40000000 #define PCB_FP_NOSAVE 0x80000000 /* The bits passed to userspace in get_fpcontext */ #define PCB_FP_USERMASK (PCB_FP_STARTED) u_int pcb_vfpcpu; /* Last cpu this thread ran VFP code */ uint64_t pcb_reserved[5]; /* * The userspace VFP state. The pcb_fpusaved pointer will point to * this unless the kernel has allocated a VFP context. * Place last to simplify the asm to access the rest if the struct. */ struct vfpstate pcb_fpustate; struct debug_monitor_state pcb_dbg_regs; }; #ifdef _KERNEL void makectx(struct trapframe *tf, struct pcb *pcb); int savectx(struct pcb *pcb) __returns_twice; #endif #endif /* !LOCORE */ #endif /* !_MACHINE_PCB_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/pcpu.h b/sys/arm64/include/pcpu.h index 38a8cd3c3e56..ebb72799d83f 100644 --- a/sys/arm64/include/pcpu.h +++ b/sys/arm64/include/pcpu.h @@ -1,91 +1,97 @@ /*- * Copyright (c) 1999 Luoqi Chen * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: FreeBSD: src/sys/i386/include/globaldata.h,v 1.27 2001/04/27 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_PCPU_H_ #define _MACHINE_PCPU_H_ #include #include #define ALT_STACK_SIZE 128 typedef int (*pcpu_bp_harden)(void); typedef int (*pcpu_ssbd)(int); struct debug_monitor_state; #define PCPU_MD_FIELDS \ u_int pc_acpi_id; /* ACPI CPU id */ \ u_int pc_midr; /* stored MIDR value */ \ uint64_t pc_clock; \ pcpu_bp_harden pc_bp_harden; \ pcpu_ssbd pc_ssbd; \ struct pmap *pc_curpmap; \ struct pmap *pc_curvmpmap; \ /* Store as two u_int values to preserve KBI */ \ uint64_t pc_mpidr; \ u_int pc_bcast_tlbi_workaround; \ char __pad[197] #ifdef _KERNEL struct pcb; struct pcpu; register struct pcpu *pcpup __asm ("x18"); static inline struct pcpu * get_pcpu(void) { struct pcpu *pcpu; __asm __volatile("mov %0, x18" : "=&r"(pcpu)); return (pcpu); } static inline struct thread * get_curthread(void) { struct thread *td; __asm __volatile("ldr %0, [x18]" : "=&r"(td)); return (td); } #define curthread get_curthread() #define PCPU_GET(member) (pcpup->pc_ ## member) #define PCPU_ADD(member, value) (pcpup->pc_ ## member += (value)) #define PCPU_PTR(member) (&pcpup->pc_ ## member) #define PCPU_SET(member,value) (pcpup->pc_ ## member = (value)) #define PCPU_GET_MPIDR(pc) ((pc)->pc_mpidr) #endif /* _KERNEL */ #endif /* !_MACHINE_PCPU_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/pcpu_aux.h b/sys/arm64/include/pcpu_aux.h index 57637c50063a..fada4ed65fb5 100644 --- a/sys/arm64/include/pcpu_aux.h +++ b/sys/arm64/include/pcpu_aux.h @@ -1,52 +1,58 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2019 The FreeBSD Foundation * * This software was developed by Konstantin Belousov * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_PCPU_AUX_H_ #define _MACHINE_PCPU_AUX_H_ #ifndef _KERNEL #error "Not for userspace" #endif #ifndef _SYS_PCPU_H_ #error "Do not include machine/pcpu_aux.h directly" #endif /* * To minimize memory waste in per-cpu UMA zones, the page size should * be a multiple of the size of struct pcpu. */ _Static_assert(PAGE_SIZE % sizeof(struct pcpu) == 0, "fix pcpu size"); extern struct pcpu pcpu0; #endif /* _MACHINE_PCPU_AUX_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/pmap.h b/sys/arm64/include/pmap.h index b855a811d3c0..5af90e6a3ca7 100644 --- a/sys/arm64/include/pmap.h +++ b/sys/arm64/include/pmap.h @@ -1,200 +1,206 @@ /*- * Copyright (c) 1991 Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * the Systems Programming Group of the University of Utah Computer * Science Department and William Jolitz of UUNET Technologies Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_PMAP_H_ #define _MACHINE_PMAP_H_ #include #ifndef LOCORE #include #include #include #include #include #ifdef _KERNEL #define vtophys(va) pmap_kextract((vm_offset_t)(va)) #endif #define pmap_page_get_memattr(m) ((m)->md.pv_memattr) #define pmap_page_is_write_mapped(m) (((m)->a.flags & PGA_WRITEABLE) != 0) void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); /* * Pmap stuff */ struct md_page { TAILQ_HEAD(,pv_entry) pv_list; int pv_gen; vm_memattr_t pv_memattr; }; /* * This structure is used to hold a virtual<->physical address * association and is used mostly by bootstrap code */ struct pv_addr { SLIST_ENTRY(pv_addr) pv_list; vm_offset_t pv_va; vm_paddr_t pv_pa; }; enum pmap_stage { PM_INVALID, PM_STAGE1, PM_STAGE2, }; struct pmap { struct mtx pm_mtx; struct pmap_statistics pm_stats; /* pmap statistics */ uint64_t pm_ttbr; vm_paddr_t pm_l0_paddr; pd_entry_t *pm_l0; TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ struct vm_radix pm_root; /* spare page table pages */ long pm_cookie; /* encodes the pmap's ASID */ struct asid_set *pm_asid_set; /* The ASID/VMID set to use */ enum pmap_stage pm_stage; int pm_levels; uint64_t pm_reserved[4]; }; typedef struct pmap *pmap_t; struct thread; #ifdef _KERNEL extern struct pmap kernel_pmap_store; #define kernel_pmap (&kernel_pmap_store) #define pmap_kernel() kernel_pmap #define PMAP_ASSERT_LOCKED(pmap) \ mtx_assert(&(pmap)->pm_mtx, MA_OWNED) #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) #define PMAP_LOCK_ASSERT(pmap, type) \ mtx_assert(&(pmap)->pm_mtx, (type)) #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ NULL, MTX_DEF | MTX_DUPOK) #define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx) #define PMAP_MTX(pmap) (&(pmap)->pm_mtx) #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) #define ASID_RESERVED_FOR_PID_0 0 #define ASID_RESERVED_FOR_EFI 1 #define ASID_FIRST_AVAILABLE (ASID_RESERVED_FOR_EFI + 1) #define ASID_TO_OPERAND(asid) ({ \ KASSERT((asid) != -1, ("invalid ASID")); \ (uint64_t)(asid) << TTBR_ASID_SHIFT; \ }) extern vm_offset_t virtual_avail; extern vm_offset_t virtual_end; /* * Macros to test if a mapping is mappable with an L1 Section mapping * or an L2 Large Page mapping. */ #define L1_MAPPABLE_P(va, pa, size) \ ((((va) | (pa)) & L1_OFFSET) == 0 && (size) >= L1_SIZE) #define pmap_vm_page_alloc_check(m) void pmap_activate_vm(pmap_t); void pmap_bootstrap(vm_paddr_t, vm_size_t); int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode); int pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot); void pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode); void pmap_kenter_device(vm_offset_t, vm_size_t, vm_paddr_t); bool pmap_klookup(vm_offset_t va, vm_paddr_t *pa); vm_paddr_t pmap_kextract(vm_offset_t va); void pmap_kremove(vm_offset_t); void pmap_kremove_device(vm_offset_t, vm_size_t); void *pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma); bool pmap_page_is_mapped(vm_page_t m); int pmap_pinit_stage(pmap_t, enum pmap_stage, int); bool pmap_ps_enabled(pmap_t pmap); uint64_t pmap_to_ttbr0(pmap_t pmap); void pmap_disable_promotion(vm_offset_t sva, vm_size_t size); void pmap_map_delete(pmap_t, vm_offset_t, vm_offset_t); void *pmap_mapdev(vm_paddr_t, vm_size_t); void *pmap_mapbios(vm_paddr_t, vm_size_t); void pmap_unmapdev(void *, vm_size_t); void pmap_unmapbios(void *, vm_size_t); bool pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, bool); void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, bool); bool pmap_get_tables(pmap_t, vm_offset_t, pd_entry_t **, pd_entry_t **, pd_entry_t **, pt_entry_t **); int pmap_fault(pmap_t, uint64_t, uint64_t); struct pcb *pmap_switch(struct thread *); extern void (*pmap_clean_stage2_tlbi)(void); extern void (*pmap_invalidate_vpipt_icache)(void); extern void (*pmap_stage2_invalidate_range)(uint64_t, vm_offset_t, vm_offset_t, bool); extern void (*pmap_stage2_invalidate_all)(uint64_t); static inline int pmap_vmspace_copy(pmap_t dst_pmap __unused, pmap_t src_pmap __unused) { return (0); } #if defined(KASAN) || defined(KMSAN) struct arm64_bootparams; void pmap_bootstrap_san(vm_paddr_t); void pmap_san_enter(vm_offset_t); void pmap_san_bootstrap(struct arm64_bootparams *); #endif #endif /* _KERNEL */ #endif /* !LOCORE */ #endif /* !_MACHINE_PMAP_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/proc.h b/sys/arm64/include/proc.h index eb5fe806088a..9538c3ea1e4a 100644 --- a/sys/arm64/include/proc.h +++ b/sys/arm64/include/proc.h @@ -1,77 +1,83 @@ /*- * Copyright (c) 1991 Regents of the University of California. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)proc.h 7.1 (Berkeley) 5/15/91 * from: FreeBSD: src/sys/i386/include/proc.h,v 1.11 2001/06/29 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_PROC_H_ #define _MACHINE_PROC_H_ struct ptrauth_key { uint64_t pa_key_lo; uint64_t pa_key_hi; }; struct mdthread { int md_spinlock_count; /* (k) */ register_t md_saved_daif; /* (k) */ uintptr_t md_canary; /* * The pointer authentication keys. These are shared within a process, * however this may change for some keys as the PAuth ABI Extension to * ELF for the Arm 64-bit Architecture [1] is currently (July 2021) at * an Alpha release quality so may change. * * [1] https://github.com/ARM-software/abi-aa/blob/main/pauthabielf64/pauthabielf64.rst */ struct { struct ptrauth_key apia; struct ptrauth_key apib; struct ptrauth_key apda; struct ptrauth_key apdb; struct ptrauth_key apga; } md_ptrauth_user; struct { struct ptrauth_key apia; } md_ptrauth_kern; uint64_t md_reserved[4]; }; struct mdproc { long md_dummy; }; #define KINFO_PROC_SIZE 1088 #define KINFO_PROC32_SIZE 816 #endif /* !_MACHINE_PROC_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/profile.h b/sys/arm64/include/profile.h index f898e2707d65..0f077e4ba6ed 100644 --- a/sys/arm64/include/profile.h +++ b/sys/arm64/include/profile.h @@ -1,91 +1,97 @@ /*- * SPDX-License-Identifier: MIT-CMU * * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. * All rights reserved. * * Author: Chris G. Demetriou * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. * * from: NetBSD: profile.h,v 1.9 1997/04/06 08:47:37 cgd Exp * from: FreeBSD: src/sys/alpha/include/profile.h,v 1.4 1999/12/29 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_PROFILE_H_ #define _MACHINE_PROFILE_H_ #define FUNCTION_ALIGNMENT 32 typedef u_long fptrdiff_t; #ifndef _KERNEL #include typedef __uintfptr_t uintfptr_t; #define _MCOUNT_DECL \ static void _mcount(uintfptr_t frompc, uintfptr_t selfpc) __used; \ static void _mcount /* * Call into _mcount. On arm64 the .mcount is a function so callers will * handle caller saved registers. As we don't directly touch any callee * saved registers we can just load the two arguments and use a tail call * into the MI _mcount function. * * When building with gcc frompc will be in x0, however this is not the * case on clang. As such we need to load it from the stack. As long as * the caller follows the ABI this will load the correct value. */ #define MCOUNT __asm( \ " .text \n" \ " .align 6 \n" \ " .type .mcount,#function \n" \ " .globl .mcount \n" \ " .mcount: \n" \ " .cfi_startproc \n" \ /* Load the caller return address as frompc */ \ " ldr x0, [x29, #8] \n" \ /* Use our return address as selfpc */ \ " mov x1, lr \n" \ " b _mcount \n" \ " .cfi_endproc \n" \ " .size .mcount, . - .mcount \n" \ ); #if 0 /* * If clang passed frompc correctly we could implement it like this, however * all clang versions we care about would need to be fixed before we could * make this change. */ void mcount(uintfptr_t frompc) { _mcount(frompc, __builtin_return_address(0)); } #endif #endif /* !_KERNEL */ #endif /* !_MACHINE_PROFILE_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/pte.h b/sys/arm64/include/pte.h index c320d71bb0f6..f51ac49a5d5d 100644 --- a/sys/arm64/include/pte.h +++ b/sys/arm64/include/pte.h @@ -1,190 +1,196 @@ /*- * Copyright (c) 2014 Andrew Turner * Copyright (c) 2014-2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Andrew Turner under * sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_PTE_H_ #define _MACHINE_PTE_H_ #ifndef LOCORE typedef uint64_t pd_entry_t; /* page directory entry */ typedef uint64_t pt_entry_t; /* page table entry */ #endif /* Table attributes */ #define TATTR_MASK UINT64_C(0xfff8000000000000) #define TATTR_AP_TABLE_MASK (3UL << 61) #define TATTR_AP_TABLE_RO (2UL << 61) #define TATTR_AP_TABLE_NO_EL0 (1UL << 61) #define TATTR_UXN_TABLE (1UL << 60) #define TATTR_PXN_TABLE (1UL << 59) /* Bits 58:51 are ignored */ /* Block and Page attributes */ #define ATTR_MASK_H UINT64_C(0xfffc000000000000) #define ATTR_MASK_L UINT64_C(0x0000000000000fff) #define ATTR_MASK (ATTR_MASK_H | ATTR_MASK_L) #define BASE_MASK ~ATTR_MASK #define BASE_ADDR(x) ((x) & BASE_MASK) #define PTE_TO_PHYS(pte) BASE_ADDR(pte) /* Convert a phys addr to the output address field of a PTE */ #define PHYS_TO_PTE(pa) (pa) /* Bits 58:55 are reserved for software */ #define ATTR_SW_UNUSED1 (1UL << 58) #define ATTR_SW_NO_PROMOTE (1UL << 57) #define ATTR_SW_MANAGED (1UL << 56) #define ATTR_SW_WIRED (1UL << 55) #define ATTR_S1_UXN (1UL << 54) #define ATTR_S1_PXN (1UL << 53) #define ATTR_S1_XN (ATTR_S1_PXN | ATTR_S1_UXN) #define ATTR_S2_XN(x) ((x) << 53) #define ATTR_S2_XN_MASK ATTR_S2_XN(3UL) #define ATTR_S2_XN_NONE 0UL /* Allow execution at EL0 & EL1 */ #define ATTR_S2_XN_EL1 1UL /* Allow execution at EL0 */ #define ATTR_S2_XN_ALL 2UL /* No execution */ #define ATTR_S2_XN_EL0 3UL /* Allow execution at EL1 */ #define ATTR_CONTIGUOUS (1UL << 52) #define ATTR_DBM (1UL << 51) #define ATTR_S1_nG (1 << 11) #define ATTR_AF (1 << 10) #define ATTR_SH(x) ((x) << 8) #define ATTR_SH_MASK ATTR_SH(3) #define ATTR_SH_NS 0 /* Non-shareable */ #define ATTR_SH_OS 2 /* Outer-shareable */ #define ATTR_SH_IS 3 /* Inner-shareable */ #define ATTR_S1_AP_RW_BIT (1 << 7) #define ATTR_S1_AP(x) ((x) << 6) #define ATTR_S1_AP_MASK ATTR_S1_AP(3) #define ATTR_S1_AP_RW (0 << 1) #define ATTR_S1_AP_RO (1 << 1) #define ATTR_S1_AP_USER (1 << 0) #define ATTR_S1_NS (1 << 5) #define ATTR_S1_IDX(x) ((x) << 2) #define ATTR_S1_IDX_MASK (7 << 2) #define ATTR_S2_S2AP(x) ((x) << 6) #define ATTR_S2_S2AP_MASK 3 #define ATTR_S2_S2AP_READ 1 #define ATTR_S2_S2AP_WRITE 2 #define ATTR_S2_MEMATTR(x) ((x) << 2) #define ATTR_S2_MEMATTR_MASK ATTR_S2_MEMATTR(0xf) #define ATTR_S2_MEMATTR_DEVICE_nGnRnE 0x0 #define ATTR_S2_MEMATTR_NC 0xf #define ATTR_S2_MEMATTR_WT 0xa #define ATTR_S2_MEMATTR_WB 0xf #define ATTR_DEFAULT (ATTR_AF | ATTR_SH(ATTR_SH_IS)) #define ATTR_DESCR_MASK 3 #define ATTR_DESCR_VALID 1 #define ATTR_DESCR_TYPE_MASK 2 #define ATTR_DESCR_TYPE_TABLE 2 #define ATTR_DESCR_TYPE_PAGE 2 #define ATTR_DESCR_TYPE_BLOCK 0 #if PAGE_SIZE == PAGE_SIZE_4K #define L0_SHIFT 39 #define L1_SHIFT 30 #define L2_SHIFT 21 #define L3_SHIFT 12 #elif PAGE_SIZE == PAGE_SIZE_16K #define L0_SHIFT 47 #define L1_SHIFT 36 #define L2_SHIFT 25 #define L3_SHIFT 14 #else #error Unsupported page size #endif /* Level 0 table, 512GiB/128TiB per entry */ #define L0_SIZE (UINT64_C(1) << L0_SHIFT) #define L0_OFFSET (L0_SIZE - 1ul) #define L0_INVAL 0x0 /* An invalid address */ /* 0x1 Level 0 doesn't support block translation */ /* 0x2 also marks an invalid address */ #define L0_TABLE 0x3 /* A next-level table */ /* Level 1 table, 1GiB/64GiB per entry */ #define L1_SIZE (UINT64_C(1) << L1_SHIFT) #define L1_OFFSET (L1_SIZE - 1) #define L1_INVAL L0_INVAL #define L1_BLOCK 0x1 #define L1_TABLE L0_TABLE /* Level 2 table, 2MiB/32MiB per entry */ #define L2_SIZE (UINT64_C(1) << L2_SHIFT) #define L2_OFFSET (L2_SIZE - 1) #define L2_INVAL L1_INVAL #define L2_BLOCK 0x1 #define L2_TABLE L1_TABLE /* Level 3 table, 4KiB/16KiB per entry */ #define L3_SIZE (1 << L3_SHIFT) #define L3_OFFSET (L3_SIZE - 1) #define L3_INVAL 0x0 /* 0x1 is reserved */ /* 0x2 also marks an invalid address */ #define L3_PAGE 0x3 #define PMAP_MAPDEV_EARLY_SIZE (L2_SIZE * 8) #if PAGE_SIZE == PAGE_SIZE_4K #define L0_ENTRIES_SHIFT 9 #define Ln_ENTRIES_SHIFT 9 #elif PAGE_SIZE == PAGE_SIZE_16K #define L0_ENTRIES_SHIFT 1 #define Ln_ENTRIES_SHIFT 11 #else #error Unsupported page size #endif #define L0_ENTRIES (1 << L0_ENTRIES_SHIFT) #define L0_ADDR_MASK (L0_ENTRIES - 1) #define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT) #define Ln_ADDR_MASK (Ln_ENTRIES - 1) #define Ln_TABLE_MASK ((1 << 12) - 1) #define pmap_l0_index(va) (((va) >> L0_SHIFT) & L0_ADDR_MASK) #define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK) #define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK) #define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK) #endif /* !_MACHINE_PTE_H_ */ /* End of pte.h */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/reg.h b/sys/arm64/include/reg.h index 4e8ca4f4e834..027c02a59903 100644 --- a/sys/arm64/include/reg.h +++ b/sys/arm64/include/reg.h @@ -1,93 +1,99 @@ /*- * Copyright (c) 2014 Andrew Turner * Copyright (c) 2014-2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Andrew Turner under * sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_REG_H_ #define _MACHINE_REG_H_ #include struct reg { __uint64_t x[30]; __uint64_t lr; __uint64_t sp; __uint64_t elr; __uint64_t spsr; }; struct reg32 { unsigned int r[13]; unsigned int r_sp; unsigned int r_lr; unsigned int r_pc; unsigned int r_cpsr; }; struct fpreg { __uint128_t fp_q[32]; __uint32_t fp_sr; __uint32_t fp_cr; }; struct fpreg32 { int dummy; }; struct dbreg { __uint8_t db_debug_ver; __uint8_t db_nbkpts; __uint8_t db_nwtpts; __uint8_t db_pad[5]; struct { __uint64_t dbr_addr; __uint32_t dbr_ctrl; __uint32_t dbr_pad; } db_breakregs[16]; struct { __uint64_t dbw_addr; __uint32_t dbw_ctrl; __uint32_t dbw_pad; } db_watchregs[16]; }; struct dbreg32 { int dummy; }; struct arm64_addr_mask { __uint64_t code; __uint64_t data; }; #define __HAVE_REG32 #endif /* !_MACHINE_REG_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/reloc.h b/sys/arm64/include/reloc.h index da23dbe43a4f..b6e2eb6f775c 100644 --- a/sys/arm64/include/reloc.h +++ b/sys/arm64/include/reloc.h @@ -1 +1,7 @@ /* $FreeBSD$ */ + +#ifdef __arm__ +#include +#else /* !__arm__ */ +/* empty */ +#endif /* !__arm__ */ diff --git a/sys/arm64/include/resource.h b/sys/arm64/include/resource.h index aef4fad4516d..82d36fe6beb7 100644 --- a/sys/arm64/include/resource.h +++ b/sys/arm64/include/resource.h @@ -1,49 +1,55 @@ /*- * Copyright 1998 Massachusetts Institute of Technology * * Permission to use, copy, modify, and distribute this software and * its documentation for any purpose and without fee is hereby * granted, provided that both the above copyright notice and this * permission notice appear in all copies, that both the above * copyright notice and this permission notice appear in all * supporting documentation, and that the name of M.I.T. not be used * in advertising or publicity pertaining to distribution of the * software without specific, written prior permission. M.I.T. makes * no representations about the suitability of this software for any * purpose. It is provided "as is" without express or implied * warranty. * * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_RESOURCE_H_ #define _MACHINE_RESOURCE_H_ 1 /* * Definitions of resource types for Intel Architecture machines * with support for legacy ISA devices and drivers. */ #define SYS_RES_IRQ 1 /* interrupt lines */ #define SYS_RES_DRQ 2 /* isa dma lines */ #define SYS_RES_MEMORY 3 /* i/o memory */ #define SYS_RES_IOPORT 4 /* i/o ports */ #define SYS_RES_GPIO 5 /* general purpose i/o */ #ifdef NEW_PCIB #define PCI_RES_BUS 6 /* PCI bus numbers */ #endif #endif /* !_MACHINE_RESOURCE_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/runq.h b/sys/arm64/include/runq.h index eaeb824a6698..0dfd55d3b726 100644 --- a/sys/arm64/include/runq.h +++ b/sys/arm64/include/runq.h @@ -1,46 +1,52 @@ /*- * Copyright (c) 2001 Jake Burkholder * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_RUNQ_H_ #define _MACHINE_RUNQ_H_ #define RQB_LEN (1) /* Number of priority status words. */ #define RQB_L2BPW (6) /* Log2(sizeof(rqb_word_t) * NBBY)). */ #define RQB_BPW (1<> RQB_L2BPW) #define RQB_FFS(word) (ffsl(word) - 1) /* * Type of run queue status word. */ typedef unsigned long rqb_word_t; #endif + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/setjmp.h b/sys/arm64/include/setjmp.h index af11a246cd3f..a88452a55015 100644 --- a/sys/arm64/include/setjmp.h +++ b/sys/arm64/include/setjmp.h @@ -1,73 +1,79 @@ /*- * Copyright (c) 2014 Andrew Turner * Copyright (c) 2014-2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Andrew Turner under * sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_SETJMP_H_ #define _MACHINE_SETJMP_H_ #include /* * We need to store: * - A magic value to differentiate the buffers * - The stack pointer * - The link register * - 11 general purpose registers * - 8 floating point registers * - The signal mask (128 bits) * i.e. 24 64-bit words, round this up to 31(+1) 128-bit words to allow for * CPU extensions with larger registers and stronger alignment requirements. * * The registers to save are: r19 to r29, and d8 to d15. */ #define _JBLEN 31 #define _JB_SIGMASK 22 /* This should only be needed in libc and may change */ #ifdef __ASSEMBLER__ #define _JB_MAGIC__SETJMP 0xfb5d25837d7ff700 #define _JB_MAGIC_SETJMP 0xfb5d25837d7ff701 #endif #ifndef __ASSEMBLER__ /* * jmp_buf and sigjmp_buf are encapsulated in different structs to force * compile-time diagnostics for mismatches. The structs are the same * internally to avoid some run-time errors for mismatches. */ #if __BSD_VISIBLE || __POSIX_VISIBLE || __XSI_VISIBLE typedef struct _sigjmp_buf { __int128_t _sjb[_JBLEN + 1]; } sigjmp_buf[1]; #endif typedef struct _jmp_buf { __int128_t _jb[_JBLEN + 1]; } jmp_buf[1]; #endif /* __ASSEMBLER__ */ #endif /* !_MACHINE_SETJMP_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/sf_buf.h b/sys/arm64/include/sf_buf.h index 59f9009bd086..7e99ae379b8a 100644 --- a/sys/arm64/include/sf_buf.h +++ b/sys/arm64/include/sf_buf.h @@ -1,51 +1,57 @@ /*- * Copyright (c) 2003, 2005 Alan L. Cox * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_SF_BUF_H_ #define _MACHINE_SF_BUF_H_ /* * On this machine, the only purpose for which sf_buf is used is to implement * an opaque pointer required by the machine-independent parts of the kernel. * That pointer references the vm_page that is "mapped" by the sf_buf. The * actual mapping is provided by the direct virtual-to-physical mapping. */ static inline vm_offset_t sf_buf_kva(struct sf_buf *sf) { return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS((vm_page_t)sf))); } static inline vm_page_t sf_buf_page(struct sf_buf *sf) { return ((vm_page_t)sf); } #endif /* !_MACHINE_SF_BUF_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/signal.h b/sys/arm64/include/signal.h index 6c8ac5cabab5..2684a89952d7 100644 --- a/sys/arm64/include/signal.h +++ b/sys/arm64/include/signal.h @@ -1,50 +1,56 @@ /*- * Copyright (c) 1986, 1989, 1991, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)signal.h 8.1 (Berkeley) 6/11/93 * from: FreeBSD: src/sys/i386/include/signal.h,v 1.13 2000/11/09 * from: FreeBSD: src/sys/sparc64/include/signal.h,v 1.6 2001/09/30 18:52:17 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_SIGNAL_H_ #define _MACHINE_SIGNAL_H_ #include typedef long sig_atomic_t; #if __BSD_VISIBLE struct sigcontext { int _dummy; }; #endif #endif /* !_MACHINE_SIGNAL_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/sysarch.h b/sys/arm64/include/sysarch.h index 4d6c547fd3df..22248cf1b867 100644 --- a/sys/arm64/include/sysarch.h +++ b/sys/arm64/include/sysarch.h @@ -1,47 +1,53 @@ /*- * Copyright (c) 1993 The Regents of the University of California. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: FreeBSD: src/sys/i386/include/sysarch.h,v 1.14 2000/09/21 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + /* * Architecture specific syscalls (arm64) */ #ifndef _MACHINE_SYSARCH_H_ #define _MACHINE_SYSARCH_H_ #ifndef _KERNEL __BEGIN_DECLS int sysarch(int _number, void *_args); __END_DECLS #endif #endif /* !_MACHINE_SYSARCH_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/sysreg.h b/sys/arm64/include/sysreg.h new file mode 100644 index 000000000000..4ec435f9dcc1 --- /dev/null +++ b/sys/arm64/include/sysreg.h @@ -0,0 +1,5 @@ +#ifdef __arm__ +#include +#else /* !__arm__ */ +#error Do not include this header, used only for 32-bit compatibility +#endif /* !__arm__ */ diff --git a/sys/arm64/include/tls.h b/sys/arm64/include/tls.h index a3ec7f7952e8..c9db2bdfd708 100644 --- a/sys/arm64/include/tls.h +++ b/sys/arm64/include/tls.h @@ -1,55 +1,61 @@ /*- * Copyright (c) 2005 David Xu . * Copyright (c) 2014 the FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Andrew Turner * under sponsorship from the FreeBSD Foundation * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_TLS_H_ #define _MACHINE_TLS_H_ #include #define TLS_DTV_OFFSET 0 #define TLS_TCB_ALIGN 16 #define TLS_TP_OFFSET 0 static __inline void _tcb_set(struct tcb *tcb) { __asm __volatile("msr tpidr_el0, %x0" :: "r" (tcb)); } static __inline struct tcb * _tcb_get(void) { struct tcb *tcb; __asm __volatile("mrs %x0, tpidr_el0" : "=r" (tcb)); return (tcb); } #endif /* !_MACHINE_TLS_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/ucontext.h b/sys/arm64/include/ucontext.h index edb4cf8e63e3..d0b9296fe514 100644 --- a/sys/arm64/include/ucontext.h +++ b/sys/arm64/include/ucontext.h @@ -1,88 +1,94 @@ /*- * Copyright (c) 2014 Andrew Turner * Copyright (c) 2014-2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Andrew Turner under * sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_UCONTEXT_H_ #define _MACHINE_UCONTEXT_H_ struct gpregs { __register_t gp_x[30]; __register_t gp_lr; __register_t gp_sp; __register_t gp_elr; __uint64_t gp_spsr; }; struct fpregs { __uint128_t fp_q[32]; __uint32_t fp_sr; __uint32_t fp_cr; int fp_flags; int fp_pad; }; struct __mcontext { struct gpregs mc_gpregs; struct fpregs mc_fpregs; int mc_flags; #define _MC_FP_VALID 0x1 /* Set when mc_fpregs has valid data */ int mc_pad; /* Padding */ __uint64_t mc_spare[8]; /* Space for expansion, set to zero */ }; typedef struct __mcontext mcontext_t; #ifdef COMPAT_FREEBSD32 #include typedef struct __mcontext32 { uint32_t mc_gregset[17]; uint32_t mc_vfp_size; uint32_t mc_vfp_ptr; uint32_t mc_spare[33]; } mcontext32_t; typedef struct __ucontext32 { sigset_t uc_sigmask; mcontext32_t uc_mcontext; u_int32_t uc_link; struct sigaltstack32 uc_stack; u_int32_t uc_flags; u_int32_t __spare__[4]; } ucontext32_t; typedef struct __mcontext32_vfp { __uint64_t mcv_reg[32]; __uint32_t mcv_fpscr; } mcontext32_vfp_t; #endif /* COMPAT_FREEBSD32 */ #endif /* !_MACHINE_UCONTEXT_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/vdso.h b/sys/arm64/include/vdso.h index fef74df39663..f84c980077ab 100644 --- a/sys/arm64/include/vdso.h +++ b/sys/arm64/include/vdso.h @@ -1,39 +1,45 @@ /*- * Copyright 2012 Konstantin Belousov . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_VDSO_H_ #define _MACHINE_VDSO_H_ #define VDSO_TIMEHANDS_MD \ uint32_t th_physical; \ uint32_t th_res[7]; #define VDSO_TH_ALGO_ARM_GENTIM VDSO_TH_ALGO_1 #define VDSO_TIMEHANDS_MD32 VDSO_TIMEHANDS_MD #endif /* !_MACHINE_VDSO_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/vfp.h b/sys/arm64/include/vfp.h index 79e710694268..84c24c82ab8e 100644 --- a/sys/arm64/include/vfp.h +++ b/sys/arm64/include/vfp.h @@ -1,115 +1,121 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * * This software was developed by Andrew Turner under * sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_VFP_H_ #define _MACHINE_VFP_H_ /* VFPCR */ #define VFPCR_AHP (0x04000000) /* alt. half-precision: */ #define VFPCR_DN (0x02000000) /* default NaN enable */ #define VFPCR_FZ (0x01000000) /* flush to zero enabled */ #define VFPCR_INIT 0 /* Default fpcr after exec */ #define VFPCR_RMODE_OFF 22 /* rounding mode offset */ #define VFPCR_RMODE_MASK (0x00c00000) /* rounding mode mask */ #define VFPCR_RMODE_RN (0x00000000) /* round nearest */ #define VFPCR_RMODE_RPI (0x00400000) /* round to plus infinity */ #define VFPCR_RMODE_RNI (0x00800000) /* round to neg infinity */ #define VFPCR_RMODE_RM (0x00c00000) /* round to zero */ #define VFPCR_STRIDE_OFF 20 /* vector stride -1 */ #define VFPCR_STRIDE_MASK (0x00300000) #define VFPCR_LEN_OFF 16 /* vector length -1 */ #define VFPCR_LEN_MASK (0x00070000) #define VFPCR_IDE (0x00008000) /* input subnormal exc enable */ #define VFPCR_IXE (0x00001000) /* inexact exception enable */ #define VFPCR_UFE (0x00000800) /* underflow exception enable */ #define VFPCR_OFE (0x00000400) /* overflow exception enable */ #define VFPCR_DZE (0x00000200) /* div by zero exception en */ #define VFPCR_IOE (0x00000100) /* invalid op exec enable */ #ifndef LOCORE struct vfpstate { __uint128_t vfp_regs[32]; uint32_t vfp_fpcr; uint32_t vfp_fpsr; }; #ifdef _KERNEL struct pcb; struct thread; void vfp_init_secondary(void); void vfp_enable(void); void vfp_disable(void); void vfp_discard(struct thread *); void vfp_store(struct vfpstate *); void vfp_restore(struct vfpstate *); void vfp_new_thread(struct thread *, struct thread *, bool); void vfp_reset_state(struct thread *, struct pcb *); void vfp_restore_state(void); void vfp_save_state(struct thread *, struct pcb *); struct fpu_kern_ctx; /* * Flags for fpu_kern_alloc_ctx(), fpu_kern_enter() and fpu_kern_thread(). */ #define FPU_KERN_NORMAL 0x0000 #define FPU_KERN_NOWAIT 0x0001 #define FPU_KERN_KTHR 0x0002 #define FPU_KERN_NOCTX 0x0004 struct fpu_kern_ctx *fpu_kern_alloc_ctx(u_int); void fpu_kern_free_ctx(struct fpu_kern_ctx *); void fpu_kern_enter(struct thread *, struct fpu_kern_ctx *, u_int); int fpu_kern_leave(struct thread *, struct fpu_kern_ctx *); int fpu_kern_thread(u_int); int is_fpu_kern_thread(u_int); struct vfpstate *fpu_save_area_alloc(void); void fpu_save_area_free(struct vfpstate *fsa); void fpu_save_area_reset(struct vfpstate *fsa); /* Convert to and from Aarch32 FPSCR to Aarch64 FPCR/FPSR */ #define VFP_FPSCR_FROM_SRCR(vpsr, vpcr) ((vpsr) | ((vpcr) & 0x7c00000)) #define VFP_FPSR_FROM_FPSCR(vpscr) ((vpscr) &~ 0x7c00000) #define VFP_FPCR_FROM_FPSCR(vpsrc) ((vpsrc) & 0x7c00000) #ifdef COMPAT_FREEBSD32 void get_fpcontext32(struct thread *td, mcontext32_vfp_t *mcp); void set_fpcontext32(struct thread *td, mcontext32_vfp_t *mcp); #endif #endif #endif #endif /* !_MACHINE_VFP_H_ */ + +#endif /* !__arm__ */ diff --git a/sys/arm64/include/vmparam.h b/sys/arm64/include/vmparam.h index 23b7d0d87c94..0839e20578ae 100644 --- a/sys/arm64/include/vmparam.h +++ b/sys/arm64/include/vmparam.h @@ -1,277 +1,283 @@ /*- * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * Copyright (c) 1994 John S. Dyson * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)vmparam.h 5.9 (Berkeley) 5/12/91 * from: FreeBSD: src/sys/i386/include/vmparam.h,v 1.33 2000/03/30 * $FreeBSD$ */ +#ifdef __arm__ +#include +#else /* !__arm__ */ + #ifndef _MACHINE_VMPARAM_H_ #define _MACHINE_VMPARAM_H_ /* * Virtual memory related constants, all in bytes */ #ifndef MAXTSIZ #define MAXTSIZ (1*1024*1024*1024) /* max text size */ #endif #ifndef DFLDSIZ #define DFLDSIZ (128*1024*1024) /* initial data size limit */ #endif #ifndef MAXDSIZ #define MAXDSIZ (1*1024*1024*1024) /* max data size */ #endif #ifndef DFLSSIZ #define DFLSSIZ (128*1024*1024) /* initial stack size limit */ #endif #ifndef MAXSSIZ #define MAXSSIZ (1*1024*1024*1024) /* max stack size */ #endif #ifndef SGROWSIZ #define SGROWSIZ (128*1024) /* amount to grow stack */ #endif /* * The physical address space is sparsely populated. */ #define VM_PHYSSEG_SPARSE /* * The number of PHYSSEG entries. */ #define VM_PHYSSEG_MAX 64 /* * Create two free page pools: VM_FREEPOOL_DEFAULT is the default pool * from which physical pages are allocated and VM_FREEPOOL_DIRECT is * the pool from which physical pages for small UMA objects are * allocated. */ #define VM_NFREEPOOL 2 #define VM_FREEPOOL_DEFAULT 0 #define VM_FREEPOOL_DIRECT 1 /* * Create one free page lists: VM_FREELIST_DEFAULT is for all physical * pages. */ #define VM_NFREELIST 1 #define VM_FREELIST_DEFAULT 0 /* * When PAGE_SIZE is 4KB, an allocation size of 16MB is supported in order * to optimize the use of the direct map by UMA. Specifically, a 64-byte * cache line contains at most 8 L2 BLOCK entries, collectively mapping 16MB * of physical memory. By reducing the number of distinct 16MB "pages" that * are used by UMA, the physical memory allocator reduces the likelihood of * both 2MB page TLB misses and cache misses during the page table walk when * a 2MB page TLB miss does occur. */ #define VM_NFREEORDER 13 /* * Enable superpage reservations: 1 level. */ #ifndef VM_NRESERVLEVEL #define VM_NRESERVLEVEL 1 #endif /* * Level 0 reservations consist of 512 pages. */ #ifndef VM_LEVEL_0_ORDER #define VM_LEVEL_0_ORDER 9 #endif /** * Address space layout. * * ARMv8 implements up to a 48 bit virtual address space. The address space is * split into 2 regions at each end of the 64 bit address space, with an * out of range "hole" in the middle. * * We use the full 48 bits for each region, however the kernel may only use * a limited range within this space. * * Upper region: 0xffffffffffffffff Top of virtual memory * * 0xfffffeffffffffff End of DMAP * 0xffffa00000000000 Start of DMAP * * 0xffff009fffffffff End of KASAN shadow map * 0xffff008000000000 Start of KASAN shadow map * * 0xffff007fffffffff End of KVA * 0xffff000000000000 Kernel base address & start of KVA * * Hole: 0xfffeffffffffffff * 0x0001000000000000 * * Lower region: 0x0000ffffffffffff End of user address space * 0x0000000000000000 Start of user address space * * We use the upper region for the kernel, and the lower region for userland. * * We define some interesting address constants: * * VM_MIN_ADDRESS and VM_MAX_ADDRESS define the start and end of the entire * 64 bit address space, mostly just for convenience. * * VM_MIN_KERNEL_ADDRESS and VM_MAX_KERNEL_ADDRESS define the start and end of * mappable kernel virtual address space. * * VM_MIN_USER_ADDRESS and VM_MAX_USER_ADDRESS define the start and end of the * user address space. */ #define VM_MIN_ADDRESS (0x0000000000000000UL) #define VM_MAX_ADDRESS (0xffffffffffffffffUL) /* 512 GiB of kernel addresses */ #define VM_MIN_KERNEL_ADDRESS (0xffff000000000000UL) #define VM_MAX_KERNEL_ADDRESS (0xffff008000000000UL) /* 128 GiB KASAN shadow map */ #define KASAN_MIN_ADDRESS (0xffff008000000000UL) #define KASAN_MAX_ADDRESS (0xffff00a000000000UL) /* The address bits that hold a pointer authentication code */ #define PAC_ADDR_MASK (0xff7f000000000000UL) /* If true addr is in the kernel address space */ #define ADDR_IS_KERNEL(addr) (((addr) & (1ul << 55)) == (1ul << 55)) /* If true addr is in its canonical form (i.e. no TBI, PAC, etc.) */ #define ADDR_IS_CANONICAL(addr) \ (((addr) & 0xffff000000000000UL) == 0 || \ ((addr) & 0xffff000000000000UL) == 0xffff000000000000UL) #define ADDR_MAKE_CANONICAL(addr) ({ \ __typeof(addr) _tmp_addr = (addr); \ \ _tmp_addr &= ~0xffff000000000000UL; \ if (ADDR_IS_KERNEL(addr)) \ _tmp_addr |= 0xffff000000000000UL; \ \ _tmp_addr; \ }) /* 95 TiB maximum for the direct map region */ #define DMAP_MIN_ADDRESS (0xffffa00000000000UL) #define DMAP_MAX_ADDRESS (0xffffff0000000000UL) #define DMAP_MIN_PHYSADDR (dmap_phys_base) #define DMAP_MAX_PHYSADDR (dmap_phys_max) /* True if pa is in the dmap range */ #define PHYS_IN_DMAP(pa) ((pa) >= DMAP_MIN_PHYSADDR && \ (pa) < DMAP_MAX_PHYSADDR) /* True if va is in the dmap range */ #define VIRT_IN_DMAP(va) ((va) >= DMAP_MIN_ADDRESS && \ (va) < (dmap_max_addr)) #define PMAP_HAS_DMAP 1 #define PHYS_TO_DMAP(pa) \ ({ \ KASSERT(PHYS_IN_DMAP(pa), \ ("%s: PA out of range, PA: 0x%lx", __func__, \ (vm_paddr_t)(pa))); \ ((pa) - dmap_phys_base) + DMAP_MIN_ADDRESS; \ }) #define DMAP_TO_PHYS(va) \ ({ \ KASSERT(VIRT_IN_DMAP(va), \ ("%s: VA out of range, VA: 0x%lx", __func__, \ (vm_offset_t)(va))); \ ((va) - DMAP_MIN_ADDRESS) + dmap_phys_base; \ }) #define VM_MIN_USER_ADDRESS (0x0000000000000000UL) #define VM_MAX_USER_ADDRESS (0x0001000000000000UL) #define VM_MINUSER_ADDRESS (VM_MIN_USER_ADDRESS) #define VM_MAXUSER_ADDRESS (VM_MAX_USER_ADDRESS) #define KERNBASE (VM_MIN_KERNEL_ADDRESS) #define SHAREDPAGE (VM_MAXUSER_ADDRESS - PAGE_SIZE) #define USRSTACK SHAREDPAGE /* * How many physical pages per kmem arena virtual page. */ #ifndef VM_KMEM_SIZE_SCALE #define VM_KMEM_SIZE_SCALE (1) #endif /* * Optional ceiling (in bytes) on the size of the kmem arena: 60% of the * kernel map. */ #ifndef VM_KMEM_SIZE_MAX #define VM_KMEM_SIZE_MAX ((VM_MAX_KERNEL_ADDRESS - \ VM_MIN_KERNEL_ADDRESS + 1) * 3 / 5) #endif /* * Initial pagein size of beginning of executable file. */ #ifndef VM_INITIAL_PAGEIN #define VM_INITIAL_PAGEIN 16 #endif #if !defined(KASAN) && !defined(KMSAN) #define UMA_MD_SMALL_ALLOC #endif #ifndef LOCORE extern vm_paddr_t dmap_phys_base; extern vm_paddr_t dmap_phys_max; extern vm_offset_t dmap_max_addr; extern vm_offset_t vm_max_kernel_address; #endif #define ZERO_REGION_SIZE (64 * 1024) /* 64KB */ #define DEVMAP_MAX_VADDR VM_MAX_KERNEL_ADDRESS /* * The pmap can create non-transparent large page mappings. */ #define PMAP_HAS_LARGEPAGES 1 /* * Need a page dump array for minidump. */ #define MINIDUMP_PAGE_TRACKING 1 #endif /* !_MACHINE_VMPARAM_H_ */ + +#endif /* !__arm__ */