diff --git a/sys/dev/ichiic/ig4_pci.c b/sys/dev/ichiic/ig4_pci.c index 9f12e713cdeb..138de77c35db 100644 --- a/sys/dev/ichiic/ig4_pci.c +++ b/sys/dev/ichiic/ig4_pci.c @@ -1,417 +1,425 @@ /* * Copyright (c) 2014 The DragonFly Project. All rights reserved. * * This code is derived from software contributed to The DragonFly Project * by Matthew Dillon and was subsequently ported * to FreeBSD by Michael Gmelin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include /* * Intel fourth generation mobile cpus integrated I2C device. * * See ig4_reg.h for datasheet reference and notes. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static int ig4iic_pci_detach(device_t dev); #define PCI_CHIP_BAYTRAIL_I2C_1 0x0f418086 #define PCI_CHIP_BAYTRAIL_I2C_2 0x0f428086 #define PCI_CHIP_BAYTRAIL_I2C_3 0x0f438086 #define PCI_CHIP_BAYTRAIL_I2C_4 0x0f448086 #define PCI_CHIP_BAYTRAIL_I2C_5 0x0f458086 #define PCI_CHIP_BAYTRAIL_I2C_6 0x0f468086 #define PCI_CHIP_BAYTRAIL_I2C_7 0x0f478086 #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 #define PCI_CHIP_BRASWELL_I2C_1 0x22c18086 #define PCI_CHIP_BRASWELL_I2C_2 0x22c28086 #define PCI_CHIP_BRASWELL_I2C_3 0x22c38086 #define PCI_CHIP_BRASWELL_I2C_5 0x22c58086 #define PCI_CHIP_BRASWELL_I2C_6 0x22c68086 #define PCI_CHIP_BRASWELL_I2C_7 0x22c78086 #define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086 #define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086 #define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086 #define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086 #define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086 #define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086 #define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086 #define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086 #define PCI_CHIP_APL_I2C_0 0x5aac8086 #define PCI_CHIP_APL_I2C_1 0x5aae8086 #define PCI_CHIP_APL_I2C_2 0x5ab08086 #define PCI_CHIP_APL_I2C_3 0x5ab28086 #define PCI_CHIP_APL_I2C_4 0x5ab48086 #define PCI_CHIP_APL_I2C_5 0x5ab68086 #define PCI_CHIP_APL_I2C_6 0x5ab88086 #define PCI_CHIP_APL_I2C_7 0x5aba8086 #define PCI_CHIP_CANNONLAKE_LP_I2C_0 0x9dc58086 #define PCI_CHIP_CANNONLAKE_LP_I2C_1 0x9dc68086 #define PCI_CHIP_CANNONLAKE_LP_I2C_2 0x9de88086 #define PCI_CHIP_CANNONLAKE_LP_I2C_3 0x9de98086 #define PCI_CHIP_CANNONLAKE_LP_I2C_4 0x9dea8086 #define PCI_CHIP_CANNONLAKE_LP_I2C_5 0x9deb8086 #define PCI_CHIP_CANNONLAKE_H_I2C_0 0xa3688086 #define PCI_CHIP_CANNONLAKE_H_I2C_1 0xa3698086 #define PCI_CHIP_CANNONLAKE_H_I2C_2 0xa36a8086 #define PCI_CHIP_CANNONLAKE_H_I2C_3 0xa36b8086 #define PCI_CHIP_COMETLAKE_LP_I2C_0 0x02e88086 #define PCI_CHIP_COMETLAKE_LP_I2C_1 0x02e98086 #define PCI_CHIP_COMETLAKE_LP_I2C_2 0x02ea8086 #define PCI_CHIP_COMETLAKE_LP_I2C_3 0x02eb8086 #define PCI_CHIP_COMETLAKE_LP_I2C_4 0x02c58086 #define PCI_CHIP_COMETLAKE_LP_I2C_5 0x02c68086 #define PCI_CHIP_COMETLAKE_H_I2C_0 0x06e88086 #define PCI_CHIP_COMETLAKE_H_I2C_1 0x06e98086 #define PCI_CHIP_COMETLAKE_H_I2C_2 0x06ea8086 #define PCI_CHIP_COMETLAKE_H_I2C_3 0x06eb8086 #define PCI_CHIP_COMETLAKE_V_I2C_0 0xa3e08086 #define PCI_CHIP_COMETLAKE_V_I2C_1 0xa3e18086 #define PCI_CHIP_COMETLAKE_V_I2C_2 0xa3e28086 #define PCI_CHIP_COMETLAKE_V_I2C_3 0xa3e38086 #define PCI_CHIP_ICELAKE_LP_I2C_0 0x34e88086 #define PCI_CHIP_ICELAKE_LP_I2C_1 0x34e98086 #define PCI_CHIP_ICELAKE_LP_I2C_2 0x34ea8086 #define PCI_CHIP_ICELAKE_LP_I2C_3 0x34eb8086 #define PCI_CHIP_ICELAKE_LP_I2C_4 0x34c58086 #define PCI_CHIP_ICELAKE_LP_I2C_5 0x34c68086 #define PCI_CHIP_TIGERLAKE_H_I2C_0 0x43d88086 #define PCI_CHIP_TIGERLAKE_H_I2C_1 0x43e88086 #define PCI_CHIP_TIGERLAKE_H_I2C_2 0x43e98086 #define PCI_CHIP_TIGERLAKE_H_I2C_3 0x43ea8086 #define PCI_CHIP_TIGERLAKE_H_I2C_4 0x43eb8086 #define PCI_CHIP_TIGERLAKE_H_I2C_5 0x43ad8086 #define PCI_CHIP_TIGERLAKE_H_I2C_6 0x43ae8086 #define PCI_CHIP_TIGERLAKE_LP_I2C_0 0xa0c58086 #define PCI_CHIP_TIGERLAKE_LP_I2C_1 0xa0c68086 #define PCI_CHIP_TIGERLAKE_LP_I2C_2 0xa0d88086 #define PCI_CHIP_TIGERLAKE_LP_I2C_3 0xa0d98086 #define PCI_CHIP_TIGERLAKE_LP_I2C_4 0xa0e88086 #define PCI_CHIP_TIGERLAKE_LP_I2C_5 0xa0e98086 #define PCI_CHIP_TIGERLAKE_LP_I2C_6 0xa0ea8086 #define PCI_CHIP_TIGERLAKE_LP_I2C_7 0xa0eb8086 #define PCI_CHIP_GEMINILAKE_I2C_0 0x31ac8086 #define PCI_CHIP_GEMINILAKE_I2C_1 0x31ae8086 #define PCI_CHIP_GEMINILAKE_I2C_2 0x31b08086 #define PCI_CHIP_GEMINILAKE_I2C_3 0x31b28086 #define PCI_CHIP_GEMINILAKE_I2C_4 0x31b48086 #define PCI_CHIP_GEMINILAKE_I2C_5 0x31b68086 #define PCI_CHIP_GEMINILAKE_I2C_6 0x31b88086 #define PCI_CHIP_GEMINILAKE_I2C_7 0x31ba8086 #define PCI_CHIP_ALDERLAKE_P_I2C_0 0x51e88086 #define PCI_CHIP_ALDERLAKE_P_I2C_1 0x51e98086 #define PCI_CHIP_ALDERLAKE_P_I2C_2 0x51ea8086 #define PCI_CHIP_ALDERLAKE_P_I2C_3 0x51eb8086 #define PCI_CHIP_ALDERLAKE_P_I2C_4 0x51c58086 #define PCI_CHIP_ALDERLAKE_P_I2C_5 0x51c68086 #define PCI_CHIP_ALDERLAKE_P_I2C_6 0x51d88086 #define PCI_CHIP_ALDERLAKE_P_I2C_7 0x51d98086 #define PCI_CHIP_ALDERLAKE_S_I2C_0 0x7acc8086 #define PCI_CHIP_ALDERLAKE_S_I2C_1 0x7acd8086 #define PCI_CHIP_ALDERLAKE_S_I2C_2 0x7ace8086 #define PCI_CHIP_ALDERLAKE_S_I2C_3 0x7acf8086 #define PCI_CHIP_ALDERLAKE_S_I2C_4 0x7afc8086 #define PCI_CHIP_ALDERLAKE_S_I2C_5 0x7afd8086 #define PCI_CHIP_ALDERLAKE_M_I2C_0 0x54e88086 #define PCI_CHIP_ALDERLAKE_M_I2C_1 0x54e98086 #define PCI_CHIP_ALDERLAKE_M_I2C_2 0x54ea8086 #define PCI_CHIP_ALDERLAKE_M_I2C_3 0x54eb8086 #define PCI_CHIP_ALDERLAKE_M_I2C_4 0x54c58086 #define PCI_CHIP_ALDERLAKE_M_I2C_5 0x54c68086 +#define PCI_CHIP_METEORLAKE_M_I2C_0 0x7e788086 +#define PCI_CHIP_METEORLAKE_M_I2C_1 0x7e798086 +#define PCI_CHIP_METEORLAKE_M_I2C_2 0x7e508086 +#define PCI_CHIP_METEORLAKE_M_I2C_3 0x7e518086 struct ig4iic_pci_device { uint32_t devid; const char *desc; enum ig4_vers version; }; static struct ig4iic_pci_device ig4iic_pci_devices[] = { { PCI_CHIP_BAYTRAIL_I2C_1, "Intel BayTrail Serial I/O I2C Port 1", IG4_ATOM}, { PCI_CHIP_BAYTRAIL_I2C_2, "Intel BayTrail Serial I/O I2C Port 2", IG4_ATOM}, { PCI_CHIP_BAYTRAIL_I2C_3, "Intel BayTrail Serial I/O I2C Port 3", IG4_ATOM}, { PCI_CHIP_BAYTRAIL_I2C_4, "Intel BayTrail Serial I/O I2C Port 4", IG4_ATOM}, { PCI_CHIP_BAYTRAIL_I2C_5, "Intel BayTrail Serial I/O I2C Port 5", IG4_ATOM}, { PCI_CHIP_BAYTRAIL_I2C_6, "Intel BayTrail Serial I/O I2C Port 6", IG4_ATOM}, { PCI_CHIP_BAYTRAIL_I2C_7, "Intel BayTrail Serial I/O I2C Port 7", IG4_ATOM}, { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL}, { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL}, { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM}, { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM}, { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM}, { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM}, { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM}, { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM}, { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE}, { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE}, { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE}, { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE}, { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE}, { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE}, { PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE}, { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE}, { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL}, { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL}, { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL}, { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL}, { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL}, { PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE}, { PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE}, { PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE}, { PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE}, { PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE}, { PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE}, { PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE}, { PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE}, { PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE}, { PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_LP_I2C_0, "Intel Comet Lake-LP I2C Controller-0", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_LP_I2C_1, "Intel Comet Lake-LP I2C Controller-1", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_LP_I2C_2, "Intel Comet Lake-LP I2C Controller-2", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_LP_I2C_3, "Intel Comet Lake-LP I2C Controller-3", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_LP_I2C_4, "Intel Comet Lake-LP I2C Controller-4", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_LP_I2C_5, "Intel Comet Lake-LP I2C Controller-5", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_H_I2C_0, "Intel Comet Lake-H I2C Controller-0", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_H_I2C_1, "Intel Comet Lake-H I2C Controller-1", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_H_I2C_2, "Intel Comet Lake-H I2C Controller-2", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_H_I2C_3, "Intel Comet Lake-H I2C Controller-3", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_V_I2C_0, "Intel Comet Lake-V I2C Controller-0", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE}, { PCI_CHIP_ICELAKE_LP_I2C_0, "Intel Ice Lake-LP I2C Controller-0", IG4_TIGERLAKE}, { PCI_CHIP_ICELAKE_LP_I2C_1, "Intel Ice Lake-LP I2C Controller-1", IG4_TIGERLAKE}, { PCI_CHIP_ICELAKE_LP_I2C_2, "Intel Ice Lake-LP I2C Controller-2", IG4_TIGERLAKE}, { PCI_CHIP_ICELAKE_LP_I2C_3, "Intel Ice Lake-LP I2C Controller-3", IG4_TIGERLAKE}, { PCI_CHIP_ICELAKE_LP_I2C_4, "Intel Ice Lake-LP I2C Controller-4", IG4_TIGERLAKE}, { PCI_CHIP_ICELAKE_LP_I2C_5, "Intel Ice Lake-LP I2C Controller-5", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_H_I2C_0, "Intel Tiger Lake-H I2C Controller-0", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_H_I2C_1, "Intel Tiger Lake-H I2C Controller-1", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_H_I2C_2, "Intel Tiger Lake-H I2C Controller-2", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_H_I2C_3, "Intel Tiger Lake-H I2C Controller-3", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_H_I2C_4, "Intel Tiger Lake-H I2C Controller-4", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_H_I2C_5, "Intel Tiger Lake-H I2C Controller-5", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_H_I2C_6, "Intel Tiger Lake-H I2C Controller-6", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_LP_I2C_0, "Intel Tiger Lake-LP I2C Controller-0", IG4_SKYLAKE}, { PCI_CHIP_TIGERLAKE_LP_I2C_1, "Intel Tiger Lake-LP I2C Controller-1", IG4_SKYLAKE}, { PCI_CHIP_TIGERLAKE_LP_I2C_2, "Intel Tiger Lake-LP I2C Controller-2", IG4_SKYLAKE}, { PCI_CHIP_TIGERLAKE_LP_I2C_3, "Intel Tiger Lake-LP I2C Controller-3", IG4_SKYLAKE}, { PCI_CHIP_TIGERLAKE_LP_I2C_4, "Intel Tiger Lake-LP I2C Controller-4", IG4_SKYLAKE}, { PCI_CHIP_TIGERLAKE_LP_I2C_5, "Intel Tiger Lake-LP I2C Controller-5", IG4_SKYLAKE}, { PCI_CHIP_TIGERLAKE_LP_I2C_6, "Intel Tiger Lake-LP I2C Controller-6", IG4_SKYLAKE}, { PCI_CHIP_TIGERLAKE_LP_I2C_7, "Intel Tiger Lake-LP I2C Controller-7", IG4_SKYLAKE}, { PCI_CHIP_GEMINILAKE_I2C_0, "Intel Gemini Lake I2C Controller-0", IG4_GEMINILAKE}, { PCI_CHIP_GEMINILAKE_I2C_1, "Intel Gemini Lake I2C Controller-1", IG4_GEMINILAKE}, { PCI_CHIP_GEMINILAKE_I2C_2, "Intel Gemini Lake I2C Controller-2", IG4_GEMINILAKE}, { PCI_CHIP_GEMINILAKE_I2C_3, "Intel Gemini Lake I2C Controller-3", IG4_GEMINILAKE}, { PCI_CHIP_GEMINILAKE_I2C_4, "Intel Gemini Lake I2C Controller-4", IG4_GEMINILAKE}, { PCI_CHIP_GEMINILAKE_I2C_5, "Intel Gemini Lake I2C Controller-5", IG4_GEMINILAKE}, { PCI_CHIP_GEMINILAKE_I2C_6, "Intel Gemini Lake I2C Controller-6", IG4_GEMINILAKE}, { PCI_CHIP_GEMINILAKE_I2C_7, "Intel Gemini Lake I2C Controller-7", IG4_GEMINILAKE}, { PCI_CHIP_ALDERLAKE_P_I2C_0, "Intel Alder Lake-P I2C Controller-0", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_P_I2C_1, "Intel Alder Lake-P I2C Controller-1", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_P_I2C_2, "Intel Alder Lake-P I2C Controller-2", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_P_I2C_3, "Intel Alder Lake-P I2C Controller-3", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_P_I2C_4, "Intel Alder Lake-P I2C Controller-4", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_P_I2C_5, "Intel Alder Lake-P I2C Controller-5", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_P_I2C_6, "Intel Alder Lake-P I2C Controller-6", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_P_I2C_7, "Intel Alder Lake-P I2C Controller-7", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_S_I2C_0, "Intel Alder Lake-S I2C Controller-0", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_S_I2C_1, "Intel Alder Lake-S I2C Controller-1", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_S_I2C_2, "Intel Alder Lake-S I2C Controller-2", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_S_I2C_3, "Intel Alder Lake-S I2C Controller-3", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_S_I2C_4, "Intel Alder Lake-S I2C Controller-4", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_S_I2C_5, "Intel Alder Lake-S I2C Controller-5", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_M_I2C_0, "Intel Alder Lake-M I2C Controller-0", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_M_I2C_1, "Intel Alder Lake-M I2C Controller-1", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_M_I2C_2, "Intel Alder Lake-M I2C Controller-2", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_M_I2C_3, "Intel Alder Lake-M I2C Controller-3", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_M_I2C_4, "Intel Alder Lake-M I2C Controller-4", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_M_I2C_5, "Intel Alder Lake-M I2C Controller-5", IG4_TIGERLAKE}, + { PCI_CHIP_METEORLAKE_M_I2C_0, "Intel Meteor Lake-M I2C Controller-0", IG4_TIGERLAKE}, + { PCI_CHIP_METEORLAKE_M_I2C_1, "Intel Meteor Lake-M I2C Controller-1", IG4_TIGERLAKE}, + { PCI_CHIP_METEORLAKE_M_I2C_2, "Intel Meteor Lake-M I2C Controller-2", IG4_TIGERLAKE}, + { PCI_CHIP_METEORLAKE_M_I2C_3, "Intel Meteor Lake-M I2C Controller-3", IG4_TIGERLAKE}, }; static int ig4iic_pci_probe(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); uint32_t devid; int i; devid = pci_get_devid(dev); for (i = 0; i < nitems(ig4iic_pci_devices); i++) { if (ig4iic_pci_devices[i].devid == devid) { device_set_desc(dev, ig4iic_pci_devices[i].desc); sc->version = ig4iic_pci_devices[i].version; return (BUS_PROBE_DEFAULT); } } return (ENXIO); } static int ig4iic_pci_attach(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); int error; sc->dev = dev; sc->regs_rid = PCIR_BAR(0); sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regs_rid, RF_ACTIVE); if (sc->regs_res == NULL) { device_printf(dev, "unable to map registers\n"); ig4iic_pci_detach(dev); return (ENXIO); } sc->intr_rid = 0; if (pci_alloc_msi(dev, &sc->intr_rid)) { device_printf(dev, "Using MSI\n"); } sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); if (sc->intr_res == NULL) { device_printf(dev, "unable to map interrupt\n"); ig4iic_pci_detach(dev); return (ENXIO); } sc->platform_attached = true; error = ig4iic_attach(sc); if (error) ig4iic_pci_detach(dev); return (error); } static int ig4iic_pci_detach(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); int error; if (sc->platform_attached) { error = ig4iic_detach(sc); if (error) return (error); sc->platform_attached = false; } if (sc->intr_res) { bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, sc->intr_res); sc->intr_res = NULL; } if (sc->intr_rid != 0) pci_release_msi(dev); if (sc->regs_res) { bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, sc->regs_res); sc->regs_res = NULL; } return (0); } static int ig4iic_pci_suspend(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); return (ig4iic_suspend(sc)); } static int ig4iic_pci_resume(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); return (ig4iic_resume(sc)); } static device_method_t ig4iic_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ig4iic_pci_probe), DEVMETHOD(device_attach, ig4iic_pci_attach), DEVMETHOD(device_detach, ig4iic_pci_detach), DEVMETHOD(device_suspend, ig4iic_pci_suspend), DEVMETHOD(device_resume, ig4iic_pci_resume), /* Bus interface */ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), DEVMETHOD(bus_release_resource, bus_generic_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), /* iicbus interface */ DEVMETHOD(iicbus_transfer, ig4iic_transfer), DEVMETHOD(iicbus_reset, ig4iic_reset), DEVMETHOD(iicbus_callback, ig4iic_callback), DEVMETHOD_END }; static driver_t ig4iic_pci_driver = { "ig4iic", ig4iic_pci_methods, sizeof(struct ig4iic_softc) }; DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, 0, 0, SI_ORDER_ANY); MODULE_DEPEND(ig4iic, pci, 1, 1, 1); MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices, nitems(ig4iic_pci_devices)); diff --git a/sys/dev/ichsmb/ichsmb_pci.c b/sys/dev/ichsmb/ichsmb_pci.c index 675a15daaf1b..728bb942d503 100644 --- a/sys/dev/ichsmb/ichsmb_pci.c +++ b/sys/dev/ichsmb/ichsmb_pci.c @@ -1,325 +1,334 @@ /*- * ichsmb_pci.c * * Author: Archie Cobbs * Copyright (c) 2000 Whistle Communications, Inc. * All rights reserved. * Author: Archie Cobbs * * Subject to the following obligations and disclaimer of warranty, use and * redistribution of this software, in source or object code forms, with or * without modifications are expressly permitted by Whistle Communications; * provided, however, that: * 1. Any and all reproductions of the source or object code must include the * copyright notice above and the following disclaimer of warranties; and * 2. No rights are granted, in any manner or form, to use Whistle * Communications, Inc. trademarks, including the mark "WHISTLE * COMMUNICATIONS" on advertising, endorsements, or otherwise except as * such appears in the above copyright notice or in the software. * * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. */ #include /* * Support for the SMBus controller logical device which is part of the * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* PCI unique identifiers */ #define PCI_VENDOR_INTEL 0x8086 #define ID_82801AA 0x2413 #define ID_82801AB 0x2423 #define ID_82801BA 0x2443 #define ID_82801CA 0x2483 #define ID_82801DC 0x24C3 #define ID_82801EB 0x24D3 #define ID_82801FB 0x266A #define ID_82801GB 0x27da #define ID_82801H 0x283e #define ID_82801I 0x2930 #define ID_EP80579 0x5032 #define ID_82801JI 0x3a30 #define ID_82801JD 0x3a60 #define ID_PCH 0x3b30 #define ID_6300ESB 0x25a4 #define ID_631xESB 0x269b #define ID_DH89XXCC 0x2330 #define ID_PATSBURG 0x1d22 #define ID_CPT 0x1c22 #define ID_PPT 0x1e22 #define ID_AVOTON 0x1f3c #define ID_COLETOCRK 0x23B0 #define ID_LPT 0x8c22 #define ID_LPTLP 0x9c22 #define ID_WCPT 0x8ca2 #define ID_WCPTLP 0x9ca2 #define ID_BAYTRAIL 0x0f12 #define ID_BRASWELL 0x2292 #define ID_WELLSBURG 0x8d22 #define ID_SRPT 0xa123 #define ID_SRPTLP 0x9d23 #define ID_DENVERTON 0x19df #define ID_BROXTON 0x5ad4 #define ID_LEWISBURG 0xa1a3 #define ID_LEWISBURG2 0xa223 #define ID_KABYLAKE 0xa2a3 #define ID_CANNONLAKE 0xa323 #define ID_COMETLAKE 0x02a3 #define ID_COMETLAKE2 0x06a3 #define ID_TIGERLAKE 0xa0a3 #define ID_TIGERLAKE2 0x43a3 #define ID_GEMINILAKE 0x31d4 #define ID_CEDARFORK 0x18df #define ID_ICELAKE 0x34a3 #define ID_ALDERLAKE 0x7aa3 #define ID_ALDERLAKE2 0x51a3 #define ID_ALDERLAKE3 0x54a3 +#define ID_METEORLAKE 0x7e22 +#define ID_METEORLAKE2 0x7f23 +#define ID_METEORLAKE3 0xae22 static const struct pci_device_table ichsmb_devices[] = { { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AA), PCI_DESCR("Intel 82801AA (ICH) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AB), PCI_DESCR("Intel 82801AB (ICH0) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801BA), PCI_DESCR("Intel 82801BA (ICH2) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801CA), PCI_DESCR("Intel 82801CA (ICH3) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801DC), PCI_DESCR("Intel 82801DC (ICH4) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801EB), PCI_DESCR("Intel 82801EB (ICH5) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801FB), PCI_DESCR("Intel 82801FB (ICH6) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801GB), PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801H), PCI_DESCR("Intel 82801H (ICH8) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801I), PCI_DESCR("Intel 82801I (ICH9) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801GB), PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801H), PCI_DESCR("Intel 82801H (ICH8) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801I), PCI_DESCR("Intel 82801I (ICH9) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_EP80579), PCI_DESCR("Intel EP80579 SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801JI), PCI_DESCR("Intel 82801JI (ICH10) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_82801JD), PCI_DESCR("Intel 82801JD (ICH10) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_PCH), PCI_DESCR("Intel PCH SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_6300ESB), PCI_DESCR("Intel 6300ESB (ICH) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_631xESB), PCI_DESCR("Intel 631xESB/6321ESB (ESB2) SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_DH89XXCC), PCI_DESCR("Intel DH89xxCC SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_PATSBURG), PCI_DESCR("Intel Patsburg SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_CPT), PCI_DESCR("Intel Cougar Point SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_PPT), PCI_DESCR("Intel Panther Point SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_AVOTON), PCI_DESCR("Intel Avoton SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_LPT), PCI_DESCR("Intel Lynx Point SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_LPTLP), PCI_DESCR("Intel Lynx Point-LP SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_WCPT), PCI_DESCR("Intel Wildcat Point SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_WCPTLP), PCI_DESCR("Intel Wildcat Point-LP SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_BAYTRAIL), PCI_DESCR("Intel Baytrail SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_BRASWELL), PCI_DESCR("Intel Braswell SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_COLETOCRK), PCI_DESCR("Intel Coleto Creek SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_WELLSBURG), PCI_DESCR("Intel Wellsburg SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_SRPT), PCI_DESCR("Intel Sunrise Point-H SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_SRPTLP), PCI_DESCR("Intel Sunrise Point-LP SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_DENVERTON), PCI_DESCR("Intel Denverton SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_BROXTON), PCI_DESCR("Intel Broxton SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_LEWISBURG), PCI_DESCR("Intel Lewisburg SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_LEWISBURG2), PCI_DESCR("Intel Lewisburg SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_KABYLAKE), PCI_DESCR("Intel Kaby Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_CANNONLAKE), PCI_DESCR("Intel Cannon Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_COMETLAKE), PCI_DESCR("Intel Comet Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_COMETLAKE2), PCI_DESCR("Intel Comet Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_TIGERLAKE), PCI_DESCR("Intel Tiger Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_TIGERLAKE2), PCI_DESCR("Intel Tiger Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_GEMINILAKE), PCI_DESCR("Intel Gemini Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_CEDARFORK), PCI_DESCR("Intel Cedar Fork SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_ICELAKE), PCI_DESCR("Intel Ice Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE), PCI_DESCR("Intel Alder Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE2), PCI_DESCR("Intel Alder Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE3), PCI_DESCR("Intel Alder Lake SMBus controller") }, + { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE), + PCI_DESCR("Intel Meteor Lake SMBus controller") }, + { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE2), + PCI_DESCR("Intel Meteor Lake SMBus controller") }, + { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE3), + PCI_DESCR("Intel Meteor Lake SMBus controller") }, }; /* Internal functions */ static int ichsmb_pci_probe(device_t dev); static int ichsmb_pci_attach(device_t dev); /*Use generic one for now*/ #if 0 static int ichsmb_pci_detach(device_t dev); #endif /* Device methods */ static device_method_t ichsmb_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ichsmb_pci_probe), DEVMETHOD(device_attach, ichsmb_pci_attach), DEVMETHOD(device_detach, ichsmb_detach), /* SMBus methods */ DEVMETHOD(smbus_callback, ichsmb_callback), DEVMETHOD(smbus_quick, ichsmb_quick), DEVMETHOD(smbus_sendb, ichsmb_sendb), DEVMETHOD(smbus_recvb, ichsmb_recvb), DEVMETHOD(smbus_writeb, ichsmb_writeb), DEVMETHOD(smbus_writew, ichsmb_writew), DEVMETHOD(smbus_readb, ichsmb_readb), DEVMETHOD(smbus_readw, ichsmb_readw), DEVMETHOD(smbus_pcall, ichsmb_pcall), DEVMETHOD(smbus_bwrite, ichsmb_bwrite), DEVMETHOD(smbus_bread, ichsmb_bread), DEVMETHOD_END }; static driver_t ichsmb_pci_driver = { "ichsmb", ichsmb_pci_methods, sizeof(struct ichsmb_softc) }; DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, 0, 0); static int ichsmb_pci_probe(device_t dev) { const struct pci_device_table *tbl; tbl = PCI_MATCH(dev, ichsmb_devices); if (tbl == NULL) return (ENXIO); device_set_desc(dev, tbl->descr); return (ichsmb_probe(dev)); } static int ichsmb_pci_attach(device_t dev) { const sc_p sc = device_get_softc(dev); int error; /* Initialize private state */ bzero(sc, sizeof(*sc)); sc->ich_cmd = -1; sc->dev = dev; /* Allocate an I/O range */ sc->io_rid = ICH_SMB_BASE; sc->io_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, &sc->io_rid, 16, RF_ACTIVE); if (sc->io_res == NULL) sc->io_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, &sc->io_rid, 32, RF_ACTIVE); if (sc->io_res == NULL) { device_printf(dev, "can't map I/O\n"); error = ENXIO; goto fail; } /* Allocate interrupt */ sc->irq_rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE); if (sc->irq_res == NULL) { device_printf(dev, "can't get IRQ\n"); error = ENXIO; goto fail; } /* Enable device */ pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1); /* Done */ error = ichsmb_attach(dev); if (error) goto fail; return (0); fail: /* Attach failed, release resources */ ichsmb_release_resources(sc); return (error); } MODULE_DEPEND(ichsmb, pci, 1, 1, 1); MODULE_DEPEND(ichsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); MODULE_VERSION(ichsmb, 1); PCI_PNP_INFO(ichsmb_devices);