diff --git a/sys/arm/conf/std.qca b/sys/arm/conf/std.qca
index 00d627b77b7b..09cd61078870 100644
--- a/sys/arm/conf/std.qca
+++ b/sys/arm/conf/std.qca
@@ -1,34 +1,46 @@
 #
 # QCA SoC support (32 bit)
 #
 
 machine 	arm     armv7
 cpu 		CPU_CORTEXA
 makeoptions 	CONF_CFLAGS="-march=armv7a"
 
 files 		"../qualcomm/std.ipq4018"
 
 # Serial (COM) ports
 device 		uart
 device 		uart_msm	# Qualcomm MSM UART driver
 
+# EXT_RESOURCES pseudo devices
+options 	EXT_RESOURCES
+device 		clk
+device 		phy
+device 		hwreset
+device 		nvmem
+device 		regulator
+device 		syscon
+
 # Random
 device 		qcom_rnd
 
 device 		gic
 
 # MMC/SD/SDIO Card slot support
 device 		mmc
 device 		sdhci
 
 # Timers
 device 		generic_timer
 device 		mpcore_timer
 
 # PSCI - SMC calls, needed for qualcomm SCM
 device 		psci
 
+# Clock/Reset provider
+device 		qcom_gcc_ipq4018
+
 options 	FDT
 
 # Disable CP14 work in DDB as TZ won't let us by default
 options 	ARM_FORCE_DBG_MONITOR_DISABLE
diff --git a/sys/arm/qualcomm/qcom_gcc_ipq4018_clock.c b/sys/arm/qualcomm/qcom_gcc_ipq4018_clock.c
new file mode 100644
index 000000000000..f7f7a6c348ba
--- /dev/null
+++ b/sys/arm/qualcomm/qcom_gcc_ipq4018_clock.c
@@ -0,0 +1,82 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Driver for Qualcomm IPQ4018 clock and reset device */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/sglist.h>
+#include <sys/random.h>
+#include <sys/stdatomic.h>
+#include <sys/mutex.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+
+#include <arm/qualcomm/qcom_gcc_ipq4018_var.h>
+
+
+/*
+ * Fixed frequency clock sources:
+ *
+ * P_XO - 48MHz
+ * sleep-clk - is really 32KHz, although older DTS have it as 32.768KHz
+ */
+
+/*
+ * PLL derived sources:
+ *
+ * P_FEPLL125 - 125MHz
+ * P_FEPLL125DLY - 125MHz
+ * P_FEPLL200 - 200MHz
+ * P_FEPLL500 - 500MHz
+ * P_FEPLLWCSS2G - TBD
+ * P_FEPLLWCSS5G - TBD
+ *
+ * Then there are two DDR PLLs which are treated/configured slightly
+ * differently:
+ *
+ * P_DDRPLLAPSS - TBD
+ * P_DDRPLLSDCC - TBD
+ */
+
+/*
+ * Interesting stuff in Linux whilst I reverse engineer + figure it out:
+ * /sys/kernel/debug/clk
+ */
diff --git a/sys/arm/qualcomm/std.ipq4018 b/sys/arm/qualcomm/std.ipq4018
index 7e8ac39e7222..913314e92301 100644
--- a/sys/arm/qualcomm/std.ipq4018
+++ b/sys/arm/qualcomm/std.ipq4018
@@ -1,9 +1,10 @@
 arm/qualcomm/ipq4018_machdep.c		standard
 arm/qualcomm/ipq4018_mp.c		optional smp
 arm/qualcomm/qcom_scm_legacy.c		standard
 arm/qualcomm/qcom_cpu_kpssv2.c		optional smp
 
 dev/qcom_rnd/qcom_rnd.c			optional qcom_rnd
 arm/qualcomm/qcom_gcc_ipq4018.c		optional qcom_gcc_ipq4018
 arm/qualcomm/qcom_gcc_ipq4018_reset.c	optional qcom_gcc_ipq4018
+arm/qualcomm/qcom_gcc_ipq4018_clock.c	optional qcom_gcc_ipq4018