diff --git a/sys/mips/atheros/ar71xx_gpio.c b/sys/mips/atheros/ar71xx_gpio.c index 866c72b5b740..09b4d50124f4 100644 --- a/sys/mips/atheros/ar71xx_gpio.c +++ b/sys/mips/atheros/ar71xx_gpio.c @@ -1,446 +1,459 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2009, Luiz Otavio O Souza. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * GPIO driver for AR71xx */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include +#include #include #include "gpio_if.h" #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) struct ar71xx_gpio_pin { const char *name; int pin; int flags; }; static struct ar71xx_gpio_pin ar71xx_gpio_pins[] = { { "RFled", 2, GPIO_PIN_OUTPUT}, { "SW4", 8, GPIO_PIN_INPUT}, { NULL, 0, 0}, }; /* * Helpers */ static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask); static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask); static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin, uint32_t flags); /* * Driver stuff */ static int ar71xx_gpio_probe(device_t dev); static int ar71xx_gpio_attach(device_t dev); static int ar71xx_gpio_detach(device_t dev); static int ar71xx_gpio_filter(void *arg); static void ar71xx_gpio_intr(void *arg); /* * GPIO interface */ static int ar71xx_gpio_pin_max(device_t dev, int *maxpin); static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps); static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags); static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name); static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags); static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value); static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val); static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin); static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask) { GPIO_LOCK(sc); GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask); GPIO_UNLOCK(sc); } static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask) { GPIO_LOCK(sc); GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask); GPIO_UNLOCK(sc); } static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin, unsigned int flags) { uint32_t mask; mask = 1 << pin->gp_pin; GPIO_LOCK(sc); /* * Manage input/output */ if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); if (flags & GPIO_PIN_OUTPUT) { pin->gp_flags |= GPIO_PIN_OUTPUT; GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask); } else { pin->gp_flags |= GPIO_PIN_INPUT; GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask); } } GPIO_UNLOCK(sc); } static int ar71xx_gpio_pin_max(device_t dev, int *maxpin) { - *maxpin = AR71XX_GPIO_PINS - 1; + switch (ar71xx_soc) { + case AR71XX_SOC_AR9130: + case AR71XX_SOC_AR9132: + *maxpin = AR91XX_GPIO_PINS - 1; + break; + case AR71XX_SOC_AR7240: + case AR71XX_SOC_AR7241: + case AR71XX_SOC_AR7242: + *maxpin = AR724X_GPIO_PINS - 1; + break; + default: + *maxpin = AR71XX_GPIO_PINS - 1; + } return (0); } static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { struct ar71xx_gpio_softc *sc = device_get_softc(dev); int i; for (i = 0; i < sc->gpio_npins; i++) { if (sc->gpio_pins[i].gp_pin == pin) break; } if (i >= sc->gpio_npins) return (EINVAL); GPIO_LOCK(sc); *caps = sc->gpio_pins[i].gp_caps; GPIO_UNLOCK(sc); return (0); } static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { struct ar71xx_gpio_softc *sc = device_get_softc(dev); int i; for (i = 0; i < sc->gpio_npins; i++) { if (sc->gpio_pins[i].gp_pin == pin) break; } if (i >= sc->gpio_npins) return (EINVAL); GPIO_LOCK(sc); *flags = sc->gpio_pins[i].gp_flags; GPIO_UNLOCK(sc); return (0); } static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { struct ar71xx_gpio_softc *sc = device_get_softc(dev); int i; for (i = 0; i < sc->gpio_npins; i++) { if (sc->gpio_pins[i].gp_pin == pin) break; } if (i >= sc->gpio_npins) return (EINVAL); GPIO_LOCK(sc); memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME); GPIO_UNLOCK(sc); return (0); } static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { int i; struct ar71xx_gpio_softc *sc = device_get_softc(dev); for (i = 0; i < sc->gpio_npins; i++) { if (sc->gpio_pins[i].gp_pin == pin) break; } if (i >= sc->gpio_npins) return (EINVAL); /* Filter out unwanted flags */ if ((flags &= sc->gpio_pins[i].gp_caps) != flags) return (EINVAL); /* Can't mix input/output together */ if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) return (EINVAL); ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags); return (0); } static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct ar71xx_gpio_softc *sc = device_get_softc(dev); int i; for (i = 0; i < sc->gpio_npins; i++) { if (sc->gpio_pins[i].gp_pin == pin) break; } if (i >= sc->gpio_npins) return (EINVAL); GPIO_LOCK(sc); if (value) GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin)); else GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin)); GPIO_UNLOCK(sc); return (0); } static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { struct ar71xx_gpio_softc *sc = device_get_softc(dev); int i; for (i = 0; i < sc->gpio_npins; i++) { if (sc->gpio_pins[i].gp_pin == pin) break; } if (i >= sc->gpio_npins) return (EINVAL); GPIO_LOCK(sc); *val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0; GPIO_UNLOCK(sc); return (0); } static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin) { int res, i; struct ar71xx_gpio_softc *sc = device_get_softc(dev); for (i = 0; i < sc->gpio_npins; i++) { if (sc->gpio_pins[i].gp_pin == pin) break; } if (i >= sc->gpio_npins) return (EINVAL); GPIO_LOCK(sc); res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0; if (res) GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin)); else GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin)); GPIO_UNLOCK(sc); return (0); } static int ar71xx_gpio_filter(void *arg) { /* TODO: something useful */ return (FILTER_STRAY); } static void ar71xx_gpio_intr(void *arg) { struct ar71xx_gpio_softc *sc = arg; GPIO_LOCK(sc); /* TODO: something useful */ GPIO_UNLOCK(sc); } static int ar71xx_gpio_probe(device_t dev) { device_set_desc(dev, "Atheros AR71XX GPIO driver"); return (0); } static int ar71xx_gpio_attach(device_t dev) { struct ar71xx_gpio_softc *sc = device_get_softc(dev); int error = 0; struct ar71xx_gpio_pin *pinp; int i; KASSERT((device_get_unit(dev) == 0), ("ar71xx_gpio: Only one gpio module supported")); mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); /* Map control/status registers. */ sc->gpio_mem_rid = 0; sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->gpio_mem_rid, RF_ACTIVE); if (sc->gpio_mem_res == NULL) { device_printf(dev, "couldn't map memory\n"); error = ENXIO; ar71xx_gpio_detach(dev); return(error); } if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { device_printf(dev, "unable to allocate IRQ resource\n"); return (ENXIO); } if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC, ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) { device_printf(dev, "WARNING: unable to register interrupt handler\n"); return (ENXIO); } sc->dev = dev; ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS1_EN); ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS2_EN); /* Configure all pins as input */ /* disable interrupts for all pins */ GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0); pinp = ar71xx_gpio_pins; i = 0; while (pinp->name) { strncpy(sc->gpio_pins[i].gp_name, pinp->name, GPIOMAXNAME); sc->gpio_pins[i].gp_pin = pinp->pin; sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; sc->gpio_pins[i].gp_flags = 0; ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], pinp->flags); pinp++; i++; } sc->gpio_npins = i; device_add_child(dev, "gpioc", device_get_unit(dev)); device_add_child(dev, "gpiobus", device_get_unit(dev)); return (bus_generic_attach(dev)); } static int ar71xx_gpio_detach(device_t dev) { struct ar71xx_gpio_softc *sc = device_get_softc(dev); KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized")); ar71xx_gpio_function_disable(sc, GPIO_FUNC_SPI_CS1_EN); ar71xx_gpio_function_disable(sc, GPIO_FUNC_SPI_CS2_EN); bus_generic_detach(dev); if (sc->gpio_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid, sc->gpio_mem_res); mtx_destroy(&sc->gpio_mtx); return(0); } static device_method_t ar71xx_gpio_methods[] = { DEVMETHOD(device_probe, ar71xx_gpio_probe), DEVMETHOD(device_attach, ar71xx_gpio_attach), DEVMETHOD(device_detach, ar71xx_gpio_detach), /* GPIO protocol */ DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max), DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname), DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags), DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps), DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags), DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get), DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle), {0, 0}, }; static driver_t ar71xx_gpio_driver = { "gpio", ar71xx_gpio_methods, sizeof(struct ar71xx_gpio_softc), }; static devclass_t ar71xx_gpio_devclass; DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0); diff --git a/sys/mips/atheros/ar71xx_gpiovar.h b/sys/mips/atheros/ar71xx_gpiovar.h index a9ed7e074221..3489f5a7aea5 100644 --- a/sys/mips/atheros/ar71xx_gpiovar.h +++ b/sys/mips/atheros/ar71xx_gpiovar.h @@ -1,68 +1,70 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2009, Luiz Otavio O Souza. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef __AR71XX_GPIOVAR_H__ #define __AR71XX_GPIOVAR_H__ #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx) #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx) #define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED) /* * register space access macros */ #define GPIO_WRITE(sc, reg, val) do { \ bus_write_4(sc->gpio_mem_res, (reg), (val)); \ } while (0) #define GPIO_READ(sc, reg) bus_read_4(sc->gpio_mem_res, (reg)) #define GPIO_SET_BITS(sc, reg, bits) \ GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) | (bits)) #define GPIO_CLEAR_BITS(sc, reg, bits) \ GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) & ~(bits)) #define AR71XX_GPIO_PINS 12 +#define AR724X_GPIO_PINS 18 +#define AR91XX_GPIO_PINS 22 struct ar71xx_gpio_softc { device_t dev; struct mtx gpio_mtx; struct resource *gpio_mem_res; int gpio_mem_rid; struct resource *gpio_irq_res; int gpio_irq_rid; void *gpio_ih; int gpio_npins; struct gpio_pin gpio_pins[AR71XX_GPIO_PINS]; }; #endif /* __AR71XX_GPIOVAR_H__ */ diff --git a/sys/mips/atheros/ar724xreg.h b/sys/mips/atheros/ar724xreg.h index eaceb1d61886..73e20afe95d2 100644 --- a/sys/mips/atheros/ar724xreg.h +++ b/sys/mips/atheros/ar724xreg.h @@ -1,110 +1,108 @@ /*- * Copyright (c) 2010 Adrian Chadd * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* $FreeBSD$ */ #ifndef __AR72XX_REG_H__ #define __AR72XX_REG_H__ #define AR724X_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 #define AR724X_PLL_REG_PCIE_CONFIG AR71XX_PLL_CPU_BASE + 0x18 #define AR724X_PLL_DIV_SHIFT 0 #define AR724X_PLL_DIV_MASK 0x3ff #define AR724X_PLL_REF_DIV_SHIFT 10 #define AR724X_PLL_REF_DIV_MASK 0xf #define AR724X_AHB_DIV_SHIFT 19 #define AR724X_AHB_DIV_MASK 0x1 #define AR724X_DDR_DIV_SHIFT 22 #define AR724X_DDR_DIV_MASK 0x3 #define AR724X_PLL_VAL_1000 0x00110000 #define AR724X_PLL_VAL_100 0x00001099 #define AR724X_PLL_VAL_10 0x00991099 #define AR724X_BASE_FREQ 5000000 #define AR724X_DDR_REG_FLUSH_GE0 (AR71XX_DDR_CONFIG + 0x7c) #define AR724X_DDR_REG_FLUSH_GE1 (AR71XX_DDR_CONFIG + 0x80) #define AR724X_DDR_REG_FLUSH_USB (AR71XX_DDR_CONFIG + 0x84) #define AR724X_DDR_REG_FLUSH_PCIE (AR71XX_DDR_CONFIG + 0x88) #define AR724X_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c #define AR724X_RESET_USB_HOST (1 << 5) #define AR724X_RESET_USB_PHY (1 << 4) #define AR724X_RESET_MODULE_USB_OHCI_DLL (1 << 3) #define AR724X_RESET_GE1_MDIO (1 << 23) #define AR724X_RESET_GE0_MDIO (1 << 22) #define AR724X_RESET_PCIE_PHY_SERIAL (1 << 10) #define AR724X_RESET_PCIE_PHY (1 << 7) #define AR724X_RESET_PCIE (1 << 6) #define AR724X_RESET_USB_HOST (1 << 5) #define AR724X_RESET_USB_PHY (1 << 4) #define AR724X_RESET_USBSUS_OVERRIDE (1 << 3) /* XXX so USB requires different init code? -adrian */ #define AR7240_OHCI_BASE 0x1b000000 #define AR7240_OHCI_SIZE 0x01000000 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) #define AR724X_PCI_CRP_SIZE 0x100 #define AR724X_PCI_CFG_BASE 0x14000000 #define AR724X_PCI_CFG_SIZE 0x1000 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) #define AR724X_PCI_CTRL_SIZE 0x100 /* PCI config registers */ #define AR724X_PCI_APP 0x180f0000 #define AR724X_PCI_APP_LTSSM_ENABLE (1 << 0) #define AR724X_PCI_RESET 0x180f0018 #define AR724X_PCI_RESET_LINK_UP (1 << 0) #define AR724X_PCI_INTR_STATUS 0x180f004c #define AR724X_PCI_INTR_MASK 0x180f0050 #define AR724X_PCI_INTR_DEV0 (1 << 14) #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN (1 >> 19) #define AR724X_GPIO_FUNC_SPI_EN (1 >> 18) #define AR724X_GPIO_FUNC_SPI_CS_EN2 (1 >> 14) #define AR724X_GPIO_FUNC_SPI_CS_EN1 (1 >> 13) #define AR724X_GPIO_FUNC_CLK_OBS5_EN (1 >> 12) #define AR724X_GPIO_FUNC_CLK_OBS4_EN (1 >> 11) #define AR724X_GPIO_FUNC_CLK_OBS3_EN (1 >> 10) #define AR724X_GPIO_FUNC_CLK_OBS2_EN (1 >> 9) #define AR724X_GPIO_FUNC_CLK_OBS1_EN (1 >> 8) #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN (1 >> 7) #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN (1 >> 6) #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN (1 >> 5) #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN (1 >> 4) #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN (1 >> 3) #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN (1 >> 2) #define AR724X_GPIO_FUNC_UART_EN (1 >> 1) #define AR724X_GPIO_FUNC_JTAG_DISABLE (1 >> 0) -#define AR724X_GPIO_COUNT 18 - #endif diff --git a/sys/mips/atheros/ar91xxreg.h b/sys/mips/atheros/ar91xxreg.h index 729d9ffcf7d0..2dfaeb5936c0 100644 --- a/sys/mips/atheros/ar91xxreg.h +++ b/sys/mips/atheros/ar91xxreg.h @@ -1,86 +1,84 @@ /*- * Copyright (c) 2010 Adrian Chadd * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* $FreeBSD$ */ #ifndef __AR91XX_REG_H__ #define __AR91XX_REG_H__ #define AR91XX_BASE_FREQ 5000000 /* reset block */ #define AR91XX_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c #define AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE (1 << 10) #define AR91XX_RST_RESET_MODULE_AMBA2WMAC (1 << 22) /* PLL block */ #define AR91XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 #define AR91XX_PLL_REG_ETH_CONFIG AR71XX_PLL_CPU_BASE + 0x04 #define AR91XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14 #define AR91XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x18 #define AR91XX_PLL_DIV_SHIFT 0 #define AR91XX_PLL_DIV_MASK 0x3ff #define AR91XX_DDR_DIV_SHIFT 22 #define AR91XX_DDR_DIV_MASK 0x3 #define AR91XX_AHB_DIV_SHIFT 19 #define AR91XX_AHB_DIV_MASK 0x1 #define AR91XX_ETH0_PLL_SHIFT 20 #define AR91XX_ETH1_PLL_SHIFT 22 #define AR91XX_PLL_VAL_1000 0x1a000000 #define AR91XX_PLL_VAL_100 0x13000a44 #define AR91XX_PLL_VAL_10 0x00441099 /* DDR block */ #define AR91XX_DDR_CTRLBASE (AR71XX_APB_BASE + 0) #define AR91XX_DDR_CTRL_SIZE 0x10000 #define AR91XX_DDR_REG_FLUSH_GE0 AR91XX_DDR_CTRLBASE + 0x7c #define AR91XX_DDR_REG_FLUSH_GE1 AR91XX_DDR_CTRLBASE + 0x80 #define AR91XX_DDR_REG_FLUSH_USB AR91XX_DDR_CTRLBASE + 0x84 #define AR91XX_DDR_REG_FLUSH_WMAC AR91XX_DDR_CTRLBASE + 0x88 /* WMAC stuff */ #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) #define AR91XX_WMAC_SIZE 0x30000 /* GPIO stuff */ #define AR91XX_GPIO_FUNC_WMAC_LED_EN (1 << 22) #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN (1 << 21) #define AR91XX_GPIO_FUNC_I2S_REFCLKEN (1 << 20) #define AR91XX_GPIO_FUNC_I2S_MCKEN (1 << 19) #define AR91XX_GPIO_FUNC_I2S1_EN (1 << 18) #define AR91XX_GPIO_FUNC_I2S0_EN (1 << 17) #define AR91XX_GPIO_FUNC_SLIC_EN (1 << 16) #define AR91XX_GPIO_FUNC_UART_RTSCTS_EN (1 << 9) #define AR91XX_GPIO_FUNC_UART_EN (1 << 8) #define AR91XX_GPIO_FUNC_USB_CLK_EN (1 << 4) -#define AR91XX_GPIO_COUNT 22 - #endif