diff --git a/sys/arm/allwinner/a33_codec.c b/sys/arm/allwinner/a33_codec.c new file mode 100644 index 000000000000..2b3d5f6ef01c --- /dev/null +++ b/sys/arm/allwinner/a33_codec.c @@ -0,0 +1,417 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Oleksandr Tymoshenko + * Copyright (c) 2018 Jared McNeill + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include "opt_snd.h" +#include +#include +#include "audio_dai_if.h" + +#define SYSCLK_CTL 0x00c +#define AIF1CLK_ENA (1 << 11) +#define AIF1CLK_SRC_MASK (3 << 8) +#define AIF1CLK_SRC_PLL (2 << 8) +#define SYSCLK_ENA (1 << 3) +#define SYSCLK_SRC (1 << 0) + +#define MOD_CLK_ENA 0x010 +#define MOD_RST_CTL 0x014 +#define MOD_AIF1 (1 << 15) +#define MOD_ADC (1 << 3) +#define MOD_DAC (1 << 2) + +#define SYS_SR_CTRL 0x018 +#define AIF1_FS_MASK (0xf << 12) +#define AIF_FS_48KHZ (8 << 12) + +#define AIF1CLK_CTRL 0x040 +#define AIF1_MSTR_MOD (1 << 15) +#define AIF1_BCLK_INV (1 << 14) +#define AIF1_LRCK_INV (1 << 13) +#define AIF1_BCLK_DIV_MASK (0xf << 9) +#define AIF1_BCLK_DIV_16 (6 << 9) +#define AIF1_LRCK_DIV_MASK (7 << 6) +#define AIF1_LRCK_DIV_16 (0 << 6) +#define AIF1_LRCK_DIV_64 (2 << 6) +#define AIF1_WORD_SIZ_MASK (3 << 4) +#define AIF1_WORD_SIZ_16 (1 << 4) +#define AIF1_DATA_FMT_MASK (3 << 2) +#define AIF1_DATA_FMT_I2S (0 << 2) +#define AIF1_DATA_FMT_LJ (1 << 2) +#define AIF1_DATA_FMT_RJ (2 << 2) +#define AIF1_DATA_FMT_DSP (3 << 2) + +#define AIF1_ADCDAT_CTRL 0x044 +#define AIF1_ADC0L_ENA (1 << 15) +#define AIF1_ADC0R_ENA (1 << 14) + +#define AIF1_DACDAT_CTRL 0x048 +#define AIF1_DAC0L_ENA (1 << 15) +#define AIF1_DAC0R_ENA (1 << 14) + +#define AIF1_MXR_SRC 0x04c +#define AIF1L_MXR_SRC_MASK (0xf << 12) +#define AIF1L_MXR_SRC_AIF1 (0x8 << 12) +#define AIF1L_MXR_SRC_ADC (0x2 << 12) +#define AIF1R_MXR_SRC_MASK (0xf << 8) +#define AIF1R_MXR_SRC_AIF1 (0x8 << 8) +#define AIF1R_MXR_SRC_ADC (0x2 << 8) + +#define ADC_DIG_CTRL 0x100 +#define ADC_DIG_CTRL_ENAD (1 << 15) + +#define HMIC_CTRL1 0x110 +#define HMIC_CTRL1_N_MASK (0xf << 8) +#define HMIC_CTRL1_N(n) (((n) & 0xf) << 8) +#define HMIC_CTRL1_JACK_IN_IRQ_EN (1 << 4) +#define HMIC_CTRL1_JACK_OUT_IRQ_EN (1 << 3) +#define HMIC_CTRL1_MIC_DET_IRQ_EN (1 << 0) + +#define HMIC_CTRL2 0x114 +#define HMIC_CTRL2_MDATA_THRES __BITS(12,8) + +#define HMIC_STS 0x118 +#define HMIC_STS_MIC_PRESENT (1 << 6) +#define HMIC_STS_JACK_DET_OIRQ (1 << 4) +#define HMIC_STS_JACK_DET_IIRQ (1 << 3) +#define HMIC_STS_MIC_DET_ST (1 << 0) + +#define DAC_DIG_CTRL 0x120 +#define DAC_DIG_CTRL_ENDA (1 << 15) + +#define DAC_MXR_SRC 0x130 +#define DACL_MXR_SRC_MASK (0xf << 12) +#define DACL_MXR_SRC_AIF1_DAC0L (0x8 << 12) +#define DACR_MXR_SRC_MASK (0xf << 8) +#define DACR_MXR_SRC_AIF1_DAC0R (0x8 << 8) + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun8i-a33-codec", 1}, + { NULL, 0 } +}; + +static struct resource_spec sun8i_codec_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0 } +}; + +struct sun8i_codec_softc { + device_t dev; + struct resource *res[2]; + struct mtx mtx; + clk_t clk_gate; + clk_t clk_mod; + void * intrhand; +}; + +#define CODEC_LOCK(sc) mtx_lock(&(sc)->mtx) +#define CODEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) +#define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) + +static int sun8i_codec_probe(device_t dev); +static int sun8i_codec_attach(device_t dev); +static int sun8i_codec_detach(device_t dev); + +static int +sun8i_codec_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Allwinner Codec"); + return (BUS_PROBE_DEFAULT); +} + +static int +sun8i_codec_attach(device_t dev) +{ + struct sun8i_codec_softc *sc; + int error; + uint32_t val; + struct gpiobus_pin *pa_pin; + phandle_t node; + + sc = device_get_softc(dev); + sc->dev = dev; + node = ofw_bus_get_node(dev); + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + if (bus_alloc_resources(dev, sun8i_codec_spec, sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + error = ENXIO; + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_mod); + if (error != 0) { + device_printf(dev, "cannot get \"mod\" clock\n"); + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "bus", &sc->clk_gate); + if (error != 0) { + device_printf(dev, "cannot get \"bus\" clock\n"); + goto fail; + } + + error = clk_enable(sc->clk_gate); + if (error != 0) { + device_printf(dev, "cannot enable \"bus\" clock\n"); + goto fail; + } + + /* Enable clocks */ + val = CODEC_READ(sc, SYSCLK_CTL); + val |= AIF1CLK_ENA; + val &= ~AIF1CLK_SRC_MASK; + val |= AIF1CLK_SRC_PLL; + val |= SYSCLK_ENA; + val &= ~SYSCLK_SRC; + CODEC_WRITE(sc, SYSCLK_CTL, val); + CODEC_WRITE(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC); + CODEC_WRITE(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC); + + /* Enable digital parts */ + CODEC_WRITE(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA); + CODEC_WRITE(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD); + + /* Set AIF1 to 48 kHz */ + val = CODEC_READ(sc, SYS_SR_CTRL); + val &= ~AIF1_FS_MASK; + val |= AIF_FS_48KHZ; + CODEC_WRITE(sc, SYS_SR_CTRL, val); + + /* Set AIF1 to 16-bit */ + val = CODEC_READ(sc, AIF1CLK_CTRL); + val &= ~AIF1_WORD_SIZ_MASK; + val |= AIF1_WORD_SIZ_16; + CODEC_WRITE(sc, AIF1CLK_CTRL, val); + + /* Enable AIF1 DAC timelot 0 */ + val = CODEC_READ(sc, AIF1_DACDAT_CTRL); + val |= AIF1_DAC0L_ENA; + val |= AIF1_DAC0R_ENA; + CODEC_WRITE(sc, AIF1_DACDAT_CTRL, val); + + /* Enable AIF1 ADC timelot 0 */ + val = CODEC_READ(sc, AIF1_ADCDAT_CTRL); + val |= AIF1_ADC0L_ENA; + val |= AIF1_ADC0R_ENA; + CODEC_WRITE(sc, AIF1_ADCDAT_CTRL, val); + + /* DAC mixer source select */ + val = CODEC_READ(sc, DAC_MXR_SRC); + val &= ~DACL_MXR_SRC_MASK; + val |= DACL_MXR_SRC_AIF1_DAC0L; + val &= ~DACR_MXR_SRC_MASK; + val |= DACR_MXR_SRC_AIF1_DAC0R; + CODEC_WRITE(sc, DAC_MXR_SRC, val); + + /* ADC mixer source select */ + val = CODEC_READ(sc, AIF1_MXR_SRC); + val &= ~AIF1L_MXR_SRC_MASK; + val |= AIF1L_MXR_SRC_ADC; + val &= ~AIF1R_MXR_SRC_MASK; + val |= AIF1R_MXR_SRC_ADC; + CODEC_WRITE(sc, AIF1_MXR_SRC, val); + + /* Enable PA power */ + /* Unmute PA */ + if (gpio_pin_get_by_ofw_property(dev, node, "allwinner,pa-gpios", + &pa_pin) == 0) { + error = gpio_pin_set_active(pa_pin, 1); + if (error != 0) + device_printf(dev, "failed to unmute PA\n"); + } + + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); + +fail: + sun8i_codec_detach(dev); + return (error); +} + +static int +sun8i_codec_detach(device_t dev) +{ + struct sun8i_codec_softc *sc; + + sc = device_get_softc(dev); + + if (sc->clk_gate) + clk_release(sc->clk_gate); + + if (sc->clk_mod) + clk_release(sc->clk_mod); + + if (sc->intrhand != NULL) + bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand); + + bus_release_resources(dev, sun8i_codec_spec, sc->res); + mtx_destroy(&sc->mtx); + + return (0); +} + +static int +sun8i_codec_dai_init(device_t dev, uint32_t format) +{ + struct sun8i_codec_softc *sc; + int fmt, pol, clk; + uint32_t val; + + sc = device_get_softc(dev); + + fmt = AUDIO_DAI_FORMAT_FORMAT(format); + pol = AUDIO_DAI_FORMAT_POLARITY(format); + clk = AUDIO_DAI_FORMAT_CLOCK(format); + + val = CODEC_READ(sc, AIF1CLK_CTRL); + + val &= ~AIF1_DATA_FMT_MASK; + switch (fmt) { + case AUDIO_DAI_FORMAT_I2S: + val |= AIF1_DATA_FMT_I2S; + break; + case AUDIO_DAI_FORMAT_RJ: + val |= AIF1_DATA_FMT_RJ; + break; + case AUDIO_DAI_FORMAT_LJ: + val |= AIF1_DATA_FMT_LJ; + break; + case AUDIO_DAI_FORMAT_DSPA: + case AUDIO_DAI_FORMAT_DSPB: + val |= AIF1_DATA_FMT_DSP; + break; + default: + return EINVAL; + } + + val &= ~(AIF1_BCLK_INV|AIF1_LRCK_INV); + /* Codec LRCK polarity is inverted (datasheet is wrong) */ + if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) + val |= AIF1_LRCK_INV; + if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) + val |= AIF1_BCLK_INV; + + switch (clk) { + case AUDIO_DAI_CLOCK_CBM_CFM: + val &= ~AIF1_MSTR_MOD; /* codec is master */ + break; + case AUDIO_DAI_CLOCK_CBS_CFS: + val |= AIF1_MSTR_MOD; /* codec is slave */ + break; + default: + return EINVAL; + } + + val &= ~AIF1_LRCK_DIV_MASK; + val |= AIF1_LRCK_DIV_64; + + val &= ~AIF1_BCLK_DIV_MASK; + val |= AIF1_BCLK_DIV_16; + + CODEC_WRITE(sc, AIF1CLK_CTRL, val); + + return (0); +} + +static int +sun8i_codec_dai_trigger(device_t dev, int go, int pcm_dir) +{ + + return (0); +} + +static int +sun8i_codec_dai_setup_mixer(device_t dev, device_t pcmdev) +{ + struct sun8i_codec_softc *sc; + + sc = device_get_softc(dev); + /* Do nothing for now */ + + return (0); +} + + +static device_method_t sun8i_codec_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, sun8i_codec_probe), + DEVMETHOD(device_attach, sun8i_codec_attach), + DEVMETHOD(device_detach, sun8i_codec_detach), + + DEVMETHOD(audio_dai_init, sun8i_codec_dai_init), + DEVMETHOD(audio_dai_setup_mixer, sun8i_codec_dai_setup_mixer), + DEVMETHOD(audio_dai_trigger, sun8i_codec_dai_trigger), + + DEVMETHOD_END +}; + +static driver_t sun8i_codec_driver = { + "sun8icodec", + sun8i_codec_methods, + sizeof(struct sun8i_codec_softc), +}; + +static devclass_t sun8i_codec_devclass; + +DRIVER_MODULE(sun8i_codec, simplebus, sun8i_codec_driver, sun8i_codec_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); diff --git a/sys/arm/allwinner/a64/sun50i_a64_acodec.c b/sys/arm/allwinner/a64/sun50i_a64_acodec.c new file mode 100644 index 000000000000..10febf98abd8 --- /dev/null +++ b/sys/arm/allwinner/a64/sun50i_a64_acodec.c @@ -0,0 +1,488 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Oleksandr Tymoshenko + * Copyright (c) 2018 Jared McNeill + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include "syscon_if.h" + +#include "opt_snd.h" +#include +#include +#include "audio_dai_if.h" +#include "mixer_if.h" + +#define A64_PR_CFG 0x00 +#define A64_AC_PR_RST (1 << 28) +#define A64_AC_PR_RW (1 << 24) +#define A64_AC_PR_ADDR_MASK (0x1f << 16) +#define A64_AC_PR_ADDR(n) (((n) & 0x1f) << 16) +#define A64_ACDA_PR_WDAT_MASK (0xff << 8) +#define A64_ACDA_PR_WDAT(n) (((n) & 0xff) << 8) +#define A64_ACDA_PR_RDAT(n) ((n) & 0xff) + +#define A64_HP_CTRL 0x00 +#define A64_HPPA_EN (1 << 6) +#define A64_HPVOL_MASK 0x3f +#define A64_HPVOL(n) ((n) & 0x3f) +#define A64_OL_MIX_CTRL 0x01 +#define A64_LMIXMUTE_LDAC (1 << 1) +#define A64_OR_MIX_CTRL 0x02 +#define A64_RMIXMUTE_RDAC (1 << 1) +#define A64_LINEOUT_CTRL0 0x05 +#define A64_LINEOUT_LEFT_EN (1 << 7) +#define A64_LINEOUT_RIGHT_EN (1 << 6) +#define A64_LINEOUT_EN (A64_LINEOUT_LEFT_EN|A64_LINEOUT_RIGHT_EN) +#define A64_LINEOUT_CTRL1 0x06 +#define A64_LINEOUT_VOL __BITS(4,0) +#define A64_MIC1_CTRL 0x07 +#define A64_MIC1G __BITS(6,4) +#define A64_MIC1AMPEN (1 << 3) +#define A64_MIC1BOOST __BITS(2,0) +#define A64_MIC2_CTRL 0x08 +#define A64_MIC2_SEL (1 << 7) +#define A64_MIC2G_MASK (7 << 4) +#define A64_MIC2G(n) (((n) & 7) << 4) +#define A64_MIC2AMPEN (1 << 3) +#define A64_MIC2BOOST_MASK (7 << 0) +#define A64_MIC2BOOST(n) (((n) & 7) << 0) +#define A64_LINEIN_CTRL 0x09 +#define A64_LINEING __BITS(6,4) +#define A64_MIX_DAC_CTRL 0x0a +#define A64_DACAREN (1 << 7) +#define A64_DACALEN (1 << 6) +#define A64_RMIXEN (1 << 5) +#define A64_LMIXEN (1 << 4) +#define A64_RHPPAMUTE (1 << 3) +#define A64_LHPPAMUTE (1 << 2) +#define A64_RHPIS (1 << 1) +#define A64_LHPIS (1 << 0) +#define A64_L_ADCMIX_SRC 0x0b +#define A64_R_ADCMIX_SRC 0x0c +#define A64_ADCMIX_SRC_MIC1 (1 << 6) +#define A64_ADCMIX_SRC_MIC2 (1 << 5) +#define A64_ADCMIX_SRC_LINEIN (1 << 2) +#define A64_ADCMIX_SRC_OMIXER (1 << 1) +#define A64_ADC_CTRL 0x0d +#define A64_ADCREN (1 << 7) +#define A64_ADCLEN (1 << 6) +#define A64_ADCG __BITS(2,0) +#define A64_JACK_MIC_CTRL 0x1d +#define A64_JACKDETEN (1 << 7) +#define A64_INNERRESEN (1 << 6) +#define A64_HMICBIASEN (1 << 5) +#define A64_AUTOPLEN (1 << 1) + +#define A64CODEC_MIXER_DEVS ((1 << SOUND_MIXER_VOLUME) | \ + (1 << SOUND_MIXER_MIC)) + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun50i-a64-codec-analog", 1}, + { NULL, 0 } +}; + +struct a64codec_softc { + device_t dev; + struct resource *res; + struct mtx mtx; + u_int regaddr; /* address for the sysctl */ +}; + +#define A64CODEC_LOCK(sc) mtx_lock(&(sc)->mtx) +#define A64CODEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define A64CODEC_READ(sc, reg) bus_read_4((sc)->res, (reg)) +#define A64CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) + +static int a64codec_probe(device_t dev); +static int a64codec_attach(device_t dev); +static int a64codec_detach(device_t dev); + +static u_int +a64_acodec_pr_read(struct a64codec_softc *sc, u_int addr) +{ + uint32_t val; + + /* Read current value */ + val = A64CODEC_READ(sc, A64_PR_CFG); + + /* De-assert reset */ + val |= A64_AC_PR_RST; + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Read mode */ + val &= ~A64_AC_PR_RW; + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Set address */ + val &= ~A64_AC_PR_ADDR_MASK; + val |= A64_AC_PR_ADDR(addr); + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Read data */ + val = A64CODEC_READ(sc, A64_PR_CFG); + return A64_ACDA_PR_RDAT(val); +} + +static void +a64_acodec_pr_write(struct a64codec_softc *sc, u_int addr, u_int data) +{ + uint32_t val; + + /* Read current value */ + val = A64CODEC_READ(sc, A64_PR_CFG); + + /* De-assert reset */ + val |= A64_AC_PR_RST; + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Set address */ + val &= ~A64_AC_PR_ADDR_MASK; + val |= A64_AC_PR_ADDR(addr); + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Write data */ + val &= ~A64_ACDA_PR_WDAT_MASK; + val |= A64_ACDA_PR_WDAT(data); + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Write mode */ + val |= A64_AC_PR_RW; + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Clear write mode */ + val &= ~A64_AC_PR_RW; + A64CODEC_WRITE(sc, A64_PR_CFG, val); +} + +static void +a64_acodec_pr_set_clear(struct a64codec_softc *sc, u_int addr, u_int set, u_int clr) +{ + u_int old, new; + + old = a64_acodec_pr_read(sc, addr); + new = set | (old & ~clr); + a64_acodec_pr_write(sc, addr, new); +} + +static int +a64codec_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Allwinner A64 Analog Codec"); + return (BUS_PROBE_DEFAULT); +} + +static int +a64codec_attach(device_t dev) +{ + struct a64codec_softc *sc; + int error, rid; + phandle_t node; + regulator_t reg; + + sc = device_get_softc(dev); + sc->dev = dev; + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + rid = 0; + sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (!sc->res) { + device_printf(dev, "cannot allocate resource for device\n"); + error = ENXIO; + goto fail; + } + + if (regulator_get_by_ofw_property(dev, 0, "cpvdd-supply", ®) == 0) { + error = regulator_enable(reg); + if (error != 0) { + device_printf(dev, "cannot enable PHY regulator\n"); + goto fail; + } + } + + /* Right & Left Headphone PA enable */ + a64_acodec_pr_set_clear(sc, A64_HP_CTRL, + A64_HPPA_EN, 0); + + /* Microphone BIAS enable */ + a64_acodec_pr_set_clear(sc, A64_JACK_MIC_CTRL, + A64_HMICBIASEN | A64_INNERRESEN, 0); + + /* Unmute DAC to output mixer */ + a64_acodec_pr_set_clear(sc, A64_OL_MIX_CTRL, + A64_LMIXMUTE_LDAC, 0); + a64_acodec_pr_set_clear(sc, A64_OR_MIX_CTRL, + A64_RMIXMUTE_RDAC, 0); + + /* For now we work only with headphones */ + a64_acodec_pr_set_clear(sc, A64_LINEOUT_CTRL0, + 0, A64_LINEOUT_EN); + a64_acodec_pr_set_clear(sc, A64_HP_CTRL, + A64_HPPA_EN, 0); + + u_int val = a64_acodec_pr_read(sc, A64_HP_CTRL); + val &= ~(0x3f); + val |= 0x25; + a64_acodec_pr_write(sc, A64_HP_CTRL, val); + + a64_acodec_pr_set_clear(sc, A64_MIC2_CTRL, + A64_MIC2AMPEN | A64_MIC2_SEL | A64_MIC2G(0x3) | A64_MIC2BOOST(0x4), + A64_MIC2G_MASK | A64_MIC2BOOST_MASK); + + a64_acodec_pr_write(sc, A64_L_ADCMIX_SRC, + A64_ADCMIX_SRC_MIC2); + a64_acodec_pr_write(sc, A64_R_ADCMIX_SRC, + A64_ADCMIX_SRC_MIC2); + + /* Max out MIC2 gain */ + val = a64_acodec_pr_read(sc, A64_MIC2_CTRL); + val &= ~(0x7); + val |= (0x7); + val &= ~(7 << 4); + val |= (7 << 4); + a64_acodec_pr_write(sc, A64_MIC2_CTRL, val); + + node = ofw_bus_get_node(dev); + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); + +fail: + a64codec_detach(dev); + return (error); +} + +static int +a64codec_detach(device_t dev) +{ + struct a64codec_softc *sc; + + sc = device_get_softc(dev); + + if (sc->res) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); + mtx_destroy(&sc->mtx); + + return (0); +} + +static int +a64codec_mixer_init(struct snd_mixer *m) +{ + + mix_setdevs(m, A64CODEC_MIXER_DEVS); + + return (0); +} + +static int +a64codec_mixer_uninit(struct snd_mixer *m) +{ + + return (0); +} + +static int +a64codec_mixer_reinit(struct snd_mixer *m) +{ + + return (0); +} + +static int +a64codec_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) +{ + struct a64codec_softc *sc; + struct mtx *mixer_lock; + uint8_t do_unlock; + u_int val; + + sc = device_get_softc(mix_getdevinfo(m)); + mixer_lock = mixer_get_lock(m); + + if (mtx_owned(mixer_lock)) { + do_unlock = 0; + } else { + do_unlock = 1; + mtx_lock(mixer_lock); + } + + right = left; + + A64CODEC_LOCK(sc); + switch(dev) { + case SOUND_MIXER_VOLUME: + val = a64_acodec_pr_read(sc, A64_HP_CTRL); + val &= ~(A64_HPVOL_MASK); + val |= A64_HPVOL(left * 63 / 100); + a64_acodec_pr_write(sc, A64_HP_CTRL, val); + break; + + case SOUND_MIXER_MIC: + val = a64_acodec_pr_read(sc, A64_MIC2_CTRL); + val &= ~(A64_MIC2BOOST_MASK); + val |= A64_MIC2BOOST(left * 7 / 100); + a64_acodec_pr_write(sc, A64_MIC2_CTRL, val); + break; + default: + break; + } + A64CODEC_UNLOCK(sc); + + if (do_unlock) { + mtx_unlock(mixer_lock); + } + + return (left | (right << 8)); +} + +static unsigned +a64codec_mixer_setrecsrc(struct snd_mixer *m, unsigned src) +{ + + return (0); +} + +static kobj_method_t a64codec_mixer_methods[] = { + KOBJMETHOD(mixer_init, a64codec_mixer_init), + KOBJMETHOD(mixer_uninit, a64codec_mixer_uninit), + KOBJMETHOD(mixer_reinit, a64codec_mixer_reinit), + KOBJMETHOD(mixer_set, a64codec_mixer_set), + KOBJMETHOD(mixer_setrecsrc, a64codec_mixer_setrecsrc), + KOBJMETHOD_END +}; + +MIXER_DECLARE(a64codec_mixer); + +static int +a64codec_dai_init(device_t dev, uint32_t format) +{ + + return (0); +} + +static int +a64codec_dai_trigger(device_t dev, int go, int pcm_dir) +{ + struct a64codec_softc *sc = device_get_softc(dev); + + if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) + return (EINVAL); + + switch (go) { + case PCMTRIG_START: + if (pcm_dir == PCMDIR_PLAY) { + /* Enable DAC analog l/r channels, HP PA, and output mixer */ + a64_acodec_pr_set_clear(sc, A64_MIX_DAC_CTRL, + A64_DACAREN | A64_DACALEN | A64_RMIXEN | A64_LMIXEN | + A64_RHPPAMUTE | A64_LHPPAMUTE, 0); + } + else if (pcm_dir == PCMDIR_REC) { + /* Enable ADC analog l/r channels */ + a64_acodec_pr_set_clear(sc, A64_ADC_CTRL, + A64_ADCREN | A64_ADCLEN, 0); + } + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + if (pcm_dir == PCMDIR_PLAY) { + /* Disable DAC analog l/r channels, HP PA, and output mixer */ + a64_acodec_pr_set_clear(sc, A64_MIX_DAC_CTRL, + 0, A64_DACAREN | A64_DACALEN | A64_RMIXEN | A64_LMIXEN | + A64_RHPPAMUTE | A64_LHPPAMUTE); + } + else if (pcm_dir == PCMDIR_REC) { + /* Disable ADC analog l/r channels */ + a64_acodec_pr_set_clear(sc, A64_ADC_CTRL, + 0, A64_ADCREN | A64_ADCLEN); + } + break; + } + + return (0); +} + +static int +a64codec_dai_setup_mixer(device_t dev, device_t pcmdev) +{ + + mixer_init(pcmdev, &a64codec_mixer_class, dev); + + return (0); +} + +static device_method_t a64codec_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, a64codec_probe), + DEVMETHOD(device_attach, a64codec_attach), + DEVMETHOD(device_detach, a64codec_detach), + + DEVMETHOD(audio_dai_init, a64codec_dai_init), + DEVMETHOD(audio_dai_setup_mixer, a64codec_dai_setup_mixer), + DEVMETHOD(audio_dai_trigger, a64codec_dai_trigger), + + DEVMETHOD_END +}; + +static driver_t a64codec_driver = { + "a64codec", + a64codec_methods, + sizeof(struct a64codec_softc), +}; + +static devclass_t a64codec_devclass; + +DRIVER_MODULE(a64codec, simplebus, a64codec_driver, a64codec_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); diff --git a/sys/arm/allwinner/aw_i2s.c b/sys/arm/allwinner/aw_i2s.c new file mode 100644 index 000000000000..013e88a548a8 --- /dev/null +++ b/sys/arm/allwinner/aw_i2s.c @@ -0,0 +1,813 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Oleksandr Tymoshenko + * Copyright (c) 2018 Jared McNeill + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "syscon_if.h" + +#include "opt_snd.h" +#include +#include +#include "audio_dai_if.h" + +#define FIFO_LEVEL 0x40 + +#define DA_CTL 0x00 +#define DA_CTL_BCLK_OUT (1 << 18) /* sun8i */ +#define DA_CLK_LRCK_OUT (1 << 17) /* sun8i */ +#define DA_CTL_SDO_EN (1 << 8) +#define DA_CTL_MS (1 << 5) /* sun4i */ +#define DA_CTL_PCM (1 << 4) /* sun4i */ +#define DA_CTL_MODE_SEL_MASK (3 << 4) /* sun8i */ +#define DA_CTL_MODE_SEL_PCM (0 << 4) /* sun8i */ +#define DA_CTL_MODE_SEL_LJ (1 << 4) /* sun8i */ +#define DA_CTL_MODE_SEL_RJ (2 << 4) /* sun8i */ +#define DA_CTL_TXEN (1 << 2) +#define DA_CTL_RXEN (1 << 1) +#define DA_CTL_GEN (1 << 0) +#define DA_FAT0 0x04 +#define DA_FAT0_LRCK_PERIOD_MASK (0x3ff << 8) /* sun8i */ +#define DA_FAT0_LRCK_PERIOD(n) (((n) & 0x3fff) << 8) /* sun8i */ +#define DA_FAT0_LRCP_MASK (1 << 7) +#define DA_LRCP_NORMAL (0 << 7) +#define DA_LRCP_INVERTED (1 << 7) +#define DA_FAT0_BCP_MASK (1 << 6) +#define DA_BCP_NORMAL (0 << 6) +#define DA_BCP_INVERTED (1 << 6) +#define DA_FAT0_SR __BITS(5,4) +#define DA_FAT0_WSS __BITS(3,2) +#define DA_FAT0_FMT_MASK (3 << 0) +#define DA_FMT_I2S 0 +#define DA_FMT_LJ 1 +#define DA_FMT_RJ 2 +#define DA_FAT1 0x08 +#define DA_ISTA 0x0c +#define DA_ISTA_TXUI_INT (1 << 6) +#define DA_ISTA_TXEI_INT (1 << 4) +#define DA_ISTA_RXAI_INT (1 << 0) +#define DA_RXFIFO 0x10 +#define DA_FCTL 0x14 +#define DA_FCTL_HUB_EN (1 << 31) +#define DA_FCTL_FTX (1 << 25) +#define DA_FCTL_FRX (1 << 24) +#define DA_FCTL_TXTL_MASK (0x7f << 12) +#define DA_FCTL_TXTL(v) (((v) & 0x7f) << 12) +#define DA_FCTL_TXIM (1 << 2) +#define DA_FSTA 0x18 +#define DA_FSTA_TXE_CNT(v) (((v) >> 16) & 0xff) +#define DA_FSTA_RXA_CNT(v) ((v) & 0x3f) +#define DA_INT 0x1c +#define DA_INT_TX_DRQ (1 << 7) +#define DA_INT_TXUI_EN (1 << 6) +#define DA_INT_TXEI_EN (1 << 4) +#define DA_INT_RX_DRQ (1 << 3) +#define DA_INT_RXAI_EN (1 << 0) +#define DA_TXFIFO 0x20 +#define DA_CLKD 0x24 +#define DA_CLKD_MCLKO_EN_SUN8I (1 << 8) +#define DA_CLKD_MCLKO_EN_SUN4I (1 << 7) +#define DA_CLKD_BCLKDIV_SUN8I(n) (((n) & 0xf) << 4) +#define DA_CLKD_BCLKDIV_SUN8I_MASK (0xf << 4) +#define DA_CLKD_BCLKDIV_SUN4I(n) (((n) & 7) << 4) +#define DA_CLKD_BCLKDIV_SUN4I_MASK (7 << 4) +#define DA_CLKD_BCLKDIV_8 3 +#define DA_CLKD_BCLKDIV_16 5 +#define DA_CLKD_MCLKDIV(n) (((n) & 0xff) << 0) +#define DA_CLKD_MCLKDIV_MASK (0xf << 0) +#define DA_CLKD_MCLKDIV_1 0 +#define DA_TXCNT 0x28 +#define DA_RXCNT 0x2c +#define DA_CHCFG 0x30 /* sun8i */ +#define DA_CHCFG_TX_SLOT_HIZ (1 << 9) +#define DA_CHCFG_TXN_STATE (1 << 8) +#define DA_CHCFG_RX_SLOT_NUM_MASK (7 << 4) +#define DA_CHCFG_RX_SLOT_NUM(n) (((n) & 7) << 4) +#define DA_CHCFG_TX_SLOT_NUM_MASK (7 << 0) +#define DA_CHCFG_TX_SLOT_NUM(n) (((n) & 7) << 0) + +#define DA_CHSEL_OFFSET(n) (((n) & 3) << 12) /* sun8i */ +#define DA_CHSEL_OFFSET_MASK (3 << 12) /* sun8i */ +#define DA_CHSEL_EN(n) (((n) & 0xff) << 4) +#define DA_CHSEL_EN_MASK (0xff << 4) +#define DA_CHSEL_SEL(n) (((n) & 7) << 0) +#define DA_CHSEL_SEL_MASK (7 << 0) + +#define AUDIO_BUFFER_SIZE 48000 * 4 + +#define AW_I2S_SAMPLE_RATE 48000 +#define AW_I2S_CLK_RATE 24576000 + +enum sunxi_i2s_type { + SUNXI_I2S_SUN4I, + SUNXI_I2S_SUN8I, +}; + +struct sunxi_i2s_config { + const char *name; + enum sunxi_i2s_type type; + bus_size_t txchsel; + bus_size_t txchmap; + bus_size_t rxchsel; + bus_size_t rxchmap; +}; + +static const struct sunxi_i2s_config sun50i_a64_codec_config = { + .name = "Audio Codec (digital part)", + .type = SUNXI_I2S_SUN4I, + .txchsel = 0x30, + .txchmap = 0x34, + .rxchsel = 0x38, + .rxchmap = 0x3c, +}; + +static const struct sunxi_i2s_config sun8i_h3_config = { + .name = "I2S/PCM controller", + .type = SUNXI_I2S_SUN8I, + .txchsel = 0x34, + .txchmap = 0x44, + .rxchsel = 0x54, + .rxchmap = 0x58, +}; + +static const u_int sun4i_i2s_bclk_divmap[] = { + [0] = 2, + [1] = 4, + [2] = 6, + [3] = 8, + [4] = 12, + [5] = 16, +}; + +static const u_int sun4i_i2s_mclk_divmap[] = { + [0] = 1, + [1] = 2, + [2] = 4, + [3] = 6, + [4] = 8, + [5] = 12, + [6] = 16, + [7] = 24, +}; + +static const u_int sun8i_i2s_divmap[] = { + [1] = 1, + [2] = 2, + [3] = 4, + [4] = 6, + [5] = 8, + [6] = 12, + [7] = 16, + [8] = 24, + [9] = 32, + [10] = 48, + [11] = 64, + [12] = 96, + [13] = 128, + [14] = 176, + [15] = 192, +}; + + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun50i-a64-codec-i2s", (uintptr_t)&sun50i_a64_codec_config }, + { "allwinner,sun8i-h3-i2s", (uintptr_t)&sun8i_h3_config }, + { NULL, 0 } +}; + +static struct resource_spec aw_i2s_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0 } +}; + +struct aw_i2s_softc { + device_t dev; + struct resource *res[2]; + struct mtx mtx; + clk_t clk; + struct sunxi_i2s_config *cfg; + void * intrhand; + /* pointers to playback/capture buffers */ + uint32_t play_ptr; + uint32_t rec_ptr; +}; + +#define I2S_LOCK(sc) mtx_lock(&(sc)->mtx) +#define I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define I2S_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) +#define I2S_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) +#define I2S_TYPE(sc) ((sc)->cfg->type) + +static int aw_i2s_probe(device_t dev); +static int aw_i2s_attach(device_t dev); +static int aw_i2s_detach(device_t dev); + +static u_int +sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div) +{ + u_int n; + + for (n = 0; n < divmaplen; n++) + if (divmap[n] == div) + return n; + + return -1; +} + +static uint32_t sc_fmt[] = { + SND_FORMAT(AFMT_S16_LE, 2, 0), + 0 +}; +static struct pcmchan_caps aw_i2s_caps = {AW_I2S_SAMPLE_RATE, AW_I2S_SAMPLE_RATE, sc_fmt, 0}; + + +static int +aw_i2s_init(struct aw_i2s_softc *sc) +{ + uint32_t val; + int error; + + error = clk_enable(sc->clk); + if (error != 0) { + device_printf(sc->dev, "cannot enable mod clock\n"); + return (ENXIO); + } + + /* Reset */ + val = I2S_READ(sc, DA_CTL); + val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN); + I2S_WRITE(sc, DA_CTL, val); + + val = I2S_READ(sc, DA_FCTL); + val &= ~(DA_FCTL_FTX|DA_FCTL_FRX); + val &= ~(DA_FCTL_TXTL_MASK); + val |= DA_FCTL_TXTL(FIFO_LEVEL); + I2S_WRITE(sc, DA_FCTL, val); + + I2S_WRITE(sc, DA_TXCNT, 0); + I2S_WRITE(sc, DA_RXCNT, 0); + + /* Enable */ + val = I2S_READ(sc, DA_CTL); + val |= DA_CTL_GEN; + I2S_WRITE(sc, DA_CTL, val); + val |= DA_CTL_SDO_EN; + I2S_WRITE(sc, DA_CTL, val); + + /* Setup channels */ + I2S_WRITE(sc, sc->cfg->txchmap, 0x76543210); + val = I2S_READ(sc, sc->cfg->txchsel); + val &= ~DA_CHSEL_EN_MASK; + val |= DA_CHSEL_EN(3); + val &= ~DA_CHSEL_SEL_MASK; + val |= DA_CHSEL_SEL(1); + I2S_WRITE(sc, sc->cfg->txchsel, val); + I2S_WRITE(sc, sc->cfg->rxchmap, 0x76543210); + val = I2S_READ(sc, sc->cfg->rxchsel); + val &= ~DA_CHSEL_EN_MASK; + val |= DA_CHSEL_EN(3); + val &= ~DA_CHSEL_SEL_MASK; + val |= DA_CHSEL_SEL(1); + I2S_WRITE(sc, sc->cfg->rxchsel, val); + + if (I2S_TYPE(sc) == SUNXI_I2S_SUN8I) { + val = I2S_READ(sc, DA_CHCFG); + val &= ~DA_CHCFG_TX_SLOT_NUM_MASK; + val |= DA_CHCFG_TX_SLOT_NUM(1); + val &= ~DA_CHCFG_RX_SLOT_NUM_MASK; + val |= DA_CHCFG_RX_SLOT_NUM(1); + I2S_WRITE(sc, DA_CHCFG, val); + } + + return (0); +} + +static int +aw_i2s_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Allwinner I2S"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_i2s_attach(device_t dev) +{ + struct aw_i2s_softc *sc; + int error; + phandle_t node; + hwreset_t rst; + clk_t clk; + + sc = device_get_softc(dev); + sc->dev = dev; + + sc->cfg = (void*)ofw_bus_search_compatible(dev, compat_data)->ocd_data; + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + if (bus_alloc_resources(dev, aw_i2s_spec, sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + error = ENXIO; + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk); + if (error != 0) { + device_printf(dev, "cannot get i2s_clk clock\n"); + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "apb", &clk); + if (error != 0) { + device_printf(dev, "cannot get APB clock\n"); + goto fail; + } + + error = clk_enable(clk); + if (error != 0) { + device_printf(dev, "cannot enable APB clock\n"); + goto fail; + } + + if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { + error = hwreset_deassert(rst); + if (error != 0) { + device_printf(dev, "cannot de-assert reset\n"); + goto fail; + } + } + + aw_i2s_init(sc); + + node = ofw_bus_get_node(dev); + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); + +fail: + aw_i2s_detach(dev); + return (error); +} + +static int +aw_i2s_detach(device_t dev) +{ + struct aw_i2s_softc *i2s; + + i2s = device_get_softc(dev); + + if (i2s->clk) + clk_release(i2s->clk); + + if (i2s->intrhand != NULL) + bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); + + bus_release_resources(dev, aw_i2s_spec, i2s->res); + mtx_destroy(&i2s->mtx); + + return (0); +} + +static int +aw_i2s_dai_init(device_t dev, uint32_t format) +{ + struct aw_i2s_softc *sc; + int fmt, pol, clk; + uint32_t ctl, fat0, chsel; + u_int offset; + + sc = device_get_softc(dev); + + fmt = AUDIO_DAI_FORMAT_FORMAT(format); + pol = AUDIO_DAI_FORMAT_POLARITY(format); + clk = AUDIO_DAI_FORMAT_CLOCK(format); + + ctl = I2S_READ(sc, DA_CTL); + fat0 = I2S_READ(sc, DA_FAT0); + + if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { + fat0 &= ~DA_FAT0_FMT_MASK; + switch (fmt) { + case AUDIO_DAI_FORMAT_I2S: + fat0 |= DA_FMT_I2S; + break; + case AUDIO_DAI_FORMAT_RJ: + fat0 |= DA_FMT_RJ; + break; + case AUDIO_DAI_FORMAT_LJ: + fat0 |= DA_FMT_LJ; + break; + default: + return EINVAL; + } + ctl &= ~DA_CTL_PCM; + } else { + ctl &= ~DA_CTL_MODE_SEL_MASK; + switch (fmt) { + case AUDIO_DAI_FORMAT_I2S: + ctl |= DA_CTL_MODE_SEL_LJ; + offset = 1; + break; + case AUDIO_DAI_FORMAT_LJ: + ctl |= DA_CTL_MODE_SEL_LJ; + offset = 0; + break; + case AUDIO_DAI_FORMAT_RJ: + ctl |= DA_CTL_MODE_SEL_RJ; + offset = 0; + break; + case AUDIO_DAI_FORMAT_DSPA: + ctl |= DA_CTL_MODE_SEL_PCM; + offset = 1; + break; + case AUDIO_DAI_FORMAT_DSPB: + ctl |= DA_CTL_MODE_SEL_PCM; + offset = 0; + break; + default: + return EINVAL; + } + + chsel = I2S_READ(sc, sc->cfg->txchsel); + chsel &= ~DA_CHSEL_OFFSET_MASK; + chsel |= DA_CHSEL_OFFSET(offset); + I2S_WRITE(sc, sc->cfg->txchsel, chsel); + + chsel = I2S_READ(sc, sc->cfg->rxchsel); + chsel &= ~DA_CHSEL_OFFSET_MASK; + chsel |= DA_CHSEL_OFFSET(offset); + I2S_WRITE(sc, sc->cfg->rxchsel, chsel); + } + + fat0 &= ~(DA_FAT0_LRCP_MASK|DA_FAT0_BCP_MASK); + if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { + if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) + fat0 |= DA_BCP_INVERTED; + if (AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) + fat0 |= DA_LRCP_INVERTED; + } else { + if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) + fat0 |= DA_BCP_INVERTED; + if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) + fat0 |= DA_LRCP_INVERTED; + + fat0 &= ~DA_FAT0_LRCK_PERIOD_MASK; + fat0 |= DA_FAT0_LRCK_PERIOD(32 - 1); + } + + I2S_WRITE(sc, DA_CTL, ctl); + I2S_WRITE(sc, DA_FAT0, fat0); + + return (0); +} + + +static int +aw_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) +{ + struct aw_i2s_softc *sc; + int ret = 0; + uint32_t val, status; + + sc = device_get_softc(dev); + + I2S_LOCK(sc); + + status = I2S_READ(sc, DA_ISTA); + /* Clear interrupts */ + // device_printf(sc->dev, "status: %08x\n", status); + I2S_WRITE(sc, DA_ISTA, status); + + if (status & DA_ISTA_TXEI_INT) { + uint8_t *samples; + uint32_t count, size, readyptr, written, empty; + + val = I2S_READ(sc, DA_FSTA); + empty = DA_FSTA_TXE_CNT(val); + count = sndbuf_getready(play_buf); + size = sndbuf_getsize(play_buf); + readyptr = sndbuf_getreadyptr(play_buf); + + samples = (uint8_t*)sndbuf_getbuf(play_buf); + written = 0; + if (empty > count / 2) + empty = count / 2; + for (; empty > 0; empty--) { + val = (samples[readyptr++ % size] << 16); + val |= (samples[readyptr++ % size] << 24); + written += 2; + I2S_WRITE(sc, DA_TXFIFO, val); + } + sc->play_ptr += written; + sc->play_ptr %= size; + ret |= AUDIO_DAI_PLAY_INTR; + } + + if (status & DA_ISTA_RXAI_INT) { + uint8_t *samples; + uint32_t count, size, freeptr, recorded, available; + + val = I2S_READ(sc, DA_FSTA); + available = DA_FSTA_RXA_CNT(val); + + count = sndbuf_getfree(rec_buf); + size = sndbuf_getsize(rec_buf); + freeptr = sndbuf_getfreeptr(rec_buf); + samples = (uint8_t*)sndbuf_getbuf(rec_buf); + recorded = 0; + if (available > count / 2) + available = count / 2; + + for (; available > 0; available--) { + val = I2S_READ(sc, DA_RXFIFO); + samples[freeptr++ % size] = (val >> 16) & 0xff; + samples[freeptr++ % size] = (val >> 24) & 0xff; + recorded += 2; + } + sc->rec_ptr += recorded; + sc->rec_ptr %= size; + ret |= AUDIO_DAI_REC_INTR; + } + + I2S_UNLOCK(sc); + + return (ret); +} + +static struct pcmchan_caps * +aw_i2s_dai_get_caps(device_t dev) +{ + return (&aw_i2s_caps); +} + +static int +aw_i2s_dai_trigger(device_t dev, int go, int pcm_dir) +{ + struct aw_i2s_softc *sc = device_get_softc(dev); + uint32_t val; + + if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) + return (EINVAL); + + switch (go) { + case PCMTRIG_START: + if (pcm_dir == PCMDIR_PLAY) { + /* Flush FIFO */ + val = I2S_READ(sc, DA_FCTL); + I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX); + I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX); + + /* Reset TX sample counter */ + I2S_WRITE(sc, DA_TXCNT, 0); + + /* Enable TX block */ + val = I2S_READ(sc, DA_CTL); + I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN); + + /* Enable TX underrun interrupt */ + val = I2S_READ(sc, DA_INT); + I2S_WRITE(sc, DA_INT, val | DA_INT_TXEI_EN); + } + + if (pcm_dir == PCMDIR_REC) { + /* Flush FIFO */ + val = I2S_READ(sc, DA_FCTL); + I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX); + I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX); + + /* Reset RX sample counter */ + I2S_WRITE(sc, DA_RXCNT, 0); + + /* Enable RX block */ + val = I2S_READ(sc, DA_CTL); + I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN); + + /* Enable RX data available interrupt */ + val = I2S_READ(sc, DA_INT); + I2S_WRITE(sc, DA_INT, val | DA_INT_RXAI_EN); + } + + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + I2S_LOCK(sc); + + if (pcm_dir == PCMDIR_PLAY) { + /* Disable TX block */ + val = I2S_READ(sc, DA_CTL); + I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN); + + /* Enable TX underrun interrupt */ + val = I2S_READ(sc, DA_INT); + I2S_WRITE(sc, DA_INT, val & ~DA_INT_TXEI_EN); + + sc->play_ptr = 0; + } else { + /* Disable RX block */ + val = I2S_READ(sc, DA_CTL); + I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN); + + /* Disable RX data available interrupt */ + val = I2S_READ(sc, DA_INT); + I2S_WRITE(sc, DA_INT, val & ~DA_INT_RXAI_EN); + + sc->rec_ptr = 0; + } + + I2S_UNLOCK(sc); + break; + } + + return (0); +} + +static uint32_t +aw_i2s_dai_get_ptr(device_t dev, int pcm_dir) +{ + struct aw_i2s_softc *sc; + uint32_t ptr; + + sc = device_get_softc(dev); + + I2S_LOCK(sc); + if (pcm_dir == PCMDIR_PLAY) + ptr = sc->play_ptr; + else + ptr = sc->rec_ptr; + I2S_UNLOCK(sc); + + return ptr; +} + +static int +aw_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) +{ + struct aw_i2s_softc *sc = device_get_softc(dev); + + if (bus_setup_intr(dev, sc->res[1], + INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg, + &sc->intrhand)) { + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + + return (0); +} + +static uint32_t +aw_i2s_dai_set_chanformat(device_t dev, uint32_t format) +{ + + return (0); +} + +static int +aw_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) +{ + struct aw_i2s_softc *sc; + int bclk_val, mclk_val; + uint32_t val; + int error; + + sc = device_get_softc(dev); + + error = clk_set_freq(sc->clk, AW_I2S_CLK_RATE, CLK_SET_ROUND_DOWN); + if (error != 0) { + device_printf(sc->dev, + "couldn't set mod clock rate to %u Hz: %d\n", AW_I2S_CLK_RATE, error); + return error; + } + error = clk_enable(sc->clk); + if (error != 0) { + device_printf(sc->dev, + "couldn't enable mod clock: %d\n", error); + return error; + } + + const u_int bclk_prate = I2S_TYPE(sc) == SUNXI_I2S_SUN4I ? rate : AW_I2S_CLK_RATE; + + const u_int bclk_div = bclk_prate / (2 * 32 * AW_I2S_SAMPLE_RATE); + const u_int mclk_div = AW_I2S_CLK_RATE / rate; + + if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { + bclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_bclk_divmap, + nitems(sun4i_i2s_bclk_divmap), bclk_div); + mclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_mclk_divmap, + nitems(sun4i_i2s_mclk_divmap), mclk_div); + } else { + bclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, + nitems(sun8i_i2s_divmap), bclk_div); + mclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, + nitems(sun8i_i2s_divmap), mclk_div); + } + if (bclk_val == -1 || mclk_val == -1) { + device_printf(sc->dev, "couldn't configure bclk/mclk dividers\n"); + return EIO; + } + + val = I2S_READ(sc, DA_CLKD); + if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { + val |= DA_CLKD_MCLKO_EN_SUN4I; + val &= ~DA_CLKD_BCLKDIV_SUN4I_MASK; + val |= DA_CLKD_BCLKDIV_SUN4I(bclk_val); + } else { + val |= DA_CLKD_MCLKO_EN_SUN8I; + val &= ~DA_CLKD_BCLKDIV_SUN8I_MASK; + val |= DA_CLKD_BCLKDIV_SUN8I(bclk_val); + } + val &= ~DA_CLKD_MCLKDIV_MASK; + val |= DA_CLKD_MCLKDIV(mclk_val); + I2S_WRITE(sc, DA_CLKD, val); + + + return (0); +} + +static uint32_t +aw_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) +{ + + return (speed); +} + +static device_method_t aw_i2s_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_i2s_probe), + DEVMETHOD(device_attach, aw_i2s_attach), + DEVMETHOD(device_detach, aw_i2s_detach), + + DEVMETHOD(audio_dai_init, aw_i2s_dai_init), + DEVMETHOD(audio_dai_setup_intr, aw_i2s_dai_setup_intr), + DEVMETHOD(audio_dai_set_sysclk, aw_i2s_dai_set_sysclk), + DEVMETHOD(audio_dai_set_chanspeed, aw_i2s_dai_set_chanspeed), + DEVMETHOD(audio_dai_set_chanformat, aw_i2s_dai_set_chanformat), + DEVMETHOD(audio_dai_intr, aw_i2s_dai_intr), + DEVMETHOD(audio_dai_get_caps, aw_i2s_dai_get_caps), + DEVMETHOD(audio_dai_trigger, aw_i2s_dai_trigger), + DEVMETHOD(audio_dai_get_ptr, aw_i2s_dai_get_ptr), + + DEVMETHOD_END +}; + +static driver_t aw_i2s_driver = { + "i2s", + aw_i2s_methods, + sizeof(struct aw_i2s_softc), +}; + +static devclass_t aw_i2s_devclass; + +DRIVER_MODULE(aw_i2s, simplebus, aw_i2s_driver, aw_i2s_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); diff --git a/sys/arm64/conf/GENERIC b/sys/arm64/conf/GENERIC index 23126cc81127..8b3adc9f1357 100644 --- a/sys/arm64/conf/GENERIC +++ b/sys/arm64/conf/GENERIC @@ -1,392 +1,395 @@ # # GENERIC -- Generic kernel configuration file for FreeBSD/arm64 # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ cpu ARM64 ident GENERIC makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support options SCHED_ULE # ULE scheduler options NUMA # Non-Uniform Memory Architecture support options PREEMPTION # Enable kernel thread preemption options VIMAGE # Subsystem virtualization, e.g. VNET options INET # InterNETworking options INET6 # IPv6 communications protocols options IPSEC_SUPPORT # Allow kldload of ipsec and tcpmd5 options ROUTE_MPATH # Multipath routing support options FIB_ALGO # Modular fib lookups options TCP_OFFLOAD # TCP offload options TCP_HHOOK # hhook(9) framework for TCP options TCP_RFC7413 # TCP Fast Open options SCTP_SUPPORT # Allow kldload of SCTP options KERN_TLS # TLS transmit & receive offload options FFS # Berkeley Fast Filesystem options SOFTUPDATES # Enable FFS soft updates support options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options UFS_GJOURNAL # Enable gjournal-based UFS journaling options QUOTA # Enable disk quotas for UFS options MD_ROOT # MD is a potential root device options NFSCL # Network Filesystem Client options NFSD # Network Filesystem Server options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCL options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options TMPFS # Efficient memory filesystem options GEOM_RAID # Soft RAID functionality. options GEOM_LABEL # Provides labelization options EFIRT # EFI Runtime Services support options COMPAT_FREEBSD32 # Compatible with FreeBSD/arm options COMPAT_FREEBSD11 # Compatible with FreeBSD11 options COMPAT_FREEBSD12 # Compatible with FreeBSD12 options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE # ktrace(1) support options STACK # stack(9) support options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options KBD_INSTALL_CDEV # install a CDEV entry in /dev options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4) options AUDIT # Security event auditing options CAPABILITY_MODE # Capsicum capability mode options CAPABILITIES # Capsicum capabilities options MAC # TrustedBSD MAC Framework options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks options DDB_CTF # Kernel ELF linker loads CTF data options VFP # Floating-point support options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default options RCTL # Resource limits options INTRNG options LINUX_BOOT_ABI # Boot using booti command from U-Boot # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. # For full debugger support use (turn off in stable branch): options DDB # Support DDB. options GDB # Support remote GDB. options DEADLKRES # Enable the deadlock resolver options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones options ALT_BREAK_TO_DEBUGGER # Enter debugger on keyboard escape sequence options VERBOSE_SYSINIT=0 # Support debug.verbose_sysinit, off by default # Kernel Sanitizers #options COVERAGE # Generic kernel coverage. Used by KCOV #options KCOV # Kernel Coverage Sanitizer # Warning: KUBSAN can result in a kernel too large for loader to load #options KUBSAN # Kernel Undefined Behavior Sanitizer #options KCSAN # Kernel Concurrency Sanitizer # Kernel dump features. options EKCD # Support for encrypted kernel dumps options GZIO # gzip-compressed kernel and user dumps options ZSTDIO # zstd-compressed kernel and user dumps options DEBUGNET # debugnet networking options NETDUMP # netdump(4) client support # Make an SMP-capable kernel by default options SMP # Symmetric MultiProcessor Kernel # SoC support options SOC_ALLWINNER_A64 options SOC_ALLWINNER_H5 options SOC_ALLWINNER_H6 options SOC_CAVM_THUNDERX options SOC_FREESCALE_IMX8 options SOC_HISI_HI6220 options SOC_INTEL_STRATIX10 options SOC_BRCM_BCM2837 options SOC_BRCM_BCM2838 options SOC_BRCM_NS2 options SOC_MARVELL_8K options SOC_NVIDIA_TEGRA210 options SOC_NXP_LS options SOC_ROCKCHIP_RK3328 options SOC_ROCKCHIP_RK3399 options SOC_XILINX_ZYNQ # Timer drivers device a10_timer # Annapurna Alpine drivers device al_ccu # Alpine Cache Coherency Unit device al_nb_service # Alpine North Bridge Service device al_iofic # I/O Fabric Interrupt Controller device al_serdes # Serializer/Deserializer device al_udma # Universal DMA # Qualcomm Snapdragon drivers device qcom_gcc # Global Clock Controller # CPU frequency control device cpufreq # Bus drivers device pci device pci_n1sdp # ARM Neoverse N1 SDP PCI device al_pci # Annapurna Alpine PCI-E options PCI_HP # PCI-Express native HotPlug options PCI_IOV # PCI SR-IOV support # Block devices device ahci device scbus device da device pvscsi # VMware PVSCSI # ATA/SCSI peripherals device cd # CD device pass # Passthrough device (direct ATA/SCSI access) # NVM Express (NVMe) support device nvme # base NVMe driver options NVME_USE_NVD=0 # prefer the cam(4) based nda(4) driver device nvd # expose NVMe namespaces as disks, depends on nvme # DMA controller device a31_dmac # GPIO / PINCTRL device a37x0_gpio # Marvell Armada 37x0 GPIO controller device aw_gpio # Allwinner GPIO controller device dwgpio # Synopsys DesignWare APB GPIO Controller device gpio device gpioled device fdt_pinctrl device gpioregulator device mv_gpio # Marvell GPIO controller device mvebu_pinctrl # Marvell Pinmux Controller device pl061 # Arm PL061 GPIO controller device rk_gpio # RockChip GPIO Controller device rk_pinctrl # RockChip Pinmux Controller # I2C device a37x0_iic # Armada 37x0 I2C controller device aw_rsb # Allwinner Reduced Serial Bus device bcm2835_bsc # Broadcom BCM283x I2C bus device iicbus device iicmux device iic device icee # Generic IIC eeprom device twsi # Allwinner I2C controller device pca9547 # NPX I2C bus multiplexer device pcf8563 # NXP Real-time clock/calendar device rk_i2c # RockChip I2C controller device syr827 # Silergy SYR827 PMIC device sy8106a # SY8106A Buck Regulator device vf_i2c # Freescale Vybrid I2C controller device fsliic # Freescale iMX I2C controller # Clock and reset controllers device aw_ccu # Allwinner clock controller # Interrupt controllers device aw_nmi # Allwinner NMI support device mv_cp110_icu # Marvell CP110 ICU device mv_ap806_gicp # Marvell AP806 GICP device mv_ap806_sei # Marvell AP806 SEI # Real-time clock support device aw_rtc # Allwinner Real-time Clock device mv_rtc # Marvell Real-time Clock # Crypto accelerators device armv8crypto # ARMv8 OpenCrypto module device safexcel # Inside Secure EIP-97 # Watchdog controllers device aw_wdog # Allwinner Watchdog # Power management controllers device axp81x # X-Powers AXP81x PMIC device rk805 # RockChip RK805 PMIC # EFUSE device aw_sid # Allwinner Secure ID EFUSE # Thermal sensors device aw_thermal # Allwinner Thermal Sensor Controller device mv_thermal # Marvell Thermal Sensor Controller # SPI device spibus device a37x0_spi # Marvell Armada 37x0 SPI Controller device bcm2835_spi # Broadcom BCM283x SPI bus device rk_spi # RockChip SPI controller # PWM device pwm device aw_pwm device rk_pwm # Console device vt device kbdmux device vt_efifb # EVDEV support device evdev # input event device support options EVDEV_SUPPORT # evdev support in legacy drivers device uinput # install /dev/uinput cdev device aw_cir # Serial (COM) ports device uart # Generic UART driver device uart_imx # iMX8 UART device uart_msm # Qualcomm MSM UART driver device uart_mu # RPI3 aux port device uart_mvebu # Armada 3700 UART driver device uart_ns8250 # ns8250-type UART driver device uart_snps device pl011 # PCI/PCI-X/PCIe Ethernet NICs that use iflib infrastructure device iflib device em # Intel PRO/1000 Gigabit Ethernet Family device ix # Intel 10Gb Ethernet Family device vmx # VMware VMXNET3 Ethernet # Ethernet NICs device mdio device mii device miibus # MII bus support device al_eth # Annapurna Alpine Ethernet NIC device awg # Allwinner EMAC Gigabit Ethernet device axa # AMD Opteron A1100 integrated NIC device cgem # Cadence GEM Gigabit Ethernet device device dwc_rk # Rockchip Designware device dwc_socfpga # Altera SOCFPGA Ethernet MAC device ffec # iMX FFEC device genet # Broadcom on RPi4 device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet device neta # Marvell Armada 370/38x/XP/3700 NIC device re # RealTek 8139C+/8169/8169S/8110S device smc # SMSC LAN91C111 device vnic # Cavium ThunderX NIC # Etherswitch devices device etherswitch # Enable etherswitch support device miiproxy # Required for etherswitch device e6000sw # Marvell mv88e6085 based switches # Pseudo devices. device crypto # core crypto support device loop # Network loopback device ether # Ethernet support device vlan # 802.1Q VLAN support device tuntap # Packet tunnel. device md # Memory "disks" device gif # IPv6 and IPv4 tunneling device firmware # firmware assist module # EXT_RESOURCES pseudo devices options EXT_RESOURCES device clk device phy device hwreset device nvmem device regulator device syscon device aw_syscon # IO Domains device rk_iodomain # The `bpf' device enables the Berkeley Packet Filter. # Be aware of the administrative consequences of enabling this! # Note that 'bpf' is required for DHCP. device bpf # Berkeley packet filter # USB support options USB_DEBUG # enable debug msgs options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device aw_usbphy # Allwinner USB PHY device rk_usb2phy # Rockchip USB2PHY device rk_typec_phy # Rockchip TypeC PHY device dwcotg # DWC OTG controller device musb # Mentor Graphics USB OTG controller device ohci # OHCI USB interface device uhci # UHCI USB interface device ehci # EHCI USB interface (USB 2.0) device ehci_mv # Marvell EHCI USB interface device xhci # XHCI USB interface (USB 3.0) device dwc3 # Synopsys DWC controller device aw_dwc3 # Allwinner DWC3 controller device rk_dwc3 # Rockchip DWC3 controller device usb # USB Bus (required) device ukbd # Keyboard device umass # Disks/Mass storage - Requires scbus and da device tegra210_xusb_fw # Tegra XUSB firmware # USB ethernet support device muge device smcphy device smsc device ure # Sound support -device sound -device a10_codec +device sound +device a10_codec # Allwinner A10 codec +device aw_i2s # Allwinner I2S +device a33_codec # Allwinner A33 codec +device a64_codec # Allwinner A64 Analog codec # MMC/SD/SDIO Card slot support device sdhci device sdhci_xenon # Marvell Xenon SD/MMC controller device aw_mmc # Allwinner SD/MMC controller device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device dwmmc device dwmmc_altera device dwmmc_hisi device rk_dwmmc device rk_emmcphy # VirtIO support device virtio device virtio_pci device virtio_mmio device virtio_blk device vtnet # Chip-specific errata options THUNDERX_PASS_1_1_ERRATA options FDT device acpi # DTBs makeoptions MODULES_EXTRA="dtb/allwinner dtb/freescale dtb/imx8 dtb/nvidia dtb/mv dtb/rockchip dtb/rpi" # HID support options HID_DEBUG # enable debug msgs device hid # Generic HID support diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index 5c819001493d..8457d7203322 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -1,582 +1,585 @@ # $FreeBSD$ ## ## Kernel ## kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng kern/subr_physmem.c standard libkern/bcmp.c standard libkern/memcmp.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/memset.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/strlen.c standard libkern/arm64/crc32c_armv8.S standard arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/arm/pmu_fdt.c optional fdt arm64/acpica/acpi_iort.c optional acpi arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c standard arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gdb_machdep.c optional gdb arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/machdep_boot.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/coresight/coresight.c standard arm64/coresight/coresight_acpi.c optional acpi arm64/coresight/coresight_fdt.c optional fdt arm64/coresight/coresight_if.m standard arm64/coresight/coresight_cmd.c standard arm64/coresight/coresight_cpu_debug.c standard arm64/coresight/coresight_etm4x.c standard arm64/coresight/coresight_etm4x_acpi.c optional acpi arm64/coresight/coresight_etm4x_fdt.c optional fdt arm64/coresight/coresight_funnel.c standard arm64/coresight/coresight_funnel_acpi.c optional acpi arm64/coresight/coresight_funnel_fdt.c optional fdt arm64/coresight/coresight_replicator.c standard arm64/coresight/coresight_replicator_acpi.c optional acpi arm64/coresight/coresight_replicator_fdt.c optional fdt arm64/coresight/coresight_tmc.c standard arm64/coresight/coresight_tmc_acpi.c optional acpi arm64/coresight/coresight_tmc_fdt.c optional fdt arm64/iommu/iommu.c optional iommu arm64/iommu/iommu_if.m optional iommu arm64/iommu/iommu_pmap.c optional iommu arm64/iommu/smmu.c optional iommu arm64/iommu/smmu_acpi.c optional acpi iommu arm64/iommu/smmu_quirks.c optional iommu dev/iommu/busdma_iommu.c optional iommu dev/iommu/iommu_gas.c optional iommu crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" aesv8-armx.o optional armv8crypto \ dependency "$S/crypto/openssl/aarch64/aesv8-armx.S" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ -I$S/crypto/openssl/crypto ${WERROR} ${NO_WCAST_QUAL} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "aesv8-armx.o" ghashv8-armx.o optional armv8crypto \ dependency "$S/crypto/openssl/aarch64/ghashv8-armx.S" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ -I$S/crypto/openssl/crypto ${WERROR} ${NO_WCAST_QUAL} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "ghashv8-armx.o" crypto/des/des_enc.c optional netsmb crypto/openssl/ossl_aarch64.c optional ossl crypto/openssl/aarch64/chacha-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} ${WERROR} ${.IMPSRC}" crypto/openssl/aarch64/poly1305-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} ${WERROR} ${.IMPSRC}" crypto/openssl/aarch64/sha1-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} ${WERROR} ${.IMPSRC}" crypto/openssl/aarch64/sha256-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} ${WERROR} ${.IMPSRC}" crypto/openssl/aarch64/sha512-armv8.S optional ossl \ compile-with "${CC} -c ${CFLAGS:N-mgeneral-regs-only} ${WERROR} ${.IMPSRC}" dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pxm.c optional acpi dev/ahci/ahci_generic.c optional ahci cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" ## ## ASoC support ## dev/sound/fdt/audio_dai_if.m optional sound fdt dev/sound/fdt/audio_soc.c optional sound fdt dev/sound/fdt/dummy_codec.c optional sound fdt dev/sound/fdt/simple_amplifier.c optional sound fdt ## ## Device drivers ## dev/axgbe/if_axgbe.c optional axa dev/axgbe/xgbe-desc.c optional axa dev/axgbe/xgbe-dev.c optional axa dev/axgbe/xgbe-drv.c optional axa dev/axgbe/xgbe-mdio.c optional axa dev/axgbe/xgbe-sysctl.c optional axa dev/axgbe/xgbe-txrx.c optional axa dev/axgbe/xgbe_osdep.c optional axa dev/axgbe/xgbe-phy-v1.c optional axa dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 | fdt dwc_socfpga soc_intel_stratix10 dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 | fdt dwc_socfpga soc_intel_stratix10 dev/gpio/pl061.c optional pl061 gpio dev/gpio/pl061_acpi.c optional pl061 gpio acpi dev/gpio/pl061_fdt.c optional pl061 gpio fdt dev/gpio/qoriq_gpio.c optional SOC_NXP_LS gpio fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/ice/if_ice_iflib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_lib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_osdep.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_resmgr.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_strings.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_recovery_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_common.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_controlq.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_dcb.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flex_pipe.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flow.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_nvm.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sched.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sriov.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_switch.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_vlan_mode.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" ice_ddp.c optional ice_ddp \ compile-with "${AWK} -f $S/tools/fw_stub.awk ice_ddp.fw:ice_ddp:0x01031300 -mice_ddp -c${.TARGET}" \ no-ctfconvert no-implicit-rule before-depend local \ clean "ice_ddp.c" ice_ddp.fwo optional ice_ddp \ dependency "ice_ddp.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ice_ddp.fwo" ice_ddp.fw optional ice_ddp \ dependency "$S/contrib/dev/ice/ice-1.3.19.0.pkg" \ compile-with "${CP} $S/contrib/dev/ice/ice-1.3.19.0.pkg ice_ddp.fw" \ no-obj no-implicit-rule \ clean "ice_ddp.fw" dev/iicbus/sy8106a.c optional sy8106a fdt dev/iicbus/twsi/mv_twsi.c optional twsi fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/ipmi/ipmi.c optional ipmi dev/ipmi/ipmi_acpi.c optional ipmi acpi dev/ipmi/ipmi_kcs.c optional ipmi dev/ipmi/ipmi_smic.c optional ipmi dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_altera.c optional dwmmc dwmmc_altera fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc dwmmc_hisi fdt dev/mmc/host/dwmmc_rockchip.c optional dwmmc rk_dwmmc fdt dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofw_pci.c optional fdt pci dev/ofw/ofw_pcib.c optional fdt pci dev/pci/controller/pci_n1sdp.c optional pci_n1sdp acpi dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/pci/pci_dw_mv.c optional pci fdt dev/pci/pci_dw.c optional pci fdt dev/pci/pci_dw_if.m optional pci fdt dev/psci/psci.c standard dev/psci/smccc_arm64.S standard dev/psci/smccc.c standard dev/safexcel/safexcel.c optional safexcel fdt dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/dwc3.c optional fdt dwc3 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci dev/usb/controller/generic_ehci_acpi.c optional ehci acpi dev/usb/controller/generic_ehci_fdt.c optional ehci fdt dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/musb_otg_allwinner.c optional musb fdt soc_allwinner_a64 dev/usb/controller/usb_nop_xceiv.c optional fdt ext_resources dev/usb/controller/generic_xhci.c optional xhci dev/usb/controller/generic_xhci_acpi.c optional xhci acpi dev/usb/controller/generic_xhci_fdt.c optional xhci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional soc_cavm_thunderx pci vnic fdt dev/vnic/thunder_bgx.c optional soc_cavm_thunderx pci vnic pci dev/vnic/thunder_mdio_fdt.c optional soc_cavm_thunderx pci vnic fdt dev/vnic/thunder_mdio.c optional soc_cavm_thunderx pci vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic ## ## SoC Support ## # Allwinner common files arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/a10_codec.c optional sound a10_codec arm/allwinner/a31_dmac.c optional a31_dmac +arm/allwinner/a33_codec.c optional fdt sound a33_codec +arm/allwinner/a64/sun50i_a64_acodec.c optional fdt sound a64_codec arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_dwc3.c optional aw_dwc3 fdt +arm/allwinner/aw_i2s.c optional fdt sound aw_i2s arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/contrib/device-tree/include" arm/allwinner/aw_pwm.c optional aw_pwm fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_usb3phy.c optional xhci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_m.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_mipi.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nmm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_np.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_h6.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_h6_r.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt arm/allwinner/clkng/ccu_de2.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h6/h6_padconf.c optional soc_allwinner_h6 fdt arm/allwinner/h6/h6_r_padconf.c optional soc_allwinner_h6 fdt # Altera/Intel dev/altera/dwc/if_dwc_socfpga.c optional fdt dwc_socfpga arm64/intel/firmware.c optional soc_intel_stratix10 arm64/intel/stratix10-soc-fpga-mgr.c optional soc_intel_stratix10 arm64/intel/stratix10-svc.c optional soc_intel_stratix10 # Annapurna arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${.IMPSRC}" # Broadcom arm64/broadcom/brcmmdio/mdio_mux_iproc.c optional soc_brcm_ns2 fdt arm64/broadcom/brcmmdio/mdio_nexus_iproc.c optional soc_brcm_ns2 fdt arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c optional soc_brcm_ns2 fdt pci arm64/broadcom/genet/if_genet.c optional SOC_BRCM_BCM2838 fdt genet arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc fdt arm/broadcom/bcm2835/bcm2835_clkman.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt | vt soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_firmware.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt | gpio soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional !random_loadable soc_brcm_bcm2837 fdt | !random_loadable soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi fdt arm/broadcom/bcm2835/bcm2835_vcbus.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 arm/broadcom/bcm2835/bcm2838_pci.c optional soc_brcm_bcm2838 fdt pci arm/broadcom/bcm2835/bcm2838_xhci.c optional soc_brcm_bcm2838 fdt pci xhci arm/broadcom/bcm2835/raspberrypi_gpio.c optional soc_brcm_bcm2837 gpio | soc_brcm_bcm2838 gpio contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" # Cavium arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci # i.MX8 Clock support arm64/freescale/imx/imx8mq_ccm.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_gate.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_mux.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_composite.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_sscg_pll.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_frac_pll.c optional fdt soc_freescale_imx8 # iMX drivers arm/freescale/imx/imx_gpio.c optional gpio soc_freescale_imx8 arm/freescale/imx/imx_i2c.c optional fsliic arm/freescale/imx/imx_machdep.c optional fdt soc_freescale_imx8 arm64/freescale/imx/imx7gpc.c optional fdt soc_freescale_imx8 dev/ffec/if_ffec.c optional ffec # Marvell arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/a37x0_iic.c optional a37x0_iic iicbus fdt arm/mv/a37x0_spi.c optional a37x0_spi spibus fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt arm/mv/mv_ap806_sei.c optional mv_ap806_sei fdt arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt arm/mv/mv_cp110_icu_bus.c optional mv_cp110_icu fdt arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt # NVidia arm/nvidia/tegra_abpmisc.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_ahci.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_efuse.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_ehci.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_gpio.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_i2c.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_lic.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_mc.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_pcie.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_sdhci.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_soctherm_if.m optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_soctherm.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_uart.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_usbphy.c optional fdt soc_nvidia_tegra210 arm/nvidia/tegra_xhci.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/max77620.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/max77620_gpio.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/max77620_regulators.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/max77620_rtc.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_car.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_clk_per.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_clk_pll.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_clk_super.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_coretemp.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_cpufreq.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_pinmux.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_pmc.c optional fdt soc_nvidia_tegra210 arm64/nvidia/tegra210/tegra210_xusbpadctl.c optional fdt soc_nvidia_tegra210 # Nvidia firmware for Tegra tegra210_xusb_fw.c optional tegra210_xusb_fw \ dependency "$S/conf/files.arm64" \ compile-with "${AWK} -f $S/tools/fw_stub.awk tegra210_xusb.fw:tegra210_xusb_fw -mtegra210_xusb_fw -c${.TARGET}" \ no-ctfconvert no-implicit-rule before-depend local \ clean "tegra210_xusb_fw.c" tegra210_xusb.fwo optional tegra210_xusb_fw \ dependency "tegra210_xusb.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "tegra210_xusb.fwo" tegra210_xusb.fw optional tegra210_xusb_fw \ dependency "$S/contrib/dev/nvidia/tegra210_xusb.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "tegra210_xusb.fw" # NXP arm/freescale/vybrid/vf_i2c.c optional vf_i2c iicbus SOC_NXP_LS arm64/qoriq/qoriq_dw_pci.c optional pci fdt SOC_NXP_LS arm64/qoriq/qoriq_therm.c optional pci fdt SOC_NXP_LS arm64/qoriq/qoriq_therm_if.m optional pci fdt SOC_NXP_LS arm64/qoriq/clk/ls1028a_clkgen.c optional clk SOC_NXP_LS arm64/qoriq/clk/ls1046a_clkgen.c optional clk SOC_NXP_LS arm64/qoriq/clk/lx2160a_clkgen.c optional clk SOC_NXP_LS arm64/qoriq/clk/qoriq_clk_pll.c optional clk SOC_NXP_LS arm64/qoriq/clk/qoriq_clkgen.c optional clk SOC_NXP_LS dev/ahci/ahci_fsl_fdt.c optional SOC_NXP_LS ahci fdt # Qualcomm arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt # RockChip Drivers arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain arm64/rockchip/rk_spi.c optional fdt rk_spi arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399 arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_pwm.c optional fdt rk_pwm arm64/rockchip/rk_pcie.c optional fdt pci soc_rockchip_rk3399 arm64/rockchip/rk_pcie_phy.c optional fdt pci soc_rockchip_rk3399 # RockChip Clock support arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_fract.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 # Xilinx arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq # Linuxkpi compat/linuxkpi/common/src/linux_fpu.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" # Cloudabi arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o"