diff --git a/sys/dev/bnxt/bnxt_en/bnxt.h b/sys/dev/bnxt/bnxt_en/bnxt.h index d6fe2ce8ddb1..2faea00e4266 100644 --- a/sys/dev/bnxt/bnxt_en/bnxt.h +++ b/sys/dev/bnxt/bnxt_en/bnxt.h @@ -1,1137 +1,1314 @@ /*- * Broadcom NetXtreme-C/E network driver. * * Copyright (c) 2016 Broadcom, All Rights Reserved. * The term Broadcom refers to Broadcom Limited and/or its subsidiaries * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include #ifndef _BNXT_H #define _BNXT_H #include #include #include #include #include #include #include #include #include #include #include #include "hsi_struct_def.h" #include "bnxt_dcb.h" #include "bnxt_auxbus_compat.h" #define DFLT_HWRM_CMD_TIMEOUT 500 /* PCI IDs */ #define BROADCOM_VENDOR_ID 0x14E4 #define BCM57301 0x16c8 #define BCM57302 0x16c9 #define BCM57304 0x16ca #define BCM57311 0x16ce #define BCM57312 0x16cf #define BCM57314 0x16df #define BCM57402 0x16d0 #define BCM57402_NPAR 0x16d4 #define BCM57404 0x16d1 #define BCM57404_NPAR 0x16e7 #define BCM57406 0x16d2 #define BCM57406_NPAR 0x16e8 #define BCM57407 0x16d5 #define BCM57407_NPAR 0x16ea #define BCM57407_SFP 0x16e9 #define BCM57412 0x16d6 #define BCM57412_NPAR1 0x16de #define BCM57412_NPAR2 0x16eb #define BCM57414 0x16d7 #define BCM57414_NPAR1 0x16ec #define BCM57414_NPAR2 0x16ed #define BCM57416 0x16d8 #define BCM57416_NPAR1 0x16ee #define BCM57416_NPAR2 0x16ef #define BCM57416_SFP 0x16e3 #define BCM57417 0x16d9 #define BCM57417_NPAR1 0x16c0 #define BCM57417_NPAR2 0x16cc #define BCM57417_SFP 0x16e2 #define BCM57454 0x1614 #define BCM58700 0x16cd #define BCM57508 0x1750 #define BCM57504 0x1751 #define BCM57502 0x1752 #define NETXTREME_C_VF1 0x16cb #define NETXTREME_C_VF2 0x16e1 #define NETXTREME_C_VF3 0x16e5 #define NETXTREME_E_VF1 0x16c1 #define NETXTREME_E_VF2 0x16d3 #define NETXTREME_E_VF3 0x16dc #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \ (((data1) & \ HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL) #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ (((data1) & \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >> \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \ (((data2) & \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >> \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT) #define BNXT_EVENT_DBR_EPOCH(data) \ (((data) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK) >> \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT) #define BNXT_EVENT_THERMAL_THRESHOLD_TEMP(data2) \ (((data2) & \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK) >> \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT) #define EVENT_DATA2_NVM_ERR_ADDR(data2) \ (((data2) & \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK) >> \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT) #define EVENT_DATA1_THERMAL_THRESHOLD_DIR_INCREASING(data1) \ (((data1) & \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR) == \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING) #define EVENT_DATA1_NVM_ERR_TYPE_WRITE(data1) \ (((data1) & \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE) #define EVENT_DATA1_NVM_ERR_TYPE_ERASE(data1) \ (((data1) & \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE) #define EVENT_DATA1_THERMAL_THRESHOLD_TYPE(data1) \ ((data1) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK) #define BNXT_EVENT_THERMAL_CURRENT_TEMP(data2) \ ((data2) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK) +#define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \ + (((data1) & \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION) + +#define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \ + ((data2) & \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK) + +#define EVENT_DATA1_RECOVERY_ENABLED(data1) \ + !!((data1) & \ + HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED) + +#define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \ + !!((data1) & \ + HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC) + #define INVALID_STATS_CTX_ID -1 /* Maximum numbers of RX and TX descriptors. iflib requires this to be a power * of two. The hardware has no particular limitation. */ #define BNXT_MAX_RXD ((INT32_MAX >> 1) + 1) #define BNXT_MAX_TXD ((INT32_MAX >> 1) + 1) #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) #define BNXT_MAX_MTU 9600 #define BNXT_RSS_HASH_TYPE_TCPV4 0 #define BNXT_RSS_HASH_TYPE_UDPV4 1 #define BNXT_RSS_HASH_TYPE_IPV4 2 #define BNXT_RSS_HASH_TYPE_TCPV6 3 #define BNXT_RSS_HASH_TYPE_UDPV6 4 #define BNXT_RSS_HASH_TYPE_IPV6 5 #define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F) #define BNXT_NO_MORE_WOL_FILTERS 0xFFFF #define bnxt_wol_supported(softc) (!((softc)->flags & BNXT_FLAG_VF) && \ ((softc)->flags & BNXT_FLAG_WOL_CAP )) /* 64-bit doorbell */ #define DBR_INDEX_MASK 0x0000000000ffffffULL #define DBR_PI_LO_MASK 0xff000000UL #define DBR_PI_LO_SFT 24 #define DBR_XID_MASK 0x000fffff00000000ULL #define DBR_XID_SFT 32 #define DBR_PI_HI_MASK 0xf0000000000000ULL #define DBR_PI_HI_SFT 52 #define DBR_PATH_L2 (0x1ULL << 56) #define DBR_VALID (0x1ULL << 58) #define DBR_TYPE_SQ (0x0ULL << 60) #define DBR_TYPE_RQ (0x1ULL << 60) #define DBR_TYPE_SRQ (0x2ULL << 60) #define DBR_TYPE_SRQ_ARM (0x3ULL << 60) #define DBR_TYPE_CQ (0x4ULL << 60) #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60) #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60) #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60) #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60) #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) #define DBR_TYPE_NQ (0xaULL << 60) #define DBR_TYPE_NQ_ARM (0xbULL << 60) #define DBR_TYPE_PUSH_START (0xcULL << 60) #define DBR_TYPE_PUSH_END (0xdULL << 60) #define DBR_TYPE_NULL (0xfULL << 60) #define BNXT_MAX_L2_QUEUES 128 #define BNXT_ROCE_IRQ_COUNT 9 #define BNXT_MAX_NUM_QUEUES (BNXT_MAX_L2_QUEUES + BNXT_ROCE_IRQ_COUNT) /* Completion related defines */ #define CMP_VALID(cmp, v_bit) \ ((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) ) /* Chip class phase 5 */ #define BNXT_CHIP_P5(sc) ((sc->flags & BNXT_FLAG_CHIP_P5)) #define DB_PF_OFFSET_P5 0x10000 #define DB_VF_OFFSET_P5 0x4000 #define NQ_VALID(cmp, v_bit) \ ((!!(((nq_cn_t *)(cmp))->v & htole32(NQ_CN_V))) == !!(v_bit) ) #ifndef DIV_ROUND_UP #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) #endif #ifndef roundup #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) #endif #define NEXT_CP_CONS_V(ring, cons, v_bit) do { \ if (__predict_false(++(cons) == (ring)->ring_size)) \ ((cons) = 0, (v_bit) = !v_bit); \ } while (0) #define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \ 0 : idx + 1) #define CMPL_PREFETCH_NEXT(cpr, idx) \ __builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\ (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \ ((cpr)->ring.ring_size - 1)]) /* Lock macros */ #define BNXT_HWRM_LOCK_INIT(_softc, _name) \ mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF) #define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock) #define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock) #define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock) #define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \ MA_OWNED) #define BNXT_IS_FLOW_CTRL_CHANGED(link_info) \ ((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) || \ (link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) || \ (link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg)) /* Chip info */ #define BNXT_TSO_SIZE UINT16_MAX #define min_t(type, x, y) ({ \ type __min1 = (x); \ type __min2 = (y); \ __min1 < __min2 ? __min1 : __min2; }) #define max_t(type, x, y) ({ \ type __max1 = (x); \ type __max2 = (y); \ __max1 > __max2 ? __max1 : __max2; }) #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) #define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do { \ if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed) \ ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL); \ } while(0) #define BNXT_MIN_FRAME_SIZE 52 /* Frames must be padded to this size for some A0 chips */ #define BNXT_RX_STATS_EXT_OFFSET(counter) \ (offsetof(struct rx_port_stats_ext, counter) / 8) #define BNXT_RX_STATS_EXT_NUM_LEGACY \ BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks) #define BNXT_TX_STATS_EXT_OFFSET(counter) \ (offsetof(struct tx_port_stats_ext, counter) / 8) extern const char bnxt_driver_version[]; typedef void (*bnxt_doorbell_tx)(void *, uint16_t idx); typedef void (*bnxt_doorbell_rx)(void *, uint16_t idx); typedef void (*bnxt_doorbell_rx_cq)(void *, bool); typedef void (*bnxt_doorbell_tx_cq)(void *, bool); typedef void (*bnxt_doorbell_nq)(void *, bool); typedef struct bnxt_doorbell_ops { bnxt_doorbell_tx bnxt_db_tx; bnxt_doorbell_rx bnxt_db_rx; bnxt_doorbell_rx_cq bnxt_db_rx_cq; bnxt_doorbell_tx_cq bnxt_db_tx_cq; bnxt_doorbell_nq bnxt_db_nq; } bnxt_dooorbell_ops_t; /* NVRAM access */ enum bnxt_nvm_directory_type { BNX_DIR_TYPE_UNUSED = 0, BNX_DIR_TYPE_PKG_LOG = 1, BNX_DIR_TYPE_UPDATE = 2, BNX_DIR_TYPE_CHIMP_PATCH = 3, BNX_DIR_TYPE_BOOTCODE = 4, BNX_DIR_TYPE_VPD = 5, BNX_DIR_TYPE_EXP_ROM_MBA = 6, BNX_DIR_TYPE_AVS = 7, BNX_DIR_TYPE_PCIE = 8, BNX_DIR_TYPE_PORT_MACRO = 9, BNX_DIR_TYPE_APE_FW = 10, BNX_DIR_TYPE_APE_PATCH = 11, BNX_DIR_TYPE_KONG_FW = 12, BNX_DIR_TYPE_KONG_PATCH = 13, BNX_DIR_TYPE_BONO_FW = 14, BNX_DIR_TYPE_BONO_PATCH = 15, BNX_DIR_TYPE_TANG_FW = 16, BNX_DIR_TYPE_TANG_PATCH = 17, BNX_DIR_TYPE_BOOTCODE_2 = 18, BNX_DIR_TYPE_CCM = 19, BNX_DIR_TYPE_PCI_CFG = 20, BNX_DIR_TYPE_TSCF_UCODE = 21, BNX_DIR_TYPE_ISCSI_BOOT = 22, BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26, BNX_DIR_TYPE_EXT_PHY = 27, BNX_DIR_TYPE_SHARED_CFG = 40, BNX_DIR_TYPE_PORT_CFG = 41, BNX_DIR_TYPE_FUNC_CFG = 42, BNX_DIR_TYPE_MGMT_CFG = 48, BNX_DIR_TYPE_MGMT_DATA = 49, BNX_DIR_TYPE_MGMT_WEB_DATA = 50, BNX_DIR_TYPE_MGMT_WEB_META = 51, BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 }; enum bnxnvm_pkglog_field_index { BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 }; #define BNX_DIR_ORDINAL_FIRST 0 #define BNX_DIR_EXT_NONE 0 struct bnxt_bar_info { struct resource *res; bus_space_tag_t tag; bus_space_handle_t handle; bus_size_t size; int rid; }; struct bnxt_flow_ctrl { bool rx; bool tx; bool autoneg; }; struct bnxt_link_info { uint8_t media_type; uint8_t transceiver; uint8_t phy_addr; uint8_t phy_link_status; uint8_t wire_speed; uint8_t loop_back; uint8_t link_up; uint8_t last_link_up; uint8_t duplex; uint8_t last_duplex; uint8_t last_phy_type; struct bnxt_flow_ctrl flow_ctrl; struct bnxt_flow_ctrl last_flow_ctrl; uint8_t duplex_setting; uint8_t auto_mode; #define PHY_VER_LEN 3 uint8_t phy_ver[PHY_VER_LEN]; uint8_t phy_type; #define BNXT_PHY_STATE_ENABLED 0 #define BNXT_PHY_STATE_DISABLED 1 uint8_t phy_state; uint16_t link_speed; uint16_t support_speeds; uint16_t support_pam4_speeds; uint16_t auto_link_speeds; uint16_t auto_pam4_link_speeds; uint16_t force_link_speed; uint16_t force_pam4_link_speed; bool force_pam4_speed_set_by_user; uint16_t advertising; uint16_t advertising_pam4; uint32_t preemphasis; uint16_t support_auto_speeds; uint16_t support_force_speeds; uint16_t support_pam4_auto_speeds; uint16_t support_pam4_force_speeds; #define BNXT_SIG_MODE_NRZ HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ #define BNXT_SIG_MODE_PAM4 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 uint8_t req_signal_mode; uint8_t active_fec_sig_mode; uint8_t sig_mode; /* copy of requested setting */ uint8_t autoneg; #define BNXT_AUTONEG_SPEED 1 #define BNXT_AUTONEG_FLOW_CTRL 2 uint8_t req_duplex; uint16_t req_link_speed; uint8_t module_status; struct hwrm_port_phy_qcfg_output phy_qcfg_resp; }; enum bnxt_phy_type { BNXT_MEDIA_CR = 0, BNXT_MEDIA_LR, BNXT_MEDIA_SR, BNXT_MEDIA_KR, BNXT_MEDIA_END }; enum bnxt_cp_type { BNXT_DEFAULT, BNXT_TX, BNXT_RX, BNXT_SHARED }; struct bnxt_queue_info { uint8_t queue_id; uint8_t queue_profile; }; struct bnxt_func_info { uint32_t fw_fid; uint8_t mac_addr[ETHER_ADDR_LEN]; uint16_t max_rsscos_ctxs; uint16_t max_cp_rings; uint16_t max_tx_rings; uint16_t max_rx_rings; uint16_t max_hw_ring_grps; uint16_t max_irqs; uint16_t max_l2_ctxs; uint16_t max_vnics; uint16_t max_stat_ctxs; }; struct bnxt_pf_info { #define BNXT_FIRST_PF_FID 1 #define BNXT_FIRST_VF_FID 128 uint8_t port_id; uint32_t first_vf_id; uint16_t active_vfs; uint16_t max_vfs; uint32_t max_encap_records; uint32_t max_decap_records; uint32_t max_tx_em_flows; uint32_t max_tx_wm_flows; uint32_t max_rx_em_flows; uint32_t max_rx_wm_flows; unsigned long *vf_event_bmap; uint16_t hwrm_cmd_req_pages; void *hwrm_cmd_req_addr[4]; bus_addr_t hwrm_cmd_req_dma_addr[4]; }; struct bnxt_vf_info { uint16_t fw_fid; uint8_t mac_addr[ETHER_ADDR_LEN]; uint16_t max_rsscos_ctxs; uint16_t max_cp_rings; uint16_t max_tx_rings; uint16_t max_rx_rings; uint16_t max_hw_ring_grps; uint16_t max_l2_ctxs; uint16_t max_irqs; uint16_t max_vnics; uint16_t max_stat_ctxs; uint32_t vlan; #define BNXT_VF_QOS 0x1 #define BNXT_VF_SPOOFCHK 0x2 #define BNXT_VF_LINK_FORCED 0x4 #define BNXT_VF_LINK_UP 0x8 uint32_t flags; uint32_t func_flags; /* func cfg flags */ uint32_t min_tx_rate; uint32_t max_tx_rate; void *hwrm_cmd_req_addr; bus_addr_t hwrm_cmd_req_dma_addr; }; #define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF)) #define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF) struct bnxt_vlan_tag { SLIST_ENTRY(bnxt_vlan_tag) next; uint64_t filter_id; uint16_t tag; }; struct bnxt_vnic_info { uint16_t id; uint16_t def_ring_grp; uint16_t cos_rule; uint16_t lb_rule; uint16_t mru; uint32_t rx_mask; struct iflib_dma_info mc_list; int mc_list_count; #define BNXT_MAX_MC_ADDRS 16 uint32_t flags; #define BNXT_VNIC_FLAG_DEFAULT 0x01 #define BNXT_VNIC_FLAG_BD_STALL 0x02 #define BNXT_VNIC_FLAG_VLAN_STRIP 0x04 uint64_t filter_id; uint16_t rss_id; uint32_t rss_hash_type; uint8_t rss_hash_key[HW_HASH_KEY_SIZE]; struct iflib_dma_info rss_hash_key_tbl; struct iflib_dma_info rss_grp_tbl; SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags; struct iflib_dma_info vlan_tag_list; }; struct bnxt_grp_info { uint16_t stats_ctx; uint16_t grp_id; uint16_t rx_ring_id; uint16_t cp_ring_id; uint16_t ag_ring_id; }; struct bnxt_ring { uint64_t paddr; vm_offset_t doorbell; caddr_t vaddr; struct bnxt_softc *softc; uint32_t ring_size; /* Must be a power of two */ uint16_t id; /* Logical ID */ uint16_t phys_id; uint16_t idx; struct bnxt_full_tpa_start *tpa_start; }; struct bnxt_cp_ring { struct bnxt_ring ring; struct if_irq irq; uint32_t cons; bool v_bit; /* Value of valid bit */ struct ctx_hw_stats *stats; uint32_t stats_ctx_id; uint32_t last_idx; /* Used by RX rings only * set to the last read pidx */ uint64_t int_count; }; struct bnxt_full_tpa_start { struct rx_tpa_start_cmpl low; struct rx_tpa_start_cmpl_hi high; }; /* All the version information for the part */ #define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */ #define BNXT_NAME_SIZE 17 #define FW_VER_STR_LEN 32 #define BC_HWRM_STR_LEN 21 struct bnxt_ver_info { uint8_t hwrm_if_major; uint8_t hwrm_if_minor; uint8_t hwrm_if_update; char hwrm_if_ver[BNXT_VERSTR_SIZE]; char driver_hwrm_if_ver[BNXT_VERSTR_SIZE]; char mgmt_fw_ver[FW_VER_STR_LEN]; char netctrl_fw_ver[FW_VER_STR_LEN]; char roce_fw_ver[FW_VER_STR_LEN]; char fw_ver_str[FW_VER_STR_LEN]; char phy_ver[BNXT_VERSTR_SIZE]; char pkg_ver[64]; char hwrm_fw_name[BNXT_NAME_SIZE]; char mgmt_fw_name[BNXT_NAME_SIZE]; char netctrl_fw_name[BNXT_NAME_SIZE]; char roce_fw_name[BNXT_NAME_SIZE]; char phy_vendor[BNXT_NAME_SIZE]; char phy_partnumber[BNXT_NAME_SIZE]; uint16_t chip_num; uint8_t chip_rev; uint8_t chip_metal; uint8_t chip_bond_id; uint8_t chip_type; uint8_t hwrm_min_major; uint8_t hwrm_min_minor; uint8_t hwrm_min_update; uint64_t fw_ver_code; #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \ ((uint64_t)(maj) << 48 | (uint64_t)(min) << 32 | (uint64_t)(bld) << 16 | (rsv)) #define BNXT_FW_MAJ(softc) ((softc)->ver_info->fw_ver_code >> 48) #define BNXT_FW_MIN(softc) (((softc)->ver_info->fw_ver_code >> 32) & 0xffff) #define BNXT_FW_BLD(softc) (((softc)->ver_info->fw_ver_code >> 16) & 0xffff) #define BNXT_FW_RSV(softc) (((softc)->ver_info->fw_ver_code) & 0xffff) struct sysctl_ctx_list ver_ctx; struct sysctl_oid *ver_oid; }; struct bnxt_nvram_info { uint16_t mfg_id; uint16_t device_id; uint32_t sector_size; uint32_t size; uint32_t reserved_size; uint32_t available_size; struct sysctl_ctx_list nvm_ctx; struct sysctl_oid *nvm_oid; }; struct bnxt_func_qcfg { uint16_t alloc_completion_rings; uint16_t alloc_tx_rings; uint16_t alloc_rx_rings; uint16_t alloc_vnics; }; struct bnxt_hw_lro { uint16_t enable; uint16_t is_mode_gro; uint16_t max_agg_segs; uint16_t max_aggs; uint32_t min_agg_len; }; /* The hardware supports certain page sizes. Use the supported page sizes * to allocate the rings. */ #if (PAGE_SHIFT < 12) #define BNXT_PAGE_SHIFT 12 #elif (PAGE_SHIFT <= 13) #define BNXT_PAGE_SHIFT PAGE_SHIFT #elif (PAGE_SHIFT < 16) #define BNXT_PAGE_SHIFT 13 #else #define BNXT_PAGE_SHIFT 16 #endif #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) struct bnxt_ring_mem_info { int nr_pages; int page_size; uint16_t flags; #define BNXT_RMEM_VALID_PTE_FLAG 1 #define BNXT_RMEM_RING_PTE_FLAG 2 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4 uint16_t depth; struct bnxt_ctx_mem_type *ctx_mem; struct iflib_dma_info *pg_arr; struct iflib_dma_info pg_tbl; int vmem_size; void **vmem; }; struct bnxt_ctx_pg_info { uint32_t entries; uint32_t nr_pages; struct iflib_dma_info ctx_arr[MAX_CTX_PAGES]; struct bnxt_ring_mem_info ring_mem; struct bnxt_ctx_pg_info **ctx_pg_tbl; }; #define BNXT_MAX_TQM_SP_RINGS 1 #define BNXT_MAX_TQM_FP_LEGACY_RINGS 8 #define BNXT_MAX_TQM_FP_RINGS 9 #define BNXT_MAX_TQM_LEGACY_RINGS \ (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS) #define BNXT_MAX_TQM_RINGS \ (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 #define BNXT_BACKING_STORE_CFG_LEN \ sizeof(struct hwrm_func_backing_store_cfg_input) #define BNXT_SET_CTX_PAGE_ATTR(attr) \ do { \ if (BNXT_PAGE_SIZE == 0x2000) \ attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_SRQ_PG_SIZE_PG_8K; \ else if (BNXT_PAGE_SIZE == 0x10000) \ attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_QPC_PG_SIZE_PG_64K; \ else \ attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_QPC_PG_SIZE_PG_4K; \ } while (0) struct bnxt_ctx_mem_type { u16 type; u16 entry_size; u32 flags; #define BNXT_CTX_MEM_TYPE_VALID HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID u32 instance_bmap; u8 init_value; u8 entry_multiple; u16 init_offset; #define BNXT_CTX_INIT_INVALID_OFFSET 0xffff u32 max_entries; u32 min_entries; u8 split_entry_cnt; #define BNXT_MAX_SPLIT_ENTRY 4 union { struct { u32 qp_l2_entries; u32 qp_qp1_entries; }; u32 srq_l2_entries; u32 cq_l2_entries; u32 vnic_entries; struct { u32 mrav_av_entries; u32 mrav_num_entries_units; }; u32 split[BNXT_MAX_SPLIT_ENTRY]; }; struct bnxt_ctx_pg_info *pg_info; }; #define BNXT_CTX_QP HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP #define BNXT_CTX_SRQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ #define BNXT_CTX_CQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ #define BNXT_CTX_VNIC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC #define BNXT_CTX_STAT HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT #define BNXT_CTX_STQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING #define BNXT_CTX_FTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING #define BNXT_CTX_MRAV HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV #define BNXT_CTX_TIM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM #define BNXT_CTX_TKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC #define BNXT_CTX_RKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC #define BNXT_CTX_MTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING #define BNXT_CTX_SQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW #define BNXT_CTX_RQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW #define BNXT_CTX_SRQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW #define BNXT_CTX_CQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW #define BNXT_CTX_QTKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC #define BNXT_CTX_QRKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC #define BNXT_CTX_MAX (BNXT_CTX_QRKC + 1) struct bnxt_ctx_mem_info { u8 tqm_fp_rings_count; u32 flags; #define BNXT_CTX_FLAG_INITED 0x01 struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_MAX]; }; struct bnxt_hw_resc { uint16_t min_rsscos_ctxs; uint16_t max_rsscos_ctxs; uint16_t min_cp_rings; uint16_t max_cp_rings; uint16_t resv_cp_rings; uint16_t min_tx_rings; uint16_t max_tx_rings; uint16_t resv_tx_rings; uint16_t max_tx_sch_inputs; uint16_t min_rx_rings; uint16_t max_rx_rings; uint16_t resv_rx_rings; uint16_t min_hw_ring_grps; uint16_t max_hw_ring_grps; uint16_t resv_hw_ring_grps; uint16_t min_l2_ctxs; uint16_t max_l2_ctxs; uint16_t min_vnics; uint16_t max_vnics; uint16_t resv_vnics; uint16_t min_stat_ctxs; uint16_t max_stat_ctxs; uint16_t resv_stat_ctxs; uint16_t max_nqs; uint16_t max_irqs; uint16_t resv_irqs; }; enum bnxt_type_ets { BNXT_TYPE_ETS_TSA = 0, BNXT_TYPE_ETS_PRI2TC, BNXT_TYPE_ETS_TCBW, BNXT_TYPE_ETS_MAX }; static const char *const BNXT_ETS_TYPE_STR[] = { "tsa", "pri2tc", "tcbw", }; static const char *const BNXT_ETS_HELP_STR[] = { "X is 1 (strict), 0 (ets)", "TC values for pri 0 to 7", "TC BW values for pri 0 to 7, Sum should be 100", }; #define BNXT_HWRM_MAX_REQ_LEN (softc->hwrm_max_req_len) struct bnxt_softc_list { SLIST_ENTRY(bnxt_softc_list) next; struct bnxt_softc *softc; }; #ifndef BIT_ULL #define BIT_ULL(nr) (1ULL << (nr)) #endif struct bnxt_aux_dev { struct auxiliary_device aux_dev; struct bnxt_en_dev *edev; int id; }; struct bnxt_msix_tbl { uint32_t entry; uint32_t vector; }; +enum bnxt_health_severity { + SEVERITY_NORMAL = 0, + SEVERITY_WARNING, + SEVERITY_RECOVERABLE, + SEVERITY_FATAL, +}; + +enum bnxt_health_remedy { + REMEDY_DEVLINK_RECOVER, + REMEDY_POWER_CYCLE_DEVICE, + REMEDY_POWER_CYCLE_HOST, + REMEDY_FW_UPDATE, + REMEDY_HW_REPLACE, +}; + +struct bnxt_fw_health { + u32 flags; + u32 polling_dsecs; + u32 master_func_wait_dsecs; + u32 normal_func_wait_dsecs; + u32 post_reset_wait_dsecs; + u32 post_reset_max_wait_dsecs; + u32 regs[4]; + u32 mapped_regs[4]; +#define BNXT_FW_HEALTH_REG 0 +#define BNXT_FW_HEARTBEAT_REG 1 +#define BNXT_FW_RESET_CNT_REG 2 +#define BNXT_FW_RESET_INPROG_REG 3 + u32 fw_reset_inprog_reg_mask; + u32 last_fw_heartbeat; + u32 last_fw_reset_cnt; + u8 enabled:1; + u8 primary:1; + u8 status_reliable:1; + u8 resets_reliable:1; + u8 tmr_multiplier; + u8 tmr_counter; + u8 fw_reset_seq_cnt; + u32 fw_reset_seq_regs[16]; + u32 fw_reset_seq_vals[16]; + u32 fw_reset_seq_delay_msec[16]; + u32 echo_req_data1; + u32 echo_req_data2; + struct devlink_health_reporter *fw_reporter; + struct mutex lock; + enum bnxt_health_severity severity; + enum bnxt_health_remedy remedy; + u32 arrests; + u32 discoveries; + u32 survivals; + u32 fatalities; + u32 diagnoses; +}; + +#define BNXT_FW_HEALTH_REG_TYPE_MASK 3 +#define BNXT_FW_HEALTH_REG_TYPE_CFG 0 +#define BNXT_FW_HEALTH_REG_TYPE_GRC 1 +#define BNXT_FW_HEALTH_REG_TYPE_BAR0 2 +#define BNXT_FW_HEALTH_REG_TYPE_BAR1 3 + +#define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK) +#define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK) + +#define BNXT_FW_HEALTH_WIN_BASE 0x3000 +#define BNXT_FW_HEALTH_WIN_MAP_OFF 8 + +#define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \ + ((reg) & BNXT_GRC_OFFSET_MASK)) + +#define BNXT_FW_STATUS_HEALTH_MSK 0xffff +#define BNXT_FW_STATUS_HEALTHY 0x8000 +#define BNXT_FW_STATUS_SHUTDOWN 0x100000 +#define BNXT_FW_STATUS_RECOVERING 0x400000 + +#define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\ + BNXT_FW_STATUS_HEALTHY) + +#define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \ + BNXT_FW_STATUS_HEALTHY) + +#define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \ + BNXT_FW_STATUS_HEALTHY) + +#define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \ + ((sts) & BNXT_FW_STATUS_RECOVERING)) + +#define BNXT_FW_RETRY 5 +#define BNXT_FW_IF_RETRY 10 +#define BNXT_FW_SLOT_RESET_RETRY 4 + +#define BNXT_GRCPF_REG_CHIMP_COMM 0x0 +#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 +#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 +#define BNXT_GRCPF_REG_SYNC_TIME 0x480 +#define BNXT_GRCPF_REG_SYNC_TIME_ADJ 0x488 +#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_MSK 0xffffffUL +#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_SFT 0 +#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_MSK 0x1f000000UL +#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_SFT 24 +#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_MSK 0x20000000UL +#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_SFT 29 + +#define BNXT_GRC_REG_STATUS_P5 0x520 + +#define BNXT_GRCPF_REG_KONG_COMM 0xA00 +#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00 + +#define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 +#define BNXT_CAG_REG_BASE 0x300000 + +#define BNXT_GRC_REG_CHIP_NUM 0x48 +#define BNXT_GRC_REG_BASE 0x260000 + +#define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c +#define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810 + +#define BNXT_GRC_BASE_MASK 0xfffff000 +#define BNXT_GRC_OFFSET_MASK 0x00000ffc struct bnxt_softc { device_t dev; if_ctx_t ctx; if_softc_ctx_t scctx; if_shared_ctx_t sctx; if_t ifp; uint32_t domain; uint32_t bus; uint32_t slot; uint32_t function; uint32_t dev_fn; struct ifmedia *media; struct bnxt_ctx_mem_info *ctx_mem; struct bnxt_hw_resc hw_resc; struct bnxt_softc_list list; struct bnxt_bar_info hwrm_bar; struct bnxt_bar_info doorbell_bar; struct bnxt_link_info link_info; #define BNXT_FLAG_VF 0x0001 #define BNXT_FLAG_NPAR 0x0002 #define BNXT_FLAG_WOL_CAP 0x0004 #define BNXT_FLAG_SHORT_CMD 0x0008 #define BNXT_FLAG_FW_CAP_NEW_RM 0x0010 #define BNXT_FLAG_CHIP_P5 0x0020 #define BNXT_FLAG_TPA 0x0040 #define BNXT_FLAG_FW_CAP_EXT_STATS 0x0080 #define BNXT_FLAG_MULTI_HOST 0x0100 #define BNXT_FLAG_MULTI_ROOT 0x0200 #define BNXT_FLAG_ROCEV1_CAP 0x0400 #define BNXT_FLAG_ROCEV2_CAP 0x0800 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | BNXT_FLAG_ROCEV2_CAP) uint32_t flags; #define BNXT_STATE_LINK_CHANGE (0) #define BNXT_STATE_MAX (BNXT_STATE_LINK_CHANGE + 1) bitstr_t *state_bv; uint32_t total_irqs; struct bnxt_msix_tbl *irq_tbl; struct bnxt_func_info func; struct bnxt_func_qcfg fn_qcfg; struct bnxt_pf_info pf; struct bnxt_vf_info vf; uint16_t hwrm_cmd_seq; uint32_t hwrm_cmd_timeo; /* milliseconds */ struct iflib_dma_info hwrm_cmd_resp; struct iflib_dma_info hwrm_short_cmd_req_addr; /* Interrupt info for HWRM */ struct if_irq irq; struct mtx hwrm_lock; uint16_t hwrm_max_req_len; uint16_t hwrm_max_ext_req_len; uint32_t hwrm_spec_code; #define BNXT_MAX_QUEUE 8 uint8_t max_tc; uint8_t max_lltc; struct bnxt_queue_info tx_q_info[BNXT_MAX_QUEUE]; struct bnxt_queue_info rx_q_info[BNXT_MAX_QUEUE]; uint8_t tc_to_qidx[BNXT_MAX_QUEUE]; uint8_t tx_q_ids[BNXT_MAX_QUEUE]; uint8_t rx_q_ids[BNXT_MAX_QUEUE]; uint8_t tx_max_q; uint8_t rx_max_q; uint8_t is_asym_q; struct bnxt_ieee_ets *ieee_ets; struct bnxt_ieee_pfc *ieee_pfc; uint8_t dcbx_cap; uint8_t default_pri; uint8_t max_dscp_value; uint64_t admin_ticks; struct iflib_dma_info hw_rx_port_stats; struct iflib_dma_info hw_tx_port_stats; struct rx_port_stats *rx_port_stats; struct tx_port_stats *tx_port_stats; struct iflib_dma_info hw_tx_port_stats_ext; struct iflib_dma_info hw_rx_port_stats_ext; struct tx_port_stats_ext *tx_port_stats_ext; struct rx_port_stats_ext *rx_port_stats_ext; uint16_t fw_rx_stats_ext_size; uint16_t fw_tx_stats_ext_size; uint16_t hw_ring_stats_size; uint8_t tx_pri2cos_idx[8]; uint8_t rx_pri2cos_idx[8]; bool pri2cos_valid; uint64_t tx_bytes_pri[8]; uint64_t tx_packets_pri[8]; uint64_t rx_bytes_pri[8]; uint64_t rx_packets_pri[8]; uint8_t port_count; int num_cp_rings; struct bnxt_cp_ring *nq_rings; struct bnxt_ring *tx_rings; struct bnxt_cp_ring *tx_cp_rings; struct iflib_dma_info tx_stats[BNXT_MAX_NUM_QUEUES]; int ntxqsets; struct bnxt_vnic_info vnic_info; struct bnxt_ring *ag_rings; struct bnxt_ring *rx_rings; struct bnxt_cp_ring *rx_cp_rings; struct bnxt_grp_info *grp_info; struct iflib_dma_info rx_stats[BNXT_MAX_NUM_QUEUES]; int nrxqsets; uint16_t rx_buf_size; struct bnxt_cp_ring def_cp_ring; struct bnxt_cp_ring def_nq_ring; struct iflib_dma_info def_cp_ring_mem; struct iflib_dma_info def_nq_ring_mem; struct grouptask def_cp_task; int db_size; int legacy_db_size; struct bnxt_doorbell_ops db_ops; struct sysctl_ctx_list hw_stats; struct sysctl_oid *hw_stats_oid; struct sysctl_ctx_list hw_lro_ctx; struct sysctl_oid *hw_lro_oid; struct sysctl_ctx_list flow_ctrl_ctx; struct sysctl_oid *flow_ctrl_oid; struct sysctl_ctx_list dcb_ctx; struct sysctl_oid *dcb_oid; struct bnxt_ver_info *ver_info; struct bnxt_nvram_info *nvm_info; bool wol; bool is_dev_init; struct bnxt_hw_lro hw_lro; uint8_t wol_filter_id; uint16_t rx_coal_usecs; uint16_t rx_coal_usecs_irq; uint16_t rx_coal_frames; uint16_t rx_coal_frames_irq; uint16_t tx_coal_usecs; uint16_t tx_coal_usecs_irq; uint16_t tx_coal_frames; uint16_t tx_coal_frames_irq; #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) #define BNXT_DEF_STATS_COAL_TICKS 1000000 #define BNXT_MIN_STATS_COAL_TICKS 250000 #define BNXT_MAX_STATS_COAL_TICKS 1000000 uint64_t fw_cap; #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0) #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1) #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2) #define BNXT_FW_CAP_NEW_RM BIT_ULL(3) #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4) #define BNXT_FW_CAP_LINK_ADMIN BIT_ULL(5) #define BNXT_FW_CAP_VF_RES_MIN_GUARANTEED BIT_ULL(6) #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7) #define BNXT_FW_CAP_ADMIN_MTU BIT_ULL(8) #define BNXT_FW_CAP_ADMIN_PF BIT_ULL(9) #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10) #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11) #define BNXT_FW_CAP_VF_VNIC_NOTIFY BIT_ULL(12) #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13) #define BNXT_FW_CAP_PKG_VER BIT_ULL(14) #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15) #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16) #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17) #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18) #define BNXT_FW_CAP_SECURE_MODE BIT_ULL(19) #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20) #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21) #define BNXT_FW_CAP_CRASHDUMP BIT_ULL(23) #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24) #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25) #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26) #define BNXT_FW_CAP_CFA_EEM BIT_ULL(27) #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(29) #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30) #define BNXT_FW_CAP_ECN_STATS BIT_ULL(31) #define BNXT_FW_CAP_TRUFLOW BIT_ULL(32) #define BNXT_FW_CAP_VF_CFG_FOR_PF BIT_ULL(33) #define BNXT_FW_CAP_PTP_PPS BIT_ULL(34) #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(35) #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(36) #define BNXT_FW_CAP_NPAR_1_2 BIT_ULL(37) #define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA BIT_ULL(38) #define BNXT_FW_CAP_PTP_RTC BIT_ULL(39) #define BNXT_FW_CAP_TRUFLOW_EN BIT_ULL(40) #define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN) #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(41) #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(42) #define BNXT_FW_CAP_DBR_SUPPORTED BIT_ULL(43) #define BNXT_FW_CAP_GENERIC_STATS BIT_ULL(44) #define BNXT_FW_CAP_DBR_PACING_SUPPORTED BIT_ULL(45) #define BNXT_FW_CAP_PTP_PTM BIT_ULL(46) #define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(47) #define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(48) #define BNXT_FW_CAP_RSS_TCAM BIT_ULL(49) uint32_t lpi_tmr_lo; uint32_t lpi_tmr_hi; /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */ uint16_t phy_flags; #define BNXT_PHY_FL_EEE_CAP HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED #define BNXT_PHY_FL_EXT_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED #define BNXT_PHY_FL_AN_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED #define BNXT_PHY_FL_SHARED_PORT_CFG HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED #define BNXT_PHY_FL_PORT_STATS_NO_RESET HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET #define BNXT_PHY_FL_NO_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED #define BNXT_PHY_FL_FW_MANAGED_LKDN HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN #define BNXT_PHY_FL_NO_FCS HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS #define BNXT_PHY_FL_NO_PAUSE (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED << 8) #define BNXT_PHY_FL_NO_PFC (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED << 8) #define BNXT_PHY_FL_BANK_SEL (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED << 8) struct bnxt_aux_dev *aux_dev; struct net_device *net_dev; struct mtx en_ops_lock; uint8_t port_partition_type; struct bnxt_en_dev *edev; unsigned long state; #define BNXT_STATE_OPEN 0 #define BNXT_STATE_IN_SP_TASK 1 #define BNXT_STATE_READ_STATS 2 #define BNXT_STATE_FW_RESET_DET 3 #define BNXT_STATE_IN_FW_RESET 4 #define BNXT_STATE_ABORT_ERR 5 #define BNXT_STATE_FW_FATAL_COND 6 #define BNXT_STATE_DRV_REGISTERED 7 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8 #define BNXT_STATE_NAPI_DISABLED 9 #define BNXT_STATE_L2_FILTER_RETRY 10 #define BNXT_STATE_FW_ACTIVATE 11 #define BNXT_STATE_RECOVER 12 #define BNXT_STATE_FW_NON_FATAL_COND 13 #define BNXT_STATE_FW_ACTIVATE_RESET 14 #define BNXT_STATE_HALF_OPEN 15 #define BNXT_NO_FW_ACCESS(bp) \ test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) struct pci_dev *pdev; - int fw_reset_state; + struct work_struct sp_task; + unsigned long sp_event; +#define BNXT_RX_MASK_SP_EVENT 0 +#define BNXT_RX_NTP_FLTR_SP_EVENT 1 +#define BNXT_LINK_CHNG_SP_EVENT 2 +#define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 +#define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 +#define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 +#define BNXT_RESET_TASK_SP_EVENT 6 +#define BNXT_RST_RING_SP_EVENT 7 +#define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 +#define BNXT_PERIODIC_STATS_SP_EVENT 9 +#define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 +#define BNXT_RESET_TASK_SILENT_SP_EVENT 11 +#define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 +#define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 +#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 +#define BNXT_FLOW_STATS_SP_EVENT 15 +#define BNXT_UPDATE_PHY_SP_EVENT 16 +#define BNXT_RING_COAL_NOW_SP_EVENT 17 +#define BNXT_FW_RESET_NOTIFY_SP_EVENT 18 +#define BNXT_FW_EXCEPTION_SP_EVENT 19 +#define BNXT_VF_VNIC_CHANGE_SP_EVENT 20 +#define BNXT_LINK_CFG_CHANGE_SP_EVENT 21 +#define BNXT_PTP_CURRENT_TIME_EVENT 22 +#define BNXT_FW_ECHO_REQUEST_SP_EVENT 23 +#define BNXT_VF_CFG_CHNG_SP_EVENT 24 + + struct delayed_work fw_reset_task; + int fw_reset_state; +#define BNXT_FW_RESET_STATE_POLL_VF 1 +#define BNXT_FW_RESET_STATE_RESET_FW 2 +#define BNXT_FW_RESET_STATE_ENABLE_DEV 3 +#define BNXT_FW_RESET_STATE_POLL_FW 4 +#define BNXT_FW_RESET_STATE_OPENING 5 +#define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6 + u16 fw_reset_min_dsecs; +#define BNXT_DFLT_FW_RST_MIN_DSECS 20 + u16 fw_reset_max_dsecs; +#define BNXT_DFLT_FW_RST_MAX_DSECS 60 + unsigned long fw_reset_timestamp; + + struct bnxt_fw_health *fw_health; }; struct bnxt_filter_info { STAILQ_ENTRY(bnxt_filter_info) next; uint64_t fw_l2_filter_id; #define INVALID_MAC_INDEX ((uint16_t)-1) uint16_t mac_index; /* Filter Characteristics */ uint32_t flags; uint32_t enables; uint8_t l2_addr[ETHER_ADDR_LEN]; uint8_t l2_addr_mask[ETHER_ADDR_LEN]; uint16_t l2_ovlan; uint16_t l2_ovlan_mask; uint16_t l2_ivlan; uint16_t l2_ivlan_mask; uint8_t t_l2_addr[ETHER_ADDR_LEN]; uint8_t t_l2_addr_mask[ETHER_ADDR_LEN]; uint16_t t_l2_ovlan; uint16_t t_l2_ovlan_mask; uint16_t t_l2_ivlan; uint16_t t_l2_ivlan_mask; uint8_t tunnel_type; uint16_t mirror_vnic_id; uint32_t vni; uint8_t pri_hint; uint64_t l2_filter_id_hint; }; #define I2C_DEV_ADDR_A0 0xa0 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 /* Function declarations */ void bnxt_report_link(struct bnxt_softc *softc); bool bnxt_check_hwrm_version(struct bnxt_softc *softc); struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *name); int bnxt_read_sfp_module_eeprom_info(struct bnxt_softc *bp, uint16_t i2c_addr, uint16_t page_number, uint8_t bank, bool bank_sel_en, uint16_t start_addr, uint16_t data_length, uint8_t *buf); void bnxt_dcb_init(struct bnxt_softc *softc); void bnxt_dcb_free(struct bnxt_softc *softc); uint8_t bnxt_dcb_setdcbx(struct bnxt_softc *softc, uint8_t mode); uint8_t bnxt_dcb_getdcbx(struct bnxt_softc *softc); int bnxt_dcb_ieee_getets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets); int bnxt_dcb_ieee_setets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets); uint8_t get_phy_type(struct bnxt_softc *softc); int bnxt_dcb_ieee_getpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc); int bnxt_dcb_ieee_setpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc); int bnxt_dcb_ieee_setapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app); int bnxt_dcb_ieee_delapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app); int bnxt_dcb_ieee_listapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app, int *num_inputs); #endif /* _BNXT_H */ diff --git a/sys/dev/bnxt/bnxt_en/bnxt_hwrm.c b/sys/dev/bnxt/bnxt_en/bnxt_hwrm.c index 677869484ace..9252964900ff 100644 --- a/sys/dev/bnxt/bnxt_en/bnxt_hwrm.c +++ b/sys/dev/bnxt/bnxt_en/bnxt_hwrm.c @@ -1,3065 +1,3092 @@ /*- * Broadcom NetXtreme-C/E network driver. * * Copyright (c) 2016 Broadcom, All Rights Reserved. * The term Broadcom refers to Broadcom Limited and/or its subsidiaries * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "bnxt.h" #include "bnxt_hwrm.h" #include "hsi_struct_def.h" static int bnxt_hwrm_err_map(uint16_t err); static inline int _is_valid_ether_addr(uint8_t *); static inline void get_random_ether_addr(uint8_t *); static void bnxt_hwrm_set_link_common(struct bnxt_softc *softc, struct hwrm_port_phy_cfg_input *req); static void bnxt_hwrm_set_pause_common(struct bnxt_softc *softc, struct hwrm_port_phy_cfg_input *req); static void bnxt_hwrm_set_eee(struct bnxt_softc *softc, struct hwrm_port_phy_cfg_input *req); /* NVRam stuff has a five minute timeout */ #define BNXT_NVM_TIMEO (5 * 60 * 1000) #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ BNXT_RX_STATS_EXT_OFFSET(counter##_cos0) #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ BNXT_TX_STATS_EXT_OFFSET(counter##_cos0) #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ BNXT_RX_STATS_PRI_ENTRY(counter, 7) #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ BNXT_TX_STATS_PRI_ENTRY(counter, 7) long bnxt_rx_bytes_pri_arr_base_off[] = {BNXT_RX_STATS_PRI_ENTRIES(rx_bytes)}; long bnxt_rx_pkts_pri_arr_base_off[] = {BNXT_RX_STATS_PRI_ENTRIES(rx_packets)}; long bnxt_tx_bytes_pri_arr_base_off[] = {BNXT_TX_STATS_PRI_ENTRIES(tx_bytes)}; long bnxt_tx_pkts_pri_arr_base_off[] = {BNXT_TX_STATS_PRI_ENTRIES(tx_packets)}; static int bnxt_hwrm_err_map(uint16_t err) { int rc; switch (err) { case HWRM_ERR_CODE_SUCCESS: return 0; case HWRM_ERR_CODE_INVALID_PARAMS: case HWRM_ERR_CODE_INVALID_FLAGS: case HWRM_ERR_CODE_INVALID_ENABLES: return EINVAL; case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: return EACCES; case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: return ENOMEM; case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: return ENOSYS; case HWRM_ERR_CODE_FAIL: return EIO; case HWRM_ERR_CODE_HWRM_ERROR: case HWRM_ERR_CODE_UNKNOWN_ERR: default: return EDOOFUS; } return rc; } int bnxt_alloc_hwrm_dma_mem(struct bnxt_softc *softc) { int rc; rc = iflib_dma_alloc(softc->ctx, PAGE_SIZE, &softc->hwrm_cmd_resp, BUS_DMA_NOWAIT); return rc; } void bnxt_free_hwrm_dma_mem(struct bnxt_softc *softc) { if (softc->hwrm_cmd_resp.idi_vaddr) iflib_dma_free(&softc->hwrm_cmd_resp); softc->hwrm_cmd_resp.idi_vaddr = NULL; return; } void bnxt_hwrm_cmd_hdr_init(struct bnxt_softc *softc, void *request, uint16_t req_type) { struct input *req = request; req->req_type = htole16(req_type); req->cmpl_ring = 0xffff; req->target_id = 0xffff; req->resp_addr = htole64(softc->hwrm_cmd_resp.idi_paddr); } int _hwrm_send_message(struct bnxt_softc *softc, void *msg, uint32_t msg_len) { struct input *req = msg; struct hwrm_err_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; uint32_t *data = msg; int i; uint8_t *valid; uint16_t err; uint16_t max_req_len = BNXT_HWRM_MAX_REQ_LEN; struct hwrm_short_input short_input = {0}; /* TODO: DMASYNC in here. */ req->seq_id = htole16(softc->hwrm_cmd_seq++); memset(resp, 0, PAGE_SIZE); if (BNXT_NO_FW_ACCESS(softc) && (req->req_type != HWRM_FUNC_RESET && req->req_type != HWRM_VER_GET)) return -EINVAL; if ((softc->flags & BNXT_FLAG_SHORT_CMD) || msg_len > BNXT_HWRM_MAX_REQ_LEN) { void *short_cmd_req = softc->hwrm_short_cmd_req_addr.idi_vaddr; uint16_t max_msg_len; /* Set boundary for maximum extended request length for short * cmd format. If passed up from device use the max supported * internal req length. */ max_msg_len = softc->hwrm_max_ext_req_len; memcpy(short_cmd_req, req, msg_len); if (msg_len < max_msg_len) memset((uint8_t *) short_cmd_req + msg_len, 0, max_msg_len - msg_len); short_input.req_type = req->req_type; short_input.signature = htole16(HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD); short_input.size = htole16(msg_len); short_input.req_addr = htole64(softc->hwrm_short_cmd_req_addr.idi_paddr); data = (uint32_t *)&short_input; msg_len = sizeof(short_input); /* Sync memory write before updating doorbell */ wmb(); max_req_len = BNXT_HWRM_SHORT_REQ_LEN; } /* Write request msg to hwrm channel */ for (i = 0; i < msg_len; i += 4) { bus_space_write_4(softc->hwrm_bar.tag, softc->hwrm_bar.handle, i, *data); data++; } /* Clear to the end of the request buffer */ for (i = msg_len; i < max_req_len; i += 4) bus_space_write_4(softc->hwrm_bar.tag, softc->hwrm_bar.handle, i, 0); /* Ring channel doorbell */ bus_space_write_4(softc->hwrm_bar.tag, softc->hwrm_bar.handle, 0x100, htole32(1)); /* Check if response len is updated */ for (i = 0; i < softc->hwrm_cmd_timeo; i++) { if (resp->resp_len && resp->resp_len <= 4096) break; DELAY(1000); } if (i >= softc->hwrm_cmd_timeo) { device_printf(softc->dev, "Timeout sending %s: (timeout: %u) seq: %d\n", GET_HWRM_REQ_TYPE(req->req_type), softc->hwrm_cmd_timeo, le16toh(req->seq_id)); return ETIMEDOUT; } /* Last byte of resp contains the valid key */ valid = (uint8_t *)resp + resp->resp_len - 1; for (i = 0; i < softc->hwrm_cmd_timeo; i++) { if (*valid == HWRM_RESP_VALID_KEY) break; DELAY(1000); } if (i >= softc->hwrm_cmd_timeo) { device_printf(softc->dev, "Timeout sending %s: " "(timeout: %u) msg {0x%x 0x%x} len:%d v: %d\n", GET_HWRM_REQ_TYPE(req->req_type), softc->hwrm_cmd_timeo, le16toh(req->req_type), le16toh(req->seq_id), msg_len, *valid); return ETIMEDOUT; } err = le16toh(resp->error_code); if (err) { /* HWRM_ERR_CODE_FAIL is a "normal" error, don't log */ if (err != HWRM_ERR_CODE_FAIL) { device_printf(softc->dev, "%s command returned %s error.\n", GET_HWRM_REQ_TYPE(req->req_type), GET_HWRM_ERROR_CODE(err)); } return bnxt_hwrm_err_map(err); } return 0; } int hwrm_send_message(struct bnxt_softc *softc, void *msg, uint32_t msg_len) { int rc; BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, msg, msg_len); BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_queue_qportcfg(struct bnxt_softc *softc, uint32_t path_dir) { int rc = 0; struct hwrm_queue_qportcfg_input req = {0}; struct hwrm_queue_qportcfg_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; uint8_t max_tc, max_lltc, *max_q; uint8_t queue_profile, queue_id; struct bnxt_queue_info *q_info; uint8_t i, j, *qptr, *q_ids; bool no_rdma; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_QUEUE_QPORTCFG); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto qportcfg_exit; if (!resp->max_configurable_queues) { rc = -EINVAL; goto qportcfg_exit; } if (resp->queue_cfg_info & HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG) { softc->is_asym_q = true; /* bnxt_init_cosq_names(softc, path_dir); */ } else { softc->is_asym_q = false; /* bnxt_free_stats_cosqnames_mem(softc); */ } max_tc = min_t(uint8_t, resp->max_configurable_queues, BNXT_MAX_QUEUE); max_lltc = resp->max_configurable_lossless_queues; /* * No RDMA support yet. * no_rdma = !(softc->flags & BNXT_FLAG_ROCE_CAP); */ no_rdma = true; qptr = &resp->queue_id0; if (path_dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) { q_info = softc->tx_q_info; q_ids = softc->tx_q_ids; max_q = &softc->tx_max_q; } else { q_info = softc->rx_q_info; q_ids = softc->rx_q_ids; max_q = &softc->rx_max_q; } for (i = 0, j = 0; i < max_tc; i++) { queue_id = *qptr; qptr++; queue_profile = *qptr; qptr++; q_info[j].queue_id = queue_id; q_info[j].queue_profile = queue_profile; q_ids[i] = queue_id; softc->tc_to_qidx[j] = j; if (!BNXT_CNPQ(q_info[j].queue_profile) || (no_rdma && BNXT_PF(softc))) j++; } *max_q = max_tc; max_tc = max_t(uint8_t, j, 1); softc->max_tc = softc->max_tc ? min(softc->max_tc, max_tc) : max_tc; softc->max_lltc = softc->max_lltc ? min(softc->max_lltc, max_lltc) : max_lltc; if (softc->max_lltc > softc->max_tc) softc->max_lltc = softc->max_tc; qportcfg_exit: BNXT_HWRM_UNLOCK(softc); return rc; } static int bnxt_alloc_all_ctx_pg_info(struct bnxt_softc *softc) { struct bnxt_ctx_mem_info *ctx = softc->ctx_mem; u16 type; for (type = 0; type < BNXT_CTX_MAX; type++) { struct bnxt_ctx_mem_type *ctxm = &ctx->ctx_arr[type]; int n = 1; if (!ctxm->max_entries || ctxm->pg_info) continue; if (ctxm->instance_bmap) n = hweight32(ctxm->instance_bmap); ctxm->pg_info = kcalloc(n, sizeof(*ctxm->pg_info), GFP_KERNEL); if (!ctxm->pg_info) return -ENOMEM; } return 0; } static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_type *ctxm, u8 init_val, u8 init_offset, bool init_mask_set) { ctxm->init_value = init_val; ctxm->init_offset = BNXT_CTX_INIT_INVALID_OFFSET; if (init_mask_set) ctxm->init_offset = init_offset * 4; else ctxm->init_value = 0; } int bnxt_hwrm_func_backing_store_qcaps(struct bnxt_softc *softc) { struct hwrm_func_backing_store_qcaps_input req = {0}; struct hwrm_func_backing_store_qcaps_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; if (softc->hwrm_spec_code < 0x10902 || softc->ctx_mem) return 0; if (BNXT_VF(softc)) return 0; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_BACKING_STORE_QCAPS); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (!rc) { struct bnxt_ctx_mem_type *ctxm; struct bnxt_ctx_mem_info *ctx; u8 init_val, init_idx = 0; u16 init_mask; ctx = softc->ctx_mem; if (!ctx) { ctx = malloc(sizeof(*ctx), M_DEVBUF, M_NOWAIT | M_ZERO); if (!ctx) { rc = -ENOMEM; goto ctx_err; } softc->ctx_mem = ctx; } init_val = resp->ctx_kind_initializer; init_mask = le16_to_cpu(resp->ctx_init_mask); ctxm = &ctx->ctx_arr[BNXT_CTX_QP]; ctxm->max_entries = le32_to_cpu(resp->qp_max_entries); ctxm->qp_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); ctxm->qp_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); ctxm->entry_size = le16_to_cpu(resp->qp_entry_size); bnxt_init_ctx_initializer(ctxm, init_val, resp->qp_init_offset, (init_mask & (1 << init_idx++)) != 0); ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ]; ctxm->srq_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); ctxm->max_entries = le32_to_cpu(resp->srq_max_entries); ctxm->entry_size = le16_to_cpu(resp->srq_entry_size); bnxt_init_ctx_initializer(ctxm, init_val, resp->srq_init_offset, (init_mask & (1 << init_idx++)) != 0); ctxm = &ctx->ctx_arr[BNXT_CTX_CQ]; ctxm->cq_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); ctxm->max_entries = le32_to_cpu(resp->cq_max_entries); ctxm->entry_size = le16_to_cpu(resp->cq_entry_size); bnxt_init_ctx_initializer(ctxm, init_val, resp->cq_init_offset, (init_mask & (1 << init_idx++)) != 0); ctxm = &ctx->ctx_arr[BNXT_CTX_VNIC]; ctxm->vnic_entries = le32_to_cpu(resp->vnic_max_vnic_entries); ctxm->max_entries = ctxm->vnic_entries + le16_to_cpu(resp->vnic_max_ring_table_entries); ctxm->entry_size = le16_to_cpu(resp->vnic_entry_size); bnxt_init_ctx_initializer(ctxm, init_val, resp->vnic_init_offset, (init_mask & (1 << init_idx++)) != 0); ctxm = &ctx->ctx_arr[BNXT_CTX_STAT]; ctxm->max_entries = le32_to_cpu(resp->stat_max_entries); ctxm->entry_size = le16_to_cpu(resp->stat_entry_size); bnxt_init_ctx_initializer(ctxm, init_val, resp->stat_init_offset, (init_mask & (1 << init_idx++)) != 0); ctxm = &ctx->ctx_arr[BNXT_CTX_STQM]; ctxm->entry_size = le16_to_cpu(resp->tqm_entry_size); ctxm->min_entries = le32_to_cpu(resp->tqm_min_entries_per_ring); ctxm->max_entries = le32_to_cpu(resp->tqm_max_entries_per_ring); ctxm->entry_multiple = resp->tqm_entries_multiple; if (!ctxm->entry_multiple) ctxm->entry_multiple = 1; memcpy(&ctx->ctx_arr[BNXT_CTX_FTQM], ctxm, sizeof(*ctxm)); ctxm = &ctx->ctx_arr[BNXT_CTX_MRAV]; ctxm->max_entries = le32_to_cpu(resp->mrav_max_entries); ctxm->entry_size = le16_to_cpu(resp->mrav_entry_size); ctxm->mrav_num_entries_units = le16_to_cpu(resp->mrav_num_entries_units); bnxt_init_ctx_initializer(ctxm, init_val, resp->mrav_init_offset, (init_mask & (1 << init_idx++)) != 0); ctxm = &ctx->ctx_arr[BNXT_CTX_TIM]; ctxm->entry_size = le16_to_cpu(resp->tim_entry_size); ctxm->max_entries = le32_to_cpu(resp->tim_max_entries); ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count; if (!ctx->tqm_fp_rings_count) ctx->tqm_fp_rings_count = softc->tx_max_q; else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_LEGACY_RINGS) ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_LEGACY_RINGS; if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS && softc->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) { ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext; if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS) ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS; } ctxm = &ctx->ctx_arr[BNXT_CTX_FTQM]; memcpy(ctxm, &ctx->ctx_arr[BNXT_CTX_STQM], sizeof(*ctxm)); ctxm->instance_bmap = (1 << ctx->tqm_fp_rings_count) - 1; rc = bnxt_alloc_all_ctx_pg_info(softc); } else { rc = 0; } ctx_err: BNXT_HWRM_UNLOCK(softc); return rc; } #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES \ (HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP | \ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ | \ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ | \ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC | \ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, uint8_t *pg_attr, uint64_t *pg_dir) { uint8_t pg_size = 0; if (BNXT_PAGE_SHIFT == 13) pg_size = 1 << 4; else if (BNXT_PAGE_SIZE == 16) pg_size = 2 << 4; *pg_attr = pg_size; if (rmem->depth >= 1) { if (rmem->depth == 2) *pg_attr |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2; else *pg_attr |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1; *pg_dir = htole64(rmem->pg_tbl.idi_paddr); } else { *pg_dir = htole64(rmem->pg_arr[0].idi_paddr); } } int bnxt_hwrm_func_backing_store_cfg(struct bnxt_softc *softc, uint32_t enables) { struct hwrm_func_backing_store_cfg_input req = {0}; struct bnxt_ctx_mem_info *ctx = softc->ctx_mem; struct bnxt_ctx_pg_info *ctx_pg; struct bnxt_ctx_mem_type *ctxm; u32 req_len = sizeof(req); __le32 *num_entries; u32 ena, flags = 0; __le64 *pg_dir; u8 *pg_attr; int i; if (!ctx) return 0; if (req_len > softc->hwrm_max_ext_req_len) req_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_BACKING_STORE_CFG); req.enables = htole32(enables); if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) { ctxm = &ctx->ctx_arr[BNXT_CTX_QP]; ctx_pg = ctxm->pg_info; req.qp_num_entries = cpu_to_le32(ctx_pg->entries); req.qp_num_qp1_entries = cpu_to_le16(ctxm->qp_qp1_entries); req.qp_num_l2_entries = cpu_to_le16(ctxm->qp_l2_entries); req.qp_entry_size = cpu_to_le16(ctxm->entry_size); bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.qpc_pg_size_qpc_lvl, &req.qpc_page_dir); } if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) { ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ]; ctx_pg = ctxm->pg_info; req.srq_num_entries = cpu_to_le32(ctx_pg->entries); req.srq_num_l2_entries = cpu_to_le16(ctxm->srq_l2_entries); req.srq_entry_size = cpu_to_le16(ctxm->entry_size); bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.srq_pg_size_srq_lvl, &req.srq_page_dir); } if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) { ctxm = &ctx->ctx_arr[BNXT_CTX_CQ]; ctx_pg = ctxm->pg_info; req.cq_num_entries = cpu_to_le32(ctx_pg->entries); req.cq_num_l2_entries = cpu_to_le16(ctxm->cq_l2_entries); req.cq_entry_size = cpu_to_le16(ctxm->entry_size); bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, &req.cq_page_dir); } if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV) { ctxm = &ctx->ctx_arr[BNXT_CTX_MRAV]; ctx_pg = ctxm->pg_info; req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); if (ctxm->mrav_num_entries_units) flags |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT; req.mrav_entry_size = cpu_to_le16(ctxm->entry_size); bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.mrav_pg_size_mrav_lvl, &req.mrav_page_dir); } if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM) { ctxm = &ctx->ctx_arr[BNXT_CTX_TIM]; ctx_pg = ctxm->pg_info; req.tim_num_entries = cpu_to_le32(ctx_pg->entries); req.tim_entry_size = cpu_to_le16(ctxm->entry_size); bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.tim_pg_size_tim_lvl, &req.tim_page_dir); } if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) { ctxm = &ctx->ctx_arr[BNXT_CTX_VNIC]; ctx_pg = ctxm->pg_info; req.vnic_num_vnic_entries = cpu_to_le16(ctxm->vnic_entries); req.vnic_num_ring_table_entries = cpu_to_le16(ctxm->max_entries - ctxm->vnic_entries); req.vnic_entry_size = cpu_to_le16(ctxm->entry_size); bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.vnic_pg_size_vnic_lvl, &req.vnic_page_dir); } if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) { ctxm = &ctx->ctx_arr[BNXT_CTX_STAT]; ctx_pg = ctxm->pg_info; req.stat_num_entries = cpu_to_le32(ctxm->max_entries); req.stat_entry_size = cpu_to_le16(ctxm->entry_size); bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.stat_pg_size_stat_lvl, &req.stat_page_dir); } ctxm = &ctx->ctx_arr[BNXT_CTX_STQM]; for (i = 0, num_entries = &req.tqm_sp_num_entries, pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, pg_dir = &req.tqm_sp_page_dir, ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP, ctx_pg = ctxm->pg_info; i < BNXT_MAX_TQM_LEGACY_RINGS; ctx_pg = &ctx->ctx_arr[BNXT_CTX_FTQM].pg_info[i], i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { if (!(enables & ena)) continue; req.tqm_entry_size = cpu_to_le16(ctxm->entry_size); *num_entries = cpu_to_le32(ctx_pg->entries); bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); } if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) { pg_attr = &req.tqm_ring8_pg_size_tqm_ring_lvl; pg_dir = &req.tqm_ring8_page_dir; ctx_pg = &ctx->ctx_arr[BNXT_CTX_FTQM].pg_info[8]; req.tqm_ring8_num_entries = cpu_to_le32(ctx_pg->entries); bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); } req.flags = cpu_to_le32(flags); return hwrm_send_message(softc, &req, sizeof(req)); } int bnxt_hwrm_func_resc_qcaps(struct bnxt_softc *softc, bool all) { struct hwrm_func_resource_qcaps_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; struct hwrm_func_resource_qcaps_input req = {0}; struct bnxt_hw_resc *hw_resc = &softc->hw_resc; int rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_RESOURCE_QCAPS); req.fid = htole16(0xffff); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) { rc = -EIO; goto hwrm_func_resc_qcaps_exit; } hw_resc->max_tx_sch_inputs = le16toh(resp->max_tx_scheduler_inputs); if (!all) goto hwrm_func_resc_qcaps_exit; hw_resc->min_rsscos_ctxs = le16toh(resp->min_rsscos_ctx); hw_resc->max_rsscos_ctxs = le16toh(resp->max_rsscos_ctx); hw_resc->min_cp_rings = le16toh(resp->min_cmpl_rings); hw_resc->max_cp_rings = le16toh(resp->max_cmpl_rings); hw_resc->min_tx_rings = le16toh(resp->min_tx_rings); hw_resc->max_tx_rings = le16toh(resp->max_tx_rings); hw_resc->min_rx_rings = le16toh(resp->min_rx_rings); hw_resc->max_rx_rings = le16toh(resp->max_rx_rings); hw_resc->min_hw_ring_grps = le16toh(resp->min_hw_ring_grps); hw_resc->max_hw_ring_grps = le16toh(resp->max_hw_ring_grps); hw_resc->min_l2_ctxs = le16toh(resp->min_l2_ctxs); hw_resc->max_l2_ctxs = le16toh(resp->max_l2_ctxs); hw_resc->min_vnics = le16toh(resp->min_vnics); hw_resc->max_vnics = le16toh(resp->max_vnics); hw_resc->min_stat_ctxs = le16toh(resp->min_stat_ctx); hw_resc->max_stat_ctxs = le16toh(resp->max_stat_ctx); if (BNXT_CHIP_P5(softc)) { hw_resc->max_nqs = le16toh(resp->max_msix); hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; } hwrm_func_resc_qcaps_exit: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_func_backing_store_cfg_v2(struct bnxt_softc *softc, struct bnxt_ctx_mem_type *ctxm, bool last) { struct hwrm_func_backing_store_cfg_v2_input req = {0}; u32 instance_bmap = ctxm->instance_bmap; int i, j, rc = 0, n = 1; __le32 *p; if (!(ctxm->flags & BNXT_CTX_MEM_TYPE_VALID) || !ctxm->pg_info) return 0; if (instance_bmap) n = hweight32(ctxm->instance_bmap); else instance_bmap = 1; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_BACKING_STORE_CFG_V2); req.type = cpu_to_le16(ctxm->type); req.entry_size = cpu_to_le16(ctxm->entry_size); for (i = 0, p = &req.split_entry_0; i < ctxm->split_entry_cnt; i++) p[i] = cpu_to_le32(ctxm->split[i]); for (i = 0, j = 0; j < n && !rc; i++) { struct bnxt_ctx_pg_info *ctx_pg; if (!(instance_bmap & (1 << i))) continue; req.instance = cpu_to_le16(i); ctx_pg = &ctxm->pg_info[j++]; if (!ctx_pg->entries) continue; req.num_entries = cpu_to_le32(ctx_pg->entries); bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.page_size_pbl_level, &req.page_dir); if (last && j == (n - 1)) req.flags = cpu_to_le32(HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_CFG_ALL_DONE); rc = hwrm_send_message(softc, &req, sizeof(req)); } return rc; } int bnxt_hwrm_passthrough(struct bnxt_softc *softc, void *req, uint32_t req_len, void *resp, uint32_t resp_len, uint32_t app_timeout) { int rc = 0; void *output = (void *)softc->hwrm_cmd_resp.idi_vaddr; struct input *input = req; uint32_t old_timeo; input->resp_addr = htole64(softc->hwrm_cmd_resp.idi_paddr); BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; if (input->req_type == HWRM_NVM_INSTALL_UPDATE) softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; else softc->hwrm_cmd_timeo = max(app_timeout, softc->hwrm_cmd_timeo); rc = _hwrm_send_message(softc, req, req_len); softc->hwrm_cmd_timeo = old_timeo; if (rc) { device_printf(softc->dev, "%s: %s command failed with rc: 0x%x\n", __FUNCTION__, GET_HWRM_REQ_TYPE(input->req_type), rc); goto fail; } memcpy(resp, output, resp_len); fail: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_ver_get(struct bnxt_softc *softc) { struct hwrm_ver_get_input req = {0}; struct hwrm_ver_get_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; const char nastr[] = ""; const char naver[] = ""; uint32_t dev_caps_cfg; uint16_t fw_maj, fw_min, fw_bld, fw_rsv, len; softc->hwrm_max_req_len = HWRM_MAX_REQ_LEN; softc->hwrm_cmd_timeo = 1000; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VER_GET); req.hwrm_intf_maj = HWRM_VERSION_MAJOR; req.hwrm_intf_min = HWRM_VERSION_MINOR; req.hwrm_intf_upd = HWRM_VERSION_UPDATE; BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; snprintf(softc->ver_info->hwrm_if_ver, BNXT_VERSTR_SIZE, "%d.%d.%d", resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, resp->hwrm_intf_upd_8b); softc->ver_info->hwrm_if_major = resp->hwrm_intf_maj_8b; softc->ver_info->hwrm_if_minor = resp->hwrm_intf_min_8b; softc->ver_info->hwrm_if_update = resp->hwrm_intf_upd_8b; strlcpy(softc->ver_info->driver_hwrm_if_ver, HWRM_VERSION_STR, BNXT_VERSTR_SIZE); strlcpy(softc->ver_info->hwrm_fw_name, resp->hwrm_fw_name, BNXT_NAME_SIZE); softc->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | resp->hwrm_intf_min_8b << 8 | resp->hwrm_intf_upd_8b; if (resp->hwrm_intf_maj_8b < 1) { device_printf(softc->dev, "HWRM interface %d.%d.%d is older " "than 1.0.0.\n", resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, resp->hwrm_intf_upd_8b); device_printf(softc->dev, "Please update firmware with HWRM " "interface 1.0.0 or newer.\n"); } if (resp->mgmt_fw_major == 0 && resp->mgmt_fw_minor == 0 && resp->mgmt_fw_build == 0) { strlcpy(softc->ver_info->mgmt_fw_ver, naver, BNXT_VERSTR_SIZE); strlcpy(softc->ver_info->mgmt_fw_name, nastr, BNXT_NAME_SIZE); } else { snprintf(softc->ver_info->mgmt_fw_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", resp->mgmt_fw_major, resp->mgmt_fw_minor, resp->mgmt_fw_build, resp->mgmt_fw_patch); strlcpy(softc->ver_info->mgmt_fw_name, resp->mgmt_fw_name, BNXT_NAME_SIZE); } if (resp->netctrl_fw_major == 0 && resp->netctrl_fw_minor == 0 && resp->netctrl_fw_build == 0) { strlcpy(softc->ver_info->netctrl_fw_ver, naver, BNXT_VERSTR_SIZE); strlcpy(softc->ver_info->netctrl_fw_name, nastr, BNXT_NAME_SIZE); } else { snprintf(softc->ver_info->netctrl_fw_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", resp->netctrl_fw_major, resp->netctrl_fw_minor, resp->netctrl_fw_build, resp->netctrl_fw_patch); strlcpy(softc->ver_info->netctrl_fw_name, resp->netctrl_fw_name, BNXT_NAME_SIZE); } if (resp->roce_fw_major == 0 && resp->roce_fw_minor == 0 && resp->roce_fw_build == 0) { strlcpy(softc->ver_info->roce_fw_ver, naver, BNXT_VERSTR_SIZE); strlcpy(softc->ver_info->roce_fw_name, nastr, BNXT_NAME_SIZE); } else { snprintf(softc->ver_info->roce_fw_ver, BNXT_VERSTR_SIZE, "%d.%d.%d.%d", resp->roce_fw_major, resp->roce_fw_minor, resp->roce_fw_build, resp->roce_fw_patch); strlcpy(softc->ver_info->roce_fw_name, resp->roce_fw_name, BNXT_NAME_SIZE); } fw_maj = le32toh(resp->hwrm_fw_major); if (softc->hwrm_spec_code > 0x10803 && fw_maj) { fw_min = le16toh(resp->hwrm_fw_minor); fw_bld = le16toh(resp->hwrm_fw_build); fw_rsv = le16toh(resp->hwrm_fw_patch); len = FW_VER_STR_LEN; } else { fw_maj = resp->hwrm_fw_maj_8b; fw_min = resp->hwrm_fw_min_8b; fw_bld = resp->hwrm_fw_bld_8b; fw_rsv = resp->hwrm_fw_rsvd_8b; len = BC_HWRM_STR_LEN; } softc->ver_info->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv); snprintf (softc->ver_info->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld, fw_rsv); if (strlen(resp->active_pkg_name)) { int fw_ver_len = strlen (softc->ver_info->fw_ver_str); snprintf(softc->ver_info->fw_ver_str + fw_ver_len, FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", resp->active_pkg_name); softc->fw_cap |= BNXT_FW_CAP_PKG_VER; } softc->ver_info->chip_num = le16toh(resp->chip_num); softc->ver_info->chip_rev = resp->chip_rev; softc->ver_info->chip_metal = resp->chip_metal; softc->ver_info->chip_bond_id = resp->chip_bond_id; softc->ver_info->chip_type = resp->chip_platform_type; if (resp->hwrm_intf_maj_8b >= 1) { softc->hwrm_max_req_len = le16toh(resp->max_req_win_len); softc->hwrm_max_ext_req_len = le16toh(resp->max_ext_req_len); } softc->hwrm_cmd_timeo = le16toh(resp->def_req_timeout); if (!softc->hwrm_cmd_timeo) softc->hwrm_cmd_timeo = DFLT_HWRM_CMD_TIMEOUT; dev_caps_cfg = le32toh(resp->dev_caps_cfg); if ((dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && (dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) softc->flags |= BNXT_FLAG_SHORT_CMD; if ((dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && (dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) softc->fw_cap |= BNXT_FW_CAP_SHORT_CMD; if (dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; if (dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; if (dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; if (dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; if (dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_CFA_EEM; if (dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN; fail: BNXT_HWRM_UNLOCK(softc); return rc; } -int -bnxt_hwrm_func_drv_rgtr(struct bnxt_softc *softc) -{ +static const u16 bnxt_async_events_arr[] = { + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT, + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE, +}; + +int bnxt_hwrm_func_drv_rgtr(struct bnxt_softc *bp, unsigned long *bmap, int bmap_size, + bool async_only) +{ + DECLARE_BITMAP(async_events_bmap, 256); + u32 *events = (u32 *)async_events_bmap; + struct hwrm_func_drv_rgtr_output *resp = + (void *)bp->hwrm_cmd_resp.idi_vaddr; struct hwrm_func_drv_rgtr_input req = {0}; + u32 flags = 0; + int rc; + int i; - bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_DRV_RGTR); - - req.enables = htole32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER | - HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE); - req.os_type = htole16(HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD); - + bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR); req.ver_maj = HWRM_VERSION_MAJOR; req.ver_min = HWRM_VERSION_MINOR; req.ver_upd = HWRM_VERSION_UPDATE; - return hwrm_send_message(softc, &req, sizeof(req)); + req.enables = htole32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE | + HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER | + HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD); + + if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) + flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT; + if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) + flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT | + HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT; + if (bp->fw_cap & BNXT_FW_CAP_NPAR_1_2) + flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT; + flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT; + req.flags = htole32(flags); + req.os_type = htole16(HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD); + + if (BNXT_PF(bp)) { + req.enables |= + htole32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD); + } + + if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) + req.flags |= cpu_to_le32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE); + + memset(async_events_bmap, 0, sizeof(async_events_bmap)); + for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { + u16 event_id = bnxt_async_events_arr[i]; + + if (event_id == HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && + !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) { + continue; + } + __set_bit(bnxt_async_events_arr[i], async_events_bmap); + } + if (bmap && bmap_size) { + for (i = 0; i < bmap_size; i++) { + if (test_bit(i, bmap)) + __set_bit(i, async_events_bmap); + } + } + for (i = 0; i < 8; i++) + req.async_event_fwd[i] |= htole32(events[i]); + + if (async_only) + req.enables = + htole32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD); + + rc = hwrm_send_message(bp, &req, sizeof(req)); + + if (!rc) { + if (resp->flags & + le32toh(HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)) + bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; + } + + + return rc; } int bnxt_hwrm_func_drv_unrgtr(struct bnxt_softc *softc, bool shutdown) { struct hwrm_func_drv_unrgtr_input req = {0}; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_DRV_UNRGTR); if (shutdown == true) req.flags |= HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN; return hwrm_send_message(softc, &req, sizeof(req)); } static inline int _is_valid_ether_addr(uint8_t *addr) { char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) return (FALSE); return (TRUE); } static inline void get_random_ether_addr(uint8_t *addr) { uint8_t temp[ETHER_ADDR_LEN]; arc4rand(&temp, sizeof(temp), 0); temp[0] &= 0xFE; temp[0] |= 0x02; bcopy(temp, addr, sizeof(temp)); } int bnxt_hwrm_func_qcaps(struct bnxt_softc *softc) { int rc = 0; struct hwrm_func_qcaps_input req = {0}; struct hwrm_func_qcaps_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; struct bnxt_func_info *func = &softc->func; uint32_t flags, flags_ext, flags_ext2; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_QCAPS); req.fid = htole16(0xffff); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; flags = htole32(resp->flags); if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED) softc->flags |= BNXT_FLAG_WOL_CAP; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED) softc->flags |= BNXT_FLAG_FW_CAP_EXT_STATS; /* Enable RoCE only on Thor devices */ if (BNXT_CHIP_P5(softc)) { if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED) softc->flags |= BNXT_FLAG_ROCEV1_CAP; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED) softc->flags |= BNXT_FLAG_ROCEV2_CAP; } if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_LINK_ADMIN; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_ADMIN_PF; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE) softc->fw_cap |= BNXT_FW_CAP_HOT_RESET; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) softc->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD) softc->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_VF_VNIC_NOTIFY; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_CRASHDUMP; if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) softc->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT; if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_DBG_QCAPS; flags_ext = htole32(resp->flags_ext); if (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED; if (BNXT_PF(softc) && (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED)) softc->fw_cap |= BNXT_FW_CAP_ECN_STATS; if (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_PTP_PPS; if (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_PTP_PTM; if (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_PTP_RTC; if (BNXT_PF(softc) && (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT)) softc->fw_cap |= BNXT_FW_CAP_HOT_RESET_IF; if (BNXT_PF(softc) && (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED)) softc->fw_cap |= BNXT_FW_CAP_LIVEPATCH; if (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_NPAR_1_2; if (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_BACKING_STORE_V2; if (BNXT_PF(softc) && (flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED)) softc->fw_cap |= BNXT_FW_CAP_VF_CFG_FOR_PF; flags_ext2 = htole32(resp->flags_ext2); if (flags_ext2 & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS; if (flags_ext2 & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_DBR_SUPPORTED; if (flags_ext2 & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED || flags_ext & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DBR_PACING_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_DBR_PACING_SUPPORTED; if (flags_ext2 & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_GENERIC_STATS_SUPPORTED) softc->fw_cap |= BNXT_FW_CAP_GENERIC_STATS; func->fw_fid = le16toh(resp->fid); memcpy(func->mac_addr, resp->mac_address, ETHER_ADDR_LEN); func->max_rsscos_ctxs = le16toh(resp->max_rsscos_ctx); func->max_cp_rings = le16toh(resp->max_cmpl_rings); func->max_tx_rings = le16toh(resp->max_tx_rings); func->max_rx_rings = le16toh(resp->max_rx_rings); func->max_hw_ring_grps = le32toh(resp->max_hw_ring_grps); if (!func->max_hw_ring_grps) func->max_hw_ring_grps = func->max_tx_rings; func->max_l2_ctxs = le16toh(resp->max_l2_ctxs); func->max_vnics = le16toh(resp->max_vnics); func->max_stat_ctxs = le16toh(resp->max_stat_ctx); if (BNXT_PF(softc)) { struct bnxt_pf_info *pf = &softc->pf; pf->port_id = le16toh(resp->port_id); pf->first_vf_id = le16toh(resp->first_vf_id); pf->max_vfs = le16toh(resp->max_vfs); pf->max_encap_records = le32toh(resp->max_encap_records); pf->max_decap_records = le32toh(resp->max_decap_records); pf->max_tx_em_flows = le32toh(resp->max_tx_em_flows); pf->max_tx_wm_flows = le32toh(resp->max_tx_wm_flows); pf->max_rx_em_flows = le32toh(resp->max_rx_em_flows); pf->max_rx_wm_flows = le32toh(resp->max_rx_wm_flows); } if (!_is_valid_ether_addr(func->mac_addr)) { device_printf(softc->dev, "Invalid ethernet address, generating random locally administered address\n"); get_random_ether_addr(func->mac_addr); } fail: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_func_qcfg(struct bnxt_softc *softc) { struct hwrm_func_qcfg_input req = {0}; struct hwrm_func_qcfg_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; struct bnxt_func_qcfg *fn_qcfg = &softc->fn_qcfg; uint32_t min_db_offset = 0; uint16_t flags; int rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_QCFG); req.fid = htole16(0xffff); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto end; fn_qcfg->alloc_completion_rings = le16toh(resp->alloc_cmpl_rings); fn_qcfg->alloc_tx_rings = le16toh(resp->alloc_tx_rings); fn_qcfg->alloc_rx_rings = le16toh(resp->alloc_rx_rings); fn_qcfg->alloc_vnics = le16toh(resp->alloc_vnics); switch (resp->port_partition_type) { case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0: case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2: case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5: case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0: softc->port_partition_type = resp->port_partition_type; break; } flags = le16toh(resp->flags); if (flags & (HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED | HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED)) { softc->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED) softc->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; } if (BNXT_PF(softc) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST)) softc->flags |= BNXT_FLAG_MULTI_HOST; if (BNXT_PF(softc) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT)) softc->flags |= BNXT_FLAG_MULTI_ROOT; if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED) softc->fw_cap |= BNXT_FW_CAP_SECURE_MODE; if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED) softc->fw_cap |= BNXT_FW_CAP_RING_MONITOR; if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV) softc->fw_cap |= BNXT_FW_CAP_ENABLE_RDMA_SRIOV; if (softc->db_size) goto end; softc->legacy_db_size = le16_to_cpu(resp->legacy_l2_db_size_kb) * 1024; if (BNXT_CHIP_P5(softc)) { if (BNXT_PF(softc)) min_db_offset = DB_PF_OFFSET_P5; else min_db_offset = DB_VF_OFFSET_P5; } softc->db_size = roundup2(le16_to_cpu(resp->l2_doorbell_bar_size_kb) * 1024, PAGE_SIZE); if (!softc->db_size || softc->db_size > pci_resource_len(softc->pdev, 2) || softc->db_size <= min_db_offset) softc->db_size = pci_resource_len(softc->pdev, 2); end: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_func_reset(struct bnxt_softc *softc) { struct hwrm_func_reset_input req = {0}; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_RESET); req.enables = 0; return hwrm_send_message(softc, &req, sizeof(req)); } static void bnxt_hwrm_set_link_common(struct bnxt_softc *softc, struct hwrm_port_phy_cfg_input *req) { struct bnxt_link_info *link_info = &softc->link_info; uint8_t autoneg = softc->link_info.autoneg; uint16_t fw_link_speed = softc->link_info.req_link_speed; if (autoneg & BNXT_AUTONEG_SPEED) { uint8_t phy_type = get_phy_type(softc); if (phy_type == HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET || phy_type == HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET || phy_type == HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE) { req->auto_mode |= htole32(HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK); if (link_info->advertising) { req->enables |= htole32(HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK); req->auto_link_speed_mask = htole16(link_info->advertising); } } else { req->auto_mode |= HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS; } req->enables |= htole32(HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE); req->flags |= htole32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG); } else { req->flags |= htole32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE); if (link_info->force_pam4_speed_set_by_user) { req->force_pam4_link_speed = htole16(fw_link_speed); req->enables |= htole32(HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED); link_info->force_pam4_speed_set_by_user = false; } else { req->force_link_speed = htole16(fw_link_speed); } } /* tell chimp that the setting takes effect immediately */ req->flags |= htole32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY); } static void bnxt_hwrm_set_pause_common(struct bnxt_softc *softc, struct hwrm_port_phy_cfg_input *req) { struct bnxt_link_info *link_info = &softc->link_info; if (link_info->flow_ctrl.autoneg) { req->auto_pause = HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE; if (link_info->flow_ctrl.rx) req->auto_pause |= HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; if (link_info->flow_ctrl.tx) req->auto_pause |= HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; req->enables |= htole32(HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE); } else { if (link_info->flow_ctrl.rx) req->force_pause |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; if (link_info->flow_ctrl.tx) req->force_pause |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; req->enables |= htole32(HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE); req->auto_pause = req->force_pause; req->enables |= htole32(HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE); } } /* JFV this needs interface connection */ static void bnxt_hwrm_set_eee(struct bnxt_softc *softc, struct hwrm_port_phy_cfg_input *req) { /* struct ethtool_eee *eee = &softc->eee; */ bool eee_enabled = false; if (eee_enabled) { #if 0 uint16_t eee_speeds; uint32_t flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE; if (eee->tx_lpi_enabled) flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI; req->flags |= htole32(flags); eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); req->eee_link_speed_mask = htole16(eee_speeds); req->tx_lpi_timer = htole32(eee->tx_lpi_timer); #endif } else { req->flags |= htole32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE); } } int bnxt_hwrm_set_link_setting(struct bnxt_softc *softc, bool set_pause, bool set_eee, bool set_link) { struct hwrm_port_phy_cfg_input req = {0}; int rc; if (softc->flags & BNXT_FLAG_NPAR) return ENOTSUP; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_PORT_PHY_CFG); if (set_pause) { bnxt_hwrm_set_pause_common(softc, &req); if (softc->link_info.flow_ctrl.autoneg) set_link = true; } if (set_link) bnxt_hwrm_set_link_common(softc, &req); if (set_eee) bnxt_hwrm_set_eee(softc, &req); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (!rc) { if (set_pause) { /* since changing of 'force pause' setting doesn't * trigger any link change event, the driver needs to * update the current pause result upon successfully i * return of the phy_cfg command */ if (!softc->link_info.flow_ctrl.autoneg) bnxt_report_link(softc); } } BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_vnic_set_hds(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic) { struct hwrm_vnic_plcmodes_cfg_input req = {0}; if (!BNXT_CHIP_P5(softc)) return 0; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_PLCMODES_CFG); req.flags = htole32(HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT); req.vnic_id = htole16(vnic->id); return hwrm_send_message(softc, &req, sizeof(req)); } int bnxt_hwrm_vnic_cfg(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic) { struct hwrm_vnic_cfg_input req = {0}; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_CFG); if (vnic->flags & BNXT_VNIC_FLAG_DEFAULT) req.flags |= htole32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT); if (vnic->flags & BNXT_VNIC_FLAG_BD_STALL) req.flags |= htole32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE); if (vnic->flags & BNXT_VNIC_FLAG_VLAN_STRIP) req.flags |= htole32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE); if (BNXT_CHIP_P5 (softc)) { req.default_rx_ring_id = htole16(softc->rx_rings[0].phys_id); req.default_cmpl_ring_id = htole16(softc->rx_cp_rings[0].ring.phys_id); req.enables |= htole32(HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID | HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID); req.vnic_id = htole16(vnic->id); } else { req.enables = htole32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP | HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE); req.vnic_id = htole16(vnic->id); req.dflt_ring_grp = htole16(vnic->def_ring_grp); } req.rss_rule = htole16(vnic->rss_id); req.cos_rule = htole16(vnic->cos_rule); req.lb_rule = htole16(vnic->lb_rule); req.enables |= htole32(HWRM_VNIC_CFG_INPUT_ENABLES_MRU); req.mru = htole16(vnic->mru); return hwrm_send_message(softc, &req, sizeof(req)); } int bnxt_hwrm_vnic_free(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic) { struct hwrm_vnic_free_input req = {0}; int rc = 0; if (vnic->id == (uint16_t)HWRM_NA_SIGNATURE) return rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_FREE); req.vnic_id = htole32(vnic->id); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; fail: BNXT_HWRM_UNLOCK(softc); return (rc); } int bnxt_hwrm_vnic_alloc(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic) { struct hwrm_vnic_alloc_input req = {0}; struct hwrm_vnic_alloc_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; if (vnic->id != (uint16_t)HWRM_NA_SIGNATURE) { device_printf(softc->dev, "Attempt to re-allocate vnic %04x\n", vnic->id); return EDOOFUS; } bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_ALLOC); if (vnic->flags & BNXT_VNIC_FLAG_DEFAULT) req.flags = htole32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; vnic->id = le32toh(resp->vnic_id); fail: BNXT_HWRM_UNLOCK(softc); return (rc); } int bnxt_hwrm_vnic_ctx_free(struct bnxt_softc *softc, uint16_t ctx_id) { struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; int rc = 0; if (ctx_id == (uint16_t)HWRM_NA_SIGNATURE) return rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE); req.rss_cos_lb_ctx_id = htole16(ctx_id); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; fail: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_vnic_ctx_alloc(struct bnxt_softc *softc, uint16_t *ctx_id) { struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; if (*ctx_id != (uint16_t)HWRM_NA_SIGNATURE) { device_printf(softc->dev, "Attempt to re-allocate vnic ctx %04x\n", *ctx_id); return EDOOFUS; } bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; *ctx_id = le32toh(resp->rss_cos_lb_ctx_id); fail: BNXT_HWRM_UNLOCK(softc); return (rc); } int bnxt_hwrm_ring_grp_alloc(struct bnxt_softc *softc, struct bnxt_grp_info *grp) { struct hwrm_ring_grp_alloc_input req = {0}; struct hwrm_ring_grp_alloc_output *resp; int rc = 0; if (grp->grp_id != (uint16_t)HWRM_NA_SIGNATURE) { device_printf(softc->dev, "Attempt to re-allocate ring group %04x\n", grp->grp_id); return EDOOFUS; } if (BNXT_CHIP_P5 (softc)) return 0; resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_RING_GRP_ALLOC); req.cr = htole16(grp->cp_ring_id); req.rr = htole16(grp->rx_ring_id); req.ar = htole16(grp->ag_ring_id); req.sc = htole16(grp->stats_ctx); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; grp->grp_id = le32toh(resp->ring_group_id); fail: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_ring_grp_free(struct bnxt_softc *softc, struct bnxt_grp_info *grp) { struct hwrm_ring_grp_free_input req = {0}; int rc = 0; if (grp->grp_id == (uint16_t)HWRM_NA_SIGNATURE) return 0; if (BNXT_CHIP_P5 (softc)) return 0; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_RING_GRP_FREE); req.ring_group_id = htole32(grp->grp_id); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; fail: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_ring_free(struct bnxt_softc *softc, uint32_t ring_type, struct bnxt_ring *ring, int cmpl_ring_id) { struct hwrm_ring_free_input req = {0}; struct hwrm_ring_free_output *resp; int rc = 0; uint16_t error_code; if (ring->phys_id == (uint16_t)HWRM_NA_SIGNATURE) return 0; resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_RING_FREE); req.cmpl_ring = htole16(cmpl_ring_id); req.ring_type = ring_type; req.ring_id = htole16(ring->phys_id); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); error_code = le16toh(resp->error_code); if (rc || error_code) { device_printf(softc->dev, "hwrm_ring_free type %d failed. " "rc:%x err:%x\n", ring_type, rc, error_code); if (!rc) rc = -EIO; } BNXT_HWRM_UNLOCK(softc); return rc; } /* * Ring allocation message to the firmware */ int bnxt_hwrm_ring_alloc(struct bnxt_softc *softc, uint8_t type, struct bnxt_ring *ring) { struct hwrm_ring_alloc_input req = {0}; struct hwrm_ring_alloc_output *resp; uint16_t idx = ring->idx; struct bnxt_cp_ring *cp_ring; int rc; if (ring->phys_id != (uint16_t)HWRM_NA_SIGNATURE) { device_printf(softc->dev, "Attempt to re-allocate ring %04x\n", ring->phys_id); return EDOOFUS; } resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_RING_ALLOC); req.enables = htole32(0); req.fbo = htole32(0); req.ring_type = type; req.page_tbl_addr = htole64(ring->paddr); req.logical_id = htole16(ring->id); req.length = htole32(ring->ring_size); switch (type) { case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX: cp_ring = &softc->tx_cp_rings[idx]; req.cmpl_ring_id = htole16(cp_ring->ring.phys_id); /* queue_id - what CoS queue the TX ring is associated with */ req.queue_id = htole16(softc->tx_q_info[0].queue_id); req.stat_ctx_id = htole32(cp_ring->stats_ctx_id); req.enables |= htole32( HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID); break; case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX: if (!BNXT_CHIP_P5(softc)) break; cp_ring = &softc->rx_cp_rings[idx]; req.stat_ctx_id = htole32(cp_ring->stats_ctx_id); req.rx_buf_size = htole16(softc->rx_buf_size); req.enables |= htole32( HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID | HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID); break; case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG: if (!BNXT_CHIP_P5(softc)) { req.ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX; break; } cp_ring = &softc->rx_cp_rings[idx]; req.rx_ring_id = htole16(softc->rx_rings[idx].phys_id); req.stat_ctx_id = htole32(cp_ring->stats_ctx_id); req.rx_buf_size = htole16(softc->rx_buf_size); req.enables |= htole32( HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID | HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID | HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID); break; case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL: if (!BNXT_CHIP_P5(softc)) { req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX; break; } req.cq_handle = htole64(ring->id); req.nq_ring_id = htole16(softc->nq_rings[idx].ring.phys_id); req.enables |= htole32( HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID); break; case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ: req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX; break; default: device_printf(softc->dev, "hwrm alloc invalid ring type %d\n", type); return -1; } BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; ring->phys_id = le16toh(resp->ring_id); fail: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_stat_ctx_free(struct bnxt_softc *softc, struct bnxt_cp_ring *cpr) { struct hwrm_stat_ctx_free_input req = {0}; int rc = 0; if (cpr->stats_ctx_id == HWRM_NA_SIGNATURE) return rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_STAT_CTX_FREE); req.stat_ctx_id = htole16(cpr->stats_ctx_id); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; fail: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_stat_ctx_alloc(struct bnxt_softc *softc, struct bnxt_cp_ring *cpr, uint64_t paddr) { struct hwrm_stat_ctx_alloc_input req = {0}; struct hwrm_stat_ctx_alloc_output *resp; int rc = 0; if (cpr->stats_ctx_id != HWRM_NA_SIGNATURE) { device_printf(softc->dev, "Attempt to re-allocate stats ctx %08x\n", cpr->stats_ctx_id); return EDOOFUS; } resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_STAT_CTX_ALLOC); req.update_period_ms = htole32(1000); req.stats_dma_addr = htole64(paddr); if (BNXT_CHIP_P5(softc)) req.stats_dma_length = htole16(sizeof(struct ctx_hw_stats_ext) - 8); else req.stats_dma_length = htole16(sizeof(struct ctx_hw_stats)); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; cpr->stats_ctx_id = le32toh(resp->stat_ctx_id); fail: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_port_qstats(struct bnxt_softc *softc) { struct hwrm_port_qstats_input req = {0}; int rc = 0; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_PORT_QSTATS); req.port_id = htole16(softc->pf.port_id); req.rx_stat_host_addr = htole64(softc->hw_rx_port_stats.idi_paddr); req.tx_stat_host_addr = htole64(softc->hw_tx_port_stats.idi_paddr); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); BNXT_HWRM_UNLOCK(softc); return rc; } static int bnxt_hwrm_pri2cos_idx(struct bnxt_softc *softc, uint32_t path_dir) { struct hwrm_queue_pri2cos_qcfg_input req = {0}; struct hwrm_queue_pri2cos_qcfg_output *resp; uint8_t *pri2cos_idx, *q_ids, max_q; int rc, i, j; uint8_t *pri2cos; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_QUEUE_PRI2COS_QCFG); resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; req.flags = htole32(HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN | path_dir); rc = hwrm_send_message(softc, &req, sizeof(req)); if (rc) return rc; if (path_dir == HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX) { pri2cos_idx = softc->tx_pri2cos_idx; q_ids = softc->tx_q_ids; max_q = softc->tx_max_q; } else { pri2cos_idx = softc->rx_pri2cos_idx; q_ids = softc->rx_q_ids; max_q = softc->rx_max_q; } pri2cos = &resp->pri0_cos_queue_id; for (i = 0; i < BNXT_MAX_QUEUE; i++) { uint8_t queue_id = pri2cos[i]; uint8_t queue_idx; /* Per port queue IDs start from 0, 10, 20, etc */ queue_idx = queue_id % 10; if (queue_idx > BNXT_MAX_QUEUE) { softc->pri2cos_valid = false; rc = -EINVAL; return rc; } for (j = 0; j < max_q; j++) { if (q_ids[j] == queue_id) pri2cos_idx[i] = queue_idx; } } softc->pri2cos_valid = true; return rc; } int bnxt_hwrm_port_qstats_ext(struct bnxt_softc *softc) { struct hwrm_port_qstats_ext_input req = {0}; struct hwrm_port_qstats_ext_output *resp; int rc = 0, i; uint32_t tx_stat_size; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_PORT_QSTATS_EXT); resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; tx_stat_size = sizeof(struct tx_port_stats_ext); req.port_id = htole16(softc->pf.port_id); req.tx_stat_size = htole16(tx_stat_size); req.rx_stat_size = htole16(sizeof(struct rx_port_stats_ext)); req.rx_stat_host_addr = htole64(softc->hw_rx_port_stats_ext.idi_paddr); req.tx_stat_host_addr = htole64(softc->hw_tx_port_stats_ext.idi_paddr); rc = hwrm_send_message(softc, &req, sizeof(req)); if (!rc) { softc->fw_rx_stats_ext_size = le16toh(resp->rx_stat_size) / 8; if (BNXT_FW_MAJ(softc) < 220 && softc->fw_rx_stats_ext_size > BNXT_RX_STATS_EXT_NUM_LEGACY) softc->fw_rx_stats_ext_size = BNXT_RX_STATS_EXT_NUM_LEGACY; softc->fw_tx_stats_ext_size = tx_stat_size ? le16toh(resp->tx_stat_size) / 8 : 0; } else { softc->fw_rx_stats_ext_size = 0; softc->fw_tx_stats_ext_size = 0; } if (softc->fw_tx_stats_ext_size <= offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { softc->pri2cos_valid = false; return rc; } rc = bnxt_hwrm_pri2cos_idx(softc, HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX); if (rc) return rc; if (softc->is_asym_q) { rc = bnxt_hwrm_pri2cos_idx(softc, HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX); if (rc) return rc; } else { memcpy(softc->rx_pri2cos_idx, softc->tx_pri2cos_idx, sizeof(softc->rx_pri2cos_idx)); } u64 *rx_port_stats_ext = (u64 *)softc->hw_rx_port_stats_ext.idi_vaddr; u64 *tx_port_stats_ext = (u64 *)softc->hw_tx_port_stats_ext.idi_vaddr; if (softc->pri2cos_valid) { for (i = 0; i < 8; i++) { long n = bnxt_rx_bytes_pri_arr_base_off[i] + softc->rx_pri2cos_idx[i]; softc->rx_bytes_pri[i] = *(rx_port_stats_ext + n); } for (i = 0; i < 8; i++) { long n = bnxt_rx_pkts_pri_arr_base_off[i] + softc->rx_pri2cos_idx[i]; softc->rx_packets_pri[i] = *(rx_port_stats_ext + n); } for (i = 0; i < 8; i++) { long n = bnxt_tx_bytes_pri_arr_base_off[i] + softc->tx_pri2cos_idx[i]; softc->tx_bytes_pri[i] = *(tx_port_stats_ext + n); } for (i = 0; i < 8; i++) { long n = bnxt_tx_pkts_pri_arr_base_off[i] + softc->tx_pri2cos_idx[i]; softc->tx_packets_pri[i] = *(tx_port_stats_ext + n); } } return rc; } int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic) { struct hwrm_cfa_l2_set_rx_mask_input req = {0}; uint32_t mask = vnic->rx_mask; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_CFA_L2_SET_RX_MASK); req.vnic_id = htole32(vnic->id); req.mask = htole32(mask); req.mc_tbl_addr = htole64(vnic->mc_list.idi_paddr); req.num_mc_entries = htole32(vnic->mc_list_count); return hwrm_send_message(softc, &req, sizeof(req)); } int bnxt_hwrm_l2_filter_free(struct bnxt_softc *softc, uint64_t filter_id) { struct hwrm_cfa_l2_filter_free_input req = {0}; int rc = 0; if (filter_id == -1) return rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_CFA_L2_FILTER_FREE); req.l2_filter_id = htole64(filter_id); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; fail: BNXT_HWRM_UNLOCK(softc); return (rc); } int bnxt_hwrm_free_filter(struct bnxt_softc *softc) { struct bnxt_vnic_info *vnic = &softc->vnic_info; struct bnxt_vlan_tag *tag; int rc = 0; rc = bnxt_hwrm_l2_filter_free(softc, softc->vnic_info.filter_id); if (rc) goto end; SLIST_FOREACH(tag, &vnic->vlan_tags, next) { rc = bnxt_hwrm_l2_filter_free(softc, tag->filter_id); if (rc) goto end; tag->filter_id = -1; } end: return rc; } int bnxt_hwrm_l2_filter_alloc(struct bnxt_softc *softc, uint16_t vlan_tag, uint64_t *filter_id) { struct hwrm_cfa_l2_filter_alloc_input req = {0}; struct hwrm_cfa_l2_filter_alloc_output *resp; struct bnxt_vnic_info *vnic = &softc->vnic_info; uint32_t enables = 0; int rc = 0; if (*filter_id != -1) { device_printf(softc->dev, "Attempt to re-allocate l2 ctx " "filter (fid: 0x%jx)\n", (uintmax_t)*filter_id); return EDOOFUS; } resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_CFA_L2_FILTER_ALLOC); req.flags = htole32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX); enables = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR | HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK | HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID; if (vlan_tag != 0xffff) { enables |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK | HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS; req.l2_ivlan_mask = 0xffff; req.l2_ivlan = vlan_tag; req.num_vlans = 1; } req.enables = htole32(enables); req.dst_id = htole16(vnic->id); memcpy(req.l2_addr, if_getlladdr(iflib_get_ifp(softc->ctx)), ETHER_ADDR_LEN); memset(&req.l2_addr_mask, 0xff, sizeof(req.l2_addr_mask)); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto fail; *filter_id = le64toh(resp->l2_filter_id); fail: BNXT_HWRM_UNLOCK(softc); return (rc); } int bnxt_hwrm_set_filter(struct bnxt_softc *softc) { struct bnxt_vnic_info *vnic = &softc->vnic_info; struct bnxt_vlan_tag *tag; int rc = 0; rc = bnxt_hwrm_l2_filter_alloc(softc, 0xffff, &vnic->filter_id); if (rc) goto end; SLIST_FOREACH(tag, &vnic->vlan_tags, next) { rc = bnxt_hwrm_l2_filter_alloc(softc, tag->tag, &tag->filter_id); if (rc) goto end; } end: return rc; } int bnxt_hwrm_rss_cfg(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic, uint32_t hash_type) { struct hwrm_vnic_rss_cfg_input req = {0}; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_RSS_CFG); req.hash_type = htole32(hash_type); req.ring_grp_tbl_addr = htole64(vnic->rss_grp_tbl.idi_paddr); req.hash_key_tbl_addr = htole64(vnic->rss_hash_key_tbl.idi_paddr); req.rss_ctx_idx = htole16(vnic->rss_id); req.hash_mode_flags = HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT; if (BNXT_CHIP_P5(softc)) { req.vnic_id = htole16(vnic->id); req.ring_table_pair_index = 0x0; } return hwrm_send_message(softc, &req, sizeof(req)); } int bnxt_hwrm_reserve_pf_rings(struct bnxt_softc *softc) { struct hwrm_func_cfg_input req = {0}; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_CFG); req.fid = htole16(0xffff); req.enables |= htole32(HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS); req.enables |= htole32(HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS); req.enables |= htole32(HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS); req.enables |= htole32(HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS); req.enables |= htole32(HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS); req.enables |= htole32(HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX); req.enables |= htole32(HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS); req.num_msix = htole16(BNXT_MAX_NUM_QUEUES); req.num_rsscos_ctxs = htole16(0x8); req.num_cmpl_rings = htole16(BNXT_MAX_NUM_QUEUES * 2); req.num_tx_rings = htole16(BNXT_MAX_NUM_QUEUES); req.num_rx_rings = htole16(BNXT_MAX_NUM_QUEUES); req.num_vnics = htole16(BNXT_MAX_NUM_QUEUES); req.num_stat_ctxs = htole16(BNXT_MAX_NUM_QUEUES * 2); return hwrm_send_message(softc, &req, sizeof(req)); } int bnxt_cfg_async_cr(struct bnxt_softc *softc) { int rc = 0; struct hwrm_func_cfg_input req = {0}; if (!BNXT_PF(softc)) return 0; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_CFG); req.fid = htole16(0xffff); req.enables = htole32(HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR); if (BNXT_CHIP_P5(softc)) req.async_event_cr = htole16(softc->nq_rings[0].ring.phys_id); else req.async_event_cr = htole16(softc->def_cp_ring.ring.phys_id); rc = hwrm_send_message(softc, &req, sizeof(req)); return rc; } void bnxt_validate_hw_lro_settings(struct bnxt_softc *softc) { softc->hw_lro.enable = min(softc->hw_lro.enable, 1); softc->hw_lro.is_mode_gro = min(softc->hw_lro.is_mode_gro, 1); softc->hw_lro.max_agg_segs = min(softc->hw_lro.max_agg_segs, HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX); softc->hw_lro.max_aggs = min(softc->hw_lro.max_aggs, HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX); softc->hw_lro.min_agg_len = min(softc->hw_lro.min_agg_len, BNXT_MAX_MTU); } int bnxt_hwrm_vnic_tpa_cfg(struct bnxt_softc *softc) { struct hwrm_vnic_tpa_cfg_input req = {0}; uint32_t flags; if (softc->vnic_info.id == (uint16_t) HWRM_NA_SIGNATURE) { return 0; } if (!(softc->flags & BNXT_FLAG_TPA)) return 0; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_TPA_CFG); if (softc->hw_lro.enable) { flags = HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA | HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA | HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN | HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ; if (softc->hw_lro.is_mode_gro) flags |= HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO; else flags |= HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE; req.flags = htole32(flags); req.enables = htole32(HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS | HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS | HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN); req.max_agg_segs = htole16(softc->hw_lro.max_agg_segs); req.max_aggs = htole16(softc->hw_lro.max_aggs); req.min_agg_len = htole32(softc->hw_lro.min_agg_len); } req.vnic_id = htole16(softc->vnic_info.id); return hwrm_send_message(softc, &req, sizeof(req)); } int bnxt_hwrm_nvm_find_dir_entry(struct bnxt_softc *softc, uint16_t type, uint16_t *ordinal, uint16_t ext, uint16_t *index, bool use_index, uint8_t search_opt, uint32_t *data_length, uint32_t *item_length, uint32_t *fw_ver) { struct hwrm_nvm_find_dir_entry_input req = {0}; struct hwrm_nvm_find_dir_entry_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc = 0; uint32_t old_timeo; MPASS(ordinal); bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_FIND_DIR_ENTRY); if (use_index) { req.enables = htole32( HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID); req.dir_idx = htole16(*index); } req.dir_type = htole16(type); req.dir_ordinal = htole16(*ordinal); req.dir_ext = htole16(ext); req.opt_ordinal = search_opt; BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; rc = _hwrm_send_message(softc, &req, sizeof(req)); softc->hwrm_cmd_timeo = old_timeo; if (rc) goto exit; if (item_length) *item_length = le32toh(resp->dir_item_length); if (data_length) *data_length = le32toh(resp->dir_data_length); if (fw_ver) *fw_ver = le32toh(resp->fw_ver); *ordinal = le16toh(resp->dir_ordinal); if (index) *index = le16toh(resp->dir_idx); exit: BNXT_HWRM_UNLOCK(softc); return (rc); } int bnxt_hwrm_nvm_read(struct bnxt_softc *softc, uint16_t index, uint32_t offset, uint32_t length, struct iflib_dma_info *data) { struct hwrm_nvm_read_input req = {0}; int rc; uint32_t old_timeo; if (length > data->idi_size) { rc = EINVAL; goto exit; } bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_READ); req.host_dest_addr = htole64(data->idi_paddr); req.dir_idx = htole16(index); req.offset = htole32(offset); req.len = htole32(length); BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; rc = _hwrm_send_message(softc, &req, sizeof(req)); softc->hwrm_cmd_timeo = old_timeo; BNXT_HWRM_UNLOCK(softc); if (rc) goto exit; bus_dmamap_sync(data->idi_tag, data->idi_map, BUS_DMASYNC_POSTREAD); goto exit; exit: return rc; } int bnxt_hwrm_nvm_modify(struct bnxt_softc *softc, uint16_t index, uint32_t offset, void *data, bool cpyin, uint32_t length) { struct hwrm_nvm_modify_input req = {0}; struct iflib_dma_info dma_data; int rc; uint32_t old_timeo; if (length == 0 || !data) return EINVAL; rc = iflib_dma_alloc(softc->ctx, length, &dma_data, BUS_DMA_NOWAIT); if (rc) return ENOMEM; if (cpyin) { rc = copyin(data, dma_data.idi_vaddr, length); if (rc) goto exit; } else memcpy(dma_data.idi_vaddr, data, length); bus_dmamap_sync(dma_data.idi_tag, dma_data.idi_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_MODIFY); req.host_src_addr = htole64(dma_data.idi_paddr); req.dir_idx = htole16(index); req.offset = htole32(offset); req.len = htole32(length); BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; rc = _hwrm_send_message(softc, &req, sizeof(req)); softc->hwrm_cmd_timeo = old_timeo; BNXT_HWRM_UNLOCK(softc); exit: iflib_dma_free(&dma_data); return rc; } int bnxt_hwrm_fw_reset(struct bnxt_softc *softc, uint8_t processor, uint8_t *selfreset) { struct hwrm_fw_reset_input req = {0}; struct hwrm_fw_reset_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; MPASS(selfreset); bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FW_RESET); req.embedded_proc_type = processor; req.selfrst_status = *selfreset; BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto exit; *selfreset = resp->selfrst_status; exit: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_fw_qstatus(struct bnxt_softc *softc, uint8_t type, uint8_t *selfreset) { struct hwrm_fw_qstatus_input req = {0}; struct hwrm_fw_qstatus_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; MPASS(selfreset); bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FW_QSTATUS); req.embedded_proc_type = type; BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto exit; *selfreset = resp->selfrst_status; exit: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_nvm_write(struct bnxt_softc *softc, void *data, bool cpyin, uint16_t type, uint16_t ordinal, uint16_t ext, uint16_t attr, uint16_t option, uint32_t data_length, bool keep, uint32_t *item_length, uint16_t *index) { struct hwrm_nvm_write_input req = {0}; struct hwrm_nvm_write_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; struct iflib_dma_info dma_data; int rc; uint32_t old_timeo; if (data_length) { rc = iflib_dma_alloc(softc->ctx, data_length, &dma_data, BUS_DMA_NOWAIT); if (rc) return ENOMEM; if (cpyin) { rc = copyin(data, dma_data.idi_vaddr, data_length); if (rc) goto early_exit; } else memcpy(dma_data.idi_vaddr, data, data_length); bus_dmamap_sync(dma_data.idi_tag, dma_data.idi_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } else dma_data.idi_paddr = 0; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_WRITE); req.host_src_addr = htole64(dma_data.idi_paddr); req.dir_type = htole16(type); req.dir_ordinal = htole16(ordinal); req.dir_ext = htole16(ext); req.dir_attr = htole16(attr); req.dir_data_length = htole32(data_length); req.option = htole16(option); if (keep) { req.flags = htole16(HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG); } if (item_length) req.dir_item_length = htole32(*item_length); BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; rc = _hwrm_send_message(softc, &req, sizeof(req)); softc->hwrm_cmd_timeo = old_timeo; if (rc) goto exit; if (item_length) *item_length = le32toh(resp->dir_item_length); if (index) *index = le16toh(resp->dir_idx); exit: BNXT_HWRM_UNLOCK(softc); early_exit: if (data_length) iflib_dma_free(&dma_data); return rc; } int bnxt_hwrm_nvm_erase_dir_entry(struct bnxt_softc *softc, uint16_t index) { struct hwrm_nvm_erase_dir_entry_input req = {0}; uint32_t old_timeo; int rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_ERASE_DIR_ENTRY); req.dir_idx = htole16(index); BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; rc = _hwrm_send_message(softc, &req, sizeof(req)); softc->hwrm_cmd_timeo = old_timeo; BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_nvm_get_dir_info(struct bnxt_softc *softc, uint32_t *entries, uint32_t *entry_length) { struct hwrm_nvm_get_dir_info_input req = {0}; struct hwrm_nvm_get_dir_info_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; uint32_t old_timeo; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_GET_DIR_INFO); BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; rc = _hwrm_send_message(softc, &req, sizeof(req)); softc->hwrm_cmd_timeo = old_timeo; if (rc) goto exit; if (entries) *entries = le32toh(resp->entries); if (entry_length) *entry_length = le32toh(resp->entry_length); exit: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_nvm_get_dir_entries(struct bnxt_softc *softc, uint32_t *entries, uint32_t *entry_length, struct iflib_dma_info *dma_data) { struct hwrm_nvm_get_dir_entries_input req = {0}; uint32_t ent; uint32_t ent_len; int rc; uint32_t old_timeo; if (!entries) entries = &ent; if (!entry_length) entry_length = &ent_len; rc = bnxt_hwrm_nvm_get_dir_info(softc, entries, entry_length); if (rc) goto exit; if (*entries * *entry_length > dma_data->idi_size) { rc = EINVAL; goto exit; } /* * TODO: There's a race condition here that could blow up DMA memory... * we need to allocate the max size, not the currently in use * size. The command should totally have a max size here. */ bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_GET_DIR_ENTRIES); req.host_dest_addr = htole64(dma_data->idi_paddr); BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; rc = _hwrm_send_message(softc, &req, sizeof(req)); softc->hwrm_cmd_timeo = old_timeo; BNXT_HWRM_UNLOCK(softc); if (rc) goto exit; bus_dmamap_sync(dma_data->idi_tag, dma_data->idi_map, BUS_DMASYNC_POSTWRITE); exit: return rc; } int bnxt_hwrm_nvm_get_dev_info(struct bnxt_softc *softc, uint16_t *mfg_id, uint16_t *device_id, uint32_t *sector_size, uint32_t *nvram_size, uint32_t *reserved_size, uint32_t *available_size) { struct hwrm_nvm_get_dev_info_input req = {0}; struct hwrm_nvm_get_dev_info_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; uint32_t old_timeo; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_GET_DEV_INFO); BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; rc = _hwrm_send_message(softc, &req, sizeof(req)); softc->hwrm_cmd_timeo = old_timeo; if (rc) goto exit; if (mfg_id) *mfg_id = le16toh(resp->manufacturer_id); if (device_id) *device_id = le16toh(resp->device_id); if (sector_size) *sector_size = le32toh(resp->sector_size); if (nvram_size) *nvram_size = le32toh(resp->nvram_size); if (reserved_size) *reserved_size = le32toh(resp->reserved_size); if (available_size) *available_size = le32toh(resp->available_size); exit: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_nvm_install_update(struct bnxt_softc *softc, uint32_t install_type, uint64_t *installed_items, uint8_t *result, uint8_t *problem_item, uint8_t *reset_required) { struct hwrm_nvm_install_update_input req = {0}; struct hwrm_nvm_install_update_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; uint32_t old_timeo; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_INSTALL_UPDATE); req.install_type = htole32(install_type); BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; rc = _hwrm_send_message(softc, &req, sizeof(req)); softc->hwrm_cmd_timeo = old_timeo; if (rc) goto exit; if (installed_items) *installed_items = le32toh(resp->installed_items); if (result) *result = resp->result; if (problem_item) *problem_item = resp->problem_item; if (reset_required) *reset_required = resp->reset_required; exit: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_nvm_verify_update(struct bnxt_softc *softc, uint16_t type, uint16_t ordinal, uint16_t ext) { struct hwrm_nvm_verify_update_input req = {0}; uint32_t old_timeo; int rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_VERIFY_UPDATE); req.dir_type = htole16(type); req.dir_ordinal = htole16(ordinal); req.dir_ext = htole16(ext); BNXT_HWRM_LOCK(softc); old_timeo = softc->hwrm_cmd_timeo; softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; rc = _hwrm_send_message(softc, &req, sizeof(req)); softc->hwrm_cmd_timeo = old_timeo; BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_fw_get_time(struct bnxt_softc *softc, uint16_t *year, uint8_t *month, uint8_t *day, uint8_t *hour, uint8_t *minute, uint8_t *second, uint16_t *millisecond, uint16_t *zone) { struct hwrm_fw_get_time_input req = {0}; struct hwrm_fw_get_time_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FW_GET_TIME); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto exit; if (year) *year = le16toh(resp->year); if (month) *month = resp->month; if (day) *day = resp->day; if (hour) *hour = resp->hour; if (minute) *minute = resp->minute; if (second) *second = resp->second; if (millisecond) *millisecond = le16toh(resp->millisecond); if (zone) *zone = le16toh(resp->zone); exit: BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_fw_set_time(struct bnxt_softc *softc, uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second, uint16_t millisecond, uint16_t zone) { struct hwrm_fw_set_time_input req = {0}; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FW_SET_TIME); req.year = htole16(year); req.month = month; req.day = day; req.hour = hour; req.minute = minute; req.second = second; req.millisecond = htole16(millisecond); req.zone = htole16(zone); return hwrm_send_message(softc, &req, sizeof(req)); } int bnxt_read_sfp_module_eeprom_info(struct bnxt_softc *softc, uint16_t i2c_addr, uint16_t page_number, uint8_t bank,bool bank_sel_en, uint16_t start_addr, uint16_t data_length, uint8_t *buf) { struct hwrm_port_phy_i2c_read_output *output = (void *)softc->hwrm_cmd_resp.idi_vaddr; struct hwrm_port_phy_i2c_read_input req = {0}; int rc = 0, byte_offset = 0; BNXT_HWRM_LOCK(softc); bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_PORT_PHY_I2C_READ); req.i2c_slave_addr = i2c_addr; req.page_number = htole16(page_number); req.port_id = htole16(softc->pf.port_id); do { uint16_t xfer_size; xfer_size = min_t(uint16_t, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); data_length -= xfer_size; req.page_offset = htole16(start_addr + byte_offset); req.data_length = xfer_size; req.bank_number = bank; req.enables = htole32((start_addr + byte_offset ? HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET : 0) | (bank_sel_en ? HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_BANK_NUMBER : 0)); rc = hwrm_send_message(softc, &req, sizeof(req)); if (!rc) memcpy(buf + byte_offset, output->data, xfer_size); byte_offset += xfer_size; } while (!rc && data_length > 0); BNXT_HWRM_UNLOCK(softc); return rc; } int bnxt_hwrm_port_phy_qcfg(struct bnxt_softc *softc) { struct bnxt_link_info *link_info = &softc->link_info; struct hwrm_port_phy_qcfg_input req = {0}; struct hwrm_port_phy_qcfg_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc = 0; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_PORT_PHY_QCFG); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto exit; memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); link_info->phy_link_status = resp->link; link_info->duplex = resp->duplex_cfg; link_info->auto_mode = resp->auto_mode; /* * When AUTO_PAUSE_AUTONEG_PAUSE bit is set to 1, * the advertisement of pause is enabled. * 1. When the auto_mode is not set to none and this flag is set to 1, * then the auto_pause bits on this port are being advertised and * autoneg pause results are being interpreted. * 2. When the auto_mode is not set to none and this flag is set to 0, * the pause is forced as indicated in force_pause, and also * advertised as auto_pause bits, but the autoneg results are not * interpreted since the pause configuration is being forced. * 3. When the auto_mode is set to none and this flag is set to 1, * auto_pause bits should be ignored and should be set to 0. */ link_info->flow_ctrl.autoneg = false; link_info->flow_ctrl.tx = false; link_info->flow_ctrl.rx = false; if ((resp->auto_mode) && (resp->auto_pause & BNXT_AUTO_PAUSE_AUTONEG_PAUSE)) { link_info->flow_ctrl.autoneg = true; } if (link_info->flow_ctrl.autoneg) { if (resp->auto_pause & BNXT_PAUSE_TX) link_info->flow_ctrl.tx = true; if (resp->auto_pause & BNXT_PAUSE_RX) link_info->flow_ctrl.rx = true; } else { if (resp->force_pause & BNXT_PAUSE_TX) link_info->flow_ctrl.tx = true; if (resp->force_pause & BNXT_PAUSE_RX) link_info->flow_ctrl.rx = true; } link_info->duplex_setting = resp->duplex_cfg; if (link_info->phy_link_status == HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) link_info->link_speed = le16toh(resp->link_speed); else link_info->link_speed = 0; link_info->force_link_speed = le16toh(resp->force_link_speed); link_info->auto_link_speeds = le16toh(resp->auto_link_speed); link_info->support_speeds = le16toh(resp->support_speeds); link_info->auto_link_speeds = le16toh(resp->auto_link_speed_mask); link_info->preemphasis = le32toh(resp->preemphasis); link_info->phy_ver[0] = resp->phy_maj; link_info->phy_ver[1] = resp->phy_min; link_info->phy_ver[2] = resp->phy_bld; snprintf(softc->ver_info->phy_ver, sizeof(softc->ver_info->phy_ver), "%d.%d.%d", link_info->phy_ver[0], link_info->phy_ver[1], link_info->phy_ver[2]); strlcpy(softc->ver_info->phy_vendor, resp->phy_vendor_name, BNXT_NAME_SIZE); strlcpy(softc->ver_info->phy_partnumber, resp->phy_vendor_partnumber, BNXT_NAME_SIZE); link_info->media_type = resp->media_type; link_info->phy_type = resp->phy_type; link_info->transceiver = resp->xcvr_pkg_type; link_info->phy_addr = resp->eee_config_phy_addr & HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK; link_info->module_status = resp->module_status; link_info->support_pam4_speeds = le16toh(resp->support_pam4_speeds); link_info->auto_pam4_link_speeds = le16toh(resp->auto_pam4_link_speed_mask); link_info->force_pam4_link_speed = le16toh(resp->force_pam4_link_speed); if (softc->hwrm_spec_code >= 0x10504) link_info->active_fec_sig_mode = resp->active_fec_signal_mode; exit: BNXT_HWRM_UNLOCK(softc); return rc; } static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp) { if (!resp->supported_speeds_auto_mode && !resp->supported_speeds_force_mode && !resp->supported_pam4_speeds_auto_mode && !resp->supported_pam4_speeds_force_mode) return true; return false; } int bnxt_hwrm_phy_qcaps(struct bnxt_softc *softc) { struct bnxt_link_info *link_info = &softc->link_info; struct hwrm_port_phy_qcaps_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; struct hwrm_port_phy_qcaps_input req = {}; int rc; if (softc->hwrm_spec_code < 0x10201) return 0; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_PORT_PHY_QCAPS); BNXT_HWRM_LOCK(softc); rc = _hwrm_send_message(softc, &req, sizeof(req)); if (rc) goto exit; softc->phy_flags = resp->flags | (resp->flags2 << 8); if (resp->flags & HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED) { softc->lpi_tmr_lo = le32toh(resp->tx_lpi_timer_low) & HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK; softc->lpi_tmr_hi = le32toh(resp->valid_tx_lpi_timer_high) & HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK; } if (softc->hwrm_spec_code >= 0x10a01) { if (bnxt_phy_qcaps_no_speed(resp)) { link_info->phy_state = BNXT_PHY_STATE_DISABLED; device_printf(softc->dev, "Ethernet link disabled\n"); } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) { link_info->phy_state = BNXT_PHY_STATE_ENABLED; device_printf(softc->dev, "Ethernet link enabled\n"); /* Phy re-enabled, reprobe the speeds */ link_info->support_auto_speeds = 0; link_info->support_pam4_auto_speeds = 0; } } if (resp->supported_speeds_auto_mode) link_info->support_auto_speeds = le16toh(resp->supported_speeds_auto_mode); if (resp->supported_speeds_force_mode) link_info->support_force_speeds = le16toh(resp->supported_speeds_force_mode); if (resp->supported_pam4_speeds_auto_mode) link_info->support_pam4_auto_speeds = le16toh(resp->supported_pam4_speeds_auto_mode); if (resp->supported_pam4_speeds_force_mode) link_info->support_pam4_force_speeds = le16toh(resp->supported_pam4_speeds_force_mode); exit: BNXT_HWRM_UNLOCK(softc); return rc; } uint16_t bnxt_hwrm_get_wol_fltrs(struct bnxt_softc *softc, uint16_t handle) { struct hwrm_wol_filter_qcfg_input req = {0}; struct hwrm_wol_filter_qcfg_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; uint16_t next_handle = 0; int rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_WOL_FILTER_QCFG); req.port_id = htole16(softc->pf.port_id); req.handle = htole16(handle); rc = hwrm_send_message(softc, &req, sizeof(req)); if (!rc) { next_handle = le16toh(resp->next_handle); if (next_handle != 0) { if (resp->wol_type == HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_MAGICPKT) { softc->wol = 1; softc->wol_filter_id = resp->wol_filter_id; } } } return next_handle; } int bnxt_hwrm_alloc_wol_fltr(struct bnxt_softc *softc) { struct hwrm_wol_filter_alloc_input req = {0}; struct hwrm_wol_filter_alloc_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_WOL_FILTER_ALLOC); req.port_id = htole16(softc->pf.port_id); req.wol_type = HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_MAGICPKT; req.enables = htole32(HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_MAC_ADDRESS); memcpy(req.mac_address, softc->func.mac_addr, ETHER_ADDR_LEN); rc = hwrm_send_message(softc, &req, sizeof(req)); if (!rc) softc->wol_filter_id = resp->wol_filter_id; return rc; } int bnxt_hwrm_free_wol_fltr(struct bnxt_softc *softc) { struct hwrm_wol_filter_free_input req = {0}; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_WOL_FILTER_FREE); req.port_id = htole16(softc->pf.port_id); req.enables = htole32(HWRM_WOL_FILTER_FREE_INPUT_ENABLES_WOL_FILTER_ID); req.wol_filter_id = softc->wol_filter_id; return hwrm_send_message(softc, &req, sizeof(req)); } static void bnxt_hwrm_set_coal_params(struct bnxt_softc *softc, uint32_t max_frames, uint32_t buf_tmrs, uint16_t flags, struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) { req->flags = htole16(flags); req->num_cmpl_dma_aggr = htole16((uint16_t)max_frames); req->num_cmpl_dma_aggr_during_int = htole16(max_frames >> 16); req->cmpl_aggr_dma_tmr = htole16((uint16_t)buf_tmrs); req->cmpl_aggr_dma_tmr_during_int = htole16(buf_tmrs >> 16); /* Minimum time between 2 interrupts set to buf_tmr x 2 */ req->int_lat_tmr_min = htole16((uint16_t)buf_tmrs * 2); req->int_lat_tmr_max = htole16((uint16_t)buf_tmrs * 4); req->num_cmpl_aggr_int = htole16((uint16_t)max_frames * 4); } int bnxt_hwrm_set_coal(struct bnxt_softc *softc) { int i, rc = 0; struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, req_tx = {0}, *req; uint16_t max_buf, max_buf_irq; uint16_t buf_tmr, buf_tmr_irq; uint32_t flags; bnxt_hwrm_cmd_hdr_init(softc, &req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS); bnxt_hwrm_cmd_hdr_init(softc, &req_tx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS); /* Each rx completion (2 records) should be DMAed immediately. * DMA 1/4 of the completion buffers at a time. */ max_buf = min_t(uint16_t, softc->rx_coal_frames / 4, 2); /* max_buf must not be zero */ max_buf = clamp_t(uint16_t, max_buf, 1, 63); max_buf_irq = clamp_t(uint16_t, softc->rx_coal_frames_irq, 1, 63); buf_tmr = BNXT_USEC_TO_COAL_TIMER(softc->rx_coal_usecs); /* buf timer set to 1/4 of interrupt timer */ buf_tmr = max_t(uint16_t, buf_tmr / 4, 1); buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(softc->rx_coal_usecs_irq); buf_tmr_irq = max_t(uint16_t, buf_tmr_irq, 1); flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET; /* RING_IDLE generates more IRQs for lower latency. Enable it only * if coal_usecs is less than 25 us. */ if (softc->rx_coal_usecs < 25) flags |= HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE; bnxt_hwrm_set_coal_params(softc, max_buf_irq << 16 | max_buf, buf_tmr_irq << 16 | buf_tmr, flags, &req_rx); /* max_buf must not be zero */ max_buf = clamp_t(uint16_t, softc->tx_coal_frames, 1, 63); max_buf_irq = clamp_t(uint16_t, softc->tx_coal_frames_irq, 1, 63); buf_tmr = BNXT_USEC_TO_COAL_TIMER(softc->tx_coal_usecs); /* buf timer set to 1/4 of interrupt timer */ buf_tmr = max_t(uint16_t, buf_tmr / 4, 1); buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(softc->tx_coal_usecs_irq); buf_tmr_irq = max_t(uint16_t, buf_tmr_irq, 1); flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET; bnxt_hwrm_set_coal_params(softc, max_buf_irq << 16 | max_buf, buf_tmr_irq << 16 | buf_tmr, flags, &req_tx); for (i = 0; i < softc->nrxqsets; i++) { req = &req_rx; req->ring_id = htole16(softc->grp_info[i].cp_ring_id); rc = hwrm_send_message(softc, req, sizeof(*req)); if (rc) break; } return rc; } -int bnxt_hwrm_func_rgtr_async_events(struct bnxt_softc *softc, unsigned long *bmap, - int bmap_size) -{ - struct hwrm_func_drv_rgtr_input req = {0}; - struct hwrm_func_drv_rgtr_output *resp = - (void *)softc->hwrm_cmd_resp.idi_vaddr; - bitstr_t *async_events_bmap; - uint32_t *events; - int i, rc = 0; - -#define BNXT_MAX_NUM_ASYNC_EVENTS 256 - async_events_bmap = bit_alloc(BNXT_MAX_NUM_ASYNC_EVENTS, M_DEVBUF, - M_WAITOK|M_ZERO); - events = (uint32_t *)async_events_bmap; - - bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_DRV_RGTR); - - req.enables = - htole32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD); - - memset(async_events_bmap, 0, sizeof(BNXT_MAX_NUM_ASYNC_EVENTS / 8)); - - bit_set(async_events_bmap, HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE); - bit_set(async_events_bmap, HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD); - bit_set(async_events_bmap, HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED); - bit_set(async_events_bmap, HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE); - bit_set(async_events_bmap, HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE); - - if (bmap && bmap_size) { - for (i = 0; i < bmap_size; i++) { - if (bit_test(bmap, i)) - bit_set(async_events_bmap, i); - } - } - - for (i = 0; i < 8; i++) - req.async_event_fwd[i] |= htole32(events[i]); - - free(async_events_bmap, M_DEVBUF); - - rc = hwrm_send_message(softc, &req, sizeof(req)); - if (!rc) { - if (resp->flags & - le32toh(HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)) - softc->fw_cap |= BNXT_FW_CAP_IF_CHANGE; - } - - return rc; -} - void bnxt_hwrm_ring_info_get(struct bnxt_softc *softc, uint8_t ring_type, uint32_t ring_id, uint32_t *prod, uint32_t *cons) { hwrm_dbg_ring_info_get_input_t req = {0}; hwrm_dbg_ring_info_get_output_t *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; int rc = 0; *prod = *cons = 0xffffffff; bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_DBG_RING_INFO_GET); req.ring_type = le32toh(ring_type); req.fw_ring_id = le32toh(ring_id); rc = hwrm_send_message(softc, &req, sizeof(req)); if (!rc) { *prod = resp->producer_index; *cons = resp->consumer_index; } return; } diff --git a/sys/dev/bnxt/bnxt_en/bnxt_hwrm.h b/sys/dev/bnxt/bnxt_en/bnxt_hwrm.h index 766556f9904c..126cad977c82 100644 --- a/sys/dev/bnxt/bnxt_en/bnxt_hwrm.h +++ b/sys/dev/bnxt/bnxt_en/bnxt_hwrm.h @@ -1,142 +1,144 @@ /*- * Broadcom NetXtreme-C/E network driver. * * Copyright (c) 2016 Broadcom, All Rights Reserved. * The term Broadcom refers to Broadcom Limited and/or its subsidiaries * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include #ifndef _BNXT_HWRM_H #define _BNXT_HWRM_H #define BNXT_PAUSE_TX (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX) #define BNXT_PAUSE_RX (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX) -#define BNXT_AUTO_PAUSE_AUTONEG_PAUSE \ - (HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE) +#define BNXT_AUTO_PAUSE_AUTONEG_PAUSE \ + (HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE) #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 +#define SHORT_HWRM_CMD_TIMEOUT 500 /* HWRM Function Prototypes */ int hwrm_send_message(struct bnxt_softc *softc, void *msg, uint32_t msg_len); int bnxt_alloc_hwrm_dma_mem(struct bnxt_softc *softc); void bnxt_free_hwrm_dma_mem(struct bnxt_softc *softc); int bnxt_hwrm_ring_alloc(struct bnxt_softc *softc, uint8_t type, struct bnxt_ring *ring); int bnxt_hwrm_ring_free(struct bnxt_softc *softc, uint32_t type, struct bnxt_ring *ring, int cmpl_ring_id); int bnxt_hwrm_ver_get(struct bnxt_softc *softc); int bnxt_hwrm_queue_qportcfg(struct bnxt_softc *softc, uint32_t path_dir); -int bnxt_hwrm_func_drv_rgtr(struct bnxt_softc *softc); +int bnxt_hwrm_func_drv_rgtr(struct bnxt_softc *bp, unsigned long *bmap, int bmap_size, + bool async_only); int bnxt_hwrm_func_drv_unrgtr(struct bnxt_softc *softc, bool shutdown); int bnxt_hwrm_func_qcaps(struct bnxt_softc *softc); int bnxt_hwrm_func_qcfg(struct bnxt_softc *softc); int bnxt_hwrm_func_reset(struct bnxt_softc *softc); int bnxt_hwrm_set_link_setting(struct bnxt_softc *softc, bool set_pause, bool set_eee, bool set_link); int bnxt_hwrm_set_pause(struct bnxt_softc *softc); int bnxt_hwrm_vnic_ctx_alloc(struct bnxt_softc *softc, uint16_t *ctx_id); int bnxt_hwrm_vnic_ctx_free(struct bnxt_softc *softc, uint16_t ctx_id); int bnxt_hwrm_vnic_set_hds(struct bnxt_softc *sc, struct bnxt_vnic_info *vnic); int bnxt_hwrm_vnic_cfg(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic); int bnxt_hwrm_vnic_alloc(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic); int bnxt_hwrm_vnic_free(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic); int bnxt_hwrm_stat_ctx_alloc(struct bnxt_softc *softc, struct bnxt_cp_ring *cpr, uint64_t paddr); int bnxt_hwrm_stat_ctx_free(struct bnxt_softc *softc, struct bnxt_cp_ring *cpr); int bnxt_hwrm_port_qstats(struct bnxt_softc *softc); int bnxt_hwrm_port_qstats_ext(struct bnxt_softc *softc); int bnxt_hwrm_ring_grp_alloc(struct bnxt_softc *softc, struct bnxt_grp_info *grp); int bnxt_hwrm_ring_grp_free(struct bnxt_softc *softc, struct bnxt_grp_info *gr); int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic); int bnxt_hwrm_set_filter(struct bnxt_softc *softc); int bnxt_hwrm_free_filter(struct bnxt_softc *softc); int bnxt_hwrm_l2_filter_alloc(struct bnxt_softc *softc, uint16_t vlan_tag, uint64_t *filter_id); int bnxt_hwrm_l2_filter_free(struct bnxt_softc *softc, uint64_t filter_id); int bnxt_hwrm_rss_cfg(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic, uint32_t hash_type); int bnxt_cfg_async_cr(struct bnxt_softc *softc); int bnxt_hwrm_vnic_tpa_cfg(struct bnxt_softc *softc); void bnxt_validate_hw_lro_settings(struct bnxt_softc *softc); int bnxt_hwrm_nvm_find_dir_entry(struct bnxt_softc *softc, uint16_t type, uint16_t *ordinal, uint16_t ext, uint16_t *index, bool use_index, uint8_t search_opt, uint32_t *data_length, uint32_t *item_length, uint32_t *fw_ver); int bnxt_hwrm_nvm_read(struct bnxt_softc *softc, uint16_t index, uint32_t offset, uint32_t length, struct iflib_dma_info *data); int bnxt_hwrm_nvm_modify(struct bnxt_softc *softc, uint16_t index, uint32_t offset, void *data, bool cpyin, uint32_t length); int bnxt_hwrm_fw_reset(struct bnxt_softc *softc, uint8_t processor, uint8_t *selfreset); int bnxt_hwrm_fw_qstatus(struct bnxt_softc *softc, uint8_t type, uint8_t *selfreset); int bnxt_hwrm_nvm_write(struct bnxt_softc *softc, void *data, bool cpyin, uint16_t type, uint16_t ordinal, uint16_t ext, uint16_t attr, uint16_t option, uint32_t data_length, bool keep, uint32_t *item_length, uint16_t *index); int bnxt_hwrm_nvm_erase_dir_entry(struct bnxt_softc *softc, uint16_t index); int bnxt_hwrm_nvm_get_dir_info(struct bnxt_softc *softc, uint32_t *entries, uint32_t *entry_length); int bnxt_hwrm_nvm_get_dir_entries(struct bnxt_softc *softc, uint32_t *entries, uint32_t *entry_length, struct iflib_dma_info *dma_data); int bnxt_hwrm_nvm_get_dev_info(struct bnxt_softc *softc, uint16_t *mfg_id, uint16_t *device_id, uint32_t *sector_size, uint32_t *nvram_size, uint32_t *reserved_size, uint32_t *available_size); int bnxt_hwrm_nvm_install_update(struct bnxt_softc *softc, uint32_t install_type, uint64_t *installed_items, uint8_t *result, uint8_t *problem_item, uint8_t *reset_required); int bnxt_hwrm_nvm_verify_update(struct bnxt_softc *softc, uint16_t type, uint16_t ordinal, uint16_t ext); int bnxt_hwrm_fw_get_time(struct bnxt_softc *softc, uint16_t *year, uint8_t *month, uint8_t *day, uint8_t *hour, uint8_t *minute, uint8_t *second, uint16_t *millisecond, uint16_t *zone); int bnxt_hwrm_fw_set_time(struct bnxt_softc *softc, uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second, uint16_t millisecond, uint16_t zone); int bnxt_hwrm_port_phy_qcfg(struct bnxt_softc *softc); int bnxt_hwrm_phy_qcaps(struct bnxt_softc *softc); uint16_t bnxt_hwrm_get_wol_fltrs(struct bnxt_softc *softc, uint16_t handle); int bnxt_hwrm_alloc_wol_fltr(struct bnxt_softc *softc); int bnxt_hwrm_free_wol_fltr(struct bnxt_softc *softc); int bnxt_hwrm_set_coal(struct bnxt_softc *softc); int bnxt_hwrm_func_rgtr_async_events(struct bnxt_softc *softc, unsigned long *bmap, int bmap_size); int bnxt_hwrm_func_backing_store_qcaps(struct bnxt_softc *softc); int bnxt_hwrm_func_backing_store_cfg(struct bnxt_softc *softc, uint32_t); int bnxt_hwrm_func_backing_store_cfg_v2(struct bnxt_softc *softc, struct bnxt_ctx_mem_type *ctxm, bool last); int bnxt_hwrm_func_resc_qcaps(struct bnxt_softc *softc, bool all); int bnxt_hwrm_reserve_pf_rings (struct bnxt_softc *softc); void bnxt_hwrm_ring_info_get(struct bnxt_softc *softc, uint8_t ring_type, uint32_t ring_id, uint32_t *prod, uint32_t *); int bnxt_hwrm_passthrough(struct bnxt_softc *softc, void *req, uint32_t req_len, void *resp, uint32_t resp_len, uint32_t timeout); int _hwrm_send_message(struct bnxt_softc *, void *, uint32_t); int hwrm_send_message(struct bnxt_softc *, void *, uint32_t); void bnxt_hwrm_cmd_hdr_init(struct bnxt_softc *, void *, uint16_t); #endif diff --git a/sys/dev/bnxt/bnxt_en/bnxt_sysctl.c b/sys/dev/bnxt/bnxt_en/bnxt_sysctl.c index fdc54ab34511..012903ce21b3 100644 --- a/sys/dev/bnxt/bnxt_en/bnxt_sysctl.c +++ b/sys/dev/bnxt/bnxt_en/bnxt_sysctl.c @@ -1,2114 +1,2164 @@ /*- * Broadcom NetXtreme-C/E network driver. * * Copyright (c) 2016 Broadcom, All Rights Reserved. * The term Broadcom refers to Broadcom Limited and/or its subsidiaries * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include +#include #include "bnxt.h" #include "bnxt_hwrm.h" #include "bnxt_sysctl.h" +DEFINE_MUTEX(tmp_mutex); /* mutex lock for driver */ +extern void bnxt_fw_reset(struct bnxt_softc *bp); +extern void bnxt_queue_sp_work(struct bnxt_softc *bp); +extern void +process_nq(struct bnxt_softc *softc, uint16_t nqid); /* * We want to create: * dev.bnxt.0.hwstats.txq0 * dev.bnxt.0.hwstats.txq0.txmbufs * dev.bnxt.0.hwstats.rxq0 * dev.bnxt.0.hwstats.txq0.rxmbufs * so the hwstats ctx list needs to be created in attach_post and populated * during init. * * Then, it needs to be cleaned up in stop. */ int bnxt_init_sysctl_ctx(struct bnxt_softc *softc) { struct sysctl_ctx_list *ctx; sysctl_ctx_init(&softc->hw_stats); ctx = device_get_sysctl_ctx(softc->dev); softc->hw_stats_oid = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev)), OID_AUTO, "hwstats", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "hardware statistics"); if (!softc->hw_stats_oid) { sysctl_ctx_free(&softc->hw_stats); return ENOMEM; } sysctl_ctx_init(&softc->ver_info->ver_ctx); ctx = device_get_sysctl_ctx(softc->dev); softc->ver_info->ver_oid = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev)), OID_AUTO, "ver", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "hardware/firmware version information"); if (!softc->ver_info->ver_oid) { sysctl_ctx_free(&softc->ver_info->ver_ctx); return ENOMEM; } if (BNXT_PF(softc)) { sysctl_ctx_init(&softc->nvm_info->nvm_ctx); ctx = device_get_sysctl_ctx(softc->dev); softc->nvm_info->nvm_oid = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev)), OID_AUTO, "nvram", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "nvram information"); if (!softc->nvm_info->nvm_oid) { sysctl_ctx_free(&softc->nvm_info->nvm_ctx); return ENOMEM; } } sysctl_ctx_init(&softc->hw_lro_ctx); ctx = device_get_sysctl_ctx(softc->dev); softc->hw_lro_oid = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev)), OID_AUTO, "hw_lro", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "hardware lro"); if (!softc->hw_lro_oid) { sysctl_ctx_free(&softc->hw_lro_ctx); return ENOMEM; } sysctl_ctx_init(&softc->flow_ctrl_ctx); ctx = device_get_sysctl_ctx(softc->dev); softc->flow_ctrl_oid = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev)), OID_AUTO, "fc", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "flow ctrl"); if (!softc->flow_ctrl_oid) { sysctl_ctx_free(&softc->flow_ctrl_ctx); return ENOMEM; } sysctl_ctx_init(&softc->dcb_ctx); ctx = device_get_sysctl_ctx(softc->dev); softc->dcb_oid = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev)), OID_AUTO, "dcb", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "dcb"); if (!softc->dcb_oid) { sysctl_ctx_free(&softc->dcb_ctx); return ENOMEM; } return 0; } int bnxt_free_sysctl_ctx(struct bnxt_softc *softc) { int orc; int rc = 0; if (softc->hw_stats_oid != NULL) { orc = sysctl_ctx_free(&softc->hw_stats); if (orc) rc = orc; else softc->hw_stats_oid = NULL; } if (softc->ver_info->ver_oid != NULL) { orc = sysctl_ctx_free(&softc->ver_info->ver_ctx); if (orc) rc = orc; else softc->ver_info->ver_oid = NULL; } if (BNXT_PF(softc) && softc->nvm_info->nvm_oid != NULL) { orc = sysctl_ctx_free(&softc->nvm_info->nvm_ctx); if (orc) rc = orc; else softc->nvm_info->nvm_oid = NULL; } if (softc->hw_lro_oid != NULL) { orc = sysctl_ctx_free(&softc->hw_lro_ctx); if (orc) rc = orc; else softc->hw_lro_oid = NULL; } if (softc->flow_ctrl_oid != NULL) { orc = sysctl_ctx_free(&softc->flow_ctrl_ctx); if (orc) rc = orc; else softc->flow_ctrl_oid = NULL; } if (softc->dcb_oid != NULL) { orc = sysctl_ctx_free(&softc->dcb_ctx); if (orc) rc = orc; else softc->dcb_oid = NULL; } return rc; } int bnxt_create_tx_sysctls(struct bnxt_softc *softc, int txr) { struct sysctl_oid *oid; struct ctx_hw_stats *tx_stats = (void *)softc->tx_stats[txr].idi_vaddr; char name[32]; char desc[64]; sprintf(name, "txq%d", txr); sprintf(desc, "transmit queue %d", txr); oid = SYSCTL_ADD_NODE(&softc->hw_stats, SYSCTL_CHILDREN(softc->hw_stats_oid), OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, desc); if (!oid) return ENOMEM; SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "ucast_pkts", CTLFLAG_RD, &tx_stats->tx_ucast_pkts, "unicast packets sent"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "mcast_pkts", CTLFLAG_RD, &tx_stats->tx_mcast_pkts, "multicast packets sent"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "bcast_pkts", CTLFLAG_RD, &tx_stats->tx_bcast_pkts, "broadcast packets sent"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "discard_pkts", CTLFLAG_RD, &tx_stats->tx_discard_pkts, "discarded transmit packets"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "error_pkts", CTLFLAG_RD, &tx_stats->tx_error_pkts, "Error transmit packets"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "ucast_bytes", CTLFLAG_RD, &tx_stats->tx_ucast_bytes, "unicast bytes sent"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "mcast_bytes", CTLFLAG_RD, &tx_stats->tx_mcast_bytes, "multicast bytes sent"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "bcast_bytes", CTLFLAG_RD, &tx_stats->tx_bcast_bytes, "broadcast bytes sent"); return 0; } int bnxt_create_port_stats_sysctls(struct bnxt_softc *softc) { struct sysctl_oid *oid; char name[32]; char desc[64]; sprintf(name, "port_stats"); sprintf(desc, "Port Stats"); oid = SYSCTL_ADD_NODE(&softc->hw_stats, SYSCTL_CHILDREN(softc->hw_stats_oid), OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, desc); if (!oid) return ENOMEM; SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_64b_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_64b_frames, "Transmitted 64b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_65b_127b_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_65b_127b_frames, "Transmitted 65b 127b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_128b_255b_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_128b_255b_frames, "Transmitted 128b 255b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_256b_511b_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_256b_511b_frames, "Transmitted 256b 511b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_512b_1023b_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_512b_1023b_frames, "Transmitted 512b 1023b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_1024b_1518b_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_1024b_1518b_frames, "Transmitted 1024b 1518b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_good_vlan_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_good_vlan_frames, "Transmitted good vlan frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_1519b_2047b_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_1519b_2047b_frames, "Transmitted 1519b 2047b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_2048b_4095b_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_2048b_4095b_frames, "Transmitted 2048b 4095b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_4096b_9216b_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_4096b_9216b_frames, "Transmitted 4096b 9216b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_9217b_16383b_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_9217b_16383b_frames, "Transmitted 9217b 16383b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_good_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_good_frames, "Transmitted good frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_total_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_total_frames, "Transmitted total frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_ucast_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_ucast_frames, "Transmitted ucast frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_mcast_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_mcast_frames, "Transmitted mcast frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bcast_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_bcast_frames, "Transmitted bcast frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_pause_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_pause_frames, "Transmitted pause frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_pfc_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_pfc_frames, "Transmitted pfc frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_jabber_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_jabber_frames, "Transmitted jabber frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_fcs_err_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_fcs_err_frames, "Transmitted fcs err frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_err", CTLFLAG_RD, &softc->tx_port_stats->tx_err, "Transmitted err"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_fifo_underruns", CTLFLAG_RD, &softc->tx_port_stats->tx_fifo_underruns, "Transmitted fifo underruns"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_pfc_ena_frames_pri0", CTLFLAG_RD, &softc->tx_port_stats->tx_pfc_ena_frames_pri0, "Transmitted pfc ena frames pri0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_pfc_ena_frames_pri1", CTLFLAG_RD, &softc->tx_port_stats->tx_pfc_ena_frames_pri1, "Transmitted pfc ena frames pri1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_pfc_ena_frames_pri2", CTLFLAG_RD, &softc->tx_port_stats->tx_pfc_ena_frames_pri2, "Transmitted pfc ena frames pri2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_pfc_ena_frames_pri3", CTLFLAG_RD, &softc->tx_port_stats->tx_pfc_ena_frames_pri3, "Transmitted pfc ena frames pri3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_pfc_ena_frames_pri4", CTLFLAG_RD, &softc->tx_port_stats->tx_pfc_ena_frames_pri4, "Transmitted pfc ena frames pri4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_pfc_ena_frames_pri5", CTLFLAG_RD, &softc->tx_port_stats->tx_pfc_ena_frames_pri5, "Transmitted pfc ena frames pri5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_pfc_ena_frames_pri6", CTLFLAG_RD, &softc->tx_port_stats->tx_pfc_ena_frames_pri6, "Transmitted pfc ena frames pri6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_pfc_ena_frames_pri7", CTLFLAG_RD, &softc->tx_port_stats->tx_pfc_ena_frames_pri7, "Transmitted pfc ena frames pri7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_eee_lpi_events", CTLFLAG_RD, &softc->tx_port_stats->tx_eee_lpi_events, "Transmitted eee lpi events"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_eee_lpi_duration", CTLFLAG_RD, &softc->tx_port_stats->tx_eee_lpi_duration, "Transmitted eee lpi duration"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_llfc_logical_msgs", CTLFLAG_RD, &softc->tx_port_stats->tx_llfc_logical_msgs, "Transmitted llfc logical msgs"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_hcfc_msgs", CTLFLAG_RD, &softc->tx_port_stats->tx_hcfc_msgs, "Transmitted hcfc msgs"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_total_collisions", CTLFLAG_RD, &softc->tx_port_stats->tx_total_collisions, "Transmitted total collisions"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes", CTLFLAG_RD, &softc->tx_port_stats->tx_bytes, "Transmitted bytes"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_xthol_frames", CTLFLAG_RD, &softc->tx_port_stats->tx_xthol_frames, "Transmitted xthol frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_stat_discard", CTLFLAG_RD, &softc->tx_port_stats->tx_stat_discard, "Transmitted stat discard"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_stat_error", CTLFLAG_RD, &softc->tx_port_stats->tx_stat_error, "Transmitted stat error"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_64b_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_64b_frames, "Received 64b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_65b_127b_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_65b_127b_frames, "Received 65b 127b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_128b_255b_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_128b_255b_frames, "Received 128b 255b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_256b_511b_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_256b_511b_frames, "Received 256b 511b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_512b_1023b_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_512b_1023b_frames, "Received 512b 1023b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_1024b_1518b_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_1024b_1518b_frames, "Received 1024b 1518 frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_good_vlan_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_good_vlan_frames, "Received good vlan frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_1519b_2047b_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_1519b_2047b_frames, "Received 1519b 2047b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_2048b_4095b_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_2048b_4095b_frames, "Received 2048b 4095b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_4096b_9216b_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_4096b_9216b_frames, "Received 4096b 9216b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_9217b_16383b_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_9217b_16383b_frames, "Received 9217b 16383b frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_total_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_total_frames, "Received total frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_ucast_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_ucast_frames, "Received ucast frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_mcast_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_mcast_frames, "Received mcast frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bcast_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_bcast_frames, "Received bcast frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_fcs_err_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_fcs_err_frames, "Received fcs err frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_ctrl_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_ctrl_frames, "Received ctrl frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pause_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_pause_frames, "Received pause frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pfc_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_pfc_frames, "Received pfc frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_align_err_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_align_err_frames, "Received align err frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_ovrsz_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_ovrsz_frames, "Received ovrsz frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_jbr_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_jbr_frames, "Received jbr frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_mtu_err_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_mtu_err_frames, "Received mtu err frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_tagged_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_tagged_frames, "Received tagged frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_double_tagged_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_double_tagged_frames, "Received double tagged frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_good_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_good_frames, "Received good frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pfc_ena_frames_pri0", CTLFLAG_RD, &softc->rx_port_stats->rx_pfc_ena_frames_pri0, "Received pfc ena frames pri0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pfc_ena_frames_pri1", CTLFLAG_RD, &softc->rx_port_stats->rx_pfc_ena_frames_pri1, "Received pfc ena frames pri1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pfc_ena_frames_pri2", CTLFLAG_RD, &softc->rx_port_stats->rx_pfc_ena_frames_pri2, "Received pfc ena frames pri2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pfc_ena_frames_pri3", CTLFLAG_RD, &softc->rx_port_stats->rx_pfc_ena_frames_pri3, "Received pfc ena frames pri3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pfc_ena_frames_pri4", CTLFLAG_RD, &softc->rx_port_stats->rx_pfc_ena_frames_pri4, "Received pfc ena frames pri4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pfc_ena_frames_pri5", CTLFLAG_RD, &softc->rx_port_stats->rx_pfc_ena_frames_pri5, "Received pfc ena frames pri5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pfc_ena_frames_pri6", CTLFLAG_RD, &softc->rx_port_stats->rx_pfc_ena_frames_pri6, "Received pfc ena frames pri6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pfc_ena_frames_pri7", CTLFLAG_RD, &softc->rx_port_stats->rx_pfc_ena_frames_pri7, "Received pfc ena frames pri7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_sch_crc_err_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_sch_crc_err_frames, "Received sch crc err frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_undrsz_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_undrsz_frames, "Received undrsz frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_eee_lpi_events", CTLFLAG_RD, &softc->rx_port_stats->rx_eee_lpi_events, "Received eee lpi events"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_eee_lpi_duration", CTLFLAG_RD, &softc->rx_port_stats->rx_eee_lpi_duration, "Received eee lpi duration"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_llfc_physical_msgs", CTLFLAG_RD, &softc->rx_port_stats->rx_llfc_physical_msgs, "Received llfc physical msgs"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_llfc_logical_msgs", CTLFLAG_RD, &softc->rx_port_stats->rx_llfc_logical_msgs, "Received llfc logical msgs"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_llfc_msgs_with_crc_err", CTLFLAG_RD, &softc->rx_port_stats->rx_llfc_msgs_with_crc_err, "Received llfc msgs with crc err"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_hcfc_msgs", CTLFLAG_RD, &softc->rx_port_stats->rx_hcfc_msgs, "Received hcfc msgs"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_hcfc_msgs_with_crc_err", CTLFLAG_RD, &softc->rx_port_stats->rx_hcfc_msgs_with_crc_err, "Received hcfc msgs with crc err"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes", CTLFLAG_RD, &softc->rx_port_stats->rx_bytes, "Received bytes"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_runt_bytes", CTLFLAG_RD, &softc->rx_port_stats->rx_runt_bytes, "Received runt bytes"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_runt_frames", CTLFLAG_RD, &softc->rx_port_stats->rx_runt_frames, "Received runt frames"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_stat_discard", CTLFLAG_RD, &softc->rx_port_stats->rx_stat_discard, "Received stat discard"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_stat_err", CTLFLAG_RD, &softc->rx_port_stats->rx_stat_err, "Received stat err"); if (BNXT_CHIP_P5(softc) && (softc->flags & BNXT_FLAG_FW_CAP_EXT_STATS)) { SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_cos0", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_bytes_cos0, "Transmitted bytes count cos0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_cos0", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_packets_cos0, "Transmitted packets count cos0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_cos1", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_bytes_cos1, "Transmitted bytes count cos1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_cos1", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_packets_cos1, "Transmitted packets count cos1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_cos2", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_bytes_cos2, "Transmitted bytes count cos2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_cos2", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_packets_cos2, "Transmitted packets count cos2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_cos3", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_bytes_cos3, "Transmitted bytes count cos3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_cos3", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_packets_cos3, "Transmitted packets count cos3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_cos4", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_bytes_cos4, "Transmitted bytes count cos4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_cos4", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_packets_cos4, "Transmitted packets count cos4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_cos5", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_bytes_cos5, "Transmitted bytes count cos5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_cos5", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_packets_cos5, "Transmitted packets count cos5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_cos6", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_bytes_cos6, "Transmitted bytes count cos6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_cos6", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_packets_cos6, "Transmitted packets count cos6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_cos7", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_bytes_cos7, "Transmitted bytes count cos7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_cos7", CTLFLAG_RD, &softc->tx_port_stats_ext->tx_packets_cos7, "Transmitted packets count cos7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_pri0", CTLFLAG_RD, &softc->tx_bytes_pri[0], "Transmitted bytes count pri0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_pri0", CTLFLAG_RD, &softc->tx_packets_pri[0], "Transmitted packets count pri0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_pri1", CTLFLAG_RD, &softc->tx_bytes_pri[1], "Transmitted bytes count pri1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_pri1", CTLFLAG_RD, &softc->tx_packets_pri[1], "Transmitted packets count pri1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_pri2", CTLFLAG_RD, &softc->tx_bytes_pri[2], "Transmitted bytes count pri2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_pri2", CTLFLAG_RD, &softc->tx_packets_pri[2], "Transmitted packets count pri2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_pri3", CTLFLAG_RD, &softc->tx_bytes_pri[3], "Transmitted bytes count pri3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_pri3", CTLFLAG_RD, &softc->tx_packets_pri[3], "Transmitted packets count pri3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_pri4", CTLFLAG_RD, &softc->tx_bytes_pri[4], "Transmitted bytes count pri4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_pri4", CTLFLAG_RD, &softc->tx_packets_pri[4], "Transmitted packets count pri4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_pri5", CTLFLAG_RD, &softc->tx_bytes_pri[5], "Transmitted bytes count pri5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_pri5", CTLFLAG_RD, &softc->tx_packets_pri[5], "Transmitted packets count pri5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_pri6", CTLFLAG_RD, &softc->tx_bytes_pri[6], "Transmitted bytes count pri6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_pri6", CTLFLAG_RD, &softc->tx_packets_pri[6], "Transmitted packets count pri6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_bytes_pri7", CTLFLAG_RD, &softc->tx_bytes_pri[7], "Transmitted bytes count pri7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tx_packets_pri7", CTLFLAG_RD, &softc->tx_packets_pri[7], "Transmitted packets count pri7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri0_tx_duration_us", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri0_tx_duration_us, "Time duration between" "XON to XOFF and XOFF to XON for pri0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri0_tx_transitions", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri0_tx_transitions, "Num times transition" "between XON to XOFF and XOFF to XON for pri0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri1_tx_duration_us", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri1_tx_duration_us, "Time duration between" "XON to XOFF and XOFF to XON for pri1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri1_tx_transitions", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri1_tx_transitions, "Num times transition" "between XON to XOFF and XOFF to XON for pri1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri2_tx_duration_us", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri2_tx_duration_us, "Time duration between" "XON to XOFF and XOFF to XON for pri2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri2_tx_transitions", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri2_tx_transitions, "Num times transition" "between XON to XOFF and XOFF to XON for pri2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri3_tx_duration_us", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri3_tx_duration_us, "Time duration between" "XON to XOFF and XOFF to XON for pri3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri3_tx_transitions", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri3_tx_transitions, "Num times transition" "between XON to XOFF and XOFF to XON for pri3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri4_tx_duration_us", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri4_tx_duration_us, "Time duration between" "XON to XOFF and XOFF to XON for pri4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri4_tx_transitions", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri4_tx_transitions, "Num times transition" "between XON to XOFF and XOFF to XON for pri4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri5_tx_duration_us", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri5_tx_duration_us, "Time duration between" "XON to XOFF and XOFF to XON for pri5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri5_tx_transitions", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri5_tx_transitions, "Num times transition" "between XON to XOFF and XOFF to XON for pri5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri6_tx_duration_us", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri6_tx_duration_us, "Time duration between" "XON to XOFF and XOFF to XON for pri6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri6_tx_transitions", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri6_tx_transitions, "Num times transition" "between XON to XOFF and XOFF to XON for pri6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri7_tx_duration_us", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri7_tx_duration_us, "Time duration between" "XON to XOFF and XOFF to XON for pri7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri7_tx_transitions", CTLFLAG_RD, &softc->tx_port_stats_ext->pfc_pri7_tx_transitions, "Num times transition" "between XON to XOFF and XOFF to XON for pri7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "link_down_events", CTLFLAG_RD, &softc->rx_port_stats_ext->link_down_events, "Num times link states down"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "continuous_pause_events", CTLFLAG_RD, &softc->rx_port_stats_ext->continuous_pause_events, "Num times pause events"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "resume_pause_events", CTLFLAG_RD, &softc->rx_port_stats_ext->resume_pause_events, "Num times pause events" "resumes"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "continuous_roce_pause_events", CTLFLAG_RD, &softc->rx_port_stats_ext->continuous_roce_pause_events, "Num times roce" "pause events"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "resume_roce_pause_events", CTLFLAG_RD, &softc->rx_port_stats_ext->resume_roce_pause_events, "Num times roce pause" "events resumes"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_cos0", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_bytes_cos0, "Received bytes count cos0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_cos0", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_packets_cos0, "Received packets count cos0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_cos1", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_bytes_cos1, "Received bytes count cos1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_cos1", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_packets_cos1, "Received packets count cos1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_cos2", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_bytes_cos2, "Received bytes count cos2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_cos2", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_packets_cos2, "Received packets count cos2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_cos3", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_bytes_cos3, "Received bytes count cos3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_cos3", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_packets_cos3, "Received packets count cos3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_cos4", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_bytes_cos4, "Received bytes count cos4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_cos4", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_packets_cos4, "Received packets count cos4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_cos5", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_bytes_cos5, "Received bytes count cos5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_cos5", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_packets_cos5, "Received packets count cos5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_cos6", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_bytes_cos6, "Received bytes count cos6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_cos6", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_packets_cos6, "Received packets count cos6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_cos7", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_bytes_cos7, "Received bytes count cos7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_cos7", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_packets_cos7, "Received packets count cos7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_pri0", CTLFLAG_RD, &softc->rx_bytes_pri[0], "Received bytes count pri0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_pri0", CTLFLAG_RD, &softc->rx_packets_pri[0], "Received packets count pri0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_pri1", CTLFLAG_RD, &softc->rx_bytes_pri[1], "Received bytes count pri1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_pri1", CTLFLAG_RD, &softc->rx_packets_pri[1], "Received packets count pri1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_pri2", CTLFLAG_RD, &softc->rx_bytes_pri[2], "Received bytes count pri2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_pri2", CTLFLAG_RD, &softc->rx_packets_pri[2], "Received packets count pri2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_pri3", CTLFLAG_RD, &softc->rx_bytes_pri[3], "Received bytes count pri3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_pri3", CTLFLAG_RD, &softc->rx_packets_pri[3], "Received packets count pri3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_pri4", CTLFLAG_RD, &softc->rx_bytes_pri[4], "Received bytes count pri4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_pri4", CTLFLAG_RD, &softc->rx_packets_pri[4], "Received packets count pri4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_pri5", CTLFLAG_RD, &softc->rx_bytes_pri[5], "Received bytes count pri5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_pri5", CTLFLAG_RD, &softc->rx_packets_pri[5], "Received packets count pri5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_pri6", CTLFLAG_RD, &softc->rx_bytes_pri[6], "Received bytes count pri6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_pri6", CTLFLAG_RD, &softc->rx_packets_pri[6], "Received packets count pri6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bytes_pri7", CTLFLAG_RD, &softc->rx_bytes_pri[7], "Received bytes count pri7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_packets_pri7", CTLFLAG_RD, &softc->rx_packets_pri[7], "Received packets count pri7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri0_rx_duration_us", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri0_rx_duration_us, "Time duration in receiving" "between XON to XOFF and XOFF to XON for pri0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri0_rx_transitions", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri0_rx_transitions, "Num times rx transition" "between XON to XOFF and XOFF to XON for pri0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri1_rx_duration_us", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri1_rx_duration_us, "Time duration in receiving" "between XON to XOFF and XOFF to XON for pri1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri1_rx_transitions", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri1_rx_transitions, "Num times rx transition" "between XON to XOFF and XOFF to XON for pri1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri2_rx_duration_us", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri2_rx_duration_us, "Time duration in receiving" "between XON to XOFF and XOFF to XON for pri2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri2_rx_transitions", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri2_rx_transitions, "Num times rx transition" "between XON to XOFF and XOFF to XON for pri2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri3_rx_duration_us", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri3_rx_duration_us, "Time duration in receiving" "between XON to XOFF and XOFF to XON for pri3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri3_rx_transitions", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri3_rx_transitions, "Num times rx transition" "between XON to XOFF and XOFF to XON for pri3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri4_rx_duration_us", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri4_rx_duration_us, "Time duration in receiving" "between XON to XOFF and XOFF to XON for pri4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri4_rx_transitions", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri4_rx_transitions, "Num times rx transition" "between XON to XOFF and XOFF to XON for pri4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri5_rx_duration_us", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri5_rx_duration_us, "Time duration in receiving" "between XON to XOFF and XOFF to XON for pri5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri5_rx_transitions", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri5_rx_transitions, "Num times rx transition" "between XON to XOFF and XOFF to XON for pri5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri6_rx_duration_us", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri6_rx_duration_us, "Time duration in receiving" "between XON to XOFF and XOFF to XON for pri6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri6_rx_transitions", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri6_rx_transitions, "Num times rx transition" "between XON to XOFF and XOFF to XON for pri6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri7_rx_duration_us", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri7_rx_duration_us, "Time duration in receiving" "between XON to XOFF and XOFF to XON for pri7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc_pri7_rx_transitions", CTLFLAG_RD, &softc->rx_port_stats_ext->pfc_pri7_rx_transitions, "Num times rx transition" "between XON to XOFF and XOFF to XON for pri7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_bits", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_bits, "total number of received bits"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_buffer_passed_threshold", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_buffer_passed_threshold, "num of events port" "buffer" "was over 85%"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_pcs_symbol_err", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_pcs_symbol_err, "num of symbol errors wasn't" "corrected by FEC"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_corrected_bits", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_corrected_bits, "num of bits corrected by FEC"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_bytes_cos0", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_bytes_cos0, "num of rx discard bytes" "count on cos0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_packets_cos0", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_packets_cos0, "num of rx discard packets" "count on cos0"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_bytes_cos1", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_bytes_cos1, "num of rx discard bytes" "count on cos1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_packets_cos1", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_packets_cos1, "num of rx discard packets" "count on cos1"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_bytes_cos2", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_bytes_cos2, "num of rx discard bytes" "count on cos2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_packets_cos2", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_packets_cos2, "num of rx discard packets" "count on cos2"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_bytes_cos3", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_bytes_cos3, "num of rx discard bytes" "count on cos3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_packets_cos3", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_packets_cos3, "num of rx discard packets" "count on cos3"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_bytes_cos4", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_bytes_cos4, "num of rx discard bytes" "count on cos4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_packets_cos4", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_packets_cos4, "num of rx discard packets" "count on cos4"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_bytes_cos5", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_bytes_cos5, "num of rx discard bytes" "count on cos5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_packets_cos5", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_packets_cos5, "num of rx discard packets" "count on cos5"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_bytes_cos6", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_bytes_cos6, "num of rx discard bytes" "count on cos6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_packets_cos6", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_packets_cos6, "num of rx discard packets" "count on cos6"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_bytes_cos7", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_bytes_cos7, "num of rx discard bytes" "count on cos7"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rx_discard_packets_cos7", CTLFLAG_RD, &softc->rx_port_stats_ext->rx_discard_packets_cos7, "num of rx discard packets" "count on cos7"); } return 0; } int bnxt_create_rx_sysctls(struct bnxt_softc *softc, int rxr) { struct sysctl_oid *oid; struct ctx_hw_stats *rx_stats = (void *)softc->rx_stats[rxr].idi_vaddr; char name[32]; char desc[64]; sprintf(name, "rxq%d", rxr); sprintf(desc, "receive queue %d", rxr); oid = SYSCTL_ADD_NODE(&softc->hw_stats, SYSCTL_CHILDREN(softc->hw_stats_oid), OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, desc); if (!oid) return ENOMEM; if (BNXT_CHIP_P5(softc)) SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "nq_num_ints", CTLFLAG_RD, &softc->nq_rings[rxr].int_count, "Num Interrupts"); else SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "rq_num_ints", CTLFLAG_RD, &softc->rx_cp_rings[rxr].int_count, "Num Interrupts"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "ucast_pkts", CTLFLAG_RD, &rx_stats->rx_ucast_pkts, "unicast packets received"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "mcast_pkts", CTLFLAG_RD, &rx_stats->rx_mcast_pkts, "multicast packets received"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "bcast_pkts", CTLFLAG_RD, &rx_stats->rx_bcast_pkts, "broadcast packets received"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "discard_pkts", CTLFLAG_RD, &rx_stats->rx_discard_pkts, "discarded receive packets"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "error_pkts", CTLFLAG_RD, &rx_stats->rx_error_pkts, "Error receive packets"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "ucast_bytes", CTLFLAG_RD, &rx_stats->rx_ucast_bytes, "unicast bytes received"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "mcast_bytes", CTLFLAG_RD, &rx_stats->rx_mcast_bytes, "multicast bytes received"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "bcast_bytes", CTLFLAG_RD, &rx_stats->rx_bcast_bytes, "broadcast bytes received"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tpa_pkts", CTLFLAG_RD, &rx_stats->tpa_pkts, "TPA packets"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tpa_bytes", CTLFLAG_RD, &rx_stats->tpa_bytes, "TPA bytes"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tpa_events", CTLFLAG_RD, &rx_stats->tpa_events, "TPA events"); SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, "tpa_aborts", CTLFLAG_RD, &rx_stats->tpa_aborts, "TPA aborts"); return 0; } static char *bnxt_chip_type[] = { "ASIC", "FPGA", "Palladium", "Unknown" }; #define MAX_CHIP_TYPE 3 static char *bnxt_parse_pkglog(int desired_field, uint8_t *data, size_t datalen) { char *retval = NULL; char *p; char *value; int field = 0; if (datalen < 1) return NULL; /* null-terminate the log data (removing last '\n'): */ data[datalen - 1] = 0; for (p = data; *p != 0; p++) { field = 0; retval = NULL; while (*p != 0 && *p != '\n') { value = p; while (*p != 0 && *p != '\t' && *p != '\n') p++; if (field == desired_field) retval = value; if (*p != '\t') break; *p = 0; field++; p++; } if (*p == 0) break; *p = 0; } return retval; } static int bnxt_package_ver_sysctl(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; struct iflib_dma_info dma_data; char *pkglog = NULL; char *p; char unk[] = ""; char *buf = unk; int rc; uint16_t ordinal = BNX_DIR_ORDINAL_FIRST; uint16_t index; uint32_t data_len; rc = bnxt_hwrm_nvm_find_dir_entry(softc, BNX_DIR_TYPE_PKG_LOG, &ordinal, BNX_DIR_EXT_NONE, &index, false, HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ, &data_len, NULL, NULL); dma_data.idi_vaddr = NULL; if (rc == 0 && data_len) { rc = iflib_dma_alloc(softc->ctx, data_len, &dma_data, BUS_DMA_NOWAIT); if (rc == 0) { rc = bnxt_hwrm_nvm_read(softc, index, 0, data_len, &dma_data); if (rc == 0) { pkglog = dma_data.idi_vaddr; p = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkglog, data_len); if (p && *p != 0 && isdigit(*p)) buf = p; } } else dma_data.idi_vaddr = NULL; } rc = sysctl_handle_string(oidp, buf, 0, req); if (dma_data.idi_vaddr) iflib_dma_free(&dma_data); return rc; } static int bnxt_hwrm_min_ver_sysctl(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; char buf[16]; uint8_t newver[3]; int rc; sprintf(buf, "%hhu.%hhu.%hhu", softc->ver_info->hwrm_min_major, softc->ver_info->hwrm_min_minor, softc->ver_info->hwrm_min_update); rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); if (rc || req->newptr == NULL) return rc; if (sscanf(buf, "%hhu.%hhu.%hhu%*c", &newver[0], &newver[1], &newver[2]) != 3) return EINVAL; softc->ver_info->hwrm_min_major = newver[0]; softc->ver_info->hwrm_min_minor = newver[1]; softc->ver_info->hwrm_min_update = newver[2]; bnxt_check_hwrm_version(softc); return rc; } int bnxt_create_ver_sysctls(struct bnxt_softc *softc) { struct bnxt_ver_info *vi = softc->ver_info; struct sysctl_oid *oid = vi->ver_oid; if (!oid) return ENOMEM; SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "hwrm_if", CTLFLAG_RD, vi->hwrm_if_ver, 0, "HWRM interface version"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "driver_hwrm_if", CTLFLAG_RD, vi->driver_hwrm_if_ver, 0, "HWRM firmware version"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "mgmt_fw", CTLFLAG_RD, vi->mgmt_fw_ver, 0, "management firmware version"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "netctrl_fw", CTLFLAG_RD, vi->netctrl_fw_ver, 0, "network control firmware version"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "roce_fw", CTLFLAG_RD, vi->roce_fw_ver, 0, "RoCE firmware version"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "fw_ver", CTLFLAG_RD, vi->fw_ver_str, 0, "Firmware version"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "phy", CTLFLAG_RD, vi->phy_ver, 0, "PHY version"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "hwrm_fw_name", CTLFLAG_RD, vi->hwrm_fw_name, 0, "HWRM firmware name"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "mgmt_fw_name", CTLFLAG_RD, vi->mgmt_fw_name, 0, "management firmware name"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "netctrl_fw_name", CTLFLAG_RD, vi->netctrl_fw_name, 0, "network control firmware name"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "roce_fw_name", CTLFLAG_RD, vi->roce_fw_name, 0, "RoCE firmware name"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "phy_vendor", CTLFLAG_RD, vi->phy_vendor, 0, "PHY vendor name"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "phy_partnumber", CTLFLAG_RD, vi->phy_partnumber, 0, "PHY vendor part number"); SYSCTL_ADD_U16(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "chip_num", CTLFLAG_RD, &vi->chip_num, 0, "chip number"); SYSCTL_ADD_U8(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "chip_rev", CTLFLAG_RD, &vi->chip_rev, 0, "chip revision"); SYSCTL_ADD_U8(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "chip_metal", CTLFLAG_RD, &vi->chip_metal, 0, "chip metal number"); SYSCTL_ADD_U8(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "chip_bond_id", CTLFLAG_RD, &vi->chip_bond_id, 0, "chip bond id"); SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "chip_type", CTLFLAG_RD, vi->chip_type > MAX_CHIP_TYPE ? bnxt_chip_type[MAX_CHIP_TYPE] : bnxt_chip_type[vi->chip_type], 0, "RoCE firmware name"); SYSCTL_ADD_PROC(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "package_ver", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, softc, 0, bnxt_package_ver_sysctl, "A", "currently installed package version"); SYSCTL_ADD_PROC(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "hwrm_min_ver", CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_hwrm_min_ver_sysctl, "A", "minimum hwrm API vesion to support"); return 0; } int bnxt_create_nvram_sysctls(struct bnxt_nvram_info *ni) { struct sysctl_oid *oid = ni->nvm_oid; if (!oid) return ENOMEM; SYSCTL_ADD_U16(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "mfg_id", CTLFLAG_RD, &ni->mfg_id, 0, "manufacturer id"); SYSCTL_ADD_U16(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "device_id", CTLFLAG_RD, &ni->device_id, 0, "device id"); SYSCTL_ADD_U32(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "sector_size", CTLFLAG_RD, &ni->sector_size, 0, "sector size"); SYSCTL_ADD_U32(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "size", CTLFLAG_RD, &ni->size, 0, "nvram total size"); SYSCTL_ADD_U32(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "reserved_size", CTLFLAG_RD, &ni->reserved_size, 0, "total reserved space"); SYSCTL_ADD_U32(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "available_size", CTLFLAG_RD, &ni->available_size, 0, "total available space"); return 0; } static int bnxt_rss_key_sysctl(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; char buf[HW_HASH_KEY_SIZE*2+1] = {0}; char *p; int i; int rc; for (p = buf, i=0; ivnic_info.rss_hash_key[i]); rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); if (rc || req->newptr == NULL) return rc; if (strspn(buf, "0123456789abcdefABCDEF") != (HW_HASH_KEY_SIZE * 2)) return EINVAL; for (p = buf, i=0; ivnic_info.rss_hash_key[i]) != 1) return EINVAL; p += 2; } if (if_getdrvflags(iflib_get_ifp(softc->ctx)) & IFF_DRV_RUNNING) bnxt_hwrm_rss_cfg(softc, &softc->vnic_info, softc->vnic_info.rss_hash_type); return rc; } static const char *bnxt_hash_types[] = {"ipv4", "tcp_ipv4", "udp_ipv4", "ipv6", "tcp_ipv6", "udp_ipv6", NULL}; static int bnxt_get_rss_type_str_bit(char *str) { int i; for (i=0; bnxt_hash_types[i]; i++) if (strcmp(bnxt_hash_types[i], str) == 0) return i; return -1; } static int bnxt_rss_type_sysctl(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; char buf[256] = {0}; char *p; char *next; int rc; int type; int bit; for (type = softc->vnic_info.rss_hash_type; type; type &= ~(1<= sizeof(bnxt_hash_types) / sizeof(const char *)) continue; if (type != softc->vnic_info.rss_hash_type) strcat(buf, ","); strcat(buf, bnxt_hash_types[bit]); } rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); if (rc || req->newptr == NULL) return rc; for (type = 0, next = buf, p = strsep(&next, " ,"); p; p = strsep(&next, " ,")) { bit = bnxt_get_rss_type_str_bit(p); if (bit == -1) return EINVAL; type |= 1<vnic_info.rss_hash_type) { softc->vnic_info.rss_hash_type = type; if (if_getdrvflags(iflib_get_ifp(softc->ctx)) & IFF_DRV_RUNNING) bnxt_hwrm_rss_cfg(softc, &softc->vnic_info, softc->vnic_info.rss_hash_type); } return rc; } static int bnxt_rx_stall_sysctl(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int rc; int val; if (softc == NULL) return EBUSY; val = (bool)(softc->vnic_info.flags & BNXT_VNIC_FLAG_BD_STALL); rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; if (val) softc->vnic_info.flags |= BNXT_VNIC_FLAG_BD_STALL; else softc->vnic_info.flags &= ~BNXT_VNIC_FLAG_BD_STALL; if (if_getdrvflags(iflib_get_ifp(softc->ctx)) & IFF_DRV_RUNNING) rc = bnxt_hwrm_vnic_cfg(softc, &softc->vnic_info); return rc; } static int bnxt_vlan_strip_sysctl(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int rc; int val; if (softc == NULL) return EBUSY; val = (bool)(softc->vnic_info.flags & BNXT_VNIC_FLAG_VLAN_STRIP); rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; if (val) softc->vnic_info.flags |= BNXT_VNIC_FLAG_VLAN_STRIP; else softc->vnic_info.flags &= ~BNXT_VNIC_FLAG_VLAN_STRIP; if (if_getdrvflags(iflib_get_ifp(softc->ctx)) & IFF_DRV_RUNNING) rc = bnxt_hwrm_vnic_cfg(softc, &softc->vnic_info); return rc; } static int bnxt_set_coal_rx_usecs(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int rc; int val; if (softc == NULL) return EBUSY; val = softc->rx_coal_usecs; rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; softc->rx_coal_usecs = val; rc = bnxt_hwrm_set_coal(softc); return rc; } static int bnxt_set_coal_rx_frames(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int rc; int val; if (softc == NULL) return EBUSY; val = softc->rx_coal_frames; rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; softc->rx_coal_frames = val; rc = bnxt_hwrm_set_coal(softc); return rc; } static int bnxt_set_coal_rx_usecs_irq(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int rc; int val; if (softc == NULL) return EBUSY; val = softc->rx_coal_usecs_irq; rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; softc->rx_coal_usecs_irq = val; rc = bnxt_hwrm_set_coal(softc); return rc; } static int bnxt_set_coal_rx_frames_irq(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int rc; int val; if (softc == NULL) return EBUSY; val = softc->rx_coal_frames_irq; rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; softc->rx_coal_frames_irq = val; rc = bnxt_hwrm_set_coal(softc); return rc; } static int bnxt_set_coal_tx_usecs(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int rc; int val; if (softc == NULL) return EBUSY; val = softc->tx_coal_usecs; rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; softc->tx_coal_usecs = val; rc = bnxt_hwrm_set_coal(softc); return rc; } static int bnxt_set_coal_tx_frames(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int rc; int val; if (softc == NULL) return EBUSY; val = softc->tx_coal_frames; rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; softc->tx_coal_frames = val; rc = bnxt_hwrm_set_coal(softc); return rc; } static int bnxt_set_coal_tx_usecs_irq(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int rc; int val; if (softc == NULL) return EBUSY; val = softc->tx_coal_usecs_irq; rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; softc->tx_coal_usecs_irq = val; rc = bnxt_hwrm_set_coal(softc); return rc; } static int bnxt_set_coal_tx_frames_irq(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int rc; int val; if (softc == NULL) return EBUSY; val = softc->tx_coal_frames_irq; rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; softc->tx_coal_frames_irq = val; rc = bnxt_hwrm_set_coal(softc); return rc; } +static +void simulate_reset(struct bnxt_softc *bp, char *fwcli_string) +{ + struct hwrm_dbg_fw_cli_input req = {0}; + int rc = 0; + + bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_FW_CLI); + req.cmpl_ring = -1; + req.target_id = -1; + req.cli_cmd_len = strlen(fwcli_string); + req.host_buf_len = 64 * 1024; + strcpy((char *)req.cli_cmd, fwcli_string); + + BNXT_HWRM_LOCK(bp); + rc = _hwrm_send_message(bp, &req, sizeof(req)); + if (rc) { + device_printf(bp->dev, " Manual FW fault failed, rc:%x\n", rc); + } + BNXT_HWRM_UNLOCK(bp); +} + +static int +bnxt_reset_ctrl(SYSCTL_HANDLER_ARGS) { + struct bnxt_softc *softc = arg1; + int rc = 0; + char buf[50] = {0}; + + if (softc == NULL) + return EBUSY; + + rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); + if (rc || req->newptr == NULL) + return rc; + + if (BNXT_CHIP_P5(softc)) + simulate_reset(softc, buf); + + return rc; +} + int bnxt_create_config_sysctls_pre(struct bnxt_softc *softc) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(softc->dev); struct sysctl_oid_list *children; children = SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev)); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rss_key", CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_rss_key_sysctl, "A", "RSS key"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rss_type", CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_rss_type_sysctl, "A", "RSS type bits"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_stall", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_rx_stall_sysctl, "I", "buffer rx packets in hardware until the host posts new buffers"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "vlan_strip", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_vlan_strip_sysctl, "I", "strip VLAN tag in the RX path"); SYSCTL_ADD_CONST_STRING(ctx, children, OID_AUTO, "if_name", CTLFLAG_RD, if_name(iflib_get_ifp(softc->ctx)), "interface name"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_coal_rx_usecs", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_set_coal_rx_usecs, "I", "interrupt coalescing Rx Usecs"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_coal_rx_frames", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_set_coal_rx_frames, "I", "interrupt coalescing Rx Frames"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_coal_rx_usecs_irq", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_set_coal_rx_usecs_irq, "I", "interrupt coalescing Rx Usecs IRQ"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_coal_rx_frames_irq", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_set_coal_rx_frames_irq, "I", "interrupt coalescing Rx Frames IRQ"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_coal_tx_usecs", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_set_coal_tx_usecs, "I", "interrupt coalescing Tx Usces"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_coal_tx_frames", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_set_coal_tx_frames, "I", "interrupt coalescing Tx Frames"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_coal_tx_usecs_irq", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_set_coal_tx_usecs_irq, "I", "interrupt coalescing Tx Usecs IRQ"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_coal_tx_frames_irq", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_set_coal_tx_frames_irq, "I", "interrupt coalescing Tx Frames IRQ"); SYSCTL_ADD_U32(ctx, children, OID_AUTO, "flags", CTLFLAG_RD, &softc->flags, 0, "flags"); SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fw_cap", CTLFLAG_RD, &softc->fw_cap, 0, "FW caps"); + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "reset_ctrl", CTLTYPE_STRING | CTLFLAG_RWTUN, softc, + 0, bnxt_reset_ctrl, "A", + "Issue controller reset: 0 / 1"); return 0; } #define BNXT_HW_LRO_FN(fn_name, arg) \ static int \ fn_name(SYSCTL_HANDLER_ARGS) { \ struct bnxt_softc *softc = arg1; \ int rc; \ int val; \ \ if (softc == NULL) \ return EBUSY; \ \ val = softc->hw_lro.arg; \ rc = sysctl_handle_int(oidp, &val, 0, req); \ if (rc || !req->newptr) \ return rc; \ \ if ((if_getdrvflags(iflib_get_ifp(softc->ctx)) & IFF_DRV_RUNNING)) \ return EBUSY; \ \ if (!(softc->flags & BNXT_FLAG_TPA)) \ return EINVAL; \ \ softc->hw_lro.arg = val; \ bnxt_validate_hw_lro_settings(softc); \ rc = bnxt_hwrm_vnic_tpa_cfg(softc); \ \ return rc; \ } BNXT_HW_LRO_FN(bnxt_hw_lro_enable_disable, enable) BNXT_HW_LRO_FN(bnxt_hw_lro_set_mode, is_mode_gro) BNXT_HW_LRO_FN(bnxt_hw_lro_set_max_agg_segs, max_agg_segs) BNXT_HW_LRO_FN(bnxt_hw_lro_set_max_aggs, max_aggs) BNXT_HW_LRO_FN(bnxt_hw_lro_set_min_agg_len, min_agg_len) #define BNXT_FLOW_CTRL_FN(fn_name, arg) \ static int \ fn_name(SYSCTL_HANDLER_ARGS) { \ struct bnxt_softc *softc = arg1; \ int rc; \ int val; \ \ if (softc == NULL) \ return EBUSY; \ \ val = softc->link_info.flow_ctrl.arg; \ rc = sysctl_handle_int(oidp, &val, 0, req); \ if (rc || !req->newptr) \ return rc; \ \ if (val) \ val = 1; \ \ if (softc->link_info.flow_ctrl.arg != val) { \ softc->link_info.flow_ctrl.arg = val; \ rc = bnxt_hwrm_set_link_setting(softc, true, false, false);\ rc = bnxt_hwrm_port_phy_qcfg(softc); \ } \ \ return rc; \ } BNXT_FLOW_CTRL_FN(bnxt_flow_ctrl_tx, tx) BNXT_FLOW_CTRL_FN(bnxt_flow_ctrl_rx, rx) BNXT_FLOW_CTRL_FN(bnxt_flow_ctrl_autoneg, autoneg) int bnxt_create_pause_fc_sysctls(struct bnxt_softc *softc) { struct sysctl_oid *oid = softc->flow_ctrl_oid; if (!oid) return ENOMEM; SYSCTL_ADD_PROC(&softc->flow_ctrl_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "tx", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_flow_ctrl_tx, "A", "Enable or Disable Tx Flow Ctrl: 0 / 1"); SYSCTL_ADD_PROC(&softc->flow_ctrl_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "rx", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_flow_ctrl_rx, "A", "Enable or Disable Tx Flow Ctrl: 0 / 1"); SYSCTL_ADD_PROC(&softc->flow_ctrl_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "autoneg", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_flow_ctrl_autoneg, "A", "Enable or Disable Autoneg Flow Ctrl: 0 / 1"); return 0; } int bnxt_create_hw_lro_sysctls(struct bnxt_softc *softc) { struct sysctl_oid *oid = softc->hw_lro_oid; if (!oid) return ENOMEM; SYSCTL_ADD_PROC(&softc->hw_lro_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "enable", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_hw_lro_enable_disable, "A", "Enable or Disable HW LRO: 0 / 1"); SYSCTL_ADD_PROC(&softc->hw_lro_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "gro_mode", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_hw_lro_set_mode, "A", "Set mode: 1 = GRO mode, 0 = RSC mode"); SYSCTL_ADD_PROC(&softc->hw_lro_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "max_agg_segs", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_hw_lro_set_max_agg_segs, "A", "Set Max Agg Seg Value (unit is Log2): " "0 (= 1 seg) / 1 (= 2 segs) / ... / 31 (= 2^31 segs)"); SYSCTL_ADD_PROC(&softc->hw_lro_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "max_aggs", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_hw_lro_set_max_aggs, "A", "Set Max Aggs Value (unit is Log2): " "0 (= 1 agg) / 1 (= 2 aggs) / ... / 7 (= 2^7 segs)"); SYSCTL_ADD_PROC(&softc->hw_lro_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "min_agg_len", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_hw_lro_set_min_agg_len, "A", "Min Agg Len: 1 to 9000"); return 0; } static int bnxt_dcb_dcbx_cap(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; int val; int rc; if (softc == NULL) return EBUSY; val = bnxt_dcb_getdcbx(softc); rc = sysctl_handle_int(oidp, &val, 0, req); if (rc || !req->newptr) return rc; bnxt_dcb_setdcbx(softc, val); return rc; } static char bnxt_ets_tsa_to_str(struct bnxt_softc *softc, uint32_t tc) { switch (softc->ieee_ets->tc_tsa[tc]) { case BNXT_IEEE_8021QAZ_TSA_STRICT: return 's'; case BNXT_IEEE_8021QAZ_TSA_ETS: return 'e'; default: return 'X'; } } static uint32_t bnxt_ets_str_to_tsa(char tsa_str) { switch (tsa_str) { case 's': return BNXT_IEEE_8021QAZ_TSA_STRICT; case 'e': return BNXT_IEEE_8021QAZ_TSA_ETS; default: return -1; } } static int bnxt_ets_get_val(struct bnxt_softc *softc, uint32_t type, uint32_t tc) { switch (type) { case BNXT_TYPE_ETS_TSA: if (softc->ieee_ets) return softc->ieee_ets->tc_tsa[tc]; break; case BNXT_TYPE_ETS_PRI2TC: if (softc->ieee_ets) return softc->ieee_ets->prio_tc[tc]; break; case BNXT_TYPE_ETS_TCBW: if (softc->ieee_ets) return softc->ieee_ets->tc_tx_bw[tc]; break; default: break; } return -1; } static void bnxt_pfc_get_string(struct bnxt_softc *softc, char *buf, struct bnxt_ieee_pfc *pfc) { uint32_t i; bool found = false; for (i = 0; i < BNXT_IEEE_8021QAZ_MAX_TCS; i++) { if (pfc->pfc_en & (1 << i)) { if (found) buf += sprintf(buf, ", "); buf += sprintf(buf, "%d", i); found = true; } } if (!found) buf += sprintf(buf, "none"); } static char *bnxt_get_tlv_selector_str(uint8_t selector) { switch (selector) { case BNXT_IEEE_8021QAZ_APP_SEL_ETHERTYPE: return "Ethertype"; case BNXT_IEEE_8021QAZ_APP_SEL_DGRAM: return "UDP or DCCP"; case BNXT_IEEE_8021QAZ_APP_SEL_DSCP: return "DSCP"; default: return "Unknown"; } } static void bnxt_app_tlv_get_string(struct bnxt_softc *softc, char *buf, struct bnxt_dcb_app *app, int num) { uint32_t i; if (!num) { buf += sprintf(buf, " None"); return; } buf += sprintf(buf, "\n"); for (i = 0; i < num; i++) { buf += sprintf(buf, "\tAPP#%0d:\tpri: %d,\tSel: %d,\t%s: %d\n", i, app[i].priority, app[i].selector, bnxt_get_tlv_selector_str(app[i].selector), app[i].protocol); } } static void bnxt_ets_get_string(struct bnxt_softc *softc, char *buf) { uint32_t type, i; type = BNXT_TYPE_ETS_TSA; for (type = 0; type < BNXT_TYPE_ETS_MAX; type++) { for (i = 0; i < BNXT_IEEE_8021QAZ_MAX_TCS; i++) { if (i == 0) buf += sprintf(buf, "%s:", BNXT_ETS_TYPE_STR[type]); if (!softc->ieee_ets) buf += sprintf(buf, "x"); else if (type == BNXT_TYPE_ETS_TSA) buf += sprintf(buf, "%c", bnxt_ets_tsa_to_str(softc, i)); else buf += sprintf(buf, "%d", bnxt_ets_get_val(softc, type, i)); if (i != BNXT_IEEE_8021QAZ_MAX_TCS - 1) buf += sprintf(buf, ","); } if (type != BNXT_TYPE_ETS_MAX - 1) buf += sprintf(buf, "#"); } } static int bnxt_dcb_list_app(SYSCTL_HANDLER_ARGS) { struct bnxt_dcb_app app[128] = {0}; struct bnxt_softc *softc = arg1; int rc, num_inputs = 0; char *buf; if (softc == NULL) return EBUSY; #define BNXT_APP_TLV_STR_LEN 4096 buf = malloc(BNXT_APP_TLV_STR_LEN, M_DEVBUF, M_NOWAIT | M_ZERO); if (!buf) return ENOMEM; bnxt_dcb_ieee_listapp(softc, app, &num_inputs); bnxt_app_tlv_get_string(softc, buf, app, num_inputs); rc = sysctl_handle_string(oidp, buf, BNXT_APP_TLV_STR_LEN, req); if (rc || req->newptr == NULL) goto end; end: free(buf, M_DEVBUF); return rc; } static int bnxt_dcb_del_app(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; struct bnxt_dcb_app app = {0}; char buf[256] = {0}; int rc, num_inputs; if (softc == NULL) return EBUSY; rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); if (rc || req->newptr == NULL) return rc; num_inputs = sscanf(buf, "%hhu,%hhu,%hd", &app.priority, &app.selector, &app.protocol); if (num_inputs != 3) { device_printf(softc->dev, "Invalid app tlv syntax, inputs = %d\n", num_inputs); return EINVAL; } bnxt_dcb_ieee_delapp(softc, &app); return rc; } static int bnxt_dcb_set_app(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; struct bnxt_dcb_app app = {0}; char buf[256] = {0}; int rc, num_inputs; if (softc == NULL) return EBUSY; rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); if (rc || req->newptr == NULL) return rc; num_inputs = sscanf(buf, "%hhu,%hhu,%hd", &app.priority, &app.selector, &app.protocol); if (num_inputs != 3) { device_printf(softc->dev, "Invalid app tlv syntax, inputs = %d\n", num_inputs); return EINVAL; } bnxt_dcb_ieee_setapp(softc, &app); return rc; } static int bnxt_dcb_pfc(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; struct bnxt_ieee_pfc pfc = {0}; int rc, i, num_inputs; char buf[256] = {0}; int pri_mask = 0; char pri[8]; if (softc == NULL) return EBUSY; rc = bnxt_dcb_ieee_getpfc(softc, &pfc); if (!rc) bnxt_pfc_get_string(softc, buf, &pfc); else sprintf(buf, "## getpfc failed with error %d ##", rc); rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); if (rc || req->newptr == NULL) return rc; /* Check for 'none' string first */ if (sscanf(buf, "%s", buf) == 1) { if (strncmp(buf, "none", 8) == 0) { goto configure; } } num_inputs = sscanf(buf, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu,%hhu,%hhu", &pri[0], &pri[1], &pri[2], &pri[3], &pri[4], &pri[5], &pri[6], &pri[7]); if (num_inputs < 1 || num_inputs > 8) { device_printf(softc->dev, "Invalid pfc syntax, inputs = %d\n", num_inputs); return EINVAL; } for (i = 0; i < num_inputs; i++) { if (pri[i] > 7 || pri[i] < 0) { device_printf(softc->dev, "Invalid priority %d. Valid priorties are " "from 0 to 7 and string \"none\".\n", pri[i]); return EINVAL; } pri_mask |= (1 << pri[i]) & 0xFF; } configure: pfc.pfc_en = pri_mask; rc = bnxt_dcb_ieee_setpfc(softc, &pfc); if (rc) device_printf(softc->dev, "setpfc failed with status %d\n", rc); return rc; } static int bnxt_dcb_ets(SYSCTL_HANDLER_ARGS) { struct bnxt_softc *softc = arg1; struct bnxt_ieee_ets ets = {0}; int rc = 0, i, num_inputs; char buf[256] = {0}; char tsa[8]; if (softc == NULL) return EBUSY; rc = bnxt_dcb_ieee_getets(softc, &ets); if (!rc) bnxt_ets_get_string(softc, buf); else sprintf(buf, "## getets failed with error %d ##", rc); rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); if (rc || req->newptr == NULL) return rc; num_inputs = sscanf(buf, "tsa:%c,%c,%c,%c,%c,%c,%c,%c#" "pri2tc:%hhu,%hhu,%hhu,%hhu,%hhu,%hhu,%hhu,%hhu#" "tcbw:%hhu,%hhu,%hhu,%hhu,%hhu,%hhu,%hhu,%hhu", &tsa[0], &tsa[1], &tsa[2], &tsa[3], &tsa[4], &tsa[5], &tsa[6], &tsa[7], &ets.prio_tc[0], &ets.prio_tc[1], &ets.prio_tc[2], &ets.prio_tc[3], &ets.prio_tc[4], &ets.prio_tc[5], &ets.prio_tc[6], &ets.prio_tc[7], &ets.tc_tx_bw[0], &ets.tc_tx_bw[1], &ets.tc_tx_bw[2], &ets.tc_tx_bw[3], &ets.tc_tx_bw[4], &ets.tc_tx_bw[5], &ets.tc_tx_bw[6], &ets.tc_tx_bw[7]); if (num_inputs != 24) return EINVAL; for ( i= 0; i < 8; i++) ets.tc_tsa[i] = bnxt_ets_str_to_tsa(tsa[i]); rc = bnxt_dcb_ieee_setets(softc, &ets); return rc; } int bnxt_create_dcb_sysctls(struct bnxt_softc *softc) { struct sysctl_oid *oid = softc->dcb_oid; if (!oid) return ENOMEM; SYSCTL_ADD_PROC(&softc->dcb_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "dcbx_cap", CTLTYPE_INT | CTLFLAG_RWTUN, softc, 0, bnxt_dcb_dcbx_cap, "A", "Enable or Disable LRO: 0 / 1"); SYSCTL_ADD_PROC(&softc->dcb_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "ets", CTLTYPE_STRING | CTLFLAG_RWTUN, softc, 0, bnxt_dcb_ets, "A", "Enhanced Transmission Selection (ETS)"); SYSCTL_ADD_PROC(&softc->dcb_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "pfc", CTLTYPE_STRING | CTLFLAG_RWTUN, softc, 0, bnxt_dcb_pfc, "A", "Enhanced Transmission Selection (ETS)"); SYSCTL_ADD_PROC(&softc->dcb_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "set_apptlv", CTLTYPE_STRING | CTLFLAG_WR, softc, 0, bnxt_dcb_set_app, "A", "Set App TLV"); SYSCTL_ADD_PROC(&softc->dcb_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "del_apptlv", CTLTYPE_STRING | CTLFLAG_WR, softc, 0, bnxt_dcb_del_app, "A", "Delete App TLV"); SYSCTL_ADD_PROC(&softc->dcb_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "list_apptlv", CTLTYPE_STRING | CTLFLAG_RD, softc, 0, bnxt_dcb_list_app, "A", "List all App TLVs"); return 0; } int bnxt_create_config_sysctls_post(struct bnxt_softc *softc) { /* Nothing for now, meant for future expansion */ return 0; } diff --git a/sys/dev/bnxt/bnxt_en/bnxt_ulp.c b/sys/dev/bnxt/bnxt_en/bnxt_ulp.c index 90253b0f5e9f..17ae916052f4 100644 --- a/sys/dev/bnxt/bnxt_en/bnxt_ulp.c +++ b/sys/dev/bnxt/bnxt_en/bnxt_ulp.c @@ -1,524 +1,526 @@ /*- * Broadcom NetXtreme-C/E network driver. * * Copyright (c) 2024 Broadcom, All Rights Reserved. * The term Broadcom refers to Broadcom Limited and/or its subsidiaries * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "hsi_struct_def.h" #include "bnxt.h" #include "bnxt_hwrm.h" #include "bnxt_ulp.h" +void bnxt_destroy_irq(struct bnxt_softc *softc); + static int bnxt_register_dev(struct bnxt_en_dev *edev, int ulp_id, struct bnxt_ulp_ops *ulp_ops, void *handle) { struct bnxt_softc *bp = edev->softc; struct bnxt_ulp *ulp; int rc = 0; if (ulp_id >= BNXT_MAX_ULP) return -EINVAL; mtx_lock(&bp->en_ops_lock); ulp = &edev->ulp_tbl[ulp_id]; if (rcu_access_pointer(ulp->ulp_ops)) { device_printf(bp->dev, "ulp id %d already registered\n", ulp_id); rc = -EBUSY; goto exit; } edev->flags &= ~BNXT_EN_FLAG_ULP_STOPPED; atomic_set(&ulp->ref_count, 0); ulp->handle = handle; rcu_assign_pointer(ulp->ulp_ops, ulp_ops); if (ulp_id == BNXT_ROCE_ULP) { if (test_bit(BNXT_STATE_OPEN, &bp->state) && bp->is_dev_init) bnxt_hwrm_vnic_cfg(bp, &bp->vnic_info); } exit: mtx_unlock(&bp->en_ops_lock); return rc; } static int bnxt_unregister_dev(struct bnxt_en_dev *edev, int ulp_id) { struct bnxt_softc *bp = edev->softc; struct bnxt_ulp *ulp; int i = 0; if (ulp_id >= BNXT_MAX_ULP) return -EINVAL; ulp = &edev->ulp_tbl[ulp_id]; if (!rcu_access_pointer(ulp->ulp_ops)) { device_printf(bp->dev, "ulp id %d not registered\n", ulp_id); return -EINVAL; } if (ulp_id == BNXT_ROCE_ULP && ulp->msix_requested) edev->en_ops->bnxt_free_msix(edev, ulp_id); mtx_lock(&bp->en_ops_lock); RCU_INIT_POINTER(ulp->ulp_ops, NULL); synchronize_rcu(); ulp->max_async_event_id = 0; ulp->async_events_bmap = NULL; while (atomic_read(&ulp->ref_count) != 0 && i < 10) { msleep(100); i++; } mtx_unlock(&bp->en_ops_lock); return 0; } static void bnxt_fill_msix_vecs(struct bnxt_softc *bp, struct bnxt_msix_entry *ent) { struct bnxt_en_dev *edev = bp->edev; int num_msix, idx, i; num_msix = edev->ulp_tbl[BNXT_ROCE_ULP].msix_requested; idx = edev->ulp_tbl[BNXT_ROCE_ULP].msix_base; for (i = 0; i < num_msix; i++) { ent[i].vector = bp->irq_tbl[idx + i].vector; ent[i].ring_idx = idx + i; if (BNXT_CHIP_P5(bp)) ent[i].db_offset = DB_PF_OFFSET_P5; else ent[i].db_offset = (idx + i) * 0x80; } } static int bnxt_req_msix_vecs(struct bnxt_en_dev *edev, int ulp_id, struct bnxt_msix_entry *ent, int num_msix) { struct bnxt_softc *bp = edev->softc; int avail_msix, idx; if (ulp_id != BNXT_ROCE_ULP) return -EINVAL; if (edev->ulp_tbl[ulp_id].msix_requested) return -EAGAIN; idx = bp->total_irqs - BNXT_ROCE_IRQ_COUNT; avail_msix = BNXT_ROCE_IRQ_COUNT; mtx_lock(&bp->en_ops_lock); edev->ulp_tbl[ulp_id].msix_base = idx; edev->ulp_tbl[ulp_id].msix_requested = avail_msix; bnxt_fill_msix_vecs(bp, ent); edev->flags |= BNXT_EN_FLAG_MSIX_REQUESTED; mtx_unlock(&bp->en_ops_lock); return avail_msix; } static int bnxt_free_msix_vecs(struct bnxt_en_dev *edev, int ulp_id) { struct bnxt_softc *bp = edev->softc; if (ulp_id != BNXT_ROCE_ULP) return -EINVAL; if (!(edev->flags & BNXT_EN_FLAG_MSIX_REQUESTED)) return 0; mtx_lock(&bp->en_ops_lock); edev->ulp_tbl[ulp_id].msix_requested = 0; edev->flags &= ~BNXT_EN_FLAG_MSIX_REQUESTED; if (edev->flags & BNXT_EN_FLAG_ULP_STOPPED) goto stopped; stopped: mtx_unlock(&bp->en_ops_lock); return 0; } int bnxt_get_ulp_msix_num(struct bnxt_softc *bp) { if (bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) { struct bnxt_en_dev *edev = bp->edev; return edev->ulp_tbl[BNXT_ROCE_ULP].msix_requested; } return 0; } int bnxt_get_ulp_msix_base(struct bnxt_softc *bp) { if (bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) { struct bnxt_en_dev *edev = bp->edev; if (edev->ulp_tbl[BNXT_ROCE_ULP].msix_requested) return edev->ulp_tbl[BNXT_ROCE_ULP].msix_base; } return 0; } static int bnxt_send_msg(struct bnxt_en_dev *edev, int ulp_id, struct bnxt_fw_msg *fw_msg) { struct bnxt_softc *softc = edev->softc; int rc; if ((ulp_id != BNXT_ROCE_ULP) && softc->fw_reset_state) return -EBUSY; rc = bnxt_hwrm_passthrough(softc, fw_msg->msg, fw_msg->msg_len, fw_msg->resp, fw_msg->resp_max_len, fw_msg->timeout); return rc; } static void bnxt_ulp_get(struct bnxt_ulp *ulp) { atomic_inc(&ulp->ref_count); } static void bnxt_ulp_put(struct bnxt_ulp *ulp) { atomic_dec(&ulp->ref_count); } void bnxt_ulp_stop(struct bnxt_softc *bp) { struct bnxt_en_dev *edev = bp->edev; struct bnxt_ulp_ops *ops; int i; if (!edev) return; edev->flags |= BNXT_EN_FLAG_ULP_STOPPED; edev->en_state = bp->state; for (i = 0; i < BNXT_MAX_ULP; i++) { struct bnxt_ulp *ulp = &edev->ulp_tbl[i]; ops = ulp->ulp_ops; if (!ops || !ops->ulp_stop) continue; ops->ulp_stop(ulp->handle); } } void bnxt_ulp_start(struct bnxt_softc *bp, int err) { struct bnxt_en_dev *edev = bp->edev; struct bnxt_ulp_ops *ops; int i; if (!edev) return; edev->flags &= ~BNXT_EN_FLAG_ULP_STOPPED; edev->en_state = bp->state; if (err) return; for (i = 0; i < BNXT_MAX_ULP; i++) { struct bnxt_ulp *ulp = &edev->ulp_tbl[i]; ops = ulp->ulp_ops; if (!ops || !ops->ulp_start) continue; ops->ulp_start(ulp->handle); } } void bnxt_ulp_sriov_cfg(struct bnxt_softc *bp, int num_vfs) { struct bnxt_en_dev *edev = bp->edev; struct bnxt_ulp_ops *ops; int i; if (!edev) return; for (i = 0; i < BNXT_MAX_ULP; i++) { struct bnxt_ulp *ulp = &edev->ulp_tbl[i]; rcu_read_lock(); ops = rcu_dereference(ulp->ulp_ops); if (!ops || !ops->ulp_sriov_config) { rcu_read_unlock(); continue; } bnxt_ulp_get(ulp); rcu_read_unlock(); ops->ulp_sriov_config(ulp->handle, num_vfs); bnxt_ulp_put(ulp); } } void bnxt_ulp_shutdown(struct bnxt_softc *bp) { struct bnxt_en_dev *edev = bp->edev; struct bnxt_ulp_ops *ops; int i; if (!edev) return; for (i = 0; i < BNXT_MAX_ULP; i++) { struct bnxt_ulp *ulp = &edev->ulp_tbl[i]; ops = ulp->ulp_ops; if (!ops || !ops->ulp_shutdown) continue; ops->ulp_shutdown(ulp->handle); } } void bnxt_ulp_irq_stop(struct bnxt_softc *bp) { struct bnxt_en_dev *edev = bp->edev; struct bnxt_ulp_ops *ops; if (!edev || !(edev->flags & BNXT_EN_FLAG_MSIX_REQUESTED)) return; if (bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) { struct bnxt_ulp *ulp = &edev->ulp_tbl[BNXT_ROCE_ULP]; if (!ulp->msix_requested) return; ops = ulp->ulp_ops; if (!ops || !ops->ulp_irq_stop) return; ops->ulp_irq_stop(ulp->handle); } } void bnxt_ulp_async_events(struct bnxt_softc *bp, struct hwrm_async_event_cmpl *cmpl) { u16 event_id = le16_to_cpu(cmpl->event_id); struct bnxt_en_dev *edev = bp->edev; struct bnxt_ulp_ops *ops; int i; if (!edev) return; rcu_read_lock(); for (i = 0; i < BNXT_MAX_ULP; i++) { struct bnxt_ulp *ulp = &edev->ulp_tbl[i]; ops = rcu_dereference(ulp->ulp_ops); if (!ops || !ops->ulp_async_notifier) continue; if (!ulp->async_events_bmap || event_id > ulp->max_async_event_id) continue; /* Read max_async_event_id first before testing the bitmap. */ rmb(); if (edev->flags & BNXT_EN_FLAG_ULP_STOPPED) continue; if (test_bit(event_id, ulp->async_events_bmap)) ops->ulp_async_notifier(ulp->handle, cmpl); } rcu_read_unlock(); } static int bnxt_register_async_events(struct bnxt_en_dev *edev, int ulp_id, unsigned long *events_bmap, u16 max_id) { struct bnxt_softc *bp = edev->softc; struct bnxt_ulp *ulp; if (ulp_id >= BNXT_MAX_ULP) return -EINVAL; mtx_lock(&bp->en_ops_lock); ulp = &edev->ulp_tbl[ulp_id]; ulp->async_events_bmap = events_bmap; wmb(); ulp->max_async_event_id = max_id; - bnxt_hwrm_func_drv_rgtr(bp); + bnxt_hwrm_func_drv_rgtr(bp, events_bmap, max_id + 1, true); mtx_unlock(&bp->en_ops_lock); return 0; } -static void bnxt_destroy_irq(struct bnxt_softc *softc) +void bnxt_destroy_irq(struct bnxt_softc *softc) { kfree(softc->irq_tbl); } static int bnxt_populate_irq(struct bnxt_softc *softc) { struct resource_list *rl = NULL; struct resource_list_entry *rle = NULL; struct bnxt_msix_tbl *irq_tbl = NULL; struct pci_devinfo *dinfo = NULL; int i; softc->total_irqs = softc->scctx->isc_nrxqsets + BNXT_ROCE_IRQ_COUNT; irq_tbl = kzalloc(softc->total_irqs * sizeof(*softc->irq_tbl), GFP_KERNEL); if (!irq_tbl) { device_printf(softc->dev, "Failed to allocate IRQ table\n"); return -1; } dinfo = device_get_ivars(softc->pdev->dev.bsddev); rl = &dinfo->resources; rle = resource_list_find(rl, SYS_RES_IRQ, 1); softc->pdev->dev.irq_start = rle->start; softc->pdev->dev.irq_end = rle->start + softc->total_irqs; for (i = 0; i < softc->total_irqs; i++) { irq_tbl[i].entry = i; irq_tbl[i].vector = softc->pdev->dev.irq_start + i; } softc->irq_tbl = irq_tbl; return 0; } static const struct bnxt_en_ops bnxt_en_ops_tbl = { .bnxt_register_device = bnxt_register_dev, .bnxt_unregister_device = bnxt_unregister_dev, .bnxt_request_msix = bnxt_req_msix_vecs, .bnxt_free_msix = bnxt_free_msix_vecs, .bnxt_send_fw_msg = bnxt_send_msg, .bnxt_register_fw_async_events = bnxt_register_async_events, }; void bnxt_aux_dev_release(struct device *dev) { struct bnxt_aux_dev *bnxt_adev = container_of(dev, struct bnxt_aux_dev, aux_dev.dev); struct bnxt_softc *bp = bnxt_adev->edev->softc; kfree(bnxt_adev->edev); bnxt_adev->edev = NULL; bp->edev = NULL; } static inline void bnxt_set_edev_info(struct bnxt_en_dev *edev, struct bnxt_softc *bp) { edev->en_ops = &bnxt_en_ops_tbl; edev->net = bp->ifp; edev->pdev = bp->pdev; edev->softc = bp; edev->l2_db_size = bp->db_size; mtx_init(&bp->en_ops_lock, "Ethernet ops lock", NULL, MTX_DEF); if (bp->flags & BNXT_FLAG_ROCEV1_CAP) edev->flags |= BNXT_EN_FLAG_ROCEV1_CAP; if (bp->flags & BNXT_FLAG_ROCEV2_CAP) edev->flags |= BNXT_EN_FLAG_ROCEV2_CAP; if (bp->is_asym_q) edev->flags |= BNXT_EN_FLAG_ASYM_Q; edev->hwrm_bar = bp->hwrm_bar; edev->port_partition_type = bp->port_partition_type; edev->ulp_version = BNXT_ULP_VERSION; } int bnxt_rdma_aux_device_del(struct bnxt_softc *softc) { struct bnxt_aux_dev *bnxt_adev = softc->aux_dev; struct auxiliary_device *adev; adev = &bnxt_adev->aux_dev; auxiliary_device_delete(adev); auxiliary_device_uninit(adev); bnxt_destroy_irq(softc); return 0; } int bnxt_rdma_aux_device_add(struct bnxt_softc *bp) { struct bnxt_aux_dev *bnxt_adev = bp->aux_dev; struct bnxt_en_dev *edev = bnxt_adev->edev; struct auxiliary_device *aux_dev; int ret = -1; if (bnxt_populate_irq(bp)) return ret; device_printf(bp->dev, "V:D:SV:SD %x:%x:%x:%x, irq 0x%x, " "devfn 0x%x, cla 0x%x, rev 0x%x, msi_en 0x%x\n", bp->pdev->vendor, bp->pdev->device, bp->pdev->subsystem_vendor, bp->pdev->subsystem_device, bp->pdev->irq, bp->pdev->devfn, bp->pdev->class, bp->pdev->revision, bp->pdev->msi_enabled); aux_dev = &bnxt_adev->aux_dev; aux_dev->id = bnxt_adev->id; aux_dev->name = "rdma"; aux_dev->dev.parent = &bp->pdev->dev; aux_dev->dev.release = bnxt_aux_dev_release; if (!edev) { edev = kzalloc(sizeof(*edev), GFP_KERNEL); if (!edev) return -ENOMEM; } bnxt_set_edev_info(edev, bp); bnxt_adev->edev = edev; bp->edev = edev; ret = auxiliary_device_init(aux_dev); if (ret) goto err_free_edev; ret = auxiliary_device_add(aux_dev); if (ret) goto err_dev_uninit; return 0; err_dev_uninit: auxiliary_device_uninit(aux_dev); err_free_edev: kfree(edev); bnxt_adev->edev = NULL; bp->edev = NULL; return ret; } diff --git a/sys/dev/bnxt/bnxt_en/if_bnxt.c b/sys/dev/bnxt/bnxt_en/if_bnxt.c index f3f6bd83d0c3..b26997c8f197 100644 --- a/sys/dev/bnxt/bnxt_en/if_bnxt.c +++ b/sys/dev/bnxt/bnxt_en/if_bnxt.c @@ -1,3974 +1,4774 @@ /*- * Broadcom NetXtreme-C/E network driver. * * Copyright (c) 2016 Broadcom, All Rights Reserved. * The term Broadcom refers to Broadcom Limited and/or its subsidiaries * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "opt_inet.h" #include "opt_inet6.h" #include "opt_rss.h" #include "ifdi_if.h" #include "bnxt.h" #include "bnxt_hwrm.h" #include "bnxt_ioctl.h" #include "bnxt_sysctl.h" #include "hsi_struct_def.h" #include "bnxt_mgmt.h" #include "bnxt_ulp.h" #include "bnxt_auxbus_compat.h" /* * PCI Device ID Table */ static const pci_vendor_info_t bnxt_vendor_info_array[] = { PVID(BROADCOM_VENDOR_ID, BCM57301, "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet Controller"), PVID(BROADCOM_VENDOR_ID, BCM57302, "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet Controller"), PVID(BROADCOM_VENDOR_ID, BCM57304, "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet Controller"), PVID(BROADCOM_VENDOR_ID, BCM57311, "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57312, "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57314, "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57402, "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet Controller"), PVID(BROADCOM_VENDOR_ID, BCM57402_NPAR, "Broadcom BCM57402 NetXtreme-E Partition"), PVID(BROADCOM_VENDOR_ID, BCM57404, "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet Controller"), PVID(BROADCOM_VENDOR_ID, BCM57404_NPAR, "Broadcom BCM57404 NetXtreme-E Partition"), PVID(BROADCOM_VENDOR_ID, BCM57406, "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet Controller"), PVID(BROADCOM_VENDOR_ID, BCM57406_NPAR, "Broadcom BCM57406 NetXtreme-E Partition"), PVID(BROADCOM_VENDOR_ID, BCM57407, "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet Controller"), PVID(BROADCOM_VENDOR_ID, BCM57407_NPAR, "Broadcom BCM57407 NetXtreme-E Ethernet Partition"), PVID(BROADCOM_VENDOR_ID, BCM57407_SFP, "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet Controller"), PVID(BROADCOM_VENDOR_ID, BCM57412, "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57412_NPAR1, "Broadcom BCM57412 NetXtreme-E Ethernet Partition"), PVID(BROADCOM_VENDOR_ID, BCM57412_NPAR2, "Broadcom BCM57412 NetXtreme-E Ethernet Partition"), PVID(BROADCOM_VENDOR_ID, BCM57414, "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57414_NPAR1, "Broadcom BCM57414 NetXtreme-E Ethernet Partition"), PVID(BROADCOM_VENDOR_ID, BCM57414_NPAR2, "Broadcom BCM57414 NetXtreme-E Ethernet Partition"), PVID(BROADCOM_VENDOR_ID, BCM57416, "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57416_NPAR1, "Broadcom BCM57416 NetXtreme-E Ethernet Partition"), PVID(BROADCOM_VENDOR_ID, BCM57416_NPAR2, "Broadcom BCM57416 NetXtreme-E Ethernet Partition"), PVID(BROADCOM_VENDOR_ID, BCM57416_SFP, "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57417, "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57417_NPAR1, "Broadcom BCM57417 NetXtreme-E Ethernet Partition"), PVID(BROADCOM_VENDOR_ID, BCM57417_NPAR2, "Broadcom BCM57417 NetXtreme-E Ethernet Partition"), PVID(BROADCOM_VENDOR_ID, BCM57417_SFP, "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57454, "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM58700, "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57508, "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57504, "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, BCM57502, "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet"), PVID(BROADCOM_VENDOR_ID, NETXTREME_C_VF1, "Broadcom NetXtreme-C Ethernet Virtual Function"), PVID(BROADCOM_VENDOR_ID, NETXTREME_C_VF2, "Broadcom NetXtreme-C Ethernet Virtual Function"), PVID(BROADCOM_VENDOR_ID, NETXTREME_C_VF3, "Broadcom NetXtreme-C Ethernet Virtual Function"), PVID(BROADCOM_VENDOR_ID, NETXTREME_E_VF1, "Broadcom NetXtreme-E Ethernet Virtual Function"), PVID(BROADCOM_VENDOR_ID, NETXTREME_E_VF2, "Broadcom NetXtreme-E Ethernet Virtual Function"), PVID(BROADCOM_VENDOR_ID, NETXTREME_E_VF3, "Broadcom NetXtreme-E Ethernet Virtual Function"), /* required last entry */ PVID_END }; /* * Function prototypes */ SLIST_HEAD(softc_list, bnxt_softc_list) pf_list; int bnxt_num_pfs = 0; +void +process_nq(struct bnxt_softc *softc, uint16_t nqid); static void *bnxt_register(device_t dev); /* Soft queue setup and teardown */ static int bnxt_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); static int bnxt_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); static void bnxt_queues_free(if_ctx_t ctx); /* Device setup and teardown */ static int bnxt_attach_pre(if_ctx_t ctx); static int bnxt_attach_post(if_ctx_t ctx); static int bnxt_detach(if_ctx_t ctx); /* Device configuration */ static void bnxt_init(if_ctx_t ctx); static void bnxt_stop(if_ctx_t ctx); static void bnxt_multi_set(if_ctx_t ctx); static int bnxt_mtu_set(if_ctx_t ctx, uint32_t mtu); static void bnxt_media_status(if_ctx_t ctx, struct ifmediareq * ifmr); static int bnxt_media_change(if_ctx_t ctx); static int bnxt_promisc_set(if_ctx_t ctx, int flags); static uint64_t bnxt_get_counter(if_ctx_t, ift_counter); static void bnxt_update_admin_status(if_ctx_t ctx); static void bnxt_if_timer(if_ctx_t ctx, uint16_t qid); /* Interrupt enable / disable */ static void bnxt_intr_enable(if_ctx_t ctx); static int bnxt_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid); static int bnxt_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid); static void bnxt_disable_intr(if_ctx_t ctx); static int bnxt_msix_intr_assign(if_ctx_t ctx, int msix); /* vlan support */ static void bnxt_vlan_register(if_ctx_t ctx, uint16_t vtag); static void bnxt_vlan_unregister(if_ctx_t ctx, uint16_t vtag); /* ioctl */ static int bnxt_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data); static int bnxt_shutdown(if_ctx_t ctx); static int bnxt_suspend(if_ctx_t ctx); static int bnxt_resume(if_ctx_t ctx); /* Internal support functions */ static int bnxt_probe_phy(struct bnxt_softc *softc); static void bnxt_add_media_types(struct bnxt_softc *softc); static int bnxt_pci_mapping(struct bnxt_softc *softc); static void bnxt_pci_mapping_free(struct bnxt_softc *softc); static int bnxt_update_link(struct bnxt_softc *softc, bool chng_link_state); static int bnxt_handle_def_cp(void *arg); static int bnxt_handle_isr(void *arg); static void bnxt_clear_ids(struct bnxt_softc *softc); static void inline bnxt_do_enable_intr(struct bnxt_cp_ring *cpr); static void inline bnxt_do_disable_intr(struct bnxt_cp_ring *cpr); static void bnxt_mark_cpr_invalid(struct bnxt_cp_ring *cpr); static void bnxt_def_cp_task(void *context); static void bnxt_handle_async_event(struct bnxt_softc *softc, struct cmpl_base *cmpl); static uint64_t bnxt_get_baudrate(struct bnxt_link_info *link); static void bnxt_get_wol_settings(struct bnxt_softc *softc); static int bnxt_wol_config(if_ctx_t ctx); static bool bnxt_if_needs_restart(if_ctx_t, enum iflib_restart_event); static int bnxt_i2c_req(if_ctx_t ctx, struct ifi2creq *i2c); static void bnxt_get_port_module_status(struct bnxt_softc *softc); static void bnxt_rdma_aux_device_init(struct bnxt_softc *softc); static void bnxt_rdma_aux_device_uninit(struct bnxt_softc *softc); +static void bnxt_queue_fw_reset_work(struct bnxt_softc *bp, unsigned long delay); +void bnxt_queue_sp_work(struct bnxt_softc *bp); +void bnxt_fw_reset(struct bnxt_softc *bp); /* * Device Interface Declaration */ static device_method_t bnxt_methods[] = { /* Device interface */ DEVMETHOD(device_register, bnxt_register), DEVMETHOD(device_probe, iflib_device_probe), DEVMETHOD(device_attach, iflib_device_attach), DEVMETHOD(device_detach, iflib_device_detach), DEVMETHOD(device_shutdown, iflib_device_shutdown), DEVMETHOD(device_suspend, iflib_device_suspend), DEVMETHOD(device_resume, iflib_device_resume), DEVMETHOD_END }; static driver_t bnxt_driver = { "bnxt", bnxt_methods, sizeof(struct bnxt_softc), }; DRIVER_MODULE(bnxt, pci, bnxt_driver, 0, 0); MODULE_LICENSE("Dual BSD/GPL"); MODULE_DEPEND(if_bnxt, pci, 1, 1, 1); MODULE_DEPEND(if_bnxt, ether, 1, 1, 1); MODULE_DEPEND(if_bnxt, iflib, 1, 1, 1); MODULE_DEPEND(if_bnxt, linuxkpi, 1, 1, 1); MODULE_VERSION(if_bnxt, 1); IFLIB_PNP_INFO(pci, bnxt, bnxt_vendor_info_array); +void writel_fbsd(struct bnxt_softc *bp, u32, u8, u32); +u32 readl_fbsd(struct bnxt_softc *bp, u32, u8); + +u32 readl_fbsd(struct bnxt_softc *bp, u32 reg_off, u8 bar_idx) +{ + + if (!bar_idx) + return bus_space_read_4(bp->doorbell_bar.tag, bp->doorbell_bar.handle, reg_off); + else + return bus_space_read_4(bp->hwrm_bar.tag, bp->hwrm_bar.handle, reg_off); +} + +void writel_fbsd(struct bnxt_softc *bp, u32 reg_off, u8 bar_idx, u32 val) +{ + + if (!bar_idx) + bus_space_write_4(bp->doorbell_bar.tag, bp->doorbell_bar.handle, reg_off, htole32(val)); + else + bus_space_write_4(bp->hwrm_bar.tag, bp->hwrm_bar.handle, reg_off, htole32(val)); +} + static DEFINE_IDA(bnxt_aux_dev_ids); static device_method_t bnxt_iflib_methods[] = { DEVMETHOD(ifdi_tx_queues_alloc, bnxt_tx_queues_alloc), DEVMETHOD(ifdi_rx_queues_alloc, bnxt_rx_queues_alloc), DEVMETHOD(ifdi_queues_free, bnxt_queues_free), DEVMETHOD(ifdi_attach_pre, bnxt_attach_pre), DEVMETHOD(ifdi_attach_post, bnxt_attach_post), DEVMETHOD(ifdi_detach, bnxt_detach), DEVMETHOD(ifdi_init, bnxt_init), DEVMETHOD(ifdi_stop, bnxt_stop), DEVMETHOD(ifdi_multi_set, bnxt_multi_set), DEVMETHOD(ifdi_mtu_set, bnxt_mtu_set), DEVMETHOD(ifdi_media_status, bnxt_media_status), DEVMETHOD(ifdi_media_change, bnxt_media_change), DEVMETHOD(ifdi_promisc_set, bnxt_promisc_set), DEVMETHOD(ifdi_get_counter, bnxt_get_counter), DEVMETHOD(ifdi_update_admin_status, bnxt_update_admin_status), DEVMETHOD(ifdi_timer, bnxt_if_timer), DEVMETHOD(ifdi_intr_enable, bnxt_intr_enable), DEVMETHOD(ifdi_tx_queue_intr_enable, bnxt_tx_queue_intr_enable), DEVMETHOD(ifdi_rx_queue_intr_enable, bnxt_rx_queue_intr_enable), DEVMETHOD(ifdi_intr_disable, bnxt_disable_intr), DEVMETHOD(ifdi_msix_intr_assign, bnxt_msix_intr_assign), DEVMETHOD(ifdi_vlan_register, bnxt_vlan_register), DEVMETHOD(ifdi_vlan_unregister, bnxt_vlan_unregister), DEVMETHOD(ifdi_priv_ioctl, bnxt_priv_ioctl), DEVMETHOD(ifdi_suspend, bnxt_suspend), DEVMETHOD(ifdi_shutdown, bnxt_shutdown), DEVMETHOD(ifdi_resume, bnxt_resume), DEVMETHOD(ifdi_i2c_req, bnxt_i2c_req), DEVMETHOD(ifdi_needs_restart, bnxt_if_needs_restart), DEVMETHOD_END }; static driver_t bnxt_iflib_driver = { "bnxt", bnxt_iflib_methods, sizeof(struct bnxt_softc) }; /* * iflib shared context */ #define BNXT_DRIVER_VERSION "2.20.0.1" const char bnxt_driver_version[] = BNXT_DRIVER_VERSION; extern struct if_txrx bnxt_txrx; static struct if_shared_ctx bnxt_sctx_init = { .isc_magic = IFLIB_MAGIC, .isc_driver = &bnxt_iflib_driver, .isc_nfl = 2, // Number of Free Lists .isc_flags = IFLIB_HAS_RXCQ | IFLIB_HAS_TXCQ | IFLIB_NEED_ETHER_PAD, .isc_q_align = PAGE_SIZE, .isc_tx_maxsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), .isc_tx_maxsegsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), .isc_tso_maxsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), .isc_tso_maxsegsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), .isc_rx_maxsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), .isc_rx_maxsegsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), // Only use a single segment to avoid page size constraints .isc_rx_nsegments = 1, .isc_ntxqs = 3, .isc_nrxqs = 3, .isc_nrxd_min = {16, 16, 16}, .isc_nrxd_default = {PAGE_SIZE / sizeof(struct cmpl_base) * 8, PAGE_SIZE / sizeof(struct rx_prod_pkt_bd), PAGE_SIZE / sizeof(struct rx_prod_pkt_bd)}, .isc_nrxd_max = {BNXT_MAX_RXD, BNXT_MAX_RXD, BNXT_MAX_RXD}, .isc_ntxd_min = {16, 16, 16}, .isc_ntxd_default = {PAGE_SIZE / sizeof(struct cmpl_base) * 2, PAGE_SIZE / sizeof(struct tx_bd_short), /* NQ depth 4096 */ PAGE_SIZE / sizeof(struct cmpl_base) * 16}, .isc_ntxd_max = {BNXT_MAX_TXD, BNXT_MAX_TXD, BNXT_MAX_TXD}, .isc_admin_intrcnt = BNXT_ROCE_IRQ_COUNT, .isc_vendor_info = bnxt_vendor_info_array, .isc_driver_version = bnxt_driver_version, }; +#define PCI_SUBSYSTEM_ID 0x2e +static struct workqueue_struct *bnxt_pf_wq; + +extern void bnxt_destroy_irq(struct bnxt_softc *softc); + /* * Device Methods */ static void * bnxt_register(device_t dev) { return (&bnxt_sctx_init); } static void bnxt_nq_alloc(struct bnxt_softc *softc, int nqsets) { if (softc->nq_rings) return; softc->nq_rings = malloc(sizeof(struct bnxt_cp_ring) * nqsets, M_DEVBUF, M_NOWAIT | M_ZERO); } static void bnxt_nq_free(struct bnxt_softc *softc) { if (softc->nq_rings) free(softc->nq_rings, M_DEVBUF); softc->nq_rings = NULL; } /* * Device Dependent Configuration Functions */ /* Soft queue setup and teardown */ static int bnxt_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) { struct bnxt_softc *softc; int i; int rc; softc = iflib_get_softc(ctx); if (BNXT_CHIP_P5(softc)) { bnxt_nq_alloc(softc, ntxqsets); if (!softc->nq_rings) { device_printf(iflib_get_dev(ctx), "unable to allocate NQ rings\n"); rc = ENOMEM; goto nq_alloc_fail; } } softc->tx_cp_rings = malloc(sizeof(struct bnxt_cp_ring) * ntxqsets, M_DEVBUF, M_NOWAIT | M_ZERO); if (!softc->tx_cp_rings) { device_printf(iflib_get_dev(ctx), "unable to allocate TX completion rings\n"); rc = ENOMEM; goto cp_alloc_fail; } softc->tx_rings = malloc(sizeof(struct bnxt_ring) * ntxqsets, M_DEVBUF, M_NOWAIT | M_ZERO); if (!softc->tx_rings) { device_printf(iflib_get_dev(ctx), "unable to allocate TX rings\n"); rc = ENOMEM; goto ring_alloc_fail; } for (i=0; i < ntxqsets; i++) { rc = iflib_dma_alloc(ctx, sizeof(struct ctx_hw_stats), &softc->tx_stats[i], 0); if (rc) goto dma_alloc_fail; bus_dmamap_sync(softc->tx_stats[i].idi_tag, softc->tx_stats[i].idi_map, BUS_DMASYNC_PREREAD); } for (i = 0; i < ntxqsets; i++) { /* Set up the completion ring */ softc->tx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; softc->tx_cp_rings[i].ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->tx_cp_rings[i].ring.softc = softc; softc->tx_cp_rings[i].ring.idx = i; softc->tx_cp_rings[i].ring.id = (softc->scctx->isc_nrxqsets * 2) + 1 + i; softc->tx_cp_rings[i].ring.doorbell = (BNXT_CHIP_P5(softc)) ? DB_PF_OFFSET_P5: softc->tx_cp_rings[i].ring.id * 0x80; softc->tx_cp_rings[i].ring.ring_size = softc->scctx->isc_ntxd[0]; softc->tx_cp_rings[i].ring.vaddr = vaddrs[i * ntxqs]; softc->tx_cp_rings[i].ring.paddr = paddrs[i * ntxqs]; /* Set up the TX ring */ softc->tx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->tx_rings[i].softc = softc; softc->tx_rings[i].idx = i; softc->tx_rings[i].id = (softc->scctx->isc_nrxqsets * 2) + 1 + i; softc->tx_rings[i].doorbell = (BNXT_CHIP_P5(softc)) ? DB_PF_OFFSET_P5 : softc->tx_rings[i].id * 0x80; softc->tx_rings[i].ring_size = softc->scctx->isc_ntxd[1]; softc->tx_rings[i].vaddr = vaddrs[i * ntxqs + 1]; softc->tx_rings[i].paddr = paddrs[i * ntxqs + 1]; bnxt_create_tx_sysctls(softc, i); if (BNXT_CHIP_P5(softc)) { /* Set up the Notification ring (NQ) */ softc->nq_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; softc->nq_rings[i].ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->nq_rings[i].ring.softc = softc; softc->nq_rings[i].ring.idx = i; softc->nq_rings[i].ring.id = i; softc->nq_rings[i].ring.doorbell = (BNXT_CHIP_P5(softc)) ? DB_PF_OFFSET_P5 : softc->nq_rings[i].ring.id * 0x80; softc->nq_rings[i].ring.ring_size = softc->scctx->isc_ntxd[2]; softc->nq_rings[i].ring.vaddr = vaddrs[i * ntxqs + 2]; softc->nq_rings[i].ring.paddr = paddrs[i * ntxqs + 2]; } } softc->ntxqsets = ntxqsets; return rc; dma_alloc_fail: for (i = i - 1; i >= 0; i--) iflib_dma_free(&softc->tx_stats[i]); free(softc->tx_rings, M_DEVBUF); ring_alloc_fail: free(softc->tx_cp_rings, M_DEVBUF); cp_alloc_fail: bnxt_nq_free(softc); nq_alloc_fail: return rc; } static void bnxt_queues_free(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); int i; // Free TX queues for (i=0; intxqsets; i++) iflib_dma_free(&softc->tx_stats[i]); free(softc->tx_rings, M_DEVBUF); softc->tx_rings = NULL; free(softc->tx_cp_rings, M_DEVBUF); softc->tx_cp_rings = NULL; softc->ntxqsets = 0; // Free RX queues for (i=0; inrxqsets; i++) iflib_dma_free(&softc->rx_stats[i]); iflib_dma_free(&softc->hw_tx_port_stats); iflib_dma_free(&softc->hw_rx_port_stats); iflib_dma_free(&softc->hw_tx_port_stats_ext); iflib_dma_free(&softc->hw_rx_port_stats_ext); free(softc->grp_info, M_DEVBUF); free(softc->ag_rings, M_DEVBUF); free(softc->rx_rings, M_DEVBUF); free(softc->rx_cp_rings, M_DEVBUF); bnxt_nq_free(softc); } static int bnxt_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) { struct bnxt_softc *softc; int i; int rc; softc = iflib_get_softc(ctx); softc->rx_cp_rings = malloc(sizeof(struct bnxt_cp_ring) * nrxqsets, M_DEVBUF, M_NOWAIT | M_ZERO); if (!softc->rx_cp_rings) { device_printf(iflib_get_dev(ctx), "unable to allocate RX completion rings\n"); rc = ENOMEM; goto cp_alloc_fail; } softc->rx_rings = malloc(sizeof(struct bnxt_ring) * nrxqsets, M_DEVBUF, M_NOWAIT | M_ZERO); if (!softc->rx_rings) { device_printf(iflib_get_dev(ctx), "unable to allocate RX rings\n"); rc = ENOMEM; goto ring_alloc_fail; } softc->ag_rings = malloc(sizeof(struct bnxt_ring) * nrxqsets, M_DEVBUF, M_NOWAIT | M_ZERO); if (!softc->ag_rings) { device_printf(iflib_get_dev(ctx), "unable to allocate aggregation rings\n"); rc = ENOMEM; goto ag_alloc_fail; } softc->grp_info = malloc(sizeof(struct bnxt_grp_info) * nrxqsets, M_DEVBUF, M_NOWAIT | M_ZERO); if (!softc->grp_info) { device_printf(iflib_get_dev(ctx), "unable to allocate ring groups\n"); rc = ENOMEM; goto grp_alloc_fail; } for (i=0; i < nrxqsets; i++) { rc = iflib_dma_alloc(ctx, sizeof(struct ctx_hw_stats), &softc->rx_stats[i], 0); if (rc) goto hw_stats_alloc_fail; bus_dmamap_sync(softc->rx_stats[i].idi_tag, softc->rx_stats[i].idi_map, BUS_DMASYNC_PREREAD); } /* * Additional 512 bytes for future expansion. * To prevent corruption when loaded with newer firmwares with added counters. * This can be deleted when there will be no further additions of counters. */ #define BNXT_PORT_STAT_PADDING 512 rc = iflib_dma_alloc(ctx, sizeof(struct rx_port_stats) + BNXT_PORT_STAT_PADDING, &softc->hw_rx_port_stats, 0); if (rc) goto hw_port_rx_stats_alloc_fail; bus_dmamap_sync(softc->hw_rx_port_stats.idi_tag, softc->hw_rx_port_stats.idi_map, BUS_DMASYNC_PREREAD); rc = iflib_dma_alloc(ctx, sizeof(struct tx_port_stats) + BNXT_PORT_STAT_PADDING, &softc->hw_tx_port_stats, 0); if (rc) goto hw_port_tx_stats_alloc_fail; bus_dmamap_sync(softc->hw_tx_port_stats.idi_tag, softc->hw_tx_port_stats.idi_map, BUS_DMASYNC_PREREAD); softc->rx_port_stats = (void *) softc->hw_rx_port_stats.idi_vaddr; softc->tx_port_stats = (void *) softc->hw_tx_port_stats.idi_vaddr; rc = iflib_dma_alloc(ctx, sizeof(struct rx_port_stats_ext), &softc->hw_rx_port_stats_ext, 0); if (rc) goto hw_port_rx_stats_ext_alloc_fail; bus_dmamap_sync(softc->hw_rx_port_stats_ext.idi_tag, softc->hw_rx_port_stats_ext.idi_map, BUS_DMASYNC_PREREAD); rc = iflib_dma_alloc(ctx, sizeof(struct tx_port_stats_ext), &softc->hw_tx_port_stats_ext, 0); if (rc) goto hw_port_tx_stats_ext_alloc_fail; bus_dmamap_sync(softc->hw_tx_port_stats_ext.idi_tag, softc->hw_tx_port_stats_ext.idi_map, BUS_DMASYNC_PREREAD); softc->rx_port_stats_ext = (void *) softc->hw_rx_port_stats_ext.idi_vaddr; softc->tx_port_stats_ext = (void *) softc->hw_tx_port_stats_ext.idi_vaddr; for (i = 0; i < nrxqsets; i++) { /* Allocation the completion ring */ softc->rx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; softc->rx_cp_rings[i].ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->rx_cp_rings[i].ring.softc = softc; softc->rx_cp_rings[i].ring.idx = i; softc->rx_cp_rings[i].ring.id = i + 1; softc->rx_cp_rings[i].ring.doorbell = (BNXT_CHIP_P5(softc)) ? DB_PF_OFFSET_P5 : softc->rx_cp_rings[i].ring.id * 0x80; /* * If this ring overflows, RX stops working. */ softc->rx_cp_rings[i].ring.ring_size = softc->scctx->isc_nrxd[0]; softc->rx_cp_rings[i].ring.vaddr = vaddrs[i * nrxqs]; softc->rx_cp_rings[i].ring.paddr = paddrs[i * nrxqs]; /* Allocate the RX ring */ softc->rx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->rx_rings[i].softc = softc; softc->rx_rings[i].idx = i; softc->rx_rings[i].id = i + 1; softc->rx_rings[i].doorbell = (BNXT_CHIP_P5(softc)) ? DB_PF_OFFSET_P5 : softc->rx_rings[i].id * 0x80; softc->rx_rings[i].ring_size = softc->scctx->isc_nrxd[1]; softc->rx_rings[i].vaddr = vaddrs[i * nrxqs + 1]; softc->rx_rings[i].paddr = paddrs[i * nrxqs + 1]; /* Allocate the TPA start buffer */ softc->rx_rings[i].tpa_start = malloc(sizeof(struct bnxt_full_tpa_start) * (RX_TPA_START_CMPL_AGG_ID_MASK >> RX_TPA_START_CMPL_AGG_ID_SFT), M_DEVBUF, M_NOWAIT | M_ZERO); if (softc->rx_rings[i].tpa_start == NULL) { rc = -ENOMEM; device_printf(softc->dev, "Unable to allocate space for TPA\n"); goto tpa_alloc_fail; } - /* Allocate the AG ring */ softc->ag_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->ag_rings[i].softc = softc; softc->ag_rings[i].idx = i; softc->ag_rings[i].id = nrxqsets + i + 1; softc->ag_rings[i].doorbell = (BNXT_CHIP_P5(softc)) ? DB_PF_OFFSET_P5 : softc->ag_rings[i].id * 0x80; softc->ag_rings[i].ring_size = softc->scctx->isc_nrxd[2]; softc->ag_rings[i].vaddr = vaddrs[i * nrxqs + 2]; softc->ag_rings[i].paddr = paddrs[i * nrxqs + 2]; /* Allocate the ring group */ softc->grp_info[i].grp_id = (uint16_t)HWRM_NA_SIGNATURE; softc->grp_info[i].stats_ctx = softc->rx_cp_rings[i].stats_ctx_id; softc->grp_info[i].rx_ring_id = softc->rx_rings[i].phys_id; softc->grp_info[i].ag_ring_id = softc->ag_rings[i].phys_id; softc->grp_info[i].cp_ring_id = softc->rx_cp_rings[i].ring.phys_id; bnxt_create_rx_sysctls(softc, i); } /* * When SR-IOV is enabled, avoid each VF sending PORT_QSTATS * HWRM every sec with which firmware timeouts can happen */ if (BNXT_PF(softc)) bnxt_create_port_stats_sysctls(softc); /* And finally, the VNIC */ softc->vnic_info.id = (uint16_t)HWRM_NA_SIGNATURE; softc->vnic_info.filter_id = -1; softc->vnic_info.def_ring_grp = (uint16_t)HWRM_NA_SIGNATURE; softc->vnic_info.cos_rule = (uint16_t)HWRM_NA_SIGNATURE; softc->vnic_info.lb_rule = (uint16_t)HWRM_NA_SIGNATURE; softc->vnic_info.rx_mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST | HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN; softc->vnic_info.mc_list_count = 0; softc->vnic_info.flags = BNXT_VNIC_FLAG_DEFAULT; rc = iflib_dma_alloc(ctx, BNXT_MAX_MC_ADDRS * ETHER_ADDR_LEN, &softc->vnic_info.mc_list, 0); if (rc) goto mc_list_alloc_fail; /* The VNIC RSS Hash Key */ rc = iflib_dma_alloc(ctx, HW_HASH_KEY_SIZE, &softc->vnic_info.rss_hash_key_tbl, 0); if (rc) goto rss_hash_alloc_fail; bus_dmamap_sync(softc->vnic_info.rss_hash_key_tbl.idi_tag, softc->vnic_info.rss_hash_key_tbl.idi_map, BUS_DMASYNC_PREWRITE); memcpy(softc->vnic_info.rss_hash_key_tbl.idi_vaddr, softc->vnic_info.rss_hash_key, HW_HASH_KEY_SIZE); /* Allocate the RSS tables */ rc = iflib_dma_alloc(ctx, HW_HASH_INDEX_SIZE * sizeof(uint16_t), &softc->vnic_info.rss_grp_tbl, 0); if (rc) goto rss_grp_alloc_fail; bus_dmamap_sync(softc->vnic_info.rss_grp_tbl.idi_tag, softc->vnic_info.rss_grp_tbl.idi_map, BUS_DMASYNC_PREWRITE); memset(softc->vnic_info.rss_grp_tbl.idi_vaddr, 0xff, softc->vnic_info.rss_grp_tbl.idi_size); softc->nrxqsets = nrxqsets; return rc; rss_grp_alloc_fail: iflib_dma_free(&softc->vnic_info.rss_hash_key_tbl); rss_hash_alloc_fail: iflib_dma_free(&softc->vnic_info.mc_list); mc_list_alloc_fail: for (i = i - 1; i >= 0; i--) { if (softc->rx_rings[i].tpa_start) free(softc->rx_rings[i].tpa_start, M_DEVBUF); } tpa_alloc_fail: iflib_dma_free(&softc->hw_tx_port_stats_ext); hw_port_tx_stats_ext_alloc_fail: iflib_dma_free(&softc->hw_rx_port_stats_ext); hw_port_rx_stats_ext_alloc_fail: iflib_dma_free(&softc->hw_tx_port_stats); hw_port_tx_stats_alloc_fail: iflib_dma_free(&softc->hw_rx_port_stats); hw_port_rx_stats_alloc_fail: for (i=0; i < nrxqsets; i++) { if (softc->rx_stats[i].idi_vaddr) iflib_dma_free(&softc->rx_stats[i]); } hw_stats_alloc_fail: free(softc->grp_info, M_DEVBUF); grp_alloc_fail: free(softc->ag_rings, M_DEVBUF); ag_alloc_fail: free(softc->rx_rings, M_DEVBUF); ring_alloc_fail: free(softc->rx_cp_rings, M_DEVBUF); cp_alloc_fail: return rc; } static void bnxt_free_hwrm_short_cmd_req(struct bnxt_softc *softc) { if (softc->hwrm_short_cmd_req_addr.idi_vaddr) iflib_dma_free(&softc->hwrm_short_cmd_req_addr); softc->hwrm_short_cmd_req_addr.idi_vaddr = NULL; } static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt_softc *softc) { int rc; rc = iflib_dma_alloc(softc->ctx, softc->hwrm_max_req_len, &softc->hwrm_short_cmd_req_addr, BUS_DMA_NOWAIT); return rc; } static void bnxt_free_ring(struct bnxt_softc *softc, struct bnxt_ring_mem_info *rmem) { int i; for (i = 0; i < rmem->nr_pages; i++) { if (!rmem->pg_arr[i].idi_vaddr) continue; iflib_dma_free(&rmem->pg_arr[i]); rmem->pg_arr[i].idi_vaddr = NULL; } if (rmem->pg_tbl.idi_vaddr) { iflib_dma_free(&rmem->pg_tbl); rmem->pg_tbl.idi_vaddr = NULL; } if (rmem->vmem_size && *rmem->vmem) { free(*rmem->vmem, M_DEVBUF); *rmem->vmem = NULL; } } static void bnxt_init_ctx_mem(struct bnxt_ctx_mem_type *ctxm, void *p, int len) { u8 init_val = ctxm->init_value; u16 offset = ctxm->init_offset; u8 *p2 = p; int i; if (!init_val) return; if (offset == BNXT_CTX_INIT_INVALID_OFFSET) { memset(p, init_val, len); return; } for (i = 0; i < len; i += ctxm->entry_size) *(p2 + i + offset) = init_val; } static int bnxt_alloc_ring(struct bnxt_softc *softc, struct bnxt_ring_mem_info *rmem) { uint64_t valid_bit = 0; int i; int rc; if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) valid_bit = PTU_PTE_VALID; if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl.idi_vaddr) { size_t pg_tbl_size = rmem->nr_pages * 8; if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) pg_tbl_size = rmem->page_size; rc = iflib_dma_alloc(softc->ctx, pg_tbl_size, &rmem->pg_tbl, 0); if (rc) return -ENOMEM; } for (i = 0; i < rmem->nr_pages; i++) { uint64_t extra_bits = valid_bit; uint64_t *ptr; rc = iflib_dma_alloc(softc->ctx, rmem->page_size, &rmem->pg_arr[i], 0); if (rc) return -ENOMEM; if (rmem->ctx_mem) bnxt_init_ctx_mem(rmem->ctx_mem, rmem->pg_arr[i].idi_vaddr, rmem->page_size); if (rmem->nr_pages > 1 || rmem->depth > 0) { if (i == rmem->nr_pages - 2 && (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) extra_bits |= PTU_PTE_NEXT_TO_LAST; else if (i == rmem->nr_pages - 1 && (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) extra_bits |= PTU_PTE_LAST; ptr = (void *) rmem->pg_tbl.idi_vaddr; ptr[i] = htole64(rmem->pg_arr[i].idi_paddr | extra_bits); } } if (rmem->vmem_size) { *rmem->vmem = malloc(rmem->vmem_size, M_DEVBUF, M_NOWAIT | M_ZERO); if (!(*rmem->vmem)) return -ENOMEM; } return 0; } #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES \ (HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP | \ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ | \ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ | \ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC | \ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) static int bnxt_alloc_ctx_mem_blk(struct bnxt_softc *softc, struct bnxt_ctx_pg_info *ctx_pg) { struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; rmem->page_size = BNXT_PAGE_SIZE; rmem->pg_arr = ctx_pg->ctx_arr; rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; if (rmem->depth >= 1) rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; return bnxt_alloc_ring(softc, rmem); } static int bnxt_alloc_ctx_pg_tbls(struct bnxt_softc *softc, struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, u8 depth, struct bnxt_ctx_mem_type *ctxm) { struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; int rc; if (!mem_size) return -EINVAL; ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { ctx_pg->nr_pages = 0; return -EINVAL; } if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { int nr_tbls, i; rmem->depth = 2; ctx_pg->ctx_pg_tbl = kzalloc(MAX_CTX_PAGES * sizeof(ctx_pg), GFP_KERNEL); if (!ctx_pg->ctx_pg_tbl) return -ENOMEM; nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); rmem->nr_pages = nr_tbls; rc = bnxt_alloc_ctx_mem_blk(softc, ctx_pg); if (rc) return rc; for (i = 0; i < nr_tbls; i++) { struct bnxt_ctx_pg_info *pg_tbl; pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); if (!pg_tbl) return -ENOMEM; ctx_pg->ctx_pg_tbl[i] = pg_tbl; rmem = &pg_tbl->ring_mem; memcpy(&rmem->pg_tbl, &ctx_pg->ctx_arr[i], sizeof(struct iflib_dma_info)); rmem->depth = 1; rmem->nr_pages = MAX_CTX_PAGES; rmem->ctx_mem = ctxm; if (i == (nr_tbls - 1)) { int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; if (rem) rmem->nr_pages = rem; } rc = bnxt_alloc_ctx_mem_blk(softc, pg_tbl); if (rc) break; } } else { rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); if (rmem->nr_pages > 1 || depth) rmem->depth = 1; rmem->ctx_mem = ctxm; rc = bnxt_alloc_ctx_mem_blk(softc, ctx_pg); } return rc; } static void bnxt_free_ctx_pg_tbls(struct bnxt_softc *softc, struct bnxt_ctx_pg_info *ctx_pg) { struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || ctx_pg->ctx_pg_tbl) { int i, nr_tbls = rmem->nr_pages; for (i = 0; i < nr_tbls; i++) { struct bnxt_ctx_pg_info *pg_tbl; struct bnxt_ring_mem_info *rmem2; pg_tbl = ctx_pg->ctx_pg_tbl[i]; if (!pg_tbl) continue; rmem2 = &pg_tbl->ring_mem; bnxt_free_ring(softc, rmem2); ctx_pg->ctx_arr[i].idi_vaddr = NULL; free(pg_tbl , M_DEVBUF); ctx_pg->ctx_pg_tbl[i] = NULL; } kfree(ctx_pg->ctx_pg_tbl); ctx_pg->ctx_pg_tbl = NULL; } bnxt_free_ring(softc, rmem); ctx_pg->nr_pages = 0; } static int bnxt_setup_ctxm_pg_tbls(struct bnxt_softc *softc, struct bnxt_ctx_mem_type *ctxm, u32 entries, u8 pg_lvl) { struct bnxt_ctx_pg_info *ctx_pg = ctxm->pg_info; int i, rc = 0, n = 1; u32 mem_size; if (!ctxm->entry_size || !ctx_pg) return -EINVAL; if (ctxm->instance_bmap) n = hweight32(ctxm->instance_bmap); if (ctxm->entry_multiple) entries = roundup(entries, ctxm->entry_multiple); entries = clamp_t(u32, entries, ctxm->min_entries, ctxm->max_entries); mem_size = entries * ctxm->entry_size; for (i = 0; i < n && !rc; i++) { ctx_pg[i].entries = entries; rc = bnxt_alloc_ctx_pg_tbls(softc, &ctx_pg[i], mem_size, pg_lvl, ctxm->init_value ? ctxm : NULL); } return rc; } static void bnxt_free_ctx_mem(struct bnxt_softc *softc) { struct bnxt_ctx_mem_info *ctx = softc->ctx_mem; u16 type; if (!ctx) return; for (type = 0; type < BNXT_CTX_MAX; type++) { struct bnxt_ctx_mem_type *ctxm = &ctx->ctx_arr[type]; struct bnxt_ctx_pg_info *ctx_pg = ctxm->pg_info; int i, n = 1; if (!ctx_pg) continue; if (ctxm->instance_bmap) n = hweight32(ctxm->instance_bmap); for (i = 0; i < n; i++) bnxt_free_ctx_pg_tbls(softc, &ctx_pg[i]); kfree(ctx_pg); ctxm->pg_info = NULL; } ctx->flags &= ~BNXT_CTX_FLAG_INITED; kfree(ctx); - softc->ctx = NULL; + softc->ctx_mem = NULL; } static int bnxt_alloc_ctx_mem(struct bnxt_softc *softc) { struct bnxt_ctx_pg_info *ctx_pg; struct bnxt_ctx_mem_type *ctxm; struct bnxt_ctx_mem_info *ctx; u32 l2_qps, qp1_qps, max_qps; u32 ena, entries_sp, entries; u32 srqs, max_srqs, min; u32 num_mr, num_ah; u32 extra_srqs = 0; u32 extra_qps = 0; u8 pg_lvl = 1; int i, rc; if (!BNXT_CHIP_P5(softc)) return 0; rc = bnxt_hwrm_func_backing_store_qcaps(softc); if (rc) { device_printf(softc->dev, "Failed querying context mem capability, rc = %d.\n", rc); return rc; } ctx = softc->ctx_mem; if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) return 0; ctxm = &ctx->ctx_arr[BNXT_CTX_QP]; l2_qps = ctxm->qp_l2_entries; qp1_qps = ctxm->qp_qp1_entries; max_qps = ctxm->max_entries; ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ]; srqs = ctxm->srq_l2_entries; max_srqs = ctxm->max_entries; if (softc->flags & BNXT_FLAG_ROCE_CAP) { pg_lvl = 2; extra_qps = min_t(u32, 65536, max_qps - l2_qps - qp1_qps); extra_srqs = min_t(u32, 8192, max_srqs - srqs); } ctxm = &ctx->ctx_arr[BNXT_CTX_QP]; rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, l2_qps + qp1_qps + extra_qps, pg_lvl); if (rc) return rc; ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ]; rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, srqs + extra_srqs, pg_lvl); if (rc) return rc; ctxm = &ctx->ctx_arr[BNXT_CTX_CQ]; rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, ctxm->cq_l2_entries + extra_qps * 2, pg_lvl); if (rc) return rc; ctxm = &ctx->ctx_arr[BNXT_CTX_VNIC]; rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, ctxm->max_entries, 1); if (rc) return rc; ctxm = &ctx->ctx_arr[BNXT_CTX_STAT]; rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, ctxm->max_entries, 1); if (rc) return rc; ena = 0; if (!(softc->flags & BNXT_FLAG_ROCE_CAP)) goto skip_rdma; ctxm = &ctx->ctx_arr[BNXT_CTX_MRAV]; ctx_pg = ctxm->pg_info; /* 128K extra is needed to accomodate static AH context * allocation by f/w. */ num_mr = min_t(u32, ctxm->max_entries / 2, 1024 * 256); num_ah = min_t(u32, num_mr, 1024 * 128); rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, num_mr + num_ah, 2); if (rc) return rc; ctx_pg->entries = num_mr + num_ah; ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV; if (ctxm->mrav_num_entries_units) ctx_pg->entries = ((num_mr / ctxm->mrav_num_entries_units) << 16) | (num_ah / ctxm->mrav_num_entries_units); ctxm = &ctx->ctx_arr[BNXT_CTX_TIM]; rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, l2_qps + qp1_qps + extra_qps, 1); if (rc) return rc; ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM; skip_rdma: ctxm = &ctx->ctx_arr[BNXT_CTX_STQM]; min = ctxm->min_entries; entries_sp = ctx->ctx_arr[BNXT_CTX_VNIC].vnic_entries + l2_qps + 2 * (extra_qps + qp1_qps) + min; rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, entries_sp, 2); if (rc) return rc; ctxm = &ctx->ctx_arr[BNXT_CTX_FTQM]; entries = l2_qps + 2 * (extra_qps + qp1_qps); rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, entries, 2); if (rc) return rc; for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) { if (i < BNXT_MAX_TQM_LEGACY_RINGS) ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; else ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; } ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; rc = bnxt_hwrm_func_backing_store_cfg(softc, ena); if (rc) { device_printf(softc->dev, "Failed configuring context mem, rc = %d.\n", rc); return rc; } ctx->flags |= BNXT_CTX_FLAG_INITED; return 0; } /* * If we update the index, a write barrier is needed after the write to ensure * the completion ring has space before the RX/TX ring does. Since we can't * make the RX and AG doorbells covered by the same barrier without remapping * MSI-X vectors, we create the barrier over the enture doorbell bar. * TODO: Remap the MSI-X vectors to allow a barrier to only cover the doorbells * for a single ring group. * * A barrier of just the size of the write is used to ensure the ordering * remains correct and no writes are lost. */ static void bnxt_cuw_db_rx(void *db_ptr, uint16_t idx) { struct bnxt_ring *ring = (struct bnxt_ring *) db_ptr; struct bnxt_bar_info *db_bar = &ring->softc->doorbell_bar; bus_space_barrier(db_bar->tag, db_bar->handle, ring->doorbell, 4, BUS_SPACE_BARRIER_WRITE); bus_space_write_4(db_bar->tag, db_bar->handle, ring->doorbell, htole32(RX_DOORBELL_KEY_RX | idx)); } static void bnxt_cuw_db_tx(void *db_ptr, uint16_t idx) { struct bnxt_ring *ring = (struct bnxt_ring *) db_ptr; struct bnxt_bar_info *db_bar = &ring->softc->doorbell_bar; bus_space_barrier(db_bar->tag, db_bar->handle, ring->doorbell, 4, BUS_SPACE_BARRIER_WRITE); bus_space_write_4(db_bar->tag, db_bar->handle, ring->doorbell, htole32(TX_DOORBELL_KEY_TX | idx)); } static void bnxt_cuw_db_cq(void *db_ptr, bool enable_irq) { struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 4, BUS_SPACE_BARRIER_WRITE); bus_space_write_4(db_bar->tag, db_bar->handle, cpr->ring.doorbell, htole32(CMPL_DOORBELL_KEY_CMPL | ((cpr->cons == UINT32_MAX) ? 0 : (cpr->cons | CMPL_DOORBELL_IDX_VALID)) | ((enable_irq) ? 0 : CMPL_DOORBELL_MASK))); bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, BUS_SPACE_BARRIER_WRITE); } static void bnxt_thor_db_rx(void *db_ptr, uint16_t idx) { struct bnxt_ring *ring = (struct bnxt_ring *) db_ptr; struct bnxt_bar_info *db_bar = &ring->softc->doorbell_bar; bus_space_barrier(db_bar->tag, db_bar->handle, ring->doorbell, 8, BUS_SPACE_BARRIER_WRITE); bus_space_write_8(db_bar->tag, db_bar->handle, ring->doorbell, htole64((DBR_PATH_L2 | DBR_TYPE_SRQ | idx) | ((uint64_t)ring->phys_id << DBR_XID_SFT))); } static void bnxt_thor_db_tx(void *db_ptr, uint16_t idx) { struct bnxt_ring *ring = (struct bnxt_ring *) db_ptr; struct bnxt_bar_info *db_bar = &ring->softc->doorbell_bar; bus_space_barrier(db_bar->tag, db_bar->handle, ring->doorbell, 8, BUS_SPACE_BARRIER_WRITE); bus_space_write_8(db_bar->tag, db_bar->handle, ring->doorbell, htole64((DBR_PATH_L2 | DBR_TYPE_SQ | idx) | ((uint64_t)ring->phys_id << DBR_XID_SFT))); } static void bnxt_thor_db_rx_cq(void *db_ptr, bool enable_irq) { struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; dbc_dbc_t db_msg = { 0 }; uint32_t cons = cpr->cons; if (cons == UINT32_MAX) cons = 0; else cons = RING_NEXT(&cpr->ring, cons); db_msg.index = ((cons << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK); db_msg.type_path_xid = ((cpr->ring.phys_id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | DBC_DBC_PATH_L2 | ((enable_irq) ? DBC_DBC_TYPE_CQ_ARMALL: DBC_DBC_TYPE_CQ); bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 8, BUS_SPACE_BARRIER_WRITE); bus_space_write_8(db_bar->tag, db_bar->handle, cpr->ring.doorbell, htole64(*(uint64_t *)&db_msg)); bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, BUS_SPACE_BARRIER_WRITE); } static void bnxt_thor_db_tx_cq(void *db_ptr, bool enable_irq) { struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; dbc_dbc_t db_msg = { 0 }; uint32_t cons = cpr->cons; db_msg.index = ((cons << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK); db_msg.type_path_xid = ((cpr->ring.phys_id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | DBC_DBC_PATH_L2 | ((enable_irq) ? DBC_DBC_TYPE_CQ_ARMALL: DBC_DBC_TYPE_CQ); bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 8, BUS_SPACE_BARRIER_WRITE); bus_space_write_8(db_bar->tag, db_bar->handle, cpr->ring.doorbell, htole64(*(uint64_t *)&db_msg)); bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, BUS_SPACE_BARRIER_WRITE); } static void bnxt_thor_db_nq(void *db_ptr, bool enable_irq) { struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; dbc_dbc_t db_msg = { 0 }; uint32_t cons = cpr->cons; db_msg.index = ((cons << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK); db_msg.type_path_xid = ((cpr->ring.phys_id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | DBC_DBC_PATH_L2 | ((enable_irq) ? DBC_DBC_TYPE_NQ_ARM: DBC_DBC_TYPE_NQ); bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 8, BUS_SPACE_BARRIER_WRITE); bus_space_write_8(db_bar->tag, db_bar->handle, cpr->ring.doorbell, htole64(*(uint64_t *)&db_msg)); bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, BUS_SPACE_BARRIER_WRITE); } struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *dev_name) { struct bnxt_softc_list *sc = NULL; SLIST_FOREACH(sc, &pf_list, next) { /* get the softc reference based on device name */ if (dev_name && !strncmp(dev_name, if_name(iflib_get_ifp(sc->softc->ctx)), BNXT_MAX_STR)) { return sc->softc; } /* get the softc reference based on domain,bus,device,function */ if (!dev_name && (domain == sc->softc->domain) && (bus == sc->softc->bus) && (dev_fn == sc->softc->dev_fn)) { return sc->softc; } } return NULL; } static void bnxt_verify_asym_queues(struct bnxt_softc *softc) { uint8_t i, lltc = 0; if (!softc->max_lltc) return; /* Verify that lossless TX and RX queues are in the same index */ for (i = 0; i < softc->max_tc; i++) { if (BNXT_LLQ(softc->tx_q_info[i].queue_profile) && BNXT_LLQ(softc->rx_q_info[i].queue_profile)) lltc++; } softc->max_lltc = min(softc->max_lltc, lltc); } +static int bnxt_hwrm_poll(struct bnxt_softc *bp) +{ + struct hwrm_ver_get_output *resp = + (void *)bp->hwrm_cmd_resp.idi_vaddr; + struct hwrm_ver_get_input req = {0}; + int rc; + + bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET); + + req.hwrm_intf_maj = HWRM_VERSION_MAJOR; + req.hwrm_intf_min = HWRM_VERSION_MINOR; + req.hwrm_intf_upd = HWRM_VERSION_UPDATE; + + rc = _hwrm_send_message(bp, &req, sizeof(req)); + if (rc) + return rc; + + if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) + rc = -EAGAIN; + + return rc; +} + +static void bnxt_rtnl_lock_sp(struct bnxt_softc *bp) +{ + /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK + * set. If the device is being closed, bnxt_close() may be holding + * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we + * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). + */ + clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); + rtnl_lock(); +} + +static void bnxt_rtnl_unlock_sp(struct bnxt_softc *bp) +{ + set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); + rtnl_unlock(); +} + +static void bnxt_fw_fatal_close(struct bnxt_softc *softc) +{ + bnxt_disable_intr(softc->ctx); + if (pci_is_enabled(softc->pdev)) + pci_disable_device(softc->pdev); +} + +static u32 bnxt_fw_health_readl(struct bnxt_softc *bp, int reg_idx) +{ + struct bnxt_fw_health *fw_health = bp->fw_health; + u32 reg = fw_health->regs[reg_idx]; + u32 reg_type, reg_off, val = 0; + + reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); + reg_off = BNXT_FW_HEALTH_REG_OFF(reg); + switch (reg_type) { + case BNXT_FW_HEALTH_REG_TYPE_CFG: + pci_read_config_dword(bp->pdev, reg_off, &val); + break; + case BNXT_FW_HEALTH_REG_TYPE_GRC: + reg_off = fw_health->mapped_regs[reg_idx]; + fallthrough; + case BNXT_FW_HEALTH_REG_TYPE_BAR0: + val = readl_fbsd(bp, reg_off, 0); + break; + case BNXT_FW_HEALTH_REG_TYPE_BAR1: + val = readl_fbsd(bp, reg_off, 2); + break; + } + if (reg_idx == BNXT_FW_RESET_INPROG_REG) + val &= fw_health->fw_reset_inprog_reg_mask; + return val; +} + +static void bnxt_fw_reset_close(struct bnxt_softc *bp) +{ + int i; + bnxt_ulp_stop(bp); + /* When firmware is in fatal state, quiesce device and disable + * bus master to prevent any potential bad DMAs before freeing + * kernel memory. + */ + if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { + u16 val = 0; + + val = pci_read_config(bp->dev, PCI_SUBSYSTEM_ID, 2); + if (val == 0xffff) { + bp->fw_reset_min_dsecs = 0; + } + bnxt_fw_fatal_close(bp); + } + + iflib_request_reset(bp->ctx); + bnxt_stop(bp->ctx); + bnxt_hwrm_func_drv_unrgtr(bp, false); + + for (i = bp->nrxqsets-1; i>=0; i--) { + if (BNXT_CHIP_P5(bp)) + iflib_irq_free(bp->ctx, &bp->nq_rings[i].irq); + else + iflib_irq_free(bp->ctx, &bp->rx_cp_rings[i].irq); + + } + if (pci_is_enabled(bp->pdev)) + pci_disable_device(bp->pdev); + pci_disable_busmaster(bp->dev); + bnxt_free_ctx_mem(bp); +} + +static bool is_bnxt_fw_ok(struct bnxt_softc *bp) +{ + struct bnxt_fw_health *fw_health = bp->fw_health; + bool no_heartbeat = false, has_reset = false; + u32 val; + + val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); + if (val == fw_health->last_fw_heartbeat) + no_heartbeat = true; + + val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); + if (val != fw_health->last_fw_reset_cnt) + has_reset = true; + + if (!no_heartbeat && has_reset) + return true; + + return false; +} + +void bnxt_fw_reset(struct bnxt_softc *bp) +{ + bnxt_rtnl_lock_sp(bp); + if (test_bit(BNXT_STATE_OPEN, &bp->state) && + !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { + int tmo; + set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); + bnxt_fw_reset_close(bp); + + if ((bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD)) { + bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; + tmo = HZ / 10; + } else { + bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; + tmo = bp->fw_reset_min_dsecs * HZ /10; + } + bnxt_queue_fw_reset_work(bp, tmo); + } + bnxt_rtnl_unlock_sp(bp); +} + +static void bnxt_queue_fw_reset_work(struct bnxt_softc *bp, unsigned long delay) +{ + if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))) + return; + + if (BNXT_PF(bp)) + queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); + else + schedule_delayed_work(&bp->fw_reset_task, delay); +} + +void bnxt_queue_sp_work(struct bnxt_softc *bp) +{ + if (BNXT_PF(bp)) + queue_work(bnxt_pf_wq, &bp->sp_task); + else + schedule_work(&bp->sp_task); +} + +static void bnxt_fw_reset_writel(struct bnxt_softc *bp, int reg_idx) +{ + struct bnxt_fw_health *fw_health = bp->fw_health; + u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; + u32 val = fw_health->fw_reset_seq_vals[reg_idx]; + u32 reg_type, reg_off, delay_msecs; + + delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; + reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); + reg_off = BNXT_FW_HEALTH_REG_OFF(reg); + switch (reg_type) { + case BNXT_FW_HEALTH_REG_TYPE_CFG: + pci_write_config_dword(bp->pdev, reg_off, val); + break; + case BNXT_FW_HEALTH_REG_TYPE_GRC: + writel_fbsd(bp, BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4, 0, reg_off & BNXT_GRC_BASE_MASK); + reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; + fallthrough; + case BNXT_FW_HEALTH_REG_TYPE_BAR0: + writel_fbsd(bp, reg_off, 0, val); + break; + case BNXT_FW_HEALTH_REG_TYPE_BAR1: + writel_fbsd(bp, reg_off, 2, val); + break; + } + if (delay_msecs) { + pci_read_config_dword(bp->pdev, 0, &val); + msleep(delay_msecs); + } +} + +static void bnxt_reset_all(struct bnxt_softc *bp) +{ + struct bnxt_fw_health *fw_health = bp->fw_health; + int i, rc; + + if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { + bp->fw_reset_timestamp = jiffies; + return; + } + + if (fw_health->flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST) { + for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) + bnxt_fw_reset_writel(bp, i); + } else if (fw_health->flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU) { + struct hwrm_fw_reset_input req = {0}; + + bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET); + req.target_id = htole16(HWRM_TARGET_ID_KONG); + req.embedded_proc_type = HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP; + req.selfrst_status = HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP; + req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL; + rc = hwrm_send_message(bp, &req, sizeof(req)); + + if (rc != -ENODEV) + device_printf(bp->dev, "Unable to reset FW rc=%d\n", rc); + } + bp->fw_reset_timestamp = jiffies; +} + +static int __bnxt_alloc_fw_health(struct bnxt_softc *bp) +{ + if (bp->fw_health) + return 0; + + bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); + if (!bp->fw_health) + return -ENOMEM; + + mutex_init(&bp->fw_health->lock); + return 0; +} + +static int bnxt_alloc_fw_health(struct bnxt_softc *bp) +{ + int rc; + + if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && + !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) + return 0; + + rc = __bnxt_alloc_fw_health(bp); + if (rc) { + bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; + bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; + return rc; + } + + return 0; +} + +static inline void __bnxt_map_fw_health_reg(struct bnxt_softc *bp, u32 reg) +{ + writel_fbsd(bp, BNXT_GRCPF_REG_WINDOW_BASE_OUT + BNXT_FW_HEALTH_WIN_MAP_OFF, 0, reg & BNXT_GRC_BASE_MASK); +} + +static int bnxt_map_fw_health_regs(struct bnxt_softc *bp) +{ + struct bnxt_fw_health *fw_health = bp->fw_health; + u32 reg_base = 0xffffffff; + int i; + + bp->fw_health->status_reliable = false; + bp->fw_health->resets_reliable = false; + /* Only pre-map the monitoring GRC registers using window 3 */ + for (i = 0; i < 4; i++) { + u32 reg = fw_health->regs[i]; + + if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) + continue; + if (reg_base == 0xffffffff) + reg_base = reg & BNXT_GRC_BASE_MASK; + if ((reg & BNXT_GRC_BASE_MASK) != reg_base) + return -ERANGE; + fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg); + } + bp->fw_health->status_reliable = true; + bp->fw_health->resets_reliable = true; + if (reg_base == 0xffffffff) + return 0; + + __bnxt_map_fw_health_reg(bp, reg_base); + return 0; +} + +static void bnxt_inv_fw_health_reg(struct bnxt_softc *bp) +{ + struct bnxt_fw_health *fw_health = bp->fw_health; + u32 reg_type; + + if (!fw_health) + return; + + reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]); + if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) + fw_health->status_reliable = false; + + reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_RESET_CNT_REG]); + if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) + fw_health->resets_reliable = false; +} + +static int bnxt_hwrm_error_recovery_qcfg(struct bnxt_softc *bp) +{ + struct bnxt_fw_health *fw_health = bp->fw_health; + struct hwrm_error_recovery_qcfg_output *resp = + (void *)bp->hwrm_cmd_resp.idi_vaddr; + struct hwrm_error_recovery_qcfg_input req = {0}; + int rc, i; + + if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) + return 0; + + bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG); + rc = _hwrm_send_message(bp, &req, sizeof(req)); + + if (rc) + goto err_recovery_out; + fw_health->flags = le32toh(resp->flags); + if ((fw_health->flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU) && + !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { + rc = -EINVAL; + goto err_recovery_out; + } + fw_health->polling_dsecs = le32toh(resp->driver_polling_freq); + fw_health->master_func_wait_dsecs = + le32toh(resp->master_func_wait_period); + fw_health->normal_func_wait_dsecs = + le32toh(resp->normal_func_wait_period); + fw_health->post_reset_wait_dsecs = + le32toh(resp->master_func_wait_period_after_reset); + fw_health->post_reset_max_wait_dsecs = + le32toh(resp->max_bailout_time_after_reset); + fw_health->regs[BNXT_FW_HEALTH_REG] = + le32toh(resp->fw_health_status_reg); + fw_health->regs[BNXT_FW_HEARTBEAT_REG] = + le32toh(resp->fw_heartbeat_reg); + fw_health->regs[BNXT_FW_RESET_CNT_REG] = + le32toh(resp->fw_reset_cnt_reg); + fw_health->regs[BNXT_FW_RESET_INPROG_REG] = + le32toh(resp->reset_inprogress_reg); + fw_health->fw_reset_inprog_reg_mask = + le32toh(resp->reset_inprogress_reg_mask); + fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; + if (fw_health->fw_reset_seq_cnt >= 16) { + rc = -EINVAL; + goto err_recovery_out; + } + for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { + fw_health->fw_reset_seq_regs[i] = + le32toh(resp->reset_reg[i]); + fw_health->fw_reset_seq_vals[i] = + le32toh(resp->reset_reg_val[i]); + fw_health->fw_reset_seq_delay_msec[i] = + le32toh(resp->delay_after_reset[i]); + } +err_recovery_out: + if (!rc) + rc = bnxt_map_fw_health_regs(bp); + if (rc) + bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; + return rc; +} + +static int bnxt_drv_rgtr(struct bnxt_softc *bp) +{ + int rc; + + /* determine whether we can support error recovery before + * registering with FW + */ + if (bnxt_alloc_fw_health(bp)) { + device_printf(bp->dev, "no memory for firmware error recovery\n"); + } else { + rc = bnxt_hwrm_error_recovery_qcfg(bp); + if (rc) + device_printf(bp->dev, "hwrm query error recovery failure rc: %d\n", + rc); + } + rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); //sumit dbg: revisit the params + if (rc) + return -ENODEV; + return 0; +} + +static bool bnxt_fw_reset_timeout(struct bnxt_softc *bp) +{ + return time_after(jiffies, bp->fw_reset_timestamp + + (bp->fw_reset_max_dsecs * HZ / 10)); +} + +static int bnxt_open(struct bnxt_softc *bp) +{ + int rc = 0; + if (BNXT_PF(bp)) + rc = bnxt_hwrm_nvm_get_dev_info(bp, &bp->nvm_info->mfg_id, + &bp->nvm_info->device_id, &bp->nvm_info->sector_size, + &bp->nvm_info->size, &bp->nvm_info->reserved_size, + &bp->nvm_info->available_size); + + /* Get the queue config */ + rc = bnxt_hwrm_queue_qportcfg(bp, HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX); + if (rc) { + device_printf(bp->dev, "reinit: hwrm qportcfg (tx) failed\n"); + return rc; + } + if (bp->is_asym_q) { + rc = bnxt_hwrm_queue_qportcfg(bp, + HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX); + if (rc) { + device_printf(bp->dev, "re-init: hwrm qportcfg (rx) failed\n"); + return rc; + } + bnxt_verify_asym_queues(bp); + } else { + bp->rx_max_q = bp->tx_max_q; + memcpy(bp->rx_q_info, bp->tx_q_info, sizeof(bp->rx_q_info)); + memcpy(bp->rx_q_ids, bp->tx_q_ids, sizeof(bp->rx_q_ids)); + } + /* Get the HW capabilities */ + rc = bnxt_hwrm_func_qcaps(bp); + if (rc) + return rc; + + /* Register the driver with the FW */ + rc = bnxt_drv_rgtr(bp); + if (rc) + return rc; + if (bp->hwrm_spec_code >= 0x10803) { + rc = bnxt_alloc_ctx_mem(bp); + if (rc) { + device_printf(bp->dev, "attach: alloc_ctx_mem failed\n"); + return rc; + } + rc = bnxt_hwrm_func_resc_qcaps(bp, true); + if (!rc) + bp->flags |= BNXT_FLAG_FW_CAP_NEW_RM; + } + + if (BNXT_CHIP_P5(bp)) + bnxt_hwrm_reserve_pf_rings(bp); + /* Get the current configuration of this function */ + rc = bnxt_hwrm_func_qcfg(bp); + if (rc) { + device_printf(bp->dev, "re-init: hwrm func qcfg failed\n"); + return rc; + } + + bnxt_msix_intr_assign(bp->ctx, 0); + bnxt_init(bp->ctx); + bnxt_intr_enable(bp->ctx); + + if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { + if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { + bnxt_ulp_start(bp, 0); + } + } + + device_printf(bp->dev, "Network interface is UP and operational\n"); + + return rc; +} +static void bnxt_fw_reset_abort(struct bnxt_softc *bp, int rc) +{ + clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); + if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) { + bnxt_ulp_start(bp, rc); + } + bp->fw_reset_state = 0; +} + +static void bnxt_fw_reset_task(struct work_struct *work) +{ + struct bnxt_softc *bp = container_of(work, struct bnxt_softc, fw_reset_task.work); + int rc = 0; + + if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { + device_printf(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); + return; + } + + switch (bp->fw_reset_state) { + case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { + u32 val; + + val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); + if (!(val & BNXT_FW_STATUS_SHUTDOWN) && + !bnxt_fw_reset_timeout(bp)) { + bnxt_queue_fw_reset_work(bp, HZ / 5); + return; + } + + if (!bp->fw_health->primary) { + u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; + + bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; + bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); + return; + } + bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; + } + fallthrough; + case BNXT_FW_RESET_STATE_RESET_FW: + bnxt_reset_all(bp); + bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; + bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); + return; + case BNXT_FW_RESET_STATE_ENABLE_DEV: + bnxt_inv_fw_health_reg(bp); + if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) && + !bp->fw_reset_min_dsecs) { + u16 val; + + val = pci_read_config(bp->dev, PCI_SUBSYSTEM_ID, 2); + if (val == 0xffff) { + if (bnxt_fw_reset_timeout(bp)) { + device_printf(bp->dev, "Firmware reset aborted, PCI config space invalid\n"); + rc = -ETIMEDOUT; + goto fw_reset_abort; + } + bnxt_queue_fw_reset_work(bp, HZ / 1000); + return; + } + } + clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); + clear_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state); + if (!pci_is_enabled(bp->pdev)) { + if (pci_enable_device(bp->pdev)) { + device_printf(bp->dev, "Cannot re-enable PCI device\n"); + rc = -ENODEV; + goto fw_reset_abort; + } + } + pci_set_master(bp->pdev); + bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; + fallthrough; + case BNXT_FW_RESET_STATE_POLL_FW: + bp->hwrm_cmd_timeo = SHORT_HWRM_CMD_TIMEOUT; + rc = bnxt_hwrm_poll(bp); + if (rc) { + if (bnxt_fw_reset_timeout(bp)) { + device_printf(bp->dev, "Firmware reset aborted\n"); + goto fw_reset_abort_status; + } + bnxt_queue_fw_reset_work(bp, HZ / 5); + return; + } + bp->hwrm_cmd_timeo = DFLT_HWRM_CMD_TIMEOUT; + bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; + fallthrough; + case BNXT_FW_RESET_STATE_OPENING: + rc = bnxt_open(bp); + if (rc) { + device_printf(bp->dev, "bnxt_open() failed during FW reset\n"); + bnxt_fw_reset_abort(bp, rc); + rtnl_unlock(); + return; + } + + if ((bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) && + bp->fw_health->enabled) { + bp->fw_health->last_fw_reset_cnt = + bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); + } + bp->fw_reset_state = 0; + smp_mb__before_atomic(); + clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); + bnxt_ulp_start(bp, 0); + clear_bit(BNXT_STATE_FW_ACTIVATE, &bp->state); + set_bit(BNXT_STATE_OPEN, &bp->state); + rtnl_unlock(); + } + return; + +fw_reset_abort_status: + if (bp->fw_health->status_reliable || + (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) { + u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); + + device_printf(bp->dev, "fw_health_status 0x%x\n", sts); + } +fw_reset_abort: + rtnl_lock(); + bnxt_fw_reset_abort(bp, rc); + rtnl_unlock(); +} + +static void bnxt_force_fw_reset(struct bnxt_softc *bp) +{ + struct bnxt_fw_health *fw_health = bp->fw_health; + u32 wait_dsecs; + + if (!test_bit(BNXT_STATE_OPEN, &bp->state) || + test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) + return; + bnxt_fw_reset_close(bp); + wait_dsecs = fw_health->master_func_wait_dsecs; + if (fw_health->primary) { + if (fw_health->flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU) + wait_dsecs = 0; + bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; + } else { + bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; + wait_dsecs = fw_health->normal_func_wait_dsecs; + bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; + } + + bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; + bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; + bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); +} + +static void bnxt_fw_exception(struct bnxt_softc *bp) +{ + device_printf(bp->dev, "Detected firmware fatal condition, initiating reset\n"); + set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); + bnxt_rtnl_lock_sp(bp); + bnxt_force_fw_reset(bp); + bnxt_rtnl_unlock_sp(bp); +} + +static void __bnxt_fw_recover(struct bnxt_softc *bp) +{ + if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) || + test_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state)) + bnxt_fw_reset(bp); + else + bnxt_fw_exception(bp); +} + +static void bnxt_devlink_health_fw_report(struct bnxt_softc *bp) +{ + struct bnxt_fw_health *fw_health = bp->fw_health; + + if (!fw_health) + return; + + if (!fw_health->fw_reporter) { + __bnxt_fw_recover(bp); + return; + } +} + +static void bnxt_sp_task(struct work_struct *work) +{ + struct bnxt_softc *bp = container_of(work, struct bnxt_softc, sp_task); + + set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); + smp_mb__after_atomic(); + if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { + clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); + return; + } + + if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) { + if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) || + test_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state)) + bnxt_devlink_health_fw_report(bp); + else + bnxt_fw_reset(bp); + } + + if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { + if (!is_bnxt_fw_ok(bp)) + bnxt_devlink_health_fw_report(bp); + } + smp_mb__before_atomic(); + clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); +} + /* Device setup and teardown */ static int bnxt_attach_pre(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); if_softc_ctx_t scctx; int rc = 0; softc->ctx = ctx; softc->dev = iflib_get_dev(ctx); softc->media = iflib_get_media(ctx); softc->scctx = iflib_get_softc_ctx(ctx); softc->sctx = iflib_get_sctx(ctx); scctx = softc->scctx; /* TODO: Better way of detecting NPAR/VF is needed */ switch (pci_get_device(softc->dev)) { case BCM57402_NPAR: case BCM57404_NPAR: case BCM57406_NPAR: case BCM57407_NPAR: case BCM57412_NPAR1: case BCM57412_NPAR2: case BCM57414_NPAR1: case BCM57414_NPAR2: case BCM57416_NPAR1: case BCM57416_NPAR2: softc->flags |= BNXT_FLAG_NPAR; break; case NETXTREME_C_VF1: case NETXTREME_C_VF2: case NETXTREME_C_VF3: case NETXTREME_E_VF1: case NETXTREME_E_VF2: case NETXTREME_E_VF3: softc->flags |= BNXT_FLAG_VF; break; } softc->domain = pci_get_domain(softc->dev); softc->bus = pci_get_bus(softc->dev); softc->slot = pci_get_slot(softc->dev); softc->function = pci_get_function(softc->dev); softc->dev_fn = PCI_DEVFN(softc->slot, softc->function); if (bnxt_num_pfs == 0) SLIST_INIT(&pf_list); bnxt_num_pfs++; softc->list.softc = softc; SLIST_INSERT_HEAD(&pf_list, &softc->list, next); pci_enable_busmaster(softc->dev); if (bnxt_pci_mapping(softc)) { device_printf(softc->dev, "PCI mapping failed\n"); rc = ENXIO; goto pci_map_fail; } softc->pdev = kzalloc(sizeof(*softc->pdev), GFP_KERNEL); if (!softc->pdev) { device_printf(softc->dev, "pdev alloc failed\n"); rc = -ENOMEM; goto free_pci_map; } rc = linux_pci_attach_device(softc->dev, NULL, NULL, softc->pdev); if (rc) { device_printf(softc->dev, "Failed to attach Linux PCI device 0x%x\n", rc); goto pci_attach_fail; } /* HWRM setup/init */ BNXT_HWRM_LOCK_INIT(softc, device_get_nameunit(softc->dev)); rc = bnxt_alloc_hwrm_dma_mem(softc); if (rc) goto dma_fail; /* Get firmware version and compare with driver */ softc->ver_info = malloc(sizeof(struct bnxt_ver_info), M_DEVBUF, M_NOWAIT | M_ZERO); if (softc->ver_info == NULL) { rc = ENOMEM; device_printf(softc->dev, "Unable to allocate space for version info\n"); goto ver_alloc_fail; } /* Default minimum required HWRM version */ softc->ver_info->hwrm_min_major = HWRM_VERSION_MAJOR; softc->ver_info->hwrm_min_minor = HWRM_VERSION_MINOR; softc->ver_info->hwrm_min_update = HWRM_VERSION_UPDATE; rc = bnxt_hwrm_ver_get(softc); if (rc) { device_printf(softc->dev, "attach: hwrm ver get failed\n"); goto ver_fail; } /* Now perform a function reset */ rc = bnxt_hwrm_func_reset(softc); if ((softc->flags & BNXT_FLAG_SHORT_CMD) || softc->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { rc = bnxt_alloc_hwrm_short_cmd_req(softc); if (rc) goto hwrm_short_cmd_alloc_fail; } if ((softc->ver_info->chip_num == BCM57508) || (softc->ver_info->chip_num == BCM57504) || (softc->ver_info->chip_num == BCM57502)) softc->flags |= BNXT_FLAG_CHIP_P5; softc->flags |= BNXT_FLAG_TPA; if (BNXT_CHIP_P5(softc) && (!softc->ver_info->chip_rev) && (!softc->ver_info->chip_metal)) softc->flags &= ~BNXT_FLAG_TPA; if (BNXT_CHIP_P5(softc)) softc->flags &= ~BNXT_FLAG_TPA; /* Get NVRAM info */ if (BNXT_PF(softc)) { + if (!bnxt_pf_wq) { + bnxt_pf_wq = + create_singlethread_workqueue("bnxt_pf_wq"); + if (!bnxt_pf_wq) { + device_printf(softc->dev, "Unable to create workqueue.\n"); + rc = -ENOMEM; + goto nvm_alloc_fail; + } + } + softc->nvm_info = malloc(sizeof(struct bnxt_nvram_info), M_DEVBUF, M_NOWAIT | M_ZERO); if (softc->nvm_info == NULL) { rc = ENOMEM; device_printf(softc->dev, "Unable to allocate space for NVRAM info\n"); goto nvm_alloc_fail; } rc = bnxt_hwrm_nvm_get_dev_info(softc, &softc->nvm_info->mfg_id, &softc->nvm_info->device_id, &softc->nvm_info->sector_size, &softc->nvm_info->size, &softc->nvm_info->reserved_size, &softc->nvm_info->available_size); } if (BNXT_CHIP_P5(softc)) { softc->db_ops.bnxt_db_tx = bnxt_thor_db_tx; softc->db_ops.bnxt_db_rx = bnxt_thor_db_rx; softc->db_ops.bnxt_db_rx_cq = bnxt_thor_db_rx_cq; softc->db_ops.bnxt_db_tx_cq = bnxt_thor_db_tx_cq; softc->db_ops.bnxt_db_nq = bnxt_thor_db_nq; } else { softc->db_ops.bnxt_db_tx = bnxt_cuw_db_tx; softc->db_ops.bnxt_db_rx = bnxt_cuw_db_rx; softc->db_ops.bnxt_db_rx_cq = bnxt_cuw_db_cq; softc->db_ops.bnxt_db_tx_cq = bnxt_cuw_db_cq; } - /* Register the driver with the FW */ - rc = bnxt_hwrm_func_drv_rgtr(softc); - if (rc) { - device_printf(softc->dev, "attach: hwrm drv rgtr failed\n"); - goto drv_rgtr_fail; - } - - rc = bnxt_hwrm_func_rgtr_async_events(softc, NULL, 0); - if (rc) { - device_printf(softc->dev, "attach: hwrm rgtr async evts failed\n"); - goto drv_rgtr_fail; - } /* Get the queue config */ rc = bnxt_hwrm_queue_qportcfg(softc, HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX); if (rc) { device_printf(softc->dev, "attach: hwrm qportcfg (tx) failed\n"); goto failed; } if (softc->is_asym_q) { rc = bnxt_hwrm_queue_qportcfg(softc, HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX); if (rc) { device_printf(softc->dev, "attach: hwrm qportcfg (rx) failed\n"); return rc; } bnxt_verify_asym_queues(softc); } else { softc->rx_max_q = softc->tx_max_q; memcpy(softc->rx_q_info, softc->tx_q_info, sizeof(softc->rx_q_info)); memcpy(softc->rx_q_ids, softc->tx_q_ids, sizeof(softc->rx_q_ids)); } /* Get the HW capabilities */ rc = bnxt_hwrm_func_qcaps(softc); if (rc) goto failed; + /* + * Register the driver with the FW + * Register the async events with the FW + */ + rc = bnxt_drv_rgtr(softc); + if (rc) + goto failed; + if (softc->hwrm_spec_code >= 0x10803) { rc = bnxt_alloc_ctx_mem(softc); if (rc) { device_printf(softc->dev, "attach: alloc_ctx_mem failed\n"); return rc; } rc = bnxt_hwrm_func_resc_qcaps(softc, true); if (!rc) softc->flags |= BNXT_FLAG_FW_CAP_NEW_RM; } /* Get the current configuration of this function */ rc = bnxt_hwrm_func_qcfg(softc); if (rc) { device_printf(softc->dev, "attach: hwrm func qcfg failed\n"); goto failed; } iflib_set_mac(ctx, softc->func.mac_addr); scctx->isc_txrx = &bnxt_txrx; scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_TSO); scctx->isc_capabilities = scctx->isc_capenable = /* These are translated to hwassit bits */ IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6 | IFCAP_TSO4 | IFCAP_TSO6 | /* These are checked by iflib */ IFCAP_LRO | IFCAP_VLAN_HWFILTER | /* These are part of the iflib mask */ IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6 | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | /* These likely get lost... */ IFCAP_VLAN_HWCSUM | IFCAP_JUMBO_MTU; if (bnxt_wol_supported(softc)) scctx->isc_capabilities |= IFCAP_WOL_MAGIC; bnxt_get_wol_settings(softc); if (softc->wol) scctx->isc_capenable |= IFCAP_WOL_MAGIC; /* Get the queue config */ bnxt_get_wol_settings(softc); if (BNXT_CHIP_P5(softc)) bnxt_hwrm_reserve_pf_rings(softc); rc = bnxt_hwrm_func_qcfg(softc); if (rc) { device_printf(softc->dev, "attach: hwrm func qcfg failed\n"); goto failed; } bnxt_clear_ids(softc); if (rc) goto failed; /* Now set up iflib sc */ scctx->isc_tx_nsegments = 31, scctx->isc_tx_tso_segments_max = 31; scctx->isc_tx_tso_size_max = BNXT_TSO_SIZE; scctx->isc_tx_tso_segsize_max = BNXT_TSO_SIZE; scctx->isc_vectors = softc->func.max_cp_rings; scctx->isc_min_frame_size = BNXT_MIN_FRAME_SIZE; scctx->isc_txrx = &bnxt_txrx; if (scctx->isc_nrxd[0] < ((scctx->isc_nrxd[1] * 4) + scctx->isc_nrxd[2])) device_printf(softc->dev, "WARNING: nrxd0 (%d) should be at least 4 * nrxd1 (%d) + nrxd2 (%d). Driver may be unstable\n", scctx->isc_nrxd[0], scctx->isc_nrxd[1], scctx->isc_nrxd[2]); if (scctx->isc_ntxd[0] < scctx->isc_ntxd[1] * 2) device_printf(softc->dev, "WARNING: ntxd0 (%d) should be at least 2 * ntxd1 (%d). Driver may be unstable\n", scctx->isc_ntxd[0], scctx->isc_ntxd[1]); scctx->isc_txqsizes[0] = sizeof(struct cmpl_base) * scctx->isc_ntxd[0]; scctx->isc_txqsizes[1] = sizeof(struct tx_bd_short) * scctx->isc_ntxd[1]; scctx->isc_txqsizes[2] = sizeof(struct cmpl_base) * scctx->isc_ntxd[2]; scctx->isc_rxqsizes[0] = sizeof(struct cmpl_base) * scctx->isc_nrxd[0]; scctx->isc_rxqsizes[1] = sizeof(struct rx_prod_pkt_bd) * scctx->isc_nrxd[1]; scctx->isc_rxqsizes[2] = sizeof(struct rx_prod_pkt_bd) * scctx->isc_nrxd[2]; scctx->isc_nrxqsets_max = min(pci_msix_count(softc->dev)-1, softc->fn_qcfg.alloc_completion_rings - 1); scctx->isc_nrxqsets_max = min(scctx->isc_nrxqsets_max, softc->fn_qcfg.alloc_rx_rings); scctx->isc_nrxqsets_max = min(scctx->isc_nrxqsets_max, softc->fn_qcfg.alloc_vnics); scctx->isc_ntxqsets_max = min(softc->fn_qcfg.alloc_tx_rings, softc->fn_qcfg.alloc_completion_rings - scctx->isc_nrxqsets_max - 1); scctx->isc_rss_table_size = HW_HASH_INDEX_SIZE; scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1; /* iflib will map and release this bar */ scctx->isc_msix_bar = pci_msix_table_bar(softc->dev); /* * Default settings for HW LRO (TPA): * Disable HW LRO by default * Can be enabled after taking care of 'packet forwarding' */ if (softc->flags & BNXT_FLAG_TPA) { softc->hw_lro.enable = 0; softc->hw_lro.is_mode_gro = 0; softc->hw_lro.max_agg_segs = 5; /* 2^5 = 32 segs */ softc->hw_lro.max_aggs = HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX; softc->hw_lro.min_agg_len = 512; } /* Allocate the default completion ring */ softc->def_cp_ring.stats_ctx_id = HWRM_NA_SIGNATURE; softc->def_cp_ring.ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->def_cp_ring.ring.softc = softc; softc->def_cp_ring.ring.id = 0; softc->def_cp_ring.ring.doorbell = (BNXT_CHIP_P5(softc)) ? DB_PF_OFFSET_P5 : softc->def_cp_ring.ring.id * 0x80; softc->def_cp_ring.ring.ring_size = PAGE_SIZE / sizeof(struct cmpl_base); rc = iflib_dma_alloc(ctx, sizeof(struct cmpl_base) * softc->def_cp_ring.ring.ring_size, &softc->def_cp_ring_mem, 0); softc->def_cp_ring.ring.vaddr = softc->def_cp_ring_mem.idi_vaddr; softc->def_cp_ring.ring.paddr = softc->def_cp_ring_mem.idi_paddr; iflib_config_gtask_init(ctx, &softc->def_cp_task, bnxt_def_cp_task, "dflt_cp"); rc = bnxt_init_sysctl_ctx(softc); if (rc) goto init_sysctl_failed; if (BNXT_PF(softc)) { rc = bnxt_create_nvram_sysctls(softc->nvm_info); if (rc) goto failed; } arc4rand(softc->vnic_info.rss_hash_key, HW_HASH_KEY_SIZE, 0); softc->vnic_info.rss_hash_type = HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 | HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 | HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 | HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 | HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 | HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; rc = bnxt_create_config_sysctls_pre(softc); if (rc) goto failed; rc = bnxt_create_hw_lro_sysctls(softc); if (rc) goto failed; rc = bnxt_create_pause_fc_sysctls(softc); if (rc) goto failed; rc = bnxt_create_dcb_sysctls(softc); if (rc) goto failed; + set_bit(BNXT_STATE_OPEN, &softc->state); + INIT_WORK(&softc->sp_task, bnxt_sp_task); + INIT_DELAYED_WORK(&softc->fw_reset_task, bnxt_fw_reset_task); + /* Initialize the vlan list */ SLIST_INIT(&softc->vnic_info.vlan_tags); softc->vnic_info.vlan_tag_list.idi_vaddr = NULL; softc->state_bv = bit_alloc(BNXT_STATE_MAX, M_DEVBUF, M_WAITOK|M_ZERO); return (rc); failed: bnxt_free_sysctl_ctx(softc); init_sysctl_failed: bnxt_hwrm_func_drv_unrgtr(softc, false); -drv_rgtr_fail: if (BNXT_PF(softc)) free(softc->nvm_info, M_DEVBUF); nvm_alloc_fail: bnxt_free_hwrm_short_cmd_req(softc); hwrm_short_cmd_alloc_fail: ver_fail: free(softc->ver_info, M_DEVBUF); ver_alloc_fail: bnxt_free_hwrm_dma_mem(softc); dma_fail: BNXT_HWRM_LOCK_DESTROY(softc); if (softc->pdev) linux_pci_detach_device(softc->pdev); pci_attach_fail: kfree(softc->pdev); softc->pdev = NULL; free_pci_map: bnxt_pci_mapping_free(softc); pci_map_fail: pci_disable_busmaster(softc->dev); return (rc); } static int bnxt_attach_post(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); if_t ifp = iflib_get_ifp(ctx); int rc; softc->ifp = ifp; bnxt_create_config_sysctls_post(softc); /* Update link state etc... */ rc = bnxt_probe_phy(softc); if (rc) goto failed; /* Needs to be done after probing the phy */ bnxt_create_ver_sysctls(softc); ifmedia_removeall(softc->media); bnxt_add_media_types(softc); ifmedia_set(softc->media, IFM_ETHER | IFM_AUTO); softc->scctx->isc_max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN; softc->rx_buf_size = min(softc->scctx->isc_max_frame_size, BNXT_PAGE_SIZE); bnxt_dcb_init(softc); bnxt_rdma_aux_device_init(softc); failed: return rc; } static int bnxt_detach(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); struct bnxt_vlan_tag *tag; struct bnxt_vlan_tag *tmp; int i; bnxt_rdma_aux_device_uninit(softc); + cancel_delayed_work_sync(&softc->fw_reset_task); + cancel_work_sync(&softc->sp_task); bnxt_dcb_free(softc); SLIST_REMOVE(&pf_list, &softc->list, bnxt_softc_list, next); bnxt_num_pfs--; bnxt_wol_config(ctx); bnxt_do_disable_intr(&softc->def_cp_ring); bnxt_free_sysctl_ctx(softc); bnxt_hwrm_func_reset(softc); bnxt_free_ctx_mem(softc); bnxt_clear_ids(softc); iflib_irq_free(ctx, &softc->def_cp_ring.irq); iflib_config_gtask_deinit(&softc->def_cp_task); /* We need to free() these here... */ for (i = softc->nrxqsets-1; i>=0; i--) { if (BNXT_CHIP_P5(softc)) iflib_irq_free(ctx, &softc->nq_rings[i].irq); else iflib_irq_free(ctx, &softc->rx_cp_rings[i].irq); } iflib_dma_free(&softc->vnic_info.mc_list); iflib_dma_free(&softc->vnic_info.rss_hash_key_tbl); iflib_dma_free(&softc->vnic_info.rss_grp_tbl); if (softc->vnic_info.vlan_tag_list.idi_vaddr) iflib_dma_free(&softc->vnic_info.vlan_tag_list); SLIST_FOREACH_SAFE(tag, &softc->vnic_info.vlan_tags, next, tmp) free(tag, M_DEVBUF); iflib_dma_free(&softc->def_cp_ring_mem); for (i = 0; i < softc->nrxqsets; i++) free(softc->rx_rings[i].tpa_start, M_DEVBUF); free(softc->ver_info, M_DEVBUF); if (BNXT_PF(softc)) free(softc->nvm_info, M_DEVBUF); bnxt_hwrm_func_drv_unrgtr(softc, false); bnxt_free_hwrm_dma_mem(softc); bnxt_free_hwrm_short_cmd_req(softc); BNXT_HWRM_LOCK_DESTROY(softc); + if (!bnxt_num_pfs && bnxt_pf_wq) + destroy_workqueue(bnxt_pf_wq); + if (softc->pdev) linux_pci_detach_device(softc->pdev); free(softc->state_bv, M_DEVBUF); pci_disable_busmaster(softc->dev); bnxt_pci_mapping_free(softc); return 0; } static void bnxt_hwrm_resource_free(struct bnxt_softc *softc) { int i, rc = 0; rc = bnxt_hwrm_ring_free(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, &softc->def_cp_ring.ring, (uint16_t)HWRM_NA_SIGNATURE); if (rc) goto fail; for (i = 0; i < softc->ntxqsets; i++) { rc = bnxt_hwrm_ring_free(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_TX, &softc->tx_rings[i], softc->tx_cp_rings[i].ring.phys_id); if (rc) goto fail; rc = bnxt_hwrm_ring_free(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, &softc->tx_cp_rings[i].ring, (uint16_t)HWRM_NA_SIGNATURE); if (rc) goto fail; rc = bnxt_hwrm_stat_ctx_free(softc, &softc->tx_cp_rings[i]); if (rc) goto fail; } rc = bnxt_hwrm_free_filter(softc); if (rc) goto fail; rc = bnxt_hwrm_vnic_free(softc, &softc->vnic_info); if (rc) goto fail; rc = bnxt_hwrm_vnic_ctx_free(softc, softc->vnic_info.rss_id); if (rc) goto fail; for (i = 0; i < softc->nrxqsets; i++) { rc = bnxt_hwrm_ring_grp_free(softc, &softc->grp_info[i]); if (rc) goto fail; rc = bnxt_hwrm_ring_free(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG, &softc->ag_rings[i], (uint16_t)HWRM_NA_SIGNATURE); if (rc) goto fail; rc = bnxt_hwrm_ring_free(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_RX, &softc->rx_rings[i], softc->rx_cp_rings[i].ring.phys_id); if (rc) goto fail; rc = bnxt_hwrm_ring_free(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, &softc->rx_cp_rings[i].ring, (uint16_t)HWRM_NA_SIGNATURE); if (rc) goto fail; if (BNXT_CHIP_P5(softc)) { rc = bnxt_hwrm_ring_free(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ, &softc->nq_rings[i].ring, (uint16_t)HWRM_NA_SIGNATURE); if (rc) goto fail; } rc = bnxt_hwrm_stat_ctx_free(softc, &softc->rx_cp_rings[i]); if (rc) goto fail; } fail: return; } static void bnxt_func_reset(struct bnxt_softc *softc) { if (!BNXT_CHIP_P5(softc)) { bnxt_hwrm_func_reset(softc); return; } bnxt_hwrm_resource_free(softc); return; } static void bnxt_rss_grp_tbl_init(struct bnxt_softc *softc) { uint16_t *rgt = (uint16_t *) softc->vnic_info.rss_grp_tbl.idi_vaddr; int i, j; for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) { if (BNXT_CHIP_P5(softc)) { rgt[i++] = htole16(softc->rx_rings[j].phys_id); rgt[i] = htole16(softc->rx_cp_rings[j].ring.phys_id); } else { rgt[i] = htole16(softc->grp_info[j].grp_id); } if (++j == softc->nrxqsets) j = 0; } } static void bnxt_get_port_module_status(struct bnxt_softc *softc) { struct bnxt_link_info *link_info = &softc->link_info; struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; uint8_t module_status; if (bnxt_update_link(softc, false)) return; module_status = link_info->module_status; switch (module_status) { case HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX: case HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN: case HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG: device_printf(softc->dev, "Unqualified SFP+ module detected on port %d\n", softc->pf.port_id); if (softc->hwrm_spec_code >= 0x10201) { device_printf(softc->dev, "Module part number %s\n", resp->phy_vendor_partnumber); } if (module_status == HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX) device_printf(softc->dev, "TX is disabled\n"); if (module_status == HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN) device_printf(softc->dev, "SFP+ module is shutdown\n"); } } static void bnxt_aux_dev_free(struct bnxt_softc *softc) { kfree(softc->aux_dev); softc->aux_dev = NULL; } static struct bnxt_aux_dev *bnxt_aux_dev_init(struct bnxt_softc *softc) { struct bnxt_aux_dev *bnxt_adev; msleep(1000 * 2); bnxt_adev = kzalloc(sizeof(*bnxt_adev), GFP_KERNEL); if (!bnxt_adev) return ERR_PTR(-ENOMEM); return bnxt_adev; } static void bnxt_rdma_aux_device_uninit(struct bnxt_softc *softc) { struct bnxt_aux_dev *bnxt_adev = softc->aux_dev; /* Skip if no auxiliary device init was done. */ if (!(softc->flags & BNXT_FLAG_ROCE_CAP)) return; if (IS_ERR_OR_NULL(bnxt_adev)) return; bnxt_rdma_aux_device_del(softc); if (bnxt_adev->id >= 0) ida_free(&bnxt_aux_dev_ids, bnxt_adev->id); bnxt_aux_dev_free(softc); } static void bnxt_rdma_aux_device_init(struct bnxt_softc *softc) { int rc; if (!(softc->flags & BNXT_FLAG_ROCE_CAP)) return; softc->aux_dev = bnxt_aux_dev_init(softc); if (IS_ERR_OR_NULL(softc->aux_dev)) { device_printf(softc->dev, "Failed to init auxiliary device for ROCE\n"); goto skip_aux_init; } softc->aux_dev->id = ida_alloc(&bnxt_aux_dev_ids, GFP_KERNEL); if (softc->aux_dev->id < 0) { device_printf(softc->dev, "ida alloc failed for ROCE auxiliary device\n"); bnxt_aux_dev_free(softc); goto skip_aux_init; } msleep(1000 * 2); /* If aux bus init fails, continue with netdev init. */ rc = bnxt_rdma_aux_device_add(softc); if (rc) { device_printf(softc->dev, "Failed to add auxiliary device for ROCE\n"); msleep(1000 * 2); ida_free(&bnxt_aux_dev_ids, softc->aux_dev->id); - bnxt_aux_dev_free(softc); } device_printf(softc->dev, "%s:%d Added auxiliary device (id %d) for ROCE \n", __func__, __LINE__, softc->aux_dev->id); skip_aux_init: return; } /* Device configuration */ static void bnxt_init(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); struct ifmediareq ifmr; int i; int rc; if (!BNXT_CHIP_P5(softc)) { rc = bnxt_hwrm_func_reset(softc); if (rc) return; } else if (softc->is_dev_init) { bnxt_stop(ctx); } softc->is_dev_init = true; bnxt_clear_ids(softc); if (BNXT_CHIP_P5(softc)) goto skip_def_cp_ring; /* Allocate the default completion ring */ softc->def_cp_ring.cons = UINT32_MAX; softc->def_cp_ring.v_bit = 1; bnxt_mark_cpr_invalid(&softc->def_cp_ring); rc = bnxt_hwrm_ring_alloc(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, &softc->def_cp_ring.ring); if (rc) goto fail; skip_def_cp_ring: for (i = 0; i < softc->nrxqsets; i++) { /* Allocate the statistics context */ rc = bnxt_hwrm_stat_ctx_alloc(softc, &softc->rx_cp_rings[i], softc->rx_stats[i].idi_paddr); if (rc) goto fail; if (BNXT_CHIP_P5(softc)) { /* Allocate the NQ */ softc->nq_rings[i].cons = 0; softc->nq_rings[i].v_bit = 1; softc->nq_rings[i].last_idx = UINT32_MAX; bnxt_mark_cpr_invalid(&softc->nq_rings[i]); rc = bnxt_hwrm_ring_alloc(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ, &softc->nq_rings[i].ring); if (rc) goto fail; softc->db_ops.bnxt_db_nq(&softc->nq_rings[i], 1); } /* Allocate the completion ring */ softc->rx_cp_rings[i].cons = UINT32_MAX; softc->rx_cp_rings[i].v_bit = 1; softc->rx_cp_rings[i].last_idx = UINT32_MAX; bnxt_mark_cpr_invalid(&softc->rx_cp_rings[i]); rc = bnxt_hwrm_ring_alloc(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, &softc->rx_cp_rings[i].ring); if (rc) goto fail; if (BNXT_CHIP_P5(softc)) softc->db_ops.bnxt_db_rx_cq(&softc->rx_cp_rings[i], 1); /* Allocate the RX ring */ rc = bnxt_hwrm_ring_alloc(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_RX, &softc->rx_rings[i]); if (rc) goto fail; softc->db_ops.bnxt_db_rx(&softc->rx_rings[i], 0); /* Allocate the AG ring */ rc = bnxt_hwrm_ring_alloc(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG, &softc->ag_rings[i]); if (rc) goto fail; softc->db_ops.bnxt_db_rx(&softc->ag_rings[i], 0); /* Allocate the ring group */ softc->grp_info[i].stats_ctx = softc->rx_cp_rings[i].stats_ctx_id; softc->grp_info[i].rx_ring_id = softc->rx_rings[i].phys_id; softc->grp_info[i].ag_ring_id = softc->ag_rings[i].phys_id; softc->grp_info[i].cp_ring_id = softc->rx_cp_rings[i].ring.phys_id; rc = bnxt_hwrm_ring_grp_alloc(softc, &softc->grp_info[i]); if (rc) goto fail; } /* And now set the default CP / NQ ring for the async */ rc = bnxt_cfg_async_cr(softc); if (rc) goto fail; /* Allocate the VNIC RSS context */ rc = bnxt_hwrm_vnic_ctx_alloc(softc, &softc->vnic_info.rss_id); if (rc) goto fail; /* Allocate the vnic */ softc->vnic_info.def_ring_grp = softc->grp_info[0].grp_id; softc->vnic_info.mru = softc->scctx->isc_max_frame_size; rc = bnxt_hwrm_vnic_alloc(softc, &softc->vnic_info); if (rc) goto fail; rc = bnxt_hwrm_vnic_cfg(softc, &softc->vnic_info); if (rc) goto fail; rc = bnxt_hwrm_vnic_set_hds(softc, &softc->vnic_info); if (rc) goto fail; rc = bnxt_hwrm_set_filter(softc); if (rc) goto fail; bnxt_rss_grp_tbl_init(softc); rc = bnxt_hwrm_rss_cfg(softc, &softc->vnic_info, softc->vnic_info.rss_hash_type); if (rc) goto fail; rc = bnxt_hwrm_vnic_tpa_cfg(softc); if (rc) goto fail; for (i = 0; i < softc->ntxqsets; i++) { /* Allocate the statistics context */ rc = bnxt_hwrm_stat_ctx_alloc(softc, &softc->tx_cp_rings[i], softc->tx_stats[i].idi_paddr); if (rc) goto fail; /* Allocate the completion ring */ softc->tx_cp_rings[i].cons = UINT32_MAX; softc->tx_cp_rings[i].v_bit = 1; bnxt_mark_cpr_invalid(&softc->tx_cp_rings[i]); rc = bnxt_hwrm_ring_alloc(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, &softc->tx_cp_rings[i].ring); if (rc) goto fail; if (BNXT_CHIP_P5(softc)) softc->db_ops.bnxt_db_tx_cq(&softc->tx_cp_rings[i], 1); /* Allocate the TX ring */ rc = bnxt_hwrm_ring_alloc(softc, HWRM_RING_ALLOC_INPUT_RING_TYPE_TX, &softc->tx_rings[i]); if (rc) goto fail; softc->db_ops.bnxt_db_tx(&softc->tx_rings[i], 0); } bnxt_do_enable_intr(&softc->def_cp_ring); bnxt_get_port_module_status(softc); bnxt_media_status(softc->ctx, &ifmr); bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info); return; fail: bnxt_func_reset(softc); bnxt_clear_ids(softc); return; } static void bnxt_stop(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); softc->is_dev_init = false; bnxt_do_disable_intr(&softc->def_cp_ring); bnxt_func_reset(softc); bnxt_clear_ids(softc); return; } static u_int bnxt_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) { uint8_t *mta = arg; if (cnt == BNXT_MAX_MC_ADDRS) return (1); bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); return (1); } static void bnxt_multi_set(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); if_t ifp = iflib_get_ifp(ctx); uint8_t *mta; int mcnt; mta = softc->vnic_info.mc_list.idi_vaddr; bzero(mta, softc->vnic_info.mc_list.idi_size); mcnt = if_foreach_llmaddr(ifp, bnxt_copy_maddr, mta); if (mcnt > BNXT_MAX_MC_ADDRS) { softc->vnic_info.rx_mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info); } else { softc->vnic_info.rx_mask &= ~HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; bus_dmamap_sync(softc->vnic_info.mc_list.idi_tag, softc->vnic_info.mc_list.idi_map, BUS_DMASYNC_PREWRITE); softc->vnic_info.mc_list_count = mcnt; softc->vnic_info.rx_mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST; if (bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info)) device_printf(softc->dev, "set_multi: rx_mask set failed\n"); } } static int bnxt_mtu_set(if_ctx_t ctx, uint32_t mtu) { struct bnxt_softc *softc = iflib_get_softc(ctx); if (mtu > BNXT_MAX_MTU) return EINVAL; softc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; softc->rx_buf_size = min(softc->scctx->isc_max_frame_size, BNXT_PAGE_SIZE); return 0; } static void bnxt_media_status(if_ctx_t ctx, struct ifmediareq * ifmr) { struct bnxt_softc *softc = iflib_get_softc(ctx); struct bnxt_link_info *link_info = &softc->link_info; struct ifmedia_entry *next; uint64_t target_baudrate = bnxt_get_baudrate(link_info); int active_media = IFM_UNKNOWN; bnxt_update_link(softc, true); ifmr->ifm_status = IFM_AVALID; ifmr->ifm_active = IFM_ETHER; if (link_info->link_up) ifmr->ifm_status |= IFM_ACTIVE; else ifmr->ifm_status &= ~IFM_ACTIVE; if (link_info->duplex == HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL) ifmr->ifm_active |= IFM_FDX; else ifmr->ifm_active |= IFM_HDX; /* * Go through the list of supported media which got prepared * as part of bnxt_add_media_types() using api ifmedia_add(). */ LIST_FOREACH(next, &(iflib_get_media(ctx)->ifm_list), ifm_list) { if (ifmedia_baudrate(next->ifm_media) == target_baudrate) { active_media = next->ifm_media; break; } } ifmr->ifm_active |= active_media; if (link_info->flow_ctrl.rx) ifmr->ifm_active |= IFM_ETH_RXPAUSE; if (link_info->flow_ctrl.tx) ifmr->ifm_active |= IFM_ETH_TXPAUSE; bnxt_report_link(softc); return; } static int bnxt_media_change(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); struct ifmedia *ifm = iflib_get_media(ctx); struct ifmediareq ifmr; int rc; if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) return EINVAL; softc->link_info.req_signal_mode = HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4; switch (IFM_SUBTYPE(ifm->ifm_media)) { case IFM_100_T: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB; break; case IFM_1000_KX: case IFM_1000_SGMII: case IFM_1000_CX: case IFM_1000_SX: case IFM_1000_LX: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB; break; case IFM_2500_KX: case IFM_2500_T: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB; break; case IFM_10G_CR1: case IFM_10G_KR: case IFM_10G_LR: case IFM_10G_SR: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB; break; case IFM_20G_KR2: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB; break; case IFM_25G_CR: case IFM_25G_KR: case IFM_25G_SR: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB; break; case IFM_40G_CR4: case IFM_40G_KR4: case IFM_40G_LR4: case IFM_40G_SR4: case IFM_40G_XLAUI: case IFM_40G_XLAUI_AC: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB; break; case IFM_50G_CR2: case IFM_50G_KR2: case IFM_50G_SR2: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB; break; case IFM_50G_CP: case IFM_50G_LR: case IFM_50G_SR: case IFM_50G_KR_PAM4: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB; softc->link_info.req_signal_mode = HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4; softc->link_info.force_pam4_speed_set_by_user = true; break; case IFM_100G_CR4: case IFM_100G_KR4: case IFM_100G_LR4: case IFM_100G_SR4: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB; break; case IFM_100G_CP2: case IFM_100G_SR2: case IFM_100G_KR_PAM4: case IFM_100G_KR2_PAM4: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB; softc->link_info.req_signal_mode = HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4; softc->link_info.force_pam4_speed_set_by_user = true; break; case IFM_200G_SR4: case IFM_200G_FR4: case IFM_200G_LR4: case IFM_200G_DR4: case IFM_200G_CR4_PAM4: case IFM_200G_KR4_PAM4: softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; softc->link_info.req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB; softc->link_info.force_pam4_speed_set_by_user = true; softc->link_info.req_signal_mode = HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4; break; case IFM_1000_T: softc->link_info.advertising = HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB; softc->link_info.autoneg |= BNXT_AUTONEG_SPEED; break; case IFM_10G_T: softc->link_info.advertising = HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB; softc->link_info.autoneg |= BNXT_AUTONEG_SPEED; break; default: device_printf(softc->dev, "Unsupported media type! Using auto\n"); /* Fall-through */ case IFM_AUTO: // Auto softc->link_info.autoneg |= BNXT_AUTONEG_SPEED; break; } rc = bnxt_hwrm_set_link_setting(softc, true, true, true); bnxt_media_status(softc->ctx, &ifmr); return rc; } static int bnxt_promisc_set(if_ctx_t ctx, int flags) { struct bnxt_softc *softc = iflib_get_softc(ctx); if_t ifp = iflib_get_ifp(ctx); int rc; if (if_getflags(ifp) & IFF_ALLMULTI || if_llmaddr_count(ifp) > BNXT_MAX_MC_ADDRS) softc->vnic_info.rx_mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; else softc->vnic_info.rx_mask &= ~HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; if (if_getflags(ifp) & IFF_PROMISC) softc->vnic_info.rx_mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS | HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN; else softc->vnic_info.rx_mask &= ~(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS); rc = bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info); return rc; } static uint64_t bnxt_get_counter(if_ctx_t ctx, ift_counter cnt) { if_t ifp = iflib_get_ifp(ctx); if (cnt < IFCOUNTERS) return if_get_counter_default(ifp, cnt); return 0; } static void bnxt_update_admin_status(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); /* * When SR-IOV is enabled, avoid each VF sending this HWRM * request every sec with which firmware timeouts can happen */ if (!BNXT_PF(softc)) return; bnxt_hwrm_port_qstats(softc); if (BNXT_CHIP_P5(softc) && (softc->flags & BNXT_FLAG_FW_CAP_EXT_STATS)) bnxt_hwrm_port_qstats_ext(softc); if (BNXT_CHIP_P5(softc)) { struct ifmediareq ifmr; if (bit_test(softc->state_bv, BNXT_STATE_LINK_CHANGE)) { bit_clear(softc->state_bv, BNXT_STATE_LINK_CHANGE); bnxt_media_status(softc->ctx, &ifmr); } } return; } static void bnxt_if_timer(if_ctx_t ctx, uint16_t qid) { struct bnxt_softc *softc = iflib_get_softc(ctx); uint64_t ticks_now = ticks; /* Schedule bnxt_update_admin_status() once per sec */ if (ticks_now - softc->admin_ticks >= hz) { softc->admin_ticks = ticks_now; iflib_admin_intr_deferred(ctx); } return; } static void inline bnxt_do_enable_intr(struct bnxt_cp_ring *cpr) { struct bnxt_softc *softc = cpr->ring.softc; if (cpr->ring.phys_id == (uint16_t)HWRM_NA_SIGNATURE) return; if (BNXT_CHIP_P5(softc)) softc->db_ops.bnxt_db_nq(cpr, 1); else softc->db_ops.bnxt_db_rx_cq(cpr, 1); } static void inline bnxt_do_disable_intr(struct bnxt_cp_ring *cpr) { struct bnxt_softc *softc = cpr->ring.softc; if (cpr->ring.phys_id == (uint16_t)HWRM_NA_SIGNATURE) return; if (BNXT_CHIP_P5(softc)) softc->db_ops.bnxt_db_nq(cpr, 0); else softc->db_ops.bnxt_db_rx_cq(cpr, 0); } /* Enable all interrupts */ static void bnxt_intr_enable(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); int i; bnxt_do_enable_intr(&softc->def_cp_ring); for (i = 0; i < softc->nrxqsets; i++) if (BNXT_CHIP_P5(softc)) softc->db_ops.bnxt_db_nq(&softc->nq_rings[i], 1); else softc->db_ops.bnxt_db_rx_cq(&softc->rx_cp_rings[i], 1); return; } /* Enable interrupt for a single queue */ static int bnxt_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) { struct bnxt_softc *softc = iflib_get_softc(ctx); if (BNXT_CHIP_P5(softc)) softc->db_ops.bnxt_db_nq(&softc->nq_rings[qid], 1); else softc->db_ops.bnxt_db_rx_cq(&softc->tx_cp_rings[qid], 1); return 0; } static void bnxt_process_cmd_cmpl(struct bnxt_softc *softc, hwrm_cmpl_t *cmd_cmpl) { device_printf(softc->dev, "cmd sequence number %d\n", cmd_cmpl->sequence_id); return; } static void bnxt_process_async_msg(struct bnxt_cp_ring *cpr, tx_cmpl_t *cmpl) { struct bnxt_softc *softc = cpr->ring.softc; uint16_t type = cmpl->flags_type & TX_CMPL_TYPE_MASK; switch (type) { case HWRM_CMPL_TYPE_HWRM_DONE: bnxt_process_cmd_cmpl(softc, (hwrm_cmpl_t *)cmpl); break; case HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT: bnxt_handle_async_event(softc, (cmpl_base_t *) cmpl); break; default: device_printf(softc->dev, "%s:%d Unhandled async message %x\n", __FUNCTION__, __LINE__, type); break; } } -static void +void process_nq(struct bnxt_softc *softc, uint16_t nqid) { struct bnxt_cp_ring *cpr = &softc->nq_rings[nqid]; nq_cn_t *cmp = (nq_cn_t *) cpr->ring.vaddr; bool v_bit = cpr->v_bit; uint32_t cons = cpr->cons; uint16_t nq_type, nqe_cnt = 0; while (1) { if (!NQ_VALID(&cmp[cons], v_bit)) goto done; nq_type = NQ_CN_TYPE_MASK & cmp[cons].type; if (nq_type != NQ_CN_TYPE_CQ_NOTIFICATION) bnxt_process_async_msg(cpr, (tx_cmpl_t *)&cmp[cons]); NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); nqe_cnt++; } done: if (nqe_cnt) { cpr->cons = cons; cpr->v_bit = v_bit; } } static int bnxt_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) { struct bnxt_softc *softc = iflib_get_softc(ctx); if (BNXT_CHIP_P5(softc)) { process_nq(softc, qid); softc->db_ops.bnxt_db_nq(&softc->nq_rings[qid], 1); } softc->db_ops.bnxt_db_rx_cq(&softc->rx_cp_rings[qid], 1); return 0; } /* Disable all interrupts */ static void bnxt_disable_intr(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); int i; /* * NOTE: These TX interrupts should never get enabled, so don't * update the index */ for (i = 0; i < softc->nrxqsets; i++) if (BNXT_CHIP_P5(softc)) softc->db_ops.bnxt_db_nq(&softc->nq_rings[i], 0); else softc->db_ops.bnxt_db_rx_cq(&softc->rx_cp_rings[i], 0); return; } static int bnxt_msix_intr_assign(if_ctx_t ctx, int msix) { struct bnxt_softc *softc = iflib_get_softc(ctx); struct bnxt_cp_ring *ring; struct if_irq *irq; uint16_t id; int rc; int i; char irq_name[16]; if (BNXT_CHIP_P5(softc)) goto skip_default_cp; rc = iflib_irq_alloc_generic(ctx, &softc->def_cp_ring.irq, softc->def_cp_ring.ring.id + 1, IFLIB_INTR_ADMIN, bnxt_handle_def_cp, softc, 0, "def_cp"); if (rc) { device_printf(iflib_get_dev(ctx), "Failed to register default completion ring handler\n"); return rc; } skip_default_cp: for (i=0; iscctx->isc_nrxqsets; i++) { if (BNXT_CHIP_P5(softc)) { irq = &softc->nq_rings[i].irq; id = softc->nq_rings[i].ring.id; ring = &softc->nq_rings[i]; } else { irq = &softc->rx_cp_rings[i].irq; id = softc->rx_cp_rings[i].ring.id ; ring = &softc->rx_cp_rings[i]; } snprintf(irq_name, sizeof(irq_name), "rxq%d", i); rc = iflib_irq_alloc_generic(ctx, irq, id + 1, IFLIB_INTR_RX, bnxt_handle_isr, ring, i, irq_name); if (rc) { device_printf(iflib_get_dev(ctx), "Failed to register RX completion ring handler\n"); i--; goto fail; } } for (i=0; iscctx->isc_ntxqsets; i++) iflib_softirq_alloc_generic(ctx, NULL, IFLIB_INTR_TX, NULL, i, "tx_cp"); return rc; fail: for (; i>=0; i--) iflib_irq_free(ctx, &softc->rx_cp_rings[i].irq); iflib_irq_free(ctx, &softc->def_cp_ring.irq); return rc; } /* * We're explicitly allowing duplicates here. They will need to be * removed as many times as they are added. */ static void bnxt_vlan_register(if_ctx_t ctx, uint16_t vtag) { struct bnxt_softc *softc = iflib_get_softc(ctx); struct bnxt_vlan_tag *new_tag; new_tag = malloc(sizeof(struct bnxt_vlan_tag), M_DEVBUF, M_NOWAIT); if (new_tag == NULL) return; new_tag->tag = vtag; new_tag->filter_id = -1; SLIST_INSERT_HEAD(&softc->vnic_info.vlan_tags, new_tag, next); }; static void bnxt_vlan_unregister(if_ctx_t ctx, uint16_t vtag) { struct bnxt_softc *softc = iflib_get_softc(ctx); struct bnxt_vlan_tag *vlan_tag; SLIST_FOREACH(vlan_tag, &softc->vnic_info.vlan_tags, next) { if (vlan_tag->tag == vtag) { SLIST_REMOVE(&softc->vnic_info.vlan_tags, vlan_tag, bnxt_vlan_tag, next); free(vlan_tag, M_DEVBUF); break; } } } static int bnxt_wol_config(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); if_t ifp = iflib_get_ifp(ctx); if (!softc) return -EBUSY; if (!bnxt_wol_supported(softc)) return -ENOTSUP; if (if_getcapenable(ifp) & IFCAP_WOL_MAGIC) { if (!softc->wol) { if (bnxt_hwrm_alloc_wol_fltr(softc)) return -EBUSY; softc->wol = 1; } } else { if (softc->wol) { if (bnxt_hwrm_free_wol_fltr(softc)) return -EBUSY; softc->wol = 0; } } return 0; } static bool bnxt_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) { switch (event) { case IFLIB_RESTART_VLAN_CONFIG: default: return (false); } } static int bnxt_shutdown(if_ctx_t ctx) { bnxt_wol_config(ctx); return 0; } static int bnxt_suspend(if_ctx_t ctx) { bnxt_wol_config(ctx); return 0; } static int bnxt_resume(if_ctx_t ctx) { struct bnxt_softc *softc = iflib_get_softc(ctx); bnxt_get_wol_settings(softc); return 0; } static int bnxt_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data) { struct bnxt_softc *softc = iflib_get_softc(ctx); struct ifreq *ifr = (struct ifreq *)data; struct bnxt_ioctl_header *ioh; size_t iol; int rc = ENOTSUP; struct bnxt_ioctl_data iod_storage, *iod = &iod_storage; switch (command) { case SIOCGPRIVATE_0: if ((rc = priv_check(curthread, PRIV_DRIVER)) != 0) goto exit; ioh = ifr_buffer_get_buffer(ifr); iol = ifr_buffer_get_length(ifr); if (iol > sizeof(iod_storage)) return (EINVAL); if ((rc = copyin(ioh, iod, iol)) != 0) goto exit; switch (iod->hdr.type) { case BNXT_HWRM_NVM_FIND_DIR_ENTRY: { struct bnxt_ioctl_hwrm_nvm_find_dir_entry *find = &iod->find; rc = bnxt_hwrm_nvm_find_dir_entry(softc, find->type, &find->ordinal, find->ext, &find->index, find->use_index, find->search_opt, &find->data_length, &find->item_length, &find->fw_ver); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } case BNXT_HWRM_NVM_READ: { struct bnxt_ioctl_hwrm_nvm_read *rd = &iod->read; struct iflib_dma_info dma_data; size_t offset; size_t remain; size_t csize; /* * Some HWRM versions can't read more than 0x8000 bytes */ rc = iflib_dma_alloc(softc->ctx, min(rd->length, 0x8000), &dma_data, BUS_DMA_NOWAIT); if (rc) break; for (remain = rd->length, offset = 0; remain && offset < rd->length; offset += 0x8000) { csize = min(remain, 0x8000); rc = bnxt_hwrm_nvm_read(softc, rd->index, rd->offset + offset, csize, &dma_data); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); break; } else { rc = copyout(dma_data.idi_vaddr, rd->data + offset, csize); iod->hdr.rc = rc; } remain -= csize; } if (rc == 0) rc = copyout(iod, ioh, iol); iflib_dma_free(&dma_data); goto exit; } case BNXT_HWRM_FW_RESET: { struct bnxt_ioctl_hwrm_fw_reset *rst = &iod->reset; rc = bnxt_hwrm_fw_reset(softc, rst->processor, &rst->selfreset); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } case BNXT_HWRM_FW_QSTATUS: { struct bnxt_ioctl_hwrm_fw_qstatus *qstat = &iod->status; rc = bnxt_hwrm_fw_qstatus(softc, qstat->processor, &qstat->selfreset); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } case BNXT_HWRM_NVM_WRITE: { struct bnxt_ioctl_hwrm_nvm_write *wr = &iod->write; rc = bnxt_hwrm_nvm_write(softc, wr->data, true, wr->type, wr->ordinal, wr->ext, wr->attr, wr->option, wr->data_length, wr->keep, &wr->item_length, &wr->index); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } case BNXT_HWRM_NVM_ERASE_DIR_ENTRY: { struct bnxt_ioctl_hwrm_nvm_erase_dir_entry *erase = &iod->erase; rc = bnxt_hwrm_nvm_erase_dir_entry(softc, erase->index); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } case BNXT_HWRM_NVM_GET_DIR_INFO: { struct bnxt_ioctl_hwrm_nvm_get_dir_info *info = &iod->dir_info; rc = bnxt_hwrm_nvm_get_dir_info(softc, &info->entries, &info->entry_length); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } case BNXT_HWRM_NVM_GET_DIR_ENTRIES: { struct bnxt_ioctl_hwrm_nvm_get_dir_entries *get = &iod->dir_entries; struct iflib_dma_info dma_data; rc = iflib_dma_alloc(softc->ctx, get->max_size, &dma_data, BUS_DMA_NOWAIT); if (rc) break; rc = bnxt_hwrm_nvm_get_dir_entries(softc, &get->entries, &get->entry_length, &dma_data); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { rc = copyout(dma_data.idi_vaddr, get->data, get->entry_length * get->entries); iod->hdr.rc = rc; if (rc == 0) rc = copyout(iod, ioh, iol); } iflib_dma_free(&dma_data); goto exit; } case BNXT_HWRM_NVM_VERIFY_UPDATE: { struct bnxt_ioctl_hwrm_nvm_verify_update *vrfy = &iod->verify; rc = bnxt_hwrm_nvm_verify_update(softc, vrfy->type, vrfy->ordinal, vrfy->ext); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } case BNXT_HWRM_NVM_INSTALL_UPDATE: { struct bnxt_ioctl_hwrm_nvm_install_update *inst = &iod->install; rc = bnxt_hwrm_nvm_install_update(softc, inst->install_type, &inst->installed_items, &inst->result, &inst->problem_item, &inst->reset_required); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } case BNXT_HWRM_NVM_MODIFY: { struct bnxt_ioctl_hwrm_nvm_modify *mod = &iod->modify; rc = bnxt_hwrm_nvm_modify(softc, mod->index, mod->offset, mod->data, true, mod->length); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } case BNXT_HWRM_FW_GET_TIME: { struct bnxt_ioctl_hwrm_fw_get_time *gtm = &iod->get_time; rc = bnxt_hwrm_fw_get_time(softc, >m->year, >m->month, >m->day, >m->hour, >m->minute, >m->second, >m->millisecond, >m->zone); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } case BNXT_HWRM_FW_SET_TIME: { struct bnxt_ioctl_hwrm_fw_set_time *stm = &iod->set_time; rc = bnxt_hwrm_fw_set_time(softc, stm->year, stm->month, stm->day, stm->hour, stm->minute, stm->second, stm->millisecond, stm->zone); if (rc) { iod->hdr.rc = rc; rc = copyout(&iod->hdr.rc, &ioh->rc, sizeof(ioh->rc)); } else { iod->hdr.rc = 0; rc = copyout(iod, ioh, iol); } goto exit; } } break; } exit: return rc; } static int bnxt_i2c_req(if_ctx_t ctx, struct ifi2creq *i2c) { struct bnxt_softc *softc = iflib_get_softc(ctx); uint8_t *data = i2c->data; int rc; /* No point in going further if phy status indicates * module is not inserted or if it is powered down or * if it is of type 10GBase-T */ if (softc->link_info.module_status > HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) return -EOPNOTSUPP; /* This feature is not supported in older firmware versions */ if (!BNXT_CHIP_P5(softc) || (softc->hwrm_spec_code < 0x10202)) return -EOPNOTSUPP; rc = bnxt_read_sfp_module_eeprom_info(softc, I2C_DEV_ADDR_A0, 0, 0, 0, i2c->offset, i2c->len, data); return rc; } /* * Support functions */ static int bnxt_probe_phy(struct bnxt_softc *softc) { struct bnxt_link_info *link_info = &softc->link_info; int rc = 0; softc->phy_flags = 0; rc = bnxt_hwrm_phy_qcaps(softc); if (rc) { device_printf(softc->dev, "Probe phy can't get phy capabilities (rc: %x)\n", rc); return rc; } rc = bnxt_update_link(softc, false); if (rc) { device_printf(softc->dev, "Probe phy can't update link (rc: %x)\n", rc); return (rc); } bnxt_get_port_module_status(softc); /*initialize the ethool setting copy with NVM settings */ if (link_info->auto_mode != HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) link_info->autoneg |= BNXT_AUTONEG_SPEED; link_info->req_duplex = link_info->duplex_setting; /* NRZ link speed */ if (link_info->autoneg & BNXT_AUTONEG_SPEED) link_info->req_link_speed = link_info->auto_link_speeds; else link_info->req_link_speed = link_info->force_link_speed; /* PAM4 link speed */ if (link_info->auto_pam4_link_speeds) link_info->req_link_speed = link_info->auto_pam4_link_speeds; if (link_info->force_pam4_link_speed) link_info->req_link_speed = link_info->force_pam4_link_speed; return (rc); } static void add_media(struct bnxt_softc *softc, uint8_t media_type, uint16_t supported, uint16_t supported_pam4) { switch (media_type) { case BNXT_MEDIA_CR: BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_50G, IFM_50G_CP); BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_100G, IFM_100G_CP2); BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_200G, IFM_200G_CR4_PAM4); BNXT_IFMEDIA_ADD(supported, SPEEDS_100GB, IFM_100G_CR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_50GB, IFM_50G_CR2); BNXT_IFMEDIA_ADD(supported, SPEEDS_40GB, IFM_40G_CR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_25GB, IFM_25G_CR); BNXT_IFMEDIA_ADD(supported, SPEEDS_10GB, IFM_10G_CR1); BNXT_IFMEDIA_ADD(supported, SPEEDS_1GB, IFM_1000_CX); break; case BNXT_MEDIA_LR: BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_50G, IFM_50G_LR); BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_200G, IFM_200G_LR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_100GB, IFM_100G_LR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_50GB, IFM_50G_LR2); BNXT_IFMEDIA_ADD(supported, SPEEDS_40GB, IFM_40G_LR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_25GB, IFM_25G_LR); BNXT_IFMEDIA_ADD(supported, SPEEDS_10GB, IFM_10G_LR); BNXT_IFMEDIA_ADD(supported, SPEEDS_1GB, IFM_1000_LX); break; case BNXT_MEDIA_SR: BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_50G, IFM_50G_SR); BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_100G, IFM_100G_SR2); BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_200G, IFM_200G_SR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_100GB, IFM_100G_SR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_50GB, IFM_50G_SR2); BNXT_IFMEDIA_ADD(supported, SPEEDS_40GB, IFM_40G_SR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_25GB, IFM_25G_SR); BNXT_IFMEDIA_ADD(supported, SPEEDS_10GB, IFM_10G_SR); BNXT_IFMEDIA_ADD(supported, SPEEDS_1GB, IFM_1000_SX); break; case BNXT_MEDIA_KR: BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_50G, IFM_50G_KR_PAM4); BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_100G, IFM_100G_KR2_PAM4); BNXT_IFMEDIA_ADD(supported_pam4, PAM4_SPEEDS_200G, IFM_200G_KR4_PAM4); BNXT_IFMEDIA_ADD(supported, SPEEDS_100GB, IFM_100G_KR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_50GB, IFM_50G_KR2); BNXT_IFMEDIA_ADD(supported, SPEEDS_50GB, IFM_50G_KR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_40GB, IFM_40G_KR4); BNXT_IFMEDIA_ADD(supported, SPEEDS_25GB, IFM_25G_KR); BNXT_IFMEDIA_ADD(supported, SPEEDS_20GB, IFM_20G_KR2); BNXT_IFMEDIA_ADD(supported, SPEEDS_10GB, IFM_10G_KR); BNXT_IFMEDIA_ADD(supported, SPEEDS_1GB, IFM_1000_KX); break; default: break; } return; } static void bnxt_add_media_types(struct bnxt_softc *softc) { struct bnxt_link_info *link_info = &softc->link_info; uint16_t supported = 0, supported_pam4 = 0; uint8_t phy_type = get_phy_type(softc), media_type; supported = link_info->support_speeds; supported_pam4 = link_info->support_pam4_speeds; /* Auto is always supported */ ifmedia_add(softc->media, IFM_ETHER | IFM_AUTO, 0, NULL); if (softc->flags & BNXT_FLAG_NPAR) return; switch (phy_type) { case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR: media_type = BNXT_MEDIA_CR; break; case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR: media_type = BNXT_MEDIA_LR; break; case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX: media_type = BNXT_MEDIA_SR; break; case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR: media_type = BNXT_MEDIA_KR; break; case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE: BNXT_IFMEDIA_ADD(supported, SPEEDS_25GB, IFM_25G_ACC); BNXT_IFMEDIA_ADD(supported, SPEEDS_10GB, IFM_10G_AOC); BNXT_IFMEDIA_ADD(supported, SPEEDS_40GB, IFM_40G_XLAUI); BNXT_IFMEDIA_ADD(supported, SPEEDS_40GB, IFM_40G_XLAUI_AC); return; case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX: BNXT_IFMEDIA_ADD(supported, SPEEDS_1GBHD, IFM_1000_CX); return; case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET: case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE: BNXT_IFMEDIA_ADD(supported, SPEEDS_10GB, IFM_10G_T); BNXT_IFMEDIA_ADD(supported, SPEEDS_2_5GB, IFM_2500_T); BNXT_IFMEDIA_ADD(supported, SPEEDS_1GB, IFM_1000_T); BNXT_IFMEDIA_ADD(supported, SPEEDS_100MB, IFM_100_T); BNXT_IFMEDIA_ADD(supported, SPEEDS_10MB, IFM_10_T); return; case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX: BNXT_IFMEDIA_ADD(supported, SPEEDS_10GB, IFM_10G_KR); BNXT_IFMEDIA_ADD(supported, SPEEDS_2_5GB, IFM_2500_KX); BNXT_IFMEDIA_ADD(supported, SPEEDS_1GB, IFM_1000_KX); return; case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY: BNXT_IFMEDIA_ADD(supported, SPEEDS_1GB, IFM_1000_SGMII); return; case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN: /* Only Autoneg is supported for TYPE_UNKNOWN */ return; default: /* Only Autoneg is supported for new phy type values */ device_printf(softc->dev, "phy type %d not supported by driver\n", phy_type); return; } /* add_media is invoked twice, once with a firmware speed mask of 0 and a valid * value for both NRZ and PAM4 sig mode. This ensures accurate display of all * supported medias and currently configured media in the "ifconfig -m" output */ if (link_info->sig_mode == BNXT_SIG_MODE_PAM4) { add_media(softc, media_type, supported, 0); add_media(softc, media_type, 0, supported_pam4); } else { add_media(softc, media_type, 0, supported_pam4); add_media(softc, media_type, supported, 0); } return; } static int bnxt_map_bar(struct bnxt_softc *softc, struct bnxt_bar_info *bar, int bar_num, bool shareable) { uint32_t flag; if (bar->res != NULL) { device_printf(softc->dev, "Bar %d already mapped\n", bar_num); return EDOOFUS; } bar->rid = PCIR_BAR(bar_num); flag = RF_ACTIVE; if (shareable) flag |= RF_SHAREABLE; if ((bar->res = bus_alloc_resource_any(softc->dev, SYS_RES_MEMORY, &bar->rid, flag)) == NULL) { device_printf(softc->dev, "PCI BAR%d mapping failure\n", bar_num); return (ENXIO); } bar->tag = rman_get_bustag(bar->res); bar->handle = rman_get_bushandle(bar->res); bar->size = rman_get_size(bar->res); return 0; } static int bnxt_pci_mapping(struct bnxt_softc *softc) { int rc; rc = bnxt_map_bar(softc, &softc->hwrm_bar, 0, true); if (rc) return rc; rc = bnxt_map_bar(softc, &softc->doorbell_bar, 2, false); return rc; } static void bnxt_pci_mapping_free(struct bnxt_softc *softc) { if (softc->hwrm_bar.res != NULL) bus_release_resource(softc->dev, SYS_RES_MEMORY, softc->hwrm_bar.rid, softc->hwrm_bar.res); softc->hwrm_bar.res = NULL; if (softc->doorbell_bar.res != NULL) bus_release_resource(softc->dev, SYS_RES_MEMORY, softc->doorbell_bar.rid, softc->doorbell_bar.res); softc->doorbell_bar.res = NULL; } static int bnxt_update_link(struct bnxt_softc *softc, bool chng_link_state) { struct bnxt_link_info *link_info = &softc->link_info; uint8_t link_up = link_info->link_up; int rc = 0; rc = bnxt_hwrm_port_phy_qcfg(softc); if (rc) goto exit; /* TODO: need to add more logic to report VF link */ if (chng_link_state) { if (link_info->phy_link_status == HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) link_info->link_up = 1; else link_info->link_up = 0; if (link_up != link_info->link_up) bnxt_report_link(softc); } else { /* always link down if not require to update link state */ link_info->link_up = 0; } exit: return rc; } #define ETHTOOL_SPEED_1000 1000 #define ETHTOOL_SPEED_10000 10000 #define ETHTOOL_SPEED_20000 20000 #define ETHTOOL_SPEED_25000 25000 #define ETHTOOL_SPEED_40000 40000 #define ETHTOOL_SPEED_50000 50000 #define ETHTOOL_SPEED_100000 100000 #define ETHTOOL_SPEED_200000 200000 #define ETHTOOL_SPEED_UNKNOWN -1 static u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) { switch (fw_link_speed) { case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB: return ETHTOOL_SPEED_1000; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB: return ETHTOOL_SPEED_10000; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB: return ETHTOOL_SPEED_20000; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB: return ETHTOOL_SPEED_25000; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB: return ETHTOOL_SPEED_40000; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB: return ETHTOOL_SPEED_50000; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB: return ETHTOOL_SPEED_100000; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB: return ETHTOOL_SPEED_200000; default: return ETHTOOL_SPEED_UNKNOWN; } } void bnxt_report_link(struct bnxt_softc *softc) { struct bnxt_link_info *link_info = &softc->link_info; const char *duplex = NULL, *flow_ctrl = NULL; const char *signal_mode = ""; if(softc->edev) softc->edev->espeed = bnxt_fw_to_ethtool_speed(link_info->link_speed); if (link_info->link_up == link_info->last_link_up) { if (!link_info->link_up) return; if ((link_info->duplex == link_info->last_duplex) && (link_info->phy_type == link_info->last_phy_type) && (!(BNXT_IS_FLOW_CTRL_CHANGED(link_info)))) return; } if (link_info->link_up) { if (link_info->duplex == HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL) duplex = "full duplex"; else duplex = "half duplex"; if (link_info->flow_ctrl.tx & link_info->flow_ctrl.rx) flow_ctrl = "FC - receive & transmit"; else if (link_info->flow_ctrl.tx) flow_ctrl = "FC - transmit"; else if (link_info->flow_ctrl.rx) flow_ctrl = "FC - receive"; else flow_ctrl = "FC - none"; if (softc->link_info.phy_qcfg_resp.option_flags & HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN) { uint8_t sig_mode = softc->link_info.active_fec_sig_mode & HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK; switch (sig_mode) { case BNXT_SIG_MODE_NRZ: signal_mode = "(NRZ) "; break; case BNXT_SIG_MODE_PAM4: signal_mode = "(PAM4) "; break; default: break; } link_info->sig_mode = sig_mode; } iflib_link_state_change(softc->ctx, LINK_STATE_UP, IF_Gbps(100)); device_printf(softc->dev, "Link is UP %s %s, %s - %d Mbps \n", duplex, signal_mode, flow_ctrl, (link_info->link_speed * 100)); } else { iflib_link_state_change(softc->ctx, LINK_STATE_DOWN, bnxt_get_baudrate(&softc->link_info)); device_printf(softc->dev, "Link is Down\n"); } link_info->last_link_up = link_info->link_up; link_info->last_duplex = link_info->duplex; link_info->last_phy_type = link_info->phy_type; link_info->last_flow_ctrl.tx = link_info->flow_ctrl.tx; link_info->last_flow_ctrl.rx = link_info->flow_ctrl.rx; link_info->last_flow_ctrl.autoneg = link_info->flow_ctrl.autoneg; /* update media types */ ifmedia_removeall(softc->media); bnxt_add_media_types(softc); ifmedia_set(softc->media, IFM_ETHER | IFM_AUTO); } static int bnxt_handle_isr(void *arg) { struct bnxt_cp_ring *cpr = arg; struct bnxt_softc *softc = cpr->ring.softc; cpr->int_count++; /* Disable further interrupts for this queue */ if (!BNXT_CHIP_P5(softc)) softc->db_ops.bnxt_db_rx_cq(cpr, 0); return FILTER_SCHEDULE_THREAD; } static int bnxt_handle_def_cp(void *arg) { struct bnxt_softc *softc = arg; softc->db_ops.bnxt_db_rx_cq(&softc->def_cp_ring, 0); GROUPTASK_ENQUEUE(&softc->def_cp_task); return FILTER_HANDLED; } static void bnxt_clear_ids(struct bnxt_softc *softc) { int i; softc->def_cp_ring.stats_ctx_id = HWRM_NA_SIGNATURE; softc->def_cp_ring.ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->def_nq_ring.stats_ctx_id = HWRM_NA_SIGNATURE; softc->def_nq_ring.ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; for (i = 0; i < softc->ntxqsets; i++) { softc->tx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; softc->tx_cp_rings[i].ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->tx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; if (!softc->nq_rings) continue; softc->nq_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; softc->nq_rings[i].ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; } for (i = 0; i < softc->nrxqsets; i++) { softc->rx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; softc->rx_cp_rings[i].ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->rx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->ag_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; softc->grp_info[i].grp_id = (uint16_t)HWRM_NA_SIGNATURE; } softc->vnic_info.filter_id = -1; softc->vnic_info.id = (uint16_t)HWRM_NA_SIGNATURE; softc->vnic_info.rss_id = (uint16_t)HWRM_NA_SIGNATURE; memset(softc->vnic_info.rss_grp_tbl.idi_vaddr, 0xff, softc->vnic_info.rss_grp_tbl.idi_size); } static void bnxt_mark_cpr_invalid(struct bnxt_cp_ring *cpr) { struct cmpl_base *cmp = (void *)cpr->ring.vaddr; int i; for (i = 0; i < cpr->ring.ring_size; i++) cmp[i].info3_v = !cpr->v_bit; } static void bnxt_event_error_report(struct bnxt_softc *softc, u32 data1, u32 data2) { u32 err_type = BNXT_EVENT_ERROR_REPORT_TYPE(data1); switch (err_type) { case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL: device_printf(softc->dev, "1PPS: Received invalid signal on pin%u from the external source. Please fix the signal and reconfigure the pin\n", BNXT_EVENT_INVALID_SIGNAL_DATA(data2)); break; case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM: device_printf(softc->dev, "Pause Storm detected!\n"); break; case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD: device_printf(softc->dev, "One or more MMIO doorbells dropped by the device! epoch: 0x%x\n", BNXT_EVENT_DBR_EPOCH(data1)); break; case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM: { const char *nvm_err_str; if (EVENT_DATA1_NVM_ERR_TYPE_WRITE(data1)) nvm_err_str = "nvm write error"; else if (EVENT_DATA1_NVM_ERR_TYPE_ERASE(data1)) nvm_err_str = "nvm erase error"; else nvm_err_str = "unrecognized nvm error"; device_printf(softc->dev, "%s reported at address 0x%x\n", nvm_err_str, (u32)EVENT_DATA2_NVM_ERR_ADDR(data2)); break; } case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD: { char *threshold_type; char *dir_str; switch (EVENT_DATA1_THERMAL_THRESHOLD_TYPE(data1)) { case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN: threshold_type = "warning"; break; case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL: threshold_type = "critical"; break; case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL: threshold_type = "fatal"; break; case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN: threshold_type = "shutdown"; break; default: device_printf(softc->dev, "Unknown Thermal threshold type event\n"); return; } if (EVENT_DATA1_THERMAL_THRESHOLD_DIR_INCREASING(data1)) dir_str = "above"; else dir_str = "below"; device_printf(softc->dev, "Chip temperature has gone %s the %s thermal threshold!\n", dir_str, threshold_type); device_printf(softc->dev, "Temperature (In Celsius), Current: %u, threshold: %u\n", BNXT_EVENT_THERMAL_CURRENT_TEMP(data2), BNXT_EVENT_THERMAL_THRESHOLD_TEMP(data2)); break; } case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED: device_printf(softc->dev, "Speed change is not supported with dual rate transceivers on this board\n"); break; default: device_printf(softc->dev, "FW reported unknown error type: %u, data1: 0x%x data2: 0x%x\n", err_type, data1, data2); break; } } static void bnxt_handle_async_event(struct bnxt_softc *softc, struct cmpl_base *cmpl) { struct hwrm_async_event_cmpl *ae = (void *)cmpl; uint16_t async_id = le16toh(ae->event_id); struct ifmediareq ifmr; + char *type_str; + char *status_desc; + struct bnxt_fw_health *fw_health; u32 data1 = le32toh(ae->event_data1); u32 data2 = le32toh(ae->event_data2); switch (async_id) { case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: if (BNXT_CHIP_P5(softc)) bit_set(softc->state_bv, BNXT_STATE_LINK_CHANGE); else bnxt_media_status(softc->ctx, &ifmr); break; case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT: { bnxt_event_error_report(softc, data1, data2); goto async_event_process_exit; } case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE: break; + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { + type_str = "Solicited"; + + if (!softc->fw_health) + goto async_event_process_exit; + + softc->fw_reset_timestamp = jiffies; + softc->fw_reset_min_dsecs = ae->timestamp_lo; + if (!softc->fw_reset_min_dsecs) + softc->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; + softc->fw_reset_max_dsecs = le16toh(ae->timestamp_hi); + if (!softc->fw_reset_max_dsecs) + softc->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; + if (EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)) { + set_bit(BNXT_STATE_FW_ACTIVATE_RESET, &softc->state); + } else if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { + type_str = "Fatal"; + softc->fw_health->fatalities++; + set_bit(BNXT_STATE_FW_FATAL_COND, &softc->state); + } else if (data2 && BNXT_FW_STATUS_HEALTHY != + EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)) { + type_str = "Non-fatal"; + softc->fw_health->survivals++; + set_bit(BNXT_STATE_FW_NON_FATAL_COND, &softc->state); + } + device_printf(softc->dev, + "%s firmware reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n", + type_str, data1, data2, + softc->fw_reset_min_dsecs * 100, + softc->fw_reset_max_dsecs * 100); + set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &softc->sp_event); + break; + } + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { + fw_health = softc->fw_health; + status_desc = "healthy"; + u32 status; + + if (!fw_health) + goto async_event_process_exit; + + if (!EVENT_DATA1_RECOVERY_ENABLED(data1)) { + fw_health->enabled = false; + device_printf(softc->dev, "Driver recovery watchdog is disabled\n"); + break; + } + fw_health->primary = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); + fw_health->tmr_multiplier = + DIV_ROUND_UP(fw_health->polling_dsecs * HZ, + HZ * 10); + fw_health->tmr_counter = fw_health->tmr_multiplier; + if (!fw_health->enabled) + fw_health->last_fw_heartbeat = + bnxt_fw_health_readl(softc, BNXT_FW_HEARTBEAT_REG); + fw_health->last_fw_reset_cnt = + bnxt_fw_health_readl(softc, BNXT_FW_RESET_CNT_REG); + status = bnxt_fw_health_readl(softc, BNXT_FW_HEALTH_REG); + if (status != BNXT_FW_STATUS_HEALTHY) + status_desc = "unhealthy"; + device_printf(softc->dev, + "Driver recovery watchdog, role: %s, firmware status: 0x%x (%s), resets: %u\n", + fw_health->primary ? "primary" : "backup", status, + status_desc, fw_health->last_fw_reset_cnt); + if (!fw_health->enabled) { + /* Make sure tmr_counter is set and seen by + * bnxt_health_check() before setting enabled + */ + smp_mb(); + fw_health->enabled = true; + } + goto async_event_process_exit; + } + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR: device_printf(softc->dev, "Unhandled async completion type %u\n", async_id); break; default: device_printf(softc->dev, "Unknown async completion type %u\n", async_id); break; } + bnxt_queue_sp_work(softc); + async_event_process_exit: bnxt_ulp_async_events(softc, ae); } static void bnxt_def_cp_task(void *context) { if_ctx_t ctx = context; struct bnxt_softc *softc = iflib_get_softc(ctx); struct bnxt_cp_ring *cpr = &softc->def_cp_ring; /* Handle completions on the default completion ring */ struct cmpl_base *cmpl; uint32_t cons = cpr->cons; bool v_bit = cpr->v_bit; bool last_v_bit; uint32_t last_cons; uint16_t type; for (;;) { last_cons = cons; last_v_bit = v_bit; NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); cmpl = &((struct cmpl_base *)cpr->ring.vaddr)[cons]; if (!CMP_VALID(cmpl, v_bit)) break; type = le16toh(cmpl->type) & CMPL_BASE_TYPE_MASK; switch (type) { case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: bnxt_handle_async_event(softc, cmpl); break; case CMPL_BASE_TYPE_TX_L2: case CMPL_BASE_TYPE_RX_L2: case CMPL_BASE_TYPE_RX_AGG: case CMPL_BASE_TYPE_RX_TPA_START: case CMPL_BASE_TYPE_RX_TPA_END: case CMPL_BASE_TYPE_STAT_EJECT: case CMPL_BASE_TYPE_HWRM_DONE: case CMPL_BASE_TYPE_HWRM_FWD_REQ: case CMPL_BASE_TYPE_HWRM_FWD_RESP: case CMPL_BASE_TYPE_CQ_NOTIFICATION: case CMPL_BASE_TYPE_SRQ_EVENT: case CMPL_BASE_TYPE_DBQ_EVENT: case CMPL_BASE_TYPE_QP_EVENT: case CMPL_BASE_TYPE_FUNC_EVENT: device_printf(softc->dev, "Unhandled completion type %u\n", type); break; default: device_printf(softc->dev, "Unknown completion type %u\n", type); break; } } cpr->cons = last_cons; cpr->v_bit = last_v_bit; softc->db_ops.bnxt_db_rx_cq(cpr, 1); } uint8_t get_phy_type(struct bnxt_softc *softc) { struct bnxt_link_info *link_info = &softc->link_info; uint8_t phy_type = link_info->phy_type; uint16_t supported; if (phy_type != HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN) return phy_type; /* Deduce the phy type from the media type and supported speeds */ supported = link_info->support_speeds; if (link_info->media_type == HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET; if (link_info->media_type == HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC) { if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX; if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR; return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR; } if (link_info->media_type == HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE) return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR; return phy_type; } bool bnxt_check_hwrm_version(struct bnxt_softc *softc) { char buf[16]; sprintf(buf, "%hhu.%hhu.%hhu", softc->ver_info->hwrm_min_major, softc->ver_info->hwrm_min_minor, softc->ver_info->hwrm_min_update); if (softc->ver_info->hwrm_min_major > softc->ver_info->hwrm_if_major) { device_printf(softc->dev, "WARNING: HWRM version %s is too old (older than %s)\n", softc->ver_info->hwrm_if_ver, buf); return false; } else if(softc->ver_info->hwrm_min_major == softc->ver_info->hwrm_if_major) { if (softc->ver_info->hwrm_min_minor > softc->ver_info->hwrm_if_minor) { device_printf(softc->dev, "WARNING: HWRM version %s is too old (older than %s)\n", softc->ver_info->hwrm_if_ver, buf); return false; } else if (softc->ver_info->hwrm_min_minor == softc->ver_info->hwrm_if_minor) { if (softc->ver_info->hwrm_min_update > softc->ver_info->hwrm_if_update) { device_printf(softc->dev, "WARNING: HWRM version %s is too old (older than %s)\n", softc->ver_info->hwrm_if_ver, buf); return false; } } } return true; } static uint64_t bnxt_get_baudrate(struct bnxt_link_info *link) { switch (link->link_speed) { case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB: return IF_Mbps(100); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB: return IF_Gbps(1); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB: return IF_Gbps(2); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB: return IF_Mbps(2500); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB: return IF_Gbps(10); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB: return IF_Gbps(20); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB: return IF_Gbps(25); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB: return IF_Gbps(40); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB: return IF_Gbps(50); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB: return IF_Gbps(100); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB: return IF_Mbps(10); case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB: return IF_Gbps(200); } return IF_Gbps(100); } static void bnxt_get_wol_settings(struct bnxt_softc *softc) { uint16_t wol_handle = 0; if (!bnxt_wol_supported(softc)) return; do { wol_handle = bnxt_hwrm_get_wol_fltrs(softc, wol_handle); } while (wol_handle && wol_handle != BNXT_NO_MORE_WOL_FILTERS); }