diff --git a/sys/dev/ath/if_ath_sysctl.c b/sys/dev/ath/if_ath_sysctl.c index fd43ba4f6083..e116a9ed72d5 100644 --- a/sys/dev/ath/if_ath_sysctl.c +++ b/sys/dev/ath/if_ath_sysctl.c @@ -1,1359 +1,1359 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Driver for the Atheros Wireless LAN controller. * * This software is derived from work of Atsushi Onoe; his contribution * is greatly appreciated. */ #include "opt_inet.h" #include "opt_ath.h" #include "opt_wlan.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef IEEE80211_SUPPORT_SUPERG #include #endif #ifdef IEEE80211_SUPPORT_TDMA #include #endif #include #ifdef INET #include #include #endif #include #include /* XXX for softled */ #include #include #include #include #include #include #ifdef ATH_TX99_DIAG #include #endif #ifdef ATH_DEBUG_ALQ #include #endif static int ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int slottime; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); slottime = ath_hal_getslottime(sc->sc_ah); ATH_UNLOCK(sc); error = sysctl_handle_int(oidp, &slottime, 0, req); if (error || !req->newptr) goto finish; error = !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return error; } static int ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int acktimeout; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); acktimeout = ath_hal_getacktimeout(sc->sc_ah); ATH_UNLOCK(sc); error = sysctl_handle_int(oidp, &acktimeout, 0, req); if (error || !req->newptr) goto finish; error = !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int ctstimeout; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ctstimeout = ath_hal_getctstimeout(sc->sc_ah); ATH_UNLOCK(sc); error = sysctl_handle_int(oidp, &ctstimeout, 0, req); if (error || !req->newptr) goto finish; error = !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_softled(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; int softled = sc->sc_softled; int error; error = sysctl_handle_int(oidp, &softled, 0, req); if (error || !req->newptr) return error; softled = (softled != 0); if (softled != sc->sc_softled) { if (softled) { /* NB: handle any sc_ledpin change */ ath_led_config(sc); } sc->sc_softled = softled; } return 0; } static int ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; int ledpin = sc->sc_ledpin; int error; error = sysctl_handle_int(oidp, &ledpin, 0, req); if (error || !req->newptr) return error; if (ledpin != sc->sc_ledpin) { sc->sc_ledpin = ledpin; if (sc->sc_softled) { ath_led_config(sc); } } return 0; } static int ath_sysctl_hardled(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; int hardled = sc->sc_hardled; int error; error = sysctl_handle_int(oidp, &hardled, 0, req); if (error || !req->newptr) return error; hardled = (hardled != 0); if (hardled != sc->sc_hardled) { if (hardled) { /* NB: handle any sc_ledpin change */ ath_led_config(sc); } sc->sc_hardled = hardled; } return 0; } static int ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int txantenna; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); txantenna = ath_hal_getantennaswitch(sc->sc_ah); error = sysctl_handle_int(oidp, &txantenna, 0, req); if (!error && req->newptr) { /* XXX assumes 2 antenna ports */ if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B) { error = EINVAL; goto finish; } ath_hal_setantennaswitch(sc->sc_ah, txantenna); /* * NB: with the switch locked this isn't meaningful, * but set it anyway so things like radiotap get * consistent info in their data. */ sc->sc_txantenna = txantenna; } finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int defantenna; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); defantenna = ath_hal_getdefantenna(sc->sc_ah); ATH_UNLOCK(sc); error = sysctl_handle_int(oidp, &defantenna, 0, req); if (!error && req->newptr) ath_hal_setdefantenna(sc->sc_ah, defantenna); ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int diversity; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); diversity = ath_hal_getdiversity(sc->sc_ah); error = sysctl_handle_int(oidp, &diversity, 0, req); if (error || !req->newptr) goto finish; if (!ath_hal_setdiversity(sc->sc_ah, diversity)) { error = EINVAL; goto finish; } sc->sc_diversity = diversity; error = 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_diag(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int32_t diag; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); if (!ath_hal_getdiag(sc->sc_ah, &diag)) { error = EINVAL; goto finish; } error = sysctl_handle_int(oidp, &diag, 0, req); if (error || !req->newptr) goto finish; error = !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int32_t scale; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); (void) ath_hal_gettpscale(sc->sc_ah, &scale); error = sysctl_handle_int(oidp, &scale, 0, req); if (error || !req->newptr) goto finish; error = !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : (sc->sc_running) ? ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_NORMAL) : 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int tpc; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); tpc = ath_hal_gettpc(sc->sc_ah); error = sysctl_handle_int(oidp, &tpc, 0, req); if (error || !req->newptr) goto finish; error = !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; struct ath_hal *ah = sc->sc_ah; u_int rfkill; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); rfkill = ath_hal_getrfkill(ah); error = sysctl_handle_int(oidp, &rfkill, 0, req); if (error || !req->newptr) goto finish; if (rfkill == ath_hal_getrfkill(ah)) { /* unchanged */ error = 0; goto finish; } if (!ath_hal_setrfkill(ah, rfkill)) { error = EINVAL; goto finish; } error = sc->sc_running ? ath_reset(sc, ATH_RESET_FULL, HAL_RESET_NORMAL) : 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_txagg(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; int i, t, param = 0; int error; struct ath_buf *bf; error = sysctl_handle_int(oidp, ¶m, 0, req); if (error || !req->newptr) return error; if (param != 1) return 0; printf("no tx bufs (empty list): %d\n", sc->sc_stats.ast_tx_getnobuf); printf("no tx bufs (was busy): %d\n", sc->sc_stats.ast_tx_getbusybuf); printf("aggr single packet: %d\n", sc->sc_aggr_stats.aggr_single_pkt); printf("aggr single packet w/ BAW closed: %d\n", sc->sc_aggr_stats.aggr_baw_closed_single_pkt); printf("aggr non-baw packet: %d\n", sc->sc_aggr_stats.aggr_nonbaw_pkt); printf("aggr aggregate packet: %d\n", sc->sc_aggr_stats.aggr_aggr_pkt); printf("aggr single packet low hwq: %d\n", sc->sc_aggr_stats.aggr_low_hwq_single_pkt); printf("aggr single packet RTS aggr limited: %d\n", sc->sc_aggr_stats.aggr_rts_aggr_limited); printf("aggr sched, no work: %d\n", sc->sc_aggr_stats.aggr_sched_nopkt); for (i = 0; i < 64; i++) { printf("%2d: %10d ", i, sc->sc_aggr_stats.aggr_pkts[i]); if (i % 4 == 3) printf("\n"); } printf("\n"); for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { if (ATH_TXQ_SETUP(sc, i)) { printf("HW TXQ %d: axq_depth=%d, axq_aggr_depth=%d, " "axq_fifo_depth=%d, holdingbf=%p\n", i, sc->sc_txq[i].axq_depth, sc->sc_txq[i].axq_aggr_depth, sc->sc_txq[i].axq_fifo_depth, sc->sc_txq[i].axq_holdingbf); } } i = t = 0; ATH_TXBUF_LOCK(sc); TAILQ_FOREACH(bf, &sc->sc_txbuf, bf_list) { if (bf->bf_flags & ATH_BUF_BUSY) { printf("Busy: %d\n", t); i++; } t++; } ATH_TXBUF_UNLOCK(sc); printf("Total TX buffers: %d; Total TX buffers busy: %d (%d)\n", t, i, sc->sc_txbuf_cnt); i = t = 0; ATH_TXBUF_LOCK(sc); TAILQ_FOREACH(bf, &sc->sc_txbuf_mgmt, bf_list) { if (bf->bf_flags & ATH_BUF_BUSY) { printf("Busy: %d\n", t); i++; } t++; } ATH_TXBUF_UNLOCK(sc); printf("Total mgmt TX buffers: %d; Total mgmt TX buffers busy: %d\n", t, i); ATH_RX_LOCK(sc); for (i = 0; i < 2; i++) { printf("%d: fifolen: %d/%d; head=%d; tail=%d; m_pending=%p, m_holdbf=%p\n", i, sc->sc_rxedma[i].m_fifo_depth, sc->sc_rxedma[i].m_fifolen, sc->sc_rxedma[i].m_fifo_head, sc->sc_rxedma[i].m_fifo_tail, sc->sc_rxedma[i].m_rxpending, sc->sc_rxedma[i].m_holdbf); } i = 0; TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { i++; } printf("Total RX buffers in free list: %d buffers\n", i); ATH_RX_UNLOCK(sc); return 0; } static int ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int rfsilent; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent); error = sysctl_handle_int(oidp, &rfsilent, 0, req); if (error || !req->newptr) goto finish; if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) { error = EINVAL; goto finish; } /* * Earlier chips (< AR5212) have up to 8 GPIO * pins exposed. * * AR5416 and later chips have many more GPIO * pins (up to 16) so the mask is expanded to * four bits. */ sc->sc_rfsilentpin = rfsilent & 0x3c; sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; error = 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int32_t tpack; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); (void) ath_hal_gettpack(sc->sc_ah, &tpack); error = sysctl_handle_int(oidp, &tpack, 0, req); if (error || !req->newptr) goto finish; error = !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; u_int32_t tpcts; int error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); (void) ath_hal_gettpcts(sc->sc_ah, &tpcts); error = sysctl_handle_int(oidp, &tpcts, 0, req); if (error || !req->newptr) goto finish; error = !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } static int ath_sysctl_intmit(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; int intmit, error; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); intmit = ath_hal_getintmit(sc->sc_ah); error = sysctl_handle_int(oidp, &intmit, 0, req); if (error || !req->newptr) goto finish; /* reusing error; 1 here means "good"; 0 means "fail" */ error = ath_hal_setintmit(sc->sc_ah, intmit); if (! error) { error = EINVAL; goto finish; } /* * Reset the hardware here - disabling ANI in the HAL * doesn't reset ANI related registers, so it'll leave * things in an inconsistent state. */ if (sc->sc_running) ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_NORMAL); error = 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } #ifdef IEEE80211_SUPPORT_TDMA static int ath_sysctl_setcca(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; int setcca, error; setcca = sc->sc_setcca; error = sysctl_handle_int(oidp, &setcca, 0, req); if (error || !req->newptr) return error; sc->sc_setcca = (setcca != 0); return 0; } #endif /* IEEE80211_SUPPORT_TDMA */ static int ath_sysctl_forcebstuck(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; int val = 0; int error; error = sysctl_handle_int(oidp, &val, 0, req); if (error || !req->newptr) return error; if (val == 0) return 0; taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); val = 0; return 0; } static int ath_sysctl_hangcheck(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; int val = 0; int error; uint32_t mask = 0xffffffff; uint32_t *sp; uint32_t rsize; struct ath_hal *ah = sc->sc_ah; error = sysctl_handle_int(oidp, &val, 0, req); if (error || !req->newptr) return error; if (val == 0) return 0; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); ATH_UNLOCK(sc); /* Do a hang check */ if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), (void *) &sp, &rsize)) { error = 0; goto finish; } device_printf(sc->sc_dev, "%s: sp=0x%08x\n", __func__, *sp); val = 0; error = 0; finish: ATH_LOCK(sc); ath_power_restore_power_state(sc); ATH_UNLOCK(sc); return (error); } #ifdef ATH_DEBUG_ALQ static int ath_sysctl_alq_log(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; int error, enable; enable = (sc->sc_alq.sc_alq_isactive); error = sysctl_handle_int(oidp, &enable, 0, req); if (error || !req->newptr) return (error); else if (enable) error = if_ath_alq_start(&sc->sc_alq); else error = if_ath_alq_stop(&sc->sc_alq); return (error); } /* * Attach the ALQ debugging if required. */ static void ath_sysctl_alq_attach(struct ath_softc *sc) { struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "alq", CTLFLAG_RD, NULL, "Atheros ALQ logging parameters"); child = SYSCTL_CHILDREN(tree); SYSCTL_ADD_STRING(ctx, child, OID_AUTO, "filename", CTLFLAG_RW, sc->sc_alq.sc_alq_filename, 0, "ALQ filename"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "enable", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_alq_log, "I", ""); SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debugmask", CTLFLAG_RW, &sc->sc_alq.sc_alq_debug, 0, "ALQ debug mask"); SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "numlost", CTLFLAG_RW, &sc->sc_alq.sc_alq_numlost, 0, "number lost"); } #endif /* ATH_DEBUG_ALQ */ void ath_sysctlattach(struct ath_softc *sc) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); struct ath_hal *ah = sc->sc_ah; SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0, "EEPROM country code"); SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0, "EEPROM regdomain code"); #ifdef ATH_DEBUG SYSCTL_ADD_QUAD(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", CTLFLAG_RW, &sc->sc_debug, "control debugging printfs"); #endif #ifdef ATH_DEBUG_ALQ SYSCTL_ADD_QUAD(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "ktrdebug", CTLFLAG_RW, &sc->sc_ktrdebug, "control debugging KTR"); #endif /* ATH_DEBUG_ALQ */ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_slottime, "I", "802.11 slot time (us)"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_softled, "I", "enable/disable software LED support"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_ledpin, "I", "GPIO pin connected to LED"); SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, "setting to turn LED on"); SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, "idle time for inactivity LED (ticks)"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "hardled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_hardled, "I", "enable/disable hardware LED support"); /* XXX Laziness - configure pins, then flip hardled off/on */ SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "led_net_pin", CTLFLAG_RW, &sc->sc_led_net_pin, 0, "MAC Network LED pin, or -1 to disable"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "led_pwr_pin", CTLFLAG_RW, &sc->sc_led_pwr_pin, 0, "MAC Power LED pin, or -1 to disable"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_txantenna, "I", "antenna switch"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_rxantenna, "I", "default/rx antenna"); if (ath_hal_hasdiversity(ah)) SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_diversity, "I", "antenna diversity"); sc->sc_txintrperiod = ATH_TXINTR_PERIOD; SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, "tx descriptor batching"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_diag, "I", "h/w diagnostic control"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_tpscale, "I", "tx power scaling"); if (ath_hal_hastpc(ah)) { SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_tpack, "I", "tx power for ack frames"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_tpcts, "I", "tx power for cts frames"); } if (ath_hal_hasrfsilent(ah)) { SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_rfsilent, "I", "h/w RF silent config"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); } SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "txagg", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_txagg, "I", ""); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "forcebstuck", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_forcebstuck, "I", ""); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "hangcheck", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_hangcheck, "I", ""); if (ath_hal_hasintmit(ah)) { SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_intmit, "I", "interference mitigation"); } sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, "mask of error frames to pass when monitoring"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "hwq_limit_nonaggr", CTLFLAG_RW, &sc->sc_hwq_limit_nonaggr, 0, "Hardware non-AMPDU queue depth before software-queuing TX frames"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "hwq_limit_aggr", CTLFLAG_RW, &sc->sc_hwq_limit_aggr, 0, "Hardware AMPDU queue depth before software-queuing TX frames"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tid_hwq_lo", CTLFLAG_RW, &sc->sc_tid_hwq_lo, 0, ""); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tid_hwq_hi", CTLFLAG_RW, &sc->sc_tid_hwq_hi, 0, ""); /* Aggregate length twiddles */ SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "aggr_limit", CTLFLAG_RW, &sc->sc_aggr_limit, 0, "Maximum A-MPDU size, or 0 for 'default'"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "rts_aggr_limit", CTLFLAG_RW, &sc->sc_rts_aggr_limit, 0, "Maximum A-MPDU size for RTS-protected frames, or '0' " "for default"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "delim_min_pad", CTLFLAG_RW, &sc->sc_delim_min_pad, 0, "Enforce a minimum number of delimiters per A-MPDU " " sub-frame"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "txq_data_minfree", CTLFLAG_RW, &sc->sc_txq_data_minfree, 0, "Minimum free buffers before adding a data frame" " to the TX queue"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "txq_mcastq_maxdepth", CTLFLAG_RW, &sc->sc_txq_mcastq_maxdepth, 0, "Maximum buffer depth for multicast/broadcast frames"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "txq_node_maxdepth", CTLFLAG_RW, &sc->sc_txq_node_maxdepth, 0, "Maximum buffer depth for a single node"); #if 0 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "cabq_enable", CTLFLAG_RW, &sc->sc_cabq_enable, 0, "Whether to transmit on the CABQ or not"); #endif #ifdef IEEE80211_SUPPORT_TDMA if (ath_hal_macversion(ah) > 0x78) { sc->sc_tdmadbaprep = 2; SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "dbaprep", CTLFLAG_RW, &sc->sc_tdmadbaprep, 0, "TDMA DBA preparation time"); sc->sc_tdmaswbaprep = 10; SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "swbaprep", CTLFLAG_RW, &sc->sc_tdmaswbaprep, 0, "TDMA SWBA preparation time"); SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "guardtime", CTLFLAG_RW, &sc->sc_tdmaguard, 0, "TDMA slot guard time"); SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "superframe", CTLFLAG_RD, &sc->sc_tdmabintval, 0, "TDMA calculated super frame"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "setcca", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_setcca, "I", "enable CCA control"); } #endif #ifdef ATH_DEBUG_ALQ ath_sysctl_alq_attach(sc); #endif } static int ath_sysctl_clearstats(SYSCTL_HANDLER_ARGS) { struct ath_softc *sc = arg1; int val = 0; int error; error = sysctl_handle_int(oidp, &val, 0, req); if (error || !req->newptr) return error; if (val == 0) return 0; /* Not clearing the stats is still valid */ memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); memset(&sc->sc_aggr_stats, 0, sizeof(sc->sc_aggr_stats)); memset(&sc->sc_intr_stats, 0, sizeof(sc->sc_intr_stats)); val = 0; return 0; } static void ath_sysctl_stats_attach_rxphyerr(struct ath_softc *sc, struct sysctl_oid_list *parent) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); int i; char sn[8]; tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx_phy_err", CTLFLAG_RD, NULL, "Per-code RX PHY Errors"); child = SYSCTL_CHILDREN(tree); for (i = 0; i < 64; i++) { snprintf(sn, sizeof(sn), "%d", i); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, sn, CTLFLAG_RD, &sc->sc_stats.ast_rx_phy[i], 0, ""); } } static void ath_sysctl_stats_attach_intr(struct ath_softc *sc, struct sysctl_oid_list *parent) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); int i; char sn[8]; tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "sync_intr", CTLFLAG_RD, NULL, "Sync interrupt statistics"); child = SYSCTL_CHILDREN(tree); for (i = 0; i < 32; i++) { snprintf(sn, sizeof(sn), "%d", i); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, sn, CTLFLAG_RD, &sc->sc_intr_stats.sync_intr[i], 0, ""); } } void ath_sysctl_stats_attach(struct ath_softc *sc) { struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); /* Create "clear" node */ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "clear_stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, ath_sysctl_clearstats, "I", "clear stats"); /* Create stats node */ tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, NULL, "Statistics"); child = SYSCTL_CHILDREN(tree); /* This was generated from if_athioctl.h */ SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_watchdog", CTLFLAG_RD, &sc->sc_stats.ast_watchdog, 0, "device reset by watchdog"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_hardware", CTLFLAG_RD, &sc->sc_stats.ast_hardware, 0, "fatal hardware error interrupts"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss", CTLFLAG_RD, &sc->sc_stats.ast_bmiss, 0, "beacon miss interrupts"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss_phantom", CTLFLAG_RD, &sc->sc_stats.ast_bmiss_phantom, 0, "beacon miss interrupts"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bstuck", CTLFLAG_RD, &sc->sc_stats.ast_bstuck, 0, "beacon stuck interrupts"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxorn", CTLFLAG_RD, &sc->sc_stats.ast_rxorn, 0, "rx overrun interrupts"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxeol", CTLFLAG_RD, &sc->sc_stats.ast_rxeol, 0, "rx eol interrupts"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_txurn", CTLFLAG_RD, &sc->sc_stats.ast_txurn, 0, "tx underrun interrupts"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_mib", CTLFLAG_RD, &sc->sc_stats.ast_mib, 0, "mib interrupts"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_intrcoal", CTLFLAG_RD, &sc->sc_stats.ast_intrcoal, 0, "interrupts coalesced"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_packets", CTLFLAG_RD, &sc->sc_stats.ast_tx_packets, 0, "packet sent on the interface"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_mgmt", CTLFLAG_RD, &sc->sc_stats.ast_tx_mgmt, 0, "management frames transmitted"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_discard", CTLFLAG_RD, &sc->sc_stats.ast_tx_discard, 0, "frames discarded prior to assoc"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qstop", CTLFLAG_RD, &sc->sc_stats.ast_tx_qstop, 0, "output stopped 'cuz no buffer"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_encap", CTLFLAG_RD, &sc->sc_stats.ast_tx_encap, 0, "tx encapsulation failed"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nonode", CTLFLAG_RD, &sc->sc_stats.ast_tx_nonode, 0, "tx failed 'cuz no node"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nombuf", CTLFLAG_RD, &sc->sc_stats.ast_tx_nombuf, 0, "tx failed 'cuz no mbuf"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nomcl", CTLFLAG_RD, &sc->sc_stats.ast_tx_nomcl, 0, "tx failed 'cuz no cluster"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_linear", CTLFLAG_RD, &sc->sc_stats.ast_tx_linear, 0, "tx linearized to cluster"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nodata", CTLFLAG_RD, &sc->sc_stats.ast_tx_nodata, 0, "tx discarded empty frame"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_busdma", CTLFLAG_RD, &sc->sc_stats.ast_tx_busdma, 0, "tx failed for dma resrcs"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_xretries", CTLFLAG_RD, &sc->sc_stats.ast_tx_xretries, 0, "tx failed 'cuz too many retries"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_fifoerr", CTLFLAG_RD, &sc->sc_stats.ast_tx_fifoerr, 0, "tx failed 'cuz FIFO underrun"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_filtered", CTLFLAG_RD, &sc->sc_stats.ast_tx_filtered, 0, "tx failed 'cuz xmit filtered"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortretry", CTLFLAG_RD, &sc->sc_stats.ast_tx_shortretry, 0, "tx on-chip retries (short)"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_longretry", CTLFLAG_RD, &sc->sc_stats.ast_tx_longretry, 0, "tx on-chip retries (long)"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_badrate", CTLFLAG_RD, &sc->sc_stats.ast_tx_badrate, 0, "tx failed 'cuz bogus xmit rate"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_noack", CTLFLAG_RD, &sc->sc_stats.ast_tx_noack, 0, "tx frames with no ack marked"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_rts", CTLFLAG_RD, &sc->sc_stats.ast_tx_rts, 0, "tx frames with rts enabled"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_cts", CTLFLAG_RD, &sc->sc_stats.ast_tx_cts, 0, "tx frames with cts enabled"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortpre", CTLFLAG_RD, &sc->sc_stats.ast_tx_shortpre, 0, "tx frames with short preamble"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_altrate", CTLFLAG_RD, &sc->sc_stats.ast_tx_altrate, 0, "tx frames with alternate rate"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_protect", CTLFLAG_RD, &sc->sc_stats.ast_tx_protect, 0, "tx frames with protection"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsburst", CTLFLAG_RD, &sc->sc_stats.ast_tx_ctsburst, 0, "tx frames with cts and bursting"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsext", CTLFLAG_RD, &sc->sc_stats.ast_tx_ctsext, 0, "tx frames with cts extension"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_nombuf", CTLFLAG_RD, &sc->sc_stats.ast_rx_nombuf, 0, "rx setup failed 'cuz no mbuf"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_busdma", CTLFLAG_RD, &sc->sc_stats.ast_rx_busdma, 0, "rx setup failed for dma resrcs"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_orn", CTLFLAG_RD, &sc->sc_stats.ast_rx_orn, 0, "rx failed 'cuz of desc overrun"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_crcerr", CTLFLAG_RD, &sc->sc_stats.ast_rx_crcerr, 0, "rx failed 'cuz of bad CRC"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_fifoerr", CTLFLAG_RD, &sc->sc_stats.ast_rx_fifoerr, 0, "rx failed 'cuz of FIFO overrun"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badcrypt", CTLFLAG_RD, &sc->sc_stats.ast_rx_badcrypt, 0, "rx failed 'cuz decryption"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badmic", CTLFLAG_RD, &sc->sc_stats.ast_rx_badmic, 0, "rx failed 'cuz MIC failure"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_phyerr", CTLFLAG_RD, &sc->sc_stats.ast_rx_phyerr, 0, "rx failed 'cuz of PHY err"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_tooshort", CTLFLAG_RD, &sc->sc_stats.ast_rx_tooshort, 0, "rx discarded 'cuz frame too short"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_toobig", CTLFLAG_RD, &sc->sc_stats.ast_rx_toobig, 0, "rx discarded 'cuz frame too large"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_packets", CTLFLAG_RD, &sc->sc_stats.ast_rx_packets, 0, "packet recv on the interface"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_mgt", CTLFLAG_RD, &sc->sc_stats.ast_rx_mgt, 0, "management frames received"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_ctl", CTLFLAG_RD, &sc->sc_stats.ast_rx_ctl, 0, "rx discarded 'cuz ctl frame"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_xmit", CTLFLAG_RD, &sc->sc_stats.ast_be_xmit, 0, "beacons transmitted"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_nombuf", CTLFLAG_RD, &sc->sc_stats.ast_be_nombuf, 0, "beacon setup failed 'cuz no mbuf"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_cal", CTLFLAG_RD, &sc->sc_stats.ast_per_cal, 0, "periodic calibration calls"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_calfail", CTLFLAG_RD, &sc->sc_stats.ast_per_calfail, 0, "periodic calibration failed"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_rfgain", CTLFLAG_RD, &sc->sc_stats.ast_per_rfgain, 0, "periodic calibration rfgain reset"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_calls", CTLFLAG_RD, &sc->sc_stats.ast_rate_calls, 0, "rate control checks"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_raise", CTLFLAG_RD, &sc->sc_stats.ast_rate_raise, 0, "rate control raised xmit rate"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_drop", CTLFLAG_RD, &sc->sc_stats.ast_rate_drop, 0, "rate control dropped xmit rate"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_defswitch", CTLFLAG_RD, &sc->sc_stats.ast_ant_defswitch, 0, "rx/default antenna switches"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_txswitch", CTLFLAG_RD, &sc->sc_stats.ast_ant_txswitch, 0, "tx antenna switches"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_xmit", CTLFLAG_RD, &sc->sc_stats.ast_cabq_xmit, 0, "cabq frames transmitted"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_busy", CTLFLAG_RD, &sc->sc_stats.ast_cabq_busy, 0, "cabq found busy"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw", CTLFLAG_RD, &sc->sc_stats.ast_tx_raw, 0, "tx frames through raw api"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txok", CTLFLAG_RD, &sc->sc_stats.ast_ff_txok, 0, "fast frames tx'd successfully"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txerr", CTLFLAG_RD, &sc->sc_stats.ast_ff_txerr, 0, "fast frames tx'd w/ error"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_rx", CTLFLAG_RD, &sc->sc_stats.ast_ff_rx, 0, "fast frames rx'd"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_flush", CTLFLAG_RD, &sc->sc_stats.ast_ff_flush, 0, "fast frames flushed from staging q"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qfull", CTLFLAG_RD, &sc->sc_stats.ast_tx_qfull, 0, "tx dropped 'cuz of queue limit"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nobuf", CTLFLAG_RD, &sc->sc_stats.ast_tx_nobuf, 0, "tx dropped 'cuz no ath buffer"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_update", CTLFLAG_RD, &sc->sc_stats.ast_tdma_update, 0, "TDMA slot timing updates"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_timers", CTLFLAG_RD, &sc->sc_stats.ast_tdma_timers, 0, "TDMA slot update set beacon timers"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_tsf", CTLFLAG_RD, &sc->sc_stats.ast_tdma_tsf, 0, "TDMA slot update set TSF"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_ack", CTLFLAG_RD, &sc->sc_stats.ast_tdma_ack, 0, "TDMA tx failed 'cuz ACK required"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw_fail", CTLFLAG_RD, &sc->sc_stats.ast_tx_raw_fail, 0, "raw tx failed 'cuz h/w down"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nofrag", CTLFLAG_RD, &sc->sc_stats.ast_tx_nofrag, 0, "tx dropped 'cuz no ath frag buffer"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_missed", CTLFLAG_RD, &sc->sc_stats.ast_be_missed, 0, "number of -missed- beacons"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ani_cal", CTLFLAG_RD, &sc->sc_stats.ast_ani_cal, 0, "number of ANI polls"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_agg", CTLFLAG_RD, &sc->sc_stats.ast_rx_agg, 0, "number of aggregate frames received"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_halfgi", CTLFLAG_RD, &sc->sc_stats.ast_rx_halfgi, 0, "number of frames received with half-GI"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_2040", CTLFLAG_RD, &sc->sc_stats.ast_rx_2040, 0, "number of HT/40 frames received"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_pre_crc_err", CTLFLAG_RD, - &sc->sc_stats.ast_rx_pre_crc_err, 0, "number of delimeter-CRC errors detected"); + &sc->sc_stats.ast_rx_pre_crc_err, 0, "number of delimiter-CRC errors detected"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_post_crc_err", CTLFLAG_RD, &sc->sc_stats.ast_rx_post_crc_err, 0, "number of post-delimiter CRC errors detected"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_decrypt_busy_err", CTLFLAG_RD, &sc->sc_stats.ast_rx_decrypt_busy_err, 0, "number of frames received w/ busy decrypt engine"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_hi_rx_chain", CTLFLAG_RD, &sc->sc_stats.ast_rx_hi_rx_chain, 0, ""); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_htprotect", CTLFLAG_RD, &sc->sc_stats.ast_tx_htprotect, 0, "HT tx frames with protection"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_hitqueueend", CTLFLAG_RD, &sc->sc_stats.ast_rx_hitqueueend, 0, "RX hit queue end"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_timeout", CTLFLAG_RD, &sc->sc_stats.ast_tx_timeout, 0, "TX Global Timeout"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_cst", CTLFLAG_RD, &sc->sc_stats.ast_tx_cst, 0, "TX Carrier Sense Timeout"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_xtxop", CTLFLAG_RD, &sc->sc_stats.ast_tx_xtxop, 0, "TX exceeded TXOP"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_timerexpired", CTLFLAG_RD, &sc->sc_stats.ast_tx_timerexpired, 0, "TX exceeded TX_TIMER register"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_desccfgerr", CTLFLAG_RD, &sc->sc_stats.ast_tx_desccfgerr, 0, "TX Descriptor Cfg Error"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_swretries", CTLFLAG_RD, &sc->sc_stats.ast_tx_swretries, 0, "TX software retry count"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_swretrymax", CTLFLAG_RD, &sc->sc_stats.ast_tx_swretrymax, 0, "TX software retry max reached"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_data_underrun", CTLFLAG_RD, &sc->sc_stats.ast_tx_data_underrun, 0, ""); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_delim_underrun", CTLFLAG_RD, &sc->sc_stats.ast_tx_delim_underrun, 0, ""); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_aggr_failall", CTLFLAG_RD, &sc->sc_stats.ast_tx_aggr_failall, 0, "Number of aggregate TX failures (whole frame)"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_aggr_ok", CTLFLAG_RD, &sc->sc_stats.ast_tx_aggr_ok, 0, "Number of aggregate TX OK completions (subframe)"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_aggr_fail", CTLFLAG_RD, &sc->sc_stats.ast_tx_aggr_fail, 0, "Number of aggregate TX failures (subframe)"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_intr", CTLFLAG_RD, &sc->sc_stats.ast_rx_intr, 0, "RX interrupts"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_intr", CTLFLAG_RD, &sc->sc_stats.ast_tx_intr, 0, "TX interrupts"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_mcastq_overflow", CTLFLAG_RD, &sc->sc_stats.ast_tx_mcastq_overflow, 0, "Number of multicast frames exceeding maximum mcast queue depth"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_keymiss", CTLFLAG_RD, &sc->sc_stats.ast_rx_keymiss, 0, ""); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_swfiltered", CTLFLAG_RD, &sc->sc_stats.ast_tx_swfiltered, 0, ""); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nodeq_overflow", CTLFLAG_RD, &sc->sc_stats.ast_tx_nodeq_overflow, 0, "tx dropped 'cuz nodeq overflow"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_stbc", CTLFLAG_RD, &sc->sc_stats.ast_rx_stbc, 0, "Number of STBC frames received"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_stbc", CTLFLAG_RD, &sc->sc_stats.ast_tx_stbc, 0, "Number of STBC frames transmitted"); SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ldpc", CTLFLAG_RD, &sc->sc_stats.ast_tx_ldpc, 0, "Number of LDPC frames transmitted"); /* Attach the RX phy error array */ ath_sysctl_stats_attach_rxphyerr(sc, child); /* Attach the interrupt statistics array */ ath_sysctl_stats_attach_intr(sc, child); } /* * This doesn't necessarily belong here (because it's HAL related, not * driver related). */ void ath_sysctl_hal_attach(struct ath_softc *sc) { struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "hal", CTLFLAG_RD, NULL, "Atheros HAL parameters"); child = SYSCTL_CHILDREN(tree); sc->sc_ah->ah_config.ah_debug = 0; SYSCTL_ADD_INT(ctx, child, OID_AUTO, "debug", CTLFLAG_RW, &sc->sc_ah->ah_config.ah_debug, 0, "Atheros HAL debugging printfs"); sc->sc_ah->ah_config.ah_ar5416_biasadj = 0; SYSCTL_ADD_INT(ctx, child, OID_AUTO, "ar5416_biasadj", CTLFLAG_RW, &sc->sc_ah->ah_config.ah_ar5416_biasadj, 0, "Enable 2GHz AR5416 direction sensitivity bias adjust"); sc->sc_ah->ah_config.ah_dma_beacon_response_time = 2; SYSCTL_ADD_INT(ctx, child, OID_AUTO, "dma_brt", CTLFLAG_RW, &sc->sc_ah->ah_config.ah_dma_beacon_response_time, 0, "Atheros HAL DMA beacon response time"); sc->sc_ah->ah_config.ah_sw_beacon_response_time = 10; SYSCTL_ADD_INT(ctx, child, OID_AUTO, "sw_brt", CTLFLAG_RW, &sc->sc_ah->ah_config.ah_sw_beacon_response_time, 0, "Atheros HAL software beacon response time"); sc->sc_ah->ah_config.ah_additional_swba_backoff = 0; SYSCTL_ADD_INT(ctx, child, OID_AUTO, "swba_backoff", CTLFLAG_RW, &sc->sc_ah->ah_config.ah_additional_swba_backoff, 0, "Atheros HAL additional SWBA backoff time"); sc->sc_ah->ah_config.ah_force_full_reset = 0; SYSCTL_ADD_INT(ctx, child, OID_AUTO, "force_full_reset", CTLFLAG_RW, &sc->sc_ah->ah_config.ah_force_full_reset, 0, "Force full chip reset rather than a warm reset"); /* * This is initialised by the driver. */ SYSCTL_ADD_INT(ctx, child, OID_AUTO, "serialise_reg_war", CTLFLAG_RW, &sc->sc_ah->ah_config.ah_serialise_reg_war, 0, "Force register access serialisation"); } diff --git a/sys/dev/ath/if_ath_tx_ht.c b/sys/dev/ath/if_ath_tx_ht.c index 7c7a5ac493f6..1af1ec9120c7 100644 --- a/sys/dev/ath/if_ath_tx_ht.c +++ b/sys/dev/ath/if_ath_tx_ht.c @@ -1,1042 +1,1042 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include "opt_inet.h" #include "opt_ath.h" #include "opt_wlan.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef IEEE80211_SUPPORT_SUPERG #include #endif #ifdef IEEE80211_SUPPORT_TDMA #include #endif #include #ifdef INET #include #include #endif #include #include /* XXX for softled */ #include #ifdef ATH_TX99_DIAG #include #endif #include /* XXX for some support functions */ #include #include #include /* * XXX net80211? */ #define IEEE80211_AMPDU_SUBFRAME_DEFAULT 32 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */ #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ /* number of delimiters for encryption padding */ #define ATH_AGGR_ENCRYPTDELIM 10 /* * returns delimiter padding required given the packet length */ #define ATH_AGGR_GET_NDELIM(_len) \ (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) int ath_max_4ms_framelen[4][32] = { [MCS_HT20] = { 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172, 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280, 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532, 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532, }, [MCS_HT20_SGI] = { 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744, 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532, 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532, 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532, }, [MCS_HT40] = { 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532, 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532, 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532, 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532, }, [MCS_HT40_SGI] = { 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532, 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532, 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532, 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532, } }; /* * XXX should be in net80211 */ static int ieee80211_mpdudensity_map[] = { 0, /* IEEE80211_HTCAP_MPDUDENSITY_NA */ 25, /* IEEE80211_HTCAP_MPDUDENSITY_025 */ 50, /* IEEE80211_HTCAP_MPDUDENSITY_05 */ 100, /* IEEE80211_HTCAP_MPDUDENSITY_1 */ 200, /* IEEE80211_HTCAP_MPDUDENSITY_2 */ 400, /* IEEE80211_HTCAP_MPDUDENSITY_4 */ 800, /* IEEE80211_HTCAP_MPDUDENSITY_8 */ 1600, /* IEEE80211_HTCAP_MPDUDENSITY_16 */ }; /* * XXX should be in the HAL/net80211 ? */ #define BITS_PER_BYTE 8 #define OFDM_PLCP_BITS 22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x7f) #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) #define L_STF 8 #define L_LTF 8 #define L_SIG 4 #define HT_SIG 8 #define HT_STF 4 #define HT_LTF(_ns) (4 * (_ns)) #define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) #define IS_HT_RATE(_rate) ((_rate) & 0x80) const uint32_t bits_per_symbol[][2] = { /* 20MHz 40MHz */ { 26, 54 }, // 0: BPSK { 52, 108 }, // 1: QPSK 1/2 { 78, 162 }, // 2: QPSK 3/4 { 104, 216 }, // 3: 16-QAM 1/2 { 156, 324 }, // 4: 16-QAM 3/4 { 208, 432 }, // 5: 64-QAM 2/3 { 234, 486 }, // 6: 64-QAM 3/4 { 260, 540 }, // 7: 64-QAM 5/6 { 52, 108 }, // 8: BPSK { 104, 216 }, // 9: QPSK 1/2 { 156, 324 }, // 10: QPSK 3/4 { 208, 432 }, // 11: 16-QAM 1/2 { 312, 648 }, // 12: 16-QAM 3/4 { 416, 864 }, // 13: 64-QAM 2/3 { 468, 972 }, // 14: 64-QAM 3/4 { 520, 1080 }, // 15: 64-QAM 5/6 { 78, 162 }, // 16: BPSK { 156, 324 }, // 17: QPSK 1/2 { 234, 486 }, // 18: QPSK 3/4 { 312, 648 }, // 19: 16-QAM 1/2 { 468, 972 }, // 20: 16-QAM 3/4 { 624, 1296 }, // 21: 64-QAM 2/3 { 702, 1458 }, // 22: 64-QAM 3/4 { 780, 1620 }, // 23: 64-QAM 5/6 { 104, 216 }, // 24: BPSK { 208, 432 }, // 25: QPSK 1/2 { 312, 648 }, // 26: QPSK 3/4 { 416, 864 }, // 27: 16-QAM 1/2 { 624, 1296 }, // 28: 16-QAM 3/4 { 832, 1728 }, // 29: 64-QAM 2/3 { 936, 1944 }, // 30: 64-QAM 3/4 { 1040, 2160 }, // 31: 64-QAM 5/6 }; /* * Fill in the rate array information based on the current * node configuration and the choices made by the rate * selection code and ath_buf setup code. * * Later on, this may end up also being made by the * rate control code, but for now it can live here. * * This needs to be called just before the packet is * queued to the software queue or hardware queue, * so all of the needed fields in bf_state are setup. */ void ath_tx_rate_fill_rcflags(struct ath_softc *sc, struct ath_buf *bf) { struct ieee80211_node *ni = bf->bf_node; struct ieee80211vap *vap = ni->ni_vap; struct ieee80211com *ic = ni->ni_ic; const HAL_RATE_TABLE *rt = sc->sc_currates; struct ath_rc_series *rc = bf->bf_state.bfs_rc; uint8_t rate; int i; int do_ldpc; int do_stbc; /* * We only do LDPC if the rate is 11n, both we and the * receiver support LDPC and it's enabled. * * It's a global flag, not a per-try flag, so we clear * it if any of the rate entries aren't 11n. */ do_ldpc = 0; if ((ni->ni_vap->iv_flags_ht & IEEE80211_FHT_LDPC_TX) && (ni->ni_htcap & IEEE80211_HTCAP_LDPC)) do_ldpc = 1; /* * The 11n duration calculation doesn't know about LDPC, * so don't enable it for positioning. */ if (bf->bf_flags & ATH_BUF_TOA_PROBE) do_ldpc = 0; do_stbc = 0; for (i = 0; i < ATH_RC_NUM; i++) { rc[i].flags = 0; if (rc[i].tries == 0) continue; rate = rt->info[rc[i].rix].rateCode; /* * Only enable short preamble for legacy rates */ if ((! IS_HT_RATE(rate)) && bf->bf_state.bfs_shpream) rate |= rt->info[rc[i].rix].shortPreamble; /* * Save this, used by the TX and completion code */ rc[i].ratecode = rate; if (bf->bf_state.bfs_txflags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) rc[i].flags |= ATH_RC_RTSCTS_FLAG; /* * If we can't do LDPC, don't. */ if (! IS_HT_RATE(rate)) do_ldpc = 0; /* Only enable shortgi, 2040, dual-stream if HT is set */ if (IS_HT_RATE(rate)) { rc[i].flags |= ATH_RC_HT_FLAG; if (ni->ni_chw == 40) rc[i].flags |= ATH_RC_CW40_FLAG; /* * NOTE: Don't do short-gi for positioning frames. * * For now, the ath_hal and net80211 HT duration * calculation rounds up the 11n data txtime * to the nearest multiple of 3.6 microseconds * and doesn't return the fractional part, so * we are always "out" by some amount. */ if (ni->ni_chw == 40 && ic->ic_htcaps & IEEE80211_HTCAP_SHORTGI40 && ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40 && vap->iv_flags_ht & IEEE80211_FHT_SHORTGI40 && (bf->bf_flags & ATH_BUF_TOA_PROBE) == 0) { rc[i].flags |= ATH_RC_SGI_FLAG; } if (ni->ni_chw == 20 && ic->ic_htcaps & IEEE80211_HTCAP_SHORTGI20 && ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20 && vap->iv_flags_ht & IEEE80211_FHT_SHORTGI20 && (bf->bf_flags & ATH_BUF_TOA_PROBE) == 0) { rc[i].flags |= ATH_RC_SGI_FLAG; } /* * If we have STBC TX enabled and the receiver * can receive (at least) 1 stream STBC, AND it's * MCS 0-7, AND we have at least two chains enabled, * and we're not doing positioning, enable STBC. */ if (ic->ic_htcaps & IEEE80211_HTCAP_TXSTBC && (ni->ni_vap->iv_flags_ht & IEEE80211_FHT_STBC_TX) && (ni->ni_htcap & IEEE80211_HTCAP_RXSTBC) && (sc->sc_cur_txchainmask > 1) && (HT_RC_2_STREAMS(rate) == 1) && (bf->bf_flags & ATH_BUF_TOA_PROBE) == 0) { rc[i].flags |= ATH_RC_STBC_FLAG; do_stbc = 1; } /* * Dual / Triple stream rate? */ if (HT_RC_2_STREAMS(rate) == 2) rc[i].flags |= ATH_RC_DS_FLAG; else if (HT_RC_2_STREAMS(rate) == 3) rc[i].flags |= ATH_RC_TS_FLAG; } /* * Calculate the maximum TX power cap for the current * node. */ rc[i].tx_power_cap = ieee80211_get_node_txpower(ni); /* * Calculate the maximum 4ms frame length based * on the MCS rate, SGI and channel width flags. */ if ((rc[i].flags & ATH_RC_HT_FLAG) && (HT_RC_2_MCS(rate) < 32)) { int j; if (rc[i].flags & ATH_RC_CW40_FLAG) { if (rc[i].flags & ATH_RC_SGI_FLAG) j = MCS_HT40_SGI; else j = MCS_HT40; } else { if (rc[i].flags & ATH_RC_SGI_FLAG) j = MCS_HT20_SGI; else j = MCS_HT20; } rc[i].max4msframelen = ath_max_4ms_framelen[j][HT_RC_2_MCS(rate)]; } else rc[i].max4msframelen = 0; DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: i=%d, rate=0x%x, flags=0x%x, max4ms=%d\n", __func__, i, rate, rc[i].flags, rc[i].max4msframelen); } /* * LDPC is a global flag, so ... */ if (do_ldpc) { bf->bf_state.bfs_txflags |= HAL_TXDESC_LDPC; sc->sc_stats.ast_tx_ldpc++; } if (do_stbc) { sc->sc_stats.ast_tx_stbc++; } } /* * Return the number of delimiters to be added to * meet the minimum required mpdudensity. * * Caller should make sure that the rate is HT. * * TODO: is this delimiter calculation supposed to be the * total frame length, the hdr length, the data length (including * delimiters, padding, CRC, etc) or ? * * TODO: this should ensure that the rate control information * HAS been setup for the first rate. * * TODO: ensure this is only called for MCS rates. * * TODO: enforce MCS < 31 */ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_buf *first_bf, uint16_t pktlen, int is_first) { const HAL_RATE_TABLE *rt = sc->sc_currates; struct ieee80211_node *ni = first_bf->bf_node; struct ieee80211vap *vap = ni->ni_vap; int ndelim, mindelim = 0; int mpdudensity; /* in 1/100'th of a microsecond */ int peer_mpdudensity; /* net80211 value */ uint8_t rc, rix, flags; int width, half_gi; uint32_t nsymbits, nsymbols; uint16_t minlen; /* * Get the advertised density from the node. */ peer_mpdudensity = _IEEE80211_MASKSHIFT(ni->ni_htparam, IEEE80211_HTCAP_MPDUDENSITY); /* * vap->iv_ampdu_density is a net80211 value, rather than the actual * density. Larger values are longer A-MPDU density spacing values, * and we want to obey larger configured / negotiated density values * per station if we get it. */ if (vap->iv_ampdu_density > peer_mpdudensity) peer_mpdudensity = vap->iv_ampdu_density; /* * Convert the A-MPDU density net80211 value to a 1/100 microsecond * value for subsequent calculations. */ if (peer_mpdudensity > IEEE80211_HTCAP_MPDUDENSITY_16) mpdudensity = 1600; /* maximum density */ else mpdudensity = ieee80211_mpdudensity_map[peer_mpdudensity]; /* Select standard number of delimiters based on frame length */ ndelim = ATH_AGGR_GET_NDELIM(pktlen); /* * If encryption is enabled, add extra delimiters to let the * crypto hardware catch up. This could be tuned per-MAC and * per-rate, but for now we'll simply assume encryption is * always enabled. * * Also note that the Atheros reference driver inserts two * delimiters by default for pre-AR9380 peers. This will * include "that" required delimiter. */ ndelim += ATH_AGGR_ENCRYPTDELIM; /* - * For AR9380, there's a minimum number of delimeters + * For AR9380, there's a minimum number of delimiters * required when doing RTS. * * XXX TODO: this is only needed if (a) RTS/CTS is enabled for * this exchange, and (b) (done) this is the first sub-frame * in the aggregate. */ if (sc->sc_use_ent && (sc->sc_ent_cfg & AH_ENT_RTSCTS_DELIM_WAR) && ndelim < AH_FIRST_DESC_NDELIMS && is_first) ndelim = AH_FIRST_DESC_NDELIMS; /* * If sc_delim_min_pad is non-zero, enforce it as the minimum * pad delimiter count. */ if (sc->sc_delim_min_pad != 0) ndelim = MAX(ndelim, sc->sc_delim_min_pad); DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: pktlen=%d, ndelim=%d, mpdudensity=%d\n", __func__, pktlen, ndelim, mpdudensity); /* * If the MPDU density is 0, we can return here. * Otherwise, we need to convert the desired mpdudensity * into a byte length, based on the rate in the subframe. */ if (mpdudensity == 0) return ndelim; /* * Convert desired mpdu density from microeconds to bytes based * on highest rate in rate series (i.e. first rate) to determine * required minimum length for subframe. Take into account * whether high rate is 20 or 40Mhz and half or full GI. */ rix = first_bf->bf_state.bfs_rc[0].rix; rc = rt->info[rix].rateCode; flags = first_bf->bf_state.bfs_rc[0].flags; width = !! (flags & ATH_RC_CW40_FLAG); half_gi = !! (flags & ATH_RC_SGI_FLAG); /* * mpdudensity is in 1/100th of a usec, so divide by 100 */ if (half_gi) nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity); else nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity); nsymbols /= 100; if (nsymbols == 0) nsymbols = 1; nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; /* * Min length is the minimum frame length for the * required MPDU density. */ if (pktlen < minlen) { mindelim = (minlen - pktlen) / ATH_AGGR_DELIM_SZ; ndelim = MAX(mindelim, ndelim); } DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: pktlen=%d, minlen=%d, rix=%x, rc=%x, width=%d, hgi=%d, ndelim=%d\n", __func__, pktlen, minlen, rix, rc, width, half_gi, ndelim); return ndelim; } /* * XXX TODO: put into net80211 */ static int ath_rx_ampdu_to_byte(char a) { switch (a) { case IEEE80211_HTCAP_MAXRXAMPDU_16K: return 16384; break; case IEEE80211_HTCAP_MAXRXAMPDU_32K: return 32768; break; case IEEE80211_HTCAP_MAXRXAMPDU_64K: return 65536; break; case IEEE80211_HTCAP_MAXRXAMPDU_8K: default: return 8192; break; } } /* * Fetch the aggregation limit. * * It's the lowest of the four rate series 4ms frame length. * * Also take into account the hardware specific limits (8KiB on AR5416) * and per-peer limits in non-STA mode. */ static int ath_get_aggr_limit(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf) { struct ieee80211vap *vap = ni->ni_vap; int amin = ATH_AGGR_MAXSIZE; int i; /* Extract out the maximum configured driver A-MPDU limit */ if (sc->sc_aggr_limit > 0 && sc->sc_aggr_limit < ATH_AGGR_MAXSIZE) amin = sc->sc_aggr_limit; /* Check the vap configured transmit limit */ amin = MIN(amin, ath_rx_ampdu_to_byte(vap->iv_ampdu_limit)); /* * Check the HTCAP field for the maximum size the node has * negotiated. If it's smaller than what we have, cap it there. */ amin = MIN(amin, ath_rx_ampdu_to_byte( _IEEE80211_MASKSHIFT(ni->ni_htparam, IEEE80211_HTCAP_MAXRXAMPDU))); for (i = 0; i < ATH_RC_NUM; i++) { if (bf->bf_state.bfs_rc[i].tries == 0) continue; amin = MIN(amin, bf->bf_state.bfs_rc[i].max4msframelen); } DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: aggr_limit=%d, iv_ampdu_limit=%d, " "peer maxrxampdu=%d, max frame len=%d\n", __func__, sc->sc_aggr_limit, vap->iv_ampdu_limit, _IEEE80211_MASKSHIFT(ni->ni_htparam, IEEE80211_HTCAP_MAXRXAMPDU), amin); return amin; } /* * Setup a 11n rate series structure * * This should be called for both legacy and MCS rates. * * This uses the rate series stuf from ath_tx_rate_fill_rcflags(). * * It, along with ath_buf_set_rate, must be called -after- a burst * or aggregate is setup. */ static void ath_rateseries_setup(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, HAL_11N_RATE_SERIES *series) { struct ieee80211com *ic = ni->ni_ic; struct ath_hal *ah = sc->sc_ah; HAL_BOOL shortPreamble = AH_FALSE; const HAL_RATE_TABLE *rt = sc->sc_currates; int i; int pktlen; struct ath_rc_series *rc = bf->bf_state.bfs_rc; if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) shortPreamble = AH_TRUE; /* * If this is the first frame in an aggregate series, * use the aggregate length. */ if (bf->bf_state.bfs_aggr) pktlen = bf->bf_state.bfs_al; else pktlen = bf->bf_state.bfs_pktlen; /* * XXX TODO: modify this routine to use the bfs_rc[x].flags * XXX fields. */ memset(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4); for (i = 0; i < ATH_RC_NUM; i++) { /* Only set flags for actual TX attempts */ if (rc[i].tries == 0) continue; series[i].Tries = rc[i].tries; /* * XXX TODO: When the NIC is capable of three stream TX, * transmit 1/2 stream rates on two streams. * * This reduces the power consumption of the NIC and * keeps it within the PCIe slot power limits. */ series[i].ChSel = sc->sc_cur_txchainmask; /* * Setup rate and TX power cap for this series. */ series[i].Rate = rt->info[rc[i].rix].rateCode; series[i].RateIndex = rc[i].rix; series[i].tx_power_cap = rc[i].tx_power_cap; /* * Enable RTS/CTS as appropriate. */ if (rc[i].flags & ATH_RC_RTSCTS_FLAG) series[i].RateFlags |= HAL_RATESERIES_RTS_CTS; /* * 11n rate? Update 11n flags. */ if (rc[i].flags & ATH_RC_HT_FLAG) { if (rc[i].flags & ATH_RC_CW40_FLAG) series[i].RateFlags |= HAL_RATESERIES_2040; if (rc[i].flags & ATH_RC_SGI_FLAG) series[i].RateFlags |= HAL_RATESERIES_HALFGI; if (rc[i].flags & ATH_RC_STBC_FLAG) series[i].RateFlags |= HAL_RATESERIES_STBC; } /* * TODO: If we're all doing 11n rates then we can set LDPC. * If we've been asked to /do/ LDPC but we are handed a * legacy rate, then we should complain. Loudly. */ /* * PktDuration doesn't include slot, ACK, RTS, etc timing - * it's just the packet duration */ if (rc[i].flags & ATH_RC_HT_FLAG) { series[i].PktDuration = ath_computedur_ht(pktlen , series[i].Rate , HT_RC_2_STREAMS(series[i].Rate) , series[i].RateFlags & HAL_RATESERIES_2040 , series[i].RateFlags & HAL_RATESERIES_HALFGI); } else { if (shortPreamble) series[i].Rate |= rt->info[rc[i].rix].shortPreamble; /* XXX TODO: don't include SIFS */ series[i].PktDuration = ath_hal_computetxtime(ah, rt, pktlen, rc[i].rix, shortPreamble, AH_TRUE); } } } #ifdef ATH_DEBUG static void ath_rateseries_print(struct ath_softc *sc, HAL_11N_RATE_SERIES *series) { int i; for (i = 0; i < ATH_RC_NUM; i++) { device_printf(sc->sc_dev ,"series %d: rate %x; tries %d; " "pktDuration %d; chSel %d; txpowcap %d, rateFlags %x\n", i, series[i].Rate, series[i].Tries, series[i].PktDuration, series[i].ChSel, series[i].tx_power_cap, series[i].RateFlags); } } #endif /* * Setup the 11n rate scenario and burst duration for the given TX descriptor * list. * * This isn't useful for sending beacon frames, which has different needs * wrt what's passed into the rate scenario function. */ void ath_buf_set_rate(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf) { HAL_11N_RATE_SERIES series[4]; struct ath_desc *ds = bf->bf_desc; struct ath_hal *ah = sc->sc_ah; int is_pspoll = (bf->bf_state.bfs_atype == HAL_PKT_TYPE_PSPOLL); int ctsrate = bf->bf_state.bfs_ctsrate; int flags = bf->bf_state.bfs_txflags; /* Setup rate scenario */ memset(&series, 0, sizeof(series)); ath_rateseries_setup(sc, ni, bf, series); #ifdef ATH_DEBUG if (sc->sc_debug & ATH_DEBUG_XMIT) ath_rateseries_print(sc, series); #endif /* Set rate scenario */ /* * Note: Don't allow hardware to override the duration on * ps-poll packets. */ ath_hal_set11nratescenario(ah, ds, !is_pspoll, /* whether to override the duration or not */ ctsrate, /* rts/cts rate */ series, /* 11n rate series */ 4, /* number of series */ flags); /* Set burst duration */ /* * This is only required when doing 11n burst, not aggregation * ie, if there's a second frame in a RIFS or A-MPDU burst * w/ >1 A-MPDU frame bursting back to back. * Normal A-MPDU doesn't do bursting -between- aggregates. * * .. and it's highly likely this won't ever be implemented */ //ath_hal_set11nburstduration(ah, ds, 8192); } /* * Form an aggregate packet list. * * This function enforces the aggregate restrictions/requirements. * * These are: * * + The aggregate size maximum (64k for AR9160 and later, 8K for * AR5416 when doing RTS frame protection.) * + Maximum number of sub-frames for an aggregate * + The aggregate delimiter size, giving MACs time to do whatever is * needed before each frame * + Enforce the BAW limit * * Each descriptor queued should have the DMA setup. * The rate series, descriptor setup, linking, etc is all done * externally. This routine simply chains them together. * ath_tx_setds_11n() will take care of configuring the per- * descriptor setup, and ath_buf_set_rate() will configure the * rate control. * * The TID lock is required for the entirety of this function. * * If some code in another thread adds to the head of this * list, very strange behaviour will occur. Since retransmission is the * only reason this will occur, and this routine is designed to be called * from within the scheduler task, it won't ever clash with the completion * task. * * So if you want to call this from an upper layer context (eg, to direct- * dispatch aggregate frames to the hardware), please keep this in mind. */ ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, struct ath_node *an, struct ath_tid *tid, ath_bufhead *bf_q) { //struct ieee80211_node *ni = &an->an_node; struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL; int nframes = 0; uint16_t aggr_limit = 0, al = 0, bpad = 0, al_delta, h_baw; struct ieee80211_tx_ampdu *tap; int status = ATH_AGGR_DONE; int prev_frames = 0; /* XXX for AR5416 burst, not done here */ int prev_al = 0; /* XXX also for AR5416 burst */ ATH_TX_LOCK_ASSERT(sc); tap = ath_tx_get_tx_tid(an, tid->tid); if (tap == NULL) { status = ATH_AGGR_ERROR; goto finish; } /* * Limit the maximum number of frames in this A-MPDU * to half of the window size. This is done to prevent * sending a LOT of frames that may fail in one batch * when operating in higher MCS rates. If there are more * frames available to send then up to two A-MPDUs will * be queued per hardware queue, so we'll "just" get * a second A-MPDU. */ h_baw = tap->txa_wnd / 2; for (;;) { bf = ATH_TID_FIRST(tid); if (bf == NULL) { status = ATH_AGGR_DONE; break; } if (bf_first == NULL) { bf_first = bf; /* * It's the first frame; * set the aggregation limit based on the * rate control decision that has been made. */ aggr_limit = ath_get_aggr_limit(sc, &an->an_node, bf_first); if (bf_first->bf_state.bfs_rc_maxpktlen > 0) { aggr_limit = MIN(aggr_limit, bf_first->bf_state.bfs_rc_maxpktlen); } } /* Set this early just so things don't get confused */ bf->bf_next = NULL; /* * If the frame doesn't have a sequence number that we're * tracking in the BAW (eg NULL QOS data frame), we can't * aggregate it. Stop the aggregation process; the sender * can then TX what's in the list thus far and then * TX the frame individually. */ if (! bf->bf_state.bfs_dobaw) { status = ATH_AGGR_NONAGGR; break; } /* * If any of the rates are non-HT, this packet * can't be aggregated. * XXX TODO: add a bf_state flag which gets marked * if any active rate is non-HT. */ /* * do not exceed aggregation limit */ al_delta = ATH_AGGR_DELIM_SZ + bf->bf_state.bfs_pktlen; if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) { status = ATH_AGGR_LIMITED; break; } /* * If RTS/CTS is set on the first frame, enforce * the RTS aggregate limit. */ if (bf_first->bf_state.bfs_txflags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { if (nframes && (sc->sc_rts_aggr_limit < (al + bpad + al_delta + prev_al))) { status = ATH_AGGR_8K_LIMITED; break; } } /* * Do not exceed subframe limit. */ if ((nframes + prev_frames) >= MIN((h_baw), IEEE80211_AMPDU_SUBFRAME_DEFAULT)) { status = ATH_AGGR_LIMITED; break; } /* * If the current frame has an RTS/CTS configuration * that differs from the first frame, override the * subsequent frame with this config. */ if (bf != bf_first) { bf->bf_state.bfs_txflags &= ~ (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA); bf->bf_state.bfs_txflags |= bf_first->bf_state.bfs_txflags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA); } /* * If the packet has a sequence number, do not * step outside of the block-ack window. */ if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, SEQNO(bf->bf_state.bfs_seqno))) { status = ATH_AGGR_BAW_CLOSED; break; } /* * this packet is part of an aggregate. */ ATH_TID_REMOVE(tid, bf, bf_list); /* The TID lock is required for the BAW update */ ath_tx_addto_baw(sc, an, tid, bf); bf->bf_state.bfs_addedbaw = 1; /* * XXX enforce ACK for aggregate frames (this needs to be * XXX handled more gracefully? */ if (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) { device_printf(sc->sc_dev, "%s: HAL_TXDESC_NOACK set for an aggregate frame?\n", __func__); bf->bf_state.bfs_txflags &= (~HAL_TXDESC_NOACK); } /* * Add the now owned buffer (which isn't * on the software TXQ any longer) to our * aggregate frame list. */ TAILQ_INSERT_TAIL(bf_q, bf, bf_list); nframes ++; /* Completion handler */ bf->bf_comp = ath_tx_aggr_comp; /* * add padding for previous frame to aggregation length */ al += bpad + al_delta; /* * Calculate delimiters needed for the current frame */ bf->bf_state.bfs_ndelim = ath_compute_num_delims(sc, bf_first, bf->bf_state.bfs_pktlen, (bf_first == bf)); /* * Calculate the padding needed from this set of delimiters, * used when calculating if the next frame will fit in * the aggregate. */ bpad = PADBYTES(al_delta) + (bf->bf_state.bfs_ndelim << 2); /* * Chain the buffers together */ if (bf_prev) bf_prev->bf_next = bf; bf_prev = bf; /* * If we're leaking frames, just return at this point; * we've queued a single frame and we don't want to add * any more. */ if (tid->an->an_leak_count) { status = ATH_AGGR_LEAK_CLOSED; break; } #if 0 /* * terminate aggregation on a small packet boundary */ if (bf->bf_state.bfs_pktlen < ATH_AGGR_MINPLEN) { status = ATH_AGGR_SHORTPKT; break; } #endif } finish: /* * Just in case the list was empty when we tried to * dequeue a packet .. */ if (bf_first) { DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: al=%d bytes; requested %d bytes\n", __func__, al, bf_first->bf_state.bfs_rc_maxpktlen); bf_first->bf_state.bfs_al = al; bf_first->bf_state.bfs_nframes = nframes; } return status; }