diff --git a/lib/libpmc/pmc.corei7.3 b/lib/libpmc/pmc.corei7.3 index ec310548d08e..e9e2a6e61784 100644 --- a/lib/libpmc/pmc.corei7.3 +++ b/lib/libpmc/pmc.corei7.3 @@ -1,1576 +1,1606 @@ .\" Copyright (c) 2010 Fabien Thomas. All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd March 24, 2010 .Dt PMC.COREI7 3 .Os .Sh NAME .Nm pmc.corei7 .Nd measurement events for .Tn Intel .Tn Core i7 and Xeon 5500 family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Core i7" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Core i7 and Xeon 5500 PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-033US" .%D December 2009 .%Q "Intel Corporation" .Re .Ss COREI7 AND XEON 5500 FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . Not all CPUs in this family implement fixed-function counters. .Ss COREI7 AND XEON 5500 PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry -cacheline reads. Does not count L2 data read prefetches or -instruction fetches. +cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li DMND_RFO Counts the number of demand and DCU prefetch reads for ownership -(RFO) requests generated by a write to data cacheline. Does not -count L2 RFO. +(RFO) requests generated by a write to data cacheline. +Does not count L2 RFO. .It Li DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline -reads. Does not count L2 code read prefetches. -WB -Counts the number of writeback (modified to exclusive) transactions. +reads. +Does not count L2 code read prefetches. +WB Counts the number of writeback (modified to exclusive) transactions. .It Li PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li OTHER Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock. .It Li UNCORE_HIT L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping). .It Li OTHER_CORE_HIT_SNP L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean). .It Li OTHER_CORE_HITM L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM). .It Li REMOTE_CACHE_FWD L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted) .It Li REMOTE_DRAM L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM. .It Li LOCAL_DRAM L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM. .It Li NON_DRAM Non-DRAM requests that were serviced by IOH. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Core i7 and Xeon 5500 programmable PMCs support the following events: .Bl -tag -width indent .It Li SB_DRAIN.ANY .Pq Event 04H , Umask 07H Counts the number of store buffer drains. .It Li STORE_BLOCKS.AT_RET .Pq Event 06H , Umask 04H -Counts number of loads delayed with at-Retirement block code. The following -loads need to be executed at retirement and wait for all senior stores on -the same thread to be drained: load splitting across 4K boundary (page -split), load accessing uncacheable (UC or USWC) memory, load lock, and load -with page table in UC or USWC memory region. +Counts number of loads delayed with at-Retirement block code. +The following loads need to be executed at retirement and wait for all +senior stores on the same thread to be drained: load splitting across +4K boundary (page split), load accessing uncacheable +(UC or USWC) memory, load lock, and load with page table in UC or USWC memory region. .It Li STORE_BLOCKS.L1D_BLOCK .Pq Event 06H , Umask 08H Cacheable loads delayed with L1D block code .It Li PARTIAL_ADDRESS_ALIAS .Pq Event 07H , Umask 01H Counts false dependency due to partial address aliasing .It Li DTLB_LOAD_MISSES.ANY .Pq Event 08H , Umask 01H Counts all load misses that cause a page walk .It Li DTLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H , Umask 02H Counts number of completed page walks due to load miss in the STLB. .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 10H Number of cache load STLB hits .It Li DTLB_LOAD_MISSES.PDE_MISS .Pq Event 08H , Umask 20H Number of DTLB cache load misses where the low part of the linear to physical address translation was missed. .It Li DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED .Pq Event 08H , Umask 80H Counts number of completed large page walks due to load miss in the STLB. .It Li MEM_INST_RETIRED.LOADS .Pq Event 0BH , Umask 01H Counts the number of instructions with an architecturally-visible store retired on the architected path. In conjunction with ld_lat facility .It Li MEM_INST_RETIRED.STORES .Pq Event 0BH , Umask 02H Counts the number of instructions with an architecturally-visible store retired on the architected path. In conjunction with ld_lat facility .It Li MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD .Pq Event 0BH , Umask 10H Counts the number of instructions exceeding the latency specified with ld_lat facility. In conjunction with ld_lat facility .It Li MEM_STORE_RETIRED.DTLB_MISS .Pq Event 0CH , Umask 01H -The event counts the number of retired stores that missed the DTLB. The DTLB -miss is not counted if the store operation causes a fault. Does not counter -prefetches. Counts both primary and secondary misses to the TLB +The event counts the number of retired stores that missed the DTLB. +The DTLB miss is not counted if the store operation causes a fault. +Does not counter prefetches. +Counts both primary and secondary misses to the TLB .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Counts the number of Uops issued by the Register Allocation Table to the Reservation Station, i.e. the UOPs issued from the front end to the back end. .It Li UOPS_ISSUED.STALLED_CYCLES .Pq Event 0EH , Umask 01H Counts the number of cycles no Uops issued by the Register Allocation Table to the Reservation Station, i.e. the UOPs issued from the front end to the back end. set invert=1, cmask = 1 .It Li UOPS_ISSUED.FUSED .Pq Event 0EH , Umask 02H Counts the number of fused Uops that were issued from the Register Allocation Table to the Reservation Station. .It Li MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN .Pq Event 0FH , Umask 01H Counts number of memory load instructions retired where the memory reference missed L3 and data source is unknown. Available only for CPUID signature 06_2EH .It Li MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM .Pq Event 0FH , Umask 02H Counts number of memory load instructions retired where the memory reference hit modified data in a sibling core residing on the same socket. .It Li MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT .Pq Event 0FH , Umask 08H Counts number of memory load instructions retired where the memory reference -missed the L1, L2 and L3 caches and HIT in a remote socket's cache. Only -counts locally homed lines. +missed the L1, L2 and L3 caches and HIT in a remote socket's cache. +Only counts locally homed lines. .It Li MEM_UNCORE_RETIRED.REMOTE_DRAM .Pq Event 0FH , Umask 10H Counts number of memory load instructions retired where the memory reference -missed the L1, L2 and L3 caches and was remotely homed. This includes both -DRAM access and HITM in a remote socket's cache for remotely homed lines. +missed the L1, L2 and L3 caches and was remotely homed. +This includes both DRAM access and HITM in a remote socket's cache +for remotely homed lines. .It Li MEM_UNCORE_RETIRED.LOCAL_DRAM .Pq Event 0FH , Umask 20H Counts number of memory load instructions retired where the memory reference missed the L1, L2 and L3 caches and required a local socket memory -reference. This includes locally homed cachelines that were in a modified +reference. +This includes locally homed cachelines that were in a modified state in another socket. .It Li MEM_UNCORE_RETIRED.UNCACHEABLE .Pq Event 0FH , Umask 80H Counts number of memory load instructions retired where the memory reference missed the L1, L2 and L3 caches and to perform I/O. Available only for CPUID signature 06_2EH .It Li FP_COMP_OPS_EXE.X87 .Pq Event 10H , Umask 01H -Counts the number of FP Computational Uops Executed. The number of FADD, -FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer -DIVs, and IDIVs. This event does not distinguish an FADD used in the middle -of a transcendental flow from a separate FADD instruction. +Counts the number of FP Computational Uops Executed. +The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer +DIVs, and IDIVs. +This event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction. .It Li FP_COMP_OPS_EXE.MMX .Pq Event 10H , Umask 02H Counts number of MMX Uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP .Pq Event 10H , Umask 04H Counts number of SSE and SSE2 FP uops executed. .It Li FP_COMP_OPS_EXE.SSE2_INTEGER .Pq Event 10H , Umask 08H Counts number of SSE2 integer uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_PACKED .Pq Event 10H , Umask 10H Counts number of SSE FP packed uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR .Pq Event 10H , Umask 20H Counts number of SSE FP scalar uops executed. .It Li FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION .Pq Event 10H , Umask 40H Counts number of SSE* FP single precision uops executed. .It Li FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION .Pq Event 10H , Umask 80H Counts number of SSE* FP double precision uops executed. .It Li SIMD_INT_128.PACKED_MPY .Pq Event 12H , Umask 01H Counts number of 128 bit SIMD integer multiply operations. .It Li SIMD_INT_128.PACKED_SHIFT .Pq Event 12H , Umask 02H Counts number of 128 bit SIMD integer shift operations. .It Li SIMD_INT_128.PACK .Pq Event 12H , Umask 04H Counts number of 128 bit SIMD integer pack operations. .It Li SIMD_INT_128.UNPACK .Pq Event 12H , Umask 08H Counts number of 128 bit SIMD integer unpack operations. .It Li SIMD_INT_128.PACKED_LOGICAL .Pq Event 12H , Umask 10H Counts number of 128 bit SIMD integer logical operations. .It Li SIMD_INT_128.PACKED_ARITH .Pq Event 12H , Umask 20H Counts number of 128 bit SIMD integer arithmetic operations. .It Li SIMD_INT_128.SHUFFLE_MOVE .Pq Event 12H , Umask 40H Counts number of 128 bit SIMD integer shuffle and move operations. .It Li LOAD_DISPATCH.RS .Pq Event 13H , Umask 01H Counts number of loads dispatched from the Reservation Station that bypass the Memory Order Buffer. .It Li LOAD_DISPATCH.RS_DELAYED .Pq Event 13H , Umask 02H -Counts the number of delayed RS dispatches at the stage latch. If an RS -dispatch can not bypass to LB, it has another chance to dispatch from the +Counts the number of delayed RS dispatches at the stage latch. +If an RS dispatch can not bypass to LB, it has another chance to dispatch from the one-cycle delayed staging latch before it is written into the LB. .It Li LOAD_DISPATCH.MOB .Pq Event 13H , Umask 04H Counts the number of loads dispatched from the Reservation Station to the Memory Order Buffer. .It Li LOAD_DISPATCH.ANY .Pq Event 13H , Umask 07H Counts all loads dispatched from the Reservation Station. .It Li ARITH.CYCLES_DIV_BUSY .Pq Event 14H , Umask 01H Counts the number of cycles the divider is busy executing divide or square -root operations. The divide can be integer, X87 or Streaming SIMD Extensions -(SSE). The square root operation can be either X87 or SSE. +root operations. +The divide can be integer, X87 or Streaming SIMD Extensions (SSE). +The square root operation can be either X87 or SSE. Set 'edge =1, invert=1, cmask=1' to count the number of divides. Count may be incorrect When SMT is on. .It Li ARITH.MUL .Pq Event 14H , Umask 02H -Counts the number of multiply operations executed. This includes integer as -well as floating point multiply operations but excludes DPPS mul and MPSAD. +Counts the number of multiply operations executed. +This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect When SMT is on .It Li INST_QUEUE_WRITES .Pq Event 17H , Umask 01H Counts the number of instructions written into the instruction queue every cycle. .It Li INST_DECODED.DEC0 .Pq Event 18H , Umask 01H -Counts number of instructions that require decoder 0 to be decoded. Usually, -this means that the instruction maps to more than 1 uop +Counts number of instructions that require decoder 0 to be decoded. +Usually, this means that the instruction maps to more than 1 uop .It Li TWO_UOP_INSTS_DECODED .Pq Event 19H , Umask 01H An instruction that generates two uops was decoded .It Li INST_QUEUE_WRITE_CYCLES .Pq Event 1EH , Umask 01H This event counts the number of cycles during which instructions are written -to the instruction queue. Dividing this counter by the number of -instructions written to the instruction queue (INST_QUEUE_WRITES) yields the -average number of instructions decoded each cycle. If this number is less -than four and the pipe stalls, this indicates that the decoder is failing to +to the instruction queue. +Dividing this counter by the number of instructions written to the +instruction queue (INST_QUEUE_WRITES) yields the average number of +instructions decoded each cycle. +If this number is less than four and the pipe stalls, this indicates that the decoder is failing to decode enough instructions per cycle to sustain the 4-wide pipeline. If SSE* instructions that are 6 bytes or longer arrive one after another, -then front end throughput may limit execution speed. In such case, +then front end throughput may limit execution speed. +In such case, .It Li LSD_OVERFLOW .Pq Event 20H , Umask 01H Counts number of loops that cant stream from the instruction queue. .It Li L2_RQSTS.LD_HIT .Pq Event 24H , Umask 01H -Counts number of loads that hit the L2 cache. L2 loads include both L1D -demand misses as well as L1D prefetches. L2 loads can be rejected for -various reasons. Only non rejected loads are counted. +Counts number of loads that hit the L2 cache. +L2 loads include both L1D demand misses as well as L1D prefetches. +L2 loads can be rejected for various reasons. +Only non rejected loads are counted. .It Li L2_RQSTS.LD_MISS .Pq Event 24H , Umask 02H -Counts the number of loads that miss the L2 cache. L2 loads include both L1D -demand misses as well as L1D prefetches. +Counts the number of loads that miss the L2 cache. +L2 loads include both L1D demand misses as well as L1D prefetches. .It Li L2_RQSTS.LOADS .Pq Event 24H , Umask 03H -Counts all L2 load requests. L2 loads include both L1D demand misses as well -as L1D prefetches. +Counts all L2 load requests. +L2 loads include both L1D demand misses as well as L1D prefetches. .It Li L2_RQSTS.RFO_HIT .Pq Event 24H , Umask 04H -Counts the number of store RFO requests that hit the L2 cache. L2 RFO -requests include both L1D demand RFO misses as well as L1D RFO prefetches. +Counts the number of store RFO requests that hit the L2 cache. +L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. Count includes WC memory requests, where the data is not fetched but the permission to write the line is required. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H -Counts the number of store RFO requests that miss the L2 cache. L2 RFO -requests include both L1D demand RFO misses as well as L1D RFO prefetches. +Counts the number of store RFO requests that miss the L2 cache. +L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. .It Li L2_RQSTS.RFOS .Pq Event 24H , Umask 0CH -Counts all L2 store RFO requests. L2 RFO requests include both L1D demand -RFO misses as well as L1D RFO prefetches. +Counts all L2 store RFO requests. +L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. .It Li L2_RQSTS.IFETCH_HIT .Pq Event 24H , Umask 10H -Counts number of instruction fetches that hit the L2 cache. L2 instruction -fetches include both L1I demand misses as well as L1I instruction +Counts number of instruction fetches that hit the L2 cache. +L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.IFETCH_MISS .Pq Event 24H , Umask 20H -Counts number of instruction fetches that miss the L2 cache. L2 instruction -fetches include both L1I demand misses as well as L1I instruction +Counts number of instruction fetches that miss the L2 cache. +L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.IFETCHES .Pq Event 24H , Umask 30H -Counts all instruction fetches. L2 instruction fetches include both L1I -demand misses as well as L1I instruction prefetches. +Counts all instruction fetches. +L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.PREFETCH_HIT .Pq Event 24H , Umask 40H Counts L2 prefetch hits for both code and data. .It Li L2_RQSTS.PREFETCH_MISS .Pq Event 24H , Umask 80H Counts L2 prefetch misses for both code and data. .It Li L2_RQSTS.PREFETCHES .Pq Event 24H , Umask C0H Counts all L2 prefetches for both code and data. .It Li L2_RQSTS.MISS .Pq Event 24H , Umask AAH Counts all L2 misses for both code and data. .It Li L2_RQSTS.REFERENCES .Pq Event 24H , Umask FFH Counts all L2 requests for both code and data. .It Li L2_DATA_RQSTS.DEMAND.I_STATE .Pq Event 26H , Umask 01H Counts number of L2 data demand loads where the cache line to be loaded is -in the I (invalid) state, i.e. a cache miss. L2 demand loads are both L1D -demand misses and L1D prefetches. +in the I (invalid) state, i.e. a cache miss. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.S_STATE .Pq Event 26H , Umask 02H Counts number of L2 data demand loads where the cache line to be loaded is -in the S (shared) state. L2 demand loads are both L1D demand misses and L1D -prefetches. +in the S (shared) state. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.E_STATE .Pq Event 26H , Umask 04H Counts number of L2 data demand loads where the cache line to be loaded is -in the E (exclusive) state. L2 demand loads are both L1D demand misses and -L1D prefetches. +in the E (exclusive) state. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.M_STATE .Pq Event 26H , Umask 08H Counts number of L2 data demand loads where the cache line to be loaded is -in the M (modified) state. L2 demand loads are both L1D demand misses and -L1D prefetches. +in the M (modified) state. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.MESI .Pq Event 26H , Umask 0FH -Counts all L2 data demand requests. L2 demand loads are both L1D demand -misses and L1D prefetches. +Counts all L2 data demand requests. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.PREFETCH.I_STATE .Pq Event 26H , Umask 10H Counts number of L2 prefetch data loads where the cache line to be loaded is in the I (invalid) state, i.e. a cache miss. .It Li L2_DATA_RQSTS.PREFETCH.S_STATE .Pq Event 26H , Umask 20H Counts number of L2 prefetch data loads where the cache line to be loaded is -in the S (shared) state. A prefetch RFO will miss on an S state line, while -a prefetch read will hit on an S state line. +in the S (shared) state. +A prefetch RFO will miss on an S state line, while a prefetch read will +hit on an S state line. .It Li L2_DATA_RQSTS.PREFETCH.E_STATE .Pq Event 26H , Umask 40H Counts number of L2 prefetch data loads where the cache line to be loaded is in the E (exclusive) state. .It Li L2_DATA_RQSTS.PREFETCH.M_STATE .Pq Event 26H , Umask 80H Counts number of L2 prefetch data loads where the cache line to be loaded is in the M (modified) state. .It Li L2_DATA_RQSTS.PREFETCH.MESI .Pq Event 26H , Umask F0H Counts all L2 prefetch requests. .It Li L2_DATA_RQSTS.ANY .Pq Event 26H , Umask FFH Counts all L2 data requests. .It Li L2_WRITE.RFO.I_STATE .Pq Event 27H , Umask 01H Counts number of L2 demand store RFO requests where the cache line to be -loaded is in the I (invalid) state, i.e, a cache miss. The L1D prefetcher -does not issue a RFO prefetch. +loaded is in the I (invalid) state, i.e, a cache miss. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.S_STATE .Pq Event 27H , Umask 02H Counts number of L2 store RFO requests where the cache line to be loaded is -in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch,. +in the S (shared) state. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.M_STATE .Pq Event 27H , Umask 08H Counts number of L2 store RFO requests where the cache line to be loaded is -in the M (modified) state. The L1D prefetcher does not issue a RFO prefetch. +in the M (modified) state. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.HIT .Pq Event 27H , Umask 0EH Counts number of L2 store RFO requests where the cache line to be loaded is -in either the S, E or M states. The L1D prefetcher does not issue a RFO -prefetch. +in either the S, E or M states. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.MESI .Pq Event 27H , Umask 0FH -Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO -prefetch. +Counts all L2 store RFO requests. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.LOCK.I_STATE .Pq Event 27H , Umask 10H Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the I (invalid) state, i.e. a cache miss. .It Li L2_WRITE.LOCK.S_STATE .Pq Event 27H , Umask 20H Counts number of L2 lock RFO requests where the cache line to be loaded is in the S (shared) state. .It Li L2_WRITE.LOCK.E_STATE .Pq Event 27H , Umask 40H Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the E (exclusive) state. .It Li L2_WRITE.LOCK.M_STATE .Pq Event 27H , Umask 80H Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the M (modified) state. .It Li L2_WRITE.LOCK.HIT .Pq Event 27H , Umask E0H Counts number of L2 demand lock RFO requests where the cache line to be loaded is in either the S, E, or M state. .It Li L2_WRITE.LOCK.MESI .Pq Event 27H , Umask F0H Counts all L2 demand lock RFO requests. .It Li L1D_WB_L2.I_STATE .Pq Event 28H , Umask 01H Counts number of L1 writebacks to the L2 where the cache line to be written is in the I (invalid) state, i.e. a cache miss. .It Li L1D_WB_L2.S_STATE .Pq Event 28H , Umask 02H Counts number of L1 writebacks to the L2 where the cache line to be written is in the S state. .It Li L1D_WB_L2.E_STATE .Pq Event 28H , Umask 04H Counts number of L1 writebacks to the L2 where the cache line to be written is in the E (exclusive) state. .It Li L1D_WB_L2.M_STATE .Pq Event 28H , Umask 08H Counts number of L1 writebacks to the L2 where the cache line to be written is in the M (modified) state. .It Li L1D_WB_L2.MESI .Pq Event 28H , Umask 0FH Counts all L1 writebacks to the L2. .It Li L3_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache -line in the last level cache. The event count includes speculative traffic -but excludes cache line fills due to a L2 hardware-prefetch. Because cache -hierarchy, cache sizes and other implementation-specific characteristics; -value comparison to estimate performance differences is not recommended. +line in the last level cache. +The event count includes speculative traffic but excludes cache line fills +due to a L2 hardware-prefetch. +Because cache hierarchy, cache sizes and other implementation-specific +characteristics; value comparison to estimate performance differences is not recommended. see Table A-1 .It Li L3_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level -cache. The event count may include speculative traffic but excludes cache -line fills due to L2 hardware-prefetches. Because cache hierarchy, cache -sizes and other implementation-specific characteristics; value comparison to -estimate performance differences is not recommended. +cache. +The event count may include speculative traffic but excludes cache +line fills due to L2 hardware-prefetches. +Because cache hierarchy, cache sizes and other implementation-specific +characteristics; value comparison to estimate performance differences is not recommended. see Table A-1 .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. -The thread enters the halt state when it is running the HLT instruction. The -core frequency may change from time to time due to power or thermal -throttling. +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. see Table A-1 .It Li CPU_CLK_UNHALTED.REF_P .Pq Event 3CH , Umask 01H Increments at the frequency of TSC when not halted. see Table A-1 .It Li L1D_CACHE_LD.I_STATE .Pq Event 40H , Umask 01H Counts L1 data cache read requests where the cache line to be loaded is in the I (invalid) state, i.e. the read request missed the cache. Counter 0, 1 only .It Li L1D_CACHE_LD.S_STATE .Pq Event 40H , Umask 02H Counts L1 data cache read requests where the cache line to be loaded is in the S (shared) state. Counter 0, 1 only .It Li L1D_CACHE_LD.E_STATE .Pq Event 40H , Umask 04H Counts L1 data cache read requests where the cache line to be loaded is in the E (exclusive) state. Counter 0, 1 only .It Li L1D_CACHE_LD.M_STATE .Pq Event 40H , Umask 08H Counts L1 data cache read requests where the cache line to be loaded is in the M (modified) state. Counter 0, 1 only .It Li L1D_CACHE_LD.MESI .Pq Event 40H , Umask 0FH Counts L1 data cache read requests. Counter 0, 1 only .It Li L1D_CACHE_ST.S_STATE .Pq Event 41H , Umask 02H Counts L1 data cache store RFO requests where the cache line to be loaded is in the S (shared) state. Counter 0, 1 only .It Li L1D_CACHE_ST.E_STATE .Pq Event 41H , Umask 04H Counts L1 data cache store RFO requests where the cache line to be loaded is in the E (exclusive) state. Counter 0, 1 only .It Li L1D_CACHE_ST.M_STATE .Pq Event 41H , Umask 08H Counts L1 data cache store RFO requests where cache line to be loaded is in the M (modified) state. Counter 0, 1 only .It Li L1D_CACHE_LOCK.HIT .Pq Event 42H , Umask 01H Counts retired load locks that hit in the L1 data cache or hit in an already -allocated fill buffer. The lock portion of the load lock transaction must -hit in the L1D. -The initial load will pull the lock into the L1 data cache. Counter 0, 1 -only +allocated fill buffer. +The lock portion of the load lock transaction must hit in the L1D. +The initial load will pull the lock into the L1 data cache. +Counter 0, 1 only .It Li L1D_CACHE_LOCK.S_STATE .Pq Event 42H , Umask 02H Counts L1 data cache retired load locks that hit the target cache line in the shared state. Counter 0, 1 only .It Li L1D_CACHE_LOCK.E_STATE .Pq Event 42H , Umask 04H Counts L1 data cache retired load locks that hit the target cache line in the exclusive state. Counter 0, 1 only .It Li L1D_CACHE_LOCK.M_STATE .Pq Event 42H , Umask 08H Counts L1 data cache retired load locks that hit the target cache line in the modified state. Counter 0, 1 only .It Li L1D_ALL_REF.ANY .Pq Event 43H , Umask 01H Counts all references (uncached, speculated and retired) to the L1 data -cache, including all loads and stores with any memory types. The event -counts memory accesses only when they are actually performed. For example, a -load blocked by unknown store address and later performed is only counted -once. +cache, including all loads and stores with any memory types. +The event counts memory accesses only when they are actually performed. +For example, a load blocked by unknown store address and later performed +is only counted once. The event does not include non- memory accesses, such as I/O accesses. Counter 0, 1 only .It Li L1D_ALL_REF.CACHEABLE .Pq Event 43H , Umask 02H Counts all data reads and writes (speculated and retired) from cacheable memory, including locked operations. Counter 0, 1 only .It Li DTLB_MISSES.ANY .Pq Event 49H , Umask 01H Counts the number of misses in the STLB which causes a page walk. .It Li DTLB_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 02H Counts number of misses in the STLB which resulted in a completed page walk. .It Li DTLB_MISSES.STLB_HIT .Pq Event 49H , Umask 10H -Counts the number of DTLB first level misses that hit in the second level -TLB. This event is only relevant if the core contains multiple DTLB levels. +Counts the number of DTLB first level misses that hit in the second level TLB. +This event is only relevant if the core contains multiple DTLB levels. .It Li DTLB_MISSES.PDE_MISS .Pq Event 49H , Umask 20H Number of DTLB misses caused by low part of address, includes references to 2M pages because 2M pages do not use the PDE. .It Li DTLB_MISSES.LARGE_WALK_COMPLETED .Pq Event 49H , Umask 80H Counts number of misses in the STLB which resulted in a completed page walk for large pages. .It Li LOAD_HIT_PRE .Pq Event 4CH , Umask 01H Counts load operations sent to the L1 data cache while a previous SSE prefetch instruction to the same cache line has started prefetching but has not yet finished. .It Li L1D_PREFETCH.REQUESTS .Pq Event 4EH , Umask 01H Counts number of hardware prefetch requests dispatched out of the prefetch FIFO. .It Li L1D_PREFETCH.MISS .Pq Event 4EH , Umask 02H -Counts number of hardware prefetch requests that miss the L1D. There are two -prefetchers in the L1D. A streamer, which predicts lines sequentially after -this one should be fetched, and the IP prefetcher that remembers access -patterns for the current instruction. The streamer prefetcher stops on an -L1D hit, while the IP prefetcher does not. +Counts number of hardware prefetch requests that miss the L1D. +There are two prefetchers in the L1D. +A streamer, which predicts lines sequentially after this one should be fetched, +and the IP prefetcher that remembers access patterns for the current instruction. +The streamer prefetcher stops on an L1D hit, while the IP prefetcher does not. .It Li L1D_PREFETCH.TRIGGERS .Pq Event 4EH , Umask 04H Counts number of prefetch requests triggered by the Finite State Machine and -pushed into the prefetch FIFO. Some of the prefetch requests are dropped due -to overwrites or competition between the IP index prefetcher and streamer -prefetcher. The prefetch FIFO contains 4 entries. +pushed into the prefetch FIFO. +Some of the prefetch requests are dropped due to overwrites or competition between +the IP index prefetcher and streamer prefetcher. +The prefetch FIFO contains 4 entries. .It Li L1D.REPL .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. Counter 0, 1 only .It Li L1D.M_REPL .Pq Event 51H , Umask 02H Counts the number of modified lines brought into the L1 data cache. Counter 0, 1 only .It Li L1D.M_EVICT .Pq Event 51H , Umask 04H Counts the number of modified lines evicted from the L1 data cache due to replacement. Counter 0, 1 only .It Li L1D.M_SNOOP_EVICT .Pq Event 51H , Umask 08H Counts the number of modified lines evicted from the L1 data cache due to snoop HITM intervention. Counter 0, 1 only .It Li L1D_CACHE_PREFETCH_LOCK_FB_HIT .Pq Event 52H , Umask 01H Counts the number of cacheable load lock speculated instructions accepted into the fill buffer. .It Li L1D_CACHE_LOCK_FB_HIT .Pq Event 53H , Umask 01H Counts the number of cacheable load lock speculated or retired instructions accepted into the fill buffer. .It Li CACHE_LOCK_CYCLES.L1D_L2 .Pq Event 63H , Umask 01H -Cycle count during which the L1D and L2 are locked. A lock is asserted when -there is a locked memory access, due to uncacheable memory, a locked +Cycle count during which the L1D and L2 are locked. +A lock is asserted when there is a locked memory access, due to uncacheable memory, a locked operation that spans two cache lines, or a page walk from an uncacheable page table. -Counter 0, 1 only. L1D and L2 locks have a very high performance penalty and -it is highly recommended to avoid such accesses. +Counter 0, 1 only. +L1D and L2 locks have a very high performance penalty and it is highly recommended to +avoid such accesses. .It Li CACHE_LOCK_CYCLES.L1D .Pq Event 63H , Umask 02H Counts the number of cycles that cacheline in the L1 data cache unit is locked. Counter 0, 1 only. .It Li IO_TRANSACTIONS .Pq Event 6CH , Umask 01H Counts the number of completed I/O transactions. .It Li L1I.HITS .Pq Event 80H , Umask 01H Counts all instruction fetches that hit the L1 instruction cache. .It Li L1I.MISSES .Pq Event 80H , Umask 02H -Counts all instruction fetches that miss the L1I cache. This includes -instruction cache misses, streaming buffer misses, victim cache misses and -uncacheable fetches. An instruction fetch miss is counted only once and not -once for every cycle it is outstanding. +Counts all instruction fetches that miss the L1I cache. +This includes instruction cache misses, streaming buffer misses, victim cache misses and +uncacheable fetches. +An instruction fetch miss is counted only once and not once for every cycle +it is outstanding. .It Li L1I.READS .Pq Event 80H , Umask 03H Counts all instruction fetches, including uncacheable fetches that bypass the L1I. .It Li L1I.CYCLES_STALLED .Pq Event 80H , Umask 04H Cycle counts for which an instruction fetch stalls due to a L1I cache miss, ITLB miss or ITLB fault. .It Li LARGE_ITLB.HIT .Pq Event 82H , Umask 01H Counts number of large ITLB hits. .It Li ITLB_MISSES.ANY .Pq Event 85H , Umask 01H Counts the number of misses in all levels of the ITLB which causes a page walk. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 02H Counts number of misses in all levels of the ITLB which resulted in a completed page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Cycles Instruction Length Decoder stalls due to length changing prefixes: 66, 67 or REX.W (for EM64T) instructions which change the length of the decoded instruction. .It Li ILD_STALL.MRU .Pq Event 87H , Umask 02H Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) Most Recently Used (MRU) bypass. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to a full instruction queue. .It Li ILD_STALL.REGEN .Pq Event 87H , Umask 08H Counts the number of regen stalls. .It Li ILD_STALL.ANY .Pq Event 87H , Umask 0FH Counts any cycles the Instruction Length Decoder is stalled. .It Li BR_INST_EXEC.COND .Pq Event 88H , Umask 01H Counts the number of conditional near branch instructions executed, but not necessarily retired. .It Li BR_INST_EXEC.DIRECT .Pq Event 88H , Umask 02H Counts all unconditional near branch instructions excluding calls and indirect branches. .It Li BR_INST_EXEC.INDIRECT_NON_CALL .Pq Event 88H , Umask 04H Counts the number of executed indirect near branch instructions that are not calls. .It Li BR_INST_EXEC.NON_CALLS .Pq Event 88H , Umask 07H Counts all non call near branch instructions executed, but not necessarily retired. .It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H , Umask 08H Counts indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H , Umask 10H Counts unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H , Umask 20H Counts indirect near calls, including both register and memory indirect, executed. .It Li BR_INST_EXEC.NEAR_CALLS .Pq Event 88H , Umask 30H Counts all near call branches executed, but not necessarily retired. .It Li BR_INST_EXEC.TAKEN .Pq Event 88H , Umask 40H Counts taken near branches executed, but not necessarily retired. .It Li BR_INST_EXEC.ANY .Pq Event 88H , Umask 7FH -Counts all near executed branches (not necessarily retired). This includes -only instructions and not micro-op branches. Frequent branching is not -necessarily a major performance issue. However frequent branch -mispredictions may be a problem. +Counts all near executed branches (not necessarily retired). +This includes only instructions and not micro-op branches. +Frequent branching is not necessarily a major performance issue. +However frequent branch mispredictions may be a problem. .It Li BR_MISP_EXEC.COND .Pq Event 89H , Umask 01H Counts the number of mispredicted conditional near branch instructions executed, but not necessarily retired. .It Li BR_MISP_EXEC.DIRECT .Pq Event 89H , Umask 02H Counts mispredicted macro unconditional near branch instructions, excluding calls and indirect branches (should always be 0). .It Li BR_MISP_EXEC.INDIRECT_NON_CALL .Pq Event 89H , Umask 04H Counts the number of executed mispredicted indirect near branch instructions that are not calls. .It Li BR_MISP_EXEC.NON_CALLS .Pq Event 89H , Umask 07H Counts mispredicted non call near branches executed, but not necessarily retired. .It Li BR_MISP_EXEC.RETURN_NEAR .Pq Event 89H , Umask 08H Counts mispredicted indirect branches that have a rear return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H , Umask 10H Counts mispredicted non-indirect near calls executed, (should always be 0). .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H , Umask 20H Counts mispredicted indirect near calls executed, including both register and memory indirect. .It Li BR_MISP_EXEC.NEAR_CALLS .Pq Event 89H , Umask 30H Counts all mispredicted near call branches executed, but not necessarily retired. .It Li BR_MISP_EXEC.TAKEN .Pq Event 89H , Umask 40H Counts executed mispredicted near branches that are taken, but not necessarily retired. .It Li BR_MISP_EXEC.ANY .Pq Event 89H , Umask 7FH Counts the number of mispredicted near branch instructions that were executed, but not necessarily retired. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H -Counts the number of Allocator resource related stalls. Includes register -renaming buffer entries, memory buffer entries. In addition to resource -related stalls, this event counts some other events. Includes stalls arising -during branch misprediction recovery, such as if retirement of the +Counts the number of Allocator resource related stalls. +Includes register renaming buffer entries, memory buffer entries. +In addition to resource related stalls, this event counts some other events. +Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations. Does not include stalls due to SuperQ (off core) queue full, too many cache misses, etc. .It Li RESOURCE_STALLS.LOAD .Pq Event A2H , Umask 02H Counts the cycles of stall due to lack of load buffer for load operation. .It Li RESOURCE_STALLS.RS_FULL .Pq Event A2H , Umask 04H This event counts the number of cycles when the number of instructions in -the pipeline waiting for execution reaches the limit the processor can -handle. A high count of this event indicates that there are long latency +the pipeline waiting for execution reaches the limit the processor can handle. +A high count of this event indicates that there are long latency operations in the pipe (possibly load and store operations that miss the L2 cache, or instructions dependent upon instructions further down the pipeline that have yet to retire. When RS is full, new instructions can not enter the reservation station and start execution. .It Li RESOURCE_STALLS.STORE .Pq Event A2H , Umask 08H This event counts the number of cycles that a resource related stall will occur due to the number of store instructions reaching the limit of the -pipeline, (i.e. all store buffers are used). The stall ends when a store -instruction commits its data to the cache or memory. +pipeline, (i.e. all store buffers are used). +The stall ends when a store instruction commits its data to the cache or memory. .It Li RESOURCE_STALLS.ROB_FULL .Pq Event A2H , Umask 10H Counts the cycles of stall due to re- order buffer full. .It Li RESOURCE_STALLS.FPCW .Pq Event A2H , Umask 20H Counts the number of cycles while execution was stalled due to writing the floating-point unit (FPU) control word. .It Li RESOURCE_STALLS.MXCSR .Pq Event A2H , Umask 40H Stalls due to the MXCSR register rename occurring to close to a previous -MXCSR rename. The MXCSR provides control and status for the MMX registers. +MXCSR rename. +The MXCSR provides control and status for the MMX registers. .It Li RESOURCE_STALLS.OTHER .Pq Event A2H , Umask 80H Counts the number of cycles while execution was stalled due to other resource issues. .It Li MACRO_INSTS.FUSIONS_DECODED .Pq Event A6H , Umask 01H Counts the number of instructions decoded that are macro-fused but not necessarily executed or retired. .It Li BACLEAR_FORCE_IQ .Pq Event A7H , Umask 01H -Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ -is also responsible for providing conditional branch prediction direction +Counts number of times a BACLEAR was forced by the Instruction Queue. +The IQ is also responsible for providing conditional branch prediction direction based on a static scheme and dynamic data provided by the L2 Branch -Prediction Unit. If the conditional branch target is not found in the Target -Array and the IQ predicts that the branch is taken, then the IQ will force -the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by -the BAC generates approximately an 8 cycle bubble in the instruction fetch -pipeline. +Prediction Unit. +If the conditional branch target is not found in the Target Array and the IQ +predicts that the branch is taken, then the IQ will force +the Branch Address Calculator to issue a BACLEAR. +Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble +in the instruction fetch pipeline. .It Li LSD.UOPS .Pq Event A8H , Umask 01H Counts the number of micro-ops delivered by loop stream detector Use cmask=1 and invert to count cycles .It Li ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes .It Li OFFCORE_REQUESTS.L1D_WRITEBACK .Pq Event B0H , Umask 40H Counts number of L1D writebacks to the uncore. .It Li UOPS_EXECUTED.PORT0 .Pq Event B1H , Umask 01H -Counts number of Uops executed that were issued on port 0. Port 0 handles -integer arithmetic, SIMD and FP add Uops. +Counts number of Uops executed that were issued on port 0. +Port 0 handles integer arithmetic, SIMD and FP add Uops. .It Li UOPS_EXECUTED.PORT1 .Pq Event B1H , Umask 02H -Counts number of Uops executed that were issued on port 1. Port 1 handles -integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops. +Counts number of Uops executed that were issued on port 1. +Port 1 handles integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops. .It Li UOPS_EXECUTED.PORT2_CORE .Pq Event B1H , Umask 04H -Counts number of Uops executed that were issued on port 2. Port 2 handles -the load Uops. This is a core count only and can not be collected per -thread. +Counts number of Uops executed that were issued on port 2. +Port 2 handles the load Uops. +This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.PORT3_CORE .Pq Event B1H , Umask 08H -Counts number of Uops executed that were issued on port 3. Port 3 handles -store Uops. This is a core count only and can not be collected per thread. +Counts number of Uops executed that were issued on port 3. +Port 3 handles store Uops. +This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.PORT4_CORE .Pq Event B1H , Umask 10H -Counts number of Uops executed that where issued on port 4. Port 4 handles -the value to be stored for the store Uops issued on port 3. This is a core -count only and can not be collected per thread. +Counts number of Uops executed that where issued on port 4. +Port 4 handles the value to be stored for the store Uops issued on port 3. +This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 .Pq Event B1H , Umask 1FH Counts cycles when the Uops executed were issued from any ports except port -5. Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, +5. +Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls. .It Li UOPS_EXECUTED.PORT5 .Pq Event B1H , Umask 20H Counts number of Uops executed that where issued on port 5. .It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES .Pq Event B1H , Umask 3FH -Counts cycles when the Uops are executing. Use Cmask=1 for active cycles; -Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled +Counts cycles when the Uops are executing. +Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls. .It Li UOPS_EXECUTED.PORT015 .Pq Event B1H , Umask 40H Counts number of Uops executed that where issued on port 0, 1, or 5. use cmask=1, invert=1 to count stall cycles .It Li UOPS_EXECUTED.PORT234 .Pq Event B1H , Umask 80H Counts number of Uops executed that where issued on port 2, 3, or 4. .It Li OFFCORE_REQUESTS_SQ_FULL .Pq Event B2H , Umask 01H Counts number of cycles the SQ is full to handle off-core requests. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H see Section 30.6.1.3, Off-core Response Performance Monitoring in the Processor Core Requires programming MSR 01A6H .It Li SNOOP_RESPONSE.HIT .Pq Event B8H , Umask 01H Counts HIT snoop response sent by this thread in response to a snoop request. .It Li SNOOP_RESPONSE.HITE .Pq Event B8H , Umask 02H Counts HIT E snoop response sent by this thread in response to a snoop request. .It Li SNOOP_RESPONSE.HITM .Pq Event B8H , Umask 04H Counts HIT M snoop response sent by this thread in response to a snoop request. .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H see Section 30.6.1.3, Off-core Response Performance Monitoring in the Processor Core Requires programming MSR 01A7H .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 01H See Table A-1 Notes: INST_RETIRED.ANY is counted by a designated fixed counter. INST_RETIRED.ANY_P is counted by a programmable counter and is an -architectural performance event. Event is supported if CPUID.A.EBX[1] = 0. +architectural performance event. +Event is supported if CPUID.A.EBX[1] = 0. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions. .It Li INST_RETIRED.X87 .Pq Event C0H , Umask 02H Counts the number of MMX instructions retired. .It Li INST_RETIRED.MMX .Pq Event C0H , Umask 04H Counts the number of floating point computational operations retired: floating point computational operations executed by the assist handler and sub-operations of complex floating point instructions like transcendental instructions. .It Li UOPS_RETIRED.ANY .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2, -others=1; maximum count of 8 per cycle). Most instructions are composed of -one or two micro-ops. Some instructions are decoded into longer sequences -such as repeat instructions, floating point transcendental instructions, and -assists. +others=1; maximum count of 8 per cycle). +Most instructions are composed of one or two micro-ops. +Some instructions are decoded into longer sequences such as repeat instructions, +floating point transcendental instructions, and assists. Use cmask=1 and invert to count active cycles or stalled cycles .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle .It Li UOPS_RETIRED.MACRO_FUSED .Pq Event C2H , Umask 04H Counts number of macro-fused uops retired. .It Li MACHINE_CLEARS.CYCLES .Pq Event C3H , Umask 01H Counts the cycles machine clear is asserted. .It Li MACHINE_CLEARS.MEM_ORDER .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Counts the number of times that a program writes to a code section. Self-modifying code causes a sever penalty in all Intel 64 and IA-32 -processors. The modified cache line is written back to the L2 and L3caches. +processors. +The modified cache line is written back to the L2 and L3caches. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H See Table A-1 .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Counts the number of direct & indirect near unconditional calls retired .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H See Table A-1 .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H , Umask 02H Counts mispredicted direct & indirect near unconditional retired calls. .It Li SSEX_UOPS_RETIRED.PACKED_SINGLE .Pq Event C7H , Umask 01H Counts SIMD packed single-precision floating point Uops retired. .It Li SSEX_UOPS_RETIRED.SCALAR_SINGLE .Pq Event C7H , Umask 02H Counts SIMD calar single-precision floating point Uops retired. .It Li SSEX_UOPS_RETIRED.PACKED_DOUBLE .Pq Event C7H , Umask 04H Counts SIMD packed double- precision floating point Uops retired. .It Li SSEX_UOPS_RETIRED.SCALAR_DOUBLE .Pq Event C7H , Umask 08H Counts SIMD scalar double-precision floating point Uops retired. .It Li SSEX_UOPS_RETIRED.VECTOR_INTEGER .Pq Event C7H , Umask 10H Counts 128-bit SIMD vector integer Uops retired. .It Li ITLB_MISS_RETIRED .Pq Event C8H , Umask 20H Counts the number of retired instructions that missed the ITLB when the instruction was fetched. .It Li MEM_LOAD_RETIRED.L1D_HIT .Pq Event CBH , Umask 01H Counts number of retired loads that hit the L1 data cache. .It Li MEM_LOAD_RETIRED.L2_HIT .Pq Event CBH , Umask 02H Counts number of retired loads that hit the L2 data cache. .It Li MEM_LOAD_RETIRED.L3_UNSHARED_HIT .Pq Event CBH , Umask 04H Counts number of retired loads that hit their own, unshared lines in the L3 cache. .It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM .Pq Event CBH , Umask 08H -Counts number of retired loads that hit in a sibling core's L2 (on die -core). Since the L3 is inclusive of all cores on the package, this is an L3 -hit. This counts both clean or modified hits. +Counts number of retired loads that hit in a sibling core's L2 (on die core). +Since the L3 is inclusive of all cores on the package, this is an L3 hit. +This counts both clean or modified hits. .It Li MEM_LOAD_RETIRED.L3_MISS .Pq Event CBH , Umask 10H -Counts number of retired loads that miss the L3 cache. The load was -satisfied by a remote socket, local memory or an IOH. +Counts number of retired loads that miss the L3 cache. +The load was satisfied by a remote socket, local memory or an IOH. .It Li MEM_LOAD_RETIRED.HIT_LFB .Pq Event CBH , Umask 40H Counts number of retired loads that miss the L1D and the address is located -in an allocated line fill buffer and will soon be committed to cache. This -is counting secondary L1D misses. +in an allocated line fill buffer and will soon be committed to cache. +This is counting secondary L1D misses. .It Li MEM_LOAD_RETIRED.DTLB_MISS .Pq Event CBH , Umask 80H -Counts the number of retired loads that missed the DTLB. The DTLB miss is -not counted if the load operation causes a fault. This event counts loads -from cacheable memory only. The event does not count loads by software -prefetches. Counts both primary and secondary misses to the TLB. +Counts the number of retired loads that missed the DTLB. +The DTLB miss is not counted if the load operation causes a fault. +This event counts loads from cacheable memory only. +The event does not count loads by software prefetches. +Counts both primary and secondary misses to the TLB. .It Li FP_MMX_TRANS.TO_FP .Pq Event CCH , Umask 01H Counts the first floating-point instruction following any MMX instruction. You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. .It Li FP_MMX_TRANS.TO_MMX .Pq Event CCH , Umask 02H -Counts the first MMX instruction following a floating-point instruction. You -can use this event to estimate the penalties for the transitions between +Counts the first MMX instruction following a floating-point instruction. +You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. .It Li FP_MMX_TRANS.ANY .Pq Event CCH , Umask 03H Counts all transitions from floating point to MMX instructions and from MMX -instructions to floating point instructions. You can use this event to -estimate the penalties for the transitions between floating-point and MMX -technology states. +instructions to floating point instructions. +You can use this event to estimate the penalties for the transitions between +floating-point and MMX technology states. .It Li MACRO_INSTS.DECODED .Pq Event D0H , Umask 01H Counts the number of instructions decoded, (but not necessarily executed or retired). .It Li UOPS_DECODED.MS .Pq Event D1H , Umask 02H -Counts the number of Uops decoded by the Microcode Sequencer, MS. The MS -delivers uops when the instruction is more than 4 uops long or a microcode +Counts the number of Uops decoded by the Microcode Sequencer, MS. +The MS delivers uops when the instruction is more than 4 uops long or a microcode assist is occurring. .It Li UOPS_DECODED.ESP_FOLDING .Pq Event D1H , Umask 04H Counts number of stack pointer (ESP) instructions decoded: push , pop , call -, ret, etc. ESP instructions do not generate a Uop to increment or decrement -ESP. Instead, they update an ESP_Offset register that keeps track of the +, ret, etc. +ESP instructions do not generate a Uop to increment or decrement ESP. +Instead, they update an ESP_Offset register that keeps track of the delta to the current value of the ESP register. .It Li UOPS_DECODED.ESP_SYNC .Pq Event D1H , Umask 08H Counts number of stack pointer (ESP) sync operations where an ESP instruction is corrected by adding the ESP offset register to the current value of the ESP register. .It Li RAT_STALLS.FLAGS .Pq Event D2H , Umask 01H Counts the number of cycles during which execution stalled due to several -reasons, one of which is a partial flag register stall. A partial register -stall may occur when two conditions are met: 1) an instruction modifies +reasons, one of which is a partial flag register stall. +A partial register stall may occur when two conditions are met: 1) an instruction modifies some, but not all, of the flags in the flag register and 2) the next instruction, which depends on flags, depends on flags that were not modified by this instruction. .It Li RAT_STALLS.REGISTERS .Pq Event D2H , Umask 02H This event counts the number of cycles instruction execution latency became longer than the defined latency because the instruction used a register that was partially written by previous instruction. .It Li RAT_STALLS.ROB_READ_PORT .Pq Event D2H , Umask 04H Counts the number of cycles when ROB read port stalls occurred, which did -not allow new micro-ops to enter the out-of-order pipeline. Note that, at -this stage in the pipeline, additional stalls may occur at the same cycle -and prevent the stalled micro-ops from entering the pipe. In such a case, -micro-ops retry entering the execution pipe in the next cycle and the -ROB-read port stall is counted again. +not allow new micro-ops to enter the out-of-order pipeline. +Note that, at this stage in the pipeline, additional stalls may occur at +the same cycle and prevent the stalled micro-ops from entering the pipe. +In such a case, micro-ops retry entering the execution pipe in the next +cycle and the ROB-read port stall is counted again. .It Li RAT_STALLS.SCOREBOARD .Pq Event D2H , Umask 08H Counts the cycles where we stall due to microarchitecturally required -serialization. Microcode scoreboarding stalls. +serialization. +Microcode scoreboarding stalls. .It Li RAT_STALLS.ANY .Pq Event D2H , Umask 0FH Counts all Register Allocation Table stall cycles due to: Cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the -execution pipe. Cycles when partial register stalls occurred Cycles when -flag stalls occurred Cycles floating-point unit (FPU) status word stalls -occurred. To count each of these conditions separately use the events: +execution pipe. +Cycles when partial register stalls occurred Cycles when flag stalls occurred +Cycles floating-point unit (FPU) status word stalls occurred. +To count each of these conditions separately use the events: RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and RAT_STALLS.FPSW. .It Li SEG_RENAME_STALLS .Pq Event D4H , Umask 01H Counts the number of stall cycles due to the lack of renaming resources for -the ES, DS, FS, and GS segment registers. If a segment is renamed but not -retired and a second update to the same segment occurs, a stall occurs in -the front-end of the pipeline until the renamed segment retires. +the ES, DS, FS, and GS segment registers. +If a segment is renamed but not retired and a second update to the same +segment occurs, a stall occurs in the front-end of the pipeline until the +renamed segment retires. .It Li ES_REG_RENAMES .Pq Event D5H , Umask 01H Counts the number of times the ES segment register is renamed. .It Li UOP_UNFUSION .Pq Event DBH , Umask 01H Counts unfusion events due to floating point exception to a fused uop. .It Li BR_INST_DECODED .Pq Event E0H , Umask 01H Counts the number of branch instructions decoded. .It Li BPU_MISSED_CALL_RET .Pq Event E5H , Umask 01H Counts number of times the Branch Prediction Unit missed predicting a call or return branch. .It Li BACLEAR.CLEAR .Pq Event E6H , Umask 01H Counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is -corrected by the Branch Address Calculator at the front end. This can occur -if the code has many branches such that they cannot be consumed by the BPU. +corrected by the Branch Address Calculator at the front end. +This can occur if the code has many branches such that they cannot be +consumed by the BPU. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble -in the instruction fetch pipeline. The effect on total execution time -depends on the surrounding code. +in the instruction fetch pipeline. +The effect on total execution time depends on the surrounding code. .It Li BACLEAR.BAD_TARGET .Pq Event E6H , Umask 02H Counts number of Branch Address Calculator clears (BACLEAR) asserted due to conditional branch instructions in which there was a target hit but the -direction was wrong. Each BACLEAR asserted by the BAC generates -approximately an 8 cycle bubble in the instruction fetch pipeline. +direction was wrong. +Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in +the instruction fetch pipeline. .It Li BPU_CLEARS.EARLY .Pq Event E8H , Umask 01H Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken branch after incorrectly assuming that it was not taken. The BPU clear leads to 2 cycle bubble in the Front End. .It Li BPU_CLEARS.LATE .Pq Event E8H , Umask 02H -Counts late Branch Prediction Unit clears due to Most Recently Used -conflicts. The PBU clear leads to a 3 cycle bubble in the Front End. +Counts late Branch Prediction Unit clears due to Most Recently Used conflicts. +The PBU clear leads to a 3 cycle bubble in the Front End. .It Li L2_TRANSACTIONS.LOAD .Pq Event F0H , Umask 01H Counts L2 load operations due to HW prefetch or demand loads. .It Li L2_TRANSACTIONS.RFO .Pq Event F0H , Umask 02H Counts L2 RFO operations due to HW prefetch or demand RFOs. .It Li L2_TRANSACTIONS.IFETCH .Pq Event F0H , Umask 04H Counts L2 instruction fetch operations due to HW prefetch or demand ifetch. .It Li L2_TRANSACTIONS.PREFETCH .Pq Event F0H , Umask 08H Counts L2 prefetch operations. .It Li L2_TRANSACTIONS.L1D_WB .Pq Event F0H , Umask 10H Counts L1D writeback operations to the L2. .It Li L2_TRANSACTIONS.FILL .Pq Event F0H , Umask 20H Counts L2 cache line fill operations due to load, RFO, L1D writeback or prefetch. .It Li L2_TRANSACTIONS.WB .Pq Event F0H , Umask 40H Counts L2 writeback operations to the L3. .It Li L2_TRANSACTIONS.ANY .Pq Event F0H , Umask 80H Counts all L2 cache operations. .It Li L2_LINES_IN.S_STATE .Pq Event F1H , Umask 02H Counts the number of cache lines allocated in the L2 cache in the S (shared) state. .It Li L2_LINES_IN.E_STATE .Pq Event F1H , Umask 04H Counts the number of cache lines allocated in the L2 cache in the E (exclusive) state. .It Li L2_LINES_IN.ANY .Pq Event F1H , Umask 07H Counts the number of cache lines allocated in the L2 cache. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 01H Counts L2 clean cache lines evicted by a demand request. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 02H Counts L2 dirty (modified) cache lines evicted by a demand request. .It Li L2_LINES_OUT.PREFETCH_CLEAN .Pq Event F2H , Umask 04H Counts L2 clean cache line evicted by a prefetch request. .It Li L2_LINES_OUT.PREFETCH_DIRTY .Pq Event F2H , Umask 08H Counts L2 modified cache line evicted by a prefetch request. .It Li L2_LINES_OUT.ANY .Pq Event F2H , Umask 0FH Counts all L2 cache lines evicted for any reason. .It Li SQ_MISC.SPLIT_LOCK .Pq Event F4H , Umask 10H Counts the number of SQ lock splits across a cache line. .It Li SQ_FULL_STALL_CYCLES .Pq Event F6H , Umask 01H -Counts cycles the Super Queue is full. Neither of the threads on this core -will be able to access the uncore. +Counts cycles the Super Queue is full. +Neither of the threads on this core will be able to access the uncore. .It Li FP_ASSIST.ALL .Pq Event F7H , Umask 01H Counts the number of floating point operations executed that required -micro-code assist intervention. Assists are required in the following cases: +micro-code assist intervention. +Assists are required in the following cases: SSE instructions, (Denormal input when the DAZ flag is off or Underflow result when the FTZ flag is off): x87 instructions, (NaN or denormal are loaded to a register or used as input from memory, Division by 0 or Underflow output). .It Li FP_ASSIST.OUTPUT .Pq Event F7H , Umask 02H Counts number of floating point micro-code assist when the output value (destination register) is invalid. .It Li FP_ASSIST.INPUT .Pq Event F7H , Umask 04H Counts number of floating point micro-code assist when the input value (one of the source operands to an FP instruction) is invalid. .It Li SIMD_INT_64.PACKED_MPY .Pq Event FDH , Umask 01H Counts number of SID integer 64 bit packed multiply operations. .It Li SIMD_INT_64.PACKED_SHIFT .Pq Event FDH , Umask 02H Counts number of SID integer 64 bit packed shift operations. .It Li SIMD_INT_64.PACK .Pq Event FDH , Umask 04H Counts number of SID integer 64 bit pack operations. .It Li SIMD_INT_64.UNPACK .Pq Event FDH , Umask 08H Counts number of SID integer 64 bit unpack operations. .It Li SIMD_INT_64.PACKED_LOGICAL .Pq Event FDH , Umask 10H Counts number of SID integer 64 bit logical operations. .It Li SIMD_INT_64.PACKED_ARITH .Pq Event FDH , Umask 20H Counts number of SID integer 64 bit arithmetic operations. .It Li SIMD_INT_64.SHUFFLE_MOVE .Pq Event FDH , Umask 40H Counts number of SID integer 64 bit shift or move operations. .El .Ss Event Specifiers (Programmable PMCs) Core i7 and Xeon 5500 programmable PMCs support the following events as June 2009 document (removed in December 2009): .Bl -tag -width indent .It Li SB_FORWARD.ANY .Pq Event 02H , Umask 01H Counts the number of store forwards. .It Li LOAD_BLOCK.STD .Pq Event 03H , Umask 01H Counts the number of loads blocked by a preceding store with unknown data. .It Li LOAD_BLOCK.ADDRESS_OFFSET .Pq Event 03H , Umask 04H Counts the number of loads blocked by a preceding store address. .It Li LOAD_BLOCK.ADDRESS_OFFSET .Pq Event 01H , Umask 04H Counts the cycles of store buffer drains. .It Li MISALIGN_MEM_REF.LOAD .Pq Event 05H , Umask 01H Counts the number of misaligned load references .It Li MISALIGN_MEM_REF.STORE .Pq Event 05H , Umask 02H Counts the number of misaligned store references .It Li MISALIGN_MEM_REF.ANY .Pq Event 05H , Umask 03H Counts the number of misaligned memory references .It Li STORE_BLOCKS.NOT_STA .Pq Event 06H , Umask 01H This event counts the number of load operations delayed caused by preceding stores whose addresses are known but whose data is unknown, and preceding stores that conflict with the load but which incompletely overlap the load. .It Li STORE_BLOCKS.STA .Pq Event 06H , Umask 02H This event counts load operations delayed caused by preceding stores whose addresses are unknown (STA block). .It Li STORE_BLOCKS.ANY .Pq Event 06H , Umask 0FH All loads delayed due to store blocks .It Li MEMORY_DISAMBIGURATION.RESET .Pq Event 09H , Umask 01H Counts memory disambiguration reset cycles .It Li MEMORY_DISAMBIGURATION.SUCCESS .Pq Event 09H , Umask 02H Counts the number of loads that memory disambiguration succeeded .It Li MEMORY_DISAMBIGURATION.WATCHDOG .Pq Event 09H , Umask 04H Counts the number of times the memory disambiguration watchdog kicked in. .It Li MEMORY_DISAMBIGURATION.WATCH_CYCLES .Pq Event 09H , Umask 08H Counts the cycles that the memory disambiguration watchdog is active. set invert=1, cmask = 1 .It Li HW_INT.RCV .Pq Event 1DH , Umask 01H Number of interrupt received .It Li HW_INT.CYCLES_MASKED .Pq Event 1DH , Umask 02H Number of cycles interrupt are masked .It Li HW_INT.CYCLES_PENDING_AND_MASKED .Pq Event 1DH , Umask 04H Number of cycles interrupts are pending and masked .It Li HW_INT.CYCLES_PENDING_AND_MASKED .Pq Event 04H , Umask 04H Counts number of L2 store RFO requests where the cache line to be loaded is -in the E (exclusive) state. The L1D prefetcher does not issue a RFO -prefetch. +in the E (exclusive) state. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li HW_INT.CYCLES_PENDING_AND_MASKED .Pq Event 27H , Umask 04H LONGEST_LAT_CACH E.MISS .It Li UOPS_DECODED.DEC0 .Pq Event 3DH , Umask 01H Counts micro-ops decoded by decoder 0. .It Li UOPS_DECODED.DEC0 .Pq Event 01H , Umask 01H Counts L1 data cache store RFO requests where the cache line to be loaded is in the I state. Counter 0, 1 only .It Li 0FH .Pq Event 41H , Umask 41H L1D_CACHE_ST.MESI Counts L1 data cache store RFO requests. Counter 0, 1 only .It Li DTLB_MISSES.PDE_MISS .Pq Event 49H , Umask 20H Number of DTLB cache misses where the low part of the linear to physical address translation was missed. .It Li DTLB_MISSES.PDP_MISS .Pq Event 49H , Umask 40H Number of DTLB misses where the high part of the linear to physical address translation was missed. .It Li DTLB_MISSES.LARGE_WALK_COMPLETED .Pq Event 49H , Umask 80H Counts number of completed large page walks due to misses in the STLB. .It Li SSE_MEM_EXEC.NTA .Pq Event 4BH , Umask 01H Counts number of SSE NTA prefetch/weakly-ordered instructions which missed the L1 data cache. .It Li SSE_MEM_EXEC.STREAMING_STORES .Pq Event 4BH , Umask 08H Counts number of SSE non temporal stores .It Li SFENCE_CYCLES .Pq Event 4DH , Umask 01H Counts store fence cycles .It Li EPT.EPDE_MISS .Pq Event 4FH , Umask 02H -Counts Extended Page Directory Entry misses. The Extended Page Directory -cache is used by Virtual Machine operating systems while the guest operating -systems use the standard TLB caches. +Counts Extended Page Directory Entry misses. +The Extended Page Directory cache is used by Virtual Machine operating +systems while the guest operating systems use the standard TLB caches. .It Li EPT.EPDPE_HIT .Pq Event 4FH , Umask 04H Counts Extended Page Directory Pointer Entry hits. .It Li EPT.EPDPE_MISS .Pq Event 4FH , Umask 08H -Counts Extended Page Directory Pointer Entry misses. T +Counts Extended Page Directory Pointer Entry misses. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA .Pq Event 60H , Umask 01H -Counts weighted cycles of offcore demand data read requests. Does not -include L2 prefetch requests. +Counts weighted cycles of offcore demand data read requests. +Does not include L2 prefetch requests. counter 0 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE .Pq Event 60H , Umask 02H -Counts weighted cycles of offcore demand code read requests. Does not -include L2 prefetch requests. +Counts weighted cycles of offcore demand code read requests. +Does not include L2 prefetch requests. counter 0 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO .Pq Event 60H , Umask 04H -Counts weighted cycles of offcore demand RFO requests. Does not include L2 -prefetch requests. +Counts weighted cycles of offcore demand RFO requests. +Does not include L2 prefetch requests. counter 0 .It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ .Pq Event 60H , Umask 08H -Counts weighted cycles of offcore read requests of any kind. Include L2 -prefetch requests. +Counts weighted cycles of offcore read requests of any kind. +Include L2 prefetch requests. counter 0 .It Li IFU_IVC.FULL .Pq Event 81H , Umask 01H Instruction Fetche unit victim cache full. .It Li IFU_IVC.L1I_EVICTION .Pq Event 81H , Umask 02H L1 Instruction cache evictions. .It Li L1I_OPPORTUNISTIC_HITS .Pq Event 83H , Umask 01H Opportunistic hits in streaming. .It Li ITLB_MISSES.WALK_CYCLES .Pq Event 85H , Umask 04H Counts ITLB miss page walk cycles. .It Li ITLB_MISSES.PMH_BUSY_CYCLES .Pq Event 85H , Umask 04H Counts PMH busy cycles. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H Counts the number of ITLB misses that hit in the second level TLB. .It Li ITLB_MISSES.PDE_MISS .Pq Event 85H , Umask 20H Number of ITLB misses where the low part of the linear to physical address translation was missed. .It Li ITLB_MISSES.PDP_MISS .Pq Event 85H , Umask 40H Number of ITLB misses where the high part of the linear to physical address translation was missed. .It Li ITLB_MISSES.LARGE_WALK_COMPLETED .Pq Event 85H , Umask 80H Counts number of completed large page walks due to misses in the STLB. .It Li ITLB_MISSES.LARGE_WALK_COMPLETED .Pq Event 01H , Umask 80H -Counts number of offcore demand data read requests. Does not count L2 -prefetch requests. +Counts number of offcore demand data read requests. +Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.DEMAND.READ_CODE .Pq Event B0H , Umask 02H -Counts number of offcore demand code read requests. Does not count L2 -prefetch requests. +Counts number of offcore demand code read requests. +Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.DEMAND.RFO .Pq Event B0H , Umask 04H -Counts number of offcore demand RFO requests. Does not count L2 prefetch -requests. +Counts number of offcore demand RFO requests. +Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.ANY.READ .Pq Event B0H , Umask 08H -Counts number of offcore read requests. Includes L2 prefetch requests. +Counts number of offcore read requests. +Includes L2 prefetch requests. .It Li OFFCORE_REQUESTS.ANY.RFO .Pq Event B0H , Umask 10H -Counts number of offcore RFO requests. Includes L2 prefetch requests. +Counts number of offcore RFO requests. +Includes L2 prefetch requests. .It Li OFFCORE_REQUESTS.UNCACHED_MEM .Pq Event B0H , Umask 20H Counts number of offcore uncached memory requests. .It Li OFFCORE_REQUESTS.ANY .Pq Event B0H , Umask 80H Counts all offcore requests. .It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA .Pq Event B3H , Umask 01H -Counts weighted cycles of snoopq requests for data. Counter 0 only -Use cmask=1 to count cycles not empty. +Counts weighted cycles of snoopq requests for data. +Counter 0 only Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE .Pq Event B3H , Umask 02H -Counts weighted cycles of snoopq invalidate requests. Counter 0 only -Use cmask=1 to count cycles not empty. +Counts weighted cycles of snoopq invalidate requests. +Counter 0 only Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE .Pq Event B3H , Umask 04H -Counts weighted cycles of snoopq requests for code. Counter 0 only -Use cmask=1 to count cycles not empty. +Counts weighted cycles of snoopq requests for code. +Counter 0 only Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE .Pq Event BAH , Umask 04H Counts number of TPR reads .It Li PIC_ACCESSES.TPR_WRITES .Pq Event BAH , Umask 02H -Counts number of TPR writes -one or two micro-ops. Some instructions are decoded into longer sequences +Counts number of TPR writes one or two micro-ops. +Some instructions are decoded into longer sequences .It Li MACHINE_CLEARS.FUSION_ASSIST .Pq Event C3H , Umask 10H Counts the number of macro-fusion assists Counts SIMD packed single- precision floating point Uops retired. .It Li BOGUS_BR .Pq Event E4H , Umask 01H Counts the number of bogus branches. .It Li L2_HW_PREFETCH.HIT .Pq Event F3H , Umask 01H Count L2 HW prefetcher detector hits .It Li L2_HW_PREFETCH.ALLOC .Pq Event F3H , Umask 02H Count L2 HW prefetcher allocations .It Li L2_HW_PREFETCH.DATA_TRIGGER .Pq Event F3H , Umask 04H Count L2 HW data prefetcher triggered .It Li L2_HW_PREFETCH.CODE_TRIGGER .Pq Event F3H , Umask 08H Count L2 HW code prefetcher triggered .It Li L2_HW_PREFETCH.DCA_TRIGGER .Pq Event F3H , Umask 10H Count L2 HW DCA prefetcher triggered .It Li L2_HW_PREFETCH.KICK_START .Pq Event F3H , Umask 20H Count L2 HW prefetcher kick started .It Li SQ_MISC.PROMOTION .Pq Event F4H , Umask 01H Counts the number of L2 secondary misses that hit the Super Queue. .It Li SQ_MISC.PROMOTION_POST_GO .Pq Event F4H , Umask 02H Counts the number of L2 secondary misses during the Super Queue filling L2. .It Li SQ_MISC.LRU_HINTS .Pq Event F4H , Umask 04H Counts number of Super Queue LRU hints sent to L3. .It Li SQ_MISC.FILL_DROPPED .Pq Event F4H , Umask 08H Counts the number of SQ L2 fills dropped due to L2 busy. .It Li SEGMENT_REG_LOADS .Pq Event F8H , Umask 01H Counts number of segment register loads. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7uc 3 , .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . diff --git a/lib/libpmc/pmc.corei7uc.3 b/lib/libpmc/pmc.corei7uc.3 index 3bcda1c7b499..1f49222ceda6 100644 --- a/lib/libpmc/pmc.corei7uc.3 +++ b/lib/libpmc/pmc.corei7uc.3 @@ -1,880 +1,909 @@ .\" Copyright (c) 2010 Fabien Thomas. All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd March 24, 2010 .Dt PMC.COREI7UC 3 .Os .Sh NAME .Nm pmc.corei7uc .Nd uncore measurement events for .Tn Intel .Tn Core i7 and Xeon 5500 family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Core i7" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs contain 2 classes of PMCs: .Bl -tag -width "Li PMC_CLASS_UCP" .It Li PMC_CLASS_UCF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_UCP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Core i7 and Xeon 5500 PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-033US" .%D December 2009 .%Q "Intel Corporation" .Re .Ss COREI7 AND XEON 5500 UNCORE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.ucf 3 . .Ss COREI7 AND XEON 5500 UNCORE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta \&No .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta \&No .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta \&No .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .El .Ss Event Specifiers (Programmable PMCs) Core i7 and Xeon 5500 uncore programmable PMCs support the following events: .Bl -tag -width indent .It Li GQ_CYCLES_FULL.READ_TRACKER .Pq Event 00H , Umask 01H Uncore cycles Global Queue read tracker is full. .It Li GQ_CYCLES_FULL.WRITE_TRACKER .Pq Event 00H , Umask 02H Uncore cycles Global Queue write tracker is full. .It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER .Pq Event 00H , Umask 04H -Uncore cycles Global Queue peer probe tracker is full. The peer probe -tracker queue tracks snoops from the IOH and remote sockets. +Uncore cycles Global Queue peer probe tracker is full. +The peer probe tracker queue tracks snoops from the IOH and remote sockets. .It Li GQ_CYCLES_NOT_EMPTY.READ_TRACKER .Pq Event 01H , Umask 01H Uncore cycles were Global Queue read tracker has at least one valid entry. .It Li GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER .Pq Event 01H , Umask 02H Uncore cycles were Global Queue write tracker has at least one valid entry. .It Li GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER .Pq Event 01H , Umask 04H -Uncore cycles were Global Queue peer probe tracker has at least one valid -entry. The peer probe tracker queue tracks IOH and remote socket snoops. +Uncore cycles were Global Queue peer probe tracker has at least one valid entry. +The peer probe tracker queue tracks IOH and remote socket snoops. .It Li GQ_ALLOC.READ_TRACKER .Pq Event 03H , Umask 01H -Counts the number of tread tracker allocate to deallocate entries. The GQ -read tracker allocate to deallocate occupancy count is divided by the count -to obtain the average read tracker latency. +Counts the number of tread tracker allocate to deallocate entries. +The GQ read tracker allocate to deallocate occupancy count is divided +by the count to obtain the average read tracker latency. .It Li GQ_ALLOC.RT_L3_MISS .Pq Event 03H , Umask 02H Counts the number GQ read tracker entries for which a full cache line read -has missed the L3. The GQ read tracker L3 miss to fill occupancy count is -divided by this count to obtain the average cache line read L3 miss latency. +has missed the L3. +The GQ read tracker L3 miss to fill occupancy count is divided by this count +to obtain the average cache line read L3 miss latency. The latency represents the time after which the L3 has determined that the -cache line has missed. The time between a GQ read tracker allocation and the -L3 determining that the cache line has missed is the average L3 hit latency. +cache line has missed. +The time between a GQ read tracker allocation and the L3 determining that the +cache line has missed is the average L3 hit latency. The total L3 cache line read miss latency is the hit latency + L3 miss latency. .It Li GQ_ALLOC.RT_TO_L3_RESP .Pq Event 03H , Umask 04H Counts the number of GQ read tracker entries that are allocated in the read -tracker queue that hit or miss the L3. The GQ read tracker L3 hit occupancy -count is divided by this count to obtain the average L3 hit latency. +tracker queue that hit or miss the L3. +The GQ read tracker L3 hit occupancy count is divided by this count to obtain +the average L3 hit latency. .It Li GQ_ALLOC.RT_TO_RTID_ACQUIRED .Pq Event 03H , Umask 08H Counts the number of GQ read tracker entries that are allocated in the read -tracker, have missed in the L3 and have not acquired a Request Transaction -ID. The GQ read tracker L3 miss to RTID acquired occupancy count is +tracker, have missed in the L3 and have not acquired a Request Transaction ID. +The GQ read tracker L3 miss to RTID acquired occupancy count is divided by this count to obtain the average latency for a read L3 miss to acquire an RTID. .It Li GQ_ALLOC.WT_TO_RTID_ACQUIRED .Pq Event 03H , Umask 10H Counts the number of GQ write tracker entries that are allocated in the write tracker, have missed in the L3 and have not acquired a Request -Transaction ID. The GQ write tracker L3 miss to RTID occupancy count is -divided by this count to obtain the average latency for a write L3 miss to -acquire an RTID. +Transaction ID. +The GQ write tracker L3 miss to RTID occupancy count is divided by this count +to obtain the average latency for a write L3 miss to acquire an RTID. .It Li GQ_ALLOC.WRITE_TRACKER .Pq Event 03H , Umask 20H Counts the number of GQ write tracker entries that are allocated in the -write tracker queue that miss the L3. The GQ write tracker occupancy count -is divided by the this count to obtain the average L3 write miss latency. +write tracker queue that miss the L3. +The GQ write tracker occupancy count is divided by the this count to obtain the average L3 write miss latency. .It Li GQ_ALLOC.PEER_PROBE_TRACKER .Pq Event 03H , Umask 40H Counts the number of GQ peer probe tracker (snoop) entries that are -allocated in the peer probe tracker queue that miss the L3. The GQ peer -probe occupancy count is divided by this count to obtain the average L3 peer +allocated in the peer probe tracker queue that miss the L3. +The GQ peer probe occupancy count is divided by this count to obtain the average L3 peer probe miss latency. .It Li GQ_DATA.FROM_QPI .Pq Event 04H , Umask 01H Cycles Global Queue Quickpath Interface input data port is busy importing -data from the Quickpath Interface. Each cycle the input port can transfer 8 -or 16 bytes of data. +data from the Quickpath Interface. +Each cycle the input port can transfer 8 or 16 bytes of data. .It Li GQ_DATA.FROM_QMC .Pq Event 04H , Umask 02H Cycles Global Queue Quickpath Memory Interface input data port is busy -importing data from the Quickpath Memory Interface. Each cycle the input -port can transfer 8 or 16 bytes of data. +importing data from the Quickpath Memory Interface. +Each cycle the input port can transfer 8 or 16 bytes of data. .It Li GQ_DATA.FROM_L3 .Pq Event 04H , Umask 04H -Cycles GQ L3 input data port is busy importing data from the Last Level -Cache. Each cycle the input port can transfer 32 bytes of data. +Cycles GQ L3 input data port is busy importing data from the Last Level Cache. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.FROM_CORES_02 .Pq Event 04H , Umask 08H Cycles GQ Core 0 and 2 input data port is busy importing data from processor -cores 0 and 2. Each cycle the input port can transfer 32 bytes of data. +cores 0 and 2. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.FROM_CORES_13 .Pq Event 04H , Umask 10H Cycles GQ Core 1 and 3 input data port is busy importing data from processor -cores 1 and 3. Each cycle the input port can transfer 32 bytes of data. +cores 1 and 3. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.TO_QPI_QMC .Pq Event 05H , Umask 01H Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath -Interface or Quickpath Memory Interface. Each cycle the output port can -transfer 32 bytes of data. +Interface or Quickpath Memory Interface. +Each cycle the output port can transfer 32 bytes of data. .It Li GQ_DATA.TO_L3 .Pq Event 05H , Umask 02H Cycles GQ L3 output data port is busy sending data to the Last Level Cache. Each cycle the output port can transfer 32 bytes of data. .It Li GQ_DATA.TO_CORES .Pq Event 05H , Umask 04H -Cycles GQ Core output data port is busy sending data to the Cores. Each -cycle the output port can transfer 32 bytes of data. +Cycles GQ Core output data port is busy sending data to the Cores. +Each cycle the output port can transfer 32 bytes of data. .It Li SNP_RESP_TO_LOCAL_HOME.I_STATE .Pq Event 06H , Umask 01H Number of snoop responses to the local home that L3 does not have the referenced cache line. .It Li SNP_RESP_TO_LOCAL_HOME.S_STATE .Pq Event 06H , Umask 02H Number of snoop responses to the local home that L3 has the referenced line cached in the S state. .It Li SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE .Pq Event 06H , Umask 04H Number of responses to code or data read snoops to the local home that the -L3 has the referenced cache line in the E state. The L3 cache line state is -changed to the S state and the line is forwarded to the local home in the S -state. +L3 has the referenced cache line in the E state. +The L3 cache line state is changed to the S state and the line is +forwarded to the local home in the S state. .It Li SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE .Pq Event 06H , Umask 08H Number of responses to read invalidate snoops to the local home that the L3 -has the referenced cache line in the M state. The L3 cache line state is -invalidated and the line is forwarded to the local home in the M state. +has the referenced cache line in the M state. +The L3 cache line state is invalidated and the line is forwarded to the +local home in the M state. .It Li SNP_RESP_TO_LOCAL_HOME.CONFLICT .Pq Event 06H , Umask 10H Number of conflict snoop responses sent to the local home. .It Li SNP_RESP_TO_LOCAL_HOME.WB .Pq Event 06H , Umask 20H Number of responses to code or data read snoops to the local home that the L3 has the referenced line cached in the M state. .It Li SNP_RESP_TO_REMOTE_HOME.I_STATE .Pq Event 07H , Umask 01H Number of snoop responses to a remote home that L3 does not have the referenced cache line. .It Li SNP_RESP_TO_REMOTE_HOME.S_STATE .Pq Event 07H , Umask 02H Number of snoop responses to a remote home that L3 has the referenced line cached in the S state. .It Li SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE .Pq Event 07H , Umask 04H Number of responses to code or data read snoops to a remote home that the L3 -has the referenced cache line in the E state. The L3 cache line state is -changed to the S state and the line is forwarded to the remote home in the S -state. +has the referenced cache line in the E state. +The L3 cache line state is changed to the S state and the line is forwarded to +the remote home in the S state. .It Li SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE .Pq Event 07H , Umask 08H Number of responses to read invalidate snoops to a remote home that the L3 -has the referenced cache line in the M state. The L3 cache line state is -invalidated and the line is forwarded to the remote home in the M state. +has the referenced cache line in the M state. +The L3 cache line state is invalidated and the line is forwarded to the +remote home in the M state. .It Li SNP_RESP_TO_REMOTE_HOME.CONFLICT .Pq Event 07H , Umask 10H Number of conflict snoop responses sent to the local home. .It Li SNP_RESP_TO_REMOTE_HOME.WB .Pq Event 07H , Umask 20H Number of responses to code or data read snoops to a remote home that the L3 has the referenced line cached in the M state. .It Li SNP_RESP_TO_REMOTE_HOME.HITM .Pq Event 07H , Umask 24H Number of HITM snoop responses to a remote home .It Li L3_HITS.READ .Pq Event 08H , Umask 01H Number of code read, data read and RFO requests that hit in the L3 .It Li L3_HITS.WRITE .Pq Event 08H , Umask 02H -Number of writeback requests that hit in the L3. Writebacks from the cores -will always result in L3 hits due to the inclusive property of the L3. +Number of writeback requests that hit in the L3. +Writebacks from the cores will always result in L3 hits due to the inclusive property of the L3. .It Li L3_HITS.PROBE .Pq Event 08H , Umask 04H Number of snoops from IOH or remote sockets that hit in the L3. .It Li L3_HITS.ANY .Pq Event 08H , Umask 03H Number of reads and writes that hit the L3. .It Li L3_MISS.READ .Pq Event 09H , Umask 01H Number of code read, data read and RFO requests that miss the L3. .It Li L3_MISS.WRITE .Pq Event 09H , Umask 02H -Number of writeback requests that miss the L3. Should always be zero as -writebacks from the cores will always result in L3 hits due to the inclusive -property of the L3. +Number of writeback requests that miss the L3. +Should always be zero as writebacks from the cores will always result in +L3 hits due to the inclusive property of the L3. .It Li L3_MISS.PROBE .Pq Event 09H , Umask 04H Number of snoops from IOH or remote sockets that miss the L3. .It Li L3_MISS.ANY .Pq Event 09H , Umask 03H Number of reads and writes that miss the L3. .It Li L3_LINES_IN.M_STATE .Pq Event 0AH , Umask 01H -Counts the number of L3 lines allocated in M state. The only time a cache -line is allocated in the M state is when the line was forwarded in M state -is forwarded due to a Snoop Read Invalidate Own request. +Counts the number of L3 lines allocated in M state. +The only time a cache line is allocated in the M state is when the line +was forwarded in M state is forwarded due to a Snoop Read Invalidate Own request. .It Li L3_LINES_IN.E_STATE .Pq Event 0AH , Umask 02H Counts the number of L3 lines allocated in E state. .It Li L3_LINES_IN.S_STATE .Pq Event 0AH , Umask 04H Counts the number of L3 lines allocated in S state. .It Li L3_LINES_IN.F_STATE .Pq Event 0AH , Umask 08H Counts the number of L3 lines allocated in F state. .It Li L3_LINES_IN.ANY .Pq Event 0AH , Umask 0FH Counts the number of L3 lines allocated in any state. .It Li L3_LINES_OUT.M_STATE .Pq Event 0BH , Umask 01H -Counts the number of L3 lines victimized that were in the M state. When the -victim cache line is in M state, the line is written to its home cache agent +Counts the number of L3 lines victimized that were in the M state. +When the victim cache line is in M state, the line is written to its home cache agent which can be either local or remote. .It Li L3_LINES_OUT.E_STATE .Pq Event 0BH , Umask 02H Counts the number of L3 lines victimized that were in the E state. .It Li L3_LINES_OUT.S_STATE .Pq Event 0BH , Umask 04H Counts the number of L3 lines victimized that were in the S state. .It Li L3_LINES_OUT.I_STATE .Pq Event 0BH , Umask 08H Counts the number of L3 lines victimized that were in the I state. .It Li L3_LINES_OUT.F_STATE .Pq Event 0BH , Umask 10H Counts the number of L3 lines victimized that were in the F state. .It Li L3_LINES_OUT.ANY .Pq Event 0BH , Umask 1FH Counts the number of L3 lines victimized in any state. .It Li QHL_REQUESTS.IOH_READS .Pq Event 20H , Umask 01H Counts number of Quickpath Home Logic read requests from the IOH. .It Li QHL_REQUESTS.IOH_WRITES .Pq Event 20H , Umask 02H Counts number of Quickpath Home Logic write requests from the IOH. .It Li QHL_REQUESTS.REMOTE_READS .Pq Event 20H , Umask 04H Counts number of Quickpath Home Logic read requests from a remote socket. .It Li QHL_REQUESTS.REMOTE_WRITES .Pq Event 20H , Umask 08H Counts number of Quickpath Home Logic write requests from a remote socket. .It Li QHL_REQUESTS.LOCAL_READS .Pq Event 20H , Umask 10H Counts number of Quickpath Home Logic read requests from the local socket. .It Li QHL_REQUESTS.LOCAL_WRITES .Pq Event 20H , Umask 20H Counts number of Quickpath Home Logic write requests from the local socket. .It Li QHL_CYCLES_FULL.IOH .Pq Event 21H , Umask 01H Counts uclk cycles all entries in the Quickpath Home Logic IOH are full. .It Li QHL_CYCLES_FULL.REMOTE .Pq Event 21H , Umask 02H Counts uclk cycles all entries in the Quickpath Home Logic remote tracker are full. .It Li QHL_CYCLES_FULL.LOCAL .Pq Event 21H , Umask 04H Counts uclk cycles all entries in the Quickpath Home Logic local tracker are full. .It Li QHL_CYCLES_NOT_EMPTY.IOH .Pq Event 22H , Umask 01H Counts uclk cycles all entries in the Quickpath Home Logic IOH is busy. .It Li QHL_CYCLES_NOT_EMPTY.REMOTE .Pq Event 22H , Umask 02H Counts uclk cycles all entries in the Quickpath Home Logic remote tracker is busy. .It Li QHL_CYCLES_NOT_EMPTY.LOCAL .Pq Event 22H , Umask 04H Counts uclk cycles all entries in the Quickpath Home Logic local tracker is busy. .It Li QHL_OCCUPANCY.IOH .Pq Event 23H , Umask 01H QHL IOH tracker allocate to deallocate read occupancy. .It Li QHL_OCCUPANCY.REMOTE .Pq Event 23H , Umask 02H QHL remote tracker allocate to deallocate read occupancy. .It Li QHL_OCCUPANCY.LOCAL .Pq Event 23H , Umask 04H QHL local tracker allocate to deallocate read occupancy. .It Li QHL_ADDRESS_CONFLICTS.2WAY .Pq Event 24H , Umask 02H Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 -conflicts. The AAT is a structure that tracks requests that are in conflict. -The requests themselves are in the home tracker entries. The count is -reported when an AAT entry deallocates. +conflicts. +The AAT is a structure that tracks requests that are in conflict. +The requests themselves are in the home tracker entries. +The count is reported when an AAT entry deallocates. .It Li QHL_ADDRESS_CONFLICTS.3WAY .Pq Event 24H , Umask 04H Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 -conflicts. The AAT is a structure that tracks requests that are in conflict. -The requests themselves are in the home tracker entries. The count is -reported when an AAT entry deallocates. +conflicts. +The AAT is a structure that tracks requests that are in conflict. +The requests themselves are in the home tracker entries. +The count is reported when an AAT entry deallocates. .It Li QHL_CONFLICT_CYCLES.IOH .Pq Event 25H , Umask 01H Counts cycles the Quickpath Home Logic IOH Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_CONFLICT_CYCLES.REMOTE .Pq Event 25H , Umask 02H Counts cycles the Quickpath Home Logic Remote Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_CONFLICT_CYCLES.LOCAL .Pq Event 25H , Umask 04H Counts cycles the Quickpath Home Logic Local Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_TO_QMC_BYPASS .Pq Event 26H , Umask 01H Counts number or requests to the Quickpath Memory Controller that bypass the -Quickpath Home Logic. All local accesses can be bypassed. For remote -requests, only read requests can be bypassed. +Quickpath Home Logic. +All local accesses can be bypassed. +For remote requests, only read requests can be bypassed. .It Li QMC_NORMAL_FULL.READ.CH0 .Pq Event 27H , Umask 01H Uncore cycles all the entries in the DRAM channel 0 medium or low priority queue are occupied with read requests. .It Li QMC_NORMAL_FULL.READ.CH1 .Pq Event 27H , Umask 02H Uncore cycles all the entries in the DRAM channel 1 medium or low priority queue are occupied with read requests. .It Li QMC_NORMAL_FULL.READ.CH2 .Pq Event 27H , Umask 04H Uncore cycles all the entries in the DRAM channel 2 medium or low priority queue are occupied with read requests. .It Li QMC_NORMAL_FULL.WRITE.CH0 .Pq Event 27H , Umask 08H Uncore cycles all the entries in the DRAM channel 0 medium or low priority queue are occupied with write requests. .It Li QMC_NORMAL_FULL.WRITE.CH1 .Pq Event 27H , Umask 10H Counts cycles all the entries in the DRAM channel 1 medium or low priority queue are occupied with write requests. .It Li QMC_NORMAL_FULL.WRITE.CH2 .Pq Event 27H , Umask 20H Uncore cycles all the entries in the DRAM channel 2 medium or low priority queue are occupied with write requests. .It Li QMC_ISOC_FULL.READ.CH0 .Pq Event 28H , Umask 01H Counts cycles all the entries in the DRAM channel 0 high priority queue are occupied with isochronous read requests. .It Li QMC_ISOC_FULL.READ.CH1 .Pq Event 28H , Umask 02H Counts cycles all the entries in the DRAM channel 1 high priority queue are occupied with isochronous read requests. .It Li QMC_ISOC_FULL.READ.CH2 .Pq Event 28H , Umask 04H Counts cycles all the entries in the DRAM channel 2 high priority queue are occupied with isochronous read requests. .It Li QMC_ISOC_FULL.WRITE.CH0 .Pq Event 28H , Umask 08H Counts cycles all the entries in the DRAM channel 0 high priority queue are occupied with isochronous write requests. .It Li QMC_ISOC_FULL.WRITE.CH1 .Pq Event 28H , Umask 10H Counts cycles all the entries in the DRAM channel 1 high priority queue are occupied with isochronous write requests. .It Li QMC_ISOC_FULL.WRITE.CH2 .Pq Event 28H , Umask 20H Counts cycles all the entries in the DRAM channel 2 high priority queue are occupied with isochronous write requests. .It Li QMC_BUSY.READ.CH0 .Pq Event 29H , Umask 01H Counts cycles where Quickpath Memory Controller has at least 1 outstanding read request to DRAM channel 0. .It Li QMC_BUSY.READ.CH1 .Pq Event 29H , Umask 02H Counts cycles where Quickpath Memory Controller has at least 1 outstanding read request to DRAM channel 1. .It Li QMC_BUSY.READ.CH2 .Pq Event 29H , Umask 04H Counts cycles where Quickpath Memory Controller has at least 1 outstanding read request to DRAM channel 2. .It Li QMC_BUSY.WRITE.CH0 .Pq Event 29H , Umask 08H Counts cycles where Quickpath Memory Controller has at least 1 outstanding write request to DRAM channel 0. .It Li QMC_BUSY.WRITE.CH1 .Pq Event 29H , Umask 10H Counts cycles where Quickpath Memory Controller has at least 1 outstanding write request to DRAM channel 1. .It Li QMC_BUSY.WRITE.CH2 .Pq Event 29H , Umask 20H Counts cycles where Quickpath Memory Controller has at least 1 outstanding write request to DRAM channel 2. .It Li QMC_OCCUPANCY.CH0 .Pq Event 2AH , Umask 01H IMC channel 0 normal read request occupancy. .It Li QMC_OCCUPANCY.CH1 .Pq Event 2AH , Umask 02H IMC channel 1 normal read request occupancy. .It Li QMC_OCCUPANCY.CH2 .Pq Event 2AH , Umask 04H IMC channel 2 normal read request occupancy. .It Li QMC_ISSOC_OCCUPANCY.CH0 .Pq Event 2BH , Umask 01H IMC channel 0 issoc read request occupancy. .It Li QMC_ISSOC_OCCUPANCY.CH1 .Pq Event 2BH , Umask 02H IMC channel 1 issoc read request occupancy. .It Li QMC_ISSOC_OCCUPANCY.CH2 .Pq Event 2BH , Umask 04H IMC channel 2 issoc read request occupancy. .It Li QMC_ISSOC_READS.ANY .Pq Event 2BH , Umask 07H IMC issoc read request occupancy. .It Li QMC_NORMAL_READS.CH0 .Pq Event 2CH , Umask 01H Counts the number of Quickpath Memory Controller channel 0 medium and low -priority read requests. The QMC channel 0 normal read occupancy divided by -this count provides the average QMC channel 0 read latency. +priority read requests. +The QMC channel 0 normal read occupancy divided by this count provides the +average QMC channel 0 read latency. .It Li QMC_NORMAL_READS.CH1 .Pq Event 2CH , Umask 02H Counts the number of Quickpath Memory Controller channel 1 medium and low -priority read requests. The QMC channel 1 normal read occupancy divided by -this count provides the average QMC channel 1 read latency. +priority read requests. +The QMC channel 1 normal read occupancy divided by this count provides the +average QMC channel 1 read latency. .It Li QMC_NORMAL_READS.CH2 .Pq Event 2CH , Umask 04H Counts the number of Quickpath Memory Controller channel 2 medium and low -priority read requests. The QMC channel 2 normal read occupancy divided by -this count provides the average QMC channel 2 read latency. +priority read requests. +The QMC channel 2 normal read occupancy divided by this count provides the +average QMC channel 2 read latency. .It Li QMC_NORMAL_READS.ANY .Pq Event 2CH , Umask 07H Counts the number of Quickpath Memory Controller medium and low priority -read requests. The QMC normal read occupancy divided by this count provides -the average QMC read latency. +read requests. +The QMC normal read occupancy divided by this count provides the average +QMC read latency. .It Li QMC_HIGH_PRIORITY_READS.CH0 .Pq Event 2DH , Umask 01H Counts the number of Quickpath Memory Controller channel 0 high priority isochronous read requests. .It Li QMC_HIGH_PRIORITY_READS.CH1 .Pq Event 2DH , Umask 02H Counts the number of Quickpath Memory Controller channel 1 high priority isochronous read requests. .It Li QMC_HIGH_PRIORITY_READS.CH2 .Pq Event 2DH , Umask 04H Counts the number of Quickpath Memory Controller channel 2 high priority isochronous read requests. .It Li QMC_HIGH_PRIORITY_READS.ANY .Pq Event 2DH , Umask 07H Counts the number of Quickpath Memory Controller high priority isochronous read requests. .It Li QMC_CRITICAL_PRIORITY_READS.CH0 .Pq Event 2EH , Umask 01H Counts the number of Quickpath Memory Controller channel 0 critical priority isochronous read requests. .It Li QMC_CRITICAL_PRIORITY_READS.CH1 .Pq Event 2EH , Umask 02H Counts the number of Quickpath Memory Controller channel 1 critical priority isochronous read requests. .It Li QMC_CRITICAL_PRIORITY_READS.CH2 .Pq Event 2EH , Umask 04H Counts the number of Quickpath Memory Controller channel 2 critical priority isochronous read requests. .It Li QMC_CRITICAL_PRIORITY_READS.ANY .Pq Event 2EH , Umask 07H Counts the number of Quickpath Memory Controller critical priority isochronous read requests. .It Li QMC_WRITES.FULL.CH0 .Pq Event 2FH , Umask 01H Counts number of full cache line writes to DRAM channel 0. .It Li QMC_WRITES.FULL.CH1 .Pq Event 2FH , Umask 02H Counts number of full cache line writes to DRAM channel 1. .It Li QMC_WRITES.FULL.CH2 .Pq Event 2FH , Umask 04H Counts number of full cache line writes to DRAM channel 2. .It Li QMC_WRITES.FULL.ANY .Pq Event 2FH , Umask 07H Counts number of full cache line writes to DRAM. .It Li QMC_WRITES.PARTIAL.CH0 .Pq Event 2FH , Umask 08H Counts number of partial cache line writes to DRAM channel 0. .It Li QMC_WRITES.PARTIAL.CH1 .Pq Event 2FH , Umask 10H Counts number of partial cache line writes to DRAM channel 1. .It Li QMC_WRITES.PARTIAL.CH2 .Pq Event 2FH , Umask 20H Counts number of partial cache line writes to DRAM channel 2. .It Li QMC_WRITES.PARTIAL.ANY .Pq Event 2FH , Umask 38H Counts number of partial cache line writes to DRAM. .It Li QMC_CANCEL.CH0 .Pq Event 30H , Umask 01H Counts number of DRAM channel 0 cancel requests. .It Li QMC_CANCEL.CH1 .Pq Event 30H , Umask 02H Counts number of DRAM channel 1 cancel requests. .It Li QMC_CANCEL.CH2 .Pq Event 30H , Umask 04H Counts number of DRAM channel 2 cancel requests. .It Li QMC_CANCEL.ANY .Pq Event 30H , Umask 07H Counts number of DRAM cancel requests. .It Li QMC_PRIORITY_UPDATES.CH0 .Pq Event 31H , Umask 01H -Counts number of DRAM channel 0 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to -expedite the request. +Counts number of DRAM channel 0 priority updates. +A priority update occurs when an ISOC high or critical request +is received by the QHL and there is a matching request with normal priority +that has already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.CH1 .Pq Event 31H , Umask 02H -Counts number of DRAM channel 1 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to -expedite the request. +Counts number of DRAM channel 1 priority updates. +A priority update occurs when an ISOC high or critical request is received by +the QHL and there is a matching request with normal priority that has +already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.CH2 .Pq Event 31H , Umask 04H -Counts number of DRAM channel 2 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to -expedite the request. +Counts number of DRAM channel 2 priority updates. +A priority update occurs when an ISOC high or critical request is received by +the QHL and there is a matching request with normal priority that has +already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.ANY .Pq Event 31H , Umask 07H -Counts number of DRAM priority updates. A priority update occurs when an -ISOC high or critical request is received by the QHL and there is a matching -request with normal priority that has already been issued to the QMC. In -this instance, the QHL will send a priority update to QMC to expedite the -request. +Counts number of DRAM priority updates. +A priority update occurs when an ISOC high or critical request is received by +the QHL and there is a matching request with normal priority that has +already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QHL_FRC_ACK_CNFLTS.LOCAL .Pq Event 33H , Umask 04H Counts number of Force Acknowledge Conflict messages sent by the Quickpath Home Logic to the local home. .It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0 .Pq Event 40H , Umask 01H Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0 .Pq Event 40H , Umask 02H Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0 .Pq Event 40H , Umask 04H Counts cycles the Quickpath outbound link 0 non-data response virtual -channel is stalled due to lack of a VNA and VN0 credit. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1 .Pq Event 40H , Umask 08H Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1 .Pq Event 40H , Umask 10H Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1 .Pq Event 40H , Umask 20H Counts cycles the Quickpath outbound link 1 non-data response virtual -channel is stalled due to lack of a VNA and VN0 credit. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_0 .Pq Event 40H , Umask 07H Counts cycles the Quickpath outbound link 0 virtual channels are stalled due -to lack of a VNA and VN0 credit. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_1 .Pq Event 40H , Umask 38H Counts cycles the Quickpath outbound link 1 virtual channels are stalled due -to lack of a VNA and VN0 credit. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0 .Pq Event 41H , Umask 01H Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is -stalled due to lack of VNA and VN0 credits. Note that this event does not -filter out when a flit would not have been selected for arbitration because -another virtual channel is getting arbitrated. +stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0 .Pq Event 41H , Umask 02H Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0 .Pq Event 41H , Umask 04H Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1 .Pq Event 41H , Umask 08H Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is -stalled due to lack of VNA and VN0 credits. Note that this event does not -filter out when a flit would not have been selected for arbitration because -another virtual channel is getting arbitrated. +stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1 .Pq Event 41H , Umask 10H Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1 .Pq Event 41H , Umask 20H Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.LINK_0 .Pq Event 41H , Umask 07H Counts cycles the Quickpath outbound link 0 virtual channels are stalled due -to lack of VNA and VN0 credits. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.LINK_1 .Pq Event 41H , Umask 38H Counts cycles the Quickpath outbound link 1 virtual channels are stalled due -to lack of VNA and VN0 credits. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_HEADER.BUSY.LINK_0 .Pq Event 42H , Umask 02H Number of cycles that the header buffer in the Quickpath Interface outbound link 0 is busy. .It Li QPI_TX_HEADER.BUSY.LINK_1 .Pq Event 42H , Umask 08H Number of cycles that the header buffer in the Quickpath Interface outbound link 1 is busy. .It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0 .Pq Event 43H , Umask 01H Number of cycles that snoop packets incoming to the Quickpath Interface link 0 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) does not have any available entries. .It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1 .Pq Event 43H , Umask 02H Number of cycles that snoop packets incoming to the Quickpath Interface link 1 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) does not have any available entries. .It Li DRAM_OPEN.CH0 .Pq Event 60H , Umask 01H -Counts number of DRAM Channel 0 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 0 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_OPEN.CH1 .Pq Event 60H , Umask 02H -Counts number of DRAM Channel 1 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 1 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_OPEN.CH2 .Pq Event 60H , Umask 04H -Counts number of DRAM Channel 2 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 2 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_PAGE_CLOSE.CH0 .Pq Event 61H , Umask 01H DRAM channel 0 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_CLOSE.CH1 .Pq Event 61H , Umask 02H DRAM channel 1 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_CLOSE.CH2 .Pq Event 61H , Umask 04H DRAM channel 2 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH0 .Pq Event 62H , Umask 01H Counts the number of precharges (PRE) that were issued to DRAM channel 0 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and +another page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH1 .Pq Event 62H , Umask 02H Counts the number of precharges (PRE) that were issued to DRAM channel 1 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and +another page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH2 .Pq Event 62H , Umask 04H Counts the number of precharges (PRE) that were issued to DRAM channel 2 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and +another page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_READ_CAS.CH0 .Pq Event 63H , Umask 01H Counts the number of times a read CAS command was issued on DRAM channel 0. .It Li DRAM_READ_CAS.AUTOPRE_CH0 .Pq Event 63H , Umask 02H Counts the number of times a read CAS command was issued on DRAM channel 0 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_READ_CAS.CH1 .Pq Event 63H , Umask 04H Counts the number of times a read CAS command was issued on DRAM channel 1. .It Li DRAM_READ_CAS.AUTOPRE_CH1 .Pq Event 63H , Umask 08H Counts the number of times a read CAS command was issued on DRAM channel 1 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_READ_CAS.CH2 .Pq Event 63H , Umask 10H Counts the number of times a read CAS command was issued on DRAM channel 2. .It Li DRAM_READ_CAS.AUTOPRE_CH2 .Pq Event 63H , Umask 20H Counts the number of times a read CAS command was issued on DRAM channel 2 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_WRITE_CAS.CH0 .Pq Event 64H , Umask 01H Counts the number of times a write CAS command was issued on DRAM channel 0. .It Li DRAM_WRITE_CAS.AUTOPRE_CH0 .Pq Event 64H , Umask 02H Counts the number of times a write CAS command was issued on DRAM channel 0 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_WRITE_CAS.CH1 .Pq Event 64H , Umask 04H Counts the number of times a write CAS command was issued on DRAM channel 1. .It Li DRAM_WRITE_CAS.AUTOPRE_CH1 .Pq Event 64H , Umask 08H Counts the number of times a write CAS command was issued on DRAM channel 1 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_WRITE_CAS.CH2 .Pq Event 64H , Umask 10H Counts the number of times a write CAS command was issued on DRAM channel 2. .It Li DRAM_WRITE_CAS.AUTOPRE_CH2 .Pq Event 64H , Umask 20H Counts the number of times a write CAS command was issued on DRAM channel 2 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_REFRESH.CH0 .Pq Event 65H , Umask 01H -Counts number of DRAM channel 0 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be +Counts number of DRAM channel 0 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_REFRESH.CH1 .Pq Event 65H , Umask 02H -Counts number of DRAM channel 1 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be +Counts number of DRAM channel 1 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_REFRESH.CH2 .Pq Event 65H , Umask 04H -Counts number of DRAM channel 2 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be +Counts number of DRAM channel 2 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_PRE_ALL.CH0 .Pq Event 66H , Umask 01H Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go +into a power down mode. .It Li DRAM_PRE_ALL.CH1 .Pq Event 66H , Umask 02H Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go +into a power down mode. .It Li DRAM_PRE_ALL.CH2 .Pq Event 66H , Umask 04H Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go +into a power down mode. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . diff --git a/lib/libpmc/pmc.haswell.3 b/lib/libpmc/pmc.haswell.3 index 2f677b976fd5..c69d4b694ca2 100644 --- a/lib/libpmc/pmc.haswell.3 +++ b/lib/libpmc/pmc.haswell.3 @@ -1,955 +1,951 @@ .\" Copyright (c) 2013 Hiren Panchasara .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd March 22, 2013 .Dt PMC.HASWELL 3 .Os .Sh NAME .Nm pmc.haswell .Nd measurement events for .Tn Intel .Tn Haswell family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Haswell" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to two classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Haswell PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" .%N "Order Number: 325462-045US" .%D January 2013 .%Q "Intel Corporation" .Re .Ss HASWELL FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss HASWELL PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry -cacheline reads. Does not count L2 data read prefetches or -instruction fetches. +cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Haswell programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H Loads blocked by overlapping with store buffer that cannot be forwarded. .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store-address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK .Pq Event 08H , Umask 01H Misses in all TLB levels that cause a page walk of any page size. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K .Pq Event 08H , Umask 02H Completed page walks due to demand load misses that caused 4K page walks in any TLB levels. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K .Pq Event 08H , Umask 02H Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H , Umask 0EH Completed page walks in any TLB of any page size due to demand load misses .It Li DTLB_LOAD_MISSES.WALK_DURATION .Pq Event 08H , Umask 10H Cycle PMH is busy with a walk. .It Li DTLB_LOAD_MISSES.STLB_HIT_4K .Pq Event 08H , Umask 20H Load misses that missed DTLB but hit STLB (4K). .It Li DTLB_LOAD_MISSES.STLB_HIT_2M .Pq Event 08H , Umask 40H Load misses that missed DTLB but hit STLB (2M). .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 60H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS .Pq Event 08H , Umask 80H DTLB demand load misses with low part of linear-to- physical address translation missed .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH , Umask 03H Cycles waiting to recover after Machine Clears -except JEClear. Set Cmask= 1. +except JEClear. +Set Cmask= 1. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H ncrements each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H -Number of flags-merge uops allocated. Such uops -adds delay. +Number of flags-merge uops allocated. +Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H -Number of slow LEA or similar uops allocated. Such -uop has 3 sources (e.g. 2 sources + immediate) +Number of slow LEA or similar uops allocated. +Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SiNGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li L2_RQSTS.DEMAND_DATA_RD_MISS .Pq Event 24H , Umask 21H Demand Data Read requests that missed L2, no rejects. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 41H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H , Umask E1H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HIT .Pq Event 24H , Umask 42H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 22H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask E2H Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 44H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 24H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_DEMAND_MISS .Pq Event 24H , Umask 27H Demand requests that miss L2 cache. .It Li L2_RQSTS.ALL_DEMAND_REFERENCES .Pq Event 24H , Umask E7H Demand requests to L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask E4H Counts all L2 code requests. .It Li L2_RQSTS.L2_PF_HIT .Pq Event 24H , Umask 50H Counts all L2 HW prefetcher requests that hit L2. .It Li L2_RQSTS.L2_PF_MISS .Pq Event 24H , Umask 30H Counts all L2 HW prefetcher requests that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask F8H Counts all L2 HW prefetcher requests. .It Li L2_RQSTS.MISS .Pq Event 24H , Umask 3FH All requests that missed L2. .It Li L2_RQSTS.REFERENCES .Pq Event 24H , Umask FFH All requests to L2 cache. .It Li L2_DEMAND_RQSTS.WB_HIT .Pq Event 27H , Umask 50H Not rejected writebacks that hit L2 cache .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H -Counts the number of thread cycles while the thread -is not in a halt state. The thread enters the halt state -when it is running the HLT instruction. The core -frequency may change from time to time due to -power or thermal throttling. +Counts the number of thread cycles while the thread is not in a halt state. +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H -Increments the number of outstanding L1D misses -every cycle. Set Cmaks = 1 and Edge =1 to count -occurrences. +Increments the number of outstanding L1D misses every cycle. +Set Cmaks = 1 and Edge =1 to count occurrences. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K .Pq Event 49H , Umask 02H Completed page walks due to store misses in one or more TLB levels of 4K page structure. .It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M .Pq Event 49H , Umask 04H Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure. .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 0EH Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 10H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT_4K .Pq Event 49H , Umask 20H Store misses that missed DTLB but hit STLB (4K). .It Li DTLB_STORE_MISSES.STLB_HIT_2M .Pq Event 49H , Umask 40H Store misses that missed DTLB but hit STLB (2M). .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 60H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li DTLB_STORE_MISSES.PDE_CACHE_MISS .Pq Event 49H , Umask 80H DTLB store misses with low part of linear-to-physical address translation missed. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PRE.HW_PF .Pq Event 4CH , Umask 02H Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED .Pq Event 58H , Umask 04H Number of integer Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED .Pq Event 58H , Umask 08H Number of SIMD Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.INT_ELIMINATED .Pq Event 58H , Umask 01H Unhalted core cycles when the thread is in ring 0. .It Li MOVE_ELIMINATION.SMID_ELIMINATED .Pq Event 58H , Umask 02H Number of SIMD Move Elimination candidate uops that were eliminated. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is in ring 0. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H -Offcore outstanding Demand Data Read transactions -in SQ to uncore. Set Cmask=1 to count cycles. +Offcore outstanding Demand Data Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD .Pq Event 60H , Umask 02H -Offcore outstanding Demand code Read transactions -in SQ to uncore. Set Cmask=1 to count cycles. +Offcore outstanding Demand code Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H -Offcore outstanding RFO store transactions in SQ to -uncore. Set Cmask=1 to count cycles. +Offcore outstanding RFO store transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H -Offcore outstanding cacheable data read -transactions in SQ to uncore. Set Cmask=1 to count -cycles. +Offcore outstanding cacheable data read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H -Cycles in which the L1D and L2 are locked, due to a -UC lock or split lock. +Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H -Increment each cycle # of uops delivered to IDQ from -MITE path. +Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H -Increment each cycle # of uops delivered to IDQ -when MS_busy by DSB. Set Cmask = 1 to count -cycles. Add Edge=1 to count # of delivery. +Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. +Set Cmask = 1 to count cycles. +Add Edge=1 to count # of delivery. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H -ncrement each cycle # of uops delivered to IDQ -when MS_busy by MITE. Set Cmask = 1 to count -cycles. +ncrement each cycle # of uops delivered to IDQ when MS_busy by MITE. +Set Cmask = 1 to count cycles. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H -Increment each cycle # of uops delivered to IDQ from -MS by either DSB or MITE. Set Cmask = 1 to count -cycles. +Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. +Set Cmask = 1 to count cycles. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered at least one uops. Set -Cmask = 1. +Counts cycles DSB is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered four uops. Set Cmask -=4. +Counts cycles DSB is delivered four uops. +Set Cmask=4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered at least one uops. Set -Cmask = 1. +Counts cycles MITE is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered four uops. Set Cmask -=4. +Counts cycles MITE is delivered four uops. +Set Cmask =4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H -Number of Instruction Cache, Streaming Buffer and -Victim Cache Misses. Includes UC accesses. +Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. +Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in ITLB that causes a page walk of any page size. .It Li ITLB_MISSES.WALK_COMPLETED_4K .Pq Event 85H , Umask 02H Completed page walks due to misses in ITLB 4K page entries. .It Li TLB_MISSES.WALK_COMPLETED_2M_4M .Pq Event 85H , Umask 04H Completed page walks due to misses in ITLB 2M/4M page entries. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 0EH Completed page walks in ITLB of any page size. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 10H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT_4K .Pq Event 85H , Umask 20H ITLB misses that hit STLB (4K). .It Li ITLB_MISSES.STLB_HIT_2M .Pq Event 85H , Umask 40H ITLB misses that hit STLB (2K). .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 60H -TLB misses that hit STLB. No page walk. +TLB misses that hit STLB. +No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. .It Li BR_INST_EXEC.NONTAKEN_COND .Pq Event 88H , Umask 41H Count conditional near branch instructions that were executed (but not necessarily retired) and not taken. .It Li BR_INST_EXEC.TAKEN_COND .Pq Event 88H , Umask 81H Count conditional near branch instructions that were executed (but not necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP .Pq Event 88H , Umask 82H Count all unconditional near branch instructions excluding calls and indirect branches. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 88H , Umask 84H Count executed indirect near branch instructions that are not calls nor returns. .It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H , Umask 88H Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H , Umask 90H Count unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H , Umask A0H Count indirect near calls, including both register and memory indirect, executed. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). .It Li BR_MISP_EXEC.NONTAKEN_COND .Pq Event 89H , Umask 41H Count conditional near branch instructions mispredicted as nontaken. .It Li BR_MISP_EXEC.TAKEN_COND .Pq Event 89H , Umask 81H Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 89H , Umask 84H Count mispredicted indirect near branch instructions that are not calls nor returns. .It Li BR_MISP_EXEC.RETURN_NEAR .Pq Event 89H , Umask 88H Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H , Umask 90H Count mispredicted unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H , Umask A0H Count mispredicted indirect near calls, including both register and memory indirect, executed. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. .It Li UOPS_EXECUTED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_2 .Pq Event A1H , Umask 04H Cycles which a Uop is dispatched on port 2 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_3 .Pq Event A1H , Umask 08H Cycles which a Uop is dispatched on port 3 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_4 .Pq Event A1H , Umask 10H Cycles which a Uop is dispatched on port 4 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_5 .Pq Event A1H , Umask 20H Cycles which a Uop is dispatched on port 5 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_6 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 6 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_7 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 7 in this thread. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available (not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H -Cycles with pending L2 miss loads. Set Cmask=2 to -count cycle. +Cycles with pending L2 miss loads. +Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING .Pq Event A3H , Umask 02H -Cycles with pending memory loads. Set Cmask=2 to -count cycle. +Cycles with pending memory loads. +Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.STALLS_L2_PENDING .Pq Event A3H , Umask 05H Number of loads missed L2. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 08H -Cycles with pending L1 cache miss loads. Set -Cmask=8 to count cycle. +Cycles with pending L1 cache miss loads. +Set Cmask=8 to count cycle. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD .Pq Event B0H , Umask 02H Demand code read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H Requires MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H Requires MSR 01A7H .It Li PAGE_WALKER_LOADS.DTLB_L1 .Pq Event BCH , Umask 11H Number of DTLB page walker loads that hit in the L1+FB. .It Li PAGE_WALKER_LOADS.ITLB_L1 .Pq Event BCH , Umask 21H Number of ITLB page walker loads that hit in the L1+FB. .It Li PAGE_WALKER_LOADS.DTLB_L2 .Pq Event BCH , Umask 12H Number of DTLB page walker loads that hit in the L2. .It Li PAGE_WALKER_LOADS.ITLB_L2 .Pq Event BCH , Umask 22H Number of ITLB page walker loads that hit in the L2. .It Li PAGE_WALKER_LOADS.DTLB_L3 .Pq Event BCH , Umask 14H Number of DTLB page walker loads that hit in the L3. .It Li PAGE_WALKER_LOADS.ITLB_L3 .Pq Event BCH , Umask 24H Number of ITLB page walker loads that hit in the L3. .It Li PAGE_WALKER_LOADS.DTLB_MEMORY .Pq Event BCH , Umask 18H Number of DTLB page walker loads from memory. .It Li PAGE_WALKER_LOADS.ITLB_MEMORY .Pq Event BCH , Umask 28H Number of ITLB page walker loads from memory. .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread-specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 08H Number of transitions from AVX-256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 10H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li OTHER_ASSISTS.ANY_WB_ASSIST .Pq Event C1H , Umask 40H Number of microcode assists invoked by HW upon uop writeback. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Number of self-modifying-code machine clears detected. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions Supports PEBS retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 FP assists due to Output values. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 FP assists due to input values. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH , Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H -Randomly sampled loads whose latency is above a -user defined threshold. A small fraction of the overall -loads are sampled due to randomization. +Randomly sampled loads whose latency is above a user defined threshold. +A small fraction of the overall loads are sampled due to randomization. .It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS .Pq Event D0H , Umask 11H Count retired load uops that missed the STLB. .It Li MEM_UOPS_RETIRED.STLB_MISS_STORES .Pq Event D0H , Umask 12H Count retired store uops that missed the STLB. .It Li MEM_UOPS_RETIRED.SPLIT_LOADS .Pq Event D0H , Umask 41H Count retired load uops that were split across a cache line. .It Li MEM_UOPS_RETIRED.SPLIT_STORES .Pq Event D0H , Umask 42H Count retired store uops that were split across a cache line. .It Li MEM_UOPS_RETIRED.ALL_LOADS .Pq Event D0H , Umask 81H Count all retired load uops. .It Li MEM_UOPS_RETIRED.ALL_STORES .Pq Event D0H , Umask 82H Count all retired store uops. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops with LLC cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_MISS .Pq Event D1H , Umask 10H -Retired load uops missed L2. Unknown data source -excluded. +Retired load uops missed L2. +Unknown data source excluded. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H , Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H , Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H , Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H , Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM .Pq Event D3H , Umask 01H Retired load uops which data sources missed LLC but serviced from local dram. .It Li BACLEARS.ANY .Pq Event E6H , Umask 1FH Number of front end re-steers due to BPU misprediction. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H Any MLC or LLC HW prefetch accessing L2, including rejects. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. .It Li L2_LINES_IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 05H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 06H Dirty L2 cache lines evicted by demand. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.haswelluc 3 , .Xr pmc.iaf 3 , .Xr pmc.ivybridge 3 , .Xr pmc.ivybridgexeon 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS .An -nosplit The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . The support for the Haswell microarchitecture was written by .An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . diff --git a/lib/libpmc/pmc.haswelluc.3 b/lib/libpmc/pmc.haswelluc.3 index fedf056eae7f..e7b57c59d0e5 100644 --- a/lib/libpmc/pmc.haswelluc.3 +++ b/lib/libpmc/pmc.haswelluc.3 @@ -1,236 +1,235 @@ .\" Copyright (c) 2013 Hiren Panchasara .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd March 22, 2013 .Dt PMC.HASWELLUC 3 .Os .Sh NAME .Nm pmc.haswelluc .Nd uncore measurement events for .Tn Intel .Tn Haswell family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Haswell" CPUs contain PMCs conforming to version 3 of the .Tn Intel performance measurement architecture. These CPUs contain two classes of PMCs: .Bl -tag -width "Li PMC_CLASS_UCP" .It Li PMC_CLASS_UCF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_UCP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Haswell PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" .%N "Order Number: 325462-045US" .%D January 2013 .%Q "Intel Corporation" .Re .Ss HASWELL UNCORE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.ucf 3 . Not all CPUs in this family implement fixed-function counters. .Ss HASWELL UNCORE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta \&No .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta \&No .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta \&No .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .El .Ss Event Specifiers (Programmable PMCs) Haswell programmable PMCs support the following events: .Bl -tag -width indent .It Li UNC_CBO_XSNP_RESPONSE.MISS .Pq Event 22H , Umask 01H A snoop misses in some processor core. .It Li UNC_CBO_XSNP_RESPONSE.INVAL .Pq Event 22H , Umask 02H A snoop invalidates a non-modified line in some processor core. .It Li UNC_CBO_XSNP_RESPONSE.HIT .Pq Event 22H , Umask 04H A snoop hits a non-modified line in some processor core. .It Li UNC_CBO_XSNP_RESPONSE.HITM .Pq Event 22H , Umask 08H A snoop hits a modified line in some processor core. .It Li UNC_CBO_XSNP_RESPONSE.INVAL_M .Pq Event 22H , Umask 10H A snoop invalidates a modified line in some processor core. .It Li UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER .Pq Event 22H , Umask 20H Filter on cross-core snoops initiated by this Cbox due to external snoop request. .It Li UNC_CBO_XSNP_RESPONSE.XCORE_FILTER .Pq Event 22H , Umask 40H Filter on cross-core snoops initiated by this Cbox due to processor core memory request. .It Li UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER .Pq Event 22H , Umask 80H Filter on cross-core snoops initiated by this Cbox due to LLC eviction. .It Li UNC_CBO_CACHE_LOOKUP.M .Pq Event 34H , Umask 01H LLC lookup request that access cache and found line in M-state. .It Li UNC_CBO_CACHE_LOOKUP.ES .Pq Event 34H , Umask 06H LLC lookup request that access cache and found line in E or S state. .It Li UNC_CBO_CACHE_LOOKUP.I .Pq Event 34H , Umask 08H LLC lookup request that access cache and found line in I-state. .It Li UNC_CBO_CACHE_LOOKUP.READ_FILTER .Pq Event 34H , Umask 10H Filter on processor core initiated cacheable read -requests. Must combine with at least one of 01H, 02H, -04H, 08H. +requests. +Must combine with at least one of 01H, 02H, 04H, 08H. .It Li UNC_CBO_CACHE_LOOKUP.WRITE_FILTER .Pq Event 34H , Umask 20H -Filter on processor core initiated cacheable write -requests. Must combine with at least one of 01H, 02H, -04H, 08H. +Filter on processor core initiated cacheable write requests. +Must combine with at least one of 01H, 02H, 04H, 08H. .It Li UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER .Pq Event 34H , Umask 40H -Filter on external snoop requests. Must combine with -at least one of 01H, 02H, 04H, 08H. +Filter on external snoop requests. +Must combine with at least one of 01H, 02H, 04H, 08H. .It Li UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER .Pq Event 34H , Umask 80H Filter on any IRQ or IPQ initiated requests including -uncacheable, non-coherent requests. Must combine -with at least one of 01H, 02H, 04H, 08H. +uncacheable, non-coherent requests. +Must combine with at least one of 01H, 02H, 04H, 08H. .It Li UNC_ARB_TRK_OCCUPANCY.ALL .Pq Event 80H , Umask 01H Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC. .It Li UNC_ARB_TRK_REQUEST.ALL .Pq Event 81H , Umask 01H Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC. .It Li UNC_ARB_TRK_REQUEST.WRITES .Pq Event 81H , Umask 20H Counts the number of allocated write entries, include full, partial, and LLC evictions. .It Li UNC_ARB_TRK_REQUEST.EVICTIONS .Pq Event 81H , Umask 80H Counts the number of LLC evictions allocated. .It Li UNC_ARB_COH , Umask TRK_OCCUPANCY.ALL .Pq Event 83H , Umask 01H Cycles weighted by number of requests pending in Coherency Tracker. .It Li UNC_ARB_COH , Umask TRK_REQUEST.ALL .Pq Event 84H , Umask 01H Number of requests allocated in Coherency Tracker. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.haswell 3 , .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS .An -nosplit The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . The support for the Haswell microarchitecture was added by .An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . diff --git a/lib/libpmc/pmc.haswellxeon.3 b/lib/libpmc/pmc.haswellxeon.3 index 75190301cc9f..5f9a5b20eb5c 100644 --- a/lib/libpmc/pmc.haswellxeon.3 +++ b/lib/libpmc/pmc.haswellxeon.3 @@ -1,956 +1,964 @@ .\" .\" Copyright (c) 2013 Hiren Panchasara .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd November 21, 2014 .Dt PMC.HASWELLXEON 3 .Os .Sh NAME .Nm pmc.haswellxeon .Nd measurement events for .Tn Intel .Tn Haswell Xeon family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Haswell" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to two classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Haswell Xeon PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" .%N "Order Number: 325462-052US" .%D September 2014 .%Q "Intel Corporation" .Re .Ss HASWELL FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss HASWELL PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry -cacheline reads. Does not count L2 data read prefetches or -instruction fetches. +cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Haswell programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H Loads blocked by overlapping with store buffer that cannot be forwarded. .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store-address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK .Pq Event 08H , Umask 01H Misses in all TLB levels that cause a page walk of any page size. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K .Pq Event 08H , Umask 02H Completed page walks due to demand load misses that caused 4K page walks in any TLB levels. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K .Pq Event 08H , Umask 02H Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H , Umask 0EH Completed page walks in any TLB of any page size due to demand load misses .It Li DTLB_LOAD_MISSES.WALK_DURATION .Pq Event 08H , Umask 10H Cycle PMH is busy with a walk. .It Li DTLB_LOAD_MISSES.STLB_HIT_4K .Pq Event 08H , Umask 20H Load misses that missed DTLB but hit STLB (4K). .It Li DTLB_LOAD_MISSES.STLB_HIT_2M .Pq Event 08H , Umask 40H Load misses that missed DTLB but hit STLB (2M). .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 60H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS .Pq Event 08H , Umask 80H DTLB demand load misses with low part of linear-to- physical address translation missed .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH , Umask 03H Cycles waiting to recover after Machine Clears -except JEClear. Set Cmask= 1. +except JEClear. +Set Cmask= 1. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H ncrements each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H -Number of flags-merge uops allocated. Such uops -adds delay. +Number of flags-merge uops allocated. +Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H -Number of slow LEA or similar uops allocated. Such -uop has 3 sources (e.g. 2 sources + immediate) +Number of slow LEA or similar uops allocated. +Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SiNGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li L2_RQSTS.DEMAND_DATA_RD_MISS .Pq Event 24H , Umask 21H Demand Data Read requests that missed L2, no rejects. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 41H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD -.Pq Event 24H , Umask E1H +.Pq Event 24H , Umask E1H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HIT .Pq Event 24H , Umask 42H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 22H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask E2H Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 44H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 24H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_DEMAND_MISS .Pq Event 24H , Umask 27H Demand requests that miss L2 cache. .It Li L2_RQSTS.ALL_DEMAND_REFERENCES .Pq Event 24H , Umask E7H Demand requests to L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask E4H Counts all L2 code requests. .It Li L2_RQSTS.L2_PF_HIT .Pq Event 24H , Umask 50H Counts all L2 HW prefetcher requests that hit L2. .It Li L2_RQSTS.L2_PF_MISS .Pq Event 24H , Umask 30H Counts all L2 HW prefetcher requests that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask F8H Counts all L2 HW prefetcher requests. .It Li L2_RQSTS.MISS .Pq Event 24H , Umask 3FH All requests that missed L2. .It Li L2_RQSTS.REFERENCES .Pq Event 24H , Umask FFH All requests to L2 cache. .It Li L2_DEMAND_RQSTS.WB_HIT .Pq Event 27H , Umask 50H Not rejected writebacks that hit L2 cache .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread -is not in a halt state. The thread enters the halt state -when it is running the HLT instruction. The core -frequency may change from time to time due to +is not in a halt state. +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H Increments the number of outstanding L1D misses -every cycle. Set Cmaks = 1 and Edge =1 to count -occurrences. +every cycle. +Set Cmaks = 1 and Edge =1 to count occurrences. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K .Pq Event 49H , Umask 02H Completed page walks due to store misses in one or more TLB levels of 4K page structure. .It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M .Pq Event 49H , Umask 04H Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure. .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 0EH Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 10H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT_4K .Pq Event 49H , Umask 20H Store misses that missed DTLB but hit STLB (4K). .It Li DTLB_STORE_MISSES.STLB_HIT_2M .Pq Event 49H , Umask 40H Store misses that missed DTLB but hit STLB (2M). .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 60H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li DTLB_STORE_MISSES.PDE_CACHE_MISS .Pq Event 49H , Umask 80H DTLB store misses with low part of linear-to-physical address translation missed. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PRE.HW_PF .Pq Event 4CH , Umask 02H Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED .Pq Event 58H , Umask 04H Number of integer Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED .Pq Event 58H , Umask 08H Number of SIMD Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.INT_ELIMINATED .Pq Event 58H , Umask 01H Unhalted core cycles when the thread is in ring 0. .It Li MOVE_ELIMINATION.SMID_ELIMINATED .Pq Event 58H , Umask 02H Number of SIMD Move Elimination candidate uops that were eliminated. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is in ring 0. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read transactions -in SQ to uncore. Set Cmask=1 to count cycles. +in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD .Pq Event 60H , Umask 02H Offcore outstanding Demand code Read transactions -in SQ to uncore. Set Cmask=1 to count cycles. +in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H -Offcore outstanding RFO store transactions in SQ to -uncore. Set Cmask=1 to count cycles. +Offcore outstanding RFO store transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read -transactions in SQ to uncore. Set Cmask=1 to count -cycles. +transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ -when MS_busy by DSB. Set Cmask = 1 to count -cycles. Add Edge=1 to count # of delivery. +when MS_busy by DSB. +Set Cmask = 1 to count cycles. +Add Edge=1 to count # of delivery. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H ncrement each cycle # of uops delivered to IDQ -when MS_busy by MITE. Set Cmask = 1 to count -cycles. +when MS_busy by MITE. +Set Cmask = 1 to count cycles. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from -MS by either DSB or MITE. Set Cmask = 1 to count -cycles. +MS by either DSB or MITE. +Set Cmask = 1 to count cycles. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered at least one uops. Set -Cmask = 1. +Counts cycles DSB is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered four uops. Set Cmask -=4. +Counts cycles DSB is delivered four uops. +Set Cmask =4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered at least one uops. Set -Cmask = 1. +Counts cycles MITE is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered four uops. Set Cmask -=4. +Counts cycles MITE is delivered four uops. +Set Cmask =4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and -Victim Cache Misses. Includes UC accesses. +Victim Cache Misses. +Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in ITLB that causes a page walk of any page size. .It Li ITLB_MISSES.WALK_COMPLETED_4K .Pq Event 85H , Umask 02H Completed page walks due to misses in ITLB 4K page entries. .It Li TLB_MISSES.WALK_COMPLETED_2M_4M .Pq Event 85H , Umask 04H Completed page walks due to misses in ITLB 2M/4M page entries. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 0EH Completed page walks in ITLB of any page size. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 10H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT_4K .Pq Event 85H , Umask 20H ITLB misses that hit STLB (4K). .It Li ITLB_MISSES.STLB_HIT_2M .Pq Event 85H , Umask 40H ITLB misses that hit STLB (2K). .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 60H -TLB misses that hit STLB. No page walk. +TLB misses that hit STLB. +No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. .It Li BR_INST_EXEC.NONTAKEN_COND .Pq Event 88H , Umask 41H Count conditional near branch instructions that were executed (but not necessarily retired) and not taken. .It Li BR_INST_EXEC.TAKEN_COND .Pq Event 88H , Umask 81H Count conditional near branch instructions that were executed (but not necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP .Pq Event 88H , Umask 82H Count all unconditional near branch instructions excluding calls and indirect branches. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 88H , Umask 84H Count executed indirect near branch instructions that are not calls nor returns. .It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H , Umask 88H Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H , Umask 90H Count unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H , Umask A0H Count indirect near calls, including both register and memory indirect, executed. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). .It Li BR_MISP_EXEC.NONTAKEN_COND .Pq Event 89H , Umask 41H Count conditional near branch instructions mispredicted as nontaken. .It Li BR_MISP_EXEC.TAKEN_COND .Pq Event 89H , Umask 81H Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 89H , Umask 84H Count mispredicted indirect near branch instructions that are not calls nor returns. .It Li BR_MISP_EXEC.RETURN_NEAR .Pq Event 89H , Umask 88H Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H , Umask 90H Count mispredicted unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H , Umask A0H Count mispredicted indirect near calls, including both register and memory indirect, executed. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. .It Li UOPS_EXECUTED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_2 .Pq Event A1H , Umask 04H Cycles which a Uop is dispatched on port 2 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_3 .Pq Event A1H , Umask 08H Cycles which a Uop is dispatched on port 3 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_4 .Pq Event A1H , Umask 10H Cycles which a Uop is dispatched on port 4 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_5 .Pq Event A1H , Umask 20H Cycles which a Uop is dispatched on port 5 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_6 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 6 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_7 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 7 in this thread. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available (not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H -Cycles with pending L2 miss loads. Set Cmask=2 to -count cycle. +Cycles with pending L2 miss loads. +Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING .Pq Event A3H , Umask 02H -Cycles with pending memory loads. Set Cmask=2 to -count cycle. +Cycles with pending memory loads. +Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.STALLS_L2_PENDING .Pq Event A3H , Umask 05H Number of loads missed L2. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 08H -Cycles with pending L1 cache miss loads. Set -Cmask=8 to count cycle. +Cycles with pending L1 cache miss loads. +Set Cmask=8 to count cycle. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD .Pq Event B0H , Umask 02H Demand code read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H -Data read requests sent to uncore (demand and -prefetch). +Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H Requires MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H Requires MSR 01A7H .It Li PAGE_WALKER_LOADS.DTLB_L1 .Pq Event BCH , Umask 11H Number of DTLB page walker loads that hit in the L1+FB. .It Li PAGE_WALKER_LOADS.ITLB_L1 .Pq Event BCH , Umask 21H Number of ITLB page walker loads that hit in the L1+FB. .It Li PAGE_WALKER_LOADS.DTLB_L2 .Pq Event BCH , Umask 12H Number of DTLB page walker loads that hit in the L2. .It Li PAGE_WALKER_LOADS.ITLB_L2 .Pq Event BCH , Umask 22H Number of ITLB page walker loads that hit in the L2. .It Li PAGE_WALKER_LOADS.DTLB_L3 .Pq Event BCH , Umask 14H Number of DTLB page walker loads that hit in the L3. .It Li PAGE_WALKER_LOADS.ITLB_L3 .Pq Event BCH , Umask 24H Number of ITLB page walker loads that hit in the L3. .It Li PAGE_WALKER_LOADS.DTLB_MEMORY .Pq Event BCH , Umask 18H Number of DTLB page walker loads from memory. .It Li PAGE_WALKER_LOADS.ITLB_MEMORY .Pq Event BCH , Umask 28H Number of ITLB page walker loads from memory. .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread-specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 08H Number of transitions from AVX-256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 10H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li OTHER_ASSISTS.ANY_WB_ASSIST .Pq Event C1H , Umask 40H Number of microcode assists invoked by HW upon uop writeback. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Number of self-modifying-code machine clears detected. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions Supports PEBS retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 FP assists due to Output values. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 FP assists due to input values. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH , Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Randomly sampled loads whose latency is above a -user defined threshold. A small fraction of the overall -loads are sampled due to randomization. +user defined threshold. +A small fraction of the overall loads are sampled due to randomization. .It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS .Pq Event D0H , Umask 11H Count retired load uops that missed the STLB. .It Li MEM_UOPS_RETIRED.STLB_MISS_STORES .Pq Event D0H , Umask 12H Count retired store uops that missed the STLB. .It Li MEM_UOPS_RETIRED.SPLIT_LOADS .Pq Event D0H , Umask 41H Count retired load uops that were split across a cache line. .It Li MEM_UOPS_RETIRED.SPLIT_STORES .Pq Event D0H , Umask 42H Count retired store uops that were split across a cache line. .It Li MEM_UOPS_RETIRED.ALL_LOADS .Pq Event D0H , Umask 81H Count all retired load uops. .It Li MEM_UOPS_RETIRED.ALL_STORES .Pq Event D0H , Umask 82H Count all retired store uops. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops with LLC cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_MISS .Pq Event D1H , Umask 10H -Retired load uops missed L2. Unknown data source -excluded. +Retired load uops missed L2. +Unknown data source excluded. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H , Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H , Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H , Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H , Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM .Pq Event D3H , Umask 01H Retired load uops which data sources missed LLC but serviced from local dram. .It Li BACLEARS.ANY .Pq Event E6H , Umask 1FH Number of front end re-steers due to BPU misprediction. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H Any MLC or LLC HW prefetch accessing L2, including rejects. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. .It Li L2_LINES_IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 05H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 06H Dirty L2 cache lines evicted by demand. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , -.Xr pmc.iaf 3 , -.Xr pmc.ucf 3 , -.Xr pmc.k7 3 , -.Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.haswell 3 , .Xr pmc.haswelluc 3 , +.Xr pmc.iaf 3 , .Xr pmc.ivybridge 3 , .Xr pmc.ivybridgexeon 3 , +.Xr pmc.k7 3 , +.Xr pmc.k8 3 , +.Xr pmc.p4 3 , +.Xr pmc.p5 3 , +.Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , -.Xr pmc.westmere 3 , -.Xr pmc.westmereuc 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , +.Xr pmc.ucf 3 , +.Xr pmc.westmere 3 , +.Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY Support for the Haswell Xeon microarchitecture first appeared in .Fx 10.2 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org . The support for the Haswell Xeon microarchitecture was written by .An "Randall Stewart" .Aq rrs@FreeBSD.org . diff --git a/lib/libpmc/pmc.iaf.3 b/lib/libpmc/pmc.iaf.3 index 3184c199c59c..f80560999f46 100644 --- a/lib/libpmc/pmc.iaf.3 +++ b/lib/libpmc/pmc.iaf.3 @@ -1,149 +1,148 @@ .\" Copyright (c) 2008 Joseph Koshy. All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd November 14, 2008 .Dt PMC.IAF 3 .Os .Sh NAME .Nm pmc.iaf .Nd measurement events for .Tn Intel fixed function performance counters. .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel fixed-function PMCs are present in CPUs that conform to version 2 or later of the .Tn Intel Performance Measurement Architecture. Each fixed-function PMC measures a specific hardware event. The number of fixed-function PMCs implemented in a CPU can vary. The number of fixed-function PMCs present can be determined at runtime by using function .Xr pmc_cpuinfo 3 . .Pp Intel fixed-function PMCs are documented in .Rs .%B "IA-32 Intel(R) Architecture Software Developer's Manual" .%T "Volume 3: System Programming Guide" .%N "Order Number 253669-027US" .%D July 2008 .%Q "Intel Corporation" .Re -.Pp .Ss PMC Capabilities Fixed-function PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta \&No .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta \&No .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta \&No .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Class Name Prefix These PMCs are named using a class name prefix of .Dq Li iaf- . .Ss Event Qualifiers (Fixed Function PMCs) These PMCs support the following modifiers: .Bl -tag -width indent .It Li os Configure the PMC to count events occurring at ring level 0. .It Li usr Configure the PMC to count events occurring at ring levels 1, 2 or 3. .It Li anythread .Pq Tn Atom CPUs Configure the PMC to count events on all logical processors sharing a processor core. The default is to count events on the current logical processor. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Fixed Function PMCs) The fixed function PMCs are selectable using the following event names: .Bl -tag -width indent .It Li INSTR_RETIRED.ANY .Pq Fixed Function Counter 0 The number of instructions retired. .It Li CPU_CLK_UNHALTED.CORE .Pq Fixed Function Counter 1 The number of core cycles for which the core is not halted. .It Li CPU_CLK_UNHALTED.REF .Pq Fixed Function Counter 2 The number of reference cycles for which the core is not halted. .El .Sh EXAMPLES To measure the number of core cycles for which the core was not halted use the event specifier .Qq iaf-cpu-clk-unhalted.core . .Pp To measure the number of user instructions retired use the event specifier .Qq iaf-instr-retired.any,usr . .Pp To measure the number of user instructions retired on all logical processors in an .Tn Atom CPU, use the event specifier .Qq iaf-instr-retired.any,usr,anythread . .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.core2 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . diff --git a/lib/libpmc/pmc.ivybridge.3 b/lib/libpmc/pmc.ivybridge.3 index b693b30ca73b..d86199b4d407 100644 --- a/lib/libpmc/pmc.ivybridge.3 +++ b/lib/libpmc/pmc.ivybridge.3 @@ -1,853 +1,863 @@ .\" Copyright (c) 2012 Fabien Thomas. All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd October 19, 2012 .Dt PMC.IVYBRIDGE 3 .Os .Sh NAME .Nm pmc.ivybridge .Nd measurement events for .Tn Intel .Tn Ivy Bridge family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Ivy Bridge" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Ivy Bridge PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-043US" .%D May 2012 .%Q "Intel Corporation" .Re .Ss IVYBRIDGE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss IVYBRIDGE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial -cachelines as well as demand data page table entry cacheline reads. Does not -count L2 data read prefetches or instruction fetches. +cachelines as well as demand data page table entry cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Ivy Bridge programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H loads blocked by overlapping with store buffer that cannot be forwarded . .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store- address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK .Pq Event 08H , Umask 81H Misses in all TLB levels that cause a page walk of any page size from demand loads. .It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED .Pq Event 08H , Umask 82H Misses in all TLB levels that caused page walk completed of any size by demand loads. .It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION .Pq Event 08H , Umask 84H Cycle PMH is busy with a walk due to demand loads. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1to count stalled cycles. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H -Number of flags-merge uops allocated. Such uops adds delay. +Number of flags-merge uops allocated. +Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H -Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 -sources + immediate) regardless if as a result of LEA instruction or not. +Number of slow LEA or similar uops allocated. +Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SINGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H , Umask 01H -Cycles that the divider is active, includes INT and FP. Set 'edge =1, -cmask=1' to count the number of divides. +Cycles that the divider is active, includes INT and FP. +Set 'edge =1, cmask=1' to count the number of divides. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 01H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H , Umask 03H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HITS .Pq Event 24H , Umask 04H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask 0CH Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 10H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 20H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask 30H Counts all L2 code requests. .It Li L2_RQSTS.PF_HIT .Pq Event 24H , Umask 40H Counts all L2 HW prefetcher requests that hit L2. .It Li L2_RQSTS.PF_MISS .Pq Event 24H , Umask 80H Counts all L2 HW prefetcher requests that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask C0H Counts all L2 HW prefetcher requests. .It Li L2_STORE_LOCK_RQSTS.MISS .Pq Event 27H , Umask 01H RFOs that miss cache lines. .It Li L2_STORE_LOCK_RQSTS.HIT_M .Pq Event 27H , Umask 08H RFOs that hit cache lines in M state. .It Li L2_STORE_LOCK_RQSTS.ALL .Pq Event 27H , Umask 0FH RFOs that access cache lines in any state. .It Li L2_L1D_WB_RQSTS.MISS .Pq Event 28H , Umask 01H Not rejected writebacks that missed LLC. .It Li L2_L1D_WB_RQSTS.HIT_E .Pq Event 28H , Umask 04H Not rejected writebacks from L1D to L2 cache lines in E state. .It Li L2_L1D_WB_RQSTS.HIT_M .Pq Event 28H , Umask 08H Not rejected writebacks from L1D to L2 cache lines in M state. .It Li L2_L1D_WB_RQSTS.ALL .Pq Event 28H , Umask 0FH Not rejected writebacks from L1D to L2 cache lines in any state. .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. -The thread enters the halt state when it is running the HLT instruction. The -core frequency may change from time to time due to power or thermal +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H -Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 -and Edge =1 to count occurrences. +Increments the number of outstanding L1D misses every cycle. +Set Cmaks = 1 and Edge =1 to count occurrences. Counter 2 only. Set Cmask = 1 to count cycles. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 02H Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 04H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 10H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PRE.HW_PF .Pq Event 4CH , Umask 02H Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED .Pq Event 58H , Umask 01H Number of integer Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED .Pq Event 58H , Umask 02H Number of SIMD Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.INT_ELIMINATED .Pq Event 58H , Umask 04H Number of integer Move Elimination candidate uops that were eliminated. .It Li MOVE_ELIMINATION.SIMD_ELIMINATED .Pq Event 58H , Umask 08H Number of SIMD Move Elimination candidate uops that were eliminated. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is in ring 0. Use Edge to count transition. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li TLB_ACCESS.LOAD_STLB_HIT .Pq Event 5FH , Umask 01H Counts load operations that missed 1st level DTLB but hit the 2nd level. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H -Offcore outstanding Demand Data Read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding Demand Data Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD .Pq Event 60H , Umask 02H -Offcore outstanding Demand Code Read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding Demand Code Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H -Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to -count cycles. +Offcore outstanding RFO store transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H -Offcore outstanding cacheable data read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding cacheable data read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Can combine Umask 04H and 20H. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Can combine Umask 08H and 10H Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H -Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set -Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. +Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. +Set Cmask = 1 to count cycles. +Add Edge=1 to count # of delivery. Can combine Umask 04H, 08H. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H -Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set -Cmask = 1 to count cycles. +Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. +Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or -MITE. Set Cmask = 1 to count cycles. +MITE. +Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered at least one uops. Set Cmask = 1. +Counts cycles DSB is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered four uops. Set Cmask = 4. +Counts cycles DSB is delivered four uops. +Set Cmask = 4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered at least one uops. Set Cmask = 1. +Counts cycles MITE is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered four uops. Set Cmask = 4. +Counts cycles MITE is delivered four uops. +Set Cmask = 4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in all ITLB levels that cause page walks. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 02H Misses in all ITLB levels that cause completed page walks. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 04H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. .It Li BR_INST_EXEC.NONTAKEN_COND .Pq Event 88H , Umask 41H Count conditional near branch instructions that were executed (but not necessarily retired) and not taken. .It Li BR_INST_EXEC.TAKEN_COND .Pq Event 88H , Umask 81H Count conditional near branch instructions that were executed (but not necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP .Pq Event 88H , Umask 82H Count all unconditional near branch instructions excluding calls and indirect branches. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 88H , Umask 84H Count executed indirect near branch instructions that are not calls nor returns. .It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H , Umask 88H Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H , Umask 90H Count unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H , Umask A0H Count indirect near calls, including both register and memory indirect, executed. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). .It Li BR_MISP_EXEC.NONTAKEN_COND .Pq Event 89H , Umask 41H Count conditional near branch instructions mispredicted as nontaken. .It Li BR_MISP_EXEC.TAKEN_COND .Pq Event 89H , Umask 81H Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 89H , Umask 84H Count mispredicted indirect near branch instructions that are not calls nor returns. .It Li BR_MISP_EXEC.RETURN_NEAR .Pq Event 89H , Umask 88H Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H , Umask 90H Count mispredicted unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H , Umask A0H Count mispredicted indirect near calls, including both register and memory indirect, executed. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. Use Cmask to qualify uop b/w. .It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1. .It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H , Umask 04H Cycles which a load uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H , Umask 08H Cycles which a store address uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H , Umask 0CH Cycles which a Uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H , Umask 10H Cycles which a load uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H , Umask 20H Cycles which a store address uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H , Umask 30H Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 4. .It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 5. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available. (not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH , Umask 01H Number of DSB to MITE switches. .It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH , Umask 02H Cycles DSB to MITE switches caused delay. .It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH , Umask 08H DSB Fill encountered > 3 DSB lines. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD .Pq Event B0H , Umask 02H Demand code read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.THREAD .Pq Event B1H , Umask 01H -Counts total number of uops to be executed per-thread each cycle. Set Cmask -= 1, INV =1 to count stall cycles. +Counts total number of uops to be executed per-thread each cycle. +Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. Do not need to set ANY. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H Off-core Response Performance Monitoring. PMC0 only. Requires programming MSR 01A6H. .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H Off-core Response Performance Monitoring. PMC3 only. Requires programming MSR 01A7H. .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread- specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. PMC1 only. Must quiesce other PMCs. .It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H , Umask 08H Number of assists associated with 256-bit AVX store operations. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 10H Number of transitions from AVX- 256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. Supports PEBS, use Any=1 for core granular. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Number of self-modifying-code machine clears detected. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions retired. Supports PEBS. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. Supports PEBS. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H , Umask 02H Direct and indirect mispredicted near call instructions retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H , Umask 10H Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H , Umask 20H Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 FP assists due to Output values. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 FP assists due to input values. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH , Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Sample loads with specified latency threshold. PMC3 only. Specify threshold in MSR 0x3F6. .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH , Umask 02H Sample stores and collect precise store operation via PEBS record. PMC3 only. .It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS .Pq Event D0H , Umask 11H Count retired load uops that missed the STLB. .It Li MEM_UOPS_RETIRED.STLB_MISS_STORES .Pq Event D0H , Umask 12H Count retired store uops that missed the STLB. .It Li MEM_UOPS_RETIRED.SPLIT_LOADS .Pq Event D0H , Umask 41H Count retired load uops that were split across a cache line. .It Li MEM_UOPS_RETIRED.SPLIT_STORES .Pq Event D0H , Umask 42H Count retired store uops that were split across a cache line. .It Li MEM_UOPS_RETIRED.ALL_LOADS .Pq Event D0H , Umask 81H Count all retired load uops. .It Li MEM_UOPS_RETIRED.ALL_STORES .Pq Event D0H , Umask 82H Count all retired store uops. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. Supports PEBS. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops with LLC cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H , Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H , Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H , Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H , Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM .Pq Event D3H , Umask 01H Retired load uops which data sources missed LLC but serviced from local dram. Supports PEBS. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H Any MLC or LLC HW prefetch accessing L2, including rejects. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. Counting does not cover rejects. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 01H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 02H Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H , Umask 04H Clean L2 cache lines evicted by the MLC prefetcher. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H , Umask 08H Dirty L2 cache lines evicted by the MLC prefetcher. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.iaf 3 , .Xr pmc.ivybridgexeon 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS .An -nosplit The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . The support for the Ivy Bridge microarchitecture was written by .An Fabien Thomas Aq Mt fabient@FreeBSD.org . diff --git a/lib/libpmc/pmc.ivybridgexeon.3 b/lib/libpmc/pmc.ivybridgexeon.3 index 2ee5b782cc42..1bbe16039bd2 100644 --- a/lib/libpmc/pmc.ivybridgexeon.3 +++ b/lib/libpmc/pmc.ivybridgexeon.3 @@ -1,883 +1,896 @@ .\" Copyright (c) 2013 Hiren Panchasara .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" -.Dd Jan 25, 2013 +.Dd January 25, 2013 .Dt PMC.IVYBRIDGEXEON 3 .Os .Sh NAME .Nm pmc.ivybridgexeon .Nd measurement events for .Tn Intel .Tn Ivy Bridge Xeon family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Ivy Bridge Xeon" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Ivy Bridge Xeon PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" .%N "Order Number: 325462-045US" .%D January 2013 .%Q "Intel Corporation" .Re .Ss IVYBRIDGE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss IVYBRIDGE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial -cachelines as well as demand data page table entry cacheline reads. Does not -count L2 data read prefetches or instruction fetches. +cachelines as well as demand data page table entry cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Ivy Bridge programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H loads blocked by overlapping with store buffer that cannot be forwarded . .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store- address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK .Pq Event 08H , Umask 81H Misses in all TLB levels that cause a page walk of any page size from demand loads. .It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED .Pq Event 08H , Umask 82H Misses in all TLB levels that caused page walk completed of any size by demand loads. .It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION .Pq Event 08H , Umask 84H Cycle PMH is busy with a walk due to demand loads. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1to count stalled cycles. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H -Number of flags-merge uops allocated. Such uops adds delay. +Number of flags-merge uops allocated. +Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H -Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 -sources + immediate) regardless if as a result of LEA instruction or not. +Number of slow LEA or similar uops allocated. +Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SINGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H , Umask 01H -Cycles that the divider is active, includes INT and FP. Set 'edge =1, -cmask=1' to count the number of divides. +Cycles that the divider is active, includes INT and FP. +Set 'edge =1, cmask=1' to count the number of divides. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 01H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H , Umask 03H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HITS .Pq Event 24H , Umask 04H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask 0CH Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 10H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 20H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask 30H Counts all L2 code requests. .It Li L2_RQSTS.PF_HIT .Pq Event 24H , Umask 40H Counts all L2 HW prefetcher requests that hit L2. .It Li L2_RQSTS.PF_MISS .Pq Event 24H , Umask 80H Counts all L2 HW prefetcher requests that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask C0H Counts all L2 HW prefetcher requests. .It Li L2_STORE_LOCK_RQSTS.MISS .Pq Event 27H , Umask 01H RFOs that miss cache lines. .It Li L2_STORE_LOCK_RQSTS.HIT_M .Pq Event 27H , Umask 08H RFOs that hit cache lines in M state. .It Li L2_STORE_LOCK_RQSTS.ALL .Pq Event 27H , Umask 0FH RFOs that access cache lines in any state. .It Li L2_L1D_WB_RQSTS.MISS .Pq Event 28H , Umask 01H Not rejected writebacks that missed LLC. .It Li L2_L1D_WB_RQSTS.HIT_E .Pq Event 28H , Umask 04H Not rejected writebacks from L1D to L2 cache lines in E state. .It Li L2_L1D_WB_RQSTS.HIT_M .Pq Event 28H , Umask 08H Not rejected writebacks from L1D to L2 cache lines in M state. .It Li L2_L1D_WB_RQSTS.ALL .Pq Event 28H , Umask 0FH Not rejected writebacks from L1D to L2 cache lines in any state. .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. -The thread enters the halt state when it is running the HLT instruction. The -core frequency may change from time to time due to power or thermal -throttling. +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H -Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 -and Edge =1 to count occurrences. +Increments the number of outstanding L1D misses every cycle. +Set Cmaks = 1 and Edge =1 to count occurrences. Counter 2 only. Set Cmask = 1 to count cycles. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 02H Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 04H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 10H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PRE.HW_PF .Pq Event 4CH , Umask 02H Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED .Pq Event 58H , Umask 01H Number of integer Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED .Pq Event 58H , Umask 02H Number of SIMD Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.INT_ELIMINATED .Pq Event 58H , Umask 04H Number of integer Move Elimination candidate uops that were eliminated. .It Li MOVE_ELIMINATION.SIMD_ELIMINATED .Pq Event 58H , Umask 08H Number of SIMD Move Elimination candidate uops that were eliminated. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is in ring 0. Use Edge to count transition. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 5FH , Umask 04H Counts load operations that missed 1st level DTLB but hit the 2nd level. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H -Offcore outstanding Demand Data Read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding Demand Data Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD .Pq Event 60H , Umask 02H -Offcore outstanding Demand Code Read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding Demand Code Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H -Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to -count cycles. +Offcore outstanding RFO store transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H -Offcore outstanding cacheable data read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding cacheable data read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Can combine Umask 04H and 20H. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Can combine Umask 08H and 10H Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H -Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set -Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. +Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. +Set Cmask = 1 to count cycles. +Add Edge=1 to count # of delivery. Can combine Umask 04H, 08H. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H -Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set -Cmask = 1 to count cycles. +Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. +Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or -MITE. Set Cmask = 1 to count cycles. +MITE. +Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered at least one uops. Set Cmask = 1. +Counts cycles DSB is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered four uops. Set Cmask = 4. +Counts cycles DSB is delivered four uops. +Set Cmask = 4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered at least one uops. Set Cmask = 1. +Counts cycles MITE is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered four uops. Set Cmask = 4. +Counts cycles MITE is delivered four uops. +Set Cmask = 4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in all ITLB levels that cause page walks. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 02H Misses in all ITLB levels that cause completed page walks. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 04H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. .It Li BR_INST_EXEC.NONTAKEN_COND .Pq Event 88H , Umask 41H Count conditional near branch instructions that were executed (but not necessarily retired) and not taken. .It Li BR_INST_EXEC.TAKEN_COND .Pq Event 88H , Umask 81H Count conditional near branch instructions that were executed (but not necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP .Pq Event 88H , Umask 82H Count all unconditional near branch instructions excluding calls and indirect branches. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 88H , Umask 84H Count executed indirect near branch instructions that are not calls nor returns. .It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H , Umask 88H Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H , Umask 90H Count unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H , Umask A0H Count indirect near calls, including both register and memory indirect, executed. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). .It Li BR_MISP_EXEC.NONTAKEN_COND .Pq Event 89H , Umask 41H Count conditional near branch instructions mispredicted as nontaken. .It Li BR_MISP_EXEC.TAKEN_COND .Pq Event 89H , Umask 81H Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 89H , Umask 84H Count mispredicted indirect near branch instructions that are not calls nor returns. .It Li BR_MISP_EXEC.RETURN_NEAR .Pq Event 89H , Umask 88H Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H , Umask 90H Count mispredicted unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H , Umask A0H Count mispredicted indirect near calls, including both register and memory indirect, executed. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. Use Cmask to qualify uop b/w. .It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1. .It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H , Umask 04H Cycles which a load uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H , Umask 08H Cycles which a store address uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H , Umask 0CH Cycles which a Uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H , Umask 10H Cycles which a load uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H , Umask 20H Cycles which a store address uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H , Umask 30H Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 4. .It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 5. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available. (not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H -Cycles with pending L2 miss loads. Set AnyThread to count per core. +Cycles with pending L2 miss loads. +Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING .Pq Event A3H , Umask 02H -Cycles with pending memory loads. Set AnyThread to count per core. +Cycles with pending memory loads. +Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_NO_EXECUTE .Pq Event A3H , Umask 04H -Cycles of dispatch stalls. Set AnyThread to count per core. +Cycles of dispatch stalls. +Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 08H -Cycles with pending L1 cache miss loads. Set AnyThread to count per core. +Cycles with pending L1 cache miss loads. +Set AnyThread to count per core. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH , Umask 01H Number of DSB to MITE switches. .It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH , Umask 02H Cycles DSB to MITE switches caused delay. .It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH , Umask 08H DSB Fill encountered > 3 DSB lines. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD .Pq Event B0H , Umask 02H Demand code read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.THREAD .Pq Event B1H , Umask 01H -Counts total number of uops to be executed per-thread each cycle. Set Cmask -= 1, INV =1 to count stall cycles. +Counts total number of uops to be executed per-thread each cycle. +Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. Do not need to set ANY. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H Off-core Response Performance Monitoring. PMC0 only. Requires programming MSR 01A6H. .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H Off-core Response Performance Monitoring. PMC3 only. Requires programming MSR 01A7H. .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread- specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. PMC1 only. Must quiesce other PMCs. .It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H , Umask 08H Number of assists associated with 256-bit AVX store operations. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 10H Number of transitions from AVX- 256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. Supports PEBS, use Any=1 for core granular. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Number of self-modifying-code machine clears detected. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions retired. Supports PEBS. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. Supports PEBS. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H , Umask 02H Direct and indirect mispredicted near call instructions retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H , Umask 10H Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H , Umask 20H Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 FP assists due to Output values. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 FP assists due to input values. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH , Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Sample loads with specified latency threshold. PMC3 only. Specify threshold in MSR 0x3F6. .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH , Umask 02H Sample stores and collect precise store operation via PEBS record. PMC3 only. .It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS .Pq Event D0H , Umask 11H Count retired load uops that missed the STLB. .It Li MEM_UOPS_RETIRED.STLB_MISS_STORES .Pq Event D0H , Umask 12H Count retired store uops that missed the STLB. .It Li MEM_UOPS_RETIRED.SPLIT_LOADS .Pq Event D0H , Umask 41H Count retired load uops that were split across a cache line. .It Li MEM_UOPS_RETIRED.SPLIT_STORES .Pq Event D0H , Umask 42H Count retired store uops that were split across a cache line. .It Li MEM_UOPS_RETIRED.ALL_LOADS .Pq Event D0H , Umask 81H Count all retired load uops. .It Li MEM_UOPS_RETIRED.ALL_STORES .Pq Event D0H , Umask 82H Count all retired store uops. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. Supports PEBS. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops whose data source was LLC hit with no snoop required. .It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS .Pq Event D1H , Umask 20H Retired load uops whose data source is LLC miss. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H , Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H , Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H , Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H , Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM .Pq Event D3H , Umask 01H Retired load uops which data sources missed LLC but serviced from local dram. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM .Pq Event D3H , Umask 04H Retired load uops whose data source was remote DRAM. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM .Pq Event D3H , Umask 10H Retired load uops whose data source was remote HITM. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD .Pq Event D3H , Umask 20H Retired load uops whose data source was forwards from a remote cache. .It Li BACLEARS.ANY .Pq Event E6H , Umask 1FH Number of front end re-steers due to BPU misprediction. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H Any MLC or LLC HW prefetch accessing L2, including rejects. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. Counting does not cover rejects. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 01H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 02H Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H , Umask 04H Clean L2 cache lines evicted by the MLC prefetcher. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H , Umask 08H Dirty L2 cache lines evicted by the MLC prefetcher. .It Li L2_LINES_OUT.DIRTY_ALL .Pq Event F2H , Umask 0AH Dirty L2 cache lines filling the L2. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.iaf 3 , .Xr pmc.ivybridge 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS .An -nosplit The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . The support for the Ivy Bridge Xeon microarchitecture was written by .An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . diff --git a/lib/libpmc/pmc.sandybridge.3 b/lib/libpmc/pmc.sandybridge.3 index 0e219ae3aeaa..5d1c18683749 100644 --- a/lib/libpmc/pmc.sandybridge.3 +++ b/lib/libpmc/pmc.sandybridge.3 @@ -1,939 +1,942 @@ .\" Copyright (c) 2012 Davide Italiano .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd October 19, 2012 .Dt PMC.SANDYBRIDGE 3 .Os .Sh NAME .Nm pmc.sandybridge .Nd measurement events for .Tn Intel .Tn Sandy Bridge family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Sandy Bridge" CPUs contain PMCs conforming to the version 3 of the .Tn Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .It Li PMC_CLASS_TSC These PMCs are documented in .Xr pmc.tsc 3 . .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Sandy Bridge PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-039US" .%D May 2011 .%Q "Intel Corporation" .Re .Ss SANDY BRIDGE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss SANDY BRIDGE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial -cachelines as well as demand data page table entry cacheline reads. Does not -count L2 data read prefetches or instruction fetches. +cachelines as well as demand data page table entry cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Sandy Bridge programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.DATA_UNKNOWN .Pq EVENT_03H, Umask 01H Blocked loads due to store buffer blocks with unknown data. .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H, Umask 02H Loads blocked by overlapping with store buffer that cannot be forwarded. .It Li LD_BLOCKS.NO_SR .Pq Event 03H, Umask 08H # of Split loads blocked due to resource not available. .It Li LD_BLOCKS.ALL_BLOCK .Pq EVENT_03H, Umask 10H Number of cases where any load is blocked but has no DCU miss. .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H, Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H, Umask 02H Speculative cache-line split Store-address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H, Umask 01H False dependencies in MOB due to partial compare on address. .It Li LD_BLOCKS_PARTIAL.ALL_STA_BLOCK .Pq Event 07H, Umask 08H The number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type. .It LI DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK .Pq Event 08H, Umask 01H Misses in all TLB levels that cause a page walk of any page size. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H, Umask 02H Misses in all TLB levels that caused page walk completed of any size. .It Li DTLB_LOAD_MISSES.WALK_DURATION .Pq Event 08H, Umask 04H Cycle PMH is busy with a walk. .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H, Umask 10H Number of cache load STLB hits. No page walk. .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH, Umask 03H Cycles waiting to recover after Machine Clears or JEClear. Set Cmask = 1. Set Edge to count occurrences .It Li INT_MISC.RAT_STALL_CYCLES .Pq Event 0DH, Umask 40H Cycles RAT external stall is sent to IDQ for this thread. .It Li UOPS_ISSUED.ANY .Pq Event 0EH, Umask 01H Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1 to count stalled cycles of this core. Set Cmask = 1, Inv = 1 to count stalled cycles .It Li FP_COMP_OPS_EXE.X87 .Pq Event 10H, Umask 01H Counts number of X87 uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE .Pq Event 10H, Umask 10H Counts number of SSE* double precision FP packed uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE .Pq Event 10H, Umask 20H Counts number of SSE* single precision FP scalar uops executed. .It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE .Pq Event 10H, Umask 40H Counts number of SSE* single precision FP packed uops executed. .It LiFP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE .Pq Event 10H, Umask 80H Counts number of SSE* double precision FP scalar uops executed. .It Li SIMD_FP_256.PACKED_SINGLE .Pq Event 11H, Umask 01H Counts 256-bit packed single-precision floating-point instructions. .It Li SIMD_FP_256.PACKED_DOUBLE .Pq Event 11H, Umask 02H Counts 256-bit packed double-precision floating-point instructions. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H, Umask 01H Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides. .It Li INSTS_WRITTEN_TO_IQ.INSTS .Pq Event 17H, Umask 01H Counts the number of instructions written into the IQ every cycle. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H, Umask 01H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H, Umask 03H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HITS .Pq Event 24H, Umask 04H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H, Umask 08H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H, Umask 0CH Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H, Umask 10H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H, Umask 20H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H, Umask 30H Counts all L2 code requests. .It Li L2_RQSTS.PF_HIT .Pq Event 24H, Umask 40H Requests from L2 Hardware prefetcher that hit L2. .It Li L2_RQSTS.PF_MISS .Pq Event 24H, Umask 80H Requests from L2 Hardware prefetcher that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H, Umask C0H Any requests from L2 Hardware prefetchers. .It Li L2_STORE_LOCK_RQSTS.MISS .Pq Event 27H, Umask 01H RFOs that miss cache lines. .It Li L2_STORE_LOCK_RQSTS.HIT_E .Pq Event 27H, Umask 04H RFOs that hit cache lines in E state. .It Li L2_STORE_LOCK_RQSTS.HIT_M .Pq EVENT_27H, Umask 08H RFOs that hit cache lines in M state. .It Li L2_STORE_LOCK_RQSTS.ALL .Pq EVENT_27H, Umask 0FH RFOs that access cache lines in any state. .It Li L2_L1D_WB_RQSTS.HIT_E .Pq Event 28H, Umask 04H Not rejected writebacks from L1D to L2 cache lines in E state. .It Li L2_L1D_WB_RQSTS.HIT_M .Pq Event 28H, Umask 08H Not rejected writebacks from L1D to L2 cache lines in M state. .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH, Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH, Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH, Umask 00H Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH, Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H, Umask 01H Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences. Counter 2 only; Set Cmask = 1 to count cycles. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H, Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H, Umask 02H Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H, Umask 04H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H, Umask 10H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH, Umask 01H Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PER.HW_PF .Pq Event 4CH, Umask 02H Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li HW_PRE_REQ.DL1_MISS .Pq Event 4EH, Umask 02H Hardware Prefetch requests that miss the L1D cache. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for example. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. .It Li L1D.REPLACEMENT .Pq Event 51H, Umask 01H Counts the number of lines brought into the L1 data cache. .It Li L1D.ALLOCATED_IN_M .Pq Event 51H, Umask 02H Counts the number of allocations of modified L1D cache lines. .It Li L1D.EVICTION .Pq Event 51H, Umask 04H Counts the number of modified lines evicted from the L1 data cache due to replacement. .It Li L1D.ALL_M_REPLACEMENT .Pq Event 51H, Umask 08H Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement. .It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP .Pq Event 59H, Umask 20H Increments the number of flags-merge uops in flight each cycle. Set Cmask = 1 to count cycles. .It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW .Pq Event 59H, Umask 40H Cycles with at least one slow LEA uop allocated. .It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP .Pq Event 59H, Umask 80H Number of Multiply packed/scalar single precision uops allocated. .It Li RESOURCE_STALLS2.ALL_FL_EMPTY .Pq Event 5BH, Umask 0CH Cycles stalled due to free list empty. .It Li RESOURCE_STALLS2.ALL_PRF_CONTROL .Pq Event 5BH, Umask 0FH Cycles stalled due to control structures full for physical registers. .It Li RESOURCE_STALLS2.BOB_FULL .Pq Event 5BH, Umask 40H Cycles Allocator is stalled due to Branch Order Buffer. .It Li RESOURCE_STALLS2.OOO_RSRC .Pq Event 5BH, Umask 4FH Cycles stalled due to out of order resources full. .It Li CPL_CYCLES.RING0 .Pq Event 5CH, Umask 01H Unhalted core cycles when the thread is in ring 0. Use Edge to count transition .It Li CPL_CYCLES.RING123 .Pq Event 5CH, Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH, Umask 01H Cycles the RS is empty for the thread. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H, Umask 01H Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H, Umask 04H Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H, Umask 08H Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H, Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H, Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H, Umask 02H Counts cycles the IDQ is empty. .It Li IQD.MITE_UOPS .Pq Event 79H, Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. Can combine Umask 04H and 20H .It Li IDQ.DSB_UOPS .Pq Event 79H, Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. Can combine Umask 08H and 10H .It Li IDQ.MS_DSB_UOPS .Pq Event 79H, Umask 10H Increment each cycle # of uops delivered to IDQ when MS busy by DSB. Set Cmask = 1 to count cycles MS is busy. Set Cmask=1 and Edge=1 to count MS activations. Can combine Umask 08H and 10H .It Li IDQ.MS_MITE_UOPS .Pq Event 79H, Umask 20H Increment each cycle # of uops delivered to IDQ when MS is busy by MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H and 20H .It Li IDQ.MS_UOPS .Pq Event 79H, Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H and 30H .It Li ICACHE.MISSES .Pq Event 80H, Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H, Umask 01H Misses in all ITLB levels that cause page walks. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H, Umask 02H Misses in all ITLB levels that cause completed page walks. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H, Umask 04H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H, Umask 10H Number of cache load STLB hits. No page walk. .It Li ILD_STALL.LCP .Pq Event 87H, Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H, Umask 04H Stall cycles due to IQ is full. .It Li BR_INST_EXEC.NONTAKEN_COND .Pq Event 88H , Umask 41H Count conditional near branch instructions that were executed (but not necessarily retired) and not taken. .It Li BR_INST_EXEC.TAKEN_COND .Pq Event 88H , Umask 81H Count conditional near branch instructions that were executed (but not necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP .Pq Event 88H , Umask 82H Count all unconditional near branch instructions excluding calls and indirect branches. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 88H , Umask 84H Count executed indirect near branch instructions that are not calls nor returns. .It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H , Umask 88H Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H , Umask 90H Count unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H , Umask A0H Count indirect near calls, including both register and memory indirect, executed. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). .It Li BR_MISP_EXEC.NONTAKEN_COND .Pq Event 89H , Umask 41H Count conditional near branch instructions mispredicted as nontaken. .It Li BR_MISP_EXEC.TAKEN_COND .Pq Event 89H , Umask 81H Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 89H , Umask 84H Count mispredicted indirect near branch instructions that are not calls nor returns. .It Li BR_MISP_EXEC.RETURN_NEAR .Pq Event 89H , Umask 88H Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H , Umask 90H Count mispredicted unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H , Umask A0H Count mispredicted indirect near calls, including both register and memory indirect, executed. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH, Umask 01H Count number of non-delivered uops to RAT per thread. Use Cmask to qualify uop b/w .It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H, Umask 01H Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H, Umask 02H Cycles which a Uop is dispatched on port 1. .It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H, Umask 04H Cycles which a load uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H, Umask 08H Cycles which a store address uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H, Umask 0CH Cycles which a Uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H, Umask 10H Cycles which a load uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H, Umask 20H Cycles which a store address uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H, Umask 30H .Pq Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H, Umask 40H Cycles which a Uop is dispatched on port 4. .It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H, Umask 80H Cycles which a Uop is dispatched on port 5. .It Li RESOURCE_STALLS.ANY .Pq Event A2H, Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.LB .Pq Event A2H, Umask 02H Counts the cycles of stall due to lack of load buffers. .It Li RESOURCE_STALLS.LB .Pq Event A2H, Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H, Umask 08H Cycles stalled due to no store buffers available. (not including draining form sync) .It Li RESOURCE_STALLS.ROB .Pq Event A2H, Umask 10H Cycles stalled due to re-order buffer full. .It Li RESOURCE_STALLS.FCSW .Pq Event A2H, Umask 20H Cycles stalled due to writing the FPU control word. .It Li RESOURCE_STALLS.MXCSR .Pq Event A2H, Umask 40H Cycles stalled due to the MXCSR register rename occurring to close to a previous MXCSR rename. .It Li RESOURCE_STALLS.OTHER .Pq Event A2H, Umask 80H Cycles stalled while execution was stalled due to other resource issues. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH, Umask 01H Number of DSB to MITE switches. .It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH, Umask 02H Cycles DSB to MITE switches caused delay. .It Li DSB_FILL.OTHER_CANCEL .Pq Event ACH, Umask 02H Cases of cancelling valid DSB fill not because of exceeding way limit. .It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH, Umask 08H DSB Fill encountered > 3 DSB lines. .It Li DSB_FILL.ALL_CANCEL .Pq Event ACH, Umask 0AH Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit. .It Li ITLB.ITLB_FLUSH .Pq Event AEH, Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H, Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H, Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H, Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_DISPATCHED.THREAD .Pq Event B1H, Umask 01H Counts total number of uops to be dispatched per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_DISPATCHED.CORE .Pq Event B1H, Umask 02H Counts total number of uops to be dispatched per-core each cycle. Do not need to set ANY .It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL .Pq Event B2H, Umask 01H Offcore requests buffer cannot take more entries for this thread core. .It Li AGU_BYPASS_CANCEL.COUNT .Pq Event B6H, Umask 01H Counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another page. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H, Umask 01H Off-core Response Performance Monitoring; PMC0 only. Requires programming MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH, Umask 01H -Off-core Response Performance Monitoring. PMC3 only. +Off-core Response Performance Monitoring. +PMC3 only. Requires programming MSR 01A7H .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH, Umask 01H DTLB flush attempts of the thread-specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH, Umask 20H Count number of STLB flush attempts. .It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES .Pq Event BFH, Umask 05H Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports. cmask=1 .It Li INST_RETIRED.ANY_P .Pq Event C0H, Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.PREC_DIST .Pq Event C0H, Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution PMC1 only; Must quiesce other PMCs. .It Li INST_RETIRED.X87 .Pq Event C0H, Umask 02H X87 instruction retired event. .It Li OTHER_ASSISTS.ITLB_MISS_RETIRED .Pq Event C1H, Umask 02H Instructions that experienced an ITLB miss. .It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H, Umask 08H Number of assists associated with 256-bit AVX store operations. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H, Umask 10H Number of transitions from AVX256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H, Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li UOPS_RETIRED.ALL .Pq Event C2H, Umask 01H Counts the number of micro-ops retired. Use cmask=1 and invert to count active cycles or stalled cycles. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H, Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H, Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H, Umask 04H Counts the number of times that a program writes to a code section. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H, Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCH .Pq Event C4H, Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H, Umask 01H Counts the number of conditional branch instructions retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H, Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H, Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H, Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H, Umask 10H Counts the number of not taken branch instructions retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H, Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H, Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H, Umask 00H Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H, Umask 01H Mispredicted conditional branch instructions retired. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H, Umask 02H Direct and indirect mispredicted near call instructions retired. .It Li BR_MISP_RETIRED.ALL_BRANCH .Pq Event C5H, Umask 04H Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H, Umask 10H Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H, Umask 20H Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH, Umask 02H Number of X87 assists due to output value. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH, Umask 04H Number of X87 assists due to input value. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH, Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH, Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH, Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH, Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH, Umask 01H Sample loads with specified latency threshold. PMC3 only. Specify threshold in MSR 0x3F6. .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH, Umask 02H Sample stores and collect precise store operation via PEBS record. PMC3 only. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H, Umask 01H Qualify retired memory uops that are loads. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STORES .Pq Event D0H, Umask 02H Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H, Umask 10H Qualify retired memory uops with STLB miss. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H, Umask 20H Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H, Umask 40H Qualify retired memory uops with line split. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED_ALL .Pq Event D0H, Umask 80H Qualify any retired memory uops. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H, Umask 01H Retired load uops with L1 cache hits as data sources. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H, Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H, Umask 04H Retired load uops which data sources were data hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H, Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H, Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H, Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H, Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H, Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS .Pq Event D4H, Umask 02H Retired load uops with unknown information as data source in cache serviced the load. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H, Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RF0 .Pq Event F0H, Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H, Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H, Umask 08H L2 or LLC HW prefetches that access L2 cache. .It Li L2_TRANS.L1D_WB .Pq Event F0H, Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H, Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H, Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H, Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H, Umask 01H L2 cache lines in I state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.S .Pq Event F1H, Umask 02H L2 cache lines in S state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.E .Pq Event F1H, Umask 04H L2 cache lines in E state filling L2. Counting does not cover rejects. .It Li L2_LINES-IN.ALL .Pq Event F1H, Umask 07H L2 cache lines filling L2. Counting does not cover rejects. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H, Umask 01H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H, Umask 02H Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H, Umask 04H Clean L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H, Umask 08H Dirty L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.DIRTY_ALL .Pq Event F2H, Umask 0AH Dirty L2 cache lines filling the L2. Counting does not cover rejects. .It Li SQ_MISC.SPLIT_LOCK .Pq Event F4H, Umask 10H Split locks in SQ. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.iaf 3 , .Xr pmc.ivybridge 3 , .Xr pmc.ivybridgexeon 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS .An -nosplit The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . The support for the Sandy Bridge microarchitecture was written by .An Davide Italiano Aq Mt davide@FreeBSD.org . diff --git a/lib/libpmc/pmc.sandybridgexeon.3 b/lib/libpmc/pmc.sandybridgexeon.3 index b334c16265fa..4abd1fa8aa19 100644 --- a/lib/libpmc/pmc.sandybridgexeon.3 +++ b/lib/libpmc/pmc.sandybridgexeon.3 @@ -1,1011 +1,1019 @@ .\" Copyright (c) 2012 Hiren Panchasara .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd October 18, 2012 .Dt PMC.SANDYBRIDGEXEON 3 .Os .Sh NAME .Nm pmc.sandybridgexeon .Nd measurement events for .Tn Intel .Tn Sandy Bridge Xeon family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Sandy Bridge Xeon" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to two classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Sandy Bridge Xeon PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-043US" .%D August 2012 .%Q "Intel Corporation" .Re .Ss SANDYBRIDGE XEON FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss SANDYBRIDGE XEON PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial -cachelines as well as demand data page table entry cacheline reads. Does not -count L2 data read prefetches or instruction fetches. +cachelines as well as demand data page table entry cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Sandy Bridge Xeon programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.DATA_UNKNOWN .Pq Event 03H , Umask 01H blocked loads due to store buffer blocks with unknown data. .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H loads blocked by overlapping with store buffer that cannot be forwarded . .It Li LD_BLOCKS.NO_SR .Pq Event 03H , Umask 08H # of Split loads blocked due to resource not available. .It Li LD_BLOCKS.ALL_BLOCK .Pq Event 03H , Umask 10H Number of cases where any load is blocked but has no DCU miss. .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store- address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li LD_BLOCKS_PARTIAL.ALL_STALL_BLOCK .Pq Event 07H , Umask 08H The number of times that load operations are temporarily blocked because of older stores, with addresses that are -not yet known. A load operation may incur more than one -block of this type. +not yet known. +A load operation may incur more than one block of this type. .It Li TLB_LOAD_MISSES.MISS_CAUSES_A_WALK .Pq Event 08H , Umask 01H Misses in all TLB levels that cause a page walk of any page size. .It Li TLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H , Umask 02H Misses in all TLB levels that caused page walk completed of any size. .It Li DTLB_LOAD_MISSES.WALK_DURATION .Pq Event 08H , Umask 04H Cycle PMH is busy with a walk. .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 10H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH , Umask 03H Cycles waiting to recover after Machine Clears or EClear. Set Cmask= 1. .It Li INT_MISC.RAT_STALL_CYCLES .Pq Event 0DH , Umask 40H Cycles RAT external stall is sent to IDQ for this thread. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li FP_COMP_OPS_EXE.X87 .Pq Event 10H , Umask 01H Counts number of X87 uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE .Pq Event 10H , Umask 10H Counts number of SSE* double precision FP packed uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE .Pq Event 10H , Umask 20H Counts number of SSE* single precision FP scalar uops executed. .It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE .Pq Event 10H , Umask 40H Counts number of SSE* single precision FP packed uops executed. .It Li FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE .Pq Event 10H , Umask 80H Counts number of SSE* double precision FP scalar uops executed. .It Li SIMD_FP_256.PACKED_SINGLE .Pq Event 11H , Umask 01H Counts 256-bit packed single-precision floating- point instructions. .It Li SIMD_FP_256.PACKED_DOUBLE .Pq Event 11H , Umask 02H Counts 256-bit packed double-precision floating- point instructions. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H , Umask 01H Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides. .It Li INSTS_WRITTEN_TO_IQ.INSTS .Pq Event 17H , Umask 01H Counts the number of instructions written into the IQ every cycle. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 01H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H , Umask 03H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HITS .Pq Event 24H , Umask 04H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask 0CH Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 10H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 20H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask 30H Counts all L2 code requests. .It Li L2_RQSTS.PF_HIT .Pq Event 24H , Umask 40H Requests from L2 Hardware prefetcher that hit L2. .It Li L2_RQSTS.PF_MISS .Pq Event 24H , Umask 80H Requests from L2 Hardware prefetcher that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask C0H Any requests from L2 Hardware prefetchers. .It Li L2_STORE_LOCK_RQSTS.MISS .Pq Event 27H , Umask 01H ROs that miss cache lines. .It Li L2_STORE_LOCK_RQSTS.HIT_E .Pq Event 27H , Umask 04H RFOs that hit cache lines in E state. .It Li L2_STORE_LOCK_RQSTS.HIT_M .Pq Event 27H , Umask 08H RFOs that hit cache lines in M state. .It Li L2_STORE_LOCK_RQSTS.ALL .Pq Event 27H , Umask 0FH RFOs that access cache lines in any state. .It Li L2_L1D_WB_RQSTS.MISS .Pq Event 28H , Umask 01H Not rejected writebacks from L1D to L2 cache lines that missed L2. .It Li L2_L1D_WB_RQSTS.HIT_S .Pq Event 28H , Umask 02H Not rejected writebacks from L1D to L2 cache lines in S state. .It Li L2_L1D_WB_RQSTS.HIT_E .Pq Event 28H , Umask 04H Not rejected writebacks from L1D to L2 cache lines in E state. .It Li L2_L1D_WB_RQSTS.HIT_M .Pq Event 28H , Umask 08H Not rejected writebacks from L1D to L2 cache lines in M state. .It Li L2_L1D_WB_RQSTS.ALL .Pq Event 28H , Umask 0FH Not rejected writebacks from L1D to L2 cache. .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the -thread is not in a halt state. The thread enters -the halt state when it is running the HLT -instruction. The core frequency may change from -time to time due to power or thermal throttling. +thread is not in a halt state. +The thread enters the halt state when it is running the HLT +instruction. +The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 and Edge =1 to count occurrences. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 02H Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 04H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 10H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PER.HW_PF .Pq Event 4CH , Umask 02H Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li HW_PRE_REQ.DL1_MISS .Pq Event 4EH , Umask 02H -Hardware Prefetch requests that miss the L1D -cache. A request is being counted each time -it access the cache & miss it, including if -a block is applicable or if hit the Fill +Hardware Prefetch requests that miss the L1D cache. +A request is being counted each time it access the cache +& miss it, including if a block is applicable or if hit the Fill Buffer for example. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li L1D.ALLOCATED_IN_M .Pq Event 51H , Umask 02H Counts the number of allocations of modified L1D cache lines. .It Li L1D.EVICTION .Pq Event 51H , Umask 04H Counts the number of modified lines evicted from the L1 data cache due to replacement. .It Li L1D.ALL_M_REPLACEMENT .Pq Event 51H , Umask 08H Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement. .It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP .Pq Event 59H , Umask 0CH Increments the number of flags-merge uops in flight each cycle. Set Cmask = 1 to count cycles. .It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW .Pq Event 59H , Umask 0FH Cycles with at least one slow LEA uop allocated. .It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP .Pq Event 59H , Umask 40H Number of Multiply packed/scalar single precision uops allocated. .It Li RESOURCE_STALLS2.ALL_FL_EMPTY .Pq Event 5BH , Umask 0CH Cycles stalled due to free list empty. .It Li RESOURCE_STALLS2.ALL_PRF_CONTROL .Pq Event 5BH , Umask 0FH Cycles stalled due to control structures full for physical registers. .It Li RESOURCE_STALLS2.BOB_FULL .Pq Event 5BH , Umask 40H Cycles Allocator is stalled due Branch Order Buffer. .It Li RESOURCE_STALLS2.OOO_RSRC .Pq Event 5BH , Umask 4FH Cycles stalled due to out of order resources full. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is in ring 0. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read -transactions in SQ to uncore. Set Cmask=1 to count -cycles. +transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H Offcore outstanding RFO store transactions in SQ to -uncore. Set Cmask=1 to count cycles. +uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read -transactions in SQ to uncore. Set Cmask=1 to count -cycles. +transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ -when MS busy by DSB. Set Cmask = 1 to count -cycles MS is busy. Set Cmask=1 and Edge =1 to -count MS activations. +when MS busy by DSB. +Set Cmask = 1 to count cycles MS is busy. +Set Cmask=1 and Edge =1 to count MS activations. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H Increment each cycle # of uops delivered to IDQ -when MS is busy by MITE. Set Cmask = 1 to count -cycles. +when MS is busy by MITE. +Set Cmask = 1 to count cycles. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ -from MS by either DSB or MITE. Set Cmask = 1 to -count cycles. +from MS by either DSB or MITE. +Set Cmask = 1 to count cycles. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and -Victim Cache Misses. Includes UC accesses. +Victim Cache Misses. +Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in all ITLB levels that cause page walks. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 02H Misses in all ITLB levels that cause completed page walks. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 04H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. .It Li BR_INST_EXEC.NONTAKEN_COND .Pq Event 88H , Umask 41H Count conditional near branch instructions that were executed (but not necessarily retired) and not taken. .It Li BR_INST_EXEC.TAKEN_COND .Pq Event 88H , Umask 81H Count conditional near branch instructions that were executed (but not necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP .Pq Event 88H , Umask 82H Count all unconditional near branch instructions excluding calls and indirect branches. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 88H , Umask 84H Count executed indirect near branch instructions that are not calls nor returns. .It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H , Umask 88H Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H , Umask 90H Count unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H , Umask A0H Count indirect near calls, including both register and memory indirect, executed. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). .It Li BR_MISP_EXEC.NONTAKEN_COND .Pq Event 89H , Umask 41H Count conditional near branch instructions mispredicted as nontaken. .It Li BR_MISP_EXEC.TAKEN_COND .Pq Event 89H , Umask 81H Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 89H , Umask 84H Count mispredicted indirect near branch instructions that are not calls nor returns. .It Li BR_MISP_EXEC.RETURN_NEAR .Pq Event 89H , Umask 88H Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H , Umask 90H Count mispredicted unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H , Umask A0H Count mispredicted indirect near calls, including both register and memory indirect, executed. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. .It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1. .It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H , Umask 04H Cycles which a load uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H , Umask 08H Cycles which a store address uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H , Umask 0CH Cycles which a Uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H , Umask 10H Cycles which a load uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H , Umask 20H Cycles which a store address uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H , Umask 30H Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 4. .It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 5. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.LB .Pq Event A2H , Umask 01H Counts the cycles of stall due to lack of load buffers. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H -Cycles stalled due to no store buffers available. (not -including draining form sync). +Cycles stalled due to no store buffers available. +(not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li RESOURCE_STALLS.FCSW .Pq Event A2H , Umask 20H Cycles stalled due to writing the FPU control word. .It Li RESOURCE_STALLS.MXCSR .Pq Event A2H , Umask 40H Cycles stalled due to the MXCSR register rename occurring to close to a previous MXCSR rename. .It Li RESOURCE_STALLS.OTHER .Pq Event A2H , Umask 80H Cycles stalled while execution was stalled due to other resource issues. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H -Cycles with pending L2 miss loads. Set AnyThread -to count per core. +Cycles with pending L2 miss loads. +Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 02H -Cycles with pending L1 cache miss loads.Set -AnyThread to count per core. +Cycles with pending L1 cache miss loads. +Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH .Pq Event A3H , Umask 04H -Cycles of dispatch stalls. Set AnyThread to count per -core. +Cycles of dispatch stalls. +Set AnyThread to count per core. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH , Umask 01H Number of DSB to MITE switches. .It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH , Umask 02H Cycles DSB to MITE switches caused delay. .It Li DSB_FILL.OTHER_CANCEL .Pq Event ACH , Umask 02H Cases of cancelling valid DSB fill not because of exceeding way limit. .It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH , Umask 08H DSB Fill encountered > 3 DSB lines. .It Li DSB_FILL.ALL_CANCEL .Pq Event ACH , Umask 0AH Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_DISPATCHED.THREAD .Pq Event B1H , Umask 01H Counts total number of uops to be dispatched per- -thread each cycle. Set Cmask = 1, INV =1 to count -stall cycles. +thread each cycle. +Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_DISPATCHED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be dispatched per- core each cycle. .It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL .Pq Event B2H , Umask 01H Offcore requests buffer cannot take more entries for this thread core. .It Li AGU_BYPASS_CANCEL.COUNT .Pq Event B6H , Umask 01H Counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another page. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H (Event B7H, Umask 01H) Off-core Response Performance -Monitoring; PMC0 only. Requires programming MSR 01A6H +Monitoring; PMC0 only. +Requires programming MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H (Event BBH, Umask 01H) Off-core Response Performance -Monitoring; PMC3 only. Requires programming MSR 01A7H +Monitoring; PMC3 only. +Requires programming MSR 01A7H .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread-specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES .Pq Event BFH , Umask 05H Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. .It Li OTHER_ASSISTS.ITLB_MISS_RETIRED .Pq Event C1H , Umask 02H Instructions that experienced an ITLB miss. .It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H , Umask 08H Number of assists associated with 256-bit AVX store operations. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 10H Number of transitions from AVX-256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Counts the number of times that a program writes to a code section. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCH .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H , Umask 02H Direct and indirect mispredicted near call instructions retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H , Umask 10H Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H , Umask 20H Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 assists due to output value. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 assists due to input value. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY 1EH .Pq Event CAH , Umask Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Sample loads with specified latency threshold. PMC3 only. .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH , Umask 02H Sample stores and collect precise store operation -via PEBS record. PMC3 only. +via PEBS record. +PMC3 only. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H , Umask 10H Qualify retired memory uops that are loads. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STORES .Pq Event D0H , Umask 02H Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H , Umask -Qualify retired memory uops with STLB miss. Must -combine with umask 01H, 02H, to produce counts. +Qualify retired memory uops with STLB miss. +Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H , Umask -Qualify retired memory uops with lock. Must -combine with umask 01H, 02H, to produce counts. +Qualify retired memory uops with lock. +Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H , Umask -Qualify retired memory uops with line split. Must -combine with umask 01H, 02H, to produce counts. +Qualify retired memory uops with line split. +Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED_ALL .Pq Event D0H , Umask -Qualify any retired memory uops. Must combine -with umask 01H, 02H, to produce counts. +Qualify any retired memory uops. +Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops which data sources were data hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS .Pq Event D1H , Umask 20H Retired load uops which data sources were data missed LLC (excluding unknown data source). .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS .Pq Event D4H , Umask 02H Retired load uops with unknown information as data source in cache serviced the load. .It Li BACLEARS.ANY .Pq Event E6H , Umask 01H Counts the number of times the front end is re- steered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H L2 or LLC HW prefetches that access L2 cache. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. .It Li L2_LINES-IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 01H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 02H Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H , Umask 04H Clean L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H , Umask 08H Dirty L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.DIRTY_ALL .Pq Event F2H , Umask 0AH Dirty L2 cache lines filling the L2. .It Li SQ_MISC.SPLIT_LOCK .Pq Event F4H , Umask 10H Split locks in SQ. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.haswelluc 3 , .Xr pmc.iaf 3 , .Xr pmc.ivybridge 3 , .Xr pmc.ivybridgexeon 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS .An -nosplit The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . The support for the Sandy Bridge Xeon microarchitecture was written by .An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . diff --git a/lib/libpmc/pmc.westmere.3 b/lib/libpmc/pmc.westmere.3 index 36684609f6d5..4f861690584e 100644 --- a/lib/libpmc/pmc.westmere.3 +++ b/lib/libpmc/pmc.westmere.3 @@ -1,1398 +1,1398 @@ .\" Copyright (c) 2010 Fabien Thomas. All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd February 25, 2012 .Dt PMC.WESTMERE 3 .Os .Sh NAME .Nm pmc.westmere .Nd measurement events for .Tn Intel .Tn Westmere family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Westmere" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Westmere PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-033US" .%D December 2009 .%Q "Intel Corporation" .Re .Ss WESTMERE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss WESTMERE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches. .It Li DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO. .It Li DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. WB Counts the number of writeback (modified to exclusive) transactions. .It Li PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li OTHER Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock. .It Li UNCORE_HIT L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping). .It Li OTHER_CORE_HIT_SNP L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean). .It Li OTHER_CORE_HITM L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM). .It Li REMOTE_CACHE_FWD L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted) .It Li REMOTE_DRAM L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM. .It Li LOCAL_DRAM L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM. .It Li NON_DRAM Non-DRAM requests that were serviced by IOH. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Westmere programmable PMCs support the following events: .Bl -tag -width indent .It Li LOAD_BLOCK.OVERLAP_STORE .Pq Event 03H , Umask 02H Loads that partially overlap an earlier store .It Li SB_DRAIN.ANY .Pq Event 04H , Umask 07H All Store buffer stall cycles .It Li MISALIGN_MEMORY.STORE .Pq Event 05H , Umask 02H All store referenced with misaligned address .It Li STORE_BLOCKS.AT_RET .Pq Event 06H , Umask 04H Counts number of loads delayed with at-Retirement block code. The following loads need to be executed at retirement and wait for all senior stores on the same thread to be drained: load splitting across 4K boundary (page split), load accessing uncacheable (UC or USWC) memory, load lock, and load with page table in UC or USWC memory region. .It Li STORE_BLOCKS.L1D_BLOCK .Pq Event 06H , Umask 08H Cacheable loads delayed with L1D block code .It Li PARTIAL_ADDRESS_ALIAS .Pq Event 07H , Umask 01H Counts false dependency due to partial address aliasing .It Li DTLB_LOAD_MISSES.ANY .Pq Event 08H , Umask 01H Counts all load misses that cause a page walk .It Li DTLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H , Umask 02H Counts number of completed page walks due to load miss in the STLB. .It Li DTLB_LOAD_MISSES.WALK_CYCLES .Pq Event 08H , Umask 04H Cycles PMH is busy with a page walk due to a load miss in the STLB. .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 10H Number of cache load STLB hits .It Li DTLB_LOAD_MISSES.PDE_MISS .Pq Event 08H , Umask 20H Number of DTLB cache load misses where the low part of the linear to physical address translation was missed. .It Li MEM_INST_RETIRED.LOADS .Pq Event 0BH , Umask 01H Counts the number of instructions with an architecturally-visible store retired on the architected path. In conjunction with ld_lat facility .It Li MEM_INST_RETIRED.STORES .Pq Event 0BH , Umask 02H Counts the number of instructions with an architecturally-visible store retired on the architected path. In conjunction with ld_lat facility .It Li MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD .Pq Event 0BH , Umask 10H Counts the number of instructions exceeding the latency specified with ld_lat facility. In conjunction with ld_lat facility .It Li MEM_STORE_RETIRED.DTLB_MISS .Pq Event 0CH , Umask 01H The event counts the number of retired stores that missed the DTLB. The DTLB miss is not counted if the store operation causes a fault. Does not counter prefetches. Counts both primary and secondary misses to the TLB .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Counts the number of Uops issued by the Register Allocation Table to the Reservation Station, i.e. the UOPs issued from the front end to the back end. .It Li UOPS_ISSUED.STALLED_CYCLES .Pq Event 0EH , Umask 01H Counts the number of cycles no Uops issued by the Register Allocation Table to the Reservation Station, i.e. the UOPs issued from the front end to the back end. set invert=1, cmask = 1 .It Li UOPS_ISSUED.FUSED .Pq Event 0EH , Umask 02H Counts the number of fused Uops that were issued from the Register Allocation Table to the Reservation Station. .It Li MEM_UNCORE_RETIRED.LOCAL_HITM .Pq Event 0FH , Umask 02H Load instructions retired that HIT modified data in sibling core (Precise Event) .It Li MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT .Pq Event 0FH , Umask 08H Load instructions retired local dram and remote cache HIT data sources (Precise Event) .It Li MEM_UNCORE_RETIRED.LOCAL_DRAM .Pq Event 0FH , Umask 10H Load instructions retired with a data source of local DRAM or locally homed remote cache HITM (Precise Event) .It Li MEM_UNCORE_RETIRED.REMOTE_DRAM .Pq Event 0FH , Umask 20H Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) .It Li MEM_UNCORE_RETIRED.UNCACHEABLE .Pq Event 0FH , Umask 80H Load instructions retired I/O (Precise Event) .It Li FP_COMP_OPS_EXE.X87 .Pq Event 10H , Umask 01H Counts the number of FP Computational Uops Executed. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction. .It Li FP_COMP_OPS_EXE.MMX .Pq Event 10H , Umask 02H Counts number of MMX Uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP .Pq Event 10H , Umask 04H Counts number of SSE and SSE2 FP uops executed. .It Li FP_COMP_OPS_EXE.SSE2_INTEGER .Pq Event 10H , Umask 08H Counts number of SSE2 integer uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_PACKED .Pq Event 10H , Umask 10H Counts number of SSE FP packed uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR .Pq Event 10H , Umask 20H Counts number of SSE FP scalar uops executed. .It Li FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION .Pq Event 10H , Umask 40H Counts number of SSE* FP single precision uops executed. .It Li FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION .Pq Event 10H , Umask 80H Counts number of SSE* FP double precision uops executed. .It Li SIMD_INT_128.PACKED_MPY .Pq Event 12H , Umask 01H Counts number of 128 bit SIMD integer multiply operations. .It Li SIMD_INT_128.PACKED_SHIFT .Pq Event 12H , Umask 02H Counts number of 128 bit SIMD integer shift operations. .It Li SIMD_INT_128.PACK .Pq Event 12H , Umask 04H Counts number of 128 bit SIMD integer pack operations. .It Li SIMD_INT_128.UNPACK .Pq Event 12H , Umask 08H Counts number of 128 bit SIMD integer unpack operations. .It Li SIMD_INT_128.PACKED_LOGICAL .Pq Event 12H , Umask 10H Counts number of 128 bit SIMD integer logical operations. .It Li SIMD_INT_128.PACKED_ARITH .Pq Event 12H , Umask 20H Counts number of 128 bit SIMD integer arithmetic operations. .It Li SIMD_INT_128.SHUFFLE_MOVE .Pq Event 12H , Umask 40H Counts number of 128 bit SIMD integer shuffle and move operations. .It Li LOAD_DISPATCH.RS .Pq Event 13H , Umask 01H Counts number of loads dispatched from the Reservation Station that bypass the Memory Order Buffer. .It Li LOAD_DISPATCH.RS_DELAYED .Pq Event 13H , Umask 02H Counts the number of delayed RS dispatches at the stage latch. If an RS dispatch can not bypass to LB, it has another chance to dispatch from the one-cycle delayed staging latch before it is written into the LB. .It Li LOAD_DISPATCH.MOB .Pq Event 13H , Umask 04H Counts the number of loads dispatched from the Reservation Station to the Memory Order Buffer. .It Li LOAD_DISPATCH.ANY .Pq Event 13H , Umask 07H Counts all loads dispatched from the Reservation Station. .It Li ARITH.CYCLES_DIV_BUSY .Pq Event 14H , Umask 01H Counts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Set 'edge =1, invert=1, cmask=1' to count the number of divides. Count may be incorrect When SMT is on .It Li ARITH.MUL .Pq Event 14H , Umask 02H Counts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect When SMT is on .It Li INST_QUEUE_WRITES .Pq Event 17H , Umask 01H Counts the number of instructions written into the instruction queue every cycle. .It Li INST_DECODED.DEC0 .Pq Event 18H , Umask 01H Counts number of instructions that require decoder 0 to be decoded. Usually, this means that the instruction maps to more than 1 uop .It Li TWO_UOP_INSTS_DECODED .Pq Event 19H , Umask 01H An instruction that generates two uops was decoded .It Li INST_QUEUE_WRITE_CYCLES .Pq Event 1EH , Umask 01H This event counts the number of cycles during which instructions are written to the instruction queue. Dividing this counter by the number of instructions written to the instruction queue (INST_QUEUE_WRITES) yields the average number of instructions decoded each cycle. If this number is less than four and the pipe stalls, this indicates that the decoder is failing to decode enough instructions per cycle to sustain the 4-wide pipeline. If SSE* instructions that are 6 bytes or longer arrive one after another, then front end throughput may limit execution speed. In such case, .It Li LSD_OVERFLOW .Pq Event 20H , Umask 01H Number of loops that can not stream from the instruction queue. .It Li L2_RQSTS.LD_HIT .Pq Event 24H , Umask 01H Counts number of loads that hit the L2 cache. L2 loads include both L1D demand misses as well as L1D prefetches. L2 loads can be rejected for various reasons. Only non rejected loads are counted. .It Li L2_RQSTS.LD_MISS .Pq Event 24H , Umask 02H Counts the number of loads that miss the L2 cache. L2 loads include both L1D demand misses as well as L1D prefetches. .It Li L2_RQSTS.LOADS .Pq Event 24H , Umask 03H Counts all L2 load requests. L2 loads include both L1D demand misses as well as L1D prefetches. .It Li L2_RQSTS.RFO_HIT .Pq Event 24H , Umask 04H Counts the number of store RFO requests that hit the L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. Count includes WC memory requests, where the data is not fetched but the permission to write the line is required. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H Counts the number of store RFO requests that miss the L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. .It Li L2_RQSTS.RFOS .Pq Event 24H , Umask 0CH Counts all L2 store RFO requests. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. .It Li L2_RQSTS.IFETCH_HIT .Pq Event 24H , Umask 10H Counts number of instruction fetches that hit the L2 cache. L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.IFETCH_MISS .Pq Event 24H , Umask 20H Counts number of instruction fetches that miss the L2 cache. L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.IFETCHES .Pq Event 24H , Umask 30H Counts all instruction fetches. L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.PREFETCH_HIT .Pq Event 24H , Umask 40H Counts L2 prefetch hits for both code and data. .It Li L2_RQSTS.PREFETCH_MISS .Pq Event 24H , Umask 80H Counts L2 prefetch misses for both code and data. .It Li L2_RQSTS.PREFETCHES .Pq Event 24H , Umask C0H Counts all L2 prefetches for both code and data. .It Li L2_RQSTS.MISS .Pq Event 24H , Umask AAH Counts all L2 misses for both code and data. .It Li L2_RQSTS.REFERENCES .Pq Event 24H , Umask FFH Counts all L2 requests for both code and data. .It Li L2_DATA_RQSTS.DEMAND.I_STATE .Pq Event 26H , Umask 01H Counts number of L2 data demand loads where the cache line to be loaded is in the I (invalid) state, i.e. a cache miss. L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.S_STATE .Pq Event 26H , Umask 02H Counts number of L2 data demand loads where the cache line to be loaded is in the S (shared) state. L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.E_STATE .Pq Event 26H , Umask 04H Counts number of L2 data demand loads where the cache line to be loaded is in the E (exclusive) state. L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.M_STATE .Pq Event 26H , Umask 08H Counts number of L2 data demand loads where the cache line to be loaded is in the M (modified) state. L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.MESI .Pq Event 26H , Umask 0FH Counts all L2 data demand requests. L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.PREFETCH.I_STATE .Pq Event 26H , Umask 10H Counts number of L2 prefetch data loads where the cache line to be loaded is in the I (invalid) state, i.e. a cache miss. .It Li L2_DATA_RQSTS.PREFETCH.S_STATE .Pq Event 26H , Umask 20H Counts number of L2 prefetch data loads where the cache line to be loaded is in the S (shared) state. A prefetch RFO will miss on an S state line, while a prefetch read will hit on an S state line. .It Li L2_DATA_RQSTS.PREFETCH.E_STATE .Pq Event 26H , Umask 40H Counts number of L2 prefetch data loads where the cache line to be loaded is in the E (exclusive) state. .It Li L2_DATA_RQSTS.PREFETCH.M_STATE .Pq Event 26H , Umask 80H Counts number of L2 prefetch data loads where the cache line to be loaded is in the M (modified) state. .It Li L2_DATA_RQSTS.PREFETCH.MESI .Pq Event 26H , Umask F0H Counts all L2 prefetch requests. .It Li L2_DATA_RQSTS.ANY .Pq Event 26H , Umask FFH Counts all L2 data requests. .It Li L2_WRITE.RFO.I_STATE .Pq Event 27H , Umask 01H Counts number of L2 demand store RFO requests where the cache line to be loaded is in the I (invalid) state, i.e, a cache miss. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.S_STATE .Pq Event 27H , Umask 02H Counts number of L2 store RFO requests where the cache line to be loaded is in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request. .It Li L2_WRITE.RFO.M_STATE .Pq Event 27H , Umask 08H Counts number of L2 store RFO requests where the cache line to be loaded is in the M (modified) state. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request. .It Li L2_WRITE.RFO.HIT .Pq Event 27H , Umask 0EH Counts number of L2 store RFO requests where the cache line to be loaded is in either the S, E or M states. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.MESI .Pq Event 27H , Umask 0FH Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request. .It Li L2_WRITE.LOCK.I_STATE .Pq Event 27H , Umask 10H Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the I (invalid) state, i.e. a cache miss. .It Li L2_WRITE.LOCK.S_STATE .Pq Event 27H , Umask 20H Counts number of L2 lock RFO requests where the cache line to be loaded is in the S (shared) state. .It Li L2_WRITE.LOCK.E_STATE .Pq Event 27H , Umask 40H Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the E (exclusive) state. .It Li L2_WRITE.LOCK.M_STATE .Pq Event 27H , Umask 80H Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the M (modified) state. .It Li L2_WRITE.LOCK.HIT .Pq Event 27H , Umask E0H Counts number of L2 demand lock RFO requests where the cache line to be loaded is in either the S, E, or M state. .It Li L2_WRITE.LOCK.MESI .Pq Event 27H , Umask F0H Counts all L2 demand lock RFO requests. .It Li L1D_WB_L2.I_STATE .Pq Event 28H , Umask 01H Counts number of L1 writebacks to the L2 where the cache line to be written is in the I (invalid) state, i.e. a cache miss. .It Li L1D_WB_L2.S_STATE .Pq Event 28H , Umask 02H Counts number of L1 writebacks to the L2 where the cache line to be written is in the S state. .It Li L1D_WB_L2.E_STATE .Pq Event 28H , Umask 04H Counts number of L1 writebacks to the L2 where the cache line to be written is in the E (exclusive) state. .It Li L1D_WB_L2.M_STATE .Pq Event 28H , Umask 08H Counts number of L1 writebacks to the L2 where the cache line to be written is in the M (modified) state. .It Li L1D_WB_L2.MESI .Pq Event 28H , Umask 0FH Counts all L1 writebacks to the L2. .It Li L3_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 02H Counts uncore Last Level Cache references. Because cache hierarchy, cache sizes and other implementation-specific characteristics; value comparison to estimate performance differences is not recommended. See Table A-1. .It Li L3_LAT_CACHE.MISS .Pq Event 2EH , Umask 01H Counts uncore Last Level Cache misses. Because cache hierarchy, cache sizes and other implementation-specific characteristics; value comparison to estimate performance differences is not recommended. See Table A-1. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. see Table A-1 .It Li CPU_CLK_UNHALTED.REF_P .Pq Event 3CH , Umask 01H Increments at the frequency of TSC when not halted. see Table A-1 .It Li DTLB_MISSES.ANY .Pq Event 49H , Umask 01H Counts the number of misses in the STLB which causes a page walk. .It Li DTLB_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 02H Counts number of misses in the STLB which resulted in a completed page walk. .It Li DTLB_MISSES.WALK_CYCLES .Pq Event 49H , Umask 04H Counts cycles of page walk due to misses in the STLB. .It Li DTLB_MISSES.STLB_HIT .Pq Event 49H , Umask 10H Counts the number of DTLB first level misses that hit in the second level TLB. This event is only relevant if the core contains multiple DTLB levels. .It Li DTLB_MISSES.LARGE_WALK_COMPLETED .Pq Event 49H , Umask 80H Counts number of completed large page walks due to misses in the STLB. .It Li LOAD_HIT_PRE .Pq Event 4CH , Umask 01H Counts load operations sent to the L1 data cache while a previous SSE prefetch instruction to the same cache line has started prefetching but has not yet finished. .It Li L1D_PREFETCH.REQUESTS .Pq Event 4EH , Umask 01H Counts number of hardware prefetch requests dispatched out of the prefetch FIFO. .It Li L1D_PREFETCH.MISS .Pq Event 4EH , Umask 02H Counts number of hardware prefetch requests that miss the L1D. There are two prefetchers in the L1D. A streamer, which predicts lines sequentially after this one should be fetched, and the IP prefetcher that remembers access patterns for the current instruction. The streamer prefetcher stops on an L1D hit, while the IP prefetcher does not. .It Li L1D_PREFETCH.TRIGGERS .Pq Event 4EH , Umask 04H Counts number of prefetch requests triggered by the Finite State Machine and pushed into the prefetch FIFO. Some of the prefetch requests are dropped due to overwrites or competition between the IP index prefetcher and streamer prefetcher. The prefetch FIFO contains 4 entries. .It Li EPT.WALK_CYCLES .Pq Event 4FH , Umask 10H Counts Extended Page walk cycles. .It Li L1D.REPL .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. Counter 0, 1 only. .It Li L1D.M_REPL .Pq Event 51H , Umask 02H Counts the number of modified lines brought into the L1 data cache. Counter 0, 1 only. .It Li L1D.M_EVICT .Pq Event 51H , Umask 04H Counts the number of modified lines evicted from the L1 data cache due to replacement. Counter 0, 1 only. .It Li L1D.M_SNOOP_EVICT .Pq Event 51H , Umask 08H Counts the number of modified lines evicted from the L1 data cache due to snoop HITM intervention. Counter 0, 1 only .It Li L1D_CACHE_PREFETCH_LOCK_FB_HIT .Pq Event 52H , Umask 01H Counts the number of cacheable load lock speculated instructions accepted into the fill buffer. .It Li L1D_CACHE_LOCK_FB_HIT .Pq Event 53H , Umask 01H Counts the number of cacheable load lock speculated or retired instructions accepted into the fill buffer. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA .Pq Event 60H , Umask 01H Counts weighted cycles of offcore demand data read requests. Does not include L2 prefetch requests. Counter 0. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE .Pq Event 60H , Umask 02H Counts weighted cycles of offcore demand code read requests. Does not include L2 prefetch requests. Counter 0. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO .Pq Event 60H , Umask 04H Counts weighted cycles of offcore demand RFO requests. Does not include L2 prefetch requests. Counter 0. .It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ .Pq Event 60H , Umask 08H Counts weighted cycles of offcore read requests of any kind. Include L2 prefetch requests. Counter 0. .It Li CACHE_LOCK_CYCLES.L1D_L2 .Pq Event 63H , Umask 01H Cycle count during which the L1D and L2 are locked. A lock is asserted when there is a locked memory access, due to uncacheable memory, a locked operation that spans two cache lines, or a page walk from an uncacheable page table. Counter 0, 1 only. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such accesses. .It Li CACHE_LOCK_CYCLES.L1D .Pq Event 63H , Umask 02H Counts the number of cycles that cacheline in the L1 data cache unit is locked. Counter 0, 1 only. .It Li IO_TRANSACTIONS .Pq Event 6CH , Umask 01H Counts the number of completed I/O transactions. .It Li L1I.HITS .Pq Event 80H , Umask 01H Counts all instruction fetches that hit the L1 instruction cache. .It Li L1I.MISSES .Pq Event 80H , Umask 02H Counts all instruction fetches that miss the L1I cache. This includes instruction cache misses, streaming buffer misses, victim cache misses and uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding. .It Li L1I.READS .Pq Event 80H , Umask 03H Counts all instruction fetches, including uncacheable fetches that bypass the L1I. .It Li L1I.CYCLES_STALLED .Pq Event 80H , Umask 04H Cycle counts for which an instruction fetch stalls due to a L1I cache miss, ITLB miss or ITLB fault. .It Li LARGE_ITLB.HIT .Pq Event 82H , Umask 01H Counts number of large ITLB hits. .It Li ITLB_MISSES.ANY .Pq Event 85H , Umask 01H Counts the number of misses in all levels of the ITLB which causes a page walk. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 02H Counts number of misses in all levels of the ITLB which resulted in a completed page walk. .It Li ITLB_MISSES.WALK_CYCLES .Pq Event 85H , Umask 04H Counts ITLB miss page walk cycles. .It Li ITLB_MISSES.LARGE_WALK_COMPLETED .Pq Event 85H , Umask 80H Counts number of completed large page walks due to misses in the STLB. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Cycles Instruction Length Decoder stalls due to length changing prefixes: 66, 67 or REX.W (for EM64T) instructions which change the length of the decoded instruction. .It Li ILD_STALL.MRU .Pq Event 87H , Umask 02H Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) Most Recently Used (MRU) bypass. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to a full instruction queue. .It Li ILD_STALL.REGEN .Pq Event 87H , Umask 08H Counts the number of regen stalls. .It Li ILD_STALL.ANY .Pq Event 87H , Umask 0FH Counts any cycles the Instruction Length Decoder is stalled. .It Li BR_INST_EXEC.COND .Pq Event 88H , Umask 01H Counts the number of conditional near branch instructions executed, but not necessarily retired. .It Li BR_INST_EXEC.DIRECT .Pq Event 88H , Umask 02H Counts all unconditional near branch instructions excluding calls and indirect branches. .It Li BR_INST_EXEC.INDIRECT_NON_CALL .Pq Event 88H , Umask 04H Counts the number of executed indirect near branch instructions that are not calls. .It Li BR_INST_EXEC.NON_CALLS .Pq Event 88H , Umask 07H Counts all non call near branch instructions executed, but not necessarily retired. .It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H , Umask 08H Counts indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H , Umask 10H Counts unconditional near call branch instructions, excluding non call branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H , Umask 20H Counts indirect near calls, including both register and memory indirect, executed. .It Li BR_INST_EXEC.NEAR_CALLS .Pq Event 88H , Umask 30H Counts all near call branches executed, but not necessarily retired. .It Li BR_INST_EXEC.TAKEN .Pq Event 88H , Umask 40H Counts taken near branches executed, but not necessarily retired. .It Li BR_INST_EXEC.ANY .Pq Event 88H , Umask 7FH Counts all near executed branches (not necessarily retired). This includes only instructions and not micro-op branches. Frequent branching is not necessarily a major performance issue. However frequent branch mispredictions may be a problem. .It Li BR_MISP_EXEC.COND .Pq Event 89H , Umask 01H Counts the number of mispredicted conditional near branch instructions executed, but not necessarily retired. .It Li BR_MISP_EXEC.DIRECT .Pq Event 89H , Umask 02H Counts mispredicted macro unconditional near branch instructions, excluding calls and indirect branches (should always be 0). .It Li BR_MISP_EXEC.INDIRECT_NON_CALL .Pq Event 89H , Umask 04H Counts the number of executed mispredicted indirect near branch instructions that are not calls. .It Li BR_MISP_EXEC.NON_CALLS .Pq Event 89H , Umask 07H Counts mispredicted non call near branches executed, but not necessarily retired. .It Li BR_MISP_EXEC.RETURN_NEAR .Pq Event 89H , Umask 08H Counts mispredicted indirect branches that have a rear return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H , Umask 10H Counts mispredicted non-indirect near calls executed, (should always be 0). .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H , Umask 20H Counts mispredicted indirect near calls executed, including both register and memory indirect. .It Li BR_MISP_EXEC.NEAR_CALLS .Pq Event 89H , Umask 30H Counts all mispredicted near call branches executed, but not necessarily retired. .It Li BR_MISP_EXEC.TAKEN .Pq Event 89H , Umask 40H Counts executed mispredicted near branches that are taken, but not necessarily retired. .It Li BR_MISP_EXEC.ANY .Pq Event 89H , Umask 7FH Counts the number of mispredicted near branch instructions that were executed, but not necessarily retired. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Counts the number of Allocator resource related stalls. Includes register renaming buffer entries, memory buffer entries. In addition to resource related stalls, this event counts some other events. Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations. Does not include stalls due to SuperQ (off core) queue full, too many cache misses, etc. .It Li RESOURCE_STALLS.LOAD .Pq Event A2H , Umask 02H Counts the cycles of stall due to lack of load buffer for load operation. .It Li RESOURCE_STALLS.RS_FULL .Pq Event A2H , Umask 04H This event counts the number of cycles when the number of instructions in the pipeline waiting for execution reaches the limit the processor can handle. A high count of this event indicates that there are long latency operations in the pipe (possibly load and store operations that miss the L2 cache, or instructions dependent upon instructions further down the pipeline that have yet to retire. When RS is full, new instructions can not enter the reservation station and start execution. .It Li RESOURCE_STALLS.STORE .Pq Event A2H , Umask 08H This event counts the number of cycles that a resource related stall will occur due to the number of store instructions reaching the limit of the pipeline, (i.e. all store buffers are used). The stall ends when a store instruction commits its data to the cache or memory. .It Li RESOURCE_STALLS.ROB_FULL .Pq Event A2H , Umask 10H Counts the cycles of stall due to re- order buffer full. .It Li RESOURCE_STALLS.FPCW .Pq Event A2H , Umask 20H Counts the number of cycles while execution was stalled due to writing the floating-point unit (FPU) control word. .It Li RESOURCE_STALLS.MXCSR .Pq Event A2H , Umask 40H Stalls due to the MXCSR register rename occurring to close to a previous MXCSR rename. The MXCSR provides control and status for the MMX registers. .It Li RESOURCE_STALLS.OTHER .Pq Event A2H , Umask 80H Counts the number of cycles while execution was stalled due to other resource issues. .It Li MACRO_INSTS.FUSIONS_DECODED .Pq Event A6H , Umask 01H Counts the number of instructions decoded that are macro-fused but not necessarily executed or retired. .It Li BACLEAR_FORCE_IQ .Pq Event A7H , Umask 01H Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ is also responsible for providing conditional branch prediction direction based on a static scheme and dynamic data provided by the L2 Branch Prediction Unit. If the conditional branch target is not found in the Target Array and the IQ predicts that the branch is taken, then the IQ will force the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline. .It Li LSD.UOPS .Pq Event A8H , Umask 01H Counts the number of micro-ops delivered by loop stream detector Use cmask=1 and invert to count cycles .It Li ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes .It Li OFFCORE_REQUESTS.DEMAND.READ_DATA .Pq Event B0H , Umask 01H Counts number of offcore demand data read requests. Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.DEMAND.READ_CODE .Pq Event B0H , Umask 02H Counts number of offcore demand code read requests. Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.DEMAND.RFO .Pq Event B0H , Umask 04H Counts number of offcore demand RFO requests. Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.ANY.READ .Pq Event B0H , Umask 08H Counts number of offcore read requests. Includes L2 prefetch requests. .It Li OFFCORE_REQUESTS.ANY.RFO .Pq Event 80H , Umask 10H Counts number of offcore RFO requests. Includes L2 prefetch requests. .It Li OFFCORE_REQUESTS.L1D_WRITEBACK .Pq Event B0H , Umask 40H Counts number of L1D writebacks to the uncore. .It Li OFFCORE_REQUESTS.ANY .Pq Event B0H , Umask 80H Counts all offcore requests. .It Li UOPS_EXECUTED.PORT0 .Pq Event B1H , Umask 01H Counts number of Uops executed that were issued on port 0. Port 0 handles integer arithmetic, SIMD and FP add Uops. .It Li UOPS_EXECUTED.PORT1 .Pq Event B1H , Umask 02H Counts number of Uops executed that were issued on port 1. Port 1 handles integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops. .It Li UOPS_EXECUTED.PORT2_CORE .Pq Event B1H , Umask 04H Counts number of Uops executed that were issued on port 2. Port 2 handles the load Uops. This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.PORT3_CORE .Pq Event B1H , Umask 08H Counts number of Uops executed that were issued on port 3. Port 3 handles store Uops. This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.PORT4_CORE .Pq Event B1H , Umask 10H Counts number of Uops executed that where issued on port 4. Port 4 handles the value to be stored for the store Uops issued on port 3. This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 .Pq Event B1H , Umask 1FH Counts number of cycles there are one or more uops being executed and were issued on ports 0-4. This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.PORT5 .Pq Event B1H , Umask 20H Counts number of Uops executed that where issued on port 5. .It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES .Pq Event B1H , Umask 3FH Counts number of cycles there are one or more uops being executed on any ports. This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.PORT015 .Pq Event B1H , Umask 40H Counts number of Uops executed that where issued on port 0, 1, or 5. Use cmask=1, invert=1 to count stall cycles. .It Li UOPS_EXECUTED.PORT234 .Pq Event B1H , Umask 80H Counts number of Uops executed that where issued on port 2, 3, or 4. .It Li OFFCORE_REQUESTS_SQ_FULL .Pq Event B2H , Umask 01H Counts number of cycles the SQ is full to handle off-core requests. .It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA .Pq Event B3H , Umask 01H Counts weighted cycles of snoopq requests for data. Counter 0 only Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE .Pq Event B3H , Umask 02H Counts weighted cycles of snoopq invalidate requests. Counter 0 only. Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE .Pq Event B3H , Umask 04H Counts weighted cycles of snoopq requests for code. Counter 0 only. Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS.CODE .Pq Event B4H , Umask 01H Counts the number of snoop code requests. .It Li SNOOPQ_REQUESTS.DATA .Pq Event B4H , Umask 02H Counts the number of snoop data requests. .It Li SNOOPQ_REQUESTS.INVALIDATE .Pq Event B4H , Umask 04H Counts the number of snoop invalidate requests .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H see Section 30.6.1.3, Off-core Response Performance Monitoring in the Processor Core. Requires programming MSR 01A6H. .It Li SNOOP_RESPONSE.HIT .Pq Event B8H , Umask 01H Counts HIT snoop response sent by this thread in response to a snoop request. .It Li SNOOP_RESPONSE.HITE .Pq Event B8H , Umask 02H Counts HIT E snoop response sent by this thread in response to a snoop request. .It Li SNOOP_RESPONSE.HITM .Pq Event B8H , Umask 04H Counts HIT M snoop response sent by this thread in response to a snoop request. .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H see Section 30.6.1.3, Off-core Response Performance Monitoring in the Processor Core. Use MSR 01A7H. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 01H See Table A-1 Notes: INST_RETIRED.ANY is counted by a designated fixed counter. INST_RETIRED.ANY_P is counted by a programmable counter and is an architectural performance event. Event is supported if CPUID.A.EBX[1] = 0. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions. .It Li INST_RETIRED.X87 .Pq Event C0H , Umask 02H Counts the number of floating point computational operations retired floating point computational operations executed by the assist handler and sub-operations of complex floating point instructions like transcendental instructions. .It Li INST_RETIRED.MMX .Pq Event C0H , Umask 04H Counts the number of retired: MMX instructions. .It Li UOPS_RETIRED.ANY .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2, others=1; maximum count of 8 per cycle). Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. Use cmask=1 and invert to count active cycles or stalled cycles .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle .It Li UOPS_RETIRED.MACRO_FUSED .Pq Event C2H , Umask 04H Counts number of macro-fused uops retired. .It Li MACHINE_CLEARS.CYCLES .Pq Event C3H , Umask 01H Counts the cycles machine clear is asserted. .It Li MACHINE_CLEARS.MEM_ORDER .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Counts the number of times that a program writes to a code section. Self-modifying code causes a sever penalty in all Intel 64 and IA-32 processors. The modified cache line is written back to the L2 and L3caches. .It Li BR_INST_RETIRED.ANY_P .Pq Event C4H , Umask 00H See Table A-1. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Counts the number of direct & indirect near unconditional calls retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_MISP_RETIRED.ANY_P .Pq Event C5H , Umask 00H See Table A-1. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Counts mispredicted conditional retired calls. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H , Umask 02H Counts mispredicted direct & indirect near unconditional retired calls. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 04H Counts all mispredicted retired calls. .It Li SSEX_UOPS_RETIRED.PACKED_SINGLE .Pq Event C7H , Umask 01H Counts SIMD packed single-precision floating point Uops retired. .It Li SSEX_UOPS_RETIRED.SCALAR_SINGLE .Pq Event C7H , Umask 02H Counts SIMD calar single-precision floating point Uops retired. .It Li SSEX_UOPS_RETIRED.PACKED_DOUBLE .Pq Event C7H , Umask 04H Counts SIMD packed double- precision floating point Uops retired. .It Li SSEX_UOPS_RETIRED.SCALAR_DOUBLE .Pq Event C7H , Umask 08H Counts SIMD scalar double-precision floating point Uops retired. .It Li SSEX_UOPS_RETIRED.VECTOR_INTEGER .Pq Event C7H , Umask 10H Counts 128-bit SIMD vector integer Uops retired. .It Li ITLB_MISS_RETIRED .Pq Event C8H , Umask 20H Counts the number of retired instructions that missed the ITLB when the instruction was fetched. .It Li MEM_LOAD_RETIRED.L1D_HIT .Pq Event CBH , Umask 01H Counts number of retired loads that hit the L1 data cache. .It Li MEM_LOAD_RETIRED.L2_HIT .Pq Event CBH , Umask 02H Counts number of retired loads that hit the L2 data cache. .It Li MEM_LOAD_RETIRED.L3_UNSHARED_HIT .Pq Event CBH , Umask 04H Counts number of retired loads that hit their own, unshared lines in the L3 cache. .It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM .Pq Event CBH , Umask 08H Counts number of retired loads that hit in a sibling core's L2 (on die core). Since the L3 is inclusive of all cores on the package, this is an L3 hit. This counts both clean or modified hits. .It Li MEM_LOAD_RETIRED.L3_MISS .Pq Event CBH , Umask 10H Counts number of retired loads that miss the L3 cache. The load was satisfied by a remote socket, local memory or an IOH. .It Li MEM_LOAD_RETIRED.HIT_LFB .Pq Event CBH , Umask 40H Counts number of retired loads that miss the L1D and the address is located in an allocated line fill buffer and will soon be committed to cache. This is counting secondary L1D misses. .It Li MEM_LOAD_RETIRED.DTLB_MISS .Pq Event CBH , Umask 80H Counts the number of retired loads that missed the DTLB. The DTLB miss is not counted if the load operation causes a fault. This event counts loads from cacheable memory only. The event does not count loads by software prefetches. Counts both primary and secondary misses to the TLB. .It Li FP_MMX_TRANS.TO_FP .Pq Event CCH , Umask 01H Counts the first floating-point instruction following any MMX instruction. You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. .It Li FP_MMX_TRANS.TO_MMX .Pq Event CCH , Umask 02H Counts the first MMX instruction following a floating-point instruction. You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. .It Li FP_MMX_TRANS.ANY .Pq Event CCH , Umask 03H Counts all transitions from floating point to MMX instructions and from MMX instructions to floating point instructions. You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. .It Li MACRO_INSTS.DECODED .Pq Event D0H , Umask 01H Counts the number of instructions decoded, (but not necessarily executed or retired). .It Li UOPS_DECODED.STALL_CYCLES .Pq Event D1H , Umask 01H Counts the cycles of decoder stalls. .It Li UOPS_DECODED.MS .Pq Event D1H , Umask 02H Counts the number of Uops decoded by the Microcode Sequencer, MS. The MS delivers uops when the instruction is more than 4 uops long or a microcode assist is occurring. .It Li UOPS_DECODED.ESP_FOLDING .Pq Event D1H , Umask 04H Counts number of stack pointer (ESP) instructions decoded: push , pop , call -, ret, etc. ESP instructions do not generate a Uop to increment or decrement -ESP. +, ret, etc. +ESP instructions do not generate a Uop to increment or decrement ESP. Instead, they update an ESP_Offset register that keeps track of the delta to the current value of the ESP register. .It Li UOPS_DECODED.ESP_SYNC .Pq Event D1H , Umask 08H Counts number of stack pointer (ESP) sync operations where an ESP instruction is corrected by adding the ESP offset register to the current value of the ESP register. .It Li RAT_STALLS.FLAGS .Pq Event D2H , Umask 01H Counts the number of cycles during which execution stalled due to several reasons, one of which is a partial flag register stall. A partial register stall may occur when two conditions are met: 1) an instruction modifies some, but not all, of the flags in the flag register and 2) the next instruction, which depends on flags, depends on flags that were not modified by this instruction. .It Li RAT_STALLS.REGISTERS .Pq Event D2H , Umask 02H This event counts the number of cycles instruction execution latency became longer than the defined latency because the instruction used a register that was partially written by previous instruction. .It Li RAT_STALLS.ROB_READ_PORT .Pq Event D2H , Umask 04H Counts the number of cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the out-of-order pipeline. Note that, at this stage in the pipeline, additional stalls may occur at the same cycle and prevent the stalled micro-ops from entering the pipe. In such a case, micro-ops retry entering the execution pipe in the next cycle and the ROB-read port stall is counted again. .It Li RAT_STALLS.SCOREBOARD .Pq Event D2H , Umask 08H Counts the cycles where we stall due to microarchitecturally required serialization. Microcode scoreboarding stalls. .It Li RAT_STALLS.ANY .Pq Event D2H , Umask 0FH Counts all Register Allocation Table stall cycles due to: Cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the execution pipe. Cycles when partial register stalls occurred Cycles when flag stalls occurred Cycles floating-point unit (FPU) status word stalls occurred. To count each of these conditions separately use the events: RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and RAT_STALLS.FPSW. .It Li SEG_RENAME_STALLS .Pq Event D4H , Umask 01H Counts the number of stall cycles due to the lack of renaming resources for the ES, DS, FS, and GS segment registers. If a segment is renamed but not retired and a second update to the same segment occurs, a stall occurs in the front- end of the pipeline until the renamed segment retires. .It Li ES_REG_RENAMES .Pq Event D5H , Umask 01H Counts the number of times the ES segment register is renamed. .It Li UOP_UNFUSION .Pq Event DBH , Umask 01H Counts unfusion events due to floating point exception to a fused uop. .It Li BR_INST_DECODED .Pq Event E0H , Umask 01H Counts the number of branch instructions decoded. .It Li BPU_MISSED_CALL_RET .Pq Event E5H , Umask 01H Counts number of times the Branch Prediction Unit missed predicting a call or return branch. .It Li BACLEAR.CLEAR .Pq Event E6H , Umask 01H Counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. This can occur if the code has many branches such that they cannot be consumed by the BPU. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline. The effect on total execution time depends on the surrounding code. .It Li BACLEAR.BAD_TARGET .Pq Event E6H , Umask 02H Counts number of Branch Address Calculator clears (BACLEAR) asserted due to conditional branch instructions in which there was a target hit but the direction was wrong. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline. .It Li BPU_CLEARS.EARLY .Pq Event E8H , Umask 01H Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken branch after incorrectly assuming that it was not taken. The BPU clear leads to 2 cycle bubble in the Front End. .It Li BPU_CLEARS.LATE .Pq Event E8H , Umask 02H Counts late Branch Prediction Unit clears due to Most Recently Used conflicts. The PBU clear leads to a 3 cycle bubble in the Front End. .It Li THREAD_ACTIVE .Pq Event ECH , Umask 01H Counts cycles threads are active. .It Li L2_TRANSACTIONS.LOAD .Pq Event F0H , Umask 01H Counts L2 load operations due to HW prefetch or demand loads. .It Li L2_TRANSACTIONS.RFO .Pq Event F0H , Umask 02H Counts L2 RFO operations due to HW prefetch or demand RFOs. .It Li L2_TRANSACTIONS.IFETCH .Pq Event F0H , Umask 04H Counts L2 instruction fetch operations due to HW prefetch or demand ifetch. .It Li L2_TRANSACTIONS.PREFETCH .Pq Event F0H , Umask 08H Counts L2 prefetch operations. .It Li L2_TRANSACTIONS.L1D_WB .Pq Event F0H , Umask 10H Counts L1D writeback operations to the L2. .It Li L2_TRANSACTIONS.FILL .Pq Event F0H , Umask 20H Counts L2 cache line fill operations due to load, RFO, L1D writeback or prefetch. .It Li L2_TRANSACTIONS.WB .Pq Event F0H , Umask 40H Counts L2 writeback operations to the L3. .It Li L2_TRANSACTIONS.ANY .Pq Event F0H , Umask 80H Counts all L2 cache operations. .It Li L2_LINES_IN.S_STATE .Pq Event F1H , Umask 02H Counts the number of cache lines allocated in the L2 cache in the S (shared) state. .It Li L2_LINES_IN.E_STATE .Pq Event F1H , Umask 04H Counts the number of cache lines allocated in the L2 cache in the E (exclusive) state. .It Li L2_LINES_IN.ANY .Pq Event F1H , Umask 07H Counts the number of cache lines allocated in the L2 cache. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 01H Counts L2 clean cache lines evicted by a demand request. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 02H Counts L2 dirty (modified) cache lines evicted by a demand request. .It Li L2_LINES_OUT.PREFETCH_CLEAN .Pq Event F2H , Umask 04H Counts L2 clean cache line evicted by a prefetch request. .It Li L2_LINES_OUT.PREFETCH_DIRTY .Pq Event F2H , Umask 08H Counts L2 modified cache line evicted by a prefetch request. .It Li L2_LINES_OUT.ANY .Pq Event F2H , Umask 0FH Counts all L2 cache lines evicted for any reason. .It Li SQ_MISC.LRU_HINTS .Pq Event F4H , Umask 04H Counts number of Super Queue LRU hints sent to L3. .It Li SQ_MISC.SPLIT_LOCK .Pq Event F4H , Umask 10H Counts the number of SQ lock splits across a cache line. .It Li SQ_FULL_STALL_CYCLES .Pq Event F6H , Umask 01H Counts cycles the Super Queue is full. Neither of the threads on this core will be able to access the uncore. .It Li FP_ASSIST.ALL .Pq Event F7H , Umask 01H Counts the number of floating point operations executed that required micro-code assist intervention. Assists are required in the following cases: SSE instructions, (Denormal input when the DAZ flag is off or Underflow result when the FTZ flag is off): x87 instructions, (NaN or denormal are loaded to a register or used as input from memory, Division by 0 or Underflow output). .It Li FP_ASSIST.OUTPUT .Pq Event F7H , Umask 02H Counts number of floating point micro-code assist when the output value (destination register) is invalid. .It Li FP_ASSIST.INPUT .Pq Event F7H , Umask 04H Counts number of floating point micro-code assist when the input value (one of the source operands to an FP instruction) is invalid. .It Li SIMD_INT_64.PACKED_MPY .Pq Event FDH , Umask 01H Counts number of SID integer 64 bit packed multiply operations. .It Li SIMD_INT_64.PACKED_SHIFT .Pq Event FDH , Umask 02H Counts number of SID integer 64 bit packed shift operations. .It Li SIMD_INT_64.PACK .Pq Event FDH , Umask 04H Counts number of SID integer 64 bit pack operations. .It Li SIMD_INT_64.UNPACK .Pq Event FDH , Umask 08H Counts number of SID integer 64 bit unpack operations. .It Li SIMD_INT_64.PACKED_LOGICAL .Pq Event FDH , Umask 10H Counts number of SID integer 64 bit logical operations. .It Li SIMD_INT_64.PACKED_ARITH .Pq Event FDH , Umask 20H Counts number of SID integer 64 bit arithmetic operations. .It Li SIMD_INT_64.SHUFFLE_MOVE .Pq Event FDH , Umask 40H Counts number of SID integer 64 bit shift or move operations. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . diff --git a/lib/libpmc/pmc.westmereuc.3 b/lib/libpmc/pmc.westmereuc.3 index 23319cfa5fb3..5e7154efad3f 100644 --- a/lib/libpmc/pmc.westmereuc.3 +++ b/lib/libpmc/pmc.westmereuc.3 @@ -1,1083 +1,1102 @@ .\" Copyright (c) 2010 Fabien Thomas. All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd March 24, 2010 .Dt PMC.WESTMEREUC 3 .Os .Sh NAME .Nm pmc.westmere .Nd uncore measurement events for .Tn Intel .Tn Westmere family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Westmere" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs contain two classes of PMCs: .Bl -tag -width "Li PMC_CLASS_UCP" .It Li PMC_CLASS_UCF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_UCP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Westmere PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-033US" .%D December 2009 .%Q "Intel Corporation" .Re .Ss WESTMERE UNCORE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.ucf 3 . Not all CPUs in this family implement fixed-function counters. .Ss WESTMERE UNCORE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta \&No .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta \&No .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta \&No .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .El .Ss Event Specifiers (Programmable PMCs) Westmere uncore programmable PMCs support the following events: .Bl -tag -width indent .It Li GQ_CYCLES_FULL.READ_TRACKER .Pq Event 00H , Umask 01H Uncore cycles Global Queue read tracker is full. .It Li GQ_CYCLES_FULL.WRITE_TRACKER .Pq Event 00H , Umask 02H Uncore cycles Global Queue write tracker is full. .It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER .Pq Event 00H , Umask 04H -Uncore cycles Global Queue peer probe tracker is full. The peer probe -tracker queue tracks snoops from the IOH and remote sockets. +Uncore cycles Global Queue peer probe tracker is full. +The peer probe tracker queue tracks snoops from the IOH and remote sockets. .It Li GQ_CYCLES_NOT_EMPTY.READ_TRACKER .Pq Event 01H , Umask 01H Uncore cycles were Global Queue read tracker has at least one valid entry. .It Li GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER .Pq Event 01H , Umask 02H Uncore cycles were Global Queue write tracker has at least one valid entry. .It Li GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER .Pq Event 01H , Umask 04H -Uncore cycles were Global Queue peer probe tracker has at least one valid -entry. The peer probe tracker queue tracks IOH and remote socket snoops. +Uncore cycles were Global Queue peer probe tracker has at least one valid entry. +The peer probe tracker queue tracks IOH and remote socket snoops. .It Li GQ_OCCUPANCY.READ_TRACKER .Pq Event 02H , Umask 01H Increments the number of queue entries (code read, data read, and RFOs) in -the tread tracker. The GQ read tracker allocate to deallocate occupancy -count is divided by the count to obtain the average read tracker latency. +the tread tracker. +The GQ read tracker allocate to deallocate occupancy count is divided by the +count to obtain the average read tracker latency. .It Li GQ_ALLOC.READ_TRACKER .Pq Event 03H , Umask 01H -Counts the number of tread tracker allocate to deallocate entries. The GQ -read tracker allocate to deallocate occupancy count is divided by the count -to obtain the average read tracker latency. +Counts the number of tread tracker allocate to deallocate entries. +The GQ read tracker allocate to deallocate occupancy count is divided by +the count to obtain the average read tracker latency. .It Li GQ_ALLOC.RT_L3_MISS .Pq Event 03H , Umask 02H Counts the number GQ read tracker entries for which a full cache line read -has missed the L3. The GQ read tracker L3 miss to fill occupancy count is -divided by this count to obtain the average cache line read L3 miss latency. +has missed the L3. +The GQ read tracker L3 miss to fill occupancy count is divided by this count +to obtain the average cache line read L3 miss latency. The latency represents the time after which the L3 has determined that the -cache line has missed. The time between a GQ read tracker allocation and the -L3 determining that the cache line has missed is the average L3 hit latency. +cache line has missed. +The time between a GQ read tracker allocation and the L3 determining that +the cache line has missed is the average L3 hit latency. The total L3 cache line read miss latency is the hit latency + L3 miss latency. .It Li GQ_ALLOC.RT_TO_L3_RESP .Pq Event 03H , Umask 04H Counts the number of GQ read tracker entries that are allocated in the read -tracker queue that hit or miss the L3. The GQ read tracker L3 hit occupancy -count is divided by this count to obtain the average L3 hit latency. +tracker queue that hit or miss the L3. +The GQ read tracker L3 hit occupancy count is divided by this count to obtain the average L3 hit latency. .It Li GQ_ALLOC.RT_TO_RTID_ACQUIRED .Pq Event 03H , Umask 08H Counts the number of GQ read tracker entries that are allocated in the read -tracker, have missed in the L3 and have not acquired a Request Transaction -ID. The GQ read tracker L3 miss to RTID acquired occupancy count is +tracker, have missed in the L3 and have not acquired a Request Transaction ID. +The GQ read tracker L3 miss to RTID acquired occupancy count is divided by this count to obtain the average latency for a read L3 miss to acquire an RTID. .It Li GQ_ALLOC.WT_TO_RTID_ACQUIRED .Pq Event 03H , Umask 10H Counts the number of GQ write tracker entries that are allocated in the write tracker, have missed in the L3 and have not acquired a Request -Transaction ID. The GQ write tracker L3 miss to RTID occupancy count is -divided by this count to obtain the average latency for a write L3 miss to -acquire an RTID. +Transaction ID. +The GQ write tracker L3 miss to RTID occupancy count is divided by this count +to obtain the average latency for a write L3 miss to acquire an RTID. .It Li GQ_ALLOC.WRITE_TRACKER .Pq Event 03H , Umask 20H -Counts the number of GQ write tracker entries that are allocated in the -write tracker queue that miss the L3. The GQ write tracker occupancy count +Counts the number of GQ write tracker entries that are allocated in the write +tracker queue that miss the L3. +The GQ write tracker occupancy count is divided by the this count to obtain the average L3 write miss latency. .It Li GQ_ALLOC.PEER_PROBE_TRACKER .Pq Event 03H , Umask 40H Counts the number of GQ peer probe tracker (snoop) entries that are -allocated in the peer probe tracker queue that miss the L3. The GQ peer -probe occupancy count is divided by this count to obtain the average L3 peer -probe miss latency. +allocated in the peer probe tracker queue that miss the L3. +The GQ peer probe occupancy count is divided by this count to obtain the average +L3 peer probe miss latency. .It Li GQ_DATA.FROM_QPI .Pq Event 04H , Umask 01H Cycles Global Queue Quickpath Interface input data port is busy importing -data from the Quickpath Interface. Each cycle the input port can transfer 8 -or 16 bytes of data. +data from the Quickpath Interface. +Each cycle the input port can transfer 8 or 16 bytes of data. .It Li GQ_DATA.FROM_QMC .Pq Event 04H , Umask 02H Cycles Global Queue Quickpath Memory Interface input data port is busy -importing data from the Quickpath Memory Interface. Each cycle the input -port can transfer 8 or 16 bytes of data. +importing data from the Quickpath Memory Interface. +Each cycle the input port can transfer 8 or 16 bytes of data. .It Li GQ_DATA.FROM_L3 .Pq Event 04H , Umask 04H -Cycles GQ L3 input data port is busy importing data from the Last Level -Cache. Each cycle the input port can transfer 32 bytes of data. +Cycles GQ L3 input data port is busy importing data from the Last Level Cache. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.FROM_CORES_02 .Pq Event 04H , Umask 08H Cycles GQ Core 0 and 2 input data port is busy importing data from processor -cores 0 and 2. Each cycle the input port can transfer 32 bytes of data. +cores 0 and 2. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.FROM_CORES_13 .Pq Event 04H , Umask 10H Cycles GQ Core 1 and 3 input data port is busy importing data from processor -cores 1 and 3. Each cycle the input port can transfer 32 bytes of data. +cores 1 and 3. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.TO_QPI_QMC .Pq Event 05H , Umask 01H Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath -Interface or Quickpath Memory Interface. Each cycle the output port can -transfer 32 bytes of data. +Interface or Quickpath Memory Interface. +Each cycle the output port can transfer 32 bytes of data. .It Li GQ_DATA.TO_L3 .Pq Event 05H , Umask 02H Cycles GQ L3 output data port is busy sending data to the Last Level Cache. Each cycle the output port can transfer 32 bytes of data. .It Li GQ_DATA.TO_CORES .Pq Event 05H , Umask 04H -Cycles GQ Core output data port is busy sending data to the Cores. Each -cycle the output port can transfer 32 bytes of data. +Cycles GQ Core output data port is busy sending data to the Cores. +Each cycle the output port can transfer 32 bytes of data. .It Li SNP_RESP_TO_LOCAL_HOME.I_STATE .Pq Event 06H , Umask 01H Number of snoop responses to the local home that L3 does not have the referenced cache line. .It Li SNP_RESP_TO_LOCAL_HOME.S_STATE .Pq Event 06H , Umask 02H Number of snoop responses to the local home that L3 has the referenced line cached in the S state. .It Li SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE .Pq Event 06H , Umask 04H Number of responses to code or data read snoops to the local home that the -L3 has the referenced cache line in the E state. The L3 cache line state is -changed to the S state and the line is forwarded to the local home in the S -state. +L3 has the referenced cache line in the E state. +The L3 cache line state is changed to the S state and the line is forwarded +to the local home in the S state. .It Li SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE .Pq Event 06H , Umask 08H Number of responses to read invalidate snoops to the local home that the L3 -has the referenced cache line in the M state. The L3 cache line state is -invalidated and the line is forwarded to the local home in the M state. +has the referenced cache line in the M state. +The L3 cache line state is invalidated and the line is forwarded to the +local home in the M state. .It Li SNP_RESP_TO_LOCAL_HOME.CONFLICT .Pq Event 06H , Umask 10H Number of conflict snoop responses sent to the local home. .It Li SNP_RESP_TO_LOCAL_HOME.WB .Pq Event 06H , Umask 20H Number of responses to code or data read snoops to the local home that the L3 has the referenced line cached in the M state. .It Li SNP_RESP_TO_REMOTE_HOME.I_STATE .Pq Event 07H , Umask 01H Number of snoop responses to a remote home that L3 does not have the referenced cache line. .It Li SNP_RESP_TO_REMOTE_HOME.S_STATE .Pq Event 07H , Umask 02H Number of snoop responses to a remote home that L3 has the referenced line cached in the S state. .It Li SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE .Pq Event 07H , Umask 04H Number of responses to code or data read snoops to a remote home that the L3 -has the referenced cache line in the E state. The L3 cache line state is -changed to the S state and the line is forwarded to the remote home in the S -state. +has the referenced cache line in the E state. +The L3 cache line state is changed to the S state and the line is forwarded +to the remote home in the S state. .It Li SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE .Pq Event 07H , Umask 08H Number of responses to read invalidate snoops to a remote home that the L3 -has the referenced cache line in the M state. The L3 cache line state is -invalidated and the line is forwarded to the remote home in the M state. +has the referenced cache line in the M state. +The L3 cache line state is invalidated and the line is forwarded to the +remote home in the M state. .It Li SNP_RESP_TO_REMOTE_HOME.CONFLICT .Pq Event 07H , Umask 10H Number of conflict snoop responses sent to the local home. .It Li SNP_RESP_TO_REMOTE_HOME.WB .Pq Event 07H , Umask 20H Number of responses to code or data read snoops to a remote home that the L3 has the referenced line cached in the M state. .It Li SNP_RESP_TO_REMOTE_HOME.HITM .Pq Event 07H , Umask 24H Number of HITM snoop responses to a remote home. .It Li L3_HITS.READ .Pq Event 08H , Umask 01H Number of code read, data read and RFO requests that hit in the L3. .It Li L3_HITS.WRITE .Pq Event 08H , Umask 02H -Number of writeback requests that hit in the L3. Writebacks from the cores -will always result in L3 hits due to the inclusive property of the L3. +Number of writeback requests that hit in the L3. +Writebacks from the cores will always result in L3 hits due to the +inclusive property of the L3. .It Li L3_HITS.PROBE .Pq Event 08H , Umask 04H Number of snoops from IOH or remote sockets that hit in the L3. .It Li L3_HITS.ANY .Pq Event 08H , Umask 03H Number of reads and writes that hit the L3. .It Li L3_MISS.READ .Pq Event 09H , Umask 01H Number of code read, data read and RFO requests that miss the L3. .It Li L3_MISS.WRITE .Pq Event 09H , Umask 02H -Number of writeback requests that miss the L3. Should always be zero as -writebacks from the cores will always result in L3 hits due to the inclusive +Number of writeback requests that miss the L3. +Should always be zero as writebacks from the cores will always result in L3 hits due to the inclusive property of the L3. .It Li L3_MISS.PROBE .Pq Event 09H , Umask 04H Number of snoops from IOH or remote sockets that miss the L3. .It Li L3_MISS.ANY .Pq Event 09H , Umask 03H Number of reads and writes that miss the L3. .It Li L3_LINES_IN.M_STATE .Pq Event 0AH , Umask 01H -Counts the number of L3 lines allocated in M state. The only time a cache -line is allocated in the M state is when the line was forwarded in M state -is forwarded due to a Snoop Read Invalidate Own request. +Counts the number of L3 lines allocated in M state. +The only time a cache line is allocated in the M state is when the +line was forwarded in M state is forwarded due to a Snoop Read Invalidate Own request. .It Li L3_LINES_IN.E_STATE .Pq Event 0AH , Umask 02H Counts the number of L3 lines allocated in E state. .It Li L3_LINES_IN.S_STATE .Pq Event 0AH , Umask 04H Counts the number of L3 lines allocated in S state. .It Li L3_LINES_IN.F_STATE .Pq Event 0AH , Umask 08H Counts the number of L3 lines allocated in F state. .It Li L3_LINES_IN.ANY .Pq Event 0AH , Umask 0FH Counts the number of L3 lines allocated in any state. .It Li L3_LINES_OUT.M_STATE .Pq Event 0BH , Umask 01H -Counts the number of L3 lines victimized that were in the M state. When the -victim cache line is in M state, the line is written to its home cache agent +Counts the number of L3 lines victimized that were in the M state. +When the victim cache line is in M state, the line is written to its home cache agent which can be either local or remote. .It Li L3_LINES_OUT.E_STATE .Pq Event 0BH , Umask 02H Counts the number of L3 lines victimized that were in the E state. .It Li L3_LINES_OUT.S_STATE .Pq Event 0BH , Umask 04H Counts the number of L3 lines victimized that were in the S state. .It Li L3_LINES_OUT.I_STATE .Pq Event 0BH , Umask 08H Counts the number of L3 lines victimized that were in the I state. .It Li L3_LINES_OUT.F_STATE .Pq Event 0BH , Umask 10H Counts the number of L3 lines victimized that were in the F state. .It Li L3_LINES_OUT.ANY .Pq Event 0BH , Umask 1FH Counts the number of L3 lines victimized in any state. .It Li GQ_SNOOP.GOTO_S .Pq Event 0CH , Umask 01H Counts the number of remote snoops that have requested a cache line be set to the S state. .It Li GQ_SNOOP.GOTO_I .Pq Event 0CH , Umask 02H Counts the number of remote snoops that have requested a cache line be set to the I state. .It Li GQ_SNOOP.GOTO_S_HIT_E .Pq Event 0CH , Umask 04H Counts the number of remote snoops that have requested a cache line be set to the S state from E state. Requires writing MSR 301H with mask = 2H .It Li GQ_SNOOP.GOTO_S_HIT_F .Pq Event 0CH , Umask 04H Counts the number of remote snoops that have requested a cache line be set to the S state from F (forward) state. Requires writing MSR 301H with mask = 8H .It Li GQ_SNOOP.GOTO_S_HIT_M .Pq Event 0CH , Umask 04H Counts the number of remote snoops that have requested a cache line be set to the S state from M state. Requires writing MSR 301H with mask = 1H .It Li GQ_SNOOP.GOTO_S_HIT_S .Pq Event 0CH , Umask 04H Counts the number of remote snoops that have requested a cache line be set to the S state from S state. Requires writing MSR 301H with mask = 4H .It Li GQ_SNOOP.GOTO_I_HIT_E .Pq Event 0CH , Umask 08H Counts the number of remote snoops that have requested a cache line be set to the I state from E state. Requires writing MSR 301H with mask = 2H .It Li GQ_SNOOP.GOTO_I_HIT_F .Pq Event 0CH , Umask 08H Counts the number of remote snoops that have requested a cache line be set to the I state from F (forward) state. Requires writing MSR 301H with mask = 8H .It Li GQ_SNOOP.GOTO_I_HIT_M .Pq Event 0CH , Umask 08H Counts the number of remote snoops that have requested a cache line be set to the I state from M state. Requires writing MSR 301H with mask = 1H .It Li GQ_SNOOP.GOTO_I_HIT_S .Pq Event 0CH , Umask 08H Counts the number of remote snoops that have requested a cache line be set to the I state from S state. Requires writing MSR 301H with mask = 4H .It Li QHL_REQUESTS.IOH_READS .Pq Event 20H , Umask 01H Counts number of Quickpath Home Logic read requests from the IOH. .It Li QHL_REQUESTS.IOH_WRITES .Pq Event 20H , Umask 02H Counts number of Quickpath Home Logic write requests from the IOH. .It Li QHL_REQUESTS.REMOTE_READS .Pq Event 20H , Umask 04H Counts number of Quickpath Home Logic read requests from a remote socket. .It Li QHL_REQUESTS.REMOTE_WRITES .Pq Event 20H , Umask 08H Counts number of Quickpath Home Logic write requests from a remote socket. .It Li QHL_REQUESTS.LOCAL_READS .Pq Event 20H , Umask 10H Counts number of Quickpath Home Logic read requests from the local socket. .It Li QHL_REQUESTS.LOCAL_WRITES .Pq Event 20H , Umask 20H Counts number of Quickpath Home Logic write requests from the local socket. .It Li QHL_CYCLES_FULL.IOH .Pq Event 21H , Umask 01H Counts uclk cycles all entries in the Quickpath Home Logic IOH are full. .It Li QHL_CYCLES_FULL.REMOTE .Pq Event 21H , Umask 02H Counts uclk cycles all entries in the Quickpath Home Logic remote tracker are full. .It Li QHL_CYCLES_FULL.LOCAL .Pq Event 21H , Umask 04H Counts uclk cycles all entries in the Quickpath Home Logic local tracker are full. .It Li QHL_CYCLES_NOT_EMPTY.IOH .Pq Event 22H , Umask 01H Counts uclk cycles all entries in the Quickpath Home Logic IOH is busy. .It Li QHL_CYCLES_NOT_EMPTY.REMOTE .Pq Event 22H , Umask 02H Counts uclk cycles all entries in the Quickpath Home Logic remote tracker is busy. .It Li QHL_CYCLES_NOT_EMPTY.LOCAL .Pq Event 22H , Umask 04H Counts uclk cycles all entries in the Quickpath Home Logic local tracker is busy. .It Li QHL_OCCUPANCY.IOH .Pq Event 23H , Umask 01H QHL IOH tracker allocate to deallocate read occupancy. .It Li QHL_OCCUPANCY.REMOTE .Pq Event 23H , Umask 02H QHL remote tracker allocate to deallocate read occupancy. .It Li QHL_OCCUPANCY.LOCAL .Pq Event 23H , Umask 04H QHL local tracker allocate to deallocate read occupancy. .It Li QHL_ADDRESS_CONFLICTS.2WAY .Pq Event 24H , Umask 02H -Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 -conflicts. The AAT is a structure that tracks requests that are in conflict. -The requests themselves are in the home tracker entries. The count is -reported when an AAT entry deallocates. +Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 conflicts. +The AAT is a structure that tracks requests that are in conflict. +The requests themselves are in the home tracker entries. +The count is reported when an AAT entry deallocates. .It Li QHL_ADDRESS_CONFLICTS.3WAY .Pq Event 24H , Umask 04H -Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 -conflicts. The AAT is a structure that tracks requests that are in conflict. -The requests themselves are in the home tracker entries. The count is -reported when an AAT entry deallocates. +Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 conflicts. +The AAT is a structure that tracks requests that are in conflict. +The requests themselves are in the home tracker entries. +The count is reported when an AAT entry deallocates. .It Li QHL_CONFLICT_CYCLES.IOH .Pq Event 25H , Umask 01H Counts cycles the Quickpath Home Logic IOH Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_CONFLICT_CYCLES.REMOTE .Pq Event 25H , Umask 02H Counts cycles the Quickpath Home Logic Remote Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_CONFLICT_CYCLES.LOCAL .Pq Event 25H , Umask 04H Counts cycles the Quickpath Home Logic Local Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_TO_QMC_BYPASS .Pq Event 26H , Umask 01H Counts number or requests to the Quickpath Memory Controller that bypass the -Quickpath Home Logic. All local accesses can be bypassed. For remote -requests, only read requests can be bypassed. +Quickpath Home Logic. +All local accesses can be bypassed. +For remote requests, only read requests can be bypassed. .It Li QMC_ISOC_FULL.READ.CH0 .Pq Event 28H , Umask 01H Counts cycles all the entries in the DRAM channel 0 high priority queue are occupied with isochronous read requests. .It Li QMC_ISOC_FULL.READ.CH1 .Pq Event 28H , Umask 02H Counts cycles all the entries in the DRAM channel 1 high priority queue are occupied with isochronous read requests. .It Li QMC_ISOC_FULL.READ.CH2 .Pq Event 28H , Umask 04H Counts cycles all the entries in the DRAM channel 2 high priority queue are occupied with isochronous read requests. .It Li QMC_ISOC_FULL.WRITE.CH0 .Pq Event 28H , Umask 08H Counts cycles all the entries in the DRAM channel 0 high priority queue are occupied with isochronous write requests. .It Li QMC_ISOC_FULL.WRITE.CH1 .Pq Event 28H , Umask 10H Counts cycles all the entries in the DRAM channel 1 high priority queue are occupied with isochronous write requests. .It Li QMC_ISOC_FULL.WRITE.CH2 .Pq Event 28H , Umask 20H Counts cycles all the entries in the DRAM channel 2 high priority queue are occupied with isochronous write requests. .It Li QMC_BUSY.READ.CH0 .Pq Event 29H , Umask 01H Counts cycles where Quickpath Memory Controller has at least 1 outstanding read request to DRAM channel 0. .It Li QMC_BUSY.READ.CH1 .Pq Event 29H , Umask 02H Counts cycles where Quickpath Memory Controller has at least 1 outstanding read request to DRAM channel 1. .It Li QMC_BUSY.READ.CH2 .Pq Event 29H , Umask 04H Counts cycles where Quickpath Memory Controller has at least 1 outstanding read request to DRAM channel 2. .It Li QMC_BUSY.WRITE.CH0 .Pq Event 29H , Umask 08H Counts cycles where Quickpath Memory Controller has at least 1 outstanding write request to DRAM channel 0. .It Li QMC_BUSY.WRITE.CH1 .Pq Event 29H , Umask 10H Counts cycles where Quickpath Memory Controller has at least 1 outstanding write request to DRAM channel 1. .It Li QMC_BUSY.WRITE.CH2 .Pq Event 29H , Umask 20H Counts cycles where Quickpath Memory Controller has at least 1 outstanding write request to DRAM channel 2. .It Li QMC_OCCUPANCY.CH0 .Pq Event 2AH , Umask 01H IMC channel 0 normal read request occupancy. .It Li QMC_OCCUPANCY.CH1 .Pq Event 2AH , Umask 02H IMC channel 1 normal read request occupancy. .It Li QMC_OCCUPANCY.CH2 .Pq Event 2AH , Umask 04H IMC channel 2 normal read request occupancy. .It Li QMC_OCCUPANCY.ANY .Pq Event 2AH , Umask 07H Normal read request occupancy for any channel. .It Li QMC_ISSOC_OCCUPANCY.CH0 .Pq Event 2BH , Umask 01H IMC channel 0 issoc read request occupancy. .It Li QMC_ISSOC_OCCUPANCY.CH1 .Pq Event 2BH , Umask 02H IMC channel 1 issoc read request occupancy. .It Li QMC_ISSOC_OCCUPANCY.CH2 .Pq Event 2BH , Umask 04H IMC channel 2 issoc read request occupancy. .It Li QMC_ISSOC_READS.ANY .Pq Event 2BH , Umask 07H IMC issoc read request occupancy. .It Li QMC_NORMAL_READS.CH0 .Pq Event 2CH , Umask 01H Counts the number of Quickpath Memory Controller channel 0 medium and low -priority read requests. The QMC channel 0 normal read occupancy divided by -this count provides the average QMC channel 0 read latency. +priority read requests. +The QMC channel 0 normal read occupancy divided by this count provides the +average QMC channel 0 read latency. .It Li QMC_NORMAL_READS.CH1 .Pq Event 2CH , Umask 02H Counts the number of Quickpath Memory Controller channel 1 medium and low -priority read requests. The QMC channel 1 normal read occupancy divided by -this count provides the average QMC channel 1 read latency. +priority read requests. +The QMC channel 1 normal read occupancy divided by this count provides the +average QMC channel 1 read latency. .It Li QMC_NORMAL_READS.CH2 .Pq Event 2CH , Umask 04H Counts the number of Quickpath Memory Controller channel 2 medium and low -priority read requests. The QMC channel 2 normal read occupancy divided by -this count provides the average QMC channel 2 read latency. +priority read requests. +The QMC channel 2 normal read occupancy divided by this count provides the +average QMC channel 2 read latency. .It Li QMC_NORMAL_READS.ANY .Pq Event 2CH , Umask 07H -Counts the number of Quickpath Memory Controller medium and low priority -read requests. The QMC normal read occupancy divided by this count provides -the average QMC read latency. +Counts the number of Quickpath Memory Controller medium and low priority read requests. +The QMC normal read occupancy divided by this count provides the average +QMC read latency. .It Li QMC_HIGH_PRIORITY_READS.CH0 .Pq Event 2DH , Umask 01H Counts the number of Quickpath Memory Controller channel 0 high priority isochronous read requests. .It Li QMC_HIGH_PRIORITY_READS.CH1 .Pq Event 2DH , Umask 02H Counts the number of Quickpath Memory Controller channel 1 high priority isochronous read requests. .It Li QMC_HIGH_PRIORITY_READS.CH2 .Pq Event 2DH , Umask 04H Counts the number of Quickpath Memory Controller channel 2 high priority isochronous read requests. .It Li QMC_HIGH_PRIORITY_READS.ANY .Pq Event 2DH , Umask 07H Counts the number of Quickpath Memory Controller high priority isochronous read requests. .It Li QMC_CRITICAL_PRIORITY_READS.CH0 .Pq Event 2EH , Umask 01H Counts the number of Quickpath Memory Controller channel 0 critical priority isochronous read requests. .It Li QMC_CRITICAL_PRIORITY_READS.CH1 .Pq Event 2EH , Umask 02H Counts the number of Quickpath Memory Controller channel 1 critical priority isochronous read requests. .It Li QMC_CRITICAL_PRIORITY_READS.CH2 .Pq Event 2EH , Umask 04H Counts the number of Quickpath Memory Controller channel 2 critical priority isochronous read requests. .It Li QMC_CRITICAL_PRIORITY_READS.ANY .Pq Event 2EH , Umask 07H Counts the number of Quickpath Memory Controller critical priority isochronous read requests. .It Li QMC_WRITES.FULL.CH0 .Pq Event 2FH , Umask 01H Counts number of full cache line writes to DRAM channel 0. .It Li QMC_WRITES.FULL.CH1 .Pq Event 2FH , Umask 02H Counts number of full cache line writes to DRAM channel 1. .It Li QMC_WRITES.FULL.CH2 .Pq Event 2FH , Umask 04H Counts number of full cache line writes to DRAM channel 2. .It Li QMC_WRITES.FULL.ANY .Pq Event 2FH , Umask 07H Counts number of full cache line writes to DRAM. .It Li QMC_WRITES.PARTIAL.CH0 .Pq Event 2FH , Umask 08H Counts number of partial cache line writes to DRAM channel 0. .It Li QMC_WRITES.PARTIAL.CH1 .Pq Event 2FH , Umask 10H Counts number of partial cache line writes to DRAM channel 1. .It Li QMC_WRITES.PARTIAL.CH2 .Pq Event 2FH , Umask 20H Counts number of partial cache line writes to DRAM channel 2. .It Li QMC_WRITES.PARTIAL.ANY .Pq Event 2FH , Umask 38H Counts number of partial cache line writes to DRAM. .It Li QMC_CANCEL.CH0 .Pq Event 30H , Umask 01H Counts number of DRAM channel 0 cancel requests. .It Li QMC_CANCEL.CH1 .Pq Event 30H , Umask 02H Counts number of DRAM channel 1 cancel requests. .It Li QMC_CANCEL.CH2 .Pq Event 30H , Umask 04H Counts number of DRAM channel 2 cancel requests. .It Li QMC_CANCEL.ANY .Pq Event 30H , Umask 07H Counts number of DRAM cancel requests. .It Li QMC_PRIORITY_UPDATES.CH0 .Pq Event 31H , Umask 01H -Counts number of DRAM channel 0 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to +Counts number of DRAM channel 0 priority updates. +A priority update occurs when an ISOC high or critical request is +received by the QHL and there is a matching request with normal priority +that has already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.CH1 .Pq Event 31H , Umask 02H -Counts number of DRAM channel 1 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to -expedite the request. +Counts number of DRAM channel 1 priority updates. +A priority update occurs when an ISOC high or critical request is received +by the QHL and there is a matching request with normal priority that has +already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.CH2 .Pq Event 31H , Umask 04H -Counts number of DRAM channel 2 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to -expedite the request. +Counts number of DRAM channel 2 priority updates. +A priority update occurs when an ISOC high or critical request is received +by the QHL and there is a matching request with normal priority that has +already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.ANY .Pq Event 31H , Umask 07H -Counts number of DRAM priority updates. A priority update occurs when an -ISOC high or critical request is received by the QHL and there is a matching -request with normal priority that has already been issued to the QMC. In -this instance, the QHL will send a priority update to QMC to expedite the -request. +Counts number of DRAM priority updates. +A priority update occurs when an ISOC high or critical request is received +by the QHL and there is a matching request with normal priority that has already +been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li IMC_RETRY.CH0 .Pq Event 32H , Umask 01H -Counts number of IMC DRAM channel 0 retries. DRAM retry only occurs when -configured in RAS mode. +Counts number of IMC DRAM channel 0 retries. +DRAM retry only occurs when configured in RAS mode. .It Li IMC_RETRY.CH1 .Pq Event 32H , Umask 02H -Counts number of IMC DRAM channel 1 retries. DRAM retry only occurs when -configured in RAS mode. +Counts number of IMC DRAM channel 1 retries. +DRAM retry only occurs when configured in RAS mode. .It Li IMC_RETRY.CH2 .Pq Event 32H , Umask 04H -Counts number of IMC DRAM channel 2 retries. DRAM retry only occurs when -configured in RAS mode. +Counts number of IMC DRAM channel 2 retries. +DRAM retry only occurs when configured in RAS mode. .It Li IMC_RETRY.ANY .Pq Event 32H , Umask 07H -Counts number of IMC DRAM retries from any channel. DRAM retry only occurs -when configured in RAS mode. +Counts number of IMC DRAM retries from any channel. +DRAM retry only occurs when configured in RAS mode. .It Li QHL_FRC_ACK_CNFLTS.IOH .Pq Event 33H , Umask 01H Counts number of Force Acknowledge Conflict messages sent by the Quickpath Home Logic to the IOH. .It Li QHL_FRC_ACK_CNFLTS.REMOTE .Pq Event 33H , Umask 02H Counts number of Force Acknowledge Conflict messages sent by the Quickpath Home Logic to the remote home. .It Li QHL_FRC_ACK_CNFLTS.LOCAL .Pq Event 33H , Umask 04H Counts number of Force Acknowledge Conflict messages sent by the Quickpath Home Logic to the local home. .It Li QHL_FRC_ACK_CNFLTS.ANY .Pq Event 33H , Umask 07H Counts number of Force Acknowledge Conflict messages sent by the Quickpath Home Logic. .It Li QHL_SLEEPS.IOH_ORDER .Pq Event 34H , Umask 01H Counts number of occurrences a request was put to sleep due to IOH ordering -(write after read) conflicts. While in the sleep state, the request is not -eligible to be scheduled to the QMC. +(write after read) conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li QHL_SLEEPS.REMOTE_ORDER .Pq Event 34H , Umask 02H Counts number of occurrences a request was put to sleep due to remote socket -ordering (write after read) conflicts. While in the sleep state, the request -is not eligible to be scheduled to the QMC. +ordering (write after read) conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li QHL_SLEEPS.LOCAL_ORDER .Pq Event 34H , Umask 04H Counts number of occurrences a request was put to sleep due to local socket -ordering (write after read) conflicts. While in the sleep state, the request -is not eligible to be scheduled to the QMC. +ordering (write after read) conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li QHL_SLEEPS.IOH_CONFLICT .Pq Event 34H , Umask 08H -Counts number of occurrences a request was put to sleep due to IOH address -conflicts. While in the sleep state, the request is not eligible to be -scheduled to the QMC. +Counts number of occurrences a request was put to sleep due to IOH address conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li QHL_SLEEPS.REMOTE_CONFLICT .Pq Event 34H , Umask 10H Counts number of occurrences a request was put to sleep due to remote socket -address conflicts. While in the sleep state, the request is not eligible to -be scheduled to the QMC. +address conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li QHL_SLEEPS.LOCAL_CONFLICT .Pq Event 34H , Umask 20H -Counts number of occurrences a request was put to sleep due to local socket -address conflicts. While in the sleep state, the request is not eligible to -be scheduled to the QMC. +Counts number of occurrences a request was put to sleep due to local socket address conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li ADDR_OPCODE_MATCH.IOH .Pq Event 35H , Umask 01H Counts number of requests from the IOH, address/opcode of request is -qualified by mask value written to MSR 396H. The following mask values are -supported: +qualified by mask value written to MSR 396H. +The following mask values are supported: 0: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 40001D00_00000000H:RSPIWB Match opcode/address by writing MSR 396H with mask supported mask value. .It Li ADDR_OPCODE_MATCH.REMOTE .Pq Event 35H , Umask 02H Counts number of requests from the remote socket, address/opcode of request -is qualified by mask value written to MSR 396H. The following mask values -are supported: +is qualified by mask value written to MSR 396H. +The following mask values are supported: 0: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 40001D00_00000000H:RSPIWB Match opcode/address by writing MSR 396H with mask supported mask value. .It Li ADDR_OPCODE_MATCH.LOCAL .Pq Event 35H , Umask 04H Counts number of requests from the local socket, address/opcode of request -is qualified by mask value written to MSR 396H. The following mask values -are supported: +is qualified by mask value written to MSR 396H. +The following mask values are supported: 0: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 40001D00_00000000H:RSPIWB Match opcode/address by writing MSR 396H with mask supported mask value. .It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0 .Pq Event 40H , Umask 01H Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0 .Pq Event 40H , Umask 02H Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0 .Pq Event 40H , Umask 04H Counts cycles the Quickpath outbound link 0 non-data response virtual -channel is stalled due to lack of a VNA and VN0 credit. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1 .Pq Event 40H , Umask 08H Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1 .Pq Event 40H , Umask 10H Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1 .Pq Event 40H , Umask 20H Counts cycles the Quickpath outbound link 1 non-data response virtual -channel is stalled due to lack of a VNA and VN0 credit. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_0 .Pq Event 40H , Umask 07H Counts cycles the Quickpath outbound link 0 virtual channels are stalled due -to lack of a VNA and VN0 credit. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_1 .Pq Event 40H , Umask 38H Counts cycles the Quickpath outbound link 1 virtual channels are stalled due -to lack of a VNA and VN0 credit. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0 .Pq Event 41H , Umask 01H Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is -stalled due to lack of VNA and VN0 credits. Note that this event does not -filter out when a flit would not have been selected for arbitration because -another virtual channel is getting arbitrated. +stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0 .Pq Event 41H , Umask 02H Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0 .Pq Event 41H , Umask 04H Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1 .Pq Event 41H , Umask 08H Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is -stalled due to lack of VNA and VN0 credits. Note that this event does not -filter out when a flit would not have been selected for arbitration because -another virtual channel is getting arbitrated. +stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1 .Pq Event 41H , Umask 10H Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1 .Pq Event 41H , Umask 20H Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.LINK_0 .Pq Event 41H , Umask 07H Counts cycles the Quickpath outbound link 0 virtual channels are stalled due -to lack of VNA and VN0 credits. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.LINK_1 .Pq Event 41H , Umask 38H Counts cycles the Quickpath outbound link 1 virtual channels are stalled due -to lack of VNA and VN0 credits. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_HEADER.FULL.LINK_0 .Pq Event 42H , Umask 01H Number of cycles that the header buffer in the Quickpath Interface outbound link 0 is full. .It Li QPI_TX_HEADER.BUSY.LINK_0 .Pq Event 42H , Umask 02H Number of cycles that the header buffer in the Quickpath Interface outbound link 0 is busy. .It Li QPI_TX_HEADER.FULL.LINK_1 .Pq Event 42H , Umask 04H Number of cycles that the header buffer in the Quickpath Interface outbound link 1 is full. .It Li QPI_TX_HEADER.BUSY.LINK_1 .Pq Event 42H , Umask 08H Number of cycles that the header buffer in the Quickpath Interface outbound link 1 is busy. .It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0 .Pq Event 43H , Umask 01H Number of cycles that snoop packets incoming to the Quickpath Interface link 0 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) does not have any available entries. .It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1 .Pq Event 43H , Umask 02H Number of cycles that snoop packets incoming to the Quickpath Interface link 1 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) does not have any available entries. .It Li DRAM_OPEN.CH0 .Pq Event 60H , Umask 01H -Counts number of DRAM Channel 0 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 0 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_OPEN.CH1 .Pq Event 60H , Umask 02H -Counts number of DRAM Channel 1 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 1 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_OPEN.CH2 .Pq Event 60H , Umask 04H -Counts number of DRAM Channel 2 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 2 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_PAGE_CLOSE.CH0 .Pq Event 61H , Umask 01H -DRAM channel 0 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +DRAM channel 0 command issued to CLOSE a page due to page idle timer expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_CLOSE.CH1 .Pq Event 61H , Umask 02H -DRAM channel 1 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +DRAM channel 1 command issued to CLOSE a page due to page idle timer expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_CLOSE.CH2 .Pq Event 61H , Umask 04H -DRAM channel 2 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +DRAM channel 2 command issued to CLOSE a page due to page idle timer expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH0 .Pq Event 62H , Umask 01H Counts the number of precharges (PRE) that were issued to DRAM channel 0 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and another +page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH1 .Pq Event 62H , Umask 02H Counts the number of precharges (PRE) that were issued to DRAM channel 1 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and another +page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH2 .Pq Event 62H , Umask 04H Counts the number of precharges (PRE) that were issued to DRAM channel 2 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and another +page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_READ_CAS.CH0 .Pq Event 63H , Umask 01H Counts the number of times a read CAS command was issued on DRAM channel 0. .It Li DRAM_READ_CAS.AUTOPRE_CH0 .Pq Event 63H , Umask 02H Counts the number of times a read CAS command was issued on DRAM channel 0 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_READ_CAS.CH1 .Pq Event 63H , Umask 04H Counts the number of times a read CAS command was issued on DRAM channel 1. .It Li DRAM_READ_CAS.AUTOPRE_CH1 .Pq Event 63H , Umask 08H Counts the number of times a read CAS command was issued on DRAM channel 1 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_READ_CAS.CH2 .Pq Event 63H , Umask 10H Counts the number of times a read CAS command was issued on DRAM channel 2. .It Li DRAM_READ_CAS.AUTOPRE_CH2 .Pq Event 63H , Umask 20H Counts the number of times a read CAS command was issued on DRAM channel 2 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_WRITE_CAS.CH0 .Pq Event 64H , Umask 01H Counts the number of times a write CAS command was issued on DRAM channel 0. .It Li DRAM_WRITE_CAS.AUTOPRE_CH0 .Pq Event 64H , Umask 02H Counts the number of times a write CAS command was issued on DRAM channel 0 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_WRITE_CAS.CH1 .Pq Event 64H , Umask 04H Counts the number of times a write CAS command was issued on DRAM channel 1. .It Li DRAM_WRITE_CAS.AUTOPRE_CH1 .Pq Event 64H , Umask 08H Counts the number of times a write CAS command was issued on DRAM channel 1 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_WRITE_CAS.CH2 .Pq Event 64H , Umask 10H Counts the number of times a write CAS command was issued on DRAM channel 2. .It Li DRAM_WRITE_CAS.AUTOPRE_CH2 .Pq Event 64H , Umask 20H Counts the number of times a write CAS command was issued on DRAM channel 2 where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_REFRESH.CH0 .Pq Event 65H , Umask 01H -Counts number of DRAM channel 0 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be +Counts number of DRAM channel 0 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_REFRESH.CH1 .Pq Event 65H , Umask 02H -Counts number of DRAM channel 1 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be -refreshed periodically. +Counts number of DRAM channel 1 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_REFRESH.CH2 .Pq Event 65H , Umask 04H -Counts number of DRAM channel 2 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be -refreshed periodically. +Counts number of DRAM channel 2 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_PRE_ALL.CH0 .Pq Event 66H , Umask 01H Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode. .It Li DRAM_PRE_ALL.CH1 .Pq Event 66H , Umask 02H Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode. .It Li DRAM_PRE_ALL.CH2 .Pq Event 66H , Umask 04H Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode. .It Li DRAM_THERMAL_THROTTLED .Pq Event 67H , Umask 01H Uncore cycles DRAM was throttled due to its temperature being above the thermal throttling threshold. .It Li THERMAL_THROTTLING_TEMP.CORE_0 .Pq Event 80H , Umask 01H Cycles that the PCU records that core 0 is above the thermal throttling threshold temperature. .It Li THERMAL_THROTTLING_TEMP.CORE_1 .Pq Event 80H , Umask 02H Cycles that the PCU records that core 1 is above the thermal throttling threshold temperature. .It Li THERMAL_THROTTLING_TEMP.CORE_2 .Pq Event 80H , Umask 04H Cycles that the PCU records that core 2 is above the thermal throttling threshold temperature. .It Li THERMAL_THROTTLING_TEMP.CORE_3 .Pq Event 80H , Umask 08H Cycles that the PCU records that core 3 is above the thermal throttling threshold temperature. .It Li THERMAL_THROTTLED_TEMP.CORE_0 .Pq Event 81H , Umask 01H Cycles that the PCU records that core 0 is in the power throttled state due to cores temperature being above the thermal throttling threshold. .It Li THERMAL_THROTTLED_TEMP.CORE_1 .Pq Event 81H , Umask 02H Cycles that the PCU records that core 1 is in the power throttled state due to cores temperature being above the thermal throttling threshold. .It Li THERMAL_THROTTLED_TEMP.CORE_2 .Pq Event 81H , Umask 04H Cycles that the PCU records that core 2 is in the power throttled state due to cores temperature being above the thermal throttling threshold. .It Li THERMAL_THROTTLED_TEMP.CORE_3 .Pq Event 81H , Umask 08H Cycles that the PCU records that core 3 is in the power throttled state due to cores temperature being above the thermal throttling threshold. .It Li PROCHOT_ASSERTION .Pq Event 82H , Umask 01H Number of system assertions of PROCHOT indicating the entire processor has exceeded the thermal limit. .It Li THERMAL_THROTTLING_PROCHOT.CORE_0 .Pq Event 83H , Umask 01H Cycles that the PCU records that core 0 is a low power state due to the system asserting PROCHOT the entire processor has exceeded the thermal limit. .It Li THERMAL_THROTTLING_PROCHOT.CORE_1 .Pq Event 83H , Umask 02H Cycles that the PCU records that core 1 is a low power state due to the system asserting PROCHOT the entire processor has exceeded the thermal limit. .It Li THERMAL_THROTTLING_PROCHOT.CORE_2 .Pq Event 83H , Umask 04H Cycles that the PCU records that core 2 is a low power state due to the system asserting PROCHOT the entire processor has exceeded the thermal limit. .It Li THERMAL_THROTTLING_PROCHOT.CORE_3 .Pq Event 83H , Umask 08H Cycles that the PCU records that core 3 is a low power state due to the system asserting PROCHOT the entire processor has exceeded the thermal limit. .It Li TURBO_MODE.CORE_0 .Pq Event 84H , Umask 01H Uncore cycles that core 0 is operating in turbo mode. .It Li TURBO_MODE.CORE_1 .Pq Event 84H , Umask 02H Uncore cycles that core 1 is operating in turbo mode. .It Li TURBO_MODE.CORE_2 .Pq Event 84H , Umask 04H Uncore cycles that core 2 is operating in turbo mode. .It Li TURBO_MODE.CORE_3 .Pq Event 84H , Umask 08H Uncore cycles that core 3 is operating in turbo mode. .It Li CYCLES_UNHALTED_L3_FLL_ENABLE .Pq Event 85H , Umask 02H Uncore cycles that at least one core is unhalted and all L3 ways are enabled. .It Li CYCLES_UNHALTED_L3_FLL_DISABLE .Pq Event 86H , Umask 01H Uncore cycles that at least one core is unhalted and all L3 ways are disabled. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .