diff --git a/sys/dev/uart/uart_bus_pci.c b/sys/dev/uart/uart_bus_pci.c index fe5ad2b6d206..a20be1c577d4 100644 --- a/sys/dev/uart/uart_bus_pci.c +++ b/sys/dev/uart/uart_bus_pci.c @@ -1,299 +1,350 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2006 Marcel Moolenaar All rights reserved. * Copyright (c) 2001 M. Warner Losh * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include +#include #define DEFAULT_RCLK 1843200 static int uart_pci_probe(device_t dev); static int uart_pci_attach(device_t dev); static int uart_pci_detach(device_t dev); static device_method_t uart_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, uart_pci_probe), DEVMETHOD(device_attach, uart_pci_attach), DEVMETHOD(device_detach, uart_pci_detach), DEVMETHOD(device_resume, uart_bus_resume), DEVMETHOD_END }; static driver_t uart_pci_driver = { uart_driver_name, uart_pci_methods, sizeof(struct uart_softc), }; struct pci_id { uint16_t vendor; uint16_t device; uint16_t subven; uint16_t subdev; const char *desc; int rid; int rclk; int regshft; }; +struct pci_unique_id { + uint16_t vendor; + uint16_t device; +}; + #define PCI_NO_MSI 0x40000000 #define PCI_RID_MASK 0x0000ffff static const struct pci_id pci_ns8250_ids[] = { { 0x1028, 0x0008, 0xffff, 0, "Dell Remote Access Card III", 0x14, 128 * DEFAULT_RCLK }, { 0x1028, 0x0012, 0xffff, 0, "Dell RAC 4 Daughter Card Virtual UART", 0x14, 128 * DEFAULT_RCLK }, { 0x1033, 0x0074, 0x1033, 0x8014, "NEC RCV56ACF 56k Voice Modem", 0x10 }, { 0x1033, 0x007d, 0x1033, 0x8012, "NEC RS232C", 0x10 }, { 0x103c, 0x1048, 0x103c, 0x1227, "HP Diva Serial [GSP] UART - Powerbar SP2", 0x10 }, { 0x103c, 0x1048, 0x103c, 0x1301, "HP Diva RMP3", 0x14 }, { 0x103c, 0x1290, 0xffff, 0, "HP Auxiliary Diva Serial Port", 0x18 }, { 0x103c, 0x3301, 0xffff, 0, "HP iLO serial port", 0x10 }, { 0x11c1, 0x0480, 0xffff, 0, "Agere Systems Venus Modem (V90, 56KFlex)", 0x14 }, { 0x115d, 0x0103, 0xffff, 0, "Xircom Cardbus Ethernet + 56k Modem", 0x10 }, { 0x125b, 0x9100, 0xa000, 0x1000, "ASIX AX99100 PCIe 1/2/3/4-port RS-232/422/485", 0x10 }, { 0x1282, 0x6585, 0xffff, 0, "Davicom 56PDV PCI Modem", 0x10 }, { 0x12b9, 0x1008, 0xffff, 0, "3Com 56K FaxModem Model 5610", 0x10 }, { 0x131f, 0x1000, 0xffff, 0, "Siig CyberSerial (1-port) 16550", 0x18 }, { 0x131f, 0x1001, 0xffff, 0, "Siig CyberSerial (1-port) 16650", 0x18 }, { 0x131f, 0x1002, 0xffff, 0, "Siig CyberSerial (1-port) 16850", 0x18 }, { 0x131f, 0x2000, 0xffff, 0, "Siig CyberSerial (1-port) 16550", 0x10 }, { 0x131f, 0x2001, 0xffff, 0, "Siig CyberSerial (1-port) 16650", 0x10 }, { 0x131f, 0x2002, 0xffff, 0, "Siig CyberSerial (1-port) 16850", 0x10 }, { 0x135c, 0x0190, 0xffff, 0, "Quatech SSCLP-100", 0x18 }, { 0x135c, 0x01c0, 0xffff, 0, "Quatech SSCLP-200/300", 0x18 }, { 0x135e, 0x7101, 0xffff, 0, "Sealevel Systems Single Port RS-232/422/485/530", 0x18 }, { 0x1407, 0x0110, 0xffff, 0, "Lava Computer mfg DSerial-PCI Port A", 0x10 }, { 0x1407, 0x0111, 0xffff, 0, "Lava Computer mfg DSerial-PCI Port B", 0x10 }, { 0x1407, 0x0510, 0xffff, 0, "Lava SP Serial 550 PCI", 0x10 }, { 0x1409, 0x7168, 0x1409, 0x4025, "Timedia Technology Serial Port", 0x10, 8 * DEFAULT_RCLK }, { 0x1409, 0x7168, 0x1409, 0x4027, "Timedia Technology Serial Port", 0x10, 8 * DEFAULT_RCLK }, { 0x1409, 0x7168, 0x1409, 0x4028, "Timedia Technology Serial Port", 0x10, 8 * DEFAULT_RCLK }, { 0x1409, 0x7168, 0x1409, 0x5025, "Timedia Technology Serial Port", 0x10, 8 * DEFAULT_RCLK }, { 0x1409, 0x7168, 0x1409, 0x5027, "Timedia Technology Serial Port", 0x10, 8 * DEFAULT_RCLK }, { 0x1415, 0x950b, 0xffff, 0, "Oxford Semiconductor OXCB950 Cardbus 16950 UART", 0x10, 16384000 }, { 0x1415, 0xc120, 0xffff, 0, "Oxford Semiconductor OXPCIe952 PCIe 16950 UART", 0x10 }, { 0x14e4, 0x160a, 0xffff, 0, "Broadcom TruManage UART", 0x10, 128 * DEFAULT_RCLK, 2}, { 0x14e4, 0x4344, 0xffff, 0, "Sony Ericsson GC89 PC Card", 0x10}, { 0x151f, 0x0000, 0xffff, 0, "TOPIC Semiconductor TP560 56k modem", 0x10 }, { 0x1d0f, 0x8250, 0x0000, 0, "Amazon PCI serial device", 0x10 }, { 0x1d0f, 0x8250, 0x1d0f, 0, "Amazon PCI serial device", 0x10 }, { 0x1fd4, 0x1999, 0x1fd4, 0x0001, "Sunix SER5xxxx Serial Port", 0x10, 8 * DEFAULT_RCLK }, { 0x8086, 0x0f0a, 0xffff, 0, "Intel ValleyView LPIO1 HSUART#1", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x0f0c, 0xffff, 0, "Intel ValleyView LPIO1 HSUART#2", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x108f, 0xffff, 0, "Intel AMT - SOL", 0x10 }, { 0x8086, 0x19d8, 0xffff, 0, "Intel Denverton UART", 0x10 }, { 0x8086, 0x1c3d, 0xffff, 0, "Intel AMT - KT Controller", 0x10 }, { 0x8086, 0x1d3d, 0xffff, 0, "Intel C600/X79 Series Chipset KT Controller", 0x10 }, { 0x8086, 0x1e3d, 0xffff, 0, "Intel Panther Point KT Controller", 0x10 }, { 0x8086, 0x228a, 0xffff, 0, "Intel Cherryview SIO HSUART#1", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x228c, 0xffff, 0, "Intel Cherryview SIO HSUART#2", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x2a07, 0xffff, 0, "Intel AMT - PM965/GM965 KT Controller", 0x10 }, { 0x8086, 0x2a47, 0xffff, 0, "Mobile 4 Series Chipset KT Controller", 0x10 }, { 0x8086, 0x2e17, 0xffff, 0, "4 Series Chipset Serial KT Controller", 0x10 }, { 0x8086, 0x31bc, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 0", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x31be, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 1", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x31c0, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 2", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x31ee, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 3", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x3b67, 0xffff, 0, "5 Series/3400 Series Chipset KT Controller", 0x10 }, { 0x8086, 0x5abc, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 0", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x5abe, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 1", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x5ac0, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 2", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x5aee, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 3", 0x10, 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x8811, 0xffff, 0, "Intel EG20T Serial Port 0", 0x10 }, { 0x8086, 0x8812, 0xffff, 0, "Intel EG20T Serial Port 1", 0x10 }, { 0x8086, 0x8813, 0xffff, 0, "Intel EG20T Serial Port 2", 0x10 }, { 0x8086, 0x8814, 0xffff, 0, "Intel EG20T Serial Port 3", 0x10 }, { 0x8086, 0x8c3d, 0xffff, 0, "Intel Lynx Point KT Controller", 0x10 }, { 0x8086, 0x8cbd, 0xffff, 0, "Intel Wildcat Point KT Controller", 0x10 }, { 0x8086, 0x9c3d, 0xffff, 0, "Intel Lynx Point-LP HECI KT", 0x10 }, { 0x8086, 0xa13d, 0xffff, 0, "100 Series/C230 Series Chipset Family KT Redirection", 0x10 | PCI_NO_MSI }, { 0x9710, 0x9820, 0x1000, 1, "NetMos NM9820 Serial Port", 0x10 }, { 0x9710, 0x9835, 0x1000, 1, "NetMos NM9835 Serial Port", 0x10 }, { 0x9710, 0x9865, 0xa000, 0x1000, "NetMos NM9865 Serial Port", 0x10 }, { 0x9710, 0x9900, 0xa000, 0x1000, "MosChip MCS9900 PCIe to Peripheral Controller", 0x10 }, { 0x9710, 0x9901, 0xa000, 0x1000, "MosChip MCS9901 PCIe to Peripheral Controller", 0x10 }, { 0x9710, 0x9904, 0xa000, 0x1000, "MosChip MCS9904 PCIe to Peripheral Controller", 0x10 }, { 0x9710, 0x9922, 0xa000, 0x1000, "MosChip MCS9922 PCIe to Peripheral Controller", 0x10 }, { 0xdeaf, 0x9051, 0xffff, 0, "Middle Digital PC Weasel Serial Port", 0x10 }, { 0xffff, 0, 0xffff, 0, NULL, 0, 0} }; const static struct pci_id * uart_pci_match(device_t dev, const struct pci_id *id) { uint16_t device, subdev, subven, vendor; vendor = pci_get_vendor(dev); device = pci_get_device(dev); while (id->vendor != 0xffff && (id->vendor != vendor || id->device != device)) id++; if (id->vendor == 0xffff) return (NULL); if (id->subven == 0xffff) return (id); subven = pci_get_subvendor(dev); subdev = pci_get_subdevice(dev); while (id->vendor == vendor && id->device == device && (id->subven != subven || id->subdev != subdev)) id++; return ((id->vendor == vendor && id->device == device) ? id : NULL); } +extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; + +/* PCI vendor/device pairs of devices guaranteed to be unique on a system. */ +static const struct pci_unique_id pci_unique_devices[] = { +{ 0x1d0f, 0x8250 } /* Amazon PCI serial device */ +}; + +/* Match a UART to a console if it's a PCI device known to be unique. */ +static void +uart_pci_unique_console_match(device_t dev) +{ + struct uart_softc *sc; + struct uart_devinfo * sysdev; + const struct pci_unique_id * id; + uint16_t vendor, device; + + sc = device_get_softc(dev); + vendor = pci_get_vendor(dev); + device = pci_get_device(dev); + + /* Is this a device known to exist only once in a system? */ + for (id = pci_unique_devices; ; id++) { + if (id == &pci_unique_devices[nitems(pci_unique_devices)]) + return; + if (id->vendor == vendor && id->device == device) + break; + } + + /* If it matches a console, it must be the same device. */ + SLIST_FOREACH(sysdev, &uart_sysdevs, next) { + if (sysdev->pci_info.vendor == vendor && + sysdev->pci_info.device == device) { + sc->sc_sysdev = sysdev; + sysdev->bas.rclk = sc->sc_bas.rclk; + } + } +} + static int uart_pci_probe(device_t dev) { struct uart_softc *sc; const struct pci_id *id; struct pci_id cid = { .regshft = 0, .rclk = 0, .rid = 0x10 | PCI_NO_MSI, .desc = "Generic SimpleComm PCI device", }; int result; sc = device_get_softc(dev); id = uart_pci_match(dev, pci_ns8250_ids); if (id != NULL) { sc->sc_class = &uart_ns8250_class; goto match; } if (pci_get_class(dev) == PCIC_SIMPLECOMM && pci_get_subclass(dev) == PCIS_SIMPLECOMM_UART && pci_get_progif(dev) < PCIP_SIMPLECOMM_UART_16550A) { /* XXX rclk what to do */ id = &cid; sc->sc_class = &uart_ns8250_class; goto match; } /* Add checks for non-ns8250 IDs here. */ return (ENXIO); match: result = uart_bus_probe(dev, id->regshft, 0, id->rclk, id->rid & PCI_RID_MASK, 0, 0); /* Bail out on error. */ if (result > 0) return (result); + /* + * If we haven't already matched this to a console, check if it's a + * PCI device which is known to only exist once in any given system + * and we can match it that way. + */ + if (sc->sc_sysdev == NULL) + uart_pci_unique_console_match(dev); /* Set/override the device description. */ if (id->desc) device_set_desc(dev, id->desc); return (result); } static int uart_pci_attach(device_t dev) { struct uart_softc *sc; const struct pci_id *id; int count; sc = device_get_softc(dev); /* * Use MSI in preference to legacy IRQ if available. However, experience * suggests this is only reliable when one MSI vector is advertised. */ id = uart_pci_match(dev, pci_ns8250_ids); if ((id == NULL || (id->rid & PCI_NO_MSI) == 0) && pci_msi_count(dev) == 1) { count = 1; if (pci_alloc_msi(dev, &count) == 0) { sc->sc_irid = 1; device_printf(dev, "Using %d MSI message\n", count); } } return (uart_bus_attach(dev)); } static int uart_pci_detach(device_t dev) { struct uart_softc *sc; sc = device_get_softc(dev); if (sc->sc_irid != 0) pci_release_msi(dev); return (uart_bus_detach(dev)); } DRIVER_MODULE(uart, pci, uart_pci_driver, uart_devclass, NULL, NULL); diff --git a/sys/dev/uart/uart_cpu.h b/sys/dev/uart/uart_cpu.h index 4f34c767efc0..4eb7327fc788 100644 --- a/sys/dev/uart/uart_cpu.h +++ b/sys/dev/uart/uart_cpu.h @@ -1,179 +1,188 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2003, 2004 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV_UART_CPU_H_ #define _DEV_UART_CPU_H_ #include #include #include struct uart_softc; /* * Low-level operations for use by console and/or debug port support. */ struct uart_ops { int (*probe)(struct uart_bas *); void (*init)(struct uart_bas *, int, int, int, int); void (*term)(struct uart_bas *); void (*putc)(struct uart_bas *, int); int (*rxready)(struct uart_bas *); int (*getc)(struct uart_bas *, struct mtx *); }; extern bus_space_tag_t uart_bus_space_io; extern bus_space_tag_t uart_bus_space_mem; +/* + * PCI ID used for matching "unique" devices to a console. + */ +struct uart_pci_info { + uint16_t vendor; + uint16_t device; +}; + /* * Console and debug port device info. */ struct uart_devinfo { SLIST_ENTRY(uart_devinfo) next; struct uart_ops *ops; struct uart_bas bas; int baudrate; int databits; int stopbits; int parity; int type; #define UART_DEV_CONSOLE 0 #define UART_DEV_DBGPORT 1 #define UART_DEV_KEYBOARD 2 int (*attach)(struct uart_softc*); int (*detach)(struct uart_softc*); void *cookie; /* Type dependent use. */ struct mtx *hwmtx; struct uart_softc *sc; /* valid only from start of attach */ + struct uart_pci_info pci_info; }; int uart_cpu_eqres(struct uart_bas *, struct uart_bas *); int uart_cpu_getdev(int, struct uart_devinfo *); int uart_getenv(int, struct uart_devinfo *, struct uart_class *); const char *uart_getname(struct uart_class *); struct uart_ops *uart_getops(struct uart_class *); int uart_getrange(struct uart_class *); u_int uart_getregshift(struct uart_class *); u_int uart_getregiowidth(struct uart_class *); void uart_add_sysdev(struct uart_devinfo *); /* * Operations for low-level access to the UART. Primarily for use * by console and debug port logic. */ static __inline void uart_lock(struct mtx *hwmtx) { if (!kdb_active && hwmtx != NULL) mtx_lock_spin(hwmtx); } static __inline void uart_unlock(struct mtx *hwmtx) { if (!kdb_active && hwmtx != NULL) mtx_unlock_spin(hwmtx); } static __inline int uart_probe(struct uart_devinfo *di) { int res; uart_lock(di->hwmtx); res = di->ops->probe(&di->bas); uart_unlock(di->hwmtx); return (res); } static __inline void uart_init(struct uart_devinfo *di) { uart_lock(di->hwmtx); di->ops->init(&di->bas, di->baudrate, di->databits, di->stopbits, di->parity); uart_unlock(di->hwmtx); } static __inline void uart_term(struct uart_devinfo *di) { uart_lock(di->hwmtx); di->ops->term(&di->bas); uart_unlock(di->hwmtx); } static __inline void uart_putc(struct uart_devinfo *di, int c) { uart_lock(di->hwmtx); di->ops->putc(&di->bas, c); uart_unlock(di->hwmtx); } static __inline int uart_rxready(struct uart_devinfo *di) { int res; uart_lock(di->hwmtx); res = di->ops->rxready(&di->bas); uart_unlock(di->hwmtx); return (res); } static __inline int uart_poll(struct uart_devinfo *di) { int res; uart_lock(di->hwmtx); if (di->ops->rxready(&di->bas)) res = di->ops->getc(&di->bas, NULL); else res = -1; uart_unlock(di->hwmtx); return (res); } static __inline int uart_getc(struct uart_devinfo *di) { return (di->ops->getc(&di->bas, di->hwmtx)); } void uart_grab(struct uart_devinfo *di); void uart_ungrab(struct uart_devinfo *di); #endif /* _DEV_UART_CPU_H_ */ diff --git a/sys/dev/uart/uart_cpu_acpi.c b/sys/dev/uart/uart_cpu_acpi.c index 1e46462fc58a..68f743c8e8d2 100644 --- a/sys/dev/uart/uart_cpu_acpi.c +++ b/sys/dev/uart/uart_cpu_acpi.c @@ -1,199 +1,206 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2016 The FreeBSD Foundation * Copyright (c) 2019 Colin Percival * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include +#include + #include #include #include #include #include #include #include static struct acpi_uart_compat_data * uart_cpu_acpi_scan(uint8_t interface_type) { struct acpi_uart_compat_data **cd, *curcd; int i; SET_FOREACH(cd, uart_acpi_class_and_device_set) { curcd = *cd; for (i = 0; curcd[i].cd_hid != NULL; i++) { if (curcd[i].cd_port_subtype == interface_type) return (&curcd[i]); } } SET_FOREACH(cd, uart_acpi_class_set) { curcd = *cd; for (i = 0; curcd[i].cd_hid != NULL; i++) { if (curcd[i].cd_port_subtype == interface_type) return (&curcd[i]); } } return (NULL); } int uart_cpu_acpi_spcr(int devtype, struct uart_devinfo *di) { vm_paddr_t spcr_physaddr; ACPI_TABLE_SPCR *spcr; struct acpi_uart_compat_data *cd; struct uart_class *class; int error = ENXIO; /* SPCR only tells us about consoles. */ if (devtype != UART_DEV_CONSOLE) return (error); /* Look for the SPCR table. */ spcr_physaddr = acpi_find_table(ACPI_SIG_SPCR); if (spcr_physaddr == 0) return (error); spcr = acpi_map_table(spcr_physaddr, ACPI_SIG_SPCR); if (spcr == NULL) { printf("Unable to map the SPCR table!\n"); return (error); } /* Search for information about this SPCR interface type. */ cd = uart_cpu_acpi_scan(spcr->InterfaceType); if (cd == NULL) goto out; class = cd->cd_class; /* Fill in some fixed details. */ di->bas.chan = 0; di->bas.rclk = 0; di->databits = 8; di->stopbits = 1; di->parity = UART_PARITY_NONE; di->ops = uart_getops(class); /* Fill in details from SPCR table. */ switch (spcr->SerialPort.SpaceId) { case 0: di->bas.bst = uart_bus_space_mem; break; case 1: di->bas.bst = uart_bus_space_io; break; default: printf("UART in unrecognized address space: %d!\n", (int)spcr->SerialPort.SpaceId); goto out; } switch (spcr->SerialPort.AccessWidth) { case 0: /* EFI_ACPI_6_0_UNDEFINED */ /* FALLTHROUGH */ case 1: /* EFI_ACPI_6_0_BYTE */ di->bas.regiowidth = 1; break; case 2: /* EFI_ACPI_6_0_WORD */ di->bas.regiowidth = 2; break; case 3: /* EFI_ACPI_6_0_DWORD */ di->bas.regiowidth = 4; break; case 4: /* EFI_ACPI_6_0_QWORD */ di->bas.regiowidth = 8; break; default: printf("UART unsupported access width: %d!\n", (int)spcr->SerialPort.AccessWidth); goto out; } switch (spcr->SerialPort.BitWidth) { case 0: /* FALLTHROUGH */ case 8: di->bas.regshft = 0; break; case 16: di->bas.regshft = 1; break; case 32: di->bas.regshft = 2; break; case 64: di->bas.regshft = 3; break; default: printf("UART unsupported bit width: %d!\n", (int)spcr->SerialPort.BitWidth); goto out; } switch (spcr->BaudRate) { case 0: /* Special value; means "keep current value unchanged". */ di->baudrate = 0; break; case 3: di->baudrate = 9600; break; case 4: di->baudrate = 19200; break; case 6: di->baudrate = 57600; break; case 7: di->baudrate = 115200; break; default: printf("SPCR has reserved BaudRate value: %d!\n", (int)spcr->BaudRate); goto out; } + if (spcr->PciVendorId != PCIV_INVALID && + spcr->PciDeviceId != PCIV_INVALID) { + di->pci_info.vendor = spcr->PciVendorId; + di->pci_info.device = spcr->PciDeviceId; + } /* Apply device tweaks. */ if ((cd->cd_quirks & UART_F_IGNORE_SPCR_REGSHFT) == UART_F_IGNORE_SPCR_REGSHFT) { di->bas.regshft = cd->cd_regshft; } /* Create a bus space handle. */ error = bus_space_map(di->bas.bst, spcr->SerialPort.Address, uart_getrange(class), 0, &di->bas.bsh); out: acpi_unmap_table(spcr); return (error); }