diff --git a/sys/dev/rtwn/if_rtwn.c b/sys/dev/rtwn/if_rtwn.c index be01ececf307..3b286d9adba9 100644 --- a/sys/dev/rtwn/if_rtwn.c +++ b/sys/dev/rtwn/if_rtwn.c @@ -1,1976 +1,2006 @@ /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ /*- * Copyright (c) 2010 Damien Bergamini * Copyright (c) 2014 Kevin Lo * Copyright (c) 2015-2016 Andriy Voskoboinyk * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include /* * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU/RTL8812AU/RTL8821AU. */ #include "opt_wlan.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static void rtwn_radiotap_attach(struct rtwn_softc *); static void rtwn_vap_decrement_counters(struct rtwn_softc *, enum ieee80211_opmode, int); static void rtwn_set_ic_opmode(struct rtwn_softc *); static struct ieee80211vap *rtwn_vap_create(struct ieee80211com *, const char [IFNAMSIZ], int, enum ieee80211_opmode, int, const uint8_t [IEEE80211_ADDR_LEN], const uint8_t [IEEE80211_ADDR_LEN]); static void rtwn_vap_delete(struct ieee80211vap *); static int rtwn_read_chipid(struct rtwn_softc *); static int rtwn_ioctl_reset(struct ieee80211vap *, u_long); static void rtwn_set_media_status(struct rtwn_softc *, union sec_param *); #ifndef RTWN_WITHOUT_UCODE static int rtwn_tx_fwpkt_check(struct rtwn_softc *, struct ieee80211vap *); static int rtwn_construct_nulldata(struct rtwn_softc *, struct ieee80211vap *, uint8_t *, int); static int rtwn_push_nulldata(struct rtwn_softc *, struct ieee80211vap *); static void rtwn_pwrmode_init(void *); static void rtwn_set_pwrmode_cb(struct rtwn_softc *, union sec_param *); #endif static void rtwn_tsf_sync_adhoc(void *); static void rtwn_tsf_sync_adhoc_task(void *, int); static void rtwn_tsf_sync_enable(struct rtwn_softc *, struct ieee80211vap *); static void rtwn_set_ack_preamble(struct rtwn_softc *); static void rtwn_set_mode(struct rtwn_softc *, uint8_t, int); static int rtwn_monitor_newstate(struct ieee80211vap *, enum ieee80211_state, int); static int rtwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); static void rtwn_calc_basicrates(struct rtwn_softc *); static int rtwn_run(struct rtwn_softc *, struct ieee80211vap *); #ifndef D4054 static void rtwn_watchdog(void *); #endif static void rtwn_parent(struct ieee80211com *); static int rtwn_dma_init(struct rtwn_softc *); static int rtwn_mac_init(struct rtwn_softc *); static void rtwn_mrr_init(struct rtwn_softc *); static void rtwn_scan_start(struct ieee80211com *); static void rtwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); static void rtwn_scan_end(struct ieee80211com *); static void rtwn_getradiocaps(struct ieee80211com *, int, int *, struct ieee80211_channel[]); static void rtwn_update_chw(struct ieee80211com *); static void rtwn_set_channel(struct ieee80211com *); static int rtwn_wme_update(struct ieee80211com *); static void rtwn_update_slot(struct ieee80211com *); static void rtwn_update_slot_cb(struct rtwn_softc *, union sec_param *); static void rtwn_update_aifs(struct rtwn_softc *, uint8_t); static void rtwn_update_promisc(struct ieee80211com *); static void rtwn_update_mcast(struct ieee80211com *); static int rtwn_set_bssid(struct rtwn_softc *, const uint8_t *, int); static int rtwn_set_macaddr(struct rtwn_softc *, const uint8_t *, int); static struct ieee80211_node *rtwn_node_alloc(struct ieee80211vap *, const uint8_t mac[IEEE80211_ADDR_LEN]); static void rtwn_newassoc(struct ieee80211_node *, int); static void rtwn_node_free(struct ieee80211_node *); static void rtwn_init_beacon_reg(struct rtwn_softc *); static int rtwn_init(struct rtwn_softc *); static void rtwn_stop(struct rtwn_softc *); MALLOC_DEFINE(M_RTWN_PRIV, "rtwn_priv", "rtwn driver private state"); static const uint16_t wme2reg[] = { R92C_EDCA_BE_PARAM, R92C_EDCA_BK_PARAM, R92C_EDCA_VI_PARAM, R92C_EDCA_VO_PARAM }; int rtwn_attach(struct rtwn_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; int error; sc->cur_bcnq_id = RTWN_VAP_ID_INVALID; RTWN_NT_LOCK_INIT(sc); rtwn_cmdq_init(sc); #ifndef D4054 callout_init_mtx(&sc->sc_watchdog_to, &sc->sc_mtx, 0); #endif callout_init(&sc->sc_calib_to, 0); callout_init(&sc->sc_pwrmode_init, 0); mbufq_init(&sc->sc_snd, ifqmaxlen); RTWN_LOCK(sc); error = rtwn_read_chipid(sc); RTWN_UNLOCK(sc); if (error != 0) { device_printf(sc->sc_dev, "unsupported test chip\n"); goto detach; } error = rtwn_read_rom(sc); if (error != 0) { device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", __func__, error); goto detach; } if (sc->macid_limit > RTWN_MACID_LIMIT) { device_printf(sc->sc_dev, "macid limit will be reduced from %d to %d\n", sc->macid_limit, RTWN_MACID_LIMIT); sc->macid_limit = RTWN_MACID_LIMIT; } if (sc->cam_entry_limit > RTWN_CAM_ENTRY_LIMIT) { device_printf(sc->sc_dev, "cam entry limit will be reduced from %d to %d\n", sc->cam_entry_limit, RTWN_CAM_ENTRY_LIMIT); sc->cam_entry_limit = RTWN_CAM_ENTRY_LIMIT; } if (sc->txdesc_len > RTWN_TX_DESC_SIZE) { device_printf(sc->sc_dev, "adjust size for Tx descriptor (current %d, needed %d)\n", RTWN_TX_DESC_SIZE, sc->txdesc_len); goto detach; } device_printf(sc->sc_dev, "MAC/BB %s, RF 6052 %dT%dR\n", sc->name, sc->ntxchains, sc->nrxchains); ic->ic_softc = sc; ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ /* set device capabilities */ ic->ic_caps = IEEE80211_C_STA /* station mode */ | IEEE80211_C_MONITOR /* monitor mode */ | IEEE80211_C_IBSS /* adhoc mode */ | IEEE80211_C_HOSTAP /* hostap mode */ #if 0 /* TODO: HRPWM register setup */ #ifndef RTWN_WITHOUT_UCODE | IEEE80211_C_PMGT /* Station-side power mgmt */ #endif #endif | IEEE80211_C_SHPREAMBLE /* short preamble supported */ | IEEE80211_C_SHSLOT /* short slot time supported */ #if 0 | IEEE80211_C_BGSCAN /* capable of bg scanning */ #endif | IEEE80211_C_WPA /* 802.11i */ | IEEE80211_C_WME /* 802.11e */ | IEEE80211_C_SWAMSDUTX /* Do software A-MSDU TX */ | IEEE80211_C_FF /* Atheros fast-frames */ | IEEE80211_C_TXPMGT /* TX power control */ ; if (sc->sc_hwcrypto != RTWN_CRYPTO_SW) { ic->ic_cryptocaps = IEEE80211_CRYPTO_WEP | IEEE80211_CRYPTO_TKIP | IEEE80211_CRYPTO_AES_CCM; } ic->ic_htcaps = IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ | IEEE80211_HTCAP_SMPS_OFF /* SM PS mode disabled */ /* s/w capabilities */ | IEEE80211_HTC_HT /* HT operation */ | IEEE80211_HTC_RX_AMSDU_AMPDU /* A-MSDU in A-MPDU */ | IEEE80211_HTC_AMPDU /* A-MPDU tx */ | IEEE80211_HTC_AMSDU /* A-MSDU tx */ ; if (sc->sc_ht40) { ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40 /* 40 MHz channel width */ | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ ; } ic->ic_txstream = sc->ntxchains; ic->ic_rxstream = sc->nrxchains; /* Enable TX watchdog */ #ifdef D4054 ic->ic_flags_ext |= IEEE80211_FEXT_WATCHDOG; #endif /* Adjust capabilities. */ rtwn_adj_devcaps(sc); rtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, ic->ic_channels); /* XXX TODO: setup regdomain if R92C_CHANNEL_PLAN_BY_HW bit is set. */ ieee80211_ifattach(ic); ic->ic_raw_xmit = rtwn_raw_xmit; ic->ic_scan_start = rtwn_scan_start; sc->sc_scan_curchan = ic->ic_scan_curchan; ic->ic_scan_curchan = rtwn_scan_curchan; ic->ic_scan_end = rtwn_scan_end; ic->ic_getradiocaps = rtwn_getradiocaps; ic->ic_update_chw = rtwn_update_chw; ic->ic_set_channel = rtwn_set_channel; ic->ic_transmit = rtwn_transmit; ic->ic_parent = rtwn_parent; ic->ic_vap_create = rtwn_vap_create; ic->ic_vap_delete = rtwn_vap_delete; ic->ic_wme.wme_update = rtwn_wme_update; ic->ic_updateslot = rtwn_update_slot; ic->ic_update_promisc = rtwn_update_promisc; ic->ic_update_mcast = rtwn_update_mcast; ic->ic_node_alloc = rtwn_node_alloc; ic->ic_newassoc = rtwn_newassoc; sc->sc_node_free = ic->ic_node_free; ic->ic_node_free = rtwn_node_free; rtwn_postattach(sc); rtwn_radiotap_attach(sc); if (bootverbose) ieee80211_announce(ic); return (0); detach: return (ENXIO); /* failure */ } static void rtwn_radiotap_attach(struct rtwn_softc *sc) { struct rtwn_rx_radiotap_header *rxtap = &sc->sc_rxtap; struct rtwn_tx_radiotap_header *txtap = &sc->sc_txtap; ieee80211_radiotap_attach(&sc->sc_ic, &txtap->wt_ihdr, sizeof(*txtap), RTWN_TX_RADIOTAP_PRESENT, &rxtap->wr_ihdr, sizeof(*rxtap), RTWN_RX_RADIOTAP_PRESENT); } void rtwn_sysctlattach(struct rtwn_softc *sc) { struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); sc->sc_ht40 = 0; SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "ht40", CTLFLAG_RDTUN, &sc->sc_ht40, sc->sc_ht40, "Enable 40 MHz mode support"); sc->sc_ena_tsf64 = 0; SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "ena_tsf64", CTLFLAG_RWTUN, &sc->sc_ena_tsf64, sc->sc_ena_tsf64, "Enable/disable per-packet TSF64 reporting"); #ifdef RTWN_DEBUG SYSCTL_ADD_U32(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->sc_debug, sc->sc_debug, "Control debugging printfs"); #endif sc->sc_hwcrypto = RTWN_CRYPTO_PAIR; SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "hwcrypto", CTLFLAG_RDTUN, &sc->sc_hwcrypto, sc->sc_hwcrypto, "Enable h/w crypto: " "0 - disable, 1 - pairwise keys, 2 - all keys"); if (sc->sc_hwcrypto >= RTWN_CRYPTO_MAX) sc->sc_hwcrypto = RTWN_CRYPTO_FULL; sc->sc_ratectl_sysctl = RTWN_RATECTL_NET80211; SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "ratectl", CTLFLAG_RDTUN, &sc->sc_ratectl_sysctl, sc->sc_ratectl_sysctl, "Select rate control mechanism: " "0 - disabled, 1 - via net80211, 2 - via firmware"); if (sc->sc_ratectl_sysctl >= RTWN_RATECTL_MAX) sc->sc_ratectl_sysctl = RTWN_RATECTL_FW; sc->sc_ratectl = sc->sc_ratectl_sysctl; SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "ratectl_selected", CTLFLAG_RD, &sc->sc_ratectl, sc->sc_ratectl, "Currently selected rate control mechanism (by the driver)"); } void rtwn_detach(struct rtwn_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; if (ic->ic_softc == sc) { /* Stop command queue. */ RTWN_CMDQ_LOCK(sc); sc->sc_detached = 1; RTWN_CMDQ_UNLOCK(sc); ieee80211_draintask(ic, &sc->cmdq_task); ieee80211_ifdetach(ic); } rtwn_cmdq_destroy(sc); if (RTWN_NT_LOCK_INITIALIZED(sc)) RTWN_NT_LOCK_DESTROY(sc); } void rtwn_suspend(struct rtwn_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; ieee80211_suspend_all(ic); } void rtwn_resume(struct rtwn_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; ieee80211_resume_all(ic); } static void rtwn_vap_decrement_counters(struct rtwn_softc *sc, enum ieee80211_opmode opmode, int id) { RTWN_ASSERT_LOCKED(sc); if (id != RTWN_VAP_ID_INVALID) { KASSERT(id == 0 || id == 1, ("wrong vap id %d!\n", id)); KASSERT(sc->vaps[id] != NULL, ("vap pointer is NULL\n")); sc->vaps[id] = NULL; } switch (opmode) { case IEEE80211_M_HOSTAP: sc->ap_vaps--; /* FALLTHROUGH */ case IEEE80211_M_IBSS: sc->bcn_vaps--; /* FALLTHROUGH */ case IEEE80211_M_STA: sc->nvaps--; break; case IEEE80211_M_MONITOR: sc->mon_vaps--; break; default: KASSERT(0, ("wrong opmode %d\n", opmode)); break; } KASSERT(sc->vaps_running >= 0 && sc->monvaps_running >= 0, ("number of running vaps is negative (vaps %d, monvaps %d)\n", sc->vaps_running, sc->monvaps_running)); KASSERT(sc->vaps_running - sc->monvaps_running <= RTWN_PORT_COUNT, ("number of running vaps is too big (vaps %d, monvaps %d)\n", sc->vaps_running, sc->monvaps_running)); KASSERT(sc->nvaps >= 0 && sc->nvaps <= RTWN_PORT_COUNT, ("wrong value %d for nvaps\n", sc->nvaps)); KASSERT(sc->mon_vaps >= 0, ("mon_vaps is negative (%d)\n", sc->mon_vaps)); KASSERT(sc->bcn_vaps >= 0 && ((RTWN_CHIP_HAS_BCNQ1(sc) && sc->bcn_vaps <= RTWN_PORT_COUNT) || sc->bcn_vaps <= 1), ("bcn_vaps value %d is wrong\n", sc->bcn_vaps)); KASSERT(sc->ap_vaps >= 0 && ((RTWN_CHIP_HAS_BCNQ1(sc) && sc->ap_vaps <= RTWN_PORT_COUNT) || sc->ap_vaps <= 1), ("ap_vaps value %d is wrong\n", sc->ap_vaps)); } static void rtwn_set_ic_opmode(struct rtwn_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; RTWN_ASSERT_LOCKED(sc); /* for ieee80211_reset_erp() */ if (sc->bcn_vaps - sc->ap_vaps > 0) ic->ic_opmode = IEEE80211_M_IBSS; else if (sc->ap_vaps > 0) ic->ic_opmode = IEEE80211_M_HOSTAP; else if (sc->nvaps > 0) ic->ic_opmode = IEEE80211_M_STA; else ic->ic_opmode = IEEE80211_M_MONITOR; } static struct ieee80211vap * rtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, enum ieee80211_opmode opmode, int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], const uint8_t mac[IEEE80211_ADDR_LEN]) { struct rtwn_softc *sc = ic->ic_softc; struct rtwn_vap *uvp; struct ieee80211vap *vap; int id = RTWN_VAP_ID_INVALID; RTWN_LOCK(sc); KASSERT(sc->nvaps <= RTWN_PORT_COUNT, ("nvaps overflow (%d > %d)\n", sc->nvaps, RTWN_PORT_COUNT)); KASSERT(sc->ap_vaps <= RTWN_PORT_COUNT, ("ap_vaps overflow (%d > %d)\n", sc->ap_vaps, RTWN_PORT_COUNT)); KASSERT(sc->bcn_vaps <= RTWN_PORT_COUNT, ("bcn_vaps overflow (%d > %d)\n", sc->bcn_vaps, RTWN_PORT_COUNT)); if (opmode != IEEE80211_M_MONITOR) { switch (sc->nvaps) { case 0: id = 0; break; case 1: if (sc->vaps[1] == NULL) id = 1; else if (sc->vaps[0] == NULL) id = 0; KASSERT(id != RTWN_VAP_ID_INVALID, ("no free ports left\n")); break; case 2: default: goto fail; } if (opmode == IEEE80211_M_IBSS || opmode == IEEE80211_M_HOSTAP) { if ((sc->bcn_vaps == 1 && !RTWN_CHIP_HAS_BCNQ1(sc)) || sc->bcn_vaps == RTWN_PORT_COUNT) goto fail; } } switch (opmode) { case IEEE80211_M_HOSTAP: sc->ap_vaps++; /* FALLTHROUGH */ case IEEE80211_M_IBSS: sc->bcn_vaps++; /* FALLTHROUGH */ case IEEE80211_M_STA: sc->nvaps++; break; case IEEE80211_M_MONITOR: sc->mon_vaps++; break; default: KASSERT(0, ("unknown opmode %d\n", opmode)); goto fail; } RTWN_UNLOCK(sc); uvp = malloc(sizeof(struct rtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); uvp->id = id; if (id != RTWN_VAP_ID_INVALID) { RTWN_LOCK(sc); sc->vaps[id] = uvp; RTWN_UNLOCK(sc); } vap = &uvp->vap; /* enable s/w bmiss handling for sta mode */ if (ieee80211_vap_setup(ic, vap, name, unit, opmode, flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { /* out of memory */ free(uvp, M_80211_VAP); RTWN_LOCK(sc); rtwn_vap_decrement_counters(sc, opmode, id); RTWN_UNLOCK(sc); return (NULL); } rtwn_beacon_init(sc, &uvp->bcn_desc.txd[0], uvp->id); rtwn_vap_preattach(sc, vap); /* override state transition machine */ uvp->newstate = vap->iv_newstate; if (opmode == IEEE80211_M_MONITOR) vap->iv_newstate = rtwn_monitor_newstate; else vap->iv_newstate = rtwn_newstate; vap->iv_update_beacon = rtwn_update_beacon; vap->iv_reset = rtwn_ioctl_reset; vap->iv_key_alloc = rtwn_key_alloc; vap->iv_key_set = rtwn_key_set; vap->iv_key_delete = rtwn_key_delete; vap->iv_max_aid = sc->macid_limit; /* 802.11n parameters */ vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16; vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; vap->iv_ampdu_limit = IEEE80211_HTCAP_MAXRXAMPDU_64K; TIMEOUT_TASK_INIT(taskqueue_thread, &uvp->tx_beacon_csa, 0, rtwn_tx_beacon_csa, vap); if (opmode == IEEE80211_M_IBSS) { uvp->recv_mgmt = vap->iv_recv_mgmt; vap->iv_recv_mgmt = rtwn_adhoc_recv_mgmt; TASK_INIT(&uvp->tsf_sync_adhoc_task, 0, rtwn_tsf_sync_adhoc_task, vap); callout_init(&uvp->tsf_sync_adhoc, 0); } /* * NB: driver can select net80211 RA even when user requests * another mechanism. */ ieee80211_ratectl_init(vap); /* complete setup */ ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status, mac); RTWN_LOCK(sc); rtwn_set_ic_opmode(sc); if (sc->sc_flags & RTWN_RUNNING) { if (uvp->id != RTWN_VAP_ID_INVALID) rtwn_set_macaddr(sc, vap->iv_myaddr, uvp->id); rtwn_rxfilter_update(sc); } RTWN_UNLOCK(sc); return (vap); fail: RTWN_UNLOCK(sc); return (NULL); } static void rtwn_vap_delete(struct ieee80211vap *vap) { struct ieee80211com *ic = vap->iv_ic; struct rtwn_softc *sc = ic->ic_softc; struct rtwn_vap *uvp = RTWN_VAP(vap); int i; /* Put vap into INIT state + stop device if needed. */ ieee80211_stop(vap); for (i = 0; i < NET80211_IV_NSTATE_NUM; i++) ieee80211_draintask(ic, &vap->iv_nstate_task[i]); ieee80211_draintask(ic, &ic->ic_parent_task); RTWN_LOCK(sc); /* Cancel any unfinished Tx. */ rtwn_reset_lists(sc, vap); if (uvp->bcn_mbuf != NULL) m_freem(uvp->bcn_mbuf); rtwn_vap_decrement_counters(sc, vap->iv_opmode, uvp->id); rtwn_set_ic_opmode(sc); if (sc->sc_flags & RTWN_RUNNING) rtwn_rxfilter_update(sc); RTWN_UNLOCK(sc); if (vap->iv_opmode == IEEE80211_M_IBSS) { ieee80211_draintask(ic, &uvp->tsf_sync_adhoc_task); callout_drain(&uvp->tsf_sync_adhoc); } ieee80211_ratectl_deinit(vap); ieee80211_vap_detach(vap); free(uvp, M_80211_VAP); } static int rtwn_read_chipid(struct rtwn_softc *sc) { uint32_t reg; reg = rtwn_read_4(sc, R92C_SYS_CFG); if (reg & R92C_SYS_CFG_TRP_VAUX_EN) /* test chip */ return (EOPNOTSUPP); rtwn_read_chipid_vendor(sc, reg); return (0); } static int rtwn_ioctl_reset(struct ieee80211vap *vap, u_long cmd) { int error; switch (cmd) { #ifndef RTWN_WITHOUT_UCODE case IEEE80211_IOC_POWERSAVE: case IEEE80211_IOC_POWERSAVESLEEP: { struct rtwn_softc *sc = vap->iv_ic->ic_softc; struct rtwn_vap *uvp = RTWN_VAP(vap); if (vap->iv_opmode == IEEE80211_M_STA && uvp->id == 0) { RTWN_LOCK(sc); if (sc->sc_flags & RTWN_RUNNING) error = rtwn_set_pwrmode(sc, vap, 1); else error = 0; RTWN_UNLOCK(sc); if (error != 0) error = ENETRESET; } else error = EOPNOTSUPP; break; } #endif case IEEE80211_IOC_SHORTGI: case IEEE80211_IOC_RTSTHRESHOLD: case IEEE80211_IOC_PROTMODE: case IEEE80211_IOC_HTPROTMODE: case IEEE80211_IOC_LDPC: error = 0; break; case IEEE80211_IOC_TXPOWER: { struct rtwn_softc *sc = vap->iv_ic->ic_softc; RTWN_LOCK(sc); error = rtwn_set_tx_power(sc, vap); RTWN_UNLOCK(sc); } break; default: error = ENETRESET; break; } return (error); } static void rtwn_set_media_status(struct rtwn_softc *sc, union sec_param *data) { sc->sc_set_media_status(sc, data->macid); } #ifndef RTWN_WITHOUT_UCODE static int rtwn_tx_fwpkt_check(struct rtwn_softc *sc, struct ieee80211vap *vap) { int ntries, error; for (ntries = 0; ntries < 5; ntries++) { error = rtwn_push_nulldata(sc, vap); if (error == 0) break; } if (ntries == 5) { device_printf(sc->sc_dev, "%s: cannot push f/w frames into chip, error %d!\n", __func__, error); return (error); } return (0); } static int rtwn_construct_nulldata(struct rtwn_softc *sc, struct ieee80211vap *vap, uint8_t *ptr, int qos) { struct rtwn_vap *uvp = RTWN_VAP(vap); struct ieee80211com *ic = &sc->sc_ic; struct rtwn_tx_desc_common *txd; struct ieee80211_frame *wh; int pktlen; /* XXX obtain from net80211 */ wh = (struct ieee80211_frame *)(ptr + sc->txdesc_len); wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_DATA; wh->i_fc[1] = IEEE80211_FC1_DIR_TODS; IEEE80211_ADDR_COPY(wh->i_addr1, vap->iv_bss->ni_bssid); IEEE80211_ADDR_COPY(wh->i_addr2, vap->iv_myaddr); IEEE80211_ADDR_COPY(wh->i_addr3, vap->iv_bss->ni_macaddr); txd = (struct rtwn_tx_desc_common *)ptr; txd->offset = sc->txdesc_len; pktlen = sc->txdesc_len; if (qos) { struct ieee80211_qosframe *qwh; const int tid = WME_AC_TO_TID(WME_AC_BE); qwh = (struct ieee80211_qosframe *)wh; qwh->i_fc[0] |= IEEE80211_FC0_SUBTYPE_QOS_NULL; qwh->i_qos[0] = tid & IEEE80211_QOS_TID; txd->pktlen = htole16(sizeof(struct ieee80211_qosframe)); pktlen += sizeof(struct ieee80211_qosframe); } else { wh->i_fc[0] |= IEEE80211_FC0_SUBTYPE_NODATA; txd->pktlen = htole16(sizeof(struct ieee80211_frame)); pktlen += sizeof(struct ieee80211_frame); } rtwn_fill_tx_desc_null(sc, ptr, ic->ic_curmode == IEEE80211_MODE_11B, qos, uvp->id); return (pktlen); } static int rtwn_push_nulldata(struct rtwn_softc *sc, struct ieee80211vap *vap) { struct rtwn_vap *uvp = RTWN_VAP(vap); struct ieee80211com *ic = vap->iv_ic; struct ieee80211_channel *c = ic->ic_curchan; struct mbuf *m; uint8_t *ptr; int required_size, bcn_size, null_size, null_data, error; if (!(sc->sc_flags & RTWN_FW_LOADED)) return (0); /* requires firmware */ KASSERT(sc->page_size > 0, ("page size was not set!\n")); /* Leave some space for beacon (multi-vap) */ bcn_size = roundup(RTWN_BCN_MAX_SIZE, sc->page_size); /* 1 page for Null Data + 1 page for Qos Null Data frames. */ required_size = bcn_size + sc->page_size * 2; m = m_get2(required_size, M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOMEM); /* Setup beacon descriptor. */ rtwn_beacon_set_rate(sc, &uvp->bcn_desc.txd[0], IEEE80211_IS_CHAN_5GHZ(c)); ptr = mtod(m, uint8_t *); memset(ptr, 0, required_size - sc->txdesc_len); /* Construct Null Data frame. */ ptr += bcn_size - sc->txdesc_len; null_size = rtwn_construct_nulldata(sc, vap, ptr, 0); KASSERT(null_size < sc->page_size, ("recalculate size for Null Data frame\n")); /* Construct Qos Null Data frame. */ ptr += roundup(null_size, sc->page_size); null_size = rtwn_construct_nulldata(sc, vap, ptr, 1); KASSERT(null_size < sc->page_size, ("recalculate size for Qos Null Data frame\n")); /* Do not try to detect a beacon here. */ rtwn_setbits_1_shift(sc, R92C_CR, 0, R92C_CR_ENSWBCN, 1); rtwn_setbits_1_shift(sc, R92C_FWHW_TXQ_CTRL, R92C_FWHW_TXQ_CTRL_REAL_BEACON, 0, 2); if (uvp->bcn_mbuf != NULL) { rtwn_beacon_unload(sc, uvp->id); m_freem(uvp->bcn_mbuf); } m->m_pkthdr.len = m->m_len = required_size - sc->txdesc_len; uvp->bcn_mbuf = m; error = rtwn_tx_beacon_check(sc, uvp); if (error != 0) { RTWN_DPRINTF(sc, RTWN_DEBUG_BEACON, "%s: frame was not recognized!\n", __func__); goto fail; } /* Setup addresses in firmware. */ null_data = howmany(bcn_size, sc->page_size); error = rtwn_set_rsvd_page(sc, 0, null_data, null_data + 1); if (error != 0) { device_printf(sc->sc_dev, "%s: CMD_RSVD_PAGE was not sent, error %d\n", __func__, error); goto fail; } fail: /* Re-enable beacon detection. */ rtwn_setbits_1_shift(sc, R92C_FWHW_TXQ_CTRL, 0, R92C_FWHW_TXQ_CTRL_REAL_BEACON, 2); rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSWBCN, 0, 1); /* Restore beacon (if present). */ if (sc->bcn_vaps > 0 && sc->vaps[!uvp->id] != NULL) { struct rtwn_vap *uvp2 = sc->vaps[!uvp->id]; if (uvp2->curr_mode != R92C_MSR_NOLINK) error = rtwn_tx_beacon_check(sc, uvp2); } return (error); } static void rtwn_pwrmode_init(void *arg) { struct rtwn_softc *sc = arg; rtwn_cmd_sleepable(sc, NULL, 0, rtwn_set_pwrmode_cb); } static void rtwn_set_pwrmode_cb(struct rtwn_softc *sc, union sec_param *data) { struct ieee80211vap *vap = &sc->vaps[0]->vap; if (vap != NULL) rtwn_set_pwrmode(sc, vap, 1); } #endif static void rtwn_tsf_sync_adhoc(void *arg) { struct ieee80211vap *vap = arg; struct ieee80211com *ic = vap->iv_ic; struct rtwn_vap *uvp = RTWN_VAP(vap); if (uvp->curr_mode != R92C_MSR_NOLINK) { /* Do it in process context. */ ieee80211_runtask(ic, &uvp->tsf_sync_adhoc_task); } } /* * Workaround for TSF synchronization: * when BSSID filter in IBSS mode is not set * (and TSF synchronization is enabled), then any beacon may update it. * This routine synchronizes it when BSSID matching is enabled (IBSS merge * is not possible during this period). * * NOTE: there is no race with rtwn_newstate(), since it uses the same * taskqueue. */ static void rtwn_tsf_sync_adhoc_task(void *arg, int pending) { struct ieee80211vap *vap = arg; struct rtwn_vap *uvp = RTWN_VAP(vap); struct rtwn_softc *sc = vap->iv_ic->ic_softc; struct ieee80211_node *ni; RTWN_LOCK(sc); ni = ieee80211_ref_node(vap->iv_bss); /* Accept beacons with the same BSSID. */ rtwn_set_rx_bssid_all(sc, 0); /* Deny RCR updates. */ sc->sc_flags |= RTWN_RCR_LOCKED; /* Enable synchronization. */ rtwn_setbits_1(sc, R92C_BCN_CTRL(uvp->id), R92C_BCN_CTRL_DIS_TSF_UDT0, 0); /* Synchronize. */ rtwn_delay(sc, ni->ni_intval * 5 * 1000); /* Disable synchronization. */ rtwn_setbits_1(sc, R92C_BCN_CTRL(uvp->id), 0, R92C_BCN_CTRL_DIS_TSF_UDT0); /* Accept all beacons. */ sc->sc_flags &= ~RTWN_RCR_LOCKED; rtwn_set_rx_bssid_all(sc, 1); /* Schedule next TSF synchronization. */ callout_reset(&uvp->tsf_sync_adhoc, 60*hz, rtwn_tsf_sync_adhoc, vap); ieee80211_free_node(ni); RTWN_UNLOCK(sc); } static void rtwn_tsf_sync_enable(struct rtwn_softc *sc, struct ieee80211vap *vap) { struct ieee80211com *ic = &sc->sc_ic; struct rtwn_vap *uvp = RTWN_VAP(vap); /* Reset TSF. */ rtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RESET(uvp->id)); switch (vap->iv_opmode) { case IEEE80211_M_STA: /* Enable TSF synchronization. */ rtwn_setbits_1(sc, R92C_BCN_CTRL(uvp->id), R92C_BCN_CTRL_DIS_TSF_UDT0, 0); break; case IEEE80211_M_IBSS: ieee80211_runtask(ic, &uvp->tsf_sync_adhoc_task); /* FALLTHROUGH */ case IEEE80211_M_HOSTAP: /* Enable beaconing. */ rtwn_beacon_enable(sc, uvp->id, 1); break; default: device_printf(sc->sc_dev, "undefined opmode %d\n", vap->iv_opmode); return; } } static void rtwn_set_ack_preamble(struct rtwn_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; uint32_t reg; reg = rtwn_read_4(sc, R92C_WMAC_TRXPTCL_CTL); if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) reg |= R92C_WMAC_TRXPTCL_SHPRE; else reg &= ~R92C_WMAC_TRXPTCL_SHPRE; rtwn_write_4(sc, R92C_WMAC_TRXPTCL_CTL, reg); } static void rtwn_set_mode(struct rtwn_softc *sc, uint8_t mode, int id) { rtwn_setbits_1(sc, R92C_MSR, R92C_MSR_MASK << id * 2, mode << id * 2); if (sc->vaps[id] != NULL) sc->vaps[id]->curr_mode = mode; } static int rtwn_monitor_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) { struct ieee80211com *ic = vap->iv_ic; struct rtwn_softc *sc = ic->ic_softc; struct rtwn_vap *uvp = RTWN_VAP(vap); RTWN_DPRINTF(sc, RTWN_DEBUG_STATE, "%s -> %s\n", ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); if (vap->iv_state != nstate) { IEEE80211_UNLOCK(ic); RTWN_LOCK(sc); switch (nstate) { case IEEE80211_S_INIT: sc->vaps_running--; sc->monvaps_running--; if (sc->vaps_running == 0) { /* Turn link LED off. */ rtwn_set_led(sc, RTWN_LED_LINK, 0); } break; case IEEE80211_S_RUN: sc->vaps_running++; sc->monvaps_running++; if (sc->vaps_running == 1) { /* Turn link LED on. */ rtwn_set_led(sc, RTWN_LED_LINK, 1); } break; default: /* NOTREACHED */ break; } RTWN_UNLOCK(sc); IEEE80211_LOCK(ic); } return (uvp->newstate(vap, nstate, arg)); } static int rtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) { struct rtwn_vap *uvp = RTWN_VAP(vap); struct ieee80211com *ic = vap->iv_ic; struct rtwn_softc *sc = ic->ic_softc; enum ieee80211_state ostate; int error, early_newstate; ostate = vap->iv_state; RTWN_DPRINTF(sc, RTWN_DEBUG_STATE, "%s -> %s\n", ieee80211_state_name[ostate], ieee80211_state_name[nstate]); if (vap->iv_bss->ni_chan == IEEE80211_CHAN_ANYC && ostate == IEEE80211_S_INIT && nstate == IEEE80211_S_RUN) { /* need to call iv_newstate() firstly */ error = uvp->newstate(vap, nstate, arg); if (error != 0) return (error); early_newstate = 1; } else early_newstate = 0; if (ostate == IEEE80211_S_CSA) { taskqueue_cancel_timeout(taskqueue_thread, &uvp->tx_beacon_csa, NULL); /* * In multi-vap case second counter may not be cleared * properly. */ vap->iv_csa_count = 0; } IEEE80211_UNLOCK(ic); RTWN_LOCK(sc); if (ostate == IEEE80211_S_CSA) { /* Unblock all queues (multi-vap case). */ rtwn_write_1(sc, R92C_TXPAUSE, 0); } if ((ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_CSA) || ostate == IEEE80211_S_CSA) { sc->vaps_running--; /* Set media status to 'No Link'. */ rtwn_set_mode(sc, R92C_MSR_NOLINK, uvp->id); if (vap->iv_opmode == IEEE80211_M_IBSS) { /* Stop periodical TSF synchronization. */ callout_stop(&uvp->tsf_sync_adhoc); } /* Disable TSF synchronization / beaconing. */ rtwn_beacon_enable(sc, uvp->id, 0); rtwn_setbits_1(sc, R92C_BCN_CTRL(uvp->id), 0, R92C_BCN_CTRL_DIS_TSF_UDT0); /* NB: monitor mode vaps are using port 0. */ if (uvp->id != 0 || sc->monvaps_running == 0) { /* Reset TSF. */ rtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RESET(uvp->id)); } #ifndef RTWN_WITHOUT_UCODE if ((ic->ic_caps & IEEE80211_C_PMGT) != 0 && uvp->id == 0) { /* Disable power management. */ callout_stop(&sc->sc_pwrmode_init); rtwn_set_pwrmode(sc, vap, 0); } #endif if (sc->vaps_running - sc->monvaps_running > 0) { /* Recalculate basic rates bitmap. */ rtwn_calc_basicrates(sc); } if (sc->vaps_running == sc->monvaps_running) { /* Stop calibration. */ callout_stop(&sc->sc_calib_to); /* Stop Rx of data frames. */ rtwn_write_2(sc, R92C_RXFLTMAP2, 0); /* Reset EDCA parameters. */ rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); if (sc->vaps_running == 0) { /* Turn link LED off. */ rtwn_set_led(sc, RTWN_LED_LINK, 0); } } } error = 0; switch (nstate) { case IEEE80211_S_SCAN: /* Pause AC Tx queues. */ if (sc->vaps_running == 0) rtwn_setbits_1(sc, R92C_TXPAUSE, 0, R92C_TX_QUEUE_AC); break; case IEEE80211_S_RUN: error = rtwn_run(sc, vap); if (error != 0) { device_printf(sc->sc_dev, "%s: could not move to RUN state\n", __func__); break; } sc->vaps_running++; break; case IEEE80211_S_CSA: /* Block all Tx queues (except beacon queue). */ rtwn_setbits_1(sc, R92C_TXPAUSE, 0, R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | R92C_TX_QUEUE_HIGH); break; default: break; } RTWN_UNLOCK(sc); IEEE80211_LOCK(ic); if (error != 0) return (error); return (early_newstate ? 0 : uvp->newstate(vap, nstate, arg)); } static void rtwn_calc_basicrates(struct rtwn_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; uint32_t basicrates; int i; RTWN_ASSERT_LOCKED(sc); if (ic->ic_flags & IEEE80211_F_SCAN) return; /* will be done by rtwn_scan_end(). */ basicrates = 0; for (i = 0; i < nitems(sc->vaps); i++) { struct rtwn_vap *rvp; struct ieee80211vap *vap; struct ieee80211_node *ni; - uint32_t rates; + struct ieee80211_htrateset *rs_ht; + uint32_t rates = 0, htrates = 0; rvp = sc->vaps[i]; if (rvp == NULL || rvp->curr_mode == R92C_MSR_NOLINK) continue; vap = &rvp->vap; if (vap->iv_bss == NULL) continue; ni = ieee80211_ref_node(vap->iv_bss); - /* Only fetches basic rates; no need to add HT/VHT here */ - rtwn_get_rates(sc, &ni->ni_rates, NULL, &rates, NULL, NULL, 1); + if (ni->ni_flags & IEEE80211_NODE_HT) + rs_ht = &ni->ni_htrates; + else + rs_ht = NULL; + /* + * Only fetches basic rates; fetch 802.11abg and 11n basic + * rates + */ + rtwn_get_rates(sc, &ni->ni_rates, rs_ht, &rates, &htrates, + NULL, 1); + + /* + * We need at least /an/ OFDM and/or MCS rate for HT + * operation, or the MAC will generate MCS7 ACK/Block-ACK + * frames and thus performance will suffer. + */ + if (ni->ni_flags & IEEE80211_NODE_HT) { + htrates |= 0x01; /* MCS0 */ + rates |= (1 << RTWN_RIDX_OFDM6); + } + basicrates |= rates; + basicrates |= (htrates << RTWN_RIDX_HT_MCS_SHIFT); + + /* Filter out undesired high rates */ + if (ni->ni_chan != IEEE80211_CHAN_ANYC && + IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) + basicrates &= R92C_RRSR_RATE_MASK_5GHZ; + else + basicrates &= R92C_RRSR_RATE_MASK_2GHZ; + ieee80211_free_node(ni); } + if (basicrates == 0) return; - /* XXX initial RTS rate? */ + /* XXX also set initial RTS rate? */ rtwn_set_basicrates(sc, basicrates); } static int rtwn_run(struct rtwn_softc *sc, struct ieee80211vap *vap) { struct ieee80211com *ic = vap->iv_ic; struct rtwn_vap *uvp = RTWN_VAP(vap); struct ieee80211_node *ni; uint8_t mode; int error; RTWN_ASSERT_LOCKED(sc); error = 0; ni = ieee80211_ref_node(vap->iv_bss); if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || ni->ni_chan == IEEE80211_CHAN_ANYC) { error = EINVAL; goto fail; } switch (vap->iv_opmode) { case IEEE80211_M_STA: mode = R92C_MSR_INFRA; break; case IEEE80211_M_IBSS: mode = R92C_MSR_ADHOC; break; case IEEE80211_M_HOSTAP: mode = R92C_MSR_AP; break; default: KASSERT(0, ("undefined opmode %d\n", vap->iv_opmode)); error = EINVAL; goto fail; } /* Set media status to 'Associated'. */ rtwn_set_mode(sc, mode, uvp->id); /* Set AssocID. */ /* XXX multi-vap? */ rtwn_write_2(sc, R92C_BCN_PSR_RPT, 0xc000 | IEEE80211_NODE_AID(ni)); /* Set BSSID. */ rtwn_set_bssid(sc, ni->ni_bssid, uvp->id); /* Set beacon interval. */ rtwn_write_2(sc, R92C_BCN_INTERVAL(uvp->id), ni->ni_intval); if (sc->vaps_running == sc->monvaps_running) { /* Enable Rx of data frames. */ rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); /* Flush all AC queues. */ rtwn_write_1(sc, R92C_TXPAUSE, 0); } #ifndef RTWN_WITHOUT_UCODE /* Upload (QoS) Null Data frame to firmware. */ /* Note: do this for port 0 only. */ if ((ic->ic_caps & IEEE80211_C_PMGT) != 0 && vap->iv_opmode == IEEE80211_M_STA && uvp->id == 0) { error = rtwn_tx_fwpkt_check(sc, vap); if (error != 0) goto fail; /* Setup power management. */ /* * NB: it will be enabled immediately - delay it, * so 4-Way handshake will not be interrupted. */ callout_reset(&sc->sc_pwrmode_init, 5*hz, rtwn_pwrmode_init, sc); } #endif /* Enable TSF synchronization. */ rtwn_tsf_sync_enable(sc, vap); if (vap->iv_opmode == IEEE80211_M_HOSTAP || vap->iv_opmode == IEEE80211_M_IBSS) { error = rtwn_setup_beacon(sc, ni); if (error != 0) { device_printf(sc->sc_dev, "unable to push beacon into the chip, " "error %d\n", error); goto fail; } } /* Set ACK preamble type. */ rtwn_set_ack_preamble(sc); /* Set basic rates mask. */ rtwn_calc_basicrates(sc); #ifdef RTWN_TODO rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); #endif if (sc->vaps_running == sc->monvaps_running) { /* Reset temperature calibration state machine. */ sc->sc_flags &= ~RTWN_TEMP_MEASURED; sc->thcal_temp = sc->thermal_meter; /* Start periodic calibration. */ callout_reset(&sc->sc_calib_to, 2*hz, rtwn_calib_to, sc); if (sc->vaps_running == 0) { /* Turn link LED on. */ rtwn_set_led(sc, RTWN_LED_LINK, 1); } } fail: ieee80211_free_node(ni); return (error); } #ifndef D4054 static void rtwn_watchdog(void *arg) { struct rtwn_softc *sc = arg; struct ieee80211com *ic = &sc->sc_ic; RTWN_ASSERT_LOCKED(sc); KASSERT(sc->sc_flags & RTWN_RUNNING, ("not running")); if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { ic_printf(ic, "device timeout\n"); ieee80211_restart_all(ic); return; } callout_reset(&sc->sc_watchdog_to, hz, rtwn_watchdog, sc); } #endif static void rtwn_parent(struct ieee80211com *ic) { struct rtwn_softc *sc = ic->ic_softc; struct ieee80211vap *vap; if (ic->ic_nrunning > 0) { if (rtwn_init(sc) != 0) { IEEE80211_LOCK(ic); TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) ieee80211_stop_locked(vap); IEEE80211_UNLOCK(ic); } else ieee80211_start_all(ic); } else rtwn_stop(sc); } static int rtwn_dma_init(struct rtwn_softc *sc) { #define RTWN_CHK(res) do { \ if (res != 0) \ return (EIO); \ } while(0) uint16_t reg; uint8_t tx_boundary; int error; /* Initialize LLT table. */ error = rtwn_llt_init(sc); if (error != 0) return (error); /* Set the number of pages for each queue. */ RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, "%s: pages per queue: high %d, normal %d, low %d, public %d\n", __func__, sc->nhqpages, sc->nnqpages, sc->nlqpages, sc->npubqpages); RTWN_CHK(rtwn_write_1(sc, R92C_RQPN_NPQ, sc->nnqpages)); RTWN_CHK(rtwn_write_4(sc, R92C_RQPN, /* Set number of pages for public queue. */ SM(R92C_RQPN_PUBQ, sc->npubqpages) | /* Set number of pages for high priority queue. */ SM(R92C_RQPN_HPQ, sc->nhqpages) | /* Set number of pages for low priority queue. */ SM(R92C_RQPN_LPQ, sc->nlqpages) | /* Load values. */ R92C_RQPN_LD)); /* Initialize TX buffer boundary. */ KASSERT(sc->page_count < 255 && sc->page_count > 0, ("page_count is %d\n", sc->page_count)); tx_boundary = sc->page_count + 1; RTWN_CHK(rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary)); RTWN_CHK(rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary)); RTWN_CHK(rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary)); RTWN_CHK(rtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary)); RTWN_CHK(rtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary)); error = rtwn_init_bcnq1_boundary(sc); if (error != 0) return (error); /* Set queue to USB pipe mapping. */ /* Note: PCIe devices are using some magic number here. */ reg = rtwn_get_qmap(sc); RTWN_CHK(rtwn_setbits_2(sc, R92C_TRXDMA_CTRL, R92C_TRXDMA_CTRL_QMAP_M, reg)); /* Configure Tx/Rx DMA (PCIe). */ rtwn_set_desc_addr(sc); /* Set Tx/Rx transfer page boundary. */ RTWN_CHK(rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, sc->rx_dma_size - 1)); /* Set Tx/Rx transfer page size. */ rtwn_set_page_size(sc); return (0); } static int rtwn_mac_init(struct rtwn_softc *sc) { int i, error; /* Write MAC initialization values. */ for (i = 0; i < sc->mac_size; i++) { error = rtwn_write_1(sc, sc->mac_prog[i].reg, sc->mac_prog[i].val); if (error != 0) return (error); } return (0); } static void rtwn_mrr_init(struct rtwn_softc *sc) { int i; /* Drop rate index by 1 per retry. */ for (i = 0; i < R92C_DARFRC_SIZE; i++) { rtwn_write_1(sc, R92C_DARFRC + i, i + 1); rtwn_write_1(sc, R92C_RARFRC + i, i + 1); } } static void rtwn_scan_start(struct ieee80211com *ic) { struct rtwn_softc *sc = ic->ic_softc; RTWN_LOCK(sc); /* Pause beaconing. */ rtwn_setbits_1(sc, R92C_TXPAUSE, 0, R92C_TX_QUEUE_BCN); /* Receive beacons / probe responses from any BSSID. */ if (sc->bcn_vaps == 0) rtwn_set_rx_bssid_all(sc, 1); RTWN_UNLOCK(sc); } static void rtwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) { struct rtwn_softc *sc = ss->ss_ic->ic_softc; /* Make link LED blink during scan. */ RTWN_LOCK(sc); rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); RTWN_UNLOCK(sc); sc->sc_scan_curchan(ss, maxdwell); } static void rtwn_scan_end(struct ieee80211com *ic) { struct rtwn_softc *sc = ic->ic_softc; RTWN_LOCK(sc); /* Restore limitations. */ if (ic->ic_promisc == 0 && sc->bcn_vaps == 0) rtwn_set_rx_bssid_all(sc, 0); /* Restore LED state. */ rtwn_set_led(sc, RTWN_LED_LINK, (sc->vaps_running != 0)); /* Restore basic rates mask. */ rtwn_calc_basicrates(sc); /* Resume beaconing. */ rtwn_setbits_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_BCN, 0); RTWN_UNLOCK(sc); } static void rtwn_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, struct ieee80211_channel chans[]) { struct rtwn_softc *sc = ic->ic_softc; uint8_t bands[IEEE80211_MODE_BYTES]; int cbw_flags, i; cbw_flags = (ic->ic_htcaps & IEEE80211_HTCAP_CHWIDTH40) ? NET80211_CBW_FLAG_HT40 : 0; memset(bands, 0, sizeof(bands)); setbit(bands, IEEE80211_MODE_11B); setbit(bands, IEEE80211_MODE_11G); setbit(bands, IEEE80211_MODE_11NG); ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, cbw_flags); /* XXX workaround add_channel_list() limitations */ setbit(bands, IEEE80211_MODE_11A); setbit(bands, IEEE80211_MODE_11NA); for (i = 0; i < nitems(sc->chan_num_5ghz); i++) { if (sc->chan_num_5ghz[i] == 0) continue; ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, sc->chan_list_5ghz[i], sc->chan_num_5ghz[i], bands, cbw_flags); } } static void rtwn_update_chw(struct ieee80211com *ic) { } static void rtwn_set_channel(struct ieee80211com *ic) { struct rtwn_softc *sc = ic->ic_softc; struct ieee80211_channel *c = ic->ic_curchan; RTWN_LOCK(sc); rtwn_set_chan(sc, c); RTWN_UNLOCK(sc); } static int rtwn_wme_update(struct ieee80211com *ic) { struct chanAccParams chp; struct ieee80211_channel *c = ic->ic_curchan; struct rtwn_softc *sc = ic->ic_softc; struct wmeParams *wmep = sc->cap_wmeParams; uint8_t aifs, acm, slottime; int ac; ieee80211_wme_ic_getparams(ic, &chp); /* Prevent possible races. */ IEEE80211_LOCK(ic); /* XXX */ RTWN_LOCK(sc); memcpy(wmep, chp.cap_wmeParams, sizeof(sc->cap_wmeParams)); RTWN_UNLOCK(sc); IEEE80211_UNLOCK(ic); acm = 0; slottime = IEEE80211_GET_SLOTTIME(ic); RTWN_LOCK(sc); for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ aifs = wmep[ac].wmep_aifsn * slottime + (IEEE80211_IS_CHAN_5GHZ(c) ? IEEE80211_DUR_OFDM_SIFS : IEEE80211_DUR_SIFS); rtwn_write_4(sc, wme2reg[ac], SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | SM(R92C_EDCA_PARAM_AIFS, aifs)); if (ac != WME_AC_BE) acm |= wmep[ac].wmep_acm << ac; } if (acm != 0) acm |= R92C_ACMHWCTRL_EN; rtwn_setbits_1(sc, R92C_ACMHWCTRL, R92C_ACMHWCTRL_ACM_MASK, acm); RTWN_UNLOCK(sc); return 0; } static void rtwn_update_slot(struct ieee80211com *ic) { rtwn_cmd_sleepable(ic->ic_softc, NULL, 0, rtwn_update_slot_cb); } static void rtwn_update_slot_cb(struct rtwn_softc *sc, union sec_param *data) { struct ieee80211com *ic = &sc->sc_ic; uint8_t slottime; slottime = IEEE80211_GET_SLOTTIME(ic); RTWN_DPRINTF(sc, RTWN_DEBUG_STATE, "%s: setting slot time to %uus\n", __func__, slottime); rtwn_write_1(sc, R92C_SLOT, slottime); rtwn_update_aifs(sc, slottime); } static void rtwn_update_aifs(struct rtwn_softc *sc, uint8_t slottime) { struct ieee80211_channel *c = sc->sc_ic.ic_curchan; const struct wmeParams *wmep = sc->cap_wmeParams; uint8_t aifs, ac; for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ aifs = wmep[ac].wmep_aifsn * slottime + (IEEE80211_IS_CHAN_5GHZ(c) ? IEEE80211_DUR_OFDM_SIFS : IEEE80211_DUR_SIFS); rtwn_write_1(sc, wme2reg[ac], aifs); } } static void rtwn_update_promisc(struct ieee80211com *ic) { struct rtwn_softc *sc = ic->ic_softc; RTWN_LOCK(sc); if (sc->sc_flags & RTWN_RUNNING) rtwn_set_promisc(sc); RTWN_UNLOCK(sc); } static void rtwn_update_mcast(struct ieee80211com *ic) { struct rtwn_softc *sc = ic->ic_softc; RTWN_LOCK(sc); if (sc->sc_flags & RTWN_RUNNING) rtwn_set_multi(sc); RTWN_UNLOCK(sc); } static int rtwn_set_bssid(struct rtwn_softc *sc, const uint8_t *bssid, int id) { int error; error = rtwn_write_4(sc, R92C_BSSID(id), le32dec(&bssid[0])); if (error != 0) return (error); error = rtwn_write_2(sc, R92C_BSSID(id) + 4, le16dec(&bssid[4])); return (error); } static int rtwn_set_macaddr(struct rtwn_softc *sc, const uint8_t *addr, int id) { int error; error = rtwn_write_4(sc, R92C_MACID(id), le32dec(&addr[0])); if (error != 0) return (error); error = rtwn_write_2(sc, R92C_MACID(id) + 4, le16dec(&addr[4])); return (error); } static struct ieee80211_node * rtwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) { struct rtwn_node *un; un = malloc(sizeof (struct rtwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); if (un == NULL) return NULL; un->id = RTWN_MACID_UNDEFINED; un->avg_pwdb = -1; return &un->ni; } static void rtwn_newassoc(struct ieee80211_node *ni, int isnew __unused) { struct rtwn_softc *sc = ni->ni_ic->ic_softc; struct rtwn_node *un = RTWN_NODE(ni); int id; if (un->id != RTWN_MACID_UNDEFINED) return; RTWN_NT_LOCK(sc); for (id = 0; id <= sc->macid_limit; id++) { if (id != RTWN_MACID_BC && sc->node_list[id] == NULL) { un->id = id; sc->node_list[id] = ni; break; } } RTWN_NT_UNLOCK(sc); if (id > sc->macid_limit) { device_printf(sc->sc_dev, "%s: node table is full\n", __func__); return; } /* Notify firmware. */ id |= RTWN_MACID_VALID; rtwn_cmd_sleepable(sc, &id, sizeof(id), rtwn_set_media_status); } static void rtwn_node_free(struct ieee80211_node *ni) { struct rtwn_softc *sc = ni->ni_ic->ic_softc; struct rtwn_node *un = RTWN_NODE(ni); RTWN_NT_LOCK(sc); if (un->id != RTWN_MACID_UNDEFINED) { sc->node_list[un->id] = NULL; rtwn_cmd_sleepable(sc, &un->id, sizeof(un->id), rtwn_set_media_status); } RTWN_NT_UNLOCK(sc); sc->sc_node_free(ni); } static void rtwn_init_beacon_reg(struct rtwn_softc *sc) { rtwn_write_1(sc, R92C_BCN_CTRL(0), R92C_BCN_CTRL_DIS_TSF_UDT0); rtwn_write_1(sc, R92C_BCN_CTRL(1), R92C_BCN_CTRL_DIS_TSF_UDT0); rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); } static int rtwn_init(struct rtwn_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; int i, error; RTWN_LOCK(sc); if (sc->sc_flags & RTWN_RUNNING) { RTWN_UNLOCK(sc); return (0); } sc->sc_flags |= RTWN_STARTED; /* Power on adapter. */ error = rtwn_power_on(sc); if (error != 0) goto fail; #ifndef RTWN_WITHOUT_UCODE /* Load 8051 microcode. */ error = rtwn_load_firmware(sc); if (error == 0) sc->sc_flags |= RTWN_FW_LOADED; /* Init firmware commands ring. */ sc->fwcur = 0; #endif /* Initialize MAC block. */ error = rtwn_mac_init(sc); if (error != 0) { device_printf(sc->sc_dev, "%s: error while initializing MAC block\n", __func__); goto fail; } /* Initialize DMA. */ error = rtwn_dma_init(sc); if (error != 0) goto fail; /* Drop incorrect TX (USB). */ rtwn_drop_incorrect_tx(sc); /* Set info size in Rx descriptors (in 64-bit words). */ rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, R92C_RX_DRVINFO_SZ_DEF); /* Init interrupts. */ rtwn_init_intr(sc); for (i = 0; i < nitems(sc->vaps); i++) { struct rtwn_vap *uvp = sc->vaps[i]; /* Set initial network type. */ rtwn_set_mode(sc, R92C_MSR_NOLINK, i); if (uvp == NULL) continue; /* Set MAC address. */ error = rtwn_set_macaddr(sc, uvp->vap.iv_myaddr, uvp->id); if (error != 0) goto fail; } /* Initialize Rx filter. */ rtwn_rxfilter_init(sc); /* Set short/long retry limits. */ rtwn_write_2(sc, R92C_RL, SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); /* Initialize EDCA parameters. */ rtwn_init_edca(sc); rtwn_setbits_1(sc, R92C_FWHW_TXQ_CTRL, 0, R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); /* Set ACK timeout. */ rtwn_write_1(sc, R92C_ACKTO, sc->ackto); /* Setup aggregation. */ /* Tx aggregation. */ rtwn_init_tx_agg(sc); rtwn_init_rx_agg(sc); /* Initialize beacon parameters. */ rtwn_init_beacon_reg(sc); /* Init A-MPDU parameters. */ rtwn_init_ampdu(sc); /* Init MACTXEN / MACRXEN after setting RxFF boundary. */ rtwn_setbits_1(sc, R92C_CR, 0, R92C_CR_MACTXEN | R92C_CR_MACRXEN); /* Initialize BB/RF blocks. */ rtwn_init_bb(sc); rtwn_init_rf(sc); /* Initialize wireless band. */ rtwn_set_chan(sc, ic->ic_curchan); /* Clear per-station keys table. */ rtwn_init_cam(sc); /* Enable decryption / encryption. */ rtwn_init_seccfg(sc); /* Install static keys (if any). */ for (i = 0; i < nitems(sc->vaps); i++) { if (sc->vaps[i] != NULL) { error = rtwn_init_static_keys(sc, sc->vaps[i]); if (error != 0) goto fail; } } /* Initialize antenna selection. */ rtwn_init_antsel(sc); /* Enable hardware sequence numbering. */ rtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); /* Disable BAR. */ rtwn_write_4(sc, R92C_BAR_MODE_CTRL, 0x0201ffff); /* NAV limit. */ rtwn_write_1(sc, R92C_NAV_UPPER, 0); /* Initialize GPIO setting. */ rtwn_setbits_1(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENBT, 0); /* Initialize MRR. */ rtwn_mrr_init(sc); /* Device-specific post initialization. */ rtwn_post_init(sc); rtwn_start_xfers(sc); #ifndef D4054 callout_reset(&sc->sc_watchdog_to, hz, rtwn_watchdog, sc); #endif sc->sc_flags |= RTWN_RUNNING; fail: RTWN_UNLOCK(sc); return (error); } static void rtwn_stop(struct rtwn_softc *sc) { RTWN_LOCK(sc); if (!(sc->sc_flags & RTWN_STARTED)) { RTWN_UNLOCK(sc); return; } #ifndef D4054 callout_stop(&sc->sc_watchdog_to); sc->sc_tx_timer = 0; #endif sc->sc_flags &= ~(RTWN_STARTED | RTWN_RUNNING | RTWN_FW_LOADED); sc->sc_flags &= ~RTWN_TEMP_MEASURED; sc->fwver = 0; sc->thcal_temp = 0; sc->cur_bcnq_id = RTWN_VAP_ID_INVALID; bzero(&sc->last_physt, sizeof(sc->last_physt)); #ifdef D4054 ieee80211_tx_watchdog_stop(&sc->sc_ic); #endif rtwn_abort_xfers(sc); rtwn_drain_mbufq(sc); rtwn_power_off(sc); rtwn_reset_lists(sc, NULL); RTWN_UNLOCK(sc); } MODULE_VERSION(rtwn, 2); MODULE_DEPEND(rtwn, wlan, 1, 1, 1); #ifndef RTWN_WITHOUT_UCODE MODULE_DEPEND(rtwn, firmware, 1, 1, 1); #endif diff --git a/sys/dev/rtwn/if_rtwn_rx.c b/sys/dev/rtwn/if_rtwn_rx.c index 977c1d17a08a..b1465dd80ee7 100644 --- a/sys/dev/rtwn/if_rtwn_rx.c +++ b/sys/dev/rtwn/if_rtwn_rx.c @@ -1,547 +1,555 @@ /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ /*- * Copyright (c) 2010 Damien Bergamini * Copyright (c) 2014 Kevin Lo * Copyright (c) 2015-2016 Andriy Voskoboinyk * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include #include "opt_wlan.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* * Get the driver rate set for the current operating rateset(s). * * rates_p is set to a mask of 11abg ridx values (not HW rate values.) * htrates_p is set to a mask of 11n ridx values (not HW rate values), * starting at MCS0 == bit 0. * * maxrate_p is set to the ridx value. * * If basic_rates is 1 then only the 11abg basic rate logic will - * be applied; HT/VHT will be ignored. + * be applied; the HT rateset will be applied to 11n rates. */ void rtwn_get_rates(struct rtwn_softc *sc, const struct ieee80211_rateset *rs, const struct ieee80211_htrateset *rs_ht, uint32_t *rates_p, uint32_t *htrates_p, int *maxrate_p, int basic_rates) { uint32_t rates = 0, htrates = 0; uint8_t ridx; int i, maxrate; /* Get rates mask. */ rates = 0; maxrate = 0; /* This is for 11abg */ for (i = 0; i < rs->rs_nrates; i++) { /* Convert 802.11 rate to HW rate index. */ ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i])); if (ridx == RTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */ continue; if (((rs->rs_rates[i] & IEEE80211_RATE_BASIC) != 0) || !basic_rates) { rates |= 1 << ridx; if (ridx > maxrate) maxrate = ridx; } } /* If we're doing 11n, enable 11n rates */ - if (rs_ht != NULL && !basic_rates) { + if (rs_ht != NULL) { for (i = 0; i < rs_ht->rs_nrates; i++) { + uint8_t rate = rs_ht->rs_rates[i] & 0x7f; + bool is_basic = rs_ht->rs_rates[i] & + IEEE80211_RATE_BASIC; /* Only do up to 2-stream rates for now */ - if ((rs_ht->rs_rates[i] & 0x7f) > 0xf) + if ((rate) > 0xf) continue; - ridx = rs_ht->rs_rates[i] & 0xf; + + if (basic_rates && is_basic == false) + continue; + + ridx = rate & 0xf; htrates |= (1 << ridx); /* Guard against the rate table being oddly ordered */ if (RTWN_RIDX_HT_MCS(ridx) > maxrate) maxrate = RTWN_RIDX_HT_MCS(ridx); } } RTWN_DPRINTF(sc, RTWN_DEBUG_RA, - "%s: rates 0x%08X, maxrate %d\n", __func__, rates, maxrate); + "%s: rates 0x%08X htrates 0x%08X, maxrate %d\n", + __func__, rates, htrates, maxrate); if (rates_p != NULL) *rates_p = rates; if (htrates_p != NULL) *htrates_p = htrates; if (maxrate_p != NULL) *maxrate_p = maxrate; } void rtwn_set_basicrates(struct rtwn_softc *sc, uint32_t rates) { RTWN_DPRINTF(sc, RTWN_DEBUG_RA, "%s: rates 0x%08X\n", __func__, rates); rtwn_setbits_4(sc, R92C_RRSR, R92C_RRSR_RATE_BITMAP_M, rates); } static void rtwn_update_avgrssi(struct rtwn_softc *sc, struct rtwn_node *un, int8_t rssi, int is_cck) { int pwdb; /* Convert antenna signal to percentage. */ if (rssi <= -100 || rssi >= 20) pwdb = 0; else if (rssi >= 0) pwdb = 100; else pwdb = 100 + rssi; if (is_cck) { /* CCK gain is smaller than OFDM/MCS gain. */ pwdb += 6; if (pwdb > 100) pwdb = 100; if (pwdb <= 14) pwdb -= 4; else if (pwdb <= 26) pwdb -= 8; else if (pwdb <= 34) pwdb -= 6; else if (pwdb <= 42) pwdb -= 2; } if (un->avg_pwdb == -1) /* Init. */ un->avg_pwdb = pwdb; else if (un->avg_pwdb < pwdb) un->avg_pwdb = ((un->avg_pwdb * 19 + pwdb) / 20) + 1; else un->avg_pwdb = ((un->avg_pwdb * 19 + pwdb) / 20); RTWN_DPRINTF(sc, RTWN_DEBUG_RSSI, "MACID %d, PWDB %d, EMA %d\n", un->id, pwdb, un->avg_pwdb); } static int8_t rtwn_get_rssi(struct rtwn_softc *sc, void *physt, int is_cck) { int8_t rssi; if (is_cck) rssi = rtwn_get_rssi_cck(sc, physt); else /* OFDM/HT. */ rssi = rtwn_get_rssi_ofdm(sc, physt); return (rssi); } static uint32_t rtwn_get_tsf_low(struct rtwn_softc *sc, int id) { return (rtwn_read_4(sc, R92C_TSFTR(id))); } static uint32_t rtwn_get_tsf_high(struct rtwn_softc *sc, int id) { return (rtwn_read_4(sc, R92C_TSFTR(id) + 4)); } static void rtwn_get_tsf(struct rtwn_softc *sc, uint64_t *buf, int id) { /* NB: we cannot read it at once. */ *buf = rtwn_get_tsf_high(sc, id); *buf <<= 32; *buf += rtwn_get_tsf_low(sc, id); } static uint64_t rtwn_extend_rx_tsf(struct rtwn_softc *sc, const struct rtwn_rx_stat_common *stat) { uint64_t tsft; uint32_t rxdw3, tsfl, tsfl_curr; int id; rxdw3 = le32toh(stat->rxdw3); tsfl = le32toh(stat->tsf_low); id = MS(rxdw3, RTWN_RXDW3_BSSID01_FIT); switch (id) { case 1: case 2: id >>= 1; tsfl_curr = rtwn_get_tsf_low(sc, id); break; default: { uint32_t tsfl0, tsfl1; tsfl0 = rtwn_get_tsf_low(sc, 0); tsfl1 = rtwn_get_tsf_low(sc, 1); if (abs(tsfl0 - tsfl) < abs(tsfl1 - tsfl)) { id = 0; tsfl_curr = tsfl0; } else { id = 1; tsfl_curr = tsfl1; } break; } } tsft = rtwn_get_tsf_high(sc, id); if (tsfl > tsfl_curr && tsfl > 0xffff0000) tsft--; tsft <<= 32; tsft += tsfl; return (tsft); } struct ieee80211_node * rtwn_rx_common(struct rtwn_softc *sc, struct mbuf *m, void *desc) { struct ieee80211com *ic = &sc->sc_ic; struct ieee80211_node *ni; struct ieee80211_frame_min *wh; struct ieee80211_rx_stats rxs; struct rtwn_node *un; struct rtwn_rx_stat_common *stat; void *physt; uint32_t rxdw0; int8_t rssi; int cipher, infosz, is_cck, pktlen, shift; stat = desc; rxdw0 = le32toh(stat->rxdw0); cipher = MS(rxdw0, RTWN_RXDW0_CIPHER); infosz = MS(rxdw0, RTWN_RXDW0_INFOSZ) * 8; pktlen = MS(rxdw0, RTWN_RXDW0_PKTLEN); shift = MS(rxdw0, RTWN_RXDW0_SHIFT); wh = (struct ieee80211_frame_min *)(mtodo(m, shift + infosz)); if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && cipher != R92C_CAM_ALGO_NONE) m->m_flags |= M_WEP; if (pktlen >= sizeof(*wh)) { ni = ieee80211_find_rxnode(ic, wh); if (ni != NULL && (ni->ni_flags & IEEE80211_NODE_HT)) m->m_flags |= M_AMPDU; } else ni = NULL; un = RTWN_NODE(ni); if (infosz != 0 && (rxdw0 & RTWN_RXDW0_PHYST)) physt = (void *)mtodo(m, shift); else physt = (un != NULL) ? &un->last_physt : &sc->last_physt; bzero(&rxs, sizeof(rxs)); rtwn_get_rx_stats(sc, &rxs, desc, physt); if (rxs.c_pktflags & IEEE80211_RX_F_AMPDU) { /* Next MPDU will come without PHY info. */ memcpy(&sc->last_physt, physt, sizeof(sc->last_physt)); if (un != NULL) memcpy(&un->last_physt, physt, sizeof(sc->last_physt)); } /* Add some common bits. */ /* NB: should not happen. */ if (rxdw0 & RTWN_RXDW0_CRCERR) rxs.c_pktflags |= IEEE80211_RX_F_FAIL_FCSCRC; rxs.r_flags |= IEEE80211_R_TSF_START; /* XXX undocumented */ /* * Doing the TSF64 extension on USB is expensive, especially * if it's being done on every MPDU in an AMPDU burst. */ if (sc->sc_ena_tsf64) { rxs.r_flags |= IEEE80211_R_TSF64; rxs.c_rx_tsf = rtwn_extend_rx_tsf(sc, stat); } else { rxs.r_flags |= IEEE80211_R_TSF32; rxs.c_rx_tsf = le32toh(stat->tsf_low); } /* Get RSSI from PHY status descriptor. */ is_cck = (rxs.c_pktflags & IEEE80211_RX_F_CCK) != 0; rssi = rtwn_get_rssi(sc, physt, is_cck); /* XXX TODO: we really need a rate-to-string method */ RTWN_DPRINTF(sc, RTWN_DEBUG_RSSI, "%s: rssi %d, rate %d\n", __func__, rssi, rxs.c_rate); if (un != NULL && infosz != 0 && (rxdw0 & RTWN_RXDW0_PHYST)) { /* Update our average RSSI. */ rtwn_update_avgrssi(sc, un, rssi, is_cck); } rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI; rxs.c_nf = RTWN_NOISE_FLOOR; rxs.c_rssi = rssi - rxs.c_nf; (void) ieee80211_add_rx_params(m, &rxs); if (ieee80211_radiotap_active(ic)) { struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; tap->wr_flags = rtwn_rx_radiotap_flags(sc, desc); tap->wr_tsft = htole64(rxs.c_rx_tsf); tap->wr_rate = rxs.c_rate; tap->wr_dbm_antsignal = rssi; tap->wr_dbm_antnoise = rxs.c_nf; } /* Drop PHY descriptor. */ m_adj(m, infosz + shift); /* If APPFCS, drop FCS */ if (sc->rcr & R92C_RCR_APPFCS) m_adj(m, -IEEE80211_CRC_LEN); return (ni); } void rtwn_adhoc_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) { struct ieee80211vap *vap = ni->ni_vap; struct rtwn_softc *sc = vap->iv_ic->ic_softc; struct rtwn_vap *uvp = RTWN_VAP(vap); uint64_t ni_tstamp, curr_tstamp; uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); if (vap->iv_state == IEEE80211_S_RUN && (subtype == IEEE80211_FC0_SUBTYPE_BEACON || subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { ni_tstamp = le64toh(ni->ni_tstamp.tsf); RTWN_LOCK(sc); rtwn_get_tsf(sc, &curr_tstamp, uvp->id); RTWN_UNLOCK(sc); if (ni_tstamp >= curr_tstamp) (void) ieee80211_ibss_merge(ni); } } static uint8_t rtwn_get_multi_pos(const uint8_t maddr[]) { uint64_t mask = 0x00004d101df481b4; uint8_t pos = 0x27; /* initial value */ int i, j; for (i = 0; i < IEEE80211_ADDR_LEN; i++) for (j = (i == 0) ? 1 : 0; j < 8; j++) if ((maddr[i] >> j) & 1) pos ^= (mask >> (i * 8 + j - 1)); pos &= 0x3f; return (pos); } static u_int rtwm_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) { uint32_t *mfilt = arg; uint8_t pos; pos = rtwn_get_multi_pos(LLADDR(sdl)); mfilt[pos / 32] |= (1 << (pos % 32)); return (1); } void rtwn_set_multi(struct rtwn_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; uint32_t mfilt[2]; RTWN_ASSERT_LOCKED(sc); /* general structure was copied from ath(4). */ if (ic->ic_allmulti == 0) { struct ieee80211vap *vap; /* * Merge multicast addresses to form the hardware filter. */ mfilt[0] = mfilt[1] = 0; TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) if_foreach_llmaddr(vap->iv_ifp, rtwm_hash_maddr, mfilt); } else mfilt[0] = mfilt[1] = ~0; rtwn_write_4(sc, R92C_MAR + 0, mfilt[0]); rtwn_write_4(sc, R92C_MAR + 4, mfilt[1]); RTWN_DPRINTF(sc, RTWN_DEBUG_STATE, "%s: MC filter %08x:%08x\n", __func__, mfilt[0], mfilt[1]); } static void rtwn_rxfilter_update_mgt(struct rtwn_softc *sc) { uint16_t filter; filter = 0x7f7f; if (sc->bcn_vaps == 0) { /* STA and/or MONITOR mode vaps */ filter &= ~( R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); } if (sc->ap_vaps == sc->nvaps - sc->mon_vaps) { /* AP vaps only */ filter &= ~( R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP)); } rtwn_write_2(sc, R92C_RXFLTMAP0, filter); } void rtwn_rxfilter_update(struct rtwn_softc *sc) { RTWN_ASSERT_LOCKED(sc); /* Filter for management frames. */ rtwn_rxfilter_update_mgt(sc); /* Update Rx filter. */ rtwn_set_promisc(sc); } void rtwn_rxfilter_init(struct rtwn_softc *sc) { RTWN_ASSERT_LOCKED(sc); /* Setup multicast filter. */ rtwn_set_multi(sc); /* Reject all control frames. */ rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); /* Reject all data frames. */ rtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); /* Append generic Rx filter bits. */ sc->rcr |= R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; /* * Add FCS, to work around occasional 4 byte truncation * with some frames. This is more problematic on RTL8812/ * RTL8821 because they're also doing L3/L4 checksum offload * and hardware encryption, so both are tagged as "passed" * before the frame is truncated. */ sc->rcr |= R92C_RCR_APPFCS; /* Update dynamic Rx filter parts. */ rtwn_rxfilter_update(sc); } void rtwn_rxfilter_set(struct rtwn_softc *sc) { if (!(sc->sc_flags & RTWN_RCR_LOCKED)) rtwn_write_4(sc, R92C_RCR, sc->rcr); } void rtwn_set_rx_bssid_all(struct rtwn_softc *sc, int enable) { if (enable) sc->rcr &= ~R92C_RCR_CBSSID_BCN; else sc->rcr |= R92C_RCR_CBSSID_BCN; rtwn_rxfilter_set(sc); } void rtwn_set_promisc(struct rtwn_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; uint32_t mask_all, mask_min; RTWN_ASSERT_LOCKED(sc); mask_all = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; mask_min = R92C_RCR_APM | R92C_RCR_APPFCS; if (sc->bcn_vaps == 0) mask_min |= R92C_RCR_CBSSID_BCN; if (sc->ap_vaps == 0) mask_min |= R92C_RCR_CBSSID_DATA; if (ic->ic_promisc == 0 && sc->mon_vaps == 0) { if (sc->bcn_vaps != 0) mask_all |= R92C_RCR_CBSSID_BCN; if (sc->ap_vaps != 0) /* for Null data frames */ mask_all |= R92C_RCR_CBSSID_DATA; sc->rcr &= ~mask_all; sc->rcr |= mask_min; } else { sc->rcr &= ~mask_min; sc->rcr |= mask_all; } rtwn_rxfilter_set(sc); } diff --git a/sys/dev/rtwn/rtl8192c/r92c_reg.h b/sys/dev/rtwn/rtl8192c/r92c_reg.h index 6ca4a4eca031..e6d232a88834 100644 --- a/sys/dev/rtwn/rtl8192c/r92c_reg.h +++ b/sys/dev/rtwn/rtl8192c/r92c_reg.h @@ -1,903 +1,929 @@ /*- * Copyright (c) 2010 Damien Bergamini * Copyright (c) 2015 Stefan Sperling * Copyright (c) 2015-2016 Andriy Voskoboinyk * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ */ #ifndef R92C_REG_H #define R92C_REG_H /* * MAC registers. */ /* System Configuration. */ #define R92C_SYS_ISO_CTRL 0x000 #define R92C_SYS_FUNC_EN 0x002 #define R92C_APS_FSMCO 0x004 #define R92C_SYS_CLKR 0x008 #define R92C_AFE_MISC 0x010 #define R92C_SPS0_CTRL 0x011 #define R92C_SPS_OCP_CFG 0x018 #define R92C_RSV_CTRL 0x01c #define R92C_RF_CTRL 0x01f #define R92C_LDOA15_CTRL 0x020 #define R92C_LDOV12D_CTRL 0x021 #define R92C_LDOHCI12_CTRL 0x022 #define R92C_LPLDO_CTRL 0x023 #define R92C_AFE_XTAL_CTRL 0x024 #define R92C_AFE_PLL_CTRL 0x028 #define R92C_APE_PLL_CTRL_EXT 0x02c #define R92C_MAC_PHY_CTRL R92C_APE_PLL_CTRL_EXT #define R92C_EFUSE_CTRL 0x030 #define R92C_EFUSE_TEST 0x034 #define R92C_PWR_DATA 0x038 #define R92C_CAL_TIMER 0x03c #define R92C_ACLK_MON 0x03e #define R92C_GPIO_MUXCFG 0x040 #define R92C_GPIO_IO_SEL 0x042 #define R92C_MAC_PINMUX_CFG 0x043 #define R92C_GPIO_PIN_CTRL 0x044 #define R92C_GPIO_IN 0x044 #define R92C_GPIO_OUT 0x045 #define R92C_GPIO_IOSEL 0x046 #define R92C_GPIO_MOD 0x047 #define R92C_GPIO_INTM 0x048 #define R92C_LEDCFG0 0x04c #define R92C_LEDCFG1 0x04d #define R92C_LEDCFG2 0x04e #define R92C_LEDCFG3 0x04f #define R92C_FSIMR 0x050 #define R92C_FSISR 0x054 #define R92C_HSIMR 0x058 #define R92C_HSISR 0x05c #define R92C_MULTI_FUNC_CTRL 0x068 #define R92C_AFE_XTAL_CTRL_EXT 0x078 #define R92C_LDO_SWR_CTRL 0x07c #define R92C_MCUFWDL 0x080 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) #define R92C_EFUSE_ACCESS 0x0cf #define R92C_BIST_SCAN 0x0d0 #define R92C_BIST_RPT 0x0d4 #define R92C_BIST_ROM_RPT 0x0d8 #define R92C_HPON_FSM 0x0ec #define R92C_SYS_CFG 0x0f0 #define R92C_TYPE_ID 0x0fc /* MAC General Configuration. */ #define R92C_CR 0x100 #define R92C_MSR 0x102 #define R92C_PBP 0x104 #define R92C_TRXDMA_CTRL 0x10c #define R92C_TRXFF_BNDY 0x114 #define R92C_TRXFF_STATUS 0x118 #define R92C_RXFF_PTR 0x11c #define R92C_HIMR 0x120 #define R92C_HISR 0x124 #define R92C_HIMRE 0x128 #define R92C_HISRE 0x12c #define R92C_CPWM 0x12f #define R92C_FWIMR 0x130 #define R92C_FWISR 0x134 #define R92C_PKTBUF_DBG_CTRL 0x140 #define R92C_PKTBUF_DBG_DATA_L 0x144 #define R92C_PKTBUF_DBG_DATA_H 0x148 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) #define R92C_TCUNIT_BASE 0x164 #define R92C_MBIST_START 0x174 #define R92C_MBIST_DONE 0x178 #define R92C_MBIST_FAIL 0x17c #define R92C_C2H_EVT_MSG 0x1a0 #define R92C_C2H_EVT_CLEAR 0x1af #define R92C_C2H_EVT_MSG_TEST 0x1b8 #define R92C_MCUTST_1 0x1c0 #define R92C_FMETHR 0x1c8 #define R92C_HMETFR 0x1cc #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) #define R92C_LLT_INIT 0x1e0 #define R92C_BB_ACCESS_CTRL 0x1e8 #define R92C_BB_ACCESS_DATA 0x1ec /* Tx DMA Configuration. */ #define R92C_RQPN 0x200 #define R92C_FIFOPAGE 0x204 #define R92C_TDECTRL 0x208 #define R92C_TXDMA_OFFSET_CHK 0x20c #define R92C_TXDMA_STATUS 0x210 #define R92C_RQPN_NPQ 0x214 #define R92C_AUTO_LLT 0x224 /* Rx DMA Configuration. */ #define R92C_RXDMA_AGG_PG_TH 0x280 #define R92C_RXPKT_NUM 0x284 #define R92C_RXDMA_STATUS 0x288 /* Protocol Configuration. */ #define R92C_VOQ_INFORMATION 0x400 #define R92C_VIQ_INFORMATION 0x404 #define R92C_BEQ_INFORMATION 0x408 #define R92C_BKQ_INFORMATION 0x40c #define R92C_MGQ_INFORMATION 0x410 #define R92C_HGQ_INFORMATION 0x414 #define R92C_BCNQ_INFORMATION 0x418 #define R92C_CPU_MGQ_INFORMATION 0x41c #define R92C_FWHW_TXQ_CTRL 0x420 #define R92C_HWSEQ_CTRL 0x423 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 #define R92C_SPEC_SIFS 0x428 #define R92C_RL 0x42a #define R92C_DARFRC 0x430 #define R92C_RARFRC 0x438 #define R92C_RRSR 0x440 #define R92C_ARFR(i) (0x444 + (i) * 4) #define R92C_AGGLEN_LMT 0x458 #define R92C_AMPDU_MIN_SPACE 0x45c #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d #define R92C_FAST_EDCA_CTRL 0x460 #define R92C_RD_RESP_PKT_TH 0x463 #define R92C_INIRTS_RATE_SEL 0x480 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) #define R92C_POWER_STATUS 0x4a4 #define R92C_QUEUE_CTRL 0x4c6 #define R92C_MAX_AGGR_NUM 0x4ca #define R92C_BAR_MODE_CTRL 0x4cc /* EDCA Configuration. */ #define R92C_EDCA_VO_PARAM 0x500 #define R92C_EDCA_VI_PARAM 0x504 #define R92C_EDCA_BE_PARAM 0x508 #define R92C_EDCA_BK_PARAM 0x50c #define R92C_BCNTCFG 0x510 #define R92C_PIFS 0x512 #define R92C_RDG_PIFS 0x513 #define R92C_SIFS_CCK 0x514 #define R92C_SIFS_OFDM 0x516 #define R92C_AGGR_BREAK_TIME 0x51a #define R92C_SLOT 0x51b #define R92C_TX_PTCL_CTRL 0x520 #define R92C_TXPAUSE 0x522 #define R92C_DIS_TXREQ_CLR 0x523 #define R92C_RD_CTRL 0x524 #define R92C_TBTT_PROHIBIT 0x540 #define R92C_RD_NAV_NXT 0x544 #define R92C_NAV_PROT_LEN 0x546 #define R92C_BCN_CTRL(id) ((id) + 0x550) /* WARNING: R92C_USTIME_TSF == 0x55c, not 0x551 */ #define R92C_MBID_NUM 0x552 #define R92C_DUAL_TSF_RST 0x553 #define R92C_BCN_INTERVAL(id) (0x554 + (id) * 2) #define R92C_DRVERLYINT 0x558 #define R92C_BCNDMATIM 0x559 #define R92C_ATIMWND 0x55a #define R92C_USTIME_TSF 0x55c #define R92C_BCN_MAX_ERR 0x55d #define R92C_RXTSF_OFFSET_CCK 0x55e #define R92C_RXTSF_OFFSET_OFDM 0x55f #define R92C_TSFTR(i) (0x560 + (i) * 8) #define R92C_PSTIMER 0x580 #define R92C_TIMER0 0x584 #define R92C_TIMER1 0x588 #define R92C_ACMHWCTRL 0x5c0 #define R92C_ACMRSTCTRL 0x5c1 #define R92C_ACMAVG 0x5c2 #define R92C_VO_ADMTIME 0x5c4 #define R92C_VI_ADMTIME 0x5c6 #define R92C_BE_ADMTIME 0x5c8 #define R92C_EDCA_RANDOM_GEN 0x5cc #define R92C_SCH_TXCMD 0x5d0 /* WMAC Configuration. */ #define R92C_APSD_CTRL 0x600 #define R92C_BWOPMODE 0x603 #define R92C_TCR 0x604 #define R92C_RCR 0x608 #define R92C_RX_PKT_LIMIT 0x60c #define R92C_RX_DRVINFO_SZ 0x60f #define R92C_MACID0 0x610 #define R92C_BSSID0 0x618 #define R92C_MAR 0x620 #define R92C_USTIME_EDCA 0x638 #define R92C_MAC_SPEC_SIFS 0x63a #define R92C_R2T_SIFS 0x63c #define R92C_T2T_SIFS 0x63e #define R92C_ACKTO 0x640 #define R92C_NAV_UPPER 0x652 #define R92C_WMAC_TRXPTCL_CTL 0x668 #define R92C_CAMCMD 0x670 #define R92C_CAMWRITE 0x674 #define R92C_CAMREAD 0x678 #define R92C_CAMDBG 0x67c #define R92C_SECCFG 0x680 #define R92C_RXFLTMAP0 0x6a0 #define R92C_RXFLTMAP1 0x6a2 #define R92C_RXFLTMAP2 0x6a4 #define R92C_BCN_PSR_RPT 0x6a8 #define R92C_MACID1 0x700 #define R92C_BSSID1 0x708 #define R92C_MACID(id) ((id) == 0 ? R92C_MACID0 : R92C_MACID1) #define R92C_BSSID(id) ((id) == 0 ? R92C_BSSID0 : R92C_BSSID1) /* Bits for R92C_SYS_ISO_CTRL. */ #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 /* Bits for R92C_SYS_FUNC_EN. */ #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 #define R92C_SYS_FUNC_EN_USBA 0x0004 #define R92C_SYS_FUNC_EN_UPLL 0x0008 #define R92C_SYS_FUNC_EN_USBD 0x0010 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 #define R92C_SYS_FUNC_EN_PPLL 0x0080 #define R92C_SYS_FUNC_EN_PCIED 0x0100 #define R92C_SYS_FUNC_EN_DIOE 0x0200 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 #define R92C_SYS_FUNC_EN_DCORE 0x0800 #define R92C_SYS_FUNC_EN_ELDR 0x1000 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 /* Bits for R92C_APS_FSMCO. */ #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 #define R92C_APS_FSMCO_PDN_EN 0x00000010 #define R92C_APS_FSMCO_PDN_PL 0x00000020 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 /* Bits for R92C_SYS_CLKR. */ #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 #define R92C_SYS_CLKR_ANA8M 0x00000002 #define R92C_SYS_CLKR_MACSLP 0x00000010 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 #define R92C_SYS_CLKR_SEC_EN 0x00000400 #define R92C_SYS_CLKR_MAC_EN 0x00000800 #define R92C_SYS_CLKR_SYS_EN 0x00001000 #define R92C_SYS_CLKR_RING_EN 0x00002000 /* Bits for R92C_RSV_CTRL. */ #define R92C_RSV_CTRL_WLOCK_ALL 0x01 #define R92C_RSV_CTRL_WLOCK_00 0x02 #define R92C_RSV_CTRL_WLOCK_04 0x04 #define R92C_RSV_CTRL_WLOCK_08 0x08 #define R92C_RSV_CTRL_WLOCK_40 0x10 #define R92C_RSV_CTRL_R_DIS_PRST_0 0x20 #define R92C_RSV_CTRL_R_DIS_PRST_1 0x40 #define R92C_RSV_CTRL_LOCK_ALL_EN 0x80 /* Bits for R92C_RF_CTRL. */ #define R92C_RF_CTRL_EN 0x01 #define R92C_RF_CTRL_RSTB 0x02 #define R92C_RF_CTRL_SDMRSTB 0x04 /* Bits for R92C_LDOA15_CTRL. */ #define R92C_LDOA15_CTRL_EN 0x01 #define R92C_LDOA15_CTRL_STBY 0x02 #define R92C_LDOA15_CTRL_OBUF 0x04 #define R92C_LDOA15_CTRL_REG_VOS 0x08 /* Bits for R92C_LDOV12D_CTRL. */ #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 /* Bits for R92C_LPLDO_CTRL. */ #define R92C_LPLDO_CTRL_SLEEP 0x10 /* Bits for R92C_AFE_XTAL_CTRL. */ #define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 #define R92C_AFE_XTAL_CTRL_ADDR_S 11 /* Bits for R92C_AFE_PLL_CTRL. */ #define R92C_AFE_PLL_CTRL_EN 0x0001 #define R92C_AFE_PLL_CTRL_320_EN 0x0002 #define R92C_AFE_PLL_CTRL_FREF_SEL 0x0004 #define R92C_AFE_PLL_CTRL_EDGE_SEL 0x0008 #define R92C_AFE_PLL_CTRL_WDOGB 0x0010 #define R92C_AFE_PLL_CTRL_LPFEN 0x0020 /* Bits for R92C_EFUSE_CTRL. */ #define R92C_EFUSE_CTRL_DATA_M 0x000000ff #define R92C_EFUSE_CTRL_DATA_S 0 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 #define R92C_EFUSE_CTRL_ADDR_S 8 #define R92C_EFUSE_CTRL_VALID 0x80000000 /* Bits for R92C_GPIO_MUXCFG. */ #define R92C_GPIO_MUXCFG_ENBT 0x0020 #define R92C_GPIO_MUXCFG_ENSIC 0x1000 /* Bits for R92C_LEDCFG0. */ #define R92C_LEDCFG0_DIS 0x08 /* Bits for R92C_LEDCFG1. */ #define R92C_LEDCFG1_DIS 0x80 /* Bits for R92C_MULTI_FUNC_CTRL. */ #define R92C_MULTI_BT_FUNC_EN 0x00040000 /* Bits for R92C_MCUFWDL. */ #define R92C_MCUFWDL_EN 0x00000001 #define R92C_MCUFWDL_RDY 0x00000002 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */ #define R92C_MCUFWDL_PAGE_M 0x00070000 #define R92C_MCUFWDL_PAGE_S 16 #define R92C_MCUFWDL_ROM_DLEN 0x00080000 #define R92C_MCUFWDL_CPRST 0x00800000 /* Bits for R92C_EFUSE_ACCESS. */ #define R92C_EFUSE_ACCESS_OFF 0x00 #define R92C_EFUSE_ACCESS_ON 0x69 /* Bits for R92C_HPON_FSM. */ #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 /* Bits for R92C_SYS_CFG. */ #define R92C_SYS_CFG_XCLK_VLD 0x00000001 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 #define R92C_SYS_CFG_PCIRSTB 0x00000010 #define R92C_SYS_CFG_V15_VLD 0x00000020 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 #define R92C_SYS_CFG_BD_MAC2 0x00000200 #define R92C_SYS_CFG_BD_MAC1 0x00000400 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 #define R92C_SYS_CFG_BT_FUNC 0x00010000 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 #define R92C_SYS_CFG_TYPE_92C 0x08000000 /* Bits for R92C_CR. */ #define R92C_CR_HCI_TXDMA_EN 0x0001 #define R92C_CR_HCI_RXDMA_EN 0x0002 #define R92C_CR_TXDMA_EN 0x0004 #define R92C_CR_RXDMA_EN 0x0008 #define R92C_CR_PROTOCOL_EN 0x0010 #define R92C_CR_SCHEDULE_EN 0x0020 #define R92C_CR_MACTXEN 0x0040 #define R92C_CR_MACRXEN 0x0080 #define R92C_CR_ENSWBCN 0x0100 #define R92C_CR_ENSEC 0x0200 #define R92C_CR_CALTMR_EN 0x0400 /* Bits for R92C_MSR. */ #define R92C_MSR_NOLINK 0x00 #define R92C_MSR_ADHOC 0x01 #define R92C_MSR_INFRA 0x02 #define R92C_MSR_AP 0x03 #define R92C_MSR_MASK (R92C_MSR_AP) /* Bits for R92C_PBP. */ #define R92C_PBP_PSRX_M 0x0f #define R92C_PBP_PSRX_S 0 #define R92C_PBP_PSTX_M 0xf0 #define R92C_PBP_PSTX_S 4 #define R92C_PBP_64 0 #define R92C_PBP_128 1 #define R92C_PBP_256 2 #define R92C_PBP_512 3 #define R92C_PBP_1024 4 /* Bits for R92C_TRXDMA_CTRL. */ #define R92C_TRXDMA_CTRL_RX_SHIFT_EN 0x0002 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 /* Shortcuts. */ #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 /* Bits for R92C_C2H_EVT_CLEAR. */ #define R92C_C2H_EVT_HOST_CLOSE 0x00 #define R92C_C2H_EVT_FW_CLOSE 0xff /* Bits for R92C_LLT_INIT. */ #define R92C_LLT_INIT_DATA_M 0x000000ff #define R92C_LLT_INIT_DATA_S 0 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 #define R92C_LLT_INIT_ADDR_S 8 #define R92C_LLT_INIT_OP_M 0xc0000000 #define R92C_LLT_INIT_OP_S 30 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 #define R92C_LLT_INIT_OP_WRITE 1 /* Bits for R92C_RQPN. */ #define R92C_RQPN_HPQ_M 0x000000ff #define R92C_RQPN_HPQ_S 0 #define R92C_RQPN_LPQ_M 0x0000ff00 #define R92C_RQPN_LPQ_S 8 #define R92C_RQPN_PUBQ_M 0x00ff0000 #define R92C_RQPN_PUBQ_S 16 #define R92C_RQPN_LD 0x80000000 /* Bits for R92C_TDECTRL. */ #define R92C_TDECTRL_BLK_DESC_NUM_M 0x000000f0 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 #define R92C_TDECTRL_BCN_VALID 0x00010000 /* Bits for R92C_TXDMA_OFFSET_CHK. */ #define R92C_TXDMA_OFFSET_DROP_DATA_EN 0x00000200 /* Bits for R92C_AUTO_LLT. */ #define R92C_AUTO_LLT_INIT 0x00010000 /* Bits for R92C_FWHW_TXQ_CTRL. */ #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 #define R92C_FWHW_TXQ_CTRL_REAL_BEACON 0x400000 /* Bits for R92C_SPEC_SIFS. */ #define R92C_SPEC_SIFS_CCK_M 0x00ff #define R92C_SPEC_SIFS_CCK_S 0 #define R92C_SPEC_SIFS_OFDM_M 0xff00 #define R92C_SPEC_SIFS_OFDM_S 8 /* Bits for R92C_RL. */ #define R92C_RL_LRL_M 0x003f #define R92C_RL_LRL_S 0 #define R92C_RL_SRL_M 0x3f00 #define R92C_RL_SRL_S 8 /* Size of R92C_DARFRC. */ #define R92C_DARFRC_SIZE 8 /* Bits for R92C_RRSR. */ #define R92C_RRSR_RATE_BITMAP_M 0x000fffff #define R92C_RRSR_RATE_BITMAP_S 0 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 +/* Suitable low-rate defaults for 2/5GHz CTS/ACK/Block-ACK */ +/* + * Note: the RTL8192CU vendor driver disables 2M CCK as a + * basic rate due to "Low TXEVM" causing issues with other + * vendor devices. Since we want to maximise basic rate + * reliability to prevent retries (due to missing RTS/CTS + * and ACK/Block-ACK), do the same here. + * + * And, unfortunately, enabling MCS rates for self-generated + * and management/control frames can result in the peer AP + * just plainly ignoring you. This happened with older + * D-Link 802.11n era APs. The masks will exclude MCS management + * rates, it's easy to add it to the mask in rtwn_set_basicrates(). + * (Just |= 0x100, bit 12 == MCS 0.) + */ +#define R92C_RRSR_RATE_MASK_2GHZ 0x015d +#define R92C_RRSR_RATE_MASK_5GHZ 0x0150 #define R92C_RRSR_RATE_ALL 0xfffff #define R92C_RRSR_RSC_SUBCHNL_MASK 0x00600000 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 #define R92C_RRSR_SHORT 0x00800000 /* Bits for R92C_EDCA_XX_PARAM. */ #define R92C_EDCA_PARAM_AIFS_M 0x000000ff #define R92C_EDCA_PARAM_AIFS_S 0 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 #define R92C_EDCA_PARAM_ECWMIN_S 8 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 #define R92C_EDCA_PARAM_ECWMAX_S 12 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 #define R92C_EDCA_PARAM_TXOP_S 16 +/* Bits for R92C_INIRTS_RATE_SEL. */ +#define R92C_INIRTS_RATE_SEL_RATE_M 0x3f +#define R92C_INIRTS_RATE_SEL_RATE_S 0 + +/* Bits for R92C_INIDATA_RATE_SEL. */ +#define R92C_INIDATA_RATE_SEL_RATE_M 0x3f +#define R92C_INIDATA_RATE_SEL_RATE_S 0 +#define R92C_INIDATA_RATE_SEL_SHORTGI 0x40 + /* Bits for R92C_HWSEQ_CTRL / R92C_TXPAUSE. */ #define R92C_TX_QUEUE_VO 0x01 #define R92C_TX_QUEUE_VI 0x02 #define R92C_TX_QUEUE_BE 0x04 #define R92C_TX_QUEUE_BK 0x08 #define R92C_TX_QUEUE_MGT 0x10 #define R92C_TX_QUEUE_HIGH 0x20 #define R92C_TX_QUEUE_BCN 0x40 /* Shortcuts. */ #define R92C_TX_QUEUE_AC \ (R92C_TX_QUEUE_VO | R92C_TX_QUEUE_VI | \ R92C_TX_QUEUE_BE | R92C_TX_QUEUE_BK) #define R92C_TX_QUEUE_ALL \ (R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | \ R92C_TX_QUEUE_HIGH | R92C_TX_QUEUE_BCN | 0x80) /* XXX */ /* Bits for R92C_BCN_CTRL. */ #define R92C_BCN_CTRL_EN_MBSSID 0x02 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 #define R92C_BCN_CTRL_EN_BCN 0x08 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 /* Bits for R92C_DUAL_TSF_RST. */ #define R92C_DUAL_TSF_RESET(id) (0x01 << (id)) #define R92C_DUAL_TSF_RST_TXOK 0x20 /* Bits for R92C_ACMHWCTRL. */ #define R92C_ACMHWCTRL_EN 0x01 #define R92C_ACMHWCTRL_BE 0x02 #define R92C_ACMHWCTRL_VI 0x04 #define R92C_ACMHWCTRL_VO 0x08 #define R92C_ACMHWCTRL_ACM_MASK 0x0f /* Bits for R92C_APSD_CTRL. */ #define R92C_APSD_CTRL_OFF 0x40 #define R92C_APSD_CTRL_OFF_STATUS 0x80 /* Bits for R92C_BWOPMODE. */ #define R92C_BWOPMODE_11J 0x01 #define R92C_BWOPMODE_5G 0x02 #define R92C_BWOPMODE_20MHZ 0x04 /* Bits for R92C_TCR. */ #define R92C_TCR_TSFRST 0x00000001 #define R92C_TCR_DIS_GCLK 0x00000002 #define R92C_TCR_PAD_SEL 0x00000004 #define R92C_TCR_PWR_ST 0x00000040 #define R92C_TCR_PWRBIT_OW_EN 0x00000080 #define R92C_TCR_ACRC 0x00000100 #define R92C_TCR_CFENDFORM 0x00000200 #define R92C_TCR_ICV 0x00000400 /* Bits for R92C_RCR. */ #define R92C_RCR_AAP 0x00000001 #define R92C_RCR_APM 0x00000002 #define R92C_RCR_AM 0x00000004 #define R92C_RCR_AB 0x00000008 #define R92C_RCR_ADD3 0x00000010 #define R92C_RCR_APWRMGT 0x00000020 #define R92C_RCR_CBSSID_DATA 0x00000040 #define R92C_RCR_CBSSID_BCN 0x00000080 #define R92C_RCR_ACRC32 0x00000100 #define R92C_RCR_AICV 0x00000200 #define R92C_RCR_ADF 0x00000800 #define R92C_RCR_ACF 0x00001000 #define R92C_RCR_AMF 0x00002000 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 #define R92C_RCR_MFBEN 0x00400000 #define R92C_RCR_LSIGEN 0x00800000 #define R92C_RCR_ENMBID 0x01000000 #define R92C_RCR_APP_BA_SSN 0x08000000 #define R92C_RCR_APP_PHYSTS 0x10000000 #define R92C_RCR_APP_ICV 0x20000000 #define R92C_RCR_APP_MIC 0x40000000 #define R92C_RCR_APPFCS 0x80000000 /* Bits for R92C_RX_DRVINFO_SZ. */ /* XXX other values will not work */ #define R92C_RX_DRVINFO_SZ_DEF ((RTWN_PHY_STATUS_SIZE) / 8) /* Bits for R92C_WMAC_TRXPTCL_CTL. */ #define R92C_WMAC_TRXPTCL_SHPRE 0x00020000 /* Bits for R92C_CAMCMD. */ #define R92C_CAMCMD_ADDR_M 0x0000ffff #define R92C_CAMCMD_ADDR_S 0 #define R92C_CAMCMD_WRITE 0x00010000 #define R92C_CAMCMD_CLR 0x40000000 #define R92C_CAMCMD_POLLING 0x80000000 /* * CAM entries. */ #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) #define R92C_CAM_CTL6(entry) ((entry) * 8 + 6) #define R92C_CAM_CTL7(entry) ((entry) * 8 + 7) /* Bits for R92C_CAM_CTL0(i). */ #define R92C_CAM_KEYID_M 0x00000003 #define R92C_CAM_KEYID_S 0 #define R92C_CAM_ALGO_M 0x0000001c #define R92C_CAM_ALGO_S 2 #define R92C_CAM_ALGO_NONE 0 #define R92C_CAM_ALGO_WEP40 1 #define R92C_CAM_ALGO_TKIP 2 #define R92C_CAM_ALGO_AES 4 #define R92C_CAM_ALGO_WEP104 5 #define R92C_CAM_VALID 0x00008000 #define R92C_CAM_MACLO_M 0xffff0000 #define R92C_CAM_MACLO_S 16 /* Bits for R92C_SECCFG. */ #define R92C_SECCFG_TXUCKEY_DEF 0x0001 #define R92C_SECCFG_RXUCKEY_DEF 0x0002 #define R92C_SECCFG_TXENC_ENA 0x0004 #define R92C_SECCFG_RXDEC_ENA 0x0008 #define R92C_SECCFG_CMP_A2 0x0010 #define R92C_SECCFG_MC_SRCH_DIS 0x0020 #define R92C_SECCFG_TXBCKEY_DEF 0x0040 #define R92C_SECCFG_RXBCKEY_DEF 0x0080 /* Bits for R92C_RXFLTMAP*. */ #define R92C_RXFLTMAP_SUBTYPE(subtype) \ (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT)) /* * Baseband registers. */ #define R92C_FPGA0_RFMOD 0x800 #define R92C_FPGA0_TXINFO 0x804 #define R92C_FPGA0_POWER_SAVE 0x818 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) #define R92C_TXAGC_A_CCK1_MCS32 0xe08 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) #define R92C_FPGA0_ANAPARAM2 0x884 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) #define R92C_FPGA1_RFMOD 0x900 #define R92C_FPGA1_TXINFO 0x90c #define R92C_CCK0_SYSTEM 0xa00 #define R92C_CCK0_AFESETTING 0xa04 #define R92C_CONFIG_ANT(chain) (0xb68 + (chain) * 4) #define R92C_OFDM0_TRXPATHENA 0xc04 #define R92C_OFDM0_TRMUXPAR 0xc08 #define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8) #define R92C_OFDM0_ECCATHRESHOLD 0xc4c #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) #define R92C_OFDM0_AGCPARAM1 0xc70 #define R92C_OFDM0_AGCRSSITABLE 0xc78 #define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8) #define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8) #define R92C_OFDM0_RXIQEXTANTA 0xca0 #define R92C_OFDM0_TXPSEUDONOISEWGT 0xce4 #define R92C_OFDM1_LSTF 0xd00 #define R92C_FPGA0_IQK 0xe28 #define R92C_TX_IQK_TONE(chain) (0xe30 + (chain) * 32) #define R92C_RX_IQK_TONE(chain) (0xe34 + (chain) * 32) #define R92C_TX_IQK_PI(chain) (0xe38 + (chain) * 32) #define R92C_RX_IQK_PI(chain) (0xe3c + (chain) * 32) #define R92C_TX_IQK 0xe40 #define R92C_RX_IQK 0xe44 #define R92C_IQK_AGC_PTS 0xe48 #define R92C_IQK_AGC_RSP 0xe4c #define R92C_IQK_AGC_CONT 0xe60 #define R92C_TX_POWER_IQK_BEFORE(chain) (0xe94 + (chain) * 32) #define R92C_TX_POWER_IQK_AFTER(chain) (0xe9c + (chain) * 32) #define R92C_RX_POWER_IQK_BEFORE(chain) (0xea4 + (chain) * 32) #define R92C_RX_POWER_IQK_AFTER(chain) (0xeac + (chain) * 32) /* Bits for R92C_FPGA[01]_RFMOD. */ #define R92C_RFMOD_40MHZ 0x00000001 #define R92C_RFMOD_JAPAN 0x00000002 #define R92C_RFMOD_CCK_TXSC 0x00000030 #define R92C_RFMOD_CCK_EN 0x01000000 #define R92C_RFMOD_OFDM_EN 0x02000000 /* Bits for R92C_FPGA0_POWER_SAVE. */ #define R92C_FPGA0_POWER_SAVE_PS_MASK 0x0c000000 #define R92C_FPGA0_POWER_SAVE_PS_LOWER_CHANNEL 0x04000000 #define R92C_FPGA0_POWER_SAVE_PS_UPPER_CHANNEL 0x08000000 /* Bits for R92C_HSSI_PARAM1(i). */ #define R92C_HSSI_PARAM1_PI 0x00000100 /* Bits for R92C_HSSI_PARAM2(i). */ #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ #define R92C_TXAGC_A_CCK1_M 0x0000ff00 #define R92C_TXAGC_A_CCK1_S 8 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ #define R92C_TXAGC_B_CCK11_M 0x000000ff #define R92C_TXAGC_B_CCK11_S 0 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 #define R92C_TXAGC_A_CCK2_S 8 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 #define R92C_TXAGC_A_CCK55_S 16 #define R92C_TXAGC_A_CCK11_M 0xff000000 #define R92C_TXAGC_A_CCK11_S 24 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ #define R92C_TXAGC_B_CCK1_M 0x0000ff00 #define R92C_TXAGC_B_CCK1_S 8 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 #define R92C_TXAGC_B_CCK2_S 16 #define R92C_TXAGC_B_CCK55_M 0xff000000 #define R92C_TXAGC_B_CCK55_S 24 /* Bits for R92C_TXAGC_RATE18_06(x). */ #define R92C_TXAGC_RATE06_M 0x000000ff #define R92C_TXAGC_RATE06_S 0 #define R92C_TXAGC_RATE09_M 0x0000ff00 #define R92C_TXAGC_RATE09_S 8 #define R92C_TXAGC_RATE12_M 0x00ff0000 #define R92C_TXAGC_RATE12_S 16 #define R92C_TXAGC_RATE18_M 0xff000000 #define R92C_TXAGC_RATE18_S 24 /* Bits for R92C_TXAGC_RATE54_24(x). */ #define R92C_TXAGC_RATE24_M 0x000000ff #define R92C_TXAGC_RATE24_S 0 #define R92C_TXAGC_RATE36_M 0x0000ff00 #define R92C_TXAGC_RATE36_S 8 #define R92C_TXAGC_RATE48_M 0x00ff0000 #define R92C_TXAGC_RATE48_S 16 #define R92C_TXAGC_RATE54_M 0xff000000 #define R92C_TXAGC_RATE54_S 24 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ #define R92C_TXAGC_MCS00_M 0x000000ff #define R92C_TXAGC_MCS00_S 0 #define R92C_TXAGC_MCS01_M 0x0000ff00 #define R92C_TXAGC_MCS01_S 8 #define R92C_TXAGC_MCS02_M 0x00ff0000 #define R92C_TXAGC_MCS02_S 16 #define R92C_TXAGC_MCS03_M 0xff000000 #define R92C_TXAGC_MCS03_S 24 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ #define R92C_TXAGC_MCS04_M 0x000000ff #define R92C_TXAGC_MCS04_S 0 #define R92C_TXAGC_MCS05_M 0x0000ff00 #define R92C_TXAGC_MCS05_S 8 #define R92C_TXAGC_MCS06_M 0x00ff0000 #define R92C_TXAGC_MCS06_S 16 #define R92C_TXAGC_MCS07_M 0xff000000 #define R92C_TXAGC_MCS07_S 24 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ #define R92C_TXAGC_MCS08_M 0x000000ff #define R92C_TXAGC_MCS08_S 0 #define R92C_TXAGC_MCS09_M 0x0000ff00 #define R92C_TXAGC_MCS09_S 8 #define R92C_TXAGC_MCS10_M 0x00ff0000 #define R92C_TXAGC_MCS10_S 16 #define R92C_TXAGC_MCS11_M 0xff000000 #define R92C_TXAGC_MCS11_S 24 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ #define R92C_TXAGC_MCS12_M 0x000000ff #define R92C_TXAGC_MCS12_S 0 #define R92C_TXAGC_MCS13_M 0x0000ff00 #define R92C_TXAGC_MCS13_S 8 #define R92C_TXAGC_MCS14_M 0x00ff0000 #define R92C_TXAGC_MCS14_S 16 #define R92C_TXAGC_MCS15_M 0xff000000 #define R92C_TXAGC_MCS15_S 24 /* Bits for R92C_LSSI_PARAM(i). */ #define R92C_LSSI_PARAM_DATA_M 0x000fffff #define R92C_LSSI_PARAM_DATA_S 0 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 #define R92C_LSSI_PARAM_ADDR_S 20 /* Bits for R92C_FPGA0_RFIFACEOE(0). */ #define R92C_FPGA0_RFIFACEOE0_ANT_M 0x00000300 #define R92C_FPGA0_RFIFACEOE0_ANT_S 8 /* Bits for R92C_FPGA0_ANAPARAM2. */ #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 /* Bits for R92C_LSSI_READBACK(i). */ #define R92C_LSSI_READBACK_DATA_M 0x000fffff #define R92C_LSSI_READBACK_DATA_S 0 /* Bits for R92C_CCK0_SYSTEM. */ #define R92C_CCK0_SYSTEM_CCK_SIDEBAND 0x00000010 /* Bits for R92C_OFDM0_AGCCORE1(i). */ #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f #define R92C_OFDM0_AGCCORE1_GAIN_S 0 /* Bits for R92C_[RT]X_POWER_IQK*. */ #define R92C_POWER_IQK_RESULT_S 16 #define R92C_POWER_IQK_RESULT_M 0x03ff0000 /* * RF (6052) registers. */ #define R92C_RF_AC 0x00 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) #define R92C_RF_POW_TRSW 0x05 #define R92C_RF_GAIN_RX 0x06 #define R92C_RF_GAIN_TX 0x07 #define R92C_RF_TXM_IDAC 0x08 #define R92C_RF_BS_IQGEN 0x0f #define R92C_RF_MODE1 0x10 #define R92C_RF_MODE2 0x11 #define R92C_RF_RX_AGC_HP 0x12 #define R92C_RF_TX_AGC 0x13 #define R92C_RF_BIAS 0x14 #define R92C_RF_IPA 0x15 #define R92C_RF_POW_ABILITY 0x17 #define R92C_RF_CHNLBW 0x18 #define R92C_RF_RX_G1 0x1a #define R92C_RF_RX_G2 0x1b #define R92C_RF_RX_BB2 0x1c #define R92C_RF_RX_BB1 0x1d #define R92C_RF_RCK1 0x1e #define R92C_RF_RCK2 0x1f #define R92C_RF_TX_G(i) (0x20 + (i)) #define R92C_RF_TX_BB1 0x23 #define R92C_RF_T_METER 0x24 #define R92C_RF_SYN_G(i) (0x25 + (i)) #define R92C_RF_RCK_OS 0x30 #define R92C_RF_TXPA_G(i) (0x31 + (i)) /* Bits for R92C_RF_AC. */ #define R92C_RF_AC_MODE_M 0x70000 #define R92C_RF_AC_MODE_S 16 #define R92C_RF_AC_MODE_STANDBY 1 /* Bits for R92C_RF_CHNLBW. */ #define R92C_RF_CHNLBW_CHNL_M 0x003ff #define R92C_RF_CHNLBW_CHNL_S 0 #define R92C_RF_CHNLBW_BW20 0x00400 #define R92C_RF_CHNLBW_LCSTART 0x08000 /* Bits for R92C_RF_T_METER. */ #define R92C_RF_T_METER_START 0x60 #define R92C_RF_T_METER_VAL_M 0x1f #define R92C_RF_T_METER_VAL_S 0 #endif /* R92C_REG_H */