diff --git a/sys/dev/usb/controller/dwc3.c b/sys/dev/usb/controller/dwc3.c index b4156903874b..596fcb19ce1a 100644 --- a/sys/dev/usb/controller/dwc3.c +++ b/sys/dev/usb/controller/dwc3.c @@ -1,365 +1,412 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2019 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "generic_xhci.h" static struct ofw_compat_data compat_data[] = { { "snps,dwc3", 1 }, { NULL, 0 } }; struct snps_dwc3_softc { struct xhci_softc sc; device_t dev; struct resource * mem_res; bus_space_tag_t bst; bus_space_handle_t bsh; phandle_t node; phy_t usb2_phy; phy_t usb3_phy; + uint32_t snpsid; }; #define DWC3_WRITE(_sc, _off, _val) \ bus_space_write_4(_sc->bst, _sc->bsh, _off, _val) #define DWC3_READ(_sc, _off) \ bus_space_read_4(_sc->bst, _sc->bsh, _off) static int snps_dwc3_attach_xhci(device_t dev) { struct snps_dwc3_softc *snps_sc = device_get_softc(dev); struct xhci_softc *sc = &snps_sc->sc; int err = 0, rid = 0; sc->sc_io_res = snps_sc->mem_res; sc->sc_io_tag = snps_sc->bst; sc->sc_io_hdl = snps_sc->bsh; sc->sc_io_size = rman_get_size(snps_sc->mem_res); sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->sc_irq_res == NULL) { device_printf(dev, "Failed to allocate IRQ\n"); return (ENXIO); } sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); if (sc->sc_bus.bdev == NULL) { device_printf(dev, "Failed to add USB device\n"); return (ENXIO); } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); sprintf(sc->sc_vendor, "Synopsys"); device_set_desc(sc->sc_bus.bdev, "Synopsys"); err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); if (err != 0) { device_printf(dev, "Failed to setup IRQ, %d\n", err); sc->sc_intr_hdl = NULL; return (err); } err = xhci_init(sc, dev, 1); if (err != 0) { device_printf(dev, "Failed to init XHCI, with error %d\n", err); return (ENXIO); } err = xhci_start_controller(sc); if (err != 0) { device_printf(dev, "Failed to start XHCI controller, with error %d\n", err); return (ENXIO); } device_printf(sc->sc_bus.bdev, "trying to attach\n"); err = device_probe_and_attach(sc->sc_bus.bdev); if (err != 0) { device_printf(dev, "Failed to initialize USB, with error %d\n", err); return (ENXIO); } return (0); } #if 0 static void snsp_dwc3_dump_regs(struct snps_dwc3_softc *sc) { uint32_t reg; reg = DWC3_READ(sc, DWC3_GCTL); device_printf(sc->dev, "GCTL: %x\n", reg); reg = DWC3_READ(sc, DWC3_GUCTL1); device_printf(sc->dev, "GUCTL1: %x\n", reg); reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); device_printf(sc->dev, "GUSB2PHYCFG0: %x\n", reg); reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); device_printf(sc->dev, "GUSB3PIPECTL0: %x\n", reg); reg = DWC3_READ(sc, DWC3_DCFG); device_printf(sc->dev, "DCFG: %x\n", reg); } #endif +#ifdef DWC3_DEBUG +static void +snps_dwc3_dump_ctrlparams(struct snps_dwc3_softc *sc) +{ + const bus_size_t offs[] = { + DWC3_GHWPARAMS0, DWC3_GHWPARAMS1, DWC3_GHWPARAMS2, DWC3_GHWPARAMS3, + DWC3_GHWPARAMS4, DWC3_GHWPARAMS5, DWC3_GHWPARAMS6, DWC3_GHWPARAMS7, + DWC3_GHWPARAMS8, + }; + uint32_t reg; + int i; + + for (i = 0; i < nitems(offs); i++) { + reg = DWC3_READ(sc, offs[i]); + if (bootverbose) + device_printf(sc->dev, "hwparams[%d]: %#012x\n", i, reg); + } +} +#endif + static void snps_dwc3_reset(struct snps_dwc3_softc *sc) { - uint32_t gctl, phy2, phy3; + uint32_t gctl, ghwp0, phy2, phy3; if (sc->usb2_phy) phy_enable(sc->usb2_phy); if (sc->usb3_phy) phy_enable(sc->usb3_phy); + ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); + gctl = DWC3_READ(sc, DWC3_GCTL); gctl |= DWC3_GCTL_CORESOFTRESET; DWC3_WRITE(sc, DWC3_GCTL, gctl); phy2 = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); phy2 |= DWC3_GUSB2PHYCFG0_PHYSOFTRST; + if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == + DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) + phy2 &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); phy3 = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); phy3 |= DWC3_GUSB3PIPECTL0_PHYSOFTRST; + if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == + DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) + phy3 &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3; DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); DELAY(1000); phy2 &= ~DWC3_GUSB2PHYCFG0_PHYSOFTRST; DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); phy3 &= ~DWC3_GUSB3PIPECTL0_PHYSOFTRST; DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); gctl &= ~DWC3_GCTL_CORESOFTRESET; DWC3_WRITE(sc, DWC3_GCTL, gctl); } static void snps_dwc3_configure_host(struct snps_dwc3_softc *sc) { uint32_t reg; reg = DWC3_READ(sc, DWC3_GCTL); reg &= ~DWC3_GCTL_PRTCAPDIR_MASK; reg |= DWC3_GCTL_PRTCAPDIR_HOST; DWC3_WRITE(sc, DWC3_GCTL, reg); /* * Enable the Host IN Auto Retry feature, making the * host respond with a non-terminating retry ACK. * XXX If we ever support more than host mode this needs a dr_mode check. */ reg = DWC3_READ(sc, DWC3_GUCTL); reg |= DWC3_GUCTL_HOST_AUTO_RETRY; DWC3_WRITE(sc, DWC3_GUCTL, reg); } static void snps_dwc3_configure_phy(struct snps_dwc3_softc *sc) { char *phy_type; uint32_t reg; int nphy_types; phy_type = NULL; nphy_types = OF_getprop_alloc(sc->node, "phy_type", (void **)&phy_type); if (nphy_types <= 0) return; reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); if (strncmp(phy_type, "utmi_wide", 9) == 0) { reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); reg |= DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS); } else { reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); reg |= DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS); } DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); OF_prop_free(phy_type); } static void snps_dwc3_do_quirks(struct snps_dwc3_softc *sc) { - uint32_t reg; + struct xhci_softc *xsc; + uint32_t ghwp0, reg; + ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); if (device_has_property(sc->dev, "snps,dis-u2-freeclk-exists-quirk")) reg &= ~DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; else reg |= DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; if (device_has_property(sc->dev, "snps,dis_u2_susphy_quirk")) reg &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; - else + else if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == + DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) reg |= DWC3_GUSB2PHYCFG0_SUSPENDUSB20; if (device_has_property(sc->dev, "snps,dis_enblslpm_quirk")) reg &= ~DWC3_GUSB2PHYCFG0_ENBLSLPM; else reg |= DWC3_GUSB2PHYCFG0_ENBLSLPM; DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); reg = DWC3_READ(sc, DWC3_GUCTL1); if (device_has_property(sc->dev, "snps,dis-tx-ipgap-linecheck-quirk")) reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; DWC3_WRITE(sc, DWC3_GUCTL1, reg); reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); if (device_has_property(sc->dev, "snps,dis-del-phy-power-chg-quirk")) reg &= ~DWC3_GUSB3PIPECTL0_DELAYP1TRANS; if (device_has_property(sc->dev, "snps,dis_rxdet_inp3_quirk")) reg |= DWC3_GUSB3PIPECTL0_DISRXDETINP3; + if (device_has_property(sc->dev, "snps,dis_u3_susphy_quirk")) + reg &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3; + else if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == + DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) + reg |= DWC3_GUSB3PIPECTL0_SUSPENDUSB3; DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, reg); + + /* Port Disable does not work on <= 3.00a. Disable PORT_PED. */ + if ((sc->snpsid & 0xffff) <= 0x300a) { + xsc = &sc->sc; + xsc->sc_quirks |= XHCI_QUIRK_DISABLE_PORT_PED; + } } static int snps_dwc3_probe(device_t dev) { char dr_mode[16]; ssize_t s; if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); s = device_get_property(dev, "dr_mode", dr_mode, sizeof(dr_mode), DEVICE_PROP_BUFFER); if (s == -1) { device_printf(dev, "Cannot determine dr_mode\n"); return (ENXIO); } if (strcmp(dr_mode, "host") != 0) { device_printf(dev, "Found dr_mode '%s' but only 'host' supported. s=%zd\n", dr_mode, s); return (ENXIO); } device_set_desc(dev, "Synopsys Designware DWC3"); return (BUS_PROBE_DEFAULT); } static int snps_dwc3_attach(device_t dev) { struct snps_dwc3_softc *sc; int rid = 0; sc = device_get_softc(dev); sc->dev = dev; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "Failed to map memory\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->mem_res); sc->bsh = rman_get_bushandle(sc->mem_res); + sc->snpsid = DWC3_READ(sc, DWC3_GSNPSID); if (bootverbose) - device_printf(dev, "snps id: %x\n", DWC3_READ(sc, DWC3_GSNPSID)); + device_printf(sc->dev, "snps id: %#012x\n", sc->snpsid); +#ifdef DWC3_DEBUG + snps_dwc3_dump_ctrlparams(sc); +#endif /* Get the phys */ sc->node = ofw_bus_get_node(dev); phy_get_by_ofw_name(dev, sc->node, "usb2-phy", &sc->usb2_phy); phy_get_by_ofw_name(dev, sc->node, "usb3-phy", &sc->usb3_phy); snps_dwc3_reset(sc); snps_dwc3_configure_host(sc); snps_dwc3_configure_phy(sc); snps_dwc3_do_quirks(sc); #if 0 snsp_dwc3_dump_regs(sc); #endif snps_dwc3_attach_xhci(dev); return (0); } static device_method_t snps_dwc3_methods[] = { /* Device interface */ DEVMETHOD(device_probe, snps_dwc3_probe), DEVMETHOD(device_attach, snps_dwc3_attach), DEVMETHOD_END }; static driver_t snps_dwc3_driver = { "xhci", snps_dwc3_methods, sizeof(struct snps_dwc3_softc) }; static devclass_t snps_dwc3_devclass; DRIVER_MODULE(snps_dwc3, simplebus, snps_dwc3_driver, snps_dwc3_devclass, 0, 0); MODULE_DEPEND(snps_dwc3, xhci, 1, 1, 1); diff --git a/sys/dev/usb/controller/dwc3.h b/sys/dev/usb/controller/dwc3.h index 862e17b1bcd9..83951d327c8c 100644 --- a/sys/dev/usb/controller/dwc3.h +++ b/sys/dev/usb/controller/dwc3.h @@ -1,118 +1,121 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2019 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef _DWC3_H_ #define _DWC3_H_ #define DWC3_GSBUSCFG0 0xc100 #define DWC3_GSBUSCFG1 0xc104 #define DWC3_GTXTHRCFG 0xc108 #define DWC3_GRXTHRCFG 0xc10C /* Global Core Control Register */ #define DWC3_GCTL 0xc110 #define DWC3_GCTL_PRTCAPDIR_MASK (0x3 << 12) #define DWC3_GCTL_PRTCAPDIR_HOST (0x1 << 12) #define DWC3_GCTL_PRTCAPDIR_DEVICE (0x2 << 12) #define DWC3_GCTL_CORESOFTRESET (1 << 11) #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) #define DWC3_GPMSTS 0xc114 #define DWC3_GSTS 0xc118 #define DWC3_GUCTL1 0xc11c #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS (1 << 28) #define DWC3_GSNPSID 0xc120 #define DWC3_GGPIO 0xc124 #define DWC3_GUID 0xc128 #define DWC3_GUCTL 0xc12C #define DWC3_GUCTL_HOST_AUTO_RETRY (1 << 14) #define DWC3_GBUSERRADDRLO 0xc130 #define DWC3_GBUSERRADDRHI 0xc134 #define DWC3_GPRTBIMAPLO 0xc138 #define DWC3_GHWPARAMS0 0xc140 +#define DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE 0x2 +#define DWC3_GHWPARAMS0_MODE_MASK 0x3 #define DWC3_GHWPARAMS1 0xc144 #define DWC3_GHWPARAMS2 0xc148 #define DWC3_GHWPARAMS3 0xc14C #define DWC3_GHWPARAMS4 0xc150 #define DWC3_GHWPARAMS5 0xc154 #define DWC3_GHWPARAMS6 0xc158 #define DWC3_GHWPARAMS7 0xc15C #define DWC3_GDBGFIFOSPACE 0xc160 #define DWC3_GDBGLTSSM 0xc164 #define DWC3_GDBGLNMCC 0xc168 #define DWC3_GDBGBMU 0xc16C #define DWC3_GDBGLSPMUX 0xc170 #define DWC3_GDBGLSP 0xc174 #define DWC3_GDBGEPINFO0 0xc178 #define DWC3_GDBGEPINFO1 0xc17C #define DWC3_GPRTBIMAP_HSLO 0xc180 #define DWC3_GPRTBIMAP_FSLO 0xc188 #define DWC3_GUSB2PHYCFG0 0xc200 #define DWC3_GUSB2PHYCFG0_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS (1 << 30) #define DWC3_GUSB2PHYCFG0_USBTRDTIM(n) ((n) << 10) #define DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS 9 #define DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS 5 #define DWC3_GUSB2PHYCFG0_ENBLSLPM (1 << 8) #define DWC3_GUSB2PHYCFG0_PHYSEL(x) ((x >> 7) & 0x1) /* 0 = USB2.0, 1 = USB1.1 */ #define DWC3_GUSB2PHYCFG0_SUSPENDUSB20 (1 << 6) #define DWC3_GUSB2PHYCFG0_ULPI_UTMI_SEL (1 << 4) #define DWC3_GUSB2PHYCFG0_PHYIF (1 << 3) #define DWC3_GUSB3PIPECTL0 0xc2c0 #define DWC3_GUSB3PIPECTL0_PHYSOFTRST (1 << 31) #define DWC3_GUSB3PIPECTL0_DISRXDETINP3 (1 << 28) #define DWC3_GUSB3PIPECTL0_DELAYP1TRANS (1 << 18) +#define DWC3_GUSB3PIPECTL0_SUSPENDUSB3 (1 << 17) #define DWC3_GTXFIFOSIZ(x) (0xc300 + 0x4 * (x)) #define DWC3_GRXFIFOSIZ(x) (0xc380 + 0x4 * (x)) #define DWC3_GEVNTADRLO0 0xc400 #define DWC3_GEVNTADRHI0 0xc404 #define DWC3_GEVNTSIZ0 0xc408 #define DWC3_GEVNTCOUNT0 0xc40C #define DWC3_GHWPARAMS8 0xc600 #define DWC3_GTXFIFOPRIDEV 0xc610 #define DWC3_GTXFIFOPRIHST 0xc618 #define DWC3_GRXFIFOPRIHST 0xc61c #define DWC3_GFIFOPRIDBC 0xc620 #define DWC3_GDMAHLRATIO 0xc624 #define DWC3_GFLADJ 0xc630 #define DWC3_DCFG 0xc700 #define DWC3_DCTL 0xc704 #define DWC3_DEVTEN 0xc708 #define DWC3_DSTS 0xc70C #define DWC3_DGCMDPAR 0xc710 #define DWC3_DGCMD 0xc714 #define DWC3_DALEPENA 0xc720 #endif /* _DWC3_H_ */