diff --git a/sys/dev/usb/controller/atmegadci.c b/sys/dev/usb/controller/atmegadci.c index 06bee13c3a59..84f331f557a3 100644 --- a/sys/dev/usb/controller/atmegadci.c +++ b/sys/dev/usb/controller/atmegadci.c @@ -1,2100 +1,2099 @@ /* $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * This file contains the driver for the ATMEGA series USB OTG Controller. This * driver currently only supports the DCI mode of the USB hardware. */ /* * NOTE: When the chip detects BUS-reset it will also reset the * endpoints, Function-address and more. */ #ifdef USB_GLOBAL_INCLUDE_FILE #include USB_GLOBAL_INCLUDE_FILE #else #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define USB_DEBUG_VAR atmegadci_debug #include #include #include #include #include #include #include #include #include #include #endif /* USB_GLOBAL_INCLUDE_FILE */ #include #define ATMEGA_BUS2SC(bus) \ - ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ - ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus)))) + __containerof(bus, struct atmegadci_softc, sc_bus) #define ATMEGA_PC2SC(pc) \ ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) #ifdef USB_DEBUG static int atmegadci_debug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, "USB ATMEGA DCI"); SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RWTUN, &atmegadci_debug, 0, "ATMEGA DCI debug level"); #endif #define ATMEGA_INTR_ENDPT 1 /* prototypes */ static const struct usb_bus_methods atmegadci_bus_methods; static const struct usb_pipe_methods atmegadci_device_non_isoc_methods; static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods; static atmegadci_cmd_t atmegadci_setup_rx; static atmegadci_cmd_t atmegadci_data_rx; static atmegadci_cmd_t atmegadci_data_tx; static atmegadci_cmd_t atmegadci_data_tx_sync; static void atmegadci_device_done(struct usb_xfer *, usb_error_t); static void atmegadci_do_poll(struct usb_bus *); static void atmegadci_standard_done(struct usb_xfer *); static void atmegadci_root_intr(struct atmegadci_softc *sc); /* * Here is a list of what the chip supports: */ static const struct usb_hw_ep_profile atmegadci_ep_profile[2] = { [0] = { .max_in_frame_size = 64, .max_out_frame_size = 64, .is_simplex = 1, .support_control = 1, }, [1] = { .max_in_frame_size = 64, .max_out_frame_size = 64, .is_simplex = 1, .support_bulk = 1, .support_interrupt = 1, .support_isochronous = 1, .support_in = 1, .support_out = 1, }, }; static void atmegadci_get_hw_ep_profile(struct usb_device *udev, const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) { if (ep_addr == 0) *ppf = atmegadci_ep_profile; else if (ep_addr < ATMEGA_EP_MAX) *ppf = atmegadci_ep_profile + 1; else *ppf = NULL; } static void atmegadci_clocks_on(struct atmegadci_softc *sc) { if (sc->sc_flags.clocks_off && sc->sc_flags.port_powered) { DPRINTFN(5, "\n"); /* turn on clocks */ (sc->sc_clocks_on) (&sc->sc_bus); ATMEGA_WRITE_1(sc, ATMEGA_USBCON, ATMEGA_USBCON_USBE | ATMEGA_USBCON_OTGPADE | ATMEGA_USBCON_VBUSTE); sc->sc_flags.clocks_off = 0; /* enable transceiver ? */ } } static void atmegadci_clocks_off(struct atmegadci_softc *sc) { if (!sc->sc_flags.clocks_off) { DPRINTFN(5, "\n"); /* disable Transceiver ? */ ATMEGA_WRITE_1(sc, ATMEGA_USBCON, ATMEGA_USBCON_USBE | ATMEGA_USBCON_OTGPADE | ATMEGA_USBCON_FRZCLK | ATMEGA_USBCON_VBUSTE); /* turn clocks off */ (sc->sc_clocks_off) (&sc->sc_bus); sc->sc_flags.clocks_off = 1; } } static void atmegadci_pull_up(struct atmegadci_softc *sc) { /* pullup D+, if possible */ if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) { sc->sc_flags.d_pulled_up = 1; ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); } } static void atmegadci_pull_down(struct atmegadci_softc *sc) { /* pulldown D+, if possible */ if (sc->sc_flags.d_pulled_up) { sc->sc_flags.d_pulled_up = 0; ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); } } static void atmegadci_wakeup_peer(struct atmegadci_softc *sc) { uint8_t temp; if (!sc->sc_flags.status_suspend) { return; } temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); /* wait 8 milliseconds */ /* Wait for reset to complete. */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); /* hardware should have cleared RMWKUP bit */ } static void atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) { DPRINTFN(5, "addr=%d\n", addr); addr |= ATMEGA_UDADDR_ADDEN; ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); } static uint8_t atmegadci_setup_rx(struct atmegadci_td *td) { struct atmegadci_softc *sc; struct usb_device_request req; uint16_t count; uint8_t temp; /* get pointer to softc */ sc = ATMEGA_PC2SC(td->pc); /* select endpoint number */ ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); /* check endpoint status */ temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); DPRINTFN(5, "UEINTX=0x%02x\n", temp); if (!(temp & ATMEGA_UEINTX_RXSTPI)) { goto not_complete; } /* clear did stall */ td->did_stall = 0; /* get the packet byte count */ count = (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); /* mask away undefined bits */ count &= 0x7FF; /* verify data length */ if (count != td->remainder) { DPRINTFN(0, "Invalid SETUP packet " "length, %d bytes\n", count); goto not_complete; } if (count != sizeof(req)) { DPRINTFN(0, "Unsupported SETUP packet " "length, %d bytes\n", count); goto not_complete; } /* receive data */ ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, (void *)&req, sizeof(req)); /* copy data into real buffer */ usbd_copy_in(td->pc, 0, &req, sizeof(req)); td->offset = sizeof(req); td->remainder = 0; /* sneak peek the set address */ if ((req.bmRequestType == UT_WRITE_DEVICE) && (req.bRequest == UR_SET_ADDRESS)) { sc->sc_dv_addr = req.wValue[0] & 0x7F; /* must write address before ZLP */ ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); } else { sc->sc_dv_addr = 0xFF; } /* Clear SETUP packet interrupt and all other previous interrupts */ ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0); return (0); /* complete */ not_complete: /* abort any ongoing transfer */ if (!td->did_stall) { DPRINTFN(5, "stalling\n"); ATMEGA_WRITE_1(sc, ATMEGA_UECONX, ATMEGA_UECONX_EPEN | ATMEGA_UECONX_STALLRQ); td->did_stall = 1; } if (temp & ATMEGA_UEINTX_RXSTPI) { /* clear SETUP packet interrupt */ ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); } /* we only want to know if there is a SETUP packet */ ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); return (1); /* not complete */ } static uint8_t atmegadci_data_rx(struct atmegadci_td *td) { struct atmegadci_softc *sc; struct usb_page_search buf_res; uint16_t count; uint8_t temp; uint8_t to; uint8_t got_short; to = 3; /* don't loop forever! */ got_short = 0; /* get pointer to softc */ sc = ATMEGA_PC2SC(td->pc); /* select endpoint number */ ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); repeat: /* check if any of the FIFO banks have data */ /* check endpoint status */ temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); if (temp & ATMEGA_UEINTX_RXSTPI) { if (td->remainder == 0) { /* * We are actually complete and have * received the next SETUP */ DPRINTFN(5, "faking complete\n"); return (0); /* complete */ } /* * USB Host Aborted the transfer. */ td->error = 1; return (0); /* complete */ } /* check status */ if (!(temp & (ATMEGA_UEINTX_FIFOCON | ATMEGA_UEINTX_RXOUTI))) { /* no data */ goto not_complete; } /* get the packet byte count */ count = (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); /* mask away undefined bits */ count &= 0x7FF; /* verify the packet byte count */ if (count != td->max_packet_size) { if (count < td->max_packet_size) { /* we have a short packet */ td->short_pkt = 1; got_short = 1; } else { /* invalid USB packet */ td->error = 1; return (0); /* we are complete */ } } /* verify the packet byte count */ if (count > td->remainder) { /* invalid USB packet */ td->error = 1; return (0); /* we are complete */ } while (count > 0) { usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* receive data */ ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* clear OUT packet interrupt */ ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); /* release FIFO bank */ ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); /* check if we are complete */ if ((td->remainder == 0) || got_short) { if (td->short_pkt) { /* we are complete */ return (0); } /* else need to receive a zero length packet */ } if (--to) { goto repeat; } not_complete: /* we only want to know if there is a SETUP packet or OUT packet */ ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); return (1); /* not complete */ } static uint8_t atmegadci_data_tx(struct atmegadci_td *td) { struct atmegadci_softc *sc; struct usb_page_search buf_res; uint16_t count; uint8_t to; uint8_t temp; to = 3; /* don't loop forever! */ /* get pointer to softc */ sc = ATMEGA_PC2SC(td->pc); /* select endpoint number */ ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); repeat: /* check endpoint status */ temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); if (temp & ATMEGA_UEINTX_RXSTPI) { /* * The current transfer was aborted * by the USB Host */ td->error = 1; return (0); /* complete */ } temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); if (temp & 3) { /* cannot write any data - a bank is busy */ goto not_complete; } count = td->max_packet_size; if (td->remainder < count) { /* we have a short packet */ td->short_pkt = 1; count = td->remainder; } while (count > 0) { usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* transmit data */ ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* clear IN packet interrupt */ ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); /* allocate FIFO bank */ ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); /* check remainder */ if (td->remainder == 0) { if (td->short_pkt) { return (0); /* complete */ } /* else we need to transmit a short packet */ } if (--to) { goto repeat; } not_complete: /* we only want to know if there is a SETUP packet or free IN packet */ ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); return (1); /* not complete */ } static uint8_t atmegadci_data_tx_sync(struct atmegadci_td *td) { struct atmegadci_softc *sc; uint8_t temp; /* get pointer to softc */ sc = ATMEGA_PC2SC(td->pc); /* select endpoint number */ ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); /* check endpoint status */ temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); DPRINTFN(5, "temp=0x%02x\n", temp); if (temp & ATMEGA_UEINTX_RXSTPI) { DPRINTFN(5, "faking complete\n"); /* Race condition */ return (0); /* complete */ } /* * The control endpoint has only got one bank, so if that bank * is free the packet has been transferred! */ temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); if (temp & 3) { /* cannot write any data - a bank is busy */ goto not_complete; } if (sc->sc_dv_addr != 0xFF) { /* set new address */ atmegadci_set_address(sc, sc->sc_dv_addr); } return (0); /* complete */ not_complete: /* we only want to know if there is a SETUP packet or free IN packet */ ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); return (1); /* not complete */ } static uint8_t atmegadci_xfer_do_fifo(struct usb_xfer *xfer) { struct atmegadci_td *td; DPRINTFN(9, "\n"); td = xfer->td_transfer_cache; while (1) { if ((td->func) (td)) { /* operation in progress */ break; } if (((void *)td) == xfer->td_transfer_last) { goto done; } if (td->error) { goto done; } else if (td->remainder > 0) { /* * We had a short transfer. If there is no alternate * next, stop processing ! */ if (!td->alt_next) { goto done; } } /* * Fetch the next transfer descriptor and transfer * some flags to the next transfer descriptor */ td = td->obj_next; xfer->td_transfer_cache = td; } return (1); /* not complete */ done: /* compute all actual lengths */ atmegadci_standard_done(xfer); return (0); /* complete */ } static void atmegadci_interrupt_poll(struct atmegadci_softc *sc) { struct usb_xfer *xfer; repeat: TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { if (!atmegadci_xfer_do_fifo(xfer)) { /* queue has been modified */ goto repeat; } } } static void atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) { DPRINTFN(5, "vbus = %u\n", is_on); if (is_on) { if (!sc->sc_flags.status_vbus) { sc->sc_flags.status_vbus = 1; /* complete root HUB interrupt endpoint */ atmegadci_root_intr(sc); } } else { if (sc->sc_flags.status_vbus) { sc->sc_flags.status_vbus = 0; sc->sc_flags.status_bus_reset = 0; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; /* complete root HUB interrupt endpoint */ atmegadci_root_intr(sc); } } } void atmegadci_interrupt(struct atmegadci_softc *sc) { uint8_t status; USB_BUS_LOCK(&sc->sc_bus); /* read interrupt status */ status = ATMEGA_READ_1(sc, ATMEGA_UDINT); /* clear all set interrupts */ ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); DPRINTFN(14, "UDINT=0x%02x\n", status); /* check for any bus state change interrupts */ if (status & ATMEGA_UDINT_EORSTI) { DPRINTFN(5, "end of reset\n"); /* set correct state */ sc->sc_flags.status_bus_reset = 1; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; /* disable resume interrupt */ ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, ATMEGA_UDINT_SUSPE | ATMEGA_UDINT_EORSTE); /* complete root HUB interrupt endpoint */ atmegadci_root_intr(sc); } /* * If resume and suspend is set at the same time we interpret * that like RESUME. Resume is set when there is at least 3 * milliseconds of inactivity on the USB BUS. */ if (status & ATMEGA_UDINT_WAKEUPI) { DPRINTFN(5, "resume interrupt\n"); if (sc->sc_flags.status_suspend) { /* update status bits */ sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 1; /* disable resume interrupt */ ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, ATMEGA_UDINT_SUSPE | ATMEGA_UDINT_EORSTE); /* complete root HUB interrupt endpoint */ atmegadci_root_intr(sc); } } else if (status & ATMEGA_UDINT_SUSPI) { DPRINTFN(5, "suspend interrupt\n"); if (!sc->sc_flags.status_suspend) { /* update status bits */ sc->sc_flags.status_suspend = 1; sc->sc_flags.change_suspend = 1; /* disable suspend interrupt */ ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, ATMEGA_UDINT_WAKEUPE | ATMEGA_UDINT_EORSTE); /* complete root HUB interrupt endpoint */ atmegadci_root_intr(sc); } } /* check VBUS */ status = ATMEGA_READ_1(sc, ATMEGA_USBINT); /* clear all set interrupts */ ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); if (status & ATMEGA_USBINT_VBUSTI) { uint8_t temp; DPRINTFN(5, "USBINT=0x%02x\n", status); temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); } /* check for any endpoint interrupts */ status = ATMEGA_READ_1(sc, ATMEGA_UEINT); /* the hardware will clear the UEINT bits automatically */ if (status) { DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); atmegadci_interrupt_poll(sc); } USB_BUS_UNLOCK(&sc->sc_bus); } static void atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) { struct atmegadci_td *td; /* get current Transfer Descriptor */ td = temp->td_next; temp->td = td; /* prepare for next TD */ temp->td_next = td->obj_next; /* fill out the Transfer Descriptor */ td->func = temp->func; td->pc = temp->pc; td->offset = temp->offset; td->remainder = temp->len; td->error = 0; td->did_stall = temp->did_stall; td->short_pkt = temp->short_pkt; td->alt_next = temp->setup_alt_next; } static void atmegadci_setup_standard_chain(struct usb_xfer *xfer) { struct atmegadci_std_temp temp; struct atmegadci_softc *sc; struct atmegadci_td *td; uint32_t x; uint8_t ep_no; uint8_t need_sync; DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", xfer->address, UE_GET_ADDR(xfer->endpointno), xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); temp.max_frame_size = xfer->max_frame_size; td = xfer->td_start[0]; xfer->td_transfer_first = td; xfer->td_transfer_cache = td; /* setup temp */ temp.pc = NULL; temp.td = NULL; temp.td_next = xfer->td_start[0]; temp.offset = 0; temp.setup_alt_next = xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr; temp.did_stall = !xfer->flags_int.control_stall; sc = ATMEGA_BUS2SC(xfer->xroot->bus); ep_no = (xfer->endpointno & UE_ADDR); /* check if we should prepend a setup message */ if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { temp.func = &atmegadci_setup_rx; temp.len = xfer->frlengths[0]; temp.pc = xfer->frbuffers + 0; temp.short_pkt = temp.len ? 1 : 0; /* check for last frame */ if (xfer->nframes == 1) { /* no STATUS stage yet, SETUP is last */ if (xfer->flags_int.control_act) temp.setup_alt_next = 0; } atmegadci_setup_standard_chain_sub(&temp); } x = 1; } else { x = 0; } if (x != xfer->nframes) { if (xfer->endpointno & UE_DIR_IN) { temp.func = &atmegadci_data_tx; need_sync = 1; } else { temp.func = &atmegadci_data_rx; need_sync = 0; } /* setup "pc" pointer */ temp.pc = xfer->frbuffers + x; } else { need_sync = 0; } while (x != xfer->nframes) { /* DATA0 / DATA1 message */ temp.len = xfer->frlengths[x]; x++; if (x == xfer->nframes) { if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_act) { temp.setup_alt_next = 0; } } else { temp.setup_alt_next = 0; } } if (temp.len == 0) { /* make sure that we send an USB packet */ temp.short_pkt = 0; } else { /* regular data transfer */ temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; } atmegadci_setup_standard_chain_sub(&temp); if (xfer->flags_int.isochronous_xfr) { temp.offset += temp.len; } else { /* get next Page Cache pointer */ temp.pc = xfer->frbuffers + x; } } if (xfer->flags_int.control_xfr) { /* always setup a valid "pc" pointer for status and sync */ temp.pc = xfer->frbuffers + 0; temp.len = 0; temp.short_pkt = 0; temp.setup_alt_next = 0; /* check if we need to sync */ if (need_sync) { /* we need a SYNC point after TX */ temp.func = &atmegadci_data_tx_sync; atmegadci_setup_standard_chain_sub(&temp); } /* check if we should append a status stage */ if (!xfer->flags_int.control_act) { /* * Send a DATA1 message and invert the current * endpoint direction. */ if (xfer->endpointno & UE_DIR_IN) { temp.func = &atmegadci_data_rx; need_sync = 0; } else { temp.func = &atmegadci_data_tx; need_sync = 1; } atmegadci_setup_standard_chain_sub(&temp); if (need_sync) { /* we need a SYNC point after TX */ temp.func = &atmegadci_data_tx_sync; atmegadci_setup_standard_chain_sub(&temp); } } } /* must have at least one frame! */ td = temp.td; xfer->td_transfer_last = td; } static void atmegadci_timeout(void *arg) { struct usb_xfer *xfer = arg; DPRINTF("xfer=%p\n", xfer); USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); /* transfer is transferred */ atmegadci_device_done(xfer, USB_ERR_TIMEOUT); } static void atmegadci_start_standard_chain(struct usb_xfer *xfer) { DPRINTFN(9, "\n"); /* poll one time - will turn on interrupts */ if (atmegadci_xfer_do_fifo(xfer)) { /* put transfer on interrupt queue */ usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); /* start timeout, if any */ if (xfer->timeout != 0) { usbd_transfer_timeout_ms(xfer, &atmegadci_timeout, xfer->timeout); } } } static void atmegadci_root_intr(struct atmegadci_softc *sc) { DPRINTFN(9, "\n"); USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* set port bit */ sc->sc_hub_idata[0] = 0x02; /* we only have one port */ uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); } static usb_error_t atmegadci_standard_done_sub(struct usb_xfer *xfer) { struct atmegadci_td *td; uint32_t len; uint8_t error; DPRINTFN(9, "\n"); td = xfer->td_transfer_cache; do { len = td->remainder; if (xfer->aframes != xfer->nframes) { /* * Verify the length and subtract * the remainder from "frlengths[]": */ if (len > xfer->frlengths[xfer->aframes]) { td->error = 1; } else { xfer->frlengths[xfer->aframes] -= len; } } /* Check for transfer error */ if (td->error) { /* the transfer is finished */ error = 1; td = NULL; break; } /* Check for short transfer */ if (len > 0) { if (xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr) { /* follow alt next */ if (td->alt_next) { td = td->obj_next; } else { td = NULL; } } else { /* the transfer is finished */ td = NULL; } error = 0; break; } td = td->obj_next; /* this USB frame is complete */ error = 0; break; } while (0); /* update transfer cache */ xfer->td_transfer_cache = td; return (error ? USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); } static void atmegadci_standard_done(struct usb_xfer *xfer) { usb_error_t err = 0; DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", xfer, xfer->endpoint); /* reset scanner */ xfer->td_transfer_cache = xfer->td_transfer_first; if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { err = atmegadci_standard_done_sub(xfer); } xfer->aframes = 1; if (xfer->td_transfer_cache == NULL) { goto done; } } while (xfer->aframes != xfer->nframes) { err = atmegadci_standard_done_sub(xfer); xfer->aframes++; if (xfer->td_transfer_cache == NULL) { goto done; } } if (xfer->flags_int.control_xfr && !xfer->flags_int.control_act) { err = atmegadci_standard_done_sub(xfer); } done: atmegadci_device_done(xfer, err); } /*------------------------------------------------------------------------* * atmegadci_device_done * * NOTE: this function can be called more than one time on the * same USB transfer! *------------------------------------------------------------------------*/ static void atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error) { struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); uint8_t ep_no; USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", xfer, xfer->endpoint, error); if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { ep_no = (xfer->endpointno & UE_ADDR); /* select endpoint number */ ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); /* disable endpoint interrupt */ ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); DPRINTFN(15, "disabled interrupts!\n"); } /* dequeue transfer and start next transfer */ usbd_transfer_done(xfer, error); } static void atmegadci_xfer_stall(struct usb_xfer *xfer) { atmegadci_device_done(xfer, USB_ERR_STALLED); } static void atmegadci_set_stall(struct usb_device *udev, struct usb_endpoint *ep, uint8_t *did_stall) { struct atmegadci_softc *sc; uint8_t ep_no; USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); DPRINTFN(5, "endpoint=%p\n", ep); sc = ATMEGA_BUS2SC(udev->bus); /* get endpoint number */ ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); /* select endpoint number */ ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); /* set stall */ ATMEGA_WRITE_1(sc, ATMEGA_UECONX, ATMEGA_UECONX_EPEN | ATMEGA_UECONX_STALLRQ); } static void atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) { uint8_t temp; if (ep_type == UE_CONTROL) { /* clearing stall is not needed */ return; } /* select endpoint number */ ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); /* set endpoint reset */ ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); /* clear endpoint reset */ ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); /* set stall */ ATMEGA_WRITE_1(sc, ATMEGA_UECONX, ATMEGA_UECONX_EPEN | ATMEGA_UECONX_STALLRQ); /* reset data toggle */ ATMEGA_WRITE_1(sc, ATMEGA_UECONX, ATMEGA_UECONX_EPEN | ATMEGA_UECONX_RSTDT); /* clear stall */ ATMEGA_WRITE_1(sc, ATMEGA_UECONX, ATMEGA_UECONX_EPEN | ATMEGA_UECONX_STALLRQC); do { if (ep_type == UE_BULK) { temp = ATMEGA_UECFG0X_EPTYPE2; } else if (ep_type == UE_INTERRUPT) { temp = ATMEGA_UECFG0X_EPTYPE3; } else { temp = ATMEGA_UECFG0X_EPTYPE1; } if (ep_dir & UE_DIR_IN) { temp |= ATMEGA_UECFG0X_EPDIR; } /* two banks, 64-bytes wMaxPacket */ ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, ATMEGA_UECFG1X_ALLOC | ATMEGA_UECFG1X_EPBK0 | /* one bank */ ATMEGA_UECFG1X_EPSIZE(3)); temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); if (!(temp & ATMEGA_UESTA0X_CFGOK)) { device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n"); } } while (0); } static void atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) { struct atmegadci_softc *sc; struct usb_endpoint_descriptor *ed; DPRINTFN(5, "endpoint=%p\n", ep); USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); /* check mode */ if (udev->flags.usb_mode != USB_MODE_DEVICE) { /* not supported */ return; } /* get softc */ sc = ATMEGA_BUS2SC(udev->bus); /* get endpoint descriptor */ ed = ep->edesc; /* reset endpoint */ atmegadci_clear_stall_sub(sc, (ed->bEndpointAddress & UE_ADDR), (ed->bmAttributes & UE_XFERTYPE), (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); } usb_error_t atmegadci_init(struct atmegadci_softc *sc) { uint8_t n; DPRINTF("start\n"); /* set up the bus structure */ sc->sc_bus.usbrev = USB_REV_1_1; sc->sc_bus.methods = &atmegadci_bus_methods; USB_BUS_LOCK(&sc->sc_bus); /* make sure USB is enabled */ ATMEGA_WRITE_1(sc, ATMEGA_USBCON, ATMEGA_USBCON_USBE | ATMEGA_USBCON_FRZCLK); /* enable USB PAD regulator */ ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, ATMEGA_UHWCON_UVREGE | ATMEGA_UHWCON_UIMOD); /* the following register sets up the USB PLL, assuming 16MHz X-tal */ ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02); /* wait for PLL to lock */ for (n = 0; n != 20; n++) { if (ATMEGA_READ_1(sc, 0x49) & 0x01) break; /* wait a little bit for PLL to start */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); } /* make sure USB is enabled */ ATMEGA_WRITE_1(sc, ATMEGA_USBCON, ATMEGA_USBCON_USBE | ATMEGA_USBCON_OTGPADE | ATMEGA_USBCON_VBUSTE); /* turn on clocks */ (sc->sc_clocks_on) (&sc->sc_bus); /* make sure device is re-enumerated */ ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); /* wait a little for things to stabilise */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); /* enable interrupts */ ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, ATMEGA_UDINT_SUSPE | ATMEGA_UDINT_EORSTE); /* reset all endpoints */ ATMEGA_WRITE_1(sc, ATMEGA_UERST, (1 << ATMEGA_EP_MAX) - 1); /* disable reset */ ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); /* disable all endpoints */ for (n = 0; n != ATMEGA_EP_MAX; n++) { /* select endpoint */ ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); /* disable endpoint interrupt */ ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); /* disable endpoint */ ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); } /* turn off clocks */ atmegadci_clocks_off(sc); /* read initial VBUS state */ n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); USB_BUS_UNLOCK(&sc->sc_bus); /* catch any lost interrupts */ atmegadci_do_poll(&sc->sc_bus); return (0); /* success */ } void atmegadci_uninit(struct atmegadci_softc *sc) { USB_BUS_LOCK(&sc->sc_bus); /* turn on clocks */ (sc->sc_clocks_on) (&sc->sc_bus); /* disable interrupts */ ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); /* reset all endpoints */ ATMEGA_WRITE_1(sc, ATMEGA_UERST, (1 << ATMEGA_EP_MAX) - 1); /* disable reset */ ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); sc->sc_flags.port_powered = 0; sc->sc_flags.status_vbus = 0; sc->sc_flags.status_bus_reset = 0; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; atmegadci_pull_down(sc); atmegadci_clocks_off(sc); /* disable USB PAD regulator */ ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); USB_BUS_UNLOCK(&sc->sc_bus); } static void atmegadci_suspend(struct atmegadci_softc *sc) { /* TODO */ } static void atmegadci_resume(struct atmegadci_softc *sc) { /* TODO */ } static void atmegadci_do_poll(struct usb_bus *bus) { struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); USB_BUS_LOCK(&sc->sc_bus); atmegadci_interrupt_poll(sc); USB_BUS_UNLOCK(&sc->sc_bus); } /*------------------------------------------------------------------------* * atmegadci bulk support * atmegadci control support * atmegadci interrupt support *------------------------------------------------------------------------*/ static void atmegadci_device_non_isoc_open(struct usb_xfer *xfer) { return; } static void atmegadci_device_non_isoc_close(struct usb_xfer *xfer) { atmegadci_device_done(xfer, USB_ERR_CANCELLED); } static void atmegadci_device_non_isoc_enter(struct usb_xfer *xfer) { return; } static void atmegadci_device_non_isoc_start(struct usb_xfer *xfer) { /* setup TDs */ atmegadci_setup_standard_chain(xfer); atmegadci_start_standard_chain(xfer); } static const struct usb_pipe_methods atmegadci_device_non_isoc_methods = { .open = atmegadci_device_non_isoc_open, .close = atmegadci_device_non_isoc_close, .enter = atmegadci_device_non_isoc_enter, .start = atmegadci_device_non_isoc_start, }; /*------------------------------------------------------------------------* * atmegadci full speed isochronous support *------------------------------------------------------------------------*/ static void atmegadci_device_isoc_fs_open(struct usb_xfer *xfer) { return; } static void atmegadci_device_isoc_fs_close(struct usb_xfer *xfer) { atmegadci_device_done(xfer, USB_ERR_CANCELLED); } static void atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer) { struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); uint32_t nframes; DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", xfer, xfer->endpoint->isoc_next, xfer->nframes); /* get the current frame index */ nframes = (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); if (usbd_xfer_get_isochronous_start_frame( xfer, nframes, 0, 1, ATMEGA_FRAME_MASK, NULL)) DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); /* setup TDs */ atmegadci_setup_standard_chain(xfer); } static void atmegadci_device_isoc_fs_start(struct usb_xfer *xfer) { /* start TD chain */ atmegadci_start_standard_chain(xfer); } static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods = { .open = atmegadci_device_isoc_fs_open, .close = atmegadci_device_isoc_fs_close, .enter = atmegadci_device_isoc_fs_enter, .start = atmegadci_device_isoc_fs_start, }; /*------------------------------------------------------------------------* * atmegadci root control support *------------------------------------------------------------------------* * Simulate a hardware HUB by handling all the necessary requests. *------------------------------------------------------------------------*/ static const struct usb_device_descriptor atmegadci_devd = { .bLength = sizeof(struct usb_device_descriptor), .bDescriptorType = UDESC_DEVICE, .bcdUSB = {0x00, 0x02}, .bDeviceClass = UDCLASS_HUB, .bDeviceSubClass = UDSUBCLASS_HUB, .bDeviceProtocol = UDPROTO_FSHUB, .bMaxPacketSize = 64, .bcdDevice = {0x00, 0x01}, .iManufacturer = 1, .iProduct = 2, .bNumConfigurations = 1, }; static const struct atmegadci_config_desc atmegadci_confd = { .confd = { .bLength = sizeof(struct usb_config_descriptor), .bDescriptorType = UDESC_CONFIG, .wTotalLength[0] = sizeof(atmegadci_confd), .bNumInterface = 1, .bConfigurationValue = 1, .iConfiguration = 0, .bmAttributes = UC_SELF_POWERED, .bMaxPower = 0, }, .ifcd = { .bLength = sizeof(struct usb_interface_descriptor), .bDescriptorType = UDESC_INTERFACE, .bNumEndpoints = 1, .bInterfaceClass = UICLASS_HUB, .bInterfaceSubClass = UISUBCLASS_HUB, .bInterfaceProtocol = 0, }, .endpd = { .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = UDESC_ENDPOINT, .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), .bmAttributes = UE_INTERRUPT, .wMaxPacketSize[0] = 8, .bInterval = 255, }, }; #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } static const struct usb_hub_descriptor_min atmegadci_hubd = { .bDescLength = sizeof(atmegadci_hubd), .bDescriptorType = UDESC_HUB, .bNbrPorts = 1, HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), .bPwrOn2PwrGood = 50, .bHubContrCurrent = 0, .DeviceRemovable = {0}, /* port is removable */ }; #define STRING_VENDOR \ "A\0T\0M\0E\0G\0A" #define STRING_PRODUCT \ "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); static usb_error_t atmegadci_roothub_exec(struct usb_device *udev, struct usb_device_request *req, const void **pptr, uint16_t *plength) { struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); const void *ptr; uint16_t len; uint16_t value; uint16_t index; uint8_t temp; usb_error_t err; USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* buffer reset */ ptr = (const void *)&sc->sc_hub_temp; len = 0; err = 0; value = UGETW(req->wValue); index = UGETW(req->wIndex); /* demultiplex the control request */ switch (req->bmRequestType) { case UT_READ_DEVICE: switch (req->bRequest) { case UR_GET_DESCRIPTOR: goto tr_handle_get_descriptor; case UR_GET_CONFIG: goto tr_handle_get_config; case UR_GET_STATUS: goto tr_handle_get_status; default: goto tr_stalled; } break; case UT_WRITE_DEVICE: switch (req->bRequest) { case UR_SET_ADDRESS: goto tr_handle_set_address; case UR_SET_CONFIG: goto tr_handle_set_config; case UR_CLEAR_FEATURE: goto tr_valid; /* nop */ case UR_SET_DESCRIPTOR: goto tr_valid; /* nop */ case UR_SET_FEATURE: default: goto tr_stalled; } break; case UT_WRITE_ENDPOINT: switch (req->bRequest) { case UR_CLEAR_FEATURE: switch (UGETW(req->wValue)) { case UF_ENDPOINT_HALT: goto tr_handle_clear_halt; case UF_DEVICE_REMOTE_WAKEUP: goto tr_handle_clear_wakeup; default: goto tr_stalled; } break; case UR_SET_FEATURE: switch (UGETW(req->wValue)) { case UF_ENDPOINT_HALT: goto tr_handle_set_halt; case UF_DEVICE_REMOTE_WAKEUP: goto tr_handle_set_wakeup; default: goto tr_stalled; } break; case UR_SYNCH_FRAME: goto tr_valid; /* nop */ default: goto tr_stalled; } break; case UT_READ_ENDPOINT: switch (req->bRequest) { case UR_GET_STATUS: goto tr_handle_get_ep_status; default: goto tr_stalled; } break; case UT_WRITE_INTERFACE: switch (req->bRequest) { case UR_SET_INTERFACE: goto tr_handle_set_interface; case UR_CLEAR_FEATURE: goto tr_valid; /* nop */ case UR_SET_FEATURE: default: goto tr_stalled; } break; case UT_READ_INTERFACE: switch (req->bRequest) { case UR_GET_INTERFACE: goto tr_handle_get_interface; case UR_GET_STATUS: goto tr_handle_get_iface_status; default: goto tr_stalled; } break; case UT_WRITE_CLASS_INTERFACE: case UT_WRITE_VENDOR_INTERFACE: /* XXX forward */ break; case UT_READ_CLASS_INTERFACE: case UT_READ_VENDOR_INTERFACE: /* XXX forward */ break; case UT_WRITE_CLASS_DEVICE: switch (req->bRequest) { case UR_CLEAR_FEATURE: goto tr_valid; case UR_SET_DESCRIPTOR: case UR_SET_FEATURE: break; default: goto tr_stalled; } break; case UT_WRITE_CLASS_OTHER: switch (req->bRequest) { case UR_CLEAR_FEATURE: goto tr_handle_clear_port_feature; case UR_SET_FEATURE: goto tr_handle_set_port_feature; case UR_CLEAR_TT_BUFFER: case UR_RESET_TT: case UR_STOP_TT: goto tr_valid; default: goto tr_stalled; } break; case UT_READ_CLASS_OTHER: switch (req->bRequest) { case UR_GET_TT_STATE: goto tr_handle_get_tt_state; case UR_GET_STATUS: goto tr_handle_get_port_status; default: goto tr_stalled; } break; case UT_READ_CLASS_DEVICE: switch (req->bRequest) { case UR_GET_DESCRIPTOR: goto tr_handle_get_class_descriptor; case UR_GET_STATUS: goto tr_handle_get_class_status; default: goto tr_stalled; } break; default: goto tr_stalled; } goto tr_valid; tr_handle_get_descriptor: switch (value >> 8) { case UDESC_DEVICE: if (value & 0xff) { goto tr_stalled; } len = sizeof(atmegadci_devd); ptr = (const void *)&atmegadci_devd; goto tr_valid; case UDESC_CONFIG: if (value & 0xff) { goto tr_stalled; } len = sizeof(atmegadci_confd); ptr = (const void *)&atmegadci_confd; goto tr_valid; case UDESC_STRING: switch (value & 0xff) { case 0: /* Language table */ len = sizeof(usb_string_lang_en); ptr = (const void *)&usb_string_lang_en; goto tr_valid; case 1: /* Vendor */ len = sizeof(atmegadci_vendor); ptr = (const void *)&atmegadci_vendor; goto tr_valid; case 2: /* Product */ len = sizeof(atmegadci_product); ptr = (const void *)&atmegadci_product; goto tr_valid; default: break; } break; default: goto tr_stalled; } goto tr_stalled; tr_handle_get_config: len = 1; sc->sc_hub_temp.wValue[0] = sc->sc_conf; goto tr_valid; tr_handle_get_status: len = 2; USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); goto tr_valid; tr_handle_set_address: if (value & 0xFF00) { goto tr_stalled; } sc->sc_rt_addr = value; goto tr_valid; tr_handle_set_config: if (value >= 2) { goto tr_stalled; } sc->sc_conf = value; goto tr_valid; tr_handle_get_interface: len = 1; sc->sc_hub_temp.wValue[0] = 0; goto tr_valid; tr_handle_get_tt_state: tr_handle_get_class_status: tr_handle_get_iface_status: tr_handle_get_ep_status: len = 2; USETW(sc->sc_hub_temp.wValue, 0); goto tr_valid; tr_handle_set_halt: tr_handle_set_interface: tr_handle_set_wakeup: tr_handle_clear_wakeup: tr_handle_clear_halt: goto tr_valid; tr_handle_clear_port_feature: if (index != 1) { goto tr_stalled; } DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); switch (value) { case UHF_PORT_SUSPEND: atmegadci_wakeup_peer(sc); break; case UHF_PORT_ENABLE: sc->sc_flags.port_enabled = 0; break; case UHF_PORT_TEST: case UHF_PORT_INDICATOR: case UHF_C_PORT_ENABLE: case UHF_C_PORT_OVER_CURRENT: case UHF_C_PORT_RESET: /* nops */ break; case UHF_PORT_POWER: sc->sc_flags.port_powered = 0; atmegadci_pull_down(sc); atmegadci_clocks_off(sc); break; case UHF_C_PORT_CONNECTION: /* clear connect change flag */ sc->sc_flags.change_connect = 0; if (!sc->sc_flags.status_bus_reset) { /* we are not connected */ break; } /* configure the control endpoint */ /* select endpoint number */ ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); /* set endpoint reset */ ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); /* clear endpoint reset */ ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); /* enable and stall endpoint */ ATMEGA_WRITE_1(sc, ATMEGA_UECONX, ATMEGA_UECONX_EPEN | ATMEGA_UECONX_STALLRQ); /* one bank, 64-bytes wMaxPacket */ ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, ATMEGA_UECFG0X_EPTYPE0); ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, ATMEGA_UECFG1X_ALLOC | ATMEGA_UECFG1X_EPBK0 | ATMEGA_UECFG1X_EPSIZE(3)); /* check valid config */ temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); if (!(temp & ATMEGA_UESTA0X_CFGOK)) { device_printf(sc->sc_bus.bdev, "Chip rejected EP0 configuration\n"); } break; case UHF_C_PORT_SUSPEND: sc->sc_flags.change_suspend = 0; break; default: err = USB_ERR_IOERROR; goto done; } goto tr_valid; tr_handle_set_port_feature: if (index != 1) { goto tr_stalled; } DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); switch (value) { case UHF_PORT_ENABLE: sc->sc_flags.port_enabled = 1; break; case UHF_PORT_SUSPEND: case UHF_PORT_RESET: case UHF_PORT_TEST: case UHF_PORT_INDICATOR: /* nops */ break; case UHF_PORT_POWER: sc->sc_flags.port_powered = 1; break; default: err = USB_ERR_IOERROR; goto done; } goto tr_valid; tr_handle_get_port_status: DPRINTFN(9, "UR_GET_PORT_STATUS\n"); if (index != 1) { goto tr_stalled; } if (sc->sc_flags.status_vbus) { atmegadci_clocks_on(sc); atmegadci_pull_up(sc); } else { atmegadci_pull_down(sc); atmegadci_clocks_off(sc); } /* Select FULL-speed and Device Side Mode */ value = UPS_PORT_MODE_DEVICE; if (sc->sc_flags.port_powered) { value |= UPS_PORT_POWER; } if (sc->sc_flags.port_enabled) { value |= UPS_PORT_ENABLED; } if (sc->sc_flags.status_vbus && sc->sc_flags.status_bus_reset) { value |= UPS_CURRENT_CONNECT_STATUS; } if (sc->sc_flags.status_suspend) { value |= UPS_SUSPEND; } USETW(sc->sc_hub_temp.ps.wPortStatus, value); value = 0; if (sc->sc_flags.change_connect) { value |= UPS_C_CONNECT_STATUS; } if (sc->sc_flags.change_suspend) { value |= UPS_C_SUSPEND; } USETW(sc->sc_hub_temp.ps.wPortChange, value); len = sizeof(sc->sc_hub_temp.ps); goto tr_valid; tr_handle_get_class_descriptor: if (value & 0xFF) { goto tr_stalled; } ptr = (const void *)&atmegadci_hubd; len = sizeof(atmegadci_hubd); goto tr_valid; tr_stalled: err = USB_ERR_STALLED; tr_valid: done: *plength = len; *pptr = ptr; return (err); } static void atmegadci_xfer_setup(struct usb_setup_params *parm) { const struct usb_hw_ep_profile *pf; struct atmegadci_softc *sc; struct usb_xfer *xfer; void *last_obj; uint32_t ntd; uint32_t n; uint8_t ep_no; sc = ATMEGA_BUS2SC(parm->udev->bus); xfer = parm->curr_xfer; /* * NOTE: This driver does not use any of the parameters that * are computed from the following values. Just set some * reasonable dummies: */ parm->hc_max_packet_size = 0x500; parm->hc_max_packet_count = 1; parm->hc_max_frame_size = 0x500; usbd_transfer_setup_sub(parm); /* * compute maximum number of TDs */ if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ + 1 /* SYNC 2 */ ; } else { ntd = xfer->nframes + 1 /* SYNC */ ; } /* * check if "usbd_transfer_setup_sub" set an error */ if (parm->err) return; /* * allocate transfer descriptors */ last_obj = NULL; /* * get profile stuff */ ep_no = xfer->endpointno & UE_ADDR; atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); if (pf == NULL) { /* should not happen */ parm->err = USB_ERR_INVAL; return; } /* align data */ parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); for (n = 0; n != ntd; n++) { struct atmegadci_td *td; if (parm->buf) { td = USB_ADD_BYTES(parm->buf, parm->size[0]); /* init TD */ td->max_packet_size = xfer->max_packet_size; td->ep_no = ep_no; if (pf->support_multi_buffer) { td->support_multi_buffer = 1; } td->obj_next = last_obj; last_obj = td; } parm->size[0] += sizeof(*td); } xfer->td_start[0] = last_obj; } static void atmegadci_xfer_unsetup(struct usb_xfer *xfer) { return; } static void atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, struct usb_endpoint *ep) { struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode, sc->sc_rt_addr, udev->device_index); if (udev->device_index != sc->sc_rt_addr) { if (udev->speed != USB_SPEED_FULL) { /* not supported */ return; } if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) ep->methods = &atmegadci_device_isoc_fs_methods; else ep->methods = &atmegadci_device_non_isoc_methods; } } static void atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) { struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); switch (state) { case USB_HW_POWER_SUSPEND: atmegadci_suspend(sc); break; case USB_HW_POWER_SHUTDOWN: atmegadci_uninit(sc); break; case USB_HW_POWER_RESUME: atmegadci_resume(sc); break; default: break; } } static const struct usb_bus_methods atmegadci_bus_methods = { .endpoint_init = &atmegadci_ep_init, .xfer_setup = &atmegadci_xfer_setup, .xfer_unsetup = &atmegadci_xfer_unsetup, .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, .xfer_stall = &atmegadci_xfer_stall, .set_stall = &atmegadci_set_stall, .clear_stall = &atmegadci_clear_stall, .roothub_exec = &atmegadci_roothub_exec, .xfer_poll = &atmegadci_do_poll, .set_hw_power_sleep = &atmegadci_set_hw_power_sleep, }; diff --git a/sys/dev/usb/controller/avr32dci.c b/sys/dev/usb/controller/avr32dci.c index 0ab9a8ff665d..67255f051855 100644 --- a/sys/dev/usb/controller/avr32dci.c +++ b/sys/dev/usb/controller/avr32dci.c @@ -1,2055 +1,2054 @@ /* $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * This file contains the driver for the AVR32 series USB Device * Controller */ /* * NOTE: When the chip detects BUS-reset it will also reset the * endpoints, Function-address and more. */ #ifdef USB_GLOBAL_INCLUDE_FILE #include USB_GLOBAL_INCLUDE_FILE #else #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define USB_DEBUG_VAR avr32dci_debug #include #include #include #include #include #include #include #include #include #include #endif /* USB_GLOBAL_INCLUDE_FILE */ #include #define AVR32_BUS2SC(bus) \ - ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \ - ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus)))) + __containerof(bus, struct avr32dci_softc, sc_bus) #define AVR32_PC2SC(pc) \ AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) #ifdef USB_DEBUG static int avr32dci_debug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, "USB AVR32 DCI"); SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RWTUN, &avr32dci_debug, 0, "AVR32 DCI debug level"); #endif #define AVR32_INTR_ENDPT 1 /* prototypes */ static const struct usb_bus_methods avr32dci_bus_methods; static const struct usb_pipe_methods avr32dci_device_non_isoc_methods; static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods; static avr32dci_cmd_t avr32dci_setup_rx; static avr32dci_cmd_t avr32dci_data_rx; static avr32dci_cmd_t avr32dci_data_tx; static avr32dci_cmd_t avr32dci_data_tx_sync; static void avr32dci_device_done(struct usb_xfer *, usb_error_t); static void avr32dci_do_poll(struct usb_bus *); static void avr32dci_standard_done(struct usb_xfer *); static void avr32dci_root_intr(struct avr32dci_softc *sc); /* * Here is a list of what the chip supports: */ static const struct usb_hw_ep_profile avr32dci_ep_profile[4] = { [0] = { .max_in_frame_size = 64, .max_out_frame_size = 64, .is_simplex = 1, .support_control = 1, }, [1] = { .max_in_frame_size = 512, .max_out_frame_size = 512, .is_simplex = 1, .support_bulk = 1, .support_interrupt = 1, .support_isochronous = 1, .support_in = 1, .support_out = 1, }, [2] = { .max_in_frame_size = 64, .max_out_frame_size = 64, .is_simplex = 1, .support_bulk = 1, .support_interrupt = 1, .support_in = 1, .support_out = 1, }, [3] = { .max_in_frame_size = 1024, .max_out_frame_size = 1024, .is_simplex = 1, .support_bulk = 1, .support_interrupt = 1, .support_isochronous = 1, .support_in = 1, .support_out = 1, }, }; static void avr32dci_get_hw_ep_profile(struct usb_device *udev, const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) { if (ep_addr == 0) *ppf = avr32dci_ep_profile; else if (ep_addr < 3) *ppf = avr32dci_ep_profile + 1; else if (ep_addr < 5) *ppf = avr32dci_ep_profile + 2; else if (ep_addr < 7) *ppf = avr32dci_ep_profile + 3; else *ppf = NULL; } static void avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) { uint32_t temp; temp = AVR32_READ_4(sc, AVR32_CTRL); temp |= set; temp &= ~clear; AVR32_WRITE_4(sc, AVR32_CTRL, temp); } static void avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) { uint32_t temp; temp = AVR32_READ_4(sc, AVR32_IEN); temp |= set; temp &= ~clear; AVR32_WRITE_4(sc, AVR32_IEN, temp); } static void avr32dci_clocks_on(struct avr32dci_softc *sc) { if (sc->sc_flags.clocks_off && sc->sc_flags.port_powered) { DPRINTFN(5, "\n"); /* turn on clocks */ (sc->sc_clocks_on) (&sc->sc_bus); avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); sc->sc_flags.clocks_off = 0; } } static void avr32dci_clocks_off(struct avr32dci_softc *sc) { if (!sc->sc_flags.clocks_off) { DPRINTFN(5, "\n"); avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA); /* turn clocks off */ (sc->sc_clocks_off) (&sc->sc_bus); sc->sc_flags.clocks_off = 1; } } static void avr32dci_pull_up(struct avr32dci_softc *sc) { /* pullup D+, if possible */ if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) { sc->sc_flags.d_pulled_up = 1; avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH); } } static void avr32dci_pull_down(struct avr32dci_softc *sc) { /* pulldown D+, if possible */ if (sc->sc_flags.d_pulled_up) { sc->sc_flags.d_pulled_up = 0; avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); } } static void avr32dci_wakeup_peer(struct avr32dci_softc *sc) { if (!sc->sc_flags.status_suspend) { return; } avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0); /* wait 8 milliseconds */ /* Wait for reset to complete. */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); /* hardware should have cleared RMWKUP bit */ } static void avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr) { DPRINTFN(5, "addr=%d\n", addr); avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_FADDR_EN | addr, 0); } static uint8_t avr32dci_setup_rx(struct avr32dci_td *td) { struct avr32dci_softc *sc; struct usb_device_request req; uint16_t count; uint32_t temp; /* get pointer to softc */ sc = AVR32_PC2SC(td->pc); /* check endpoint status */ temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); if (!(temp & AVR32_EPTSTA_RX_SETUP)) { goto not_complete; } /* clear did stall */ td->did_stall = 0; /* get the packet byte count */ count = AVR32_EPTSTA_BYTE_COUNT(temp); /* verify data length */ if (count != td->remainder) { DPRINTFN(0, "Invalid SETUP packet " "length, %d bytes\n", count); goto not_complete; } if (count != sizeof(req)) { DPRINTFN(0, "Unsupported SETUP packet " "length, %d bytes\n", count); goto not_complete; } /* receive data */ memcpy(&req, sc->physdata, sizeof(req)); /* copy data into real buffer */ usbd_copy_in(td->pc, 0, &req, sizeof(req)); td->offset = sizeof(req); td->remainder = 0; /* sneak peek the set address */ if ((req.bmRequestType == UT_WRITE_DEVICE) && (req.bRequest == UR_SET_ADDRESS)) { sc->sc_dv_addr = req.wValue[0] & 0x7F; /* must write address before ZLP */ avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN | AVR32_CTRL_DEV_ADDR); avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0); } else { sc->sc_dv_addr = 0xFF; } /* clear SETUP packet interrupt */ AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); return (0); /* complete */ not_complete: if (temp & AVR32_EPTSTA_RX_SETUP) { /* clear SETUP packet interrupt */ AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); } /* abort any ongoing transfer */ if (!td->did_stall) { DPRINTFN(5, "stalling\n"); AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no), AVR32_EPTSTA_FRCESTALL); td->did_stall = 1; } return (1); /* not complete */ } static uint8_t avr32dci_data_rx(struct avr32dci_td *td) { struct avr32dci_softc *sc; struct usb_page_search buf_res; uint16_t count; uint32_t temp; uint8_t to; uint8_t got_short; to = 4; /* don't loop forever! */ got_short = 0; /* get pointer to softc */ sc = AVR32_PC2SC(td->pc); repeat: /* check if any of the FIFO banks have data */ /* check endpoint status */ temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); if (temp & AVR32_EPTSTA_RX_SETUP) { if (td->remainder == 0) { /* * We are actually complete and have * received the next SETUP */ DPRINTFN(5, "faking complete\n"); return (0); /* complete */ } /* * USB Host Aborted the transfer. */ td->error = 1; return (0); /* complete */ } /* check status */ if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) { /* no data */ goto not_complete; } /* get the packet byte count */ count = AVR32_EPTSTA_BYTE_COUNT(temp); /* verify the packet byte count */ if (count != td->max_packet_size) { if (count < td->max_packet_size) { /* we have a short packet */ td->short_pkt = 1; got_short = 1; } else { /* invalid USB packet */ td->error = 1; return (0); /* we are complete */ } } /* verify the packet byte count */ if (count > td->remainder) { /* invalid USB packet */ td->error = 1; return (0); /* we are complete */ } while (count > 0) { usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* receive data */ memcpy(buf_res.buffer, sc->physdata + (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + (td->ep_no << 16) + (td->offset % td->max_packet_size), buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* clear OUT packet interrupt */ AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY); /* check if we are complete */ if ((td->remainder == 0) || got_short) { if (td->short_pkt) { /* we are complete */ return (0); } /* else need to receive a zero length packet */ } if (--to) { goto repeat; } not_complete: return (1); /* not complete */ } static uint8_t avr32dci_data_tx(struct avr32dci_td *td) { struct avr32dci_softc *sc; struct usb_page_search buf_res; uint16_t count; uint8_t to; uint32_t temp; to = 4; /* don't loop forever! */ /* get pointer to softc */ sc = AVR32_PC2SC(td->pc); repeat: /* check endpoint status */ temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); if (temp & AVR32_EPTSTA_RX_SETUP) { /* * The current transfer was aborted * by the USB Host */ td->error = 1; return (0); /* complete */ } if (temp & AVR32_EPTSTA_TX_PK_RDY) { /* cannot write any data - all banks are busy */ goto not_complete; } count = td->max_packet_size; if (td->remainder < count) { /* we have a short packet */ td->short_pkt = 1; count = td->remainder; } while (count > 0) { usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* transmit data */ memcpy(sc->physdata + (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + (td->ep_no << 16) + (td->offset % td->max_packet_size), buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* allocate FIFO bank */ AVR32_WRITE_4(sc, AVR32_EPTCTL(td->ep_no), AVR32_EPTCTL_TX_PK_RDY); /* check remainder */ if (td->remainder == 0) { if (td->short_pkt) { return (0); /* complete */ } /* else we need to transmit a short packet */ } if (--to) { goto repeat; } not_complete: return (1); /* not complete */ } static uint8_t avr32dci_data_tx_sync(struct avr32dci_td *td) { struct avr32dci_softc *sc; uint32_t temp; /* get pointer to softc */ sc = AVR32_PC2SC(td->pc); /* check endpoint status */ temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); if (temp & AVR32_EPTSTA_RX_SETUP) { DPRINTFN(5, "faking complete\n"); /* Race condition */ return (0); /* complete */ } /* * The control endpoint has only got one bank, so if that bank * is free the packet has been transferred! */ if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) { /* cannot write any data - a bank is busy */ goto not_complete; } if (sc->sc_dv_addr != 0xFF) { /* set new address */ avr32dci_set_address(sc, sc->sc_dv_addr); } return (0); /* complete */ not_complete: return (1); /* not complete */ } static uint8_t avr32dci_xfer_do_fifo(struct usb_xfer *xfer) { struct avr32dci_td *td; DPRINTFN(9, "\n"); td = xfer->td_transfer_cache; while (1) { if ((td->func) (td)) { /* operation in progress */ break; } if (((void *)td) == xfer->td_transfer_last) { goto done; } if (td->error) { goto done; } else if (td->remainder > 0) { /* * We had a short transfer. If there is no alternate * next, stop processing ! */ if (!td->alt_next) { goto done; } } /* * Fetch the next transfer descriptor and transfer * some flags to the next transfer descriptor */ td = td->obj_next; xfer->td_transfer_cache = td; } return (1); /* not complete */ done: /* compute all actual lengths */ avr32dci_standard_done(xfer); return (0); /* complete */ } static void avr32dci_interrupt_poll(struct avr32dci_softc *sc) { struct usb_xfer *xfer; repeat: TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { if (!avr32dci_xfer_do_fifo(xfer)) { /* queue has been modified */ goto repeat; } } } void avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on) { DPRINTFN(5, "vbus = %u\n", is_on); if (is_on) { if (!sc->sc_flags.status_vbus) { sc->sc_flags.status_vbus = 1; /* complete root HUB interrupt endpoint */ avr32dci_root_intr(sc); } } else { if (sc->sc_flags.status_vbus) { sc->sc_flags.status_vbus = 0; sc->sc_flags.status_bus_reset = 0; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; /* complete root HUB interrupt endpoint */ avr32dci_root_intr(sc); } } } void avr32dci_interrupt(struct avr32dci_softc *sc) { uint32_t status; USB_BUS_LOCK(&sc->sc_bus); /* read interrupt status */ status = AVR32_READ_4(sc, AVR32_INTSTA); /* clear all set interrupts */ AVR32_WRITE_4(sc, AVR32_CLRINT, status); DPRINTFN(14, "INTSTA=0x%08x\n", status); /* check for any bus state change interrupts */ if (status & AVR32_INT_ENDRESET) { DPRINTFN(5, "end of reset\n"); /* set correct state */ sc->sc_flags.status_bus_reset = 1; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; /* disable resume interrupt */ avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); /* complete root HUB interrupt endpoint */ avr32dci_root_intr(sc); } /* * If resume and suspend is set at the same time we interpret * that like RESUME. Resume is set when there is at least 3 * milliseconds of inactivity on the USB BUS. */ if (status & AVR32_INT_WAKE_UP) { DPRINTFN(5, "resume interrupt\n"); if (sc->sc_flags.status_suspend) { /* update status bits */ sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 1; /* disable resume interrupt */ avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); /* complete root HUB interrupt endpoint */ avr32dci_root_intr(sc); } } else if (status & AVR32_INT_DET_SUSPD) { DPRINTFN(5, "suspend interrupt\n"); if (!sc->sc_flags.status_suspend) { /* update status bits */ sc->sc_flags.status_suspend = 1; sc->sc_flags.change_suspend = 1; /* disable suspend interrupt */ avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP | AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD); /* complete root HUB interrupt endpoint */ avr32dci_root_intr(sc); } } /* check for any endpoint interrupts */ if (status & -AVR32_INT_EPT_INT(0)) { DPRINTFN(5, "real endpoint interrupt\n"); avr32dci_interrupt_poll(sc); } USB_BUS_UNLOCK(&sc->sc_bus); } static void avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp) { struct avr32dci_td *td; /* get current Transfer Descriptor */ td = temp->td_next; temp->td = td; /* prepare for next TD */ temp->td_next = td->obj_next; /* fill out the Transfer Descriptor */ td->func = temp->func; td->pc = temp->pc; td->offset = temp->offset; td->remainder = temp->len; td->error = 0; td->did_stall = temp->did_stall; td->short_pkt = temp->short_pkt; td->alt_next = temp->setup_alt_next; } static void avr32dci_setup_standard_chain(struct usb_xfer *xfer) { struct avr32dci_std_temp temp; struct avr32dci_softc *sc; struct avr32dci_td *td; uint32_t x; uint8_t ep_no; uint8_t need_sync; DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", xfer->address, UE_GET_ADDR(xfer->endpointno), xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); temp.max_frame_size = xfer->max_frame_size; td = xfer->td_start[0]; xfer->td_transfer_first = td; xfer->td_transfer_cache = td; /* setup temp */ temp.pc = NULL; temp.td = NULL; temp.td_next = xfer->td_start[0]; temp.offset = 0; temp.setup_alt_next = xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr; temp.did_stall = !xfer->flags_int.control_stall; sc = AVR32_BUS2SC(xfer->xroot->bus); ep_no = (xfer->endpointno & UE_ADDR); /* check if we should prepend a setup message */ if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { temp.func = &avr32dci_setup_rx; temp.len = xfer->frlengths[0]; temp.pc = xfer->frbuffers + 0; temp.short_pkt = temp.len ? 1 : 0; /* check for last frame */ if (xfer->nframes == 1) { /* no STATUS stage yet, SETUP is last */ if (xfer->flags_int.control_act) temp.setup_alt_next = 0; } avr32dci_setup_standard_chain_sub(&temp); } x = 1; } else { x = 0; } if (x != xfer->nframes) { if (xfer->endpointno & UE_DIR_IN) { temp.func = &avr32dci_data_tx; need_sync = 1; } else { temp.func = &avr32dci_data_rx; need_sync = 0; } /* setup "pc" pointer */ temp.pc = xfer->frbuffers + x; } else { need_sync = 0; } while (x != xfer->nframes) { /* DATA0 / DATA1 message */ temp.len = xfer->frlengths[x]; x++; if (x == xfer->nframes) { if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_act) { temp.setup_alt_next = 0; } } else { temp.setup_alt_next = 0; } } if (temp.len == 0) { /* make sure that we send an USB packet */ temp.short_pkt = 0; } else { /* regular data transfer */ temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; } avr32dci_setup_standard_chain_sub(&temp); if (xfer->flags_int.isochronous_xfr) { temp.offset += temp.len; } else { /* get next Page Cache pointer */ temp.pc = xfer->frbuffers + x; } } if (xfer->flags_int.control_xfr) { /* always setup a valid "pc" pointer for status and sync */ temp.pc = xfer->frbuffers + 0; temp.len = 0; temp.short_pkt = 0; temp.setup_alt_next = 0; /* check if we need to sync */ if (need_sync) { /* we need a SYNC point after TX */ temp.func = &avr32dci_data_tx_sync; avr32dci_setup_standard_chain_sub(&temp); } /* check if we should append a status stage */ if (!xfer->flags_int.control_act) { /* * Send a DATA1 message and invert the current * endpoint direction. */ if (xfer->endpointno & UE_DIR_IN) { temp.func = &avr32dci_data_rx; need_sync = 0; } else { temp.func = &avr32dci_data_tx; need_sync = 1; } avr32dci_setup_standard_chain_sub(&temp); if (need_sync) { /* we need a SYNC point after TX */ temp.func = &avr32dci_data_tx_sync; avr32dci_setup_standard_chain_sub(&temp); } } } /* must have at least one frame! */ td = temp.td; xfer->td_transfer_last = td; } static void avr32dci_timeout(void *arg) { struct usb_xfer *xfer = arg; DPRINTF("xfer=%p\n", xfer); USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); /* transfer is transferred */ avr32dci_device_done(xfer, USB_ERR_TIMEOUT); } static void avr32dci_start_standard_chain(struct usb_xfer *xfer) { DPRINTFN(9, "\n"); /* poll one time - will turn on interrupts */ if (avr32dci_xfer_do_fifo(xfer)) { uint8_t ep_no = xfer->endpointno & UE_ADDR; struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0); /* put transfer on interrupt queue */ usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); /* start timeout, if any */ if (xfer->timeout != 0) { usbd_transfer_timeout_ms(xfer, &avr32dci_timeout, xfer->timeout); } } } static void avr32dci_root_intr(struct avr32dci_softc *sc) { DPRINTFN(9, "\n"); USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* set port bit */ sc->sc_hub_idata[0] = 0x02; /* we only have one port */ uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); } static usb_error_t avr32dci_standard_done_sub(struct usb_xfer *xfer) { struct avr32dci_td *td; uint32_t len; uint8_t error; DPRINTFN(9, "\n"); td = xfer->td_transfer_cache; do { len = td->remainder; if (xfer->aframes != xfer->nframes) { /* * Verify the length and subtract * the remainder from "frlengths[]": */ if (len > xfer->frlengths[xfer->aframes]) { td->error = 1; } else { xfer->frlengths[xfer->aframes] -= len; } } /* Check for transfer error */ if (td->error) { /* the transfer is finished */ error = 1; td = NULL; break; } /* Check for short transfer */ if (len > 0) { if (xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr) { /* follow alt next */ if (td->alt_next) { td = td->obj_next; } else { td = NULL; } } else { /* the transfer is finished */ td = NULL; } error = 0; break; } td = td->obj_next; /* this USB frame is complete */ error = 0; break; } while (0); /* update transfer cache */ xfer->td_transfer_cache = td; return (error ? USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); } static void avr32dci_standard_done(struct usb_xfer *xfer) { usb_error_t err = 0; DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", xfer, xfer->endpoint); /* reset scanner */ xfer->td_transfer_cache = xfer->td_transfer_first; if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { err = avr32dci_standard_done_sub(xfer); } xfer->aframes = 1; if (xfer->td_transfer_cache == NULL) { goto done; } } while (xfer->aframes != xfer->nframes) { err = avr32dci_standard_done_sub(xfer); xfer->aframes++; if (xfer->td_transfer_cache == NULL) { goto done; } } if (xfer->flags_int.control_xfr && !xfer->flags_int.control_act) { err = avr32dci_standard_done_sub(xfer); } done: avr32dci_device_done(xfer, err); } /*------------------------------------------------------------------------* * avr32dci_device_done * * NOTE: this function can be called more than one time on the * same USB transfer! *------------------------------------------------------------------------*/ static void avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error) { struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); uint8_t ep_no; USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", xfer, xfer->endpoint, error); if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { ep_no = (xfer->endpointno & UE_ADDR); /* disable endpoint interrupt */ avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no)); DPRINTFN(15, "disabled interrupts!\n"); } /* dequeue transfer and start next transfer */ usbd_transfer_done(xfer, error); } static void avr32dci_xfer_stall(struct usb_xfer *xfer) { avr32dci_device_done(xfer, USB_ERR_STALLED); } static void avr32dci_set_stall(struct usb_device *udev, struct usb_endpoint *pipe, uint8_t *did_stall) { struct avr32dci_softc *sc; uint8_t ep_no; USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); DPRINTFN(5, "pipe=%p\n", pipe); sc = AVR32_BUS2SC(udev->bus); /* get endpoint number */ ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); /* set stall */ AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); } static void avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) { const struct usb_hw_ep_profile *pf; uint32_t temp; uint32_t epsize; uint8_t n; if (ep_type == UE_CONTROL) { /* clearing stall is not needed */ return; } /* set endpoint reset */ AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no)); /* set stall */ AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); /* reset data toggle */ AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ); /* clear stall */ AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL); if (ep_type == UE_BULK) { temp = AVR32_EPTCFG_TYPE_BULK; } else if (ep_type == UE_INTERRUPT) { temp = AVR32_EPTCFG_TYPE_INTR; } else { temp = AVR32_EPTCFG_TYPE_ISOC | AVR32_EPTCFG_NB_TRANS(1); } if (ep_dir & UE_DIR_IN) { temp |= AVR32_EPTCFG_EPDIR_IN; } avr32dci_get_hw_ep_profile(NULL, &pf, ep_no); /* compute endpoint size (use maximum) */ epsize = pf->max_in_frame_size | pf->max_out_frame_size; n = 0; while ((epsize /= 2)) n++; temp |= AVR32_EPTCFG_EPSIZE(n); /* use the maximum number of banks supported */ if (ep_no < 1) temp |= AVR32_EPTCFG_NBANK(1); else if (ep_no < 3) temp |= AVR32_EPTCFG_NBANK(2); else temp |= AVR32_EPTCFG_NBANK(3); AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp); temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no)); if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n"); } else { AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no), AVR32_EPTCTL_EPT_ENABL); } } static void avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *pipe) { struct avr32dci_softc *sc; struct usb_endpoint_descriptor *ed; DPRINTFN(5, "pipe=%p\n", pipe); USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); /* check mode */ if (udev->flags.usb_mode != USB_MODE_DEVICE) { /* not supported */ return; } /* get softc */ sc = AVR32_BUS2SC(udev->bus); /* get endpoint descriptor */ ed = pipe->edesc; /* reset endpoint */ avr32dci_clear_stall_sub(sc, (ed->bEndpointAddress & UE_ADDR), (ed->bmAttributes & UE_XFERTYPE), (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); } usb_error_t avr32dci_init(struct avr32dci_softc *sc) { uint8_t n; DPRINTF("start\n"); /* set up the bus structure */ sc->sc_bus.usbrev = USB_REV_1_1; sc->sc_bus.methods = &avr32dci_bus_methods; USB_BUS_LOCK(&sc->sc_bus); /* make sure USB is enabled */ avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); /* turn on clocks */ (sc->sc_clocks_on) (&sc->sc_bus); /* make sure device is re-enumerated */ avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); /* wait a little for things to stabilise */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); /* disable interrupts */ avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); /* enable interrupts */ avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | AVR32_INT_ENDRESET, 0); /* reset all endpoints */ AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); /* disable all endpoints */ for (n = 0; n != AVR32_EP_MAX; n++) { /* disable endpoint */ AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); } /* turn off clocks */ avr32dci_clocks_off(sc); USB_BUS_UNLOCK(&sc->sc_bus); /* catch any lost interrupts */ avr32dci_do_poll(&sc->sc_bus); return (0); /* success */ } void avr32dci_uninit(struct avr32dci_softc *sc) { uint8_t n; USB_BUS_LOCK(&sc->sc_bus); /* turn on clocks */ (sc->sc_clocks_on) (&sc->sc_bus); /* disable interrupts */ avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); /* reset all endpoints */ AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); /* disable all endpoints */ for (n = 0; n != AVR32_EP_MAX; n++) { /* disable endpoint */ AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); } sc->sc_flags.port_powered = 0; sc->sc_flags.status_vbus = 0; sc->sc_flags.status_bus_reset = 0; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; avr32dci_pull_down(sc); avr32dci_clocks_off(sc); USB_BUS_UNLOCK(&sc->sc_bus); } static void avr32dci_suspend(struct avr32dci_softc *sc) { /* TODO */ } static void avr32dci_resume(struct avr32dci_softc *sc) { /* TODO */ } static void avr32dci_do_poll(struct usb_bus *bus) { struct avr32dci_softc *sc = AVR32_BUS2SC(bus); USB_BUS_LOCK(&sc->sc_bus); avr32dci_interrupt_poll(sc); USB_BUS_UNLOCK(&sc->sc_bus); } /*------------------------------------------------------------------------* * avr32dci bulk support * avr32dci control support * avr32dci interrupt support *------------------------------------------------------------------------*/ static void avr32dci_device_non_isoc_open(struct usb_xfer *xfer) { return; } static void avr32dci_device_non_isoc_close(struct usb_xfer *xfer) { avr32dci_device_done(xfer, USB_ERR_CANCELLED); } static void avr32dci_device_non_isoc_enter(struct usb_xfer *xfer) { return; } static void avr32dci_device_non_isoc_start(struct usb_xfer *xfer) { /* setup TDs */ avr32dci_setup_standard_chain(xfer); avr32dci_start_standard_chain(xfer); } static const struct usb_pipe_methods avr32dci_device_non_isoc_methods = { .open = avr32dci_device_non_isoc_open, .close = avr32dci_device_non_isoc_close, .enter = avr32dci_device_non_isoc_enter, .start = avr32dci_device_non_isoc_start, }; /*------------------------------------------------------------------------* * avr32dci full speed isochronous support *------------------------------------------------------------------------*/ static void avr32dci_device_isoc_fs_open(struct usb_xfer *xfer) { return; } static void avr32dci_device_isoc_fs_close(struct usb_xfer *xfer) { avr32dci_device_done(xfer, USB_ERR_CANCELLED); } static void avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer) { struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); uint32_t nframes; uint8_t ep_no; DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", xfer, xfer->endpoint->isoc_next, xfer->nframes); /* get the current frame index */ ep_no = xfer->endpointno & UE_ADDR; nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8); if (usbd_xfer_get_isochronous_start_frame( xfer, nframes, 0, 1, AVR32_FRAME_MASK, NULL)) DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); /* setup TDs */ avr32dci_setup_standard_chain(xfer); } static void avr32dci_device_isoc_fs_start(struct usb_xfer *xfer) { /* start TD chain */ avr32dci_start_standard_chain(xfer); } static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods = { .open = avr32dci_device_isoc_fs_open, .close = avr32dci_device_isoc_fs_close, .enter = avr32dci_device_isoc_fs_enter, .start = avr32dci_device_isoc_fs_start, }; /*------------------------------------------------------------------------* * avr32dci root control support *------------------------------------------------------------------------* * Simulate a hardware HUB by handling all the necessary requests. *------------------------------------------------------------------------*/ static const struct usb_device_descriptor avr32dci_devd = { .bLength = sizeof(struct usb_device_descriptor), .bDescriptorType = UDESC_DEVICE, .bcdUSB = {0x00, 0x02}, .bDeviceClass = UDCLASS_HUB, .bDeviceSubClass = UDSUBCLASS_HUB, .bDeviceProtocol = UDPROTO_HSHUBSTT, .bMaxPacketSize = 64, .bcdDevice = {0x00, 0x01}, .iManufacturer = 1, .iProduct = 2, .bNumConfigurations = 1, }; static const struct usb_device_qualifier avr32dci_odevd = { .bLength = sizeof(struct usb_device_qualifier), .bDescriptorType = UDESC_DEVICE_QUALIFIER, .bcdUSB = {0x00, 0x02}, .bDeviceClass = UDCLASS_HUB, .bDeviceSubClass = UDSUBCLASS_HUB, .bDeviceProtocol = UDPROTO_FSHUB, .bMaxPacketSize0 = 0, .bNumConfigurations = 0, }; static const struct avr32dci_config_desc avr32dci_confd = { .confd = { .bLength = sizeof(struct usb_config_descriptor), .bDescriptorType = UDESC_CONFIG, .wTotalLength[0] = sizeof(avr32dci_confd), .bNumInterface = 1, .bConfigurationValue = 1, .iConfiguration = 0, .bmAttributes = UC_SELF_POWERED, .bMaxPower = 0, }, .ifcd = { .bLength = sizeof(struct usb_interface_descriptor), .bDescriptorType = UDESC_INTERFACE, .bNumEndpoints = 1, .bInterfaceClass = UICLASS_HUB, .bInterfaceSubClass = UISUBCLASS_HUB, .bInterfaceProtocol = 0, }, .endpd = { .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = UDESC_ENDPOINT, .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT), .bmAttributes = UE_INTERRUPT, .wMaxPacketSize[0] = 8, .bInterval = 255, }, }; #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } static const struct usb_hub_descriptor_min avr32dci_hubd = { .bDescLength = sizeof(avr32dci_hubd), .bDescriptorType = UDESC_HUB, .bNbrPorts = 1, HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), .bPwrOn2PwrGood = 50, .bHubContrCurrent = 0, .DeviceRemovable = {0}, /* port is removable */ }; #define STRING_VENDOR \ "A\0V\0R\0003\0002" #define STRING_PRODUCT \ "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor); USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product); static usb_error_t avr32dci_roothub_exec(struct usb_device *udev, struct usb_device_request *req, const void **pptr, uint16_t *plength) { struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); const void *ptr; uint16_t len; uint16_t value; uint16_t index; uint32_t temp; usb_error_t err; USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* buffer reset */ ptr = (const void *)&sc->sc_hub_temp; len = 0; err = 0; value = UGETW(req->wValue); index = UGETW(req->wIndex); /* demultiplex the control request */ switch (req->bmRequestType) { case UT_READ_DEVICE: switch (req->bRequest) { case UR_GET_DESCRIPTOR: goto tr_handle_get_descriptor; case UR_GET_CONFIG: goto tr_handle_get_config; case UR_GET_STATUS: goto tr_handle_get_status; default: goto tr_stalled; } break; case UT_WRITE_DEVICE: switch (req->bRequest) { case UR_SET_ADDRESS: goto tr_handle_set_address; case UR_SET_CONFIG: goto tr_handle_set_config; case UR_CLEAR_FEATURE: goto tr_valid; /* nop */ case UR_SET_DESCRIPTOR: goto tr_valid; /* nop */ case UR_SET_FEATURE: default: goto tr_stalled; } break; case UT_WRITE_ENDPOINT: switch (req->bRequest) { case UR_CLEAR_FEATURE: switch (UGETW(req->wValue)) { case UF_ENDPOINT_HALT: goto tr_handle_clear_halt; case UF_DEVICE_REMOTE_WAKEUP: goto tr_handle_clear_wakeup; default: goto tr_stalled; } break; case UR_SET_FEATURE: switch (UGETW(req->wValue)) { case UF_ENDPOINT_HALT: goto tr_handle_set_halt; case UF_DEVICE_REMOTE_WAKEUP: goto tr_handle_set_wakeup; default: goto tr_stalled; } break; case UR_SYNCH_FRAME: goto tr_valid; /* nop */ default: goto tr_stalled; } break; case UT_READ_ENDPOINT: switch (req->bRequest) { case UR_GET_STATUS: goto tr_handle_get_ep_status; default: goto tr_stalled; } break; case UT_WRITE_INTERFACE: switch (req->bRequest) { case UR_SET_INTERFACE: goto tr_handle_set_interface; case UR_CLEAR_FEATURE: goto tr_valid; /* nop */ case UR_SET_FEATURE: default: goto tr_stalled; } break; case UT_READ_INTERFACE: switch (req->bRequest) { case UR_GET_INTERFACE: goto tr_handle_get_interface; case UR_GET_STATUS: goto tr_handle_get_iface_status; default: goto tr_stalled; } break; case UT_WRITE_CLASS_INTERFACE: case UT_WRITE_VENDOR_INTERFACE: /* XXX forward */ break; case UT_READ_CLASS_INTERFACE: case UT_READ_VENDOR_INTERFACE: /* XXX forward */ break; case UT_WRITE_CLASS_DEVICE: switch (req->bRequest) { case UR_CLEAR_FEATURE: goto tr_valid; case UR_SET_DESCRIPTOR: case UR_SET_FEATURE: break; default: goto tr_stalled; } break; case UT_WRITE_CLASS_OTHER: switch (req->bRequest) { case UR_CLEAR_FEATURE: goto tr_handle_clear_port_feature; case UR_SET_FEATURE: goto tr_handle_set_port_feature; case UR_CLEAR_TT_BUFFER: case UR_RESET_TT: case UR_STOP_TT: goto tr_valid; default: goto tr_stalled; } break; case UT_READ_CLASS_OTHER: switch (req->bRequest) { case UR_GET_TT_STATE: goto tr_handle_get_tt_state; case UR_GET_STATUS: goto tr_handle_get_port_status; default: goto tr_stalled; } break; case UT_READ_CLASS_DEVICE: switch (req->bRequest) { case UR_GET_DESCRIPTOR: goto tr_handle_get_class_descriptor; case UR_GET_STATUS: goto tr_handle_get_class_status; default: goto tr_stalled; } break; default: goto tr_stalled; } goto tr_valid; tr_handle_get_descriptor: switch (value >> 8) { case UDESC_DEVICE: if (value & 0xff) { goto tr_stalled; } len = sizeof(avr32dci_devd); ptr = (const void *)&avr32dci_devd; goto tr_valid; case UDESC_DEVICE_QUALIFIER: if (value & 0xff) goto tr_stalled; len = sizeof(avr32dci_odevd); ptr = (const void *)&avr32dci_odevd; goto tr_valid; case UDESC_CONFIG: if (value & 0xff) { goto tr_stalled; } len = sizeof(avr32dci_confd); ptr = (const void *)&avr32dci_confd; goto tr_valid; case UDESC_STRING: switch (value & 0xff) { case 0: /* Language table */ len = sizeof(usb_string_lang_en); ptr = (const void *)&usb_string_lang_en; goto tr_valid; case 1: /* Vendor */ len = sizeof(avr32dci_vendor); ptr = (const void *)&avr32dci_vendor; goto tr_valid; case 2: /* Product */ len = sizeof(avr32dci_product); ptr = (const void *)&avr32dci_product; goto tr_valid; default: break; } break; default: goto tr_stalled; } goto tr_stalled; tr_handle_get_config: len = 1; sc->sc_hub_temp.wValue[0] = sc->sc_conf; goto tr_valid; tr_handle_get_status: len = 2; USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); goto tr_valid; tr_handle_set_address: if (value & 0xFF00) { goto tr_stalled; } sc->sc_rt_addr = value; goto tr_valid; tr_handle_set_config: if (value >= 2) { goto tr_stalled; } sc->sc_conf = value; goto tr_valid; tr_handle_get_interface: len = 1; sc->sc_hub_temp.wValue[0] = 0; goto tr_valid; tr_handle_get_tt_state: tr_handle_get_class_status: tr_handle_get_iface_status: tr_handle_get_ep_status: len = 2; USETW(sc->sc_hub_temp.wValue, 0); goto tr_valid; tr_handle_set_halt: tr_handle_set_interface: tr_handle_set_wakeup: tr_handle_clear_wakeup: tr_handle_clear_halt: goto tr_valid; tr_handle_clear_port_feature: if (index != 1) { goto tr_stalled; } DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); switch (value) { case UHF_PORT_SUSPEND: avr32dci_wakeup_peer(sc); break; case UHF_PORT_ENABLE: sc->sc_flags.port_enabled = 0; break; case UHF_PORT_TEST: case UHF_PORT_INDICATOR: case UHF_C_PORT_ENABLE: case UHF_C_PORT_OVER_CURRENT: case UHF_C_PORT_RESET: /* nops */ break; case UHF_PORT_POWER: sc->sc_flags.port_powered = 0; avr32dci_pull_down(sc); avr32dci_clocks_off(sc); break; case UHF_C_PORT_CONNECTION: /* clear connect change flag */ sc->sc_flags.change_connect = 0; if (!sc->sc_flags.status_bus_reset) { /* we are not connected */ break; } /* configure the control endpoint */ /* set endpoint reset */ AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0)); /* set stall */ AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL); /* reset data toggle */ AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ); /* clear stall */ AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL); /* configure */ AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CTRL | AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6)); temp = AVR32_READ_4(sc, AVR32_EPTCFG(0)); if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n"); } else { AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0), AVR32_EPTCTL_EPT_ENABL); } break; case UHF_C_PORT_SUSPEND: sc->sc_flags.change_suspend = 0; break; default: err = USB_ERR_IOERROR; goto done; } goto tr_valid; tr_handle_set_port_feature: if (index != 1) { goto tr_stalled; } DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); switch (value) { case UHF_PORT_ENABLE: sc->sc_flags.port_enabled = 1; break; case UHF_PORT_SUSPEND: case UHF_PORT_RESET: case UHF_PORT_TEST: case UHF_PORT_INDICATOR: /* nops */ break; case UHF_PORT_POWER: sc->sc_flags.port_powered = 1; break; default: err = USB_ERR_IOERROR; goto done; } goto tr_valid; tr_handle_get_port_status: DPRINTFN(9, "UR_GET_PORT_STATUS\n"); if (index != 1) { goto tr_stalled; } if (sc->sc_flags.status_vbus) { avr32dci_clocks_on(sc); avr32dci_pull_up(sc); } else { avr32dci_pull_down(sc); avr32dci_clocks_off(sc); } /* Select Device Side Mode */ value = UPS_PORT_MODE_DEVICE; /* Check for High Speed */ if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED) value |= UPS_HIGH_SPEED; if (sc->sc_flags.port_powered) { value |= UPS_PORT_POWER; } if (sc->sc_flags.port_enabled) { value |= UPS_PORT_ENABLED; } if (sc->sc_flags.status_vbus && sc->sc_flags.status_bus_reset) { value |= UPS_CURRENT_CONNECT_STATUS; } if (sc->sc_flags.status_suspend) { value |= UPS_SUSPEND; } USETW(sc->sc_hub_temp.ps.wPortStatus, value); value = 0; if (sc->sc_flags.change_connect) { value |= UPS_C_CONNECT_STATUS; } if (sc->sc_flags.change_suspend) { value |= UPS_C_SUSPEND; } USETW(sc->sc_hub_temp.ps.wPortChange, value); len = sizeof(sc->sc_hub_temp.ps); goto tr_valid; tr_handle_get_class_descriptor: if (value & 0xFF) { goto tr_stalled; } ptr = (const void *)&avr32dci_hubd; len = sizeof(avr32dci_hubd); goto tr_valid; tr_stalled: err = USB_ERR_STALLED; tr_valid: done: *plength = len; *pptr = ptr; return (err); } static void avr32dci_xfer_setup(struct usb_setup_params *parm) { const struct usb_hw_ep_profile *pf; struct avr32dci_softc *sc; struct usb_xfer *xfer; void *last_obj; uint32_t ntd; uint32_t n; uint8_t ep_no; sc = AVR32_BUS2SC(parm->udev->bus); xfer = parm->curr_xfer; /* * NOTE: This driver does not use any of the parameters that * are computed from the following values. Just set some * reasonable dummies: */ parm->hc_max_packet_size = 0x400; parm->hc_max_packet_count = 1; parm->hc_max_frame_size = 0x400; usbd_transfer_setup_sub(parm); /* * compute maximum number of TDs */ if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ + 1 /* SYNC 2 */ ; } else { ntd = xfer->nframes + 1 /* SYNC */ ; } /* * check if "usbd_transfer_setup_sub" set an error */ if (parm->err) return; /* * allocate transfer descriptors */ last_obj = NULL; /* * get profile stuff */ ep_no = xfer->endpointno & UE_ADDR; avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no); if (pf == NULL) { /* should not happen */ parm->err = USB_ERR_INVAL; return; } /* align data */ parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); for (n = 0; n != ntd; n++) { struct avr32dci_td *td; if (parm->buf) { uint32_t temp; td = USB_ADD_BYTES(parm->buf, parm->size[0]); /* init TD */ td->max_packet_size = xfer->max_packet_size; td->ep_no = ep_no; temp = pf->max_in_frame_size | pf->max_out_frame_size; td->bank_shift = 0; while ((temp /= 2)) td->bank_shift++; if (pf->support_multi_buffer) { td->support_multi_buffer = 1; } td->obj_next = last_obj; last_obj = td; } parm->size[0] += sizeof(*td); } xfer->td_start[0] = last_obj; } static void avr32dci_xfer_unsetup(struct usb_xfer *xfer) { return; } static void avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, struct usb_endpoint *pipe) { struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", pipe, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode, sc->sc_rt_addr, udev->device_index); if (udev->device_index != sc->sc_rt_addr) { if ((udev->speed != USB_SPEED_FULL) && (udev->speed != USB_SPEED_HIGH)) { /* not supported */ return; } if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) pipe->methods = &avr32dci_device_isoc_fs_methods; else pipe->methods = &avr32dci_device_non_isoc_methods; } } static void avr32dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) { struct avr32dci_softc *sc = AVR32_BUS2SC(bus); switch (state) { case USB_HW_POWER_SUSPEND: avr32dci_suspend(sc); break; case USB_HW_POWER_SHUTDOWN: avr32dci_uninit(sc); break; case USB_HW_POWER_RESUME: avr32dci_resume(sc); break; default: break; } } static const struct usb_bus_methods avr32dci_bus_methods = { .endpoint_init = &avr32dci_ep_init, .xfer_setup = &avr32dci_xfer_setup, .xfer_unsetup = &avr32dci_xfer_unsetup, .get_hw_ep_profile = &avr32dci_get_hw_ep_profile, .xfer_stall = &avr32dci_xfer_stall, .set_stall = &avr32dci_set_stall, .clear_stall = &avr32dci_clear_stall, .roothub_exec = &avr32dci_roothub_exec, .xfer_poll = &avr32dci_do_poll, .set_hw_power_sleep = &avr32dci_set_hw_power_sleep, }; diff --git a/sys/dev/usb/controller/dwc_otg.c b/sys/dev/usb/controller/dwc_otg.c index 8192c7b011e9..5a1f2d271251 100644 --- a/sys/dev/usb/controller/dwc_otg.c +++ b/sys/dev/usb/controller/dwc_otg.c @@ -1,4972 +1,4971 @@ /* $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved. * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * This file contains the driver for the DesignWare series USB 2.0 OTG * Controller. */ /* * LIMITATION: Drivers must be bound to all OUT endpoints in the * active configuration for this driver to work properly. Blocking any * OUT endpoint will block all OUT endpoints including the control * endpoint. Usually this is not a problem. */ /* * NOTE: Writing to non-existing registers appears to cause an * internal reset. */ #ifdef USB_GLOBAL_INCLUDE_FILE #include USB_GLOBAL_INCLUDE_FILE #else #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define USB_DEBUG_VAR dwc_otg_debug #include #include #include #include #include #include #include #include #include #include #endif /* USB_GLOBAL_INCLUDE_FILE */ #include #include #define DWC_OTG_BUS2SC(bus) \ - ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ - ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) + __containerof(bus, struct dwc_otg_softc, sc_bus) #define DWC_OTG_PC2UDEV(pc) \ (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) #define DWC_OTG_MSK_GINT_THREAD_IRQ \ (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ GINTSTS_SESSREQINT) #ifndef DWC_OTG_PHY_DEFAULT #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI #endif static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, "USB DWC OTG"); SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+"); #ifdef USB_DEBUG static int dwc_otg_debug = 0; SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, &dwc_otg_debug, 0, "DWC OTG debug level"); #endif #define DWC_OTG_INTR_ENDPT 1 /* prototypes */ static const struct usb_bus_methods dwc_otg_bus_methods; static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; static const struct usb_pipe_methods dwc_otg_device_isoc_methods; static dwc_otg_cmd_t dwc_otg_setup_rx; static dwc_otg_cmd_t dwc_otg_data_rx; static dwc_otg_cmd_t dwc_otg_data_tx; static dwc_otg_cmd_t dwc_otg_data_tx_sync; static dwc_otg_cmd_t dwc_otg_host_setup_tx; static dwc_otg_cmd_t dwc_otg_host_data_tx; static dwc_otg_cmd_t dwc_otg_host_data_rx; static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); static void dwc_otg_do_poll(struct usb_bus *); static void dwc_otg_standard_done(struct usb_xfer *); static void dwc_otg_root_intr(struct dwc_otg_softc *); static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); /* * Here is a configuration that the chip supports. */ static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { [0] = { .max_in_frame_size = 64,/* fixed */ .max_out_frame_size = 64, /* fixed */ .is_simplex = 1, .support_control = 1, } }; static void dwc_otg_get_hw_ep_profile(struct usb_device *udev, const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) { struct dwc_otg_softc *sc; sc = DWC_OTG_BUS2SC(udev->bus); if (ep_addr < sc->sc_dev_ep_max) *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; else *ppf = NULL; } static void dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, uint32_t offset, uint32_t fifo, uint32_t count) { uint32_t temp; /* round down length to nearest 4-bytes */ temp = count & ~3; /* check if we can write the data directly */ if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { struct usb_page_search buf_res; /* pre-subtract length */ count -= temp; /* iterate buffer list */ do { /* get current buffer pointer */ usbd_get_page(pc, offset, &buf_res); if (buf_res.length > temp) buf_res.length = temp; /* transfer data into FIFO */ bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, fifo, buf_res.buffer, buf_res.length / 4); offset += buf_res.length; fifo += buf_res.length; temp -= buf_res.length; } while (temp != 0); } /* check for remainder */ if (count != 0) { /* clear topmost word before copy */ sc->sc_bounce_buffer[(count - 1) / 4] = 0; /* copy out data */ usbd_copy_out(pc, offset, sc->sc_bounce_buffer, count); /* transfer data into FIFO */ bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, fifo, sc->sc_bounce_buffer, (count + 3) / 4); } } static void dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, uint32_t offset, uint32_t count) { uint32_t temp; /* round down length to nearest 4-bytes */ temp = count & ~3; /* check if we can read the data directly */ if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { struct usb_page_search buf_res; /* pre-subtract length */ count -= temp; /* iterate buffer list */ do { /* get current buffer pointer */ usbd_get_page(pc, offset, &buf_res); if (buf_res.length > temp) buf_res.length = temp; /* transfer data from FIFO */ bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4); offset += buf_res.length; sc->sc_current_rx_fifo += buf_res.length; sc->sc_current_rx_bytes -= buf_res.length; temp -= buf_res.length; } while (temp != 0); } /* check for remainder */ if (count != 0) { /* read data into bounce buffer */ bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, sc->sc_current_rx_fifo, sc->sc_bounce_buffer, (count + 3) / 4); /* store data into proper buffer */ usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count); /* round length up to nearest 4 bytes */ count = (count + 3) & ~3; /* update counters */ sc->sc_current_rx_bytes -= count; sc->sc_current_rx_fifo += count; } } static void dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value) { uint32_t temp; /* reset FIFO */ DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value); /* wait for reset to complete */ for (temp = 0; temp != 16; temp++) { value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL); if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))) break; } } static int dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) { struct dwc_otg_profile *pf; uint32_t fifo_size; uint32_t fifo_regs; uint32_t tx_start; uint8_t x; fifo_size = sc->sc_fifo_size; /* * NOTE: Reserved fixed size area at end of RAM, which must * not be allocated to the FIFOs: */ fifo_regs = 4 * 16; if (fifo_size < fifo_regs) { DPRINTF("Too little FIFO\n"); return (EINVAL); } /* subtract FIFO regs from total once */ fifo_size -= fifo_regs; /* split equally for IN and OUT */ fifo_size /= 2; /* Align to 4 bytes boundary (refer to PGM) */ fifo_size &= ~3; /* set global receive FIFO size */ DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); tx_start = fifo_size; if (fifo_size < 64) { DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); return (EINVAL); } if (mode == DWC_MODE_HOST) { /* reset active endpoints */ sc->sc_active_rx_ep = 0; /* split equally for periodic and non-periodic */ fifo_size /= 2; DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); /* align to 4 bytes boundary */ fifo_size &= ~3; DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, ((fifo_size / 4) << 16) | (tx_start / 4)); tx_start += fifo_size; for (x = 0; x != sc->sc_host_ch_max; x++) { /* enable all host interrupts */ DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), HCINT_DEFAULT_MASK); } DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, ((fifo_size / 4) << 16) | (tx_start / 4)); /* reset host channel state */ memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); /* enable all host channel interrupts */ DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, (1U << sc->sc_host_ch_max) - 1U); /* enable proper host channel interrupts */ sc->sc_irq_mask |= GINTMSK_HCHINTMSK; sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } if (mode == DWC_MODE_DEVICE) { DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, (0x10 << 16) | (tx_start / 4)); fifo_size -= 0x40; tx_start += 0x40; /* setup control endpoint profile */ sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; /* reset active endpoints */ sc->sc_active_rx_ep = 1; for (x = 1; x != sc->sc_dev_ep_max; x++) { pf = sc->sc_hw_ep_profile + x; pf->usb.max_out_frame_size = 1024 * 3; pf->usb.is_simplex = 0; /* assume duplex */ pf->usb.support_bulk = 1; pf->usb.support_interrupt = 1; pf->usb.support_isochronous = 1; pf->usb.support_out = 1; if (x < sc->sc_dev_in_ep_max) { uint32_t limit; limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, DWC_OTG_TX_MAX_FIFO_SIZE); /* see if there is enough FIFO space */ if (limit <= fifo_size) { pf->max_buffer = limit; pf->usb.support_in = 1; } else { limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); if (limit <= fifo_size) { pf->usb.support_in = 1; } else { pf->usb.is_simplex = 1; limit = 0; } } /* set FIFO size */ DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), ((limit / 4) << 16) | (tx_start / 4)); tx_start += limit; fifo_size -= limit; pf->usb.max_in_frame_size = limit; } else { pf->usb.is_simplex = 1; } DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, pf->usb.max_in_frame_size, pf->usb.max_out_frame_size); } /* enable proper device channel interrupts */ sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK; sc->sc_irq_mask |= GINTMSK_IEPINTMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } /* reset RX FIFO */ dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH); if (mode != DWC_MODE_OTG) { /* reset all TX FIFOs */ dwc_otg_tx_fifo_reset(sc, GRSTCTL_TXFIFO(0x10) | GRSTCTL_TXFFLSH); } else { /* reset active endpoints */ sc->sc_active_rx_ep = 0; /* reset host channel state */ memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); } return (0); } static uint8_t dwc_otg_uses_split(struct usb_device *udev) { /* * When a LOW or FULL speed device is connected directly to * the USB port we don't use split transactions: */ return (udev->speed != USB_SPEED_HIGH && udev->parent_hs_hub != NULL && udev->parent_hs_hub->parent_hub != NULL); } static void dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) { /* * Disabled until further. Assuming that the register is already * programmed correctly by the boot loader. */ #if 0 uint32_t temp; /* setup HOST frame interval register, based on existing value */ temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; if (temp >= 10000) temp /= 1000; else temp /= 125; /* figure out nearest X-tal value */ if (temp >= 54) temp = 60; /* MHz */ else if (temp >= 39) temp = 48; /* MHz */ else temp = 30; /* MHz */ if (sc->sc_flags.status_high_speed) temp *= 125; else temp *= 1000; DPRINTF("HFIR=0x%08x\n", temp); DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); #endif } static void dwc_otg_clocks_on(struct dwc_otg_softc *sc) { if (sc->sc_flags.clocks_off && sc->sc_flags.port_powered) { DPRINTFN(5, "\n"); /* TODO - platform specific */ sc->sc_flags.clocks_off = 0; } } static void dwc_otg_clocks_off(struct dwc_otg_softc *sc) { if (!sc->sc_flags.clocks_off) { DPRINTFN(5, "\n"); /* TODO - platform specific */ sc->sc_flags.clocks_off = 1; } } static void dwc_otg_pull_up(struct dwc_otg_softc *sc) { uint32_t temp; /* pullup D+, if possible */ if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) { sc->sc_flags.d_pulled_up = 1; temp = DWC_OTG_READ_4(sc, DOTG_DCTL); temp &= ~DCTL_SFTDISCON; DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); } } static void dwc_otg_pull_down(struct dwc_otg_softc *sc) { uint32_t temp; /* pulldown D+, if possible */ if (sc->sc_flags.d_pulled_up) { sc->sc_flags.d_pulled_up = 0; temp = DWC_OTG_READ_4(sc, DOTG_DCTL); temp |= DCTL_SFTDISCON; DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); } } static void dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) { /* In device mode we don't use the SOF interrupt */ if (sc->sc_flags.status_device_mode != 0) return; /* Ensure the SOF interrupt is not disabled */ sc->sc_needsof = 1; /* Check if the SOF interrupt is already enabled */ if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) return; sc->sc_irq_mask |= GINTMSK_SOFMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } static void dwc_otg_resume_irq(struct dwc_otg_softc *sc) { if (sc->sc_flags.status_suspend) { /* update status bits */ sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 1; if (sc->sc_flags.status_device_mode) { /* * Disable resume interrupt and enable suspend * interrupt: */ sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } /* complete root HUB interrupt endpoint */ dwc_otg_root_intr(sc); } } static void dwc_otg_suspend_irq(struct dwc_otg_softc *sc) { if (!sc->sc_flags.status_suspend) { /* update status bits */ sc->sc_flags.status_suspend = 1; sc->sc_flags.change_suspend = 1; if (sc->sc_flags.status_device_mode) { /* * Disable suspend interrupt and enable resume * interrupt: */ sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } /* complete root HUB interrupt endpoint */ dwc_otg_root_intr(sc); } } static void dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) { if (!sc->sc_flags.status_suspend) return; DPRINTFN(5, "Remote wakeup\n"); if (sc->sc_flags.status_device_mode) { uint32_t temp; /* enable remote wakeup signalling */ temp = DWC_OTG_READ_4(sc, DOTG_DCTL); temp |= DCTL_RMTWKUPSIG; DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); /* Wait 8ms for remote wakeup to complete. */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); temp &= ~DCTL_RMTWKUPSIG; DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); } else { /* enable USB port */ DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); /* wait 10ms */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); /* resume port */ sc->sc_hprt_val |= HPRT_PRTRES; DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); /* Wait 100ms for resume signalling to complete. */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); /* clear suspend and resume */ sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); /* Wait 4ms */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); } /* need to fake resume IRQ */ dwc_otg_resume_irq(sc); } static void dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) { uint32_t temp; DPRINTFN(5, "addr=%d\n", addr); temp = DWC_OTG_READ_4(sc, DOTG_DCFG); temp &= ~DCFG_DEVADDR_SET(0x7F); temp |= DCFG_DEVADDR_SET(addr); DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); } static void dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) { DPRINTFN(5, "RX status clear\n"); /* enable RX FIFO level interrupt */ sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); if (sc->sc_current_rx_bytes != 0) { /* need to dump remaining data */ bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, sc->sc_current_rx_fifo, sc->sc_bounce_buffer, sc->sc_current_rx_bytes / 4); /* clear number of active bytes to receive */ sc->sc_current_rx_bytes = 0; } /* clear cached status */ sc->sc_last_rx_status = 0; } static void dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) { uint32_t hcint; /* clear all pending interrupts */ hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); /* clear buffered interrupts */ sc->sc_chan_state[x].hcint = 0; } static uint8_t dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint32_t temp; temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); if (td->ep_type == UE_ISOCHRONOUS) { /* * NOTE: USB INTERRUPT transactions are executed like * USB CONTROL transactions! See the setup standard * chain function for more information. */ if (!(temp & GINTSTS_PTXFEMP)) { DPRINTF("Periodic TX FIFO is not empty\n"); if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } return (1); /* busy */ } } else { if (!(temp & GINTSTS_NPTXFEMP)) { DPRINTF("Non-periodic TX FIFO is not empty\n"); if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } return (1); /* busy */ } } return (0); /* ready for transmit */ } static uint8_t dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t is_out) { uint8_t x; uint8_t y; uint8_t z; if (td->channel[0] < DWC_OTG_MAX_CHANNELS) return (0); /* already allocated */ /* check if device is suspended */ if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) return (1); /* busy - cannot transfer data */ /* compute needed TX FIFO size */ if (is_out != 0) { if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0) return (1); /* busy - cannot transfer data */ } z = td->max_packet_count; for (x = y = 0; x != sc->sc_host_ch_max; x++) { /* check if channel is allocated */ if (sc->sc_chan_state[x].allocated != 0) continue; /* check if channel is still enabled */ if (sc->sc_chan_state[x].wait_halted != 0) continue; /* store channel number */ td->channel[y++] = x; /* check if we got all channels */ if (y == z) break; } if (y != z) { /* reset channel variable */ td->channel[0] = DWC_OTG_MAX_CHANNELS; td->channel[1] = DWC_OTG_MAX_CHANNELS; td->channel[2] = DWC_OTG_MAX_CHANNELS; /* wait a bit */ dwc_otg_enable_sof_irq(sc); return (1); /* busy - not enough channels */ } for (y = 0; y != z; y++) { x = td->channel[y]; /* set allocated */ sc->sc_chan_state[x].allocated = 1; /* set wait halted */ sc->sc_chan_state[x].wait_halted = 1; /* clear interrupts */ dwc_otg_clear_hcint(sc, x); DPRINTF("CH=%d HCCHAR=0x%08x " "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); /* set active channel */ sc->sc_active_rx_ep |= (1 << x); } return (0); /* allocated */ } static void dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index) { uint32_t hcchar; uint8_t x; if (td->channel[index] >= DWC_OTG_MAX_CHANNELS) return; /* already freed */ /* free channel */ x = td->channel[index]; td->channel[index] = DWC_OTG_MAX_CHANNELS; DPRINTF("CH=%d\n", x); /* * We need to let programmed host channels run till complete * else the host channel will stop functioning. */ sc->sc_chan_state[x].allocated = 0; /* ack any pending messages */ if (sc->sc_last_rx_status != 0 && GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { dwc_otg_common_rx_ack(sc); } /* clear active channel */ sc->sc_active_rx_ep &= ~(1 << x); /* check if already halted */ if (sc->sc_chan_state[x].wait_halted == 0) return; /* disable host channel */ hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); if (hcchar & HCCHAR_CHENA) { DPRINTF("Halting channel %d\n", x); DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), hcchar | HCCHAR_CHDIS); /* don't write HCCHAR until the channel is halted */ } else { sc->sc_chan_state[x].wait_halted = 0; } } static void dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint8_t x; for (x = 0; x != td->max_packet_count; x++) dwc_otg_host_channel_free_sub(sc, td, x); } static void dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint8_t x; /* dump any pending messages */ if (sc->sc_last_rx_status == 0) return; for (x = 0; x != td->max_packet_count; x++) { if (td->channel[x] >= DWC_OTG_MAX_CHANNELS || td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) continue; dwc_otg_common_rx_ack(sc); break; } } static uint8_t dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { struct usb_device_request req __aligned(4); uint32_t hcint; uint32_t hcchar; uint8_t delta; dwc_otg_host_dump_rx(sc, td); if (td->channel[0] < DWC_OTG_MAX_CHANNELS) { hcint = sc->sc_chan_state[td->channel[0]].hcint; DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", td->channel[0], td->state, hcint, DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])), DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0]))); } else { hcint = 0; goto check_state; } if (hcint & (HCINT_RETRY | HCINT_ACK | HCINT_NYET)) { /* give success bits priority over failure bits */ } else if (hcint & HCINT_STALL) { DPRINTF("CH=%d STALL\n", td->channel[0]); td->error_stall = 1; td->error_any = 1; goto complete; } else if (hcint & HCINT_ERRORS) { DPRINTF("CH=%d ERROR\n", td->channel[0]); td->errcnt++; if (td->hcsplt != 0 || td->errcnt >= 3) { td->error_any = 1; goto complete; } } if (hcint & (HCINT_ERRORS | HCINT_RETRY | HCINT_ACK | HCINT_NYET)) { if (!(hcint & HCINT_ERRORS)) td->errcnt = 0; } check_state: switch (td->state) { case DWC_CHAN_ST_START: goto send_pkt; case DWC_CHAN_ST_WAIT_ANE: if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { td->did_nak = 1; td->tt_scheduled = 0; goto send_pkt; } else if (hcint & (HCINT_ACK | HCINT_NYET)) { td->offset += td->tx_bytes; td->remainder -= td->tx_bytes; td->toggle = 1; td->tt_scheduled = 0; goto complete; } break; case DWC_CHAN_ST_WAIT_S_ANE: if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { td->did_nak = 1; td->tt_scheduled = 0; goto send_pkt; } else if (hcint & (HCINT_ACK | HCINT_NYET)) { goto send_cpkt; } break; case DWC_CHAN_ST_WAIT_C_ANE: if (hcint & HCINT_NYET) { goto send_cpkt; } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { td->did_nak = 1; td->tt_scheduled = 0; goto send_pkt; } else if (hcint & HCINT_ACK) { td->offset += td->tx_bytes; td->remainder -= td->tx_bytes; td->toggle = 1; goto complete; } break; case DWC_CHAN_ST_WAIT_C_PKT: goto send_cpkt; default: break; } goto busy; send_pkt: /* free existing channel, if any */ dwc_otg_host_channel_free(sc, td); if (sizeof(req) != td->remainder) { td->error_any = 1; goto complete; } if (td->hcsplt != 0) { delta = td->tt_start_slot - sc->sc_last_frame_num - 1; if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { td->state = DWC_CHAN_ST_START; goto busy; } delta = sc->sc_last_frame_num - td->tt_start_slot; if (delta > 5) { /* missed it */ td->tt_scheduled = 0; td->state = DWC_CHAN_ST_START; goto busy; } } /* allocate a new channel */ if (dwc_otg_host_channel_alloc(sc, td, 1)) { td->state = DWC_CHAN_ST_START; goto busy; } if (td->hcsplt != 0) { td->hcsplt &= ~HCSPLT_COMPSPLT; td->state = DWC_CHAN_ST_WAIT_S_ANE; } else { td->state = DWC_CHAN_ST_WAIT_ANE; } /* copy out control request */ usbd_copy_out(td->pc, 0, &req, sizeof(req)); DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); hcchar = td->hcchar; hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; /* must enable channel before writing data to FIFO */ DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); /* transfer data into FIFO */ bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4); /* wait until next slot before trying complete split */ td->tt_complete_slot = sc->sc_last_frame_num + 1; /* store number of bytes transmitted */ td->tx_bytes = sizeof(req); goto busy; send_cpkt: /* free existing channel, if any */ dwc_otg_host_channel_free(sc, td); delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { td->state = DWC_CHAN_ST_WAIT_C_PKT; goto busy; } delta = sc->sc_last_frame_num - td->tt_start_slot; if (delta > DWC_OTG_TT_SLOT_MAX) { /* we missed the service interval */ if (td->ep_type != UE_ISOCHRONOUS) td->error_any = 1; goto complete; } /* allocate a new channel */ if (dwc_otg_host_channel_alloc(sc, td, 0)) { td->state = DWC_CHAN_ST_WAIT_C_PKT; goto busy; } /* wait until next slot before trying complete split */ td->tt_complete_slot = sc->sc_last_frame_num + 1; td->hcsplt |= HCSPLT_COMPSPLT; td->state = DWC_CHAN_ST_WAIT_C_ANE; DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); hcchar = td->hcchar; hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; /* must enable channel before writing data to FIFO */ DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); busy: return (1); /* busy */ complete: dwc_otg_host_channel_free(sc, td); return (0); /* complete */ } static uint8_t dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { struct usb_device_request req __aligned(4); uint32_t temp; uint16_t count; /* check endpoint status */ if (sc->sc_last_rx_status == 0) goto not_complete; if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) goto not_complete; if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != GRXSTSRD_STP_DATA) { if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != GRXSTSRD_STP_COMPLETE || td->remainder != 0) { /* release FIFO */ dwc_otg_common_rx_ack(sc); goto not_complete; } /* release FIFO */ dwc_otg_common_rx_ack(sc); return (0); /* complete */ } if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { /* release FIFO */ dwc_otg_common_rx_ack(sc); goto not_complete; } DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); /* clear did stall */ td->did_stall = 0; /* get the packet byte count */ count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); if (count != sizeof(req)) { DPRINTFN(0, "Unsupported SETUP packet " "length, %d bytes\n", count); /* release FIFO */ dwc_otg_common_rx_ack(sc); goto not_complete; } /* read FIFO */ dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req)); /* copy out control request */ usbd_copy_out(td->pc, 0, &req, sizeof(req)); td->offset = sizeof(req); td->remainder = 0; /* sneak peek the set address */ if ((req.bmRequestType == UT_WRITE_DEVICE) && (req.bRequest == UR_SET_ADDRESS)) { /* must write address before ZLP */ dwc_otg_set_address(sc, req.wValue[0] & 0x7F); } /* don't send any data by default */ DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS); DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS); /* reset IN endpoint buffer */ dwc_otg_tx_fifo_reset(sc, GRSTCTL_TXFIFO(0) | GRSTCTL_TXFFLSH); /* acknowledge RX status */ dwc_otg_common_rx_ack(sc); td->did_stall = 1; not_complete: /* abort any ongoing transfer, before enabling again */ if (!td->did_stall) { td->did_stall = 1; DPRINTFN(5, "stalling IN and OUT direction\n"); temp = sc->sc_out_ctl[0]; /* set stall after enabling endpoint */ DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp | DOEPCTL_STALL); temp = sc->sc_in_ctl[0]; /* set stall assuming endpoint is enabled */ DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), temp | DIEPCTL_STALL); } return (1); /* not complete */ } static uint8_t dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint8_t delta; delta = sc->sc_tmr_val - td->tmr_val; if (delta >= 128) return (1); /* busy */ td->tmr_val = sc->sc_tmr_val + td->tmr_res; /* set toggle, if any */ if (td->set_toggle) { td->set_toggle = 0; td->toggle = 1; } return (0); } static uint8_t dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; if (td->ep_type == UE_ISOCHRONOUS) { /* non TT isochronous traffic */ if (frame_num & (td->tmr_res - 1)) goto busy; if ((frame_num ^ td->tmr_val) & td->tmr_res) goto busy; td->tmr_val = td->tmr_res + sc->sc_last_frame_num; td->toggle = 0; return (0); } else if (td->ep_type == UE_INTERRUPT) { if (!td->tt_scheduled) goto busy; td->tt_scheduled = 0; return (0); } else if (td->did_nak != 0) { /* check if we should pause sending queries for 125us */ if (td->tmr_res == frame_num) { /* wait a bit */ dwc_otg_enable_sof_irq(sc); goto busy; } } else if (td->set_toggle) { td->set_toggle = 0; td->toggle = 1; } /* query for data one more time */ td->tmr_res = frame_num; td->did_nak = 0; return (0); busy: return (1); } static uint8_t dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t channel) { uint32_t count; /* check endpoint status */ if (sc->sc_last_rx_status == 0) goto busy; if (channel >= DWC_OTG_MAX_CHANNELS) goto busy; if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) goto busy; switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { case GRXSTSRH_IN_DATA: DPRINTF("DATA ST=%d STATUS=0x%08x\n", (int)td->state, (int)sc->sc_last_rx_status); if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { /* * When using SPLIT transactions on interrupt * endpoints, sometimes data occurs twice. */ DPRINTF("Data already received\n"); break; } /* get the packet byte count */ count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); /* check for ISOCHRONOUS endpoint */ if (td->ep_type == UE_ISOCHRONOUS) { if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { /* more data to be received */ td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; } else { /* all data received */ td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; /* verify the packet byte count */ if (count != td->remainder) { /* we have a short packet */ td->short_pkt = 1; td->got_short = 1; } } } else { /* verify the packet byte count */ if (count != td->max_packet_size) { if (count < td->max_packet_size) { /* we have a short packet */ td->short_pkt = 1; td->got_short = 1; } else { /* invalid USB packet */ td->error_any = 1; /* release FIFO */ dwc_otg_common_rx_ack(sc); goto complete; } } td->toggle ^= 1; td->tt_scheduled = 0; } /* verify the packet byte count */ if (count > td->remainder) { /* invalid USB packet */ td->error_any = 1; /* release FIFO */ dwc_otg_common_rx_ack(sc); goto complete; } /* read data from FIFO */ dwc_otg_read_fifo(sc, td->pc, td->offset, count); td->remainder -= count; td->offset += count; sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; break; default: break; } /* release FIFO */ dwc_otg_common_rx_ack(sc); busy: return (0); complete: return (1); } static uint8_t dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint32_t hcint = 0; uint32_t hcchar; uint8_t delta; uint8_t channel; uint8_t x; for (x = 0; x != td->max_packet_count; x++) { channel = td->channel[x]; if (channel >= DWC_OTG_MAX_CHANNELS) continue; hcint |= sc->sc_chan_state[channel].hcint; DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", channel, td->state, hcint, DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); /* check interrupt bits */ if (hcint & (HCINT_RETRY | HCINT_ACK | HCINT_NYET)) { /* give success bits priority over failure bits */ } else if (hcint & HCINT_STALL) { DPRINTF("CH=%d STALL\n", channel); td->error_stall = 1; td->error_any = 1; goto complete; } else if (hcint & HCINT_ERRORS) { DPRINTF("CH=%d ERROR\n", channel); td->errcnt++; if (td->hcsplt != 0 || td->errcnt >= 3) { if (td->ep_type != UE_ISOCHRONOUS) { td->error_any = 1; goto complete; } } } /* check channels for data, if any */ if (dwc_otg_host_data_rx_sub(sc, td, channel)) goto complete; /* refresh interrupt status */ hcint |= sc->sc_chan_state[channel].hcint; if (hcint & (HCINT_ERRORS | HCINT_RETRY | HCINT_ACK | HCINT_NYET)) { if (!(hcint & HCINT_ERRORS)) td->errcnt = 0; } } switch (td->state) { case DWC_CHAN_ST_START: if (td->hcsplt != 0) goto receive_spkt; else goto receive_pkt; case DWC_CHAN_ST_WAIT_ANE: if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { if (td->ep_type == UE_INTERRUPT) { /* * The USB specification does not * mandate a particular data toggle * value for USB INTERRUPT * transfers. Switch the data toggle * value to receive the packet * correctly: */ if (hcint & HCINT_DATATGLERR) { DPRINTF("Retrying packet due to " "data toggle error\n"); td->toggle ^= 1; goto receive_pkt; } } else if (td->ep_type == UE_ISOCHRONOUS) { if (td->hcsplt != 0) { /* * Sometimes the complete * split packet may be queued * too early and the * transaction translator will * return a NAK. Ignore * this message and retry the * complete split instead. */ DPRINTF("Retrying complete split\n"); goto receive_pkt; } goto complete; } td->did_nak = 1; td->tt_scheduled = 0; if (td->hcsplt != 0) goto receive_spkt; else goto receive_pkt; } else if (hcint & HCINT_NYET) { if (td->hcsplt != 0) { /* try again */ goto receive_pkt; } else { /* not a valid token for IN endpoints */ td->error_any = 1; goto complete; } } else if (hcint & HCINT_ACK) { /* wait for data - ACK arrived first */ if (!(hcint & HCINT_SOFTWARE_ONLY)) goto busy; if (td->ep_type == UE_ISOCHRONOUS) { /* check if we are complete */ if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) { goto complete; } else if (td->hcsplt != 0) { goto receive_pkt; } else { /* get more packets */ goto busy; } } else { /* check if we are complete */ if ((td->remainder == 0) || (td->got_short != 0)) { if (td->short_pkt) goto complete; /* * Else need to receive a zero length * packet. */ } td->tt_scheduled = 0; td->did_nak = 0; if (td->hcsplt != 0) goto receive_spkt; else goto receive_pkt; } } break; case DWC_CHAN_ST_WAIT_S_ANE: /* * NOTE: The DWC OTG hardware provides a fake ACK in * case of interrupt and isochronous transfers: */ if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { td->did_nak = 1; td->tt_scheduled = 0; goto receive_spkt; } else if (hcint & HCINT_NYET) { td->tt_scheduled = 0; goto receive_spkt; } else if (hcint & HCINT_ACK) { td->did_nak = 0; goto receive_pkt; } break; case DWC_CHAN_ST_WAIT_C_PKT: goto receive_pkt; default: break; } goto busy; receive_pkt: /* free existing channel, if any */ dwc_otg_host_channel_free(sc, td); if (td->hcsplt != 0) { delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { if (td->ep_type != UE_ISOCHRONOUS) { td->state = DWC_CHAN_ST_WAIT_C_PKT; goto busy; } } delta = sc->sc_last_frame_num - td->tt_start_slot; if (delta > DWC_OTG_TT_SLOT_MAX) { if (td->ep_type != UE_ISOCHRONOUS) { /* we missed the service interval */ td->error_any = 1; } goto complete; } /* complete split */ td->hcsplt |= HCSPLT_COMPSPLT; } else if (dwc_otg_host_rate_check(sc, td)) { td->state = DWC_CHAN_ST_WAIT_C_PKT; goto busy; } /* allocate a new channel */ if (dwc_otg_host_channel_alloc(sc, td, 0)) { td->state = DWC_CHAN_ST_WAIT_C_PKT; goto busy; } /* set toggle, if any */ if (td->set_toggle) { td->set_toggle = 0; td->toggle = 1; } td->state = DWC_CHAN_ST_WAIT_ANE; for (x = 0; x != td->max_packet_count; x++) { channel = td->channel[x]; /* receive one packet */ DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); hcchar = td->hcchar; hcchar |= HCCHAR_EPDIR_IN; if (td->ep_type == UE_ISOCHRONOUS) { if (td->hcsplt != 0) { /* continously buffer */ if (sc->sc_last_frame_num & 1) hcchar &= ~HCCHAR_ODDFRM; else hcchar |= HCCHAR_ODDFRM; } else { /* multi buffer, if any */ if (sc->sc_last_frame_num & 1) hcchar |= HCCHAR_ODDFRM; else hcchar &= ~HCCHAR_ODDFRM; } } else { hcchar &= ~HCCHAR_ODDFRM; } /* must enable channel before data can be received */ DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); } /* wait until next slot before trying complete split */ td->tt_complete_slot = sc->sc_last_frame_num + 1; goto busy; receive_spkt: /* free existing channel(s), if any */ dwc_otg_host_channel_free(sc, td); delta = td->tt_start_slot - sc->sc_last_frame_num - 1; if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { td->state = DWC_CHAN_ST_START; goto busy; } delta = sc->sc_last_frame_num - td->tt_start_slot; if (delta > 5) { /* missed it */ td->tt_scheduled = 0; td->state = DWC_CHAN_ST_START; goto busy; } /* allocate a new channel */ if (dwc_otg_host_channel_alloc(sc, td, 0)) { td->state = DWC_CHAN_ST_START; goto busy; } channel = td->channel[0]; td->hcsplt &= ~HCSPLT_COMPSPLT; td->state = DWC_CHAN_ST_WAIT_S_ANE; /* receive one packet */ DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); /* send after next SOF event */ if ((sc->sc_last_frame_num & 1) == 0 && td->ep_type == UE_ISOCHRONOUS) td->hcchar |= HCCHAR_ODDFRM; else td->hcchar &= ~HCCHAR_ODDFRM; hcchar = td->hcchar; hcchar |= HCCHAR_EPDIR_IN; /* wait until next slot before trying complete split */ td->tt_complete_slot = sc->sc_last_frame_num + 1; /* must enable channel before data can be received */ DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); busy: return (1); /* busy */ complete: dwc_otg_host_channel_free(sc, td); return (0); /* complete */ } static uint8_t dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint32_t temp; uint16_t count; uint8_t got_short; got_short = 0; /* check endpoint status */ if (sc->sc_last_rx_status == 0) goto not_complete; if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) goto not_complete; /* check for SETUP packet */ if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == GRXSTSRD_STP_DATA || (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == GRXSTSRD_STP_COMPLETE) { if (td->remainder == 0) { /* * We are actually complete and have * received the next SETUP */ DPRINTFN(5, "faking complete\n"); return (0); /* complete */ } /* * USB Host Aborted the transfer. */ td->error_any = 1; return (0); /* complete */ } if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != GRXSTSRD_OUT_DATA) { /* release FIFO */ dwc_otg_common_rx_ack(sc); goto not_complete; } /* get the packet byte count */ count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); /* verify the packet byte count */ if (count != td->max_packet_size) { if (count < td->max_packet_size) { /* we have a short packet */ td->short_pkt = 1; got_short = 1; } else { /* invalid USB packet */ td->error_any = 1; /* release FIFO */ dwc_otg_common_rx_ack(sc); return (0); /* we are complete */ } } /* verify the packet byte count */ if (count > td->remainder) { /* invalid USB packet */ td->error_any = 1; /* release FIFO */ dwc_otg_common_rx_ack(sc); return (0); /* we are complete */ } /* read data from FIFO */ dwc_otg_read_fifo(sc, td->pc, td->offset, count); td->remainder -= count; td->offset += count; /* release FIFO */ dwc_otg_common_rx_ack(sc); temp = sc->sc_out_ctl[td->ep_no]; /* check for isochronous mode */ if ((temp & DIEPCTL_EPTYPE_MASK) == (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { /* toggle odd or even frame bit */ if (temp & DIEPCTL_SETD1PID) { temp &= ~DIEPCTL_SETD1PID; temp |= DIEPCTL_SETD0PID; } else { temp &= ~DIEPCTL_SETD0PID; temp |= DIEPCTL_SETD1PID; } sc->sc_out_ctl[td->ep_no] = temp; } /* check if we are complete */ if ((td->remainder == 0) || got_short) { if (td->short_pkt) { /* we are complete */ return (0); } /* else need to receive a zero length packet */ } not_complete: /* enable SETUP and transfer complete interrupt */ if (td->ep_no == 0) { DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DXEPTSIZ_SET_MULTI(3) | DXEPTSIZ_SET_NPKT(1) | DXEPTSIZ_SET_NBYTES(td->max_packet_size)); } else { /* allow reception of multiple packets */ DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), DXEPTSIZ_SET_MULTI(1) | DXEPTSIZ_SET_NPKT(4) | DXEPTSIZ_SET_NBYTES(4 * ((td->max_packet_size + 3) & ~3))); } temp = sc->sc_out_ctl[td->ep_no]; DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp | DOEPCTL_EPENA | DOEPCTL_CNAK); return (1); /* not complete */ } static uint8_t dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint32_t count; uint32_t hcint; uint32_t hcchar; uint8_t delta; uint8_t channel; uint8_t x; dwc_otg_host_dump_rx(sc, td); /* check that last channel is complete */ channel = td->channel[td->npkt]; if (channel < DWC_OTG_MAX_CHANNELS) { hcint = sc->sc_chan_state[channel].hcint; DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", channel, td->state, hcint, DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); if (hcint & (HCINT_RETRY | HCINT_ACK | HCINT_NYET)) { /* give success bits priority over failure bits */ } else if (hcint & HCINT_STALL) { DPRINTF("CH=%d STALL\n", channel); td->error_stall = 1; td->error_any = 1; goto complete; } else if (hcint & HCINT_ERRORS) { DPRINTF("CH=%d ERROR\n", channel); td->errcnt++; if (td->hcsplt != 0 || td->errcnt >= 3) { td->error_any = 1; goto complete; } } if (hcint & (HCINT_ERRORS | HCINT_RETRY | HCINT_ACK | HCINT_NYET)) { if (!(hcint & HCINT_ERRORS)) td->errcnt = 0; } } else { hcint = 0; } switch (td->state) { case DWC_CHAN_ST_START: goto send_pkt; case DWC_CHAN_ST_WAIT_ANE: if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { td->did_nak = 1; td->tt_scheduled = 0; goto send_pkt; } else if (hcint & (HCINT_ACK | HCINT_NYET)) { td->offset += td->tx_bytes; td->remainder -= td->tx_bytes; td->toggle ^= 1; /* check if next response will be a NAK */ if (hcint & HCINT_NYET) td->did_nak = 1; else td->did_nak = 0; td->tt_scheduled = 0; /* check remainder */ if (td->remainder == 0) { if (td->short_pkt) goto complete; /* * Else we need to transmit a short * packet: */ } goto send_pkt; } break; case DWC_CHAN_ST_WAIT_S_ANE: if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { td->did_nak = 1; td->tt_scheduled = 0; goto send_pkt; } else if (hcint & (HCINT_ACK | HCINT_NYET)) { td->did_nak = 0; goto send_cpkt; } break; case DWC_CHAN_ST_WAIT_C_ANE: if (hcint & HCINT_NYET) { goto send_cpkt; } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { td->did_nak = 1; td->tt_scheduled = 0; goto send_pkt; } else if (hcint & HCINT_ACK) { td->offset += td->tx_bytes; td->remainder -= td->tx_bytes; td->toggle ^= 1; td->did_nak = 0; td->tt_scheduled = 0; /* check remainder */ if (td->remainder == 0) { if (td->short_pkt) goto complete; /* else we need to transmit a short packet */ } goto send_pkt; } break; case DWC_CHAN_ST_WAIT_C_PKT: goto send_cpkt; case DWC_CHAN_ST_TX_WAIT_ISOC: /* Check if ISOCHRONOUS OUT traffic is complete */ if ((hcint & HCINT_HCH_DONE_MASK) == 0) break; td->offset += td->tx_bytes; td->remainder -= td->tx_bytes; goto complete; default: break; } goto busy; send_pkt: /* free existing channel(s), if any */ dwc_otg_host_channel_free(sc, td); if (td->hcsplt != 0) { delta = td->tt_start_slot - sc->sc_last_frame_num - 1; if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { td->state = DWC_CHAN_ST_START; goto busy; } delta = sc->sc_last_frame_num - td->tt_start_slot; if (delta > 5) { /* missed it */ td->tt_scheduled = 0; td->state = DWC_CHAN_ST_START; goto busy; } } else if (dwc_otg_host_rate_check(sc, td)) { td->state = DWC_CHAN_ST_START; goto busy; } /* allocate a new channel */ if (dwc_otg_host_channel_alloc(sc, td, 1)) { td->state = DWC_CHAN_ST_START; goto busy; } /* set toggle, if any */ if (td->set_toggle) { td->set_toggle = 0; td->toggle = 1; } if (td->ep_type == UE_ISOCHRONOUS) { /* ISOCHRONOUS OUT transfers don't have any ACKs */ td->state = DWC_CHAN_ST_TX_WAIT_ISOC; td->hcsplt &= ~HCSPLT_COMPSPLT; if (td->hcsplt != 0) { /* get maximum transfer length */ count = td->remainder; if (count > HCSPLT_XACTLEN_BURST) { DPRINTF("TT overflow\n"); td->error_any = 1; goto complete; } /* Update transaction position */ td->hcsplt &= ~HCSPLT_XACTPOS_MASK; td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); } } else if (td->hcsplt != 0) { td->hcsplt &= ~HCSPLT_COMPSPLT; /* Wait for ACK/NAK/ERR from TT */ td->state = DWC_CHAN_ST_WAIT_S_ANE; } else { /* Wait for ACK/NAK/STALL from device */ td->state = DWC_CHAN_ST_WAIT_ANE; } td->tx_bytes = 0; for (x = 0; x != td->max_packet_count; x++) { uint32_t rem_bytes; channel = td->channel[x]; /* send one packet at a time */ count = td->max_packet_size; rem_bytes = td->remainder - td->tx_bytes; if (rem_bytes < count) { /* we have a short packet */ td->short_pkt = 1; count = rem_bytes; } if (count == rem_bytes) { /* last packet */ switch (x) { case 0: DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (count << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); break; case 1: DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (count << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); break; default: DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (count << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); break; } } else if (td->ep_type == UE_ISOCHRONOUS && td->max_packet_count > 1) { /* ISOCHRONOUS multi packet */ DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (count << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); } else { /* TODO: HCTSIZ_DOPNG */ /* standard BULK/INTERRUPT/CONTROL packet */ DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (count << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); } DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); hcchar = td->hcchar; hcchar &= ~HCCHAR_EPDIR_IN; /* send after next SOF event */ if ((sc->sc_last_frame_num & 1) == 0 && td->ep_type == UE_ISOCHRONOUS) hcchar |= HCCHAR_ODDFRM; else hcchar &= ~HCCHAR_ODDFRM; /* must enable before writing data to FIFO */ DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); if (count != 0) { /* write data into FIFO */ dwc_otg_write_fifo(sc, td->pc, td->offset + td->tx_bytes, DOTG_DFIFO(channel), count); } /* store number of bytes transmitted */ td->tx_bytes += count; /* store last packet index */ td->npkt = x; /* check for last packet */ if (count == rem_bytes) break; } goto busy; send_cpkt: /* free existing channel, if any */ dwc_otg_host_channel_free(sc, td); delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { td->state = DWC_CHAN_ST_WAIT_C_PKT; goto busy; } delta = sc->sc_last_frame_num - td->tt_start_slot; if (delta > DWC_OTG_TT_SLOT_MAX) { /* we missed the service interval */ if (td->ep_type != UE_ISOCHRONOUS) td->error_any = 1; goto complete; } /* allocate a new channel */ if (dwc_otg_host_channel_alloc(sc, td, 0)) { td->state = DWC_CHAN_ST_WAIT_C_PKT; goto busy; } channel = td->channel[0]; td->hcsplt |= HCSPLT_COMPSPLT; td->state = DWC_CHAN_ST_WAIT_C_ANE; DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); hcchar = td->hcchar; hcchar &= ~HCCHAR_EPDIR_IN; /* receive complete split ASAP */ if ((sc->sc_last_frame_num & 1) != 0 && td->ep_type == UE_ISOCHRONOUS) hcchar |= HCCHAR_ODDFRM; else hcchar &= ~HCCHAR_ODDFRM; /* must enable channel before data can be received */ DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); /* wait until next slot before trying complete split */ td->tt_complete_slot = sc->sc_last_frame_num + 1; busy: return (1); /* busy */ complete: dwc_otg_host_channel_free(sc, td); return (0); /* complete */ } static uint8_t dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint32_t max_buffer; uint32_t count; uint32_t fifo_left; uint32_t mpkt; uint32_t temp; uint8_t to; to = 3; /* don't loop forever! */ max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; repeat: /* check for for endpoint 0 data */ temp = sc->sc_last_rx_status; if ((td->ep_no == 0) && (temp != 0) && (GRXSTSRD_CHNUM_GET(temp) == 0)) { if ((temp & GRXSTSRD_PKTSTS_MASK) != GRXSTSRD_STP_DATA && (temp & GRXSTSRD_PKTSTS_MASK) != GRXSTSRD_STP_COMPLETE) { /* dump data - wrong direction */ dwc_otg_common_rx_ack(sc); } else { /* * The current transfer was cancelled * by the USB Host: */ td->error_any = 1; return (0); /* complete */ } } /* fill in more TX data, if possible */ if (td->tx_bytes != 0) { uint16_t cpkt; /* check if packets have been transferred */ temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); /* get current packet number */ cpkt = DXEPTSIZ_GET_NPKT(temp); if (cpkt >= td->npkt) { fifo_left = 0; } else { if (max_buffer != 0) { fifo_left = (td->npkt - cpkt) * td->max_packet_size; if (fifo_left > max_buffer) fifo_left = max_buffer; } else { fifo_left = td->max_packet_size; } } count = td->tx_bytes; if (count > fifo_left) count = fifo_left; if (count != 0) { /* write data into FIFO */ dwc_otg_write_fifo(sc, td->pc, td->offset, DOTG_DFIFO(td->ep_no), count); td->tx_bytes -= count; td->remainder -= count; td->offset += count; td->npkt = cpkt; } if (td->tx_bytes != 0) goto not_complete; /* check remainder */ if (td->remainder == 0) { if (td->short_pkt) return (0); /* complete */ /* else we need to transmit a short packet */ } } if (!to--) goto not_complete; /* check if not all packets have been transferred */ temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); if (DXEPTSIZ_GET_NPKT(temp) != 0) { DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " "DIEPCTL=0x%08x\n", td->ep_no, DXEPTSIZ_GET_NPKT(temp), temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); goto not_complete; } DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); /* try to optimise by sending more data */ if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { /* send multiple packets at the same time */ mpkt = max_buffer / td->max_packet_size; if (mpkt > 0x3FE) mpkt = 0x3FE; count = td->remainder; if (count > 0x7FFFFF) count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); td->npkt = count / td->max_packet_size; /* * NOTE: We could use 0x3FE instead of "mpkt" in the * check below to get more throughput, but then we * have a dependency towards non-generic chip features * to disable the TX-FIFO-EMPTY interrupts on a per * endpoint basis. Increase the maximum buffer size of * the IN endpoint to increase the performance. */ if (td->npkt > mpkt) { td->npkt = mpkt; count = td->max_packet_size * mpkt; } else if ((count == 0) || (count % td->max_packet_size)) { /* we are transmitting a short packet */ td->npkt++; td->short_pkt = 1; } } else { /* send one packet at a time */ mpkt = 1; count = td->max_packet_size; if (td->remainder < count) { /* we have a short packet */ td->short_pkt = 1; count = td->remainder; } td->npkt = 1; } DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), DXEPTSIZ_SET_MULTI(1) | DXEPTSIZ_SET_NPKT(td->npkt) | DXEPTSIZ_SET_NBYTES(count)); /* make room for buffering */ td->npkt += mpkt; temp = sc->sc_in_ctl[td->ep_no]; /* check for isochronous mode */ if ((temp & DIEPCTL_EPTYPE_MASK) == (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { /* toggle odd or even frame bit */ if (temp & DIEPCTL_SETD1PID) { temp &= ~DIEPCTL_SETD1PID; temp |= DIEPCTL_SETD0PID; } else { temp &= ~DIEPCTL_SETD0PID; temp |= DIEPCTL_SETD1PID; } sc->sc_in_ctl[td->ep_no] = temp; } /* must enable before writing data to FIFO */ DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | DIEPCTL_EPENA | DIEPCTL_CNAK); td->tx_bytes = count; /* check remainder */ if (td->tx_bytes == 0 && td->remainder == 0) { if (td->short_pkt) return (0); /* complete */ /* else we need to transmit a short packet */ } goto repeat; not_complete: return (1); /* not complete */ } static uint8_t dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint32_t temp; /* * If all packets are transferred we are complete: */ temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); /* check that all packets have been transferred */ if (DXEPTSIZ_GET_NPKT(temp) != 0) { DPRINTFN(5, "busy ep=%d\n", td->ep_no); goto not_complete; } return (0); not_complete: /* we only want to know if there is a SETUP packet or free IN packet */ temp = sc->sc_last_rx_status; if ((td->ep_no == 0) && (temp != 0) && (GRXSTSRD_CHNUM_GET(temp) == 0)) { if ((temp & GRXSTSRD_PKTSTS_MASK) == GRXSTSRD_STP_DATA || (temp & GRXSTSRD_PKTSTS_MASK) == GRXSTSRD_STP_COMPLETE) { DPRINTFN(5, "faking complete\n"); /* * Race condition: We are complete! */ return (0); } else { /* dump data - wrong direction */ dwc_otg_common_rx_ack(sc); } } return (1); /* not complete */ } static void dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) { struct dwc_otg_td *td; uint8_t toggle; uint8_t tmr_val; uint8_t tmr_res; DPRINTFN(9, "\n"); td = xfer->td_transfer_cache; if (td == NULL) return; while (1) { if ((td->func) (sc, td)) { /* operation in progress */ break; } if (((void *)td) == xfer->td_transfer_last) { goto done; } if (td->error_any) { goto done; } else if (td->remainder > 0) { /* * We had a short transfer. If there is no alternate * next, stop processing ! */ if (!td->alt_next) goto done; } /* * Fetch the next transfer descriptor and transfer * some flags to the next transfer descriptor */ tmr_res = td->tmr_res; tmr_val = td->tmr_val; toggle = td->toggle; td = td->obj_next; xfer->td_transfer_cache = td; td->toggle = toggle; /* transfer toggle */ td->tmr_res = tmr_res; td->tmr_val = tmr_val; } return; done: xfer->td_transfer_cache = NULL; sc->sc_xfer_complete = 1; } static uint8_t dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) { struct dwc_otg_td *td; DPRINTFN(9, "\n"); td = xfer->td_transfer_cache; if (td == NULL) { /* compute all actual lengths */ dwc_otg_standard_done(xfer); return (1); } return (0); } static void dwc_otg_timer(void *_sc) { struct dwc_otg_softc *sc = _sc; USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); DPRINTF("\n"); USB_BUS_SPIN_LOCK(&sc->sc_bus); /* increment timer value */ sc->sc_tmr_val++; /* enable SOF interrupt, which will poll jobs */ dwc_otg_enable_sof_irq(sc); USB_BUS_SPIN_UNLOCK(&sc->sc_bus); if (sc->sc_timer_active) { /* restart timer */ usb_callout_reset(&sc->sc_timer, hz / (1000 / DWC_OTG_HOST_TIMER_RATE), &dwc_otg_timer, sc); } } static void dwc_otg_timer_start(struct dwc_otg_softc *sc) { if (sc->sc_timer_active != 0) return; sc->sc_timer_active = 1; /* restart timer */ usb_callout_reset(&sc->sc_timer, hz / (1000 / DWC_OTG_HOST_TIMER_RATE), &dwc_otg_timer, sc); } static void dwc_otg_timer_stop(struct dwc_otg_softc *sc) { if (sc->sc_timer_active == 0) return; sc->sc_timer_active = 0; /* stop timer */ usb_callout_stop(&sc->sc_timer); } static uint16_t dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) { if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) pinfo->slot_index++; return (pinfo->slot_index); } static uint8_t dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) { TAILQ_HEAD(, usb_xfer) head; struct usb_xfer *xfer; struct usb_xfer *xfer_next; struct dwc_otg_td *td; uint16_t temp; uint16_t slot; temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; if (sc->sc_last_frame_num == temp) return (0); sc->sc_last_frame_num = temp; TAILQ_INIT(&head); if ((temp & 7) == 0) { /* reset the schedule */ memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { td = xfer->td_transfer_cache; if (td == NULL || td->ep_type != UE_ISOCHRONOUS) continue; /* check for IN direction */ if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) continue; sc->sc_needsof = 1; if (td->hcsplt == 0 || td->tt_scheduled != 0) continue; /* compute slot */ slot = dwc_otg_compute_isoc_rx_tt_slot( sc->sc_tt_info + td->tt_index); if (slot > 3) { /* * Not enough time to get complete * split executed. */ continue; } /* Delayed start */ td->tt_start_slot = temp + slot; td->tt_scheduled = 1; TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); TAILQ_INSERT_TAIL(&head, xfer, wait_entry); } TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { td = xfer->td_transfer_cache; if (td == NULL || td->ep_type != UE_ISOCHRONOUS) continue; /* check for OUT direction */ if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) continue; sc->sc_needsof = 1; if (td->hcsplt == 0 || td->tt_scheduled != 0) continue; /* Start ASAP */ td->tt_start_slot = temp; td->tt_scheduled = 1; TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); TAILQ_INSERT_TAIL(&head, xfer, wait_entry); } TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { td = xfer->td_transfer_cache; if (td == NULL || td->ep_type != UE_INTERRUPT) continue; if (td->tt_scheduled != 0) { sc->sc_needsof = 1; continue; } if (dwc_otg_host_rate_check_interrupt(sc, td)) continue; if (td->hcsplt == 0) { sc->sc_needsof = 1; td->tt_scheduled = 1; continue; } /* start ASAP */ td->tt_start_slot = temp; sc->sc_needsof = 1; td->tt_scheduled = 1; TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); TAILQ_INSERT_TAIL(&head, xfer, wait_entry); } TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { td = xfer->td_transfer_cache; if (td == NULL || td->ep_type != UE_CONTROL) { continue; } sc->sc_needsof = 1; if (td->hcsplt == 0 || td->tt_scheduled != 0) continue; /* start ASAP */ td->tt_start_slot = temp; td->tt_scheduled = 1; TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); TAILQ_INSERT_TAIL(&head, xfer, wait_entry); } } if ((temp & 7) < 6) { TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { td = xfer->td_transfer_cache; if (td == NULL || td->ep_type != UE_BULK) { continue; } sc->sc_needsof = 1; if (td->hcsplt == 0 || td->tt_scheduled != 0) continue; /* start ASAP */ td->tt_start_slot = temp; td->tt_scheduled = 1; TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); TAILQ_INSERT_TAIL(&head, xfer, wait_entry); } } /* Put TT transfers in execution order at the end */ TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); /* move all TT transfers in front, keeping the current order */ TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { td = xfer->td_transfer_cache; if (td == NULL || td->hcsplt == 0) continue; TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); TAILQ_INSERT_TAIL(&head, xfer, wait_entry); } TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); /* put non-TT non-ISOCHRONOUS transfers last */ TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { td = xfer->td_transfer_cache; if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS) continue; TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); TAILQ_INSERT_TAIL(&head, xfer, wait_entry); } TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); if ((temp & 7) == 0) { DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", (int)temp, (int)sc->sc_needsof); /* update SOF IRQ mask */ if (sc->sc_irq_mask & GINTMSK_SOFMSK) { if (sc->sc_needsof == 0) { sc->sc_irq_mask &= ~GINTMSK_SOFMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } } else { if (sc->sc_needsof != 0) { sc->sc_irq_mask |= GINTMSK_SOFMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } } /* clear need SOF flag */ sc->sc_needsof = 0; } return (1); } static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) { struct usb_xfer *xfer; uint32_t count; uint32_t temp; uint32_t haint; uint8_t got_rx_status; uint8_t x; if (sc->sc_flags.status_device_mode == 0) { /* * Update host transfer schedule, so that new * transfers can be issued: */ dwc_otg_update_host_transfer_schedule_locked(sc); } count = 0; repeat: if (++count == 16) { /* give other interrupts a chance */ DPRINTF("Yield\n"); return; } /* get all host channel interrupts */ haint = DWC_OTG_READ_4(sc, DOTG_HAINT); while (1) { x = ffs(haint) - 1; if (x >= sc->sc_host_ch_max) break; temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); temp &= ~HCINT_SOFTWARE_ONLY; sc->sc_chan_state[x].hcint |= temp; haint &= ~(1U << x); } if (sc->sc_last_rx_status == 0) { temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); if (temp & GINTSTS_RXFLVL) { /* pop current status */ sc->sc_last_rx_status = DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); } if (sc->sc_last_rx_status != 0) { uint8_t ep_no; temp = sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK; /* non-data messages we simply skip */ if (temp != GRXSTSRD_STP_DATA && temp != GRXSTSRD_STP_COMPLETE && temp != GRXSTSRD_OUT_DATA) { /* check for halted channel */ if (temp == GRXSTSRH_HALTED) { ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); sc->sc_chan_state[ep_no].wait_halted = 0; DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); } /* store bytes and FIFO offset */ sc->sc_current_rx_bytes = 0; sc->sc_current_rx_fifo = 0; /* acknowledge status */ dwc_otg_common_rx_ack(sc); goto repeat; } temp = GRXSTSRD_BCNT_GET( sc->sc_last_rx_status); ep_no = GRXSTSRD_CHNUM_GET( sc->sc_last_rx_status); /* store bytes and FIFO offset */ sc->sc_current_rx_bytes = (temp + 3) & ~3; sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no); DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); /* check if we should dump the data */ if (!(sc->sc_active_rx_ep & (1U << ep_no))) { dwc_otg_common_rx_ack(sc); goto repeat; } got_rx_status = 1; DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", sc->sc_last_rx_status, ep_no, (sc->sc_last_rx_status >> 15) & 3, GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), (sc->sc_last_rx_status >> 17) & 15); } else { got_rx_status = 0; } } else { uint8_t ep_no; ep_no = GRXSTSRD_CHNUM_GET( sc->sc_last_rx_status); /* check if we should dump the data */ if (!(sc->sc_active_rx_ep & (1U << ep_no))) { dwc_otg_common_rx_ack(sc); goto repeat; } got_rx_status = 1; } /* execute FIFOs */ TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) dwc_otg_xfer_do_fifo(sc, xfer); if (got_rx_status) { /* check if data was consumed */ if (sc->sc_last_rx_status == 0) goto repeat; /* disable RX FIFO level interrupt */ sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } } static void dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) { struct usb_xfer *xfer; repeat: /* scan for completion events */ TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { if (dwc_otg_xfer_do_complete_locked(sc, xfer)) goto repeat; } } static void dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) { DPRINTFN(5, "vbus = %u\n", is_on); /* * If the USB host mode is forced, then assume VBUS is always * present else rely on the input to this function: */ if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { if (!sc->sc_flags.status_vbus) { sc->sc_flags.status_vbus = 1; /* complete root HUB interrupt endpoint */ dwc_otg_root_intr(sc); } } else { if (sc->sc_flags.status_vbus) { sc->sc_flags.status_vbus = 0; sc->sc_flags.status_bus_reset = 0; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; /* complete root HUB interrupt endpoint */ dwc_otg_root_intr(sc); } } } int dwc_otg_filter_interrupt(void *arg) { struct dwc_otg_softc *sc = arg; int retval = FILTER_HANDLED; uint32_t status; USB_BUS_SPIN_LOCK(&sc->sc_bus); /* read and clear interrupt status */ status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); /* clear interrupts we are handling here */ DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); /* check for USB state change interrupts */ if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) retval = FILTER_SCHEDULE_THREAD; /* clear FIFO empty interrupts */ if (status & sc->sc_irq_mask & (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } /* clear all IN endpoint interrupts */ if (status & GINTSTS_IEPINT) { uint32_t temp; uint8_t x; for (x = 0; x != sc->sc_dev_in_ep_max; x++) { temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); /* * NOTE: Need to clear all interrupt bits, * because some appears to be unmaskable and * can cause an interrupt loop: */ if (temp != 0) DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp); } } /* poll FIFOs, if any */ dwc_otg_interrupt_poll_locked(sc); if (sc->sc_xfer_complete != 0) retval = FILTER_SCHEDULE_THREAD; USB_BUS_SPIN_UNLOCK(&sc->sc_bus); return (retval); } void dwc_otg_interrupt(void *arg) { struct dwc_otg_softc *sc = arg; uint32_t status; USB_BUS_LOCK(&sc->sc_bus); USB_BUS_SPIN_LOCK(&sc->sc_bus); /* read and clear interrupt status */ status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); /* clear interrupts we are handling here */ DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", status, DWC_OTG_READ_4(sc, DOTG_HAINT), DWC_OTG_READ_4(sc, DOTG_HFNUM)); if (status & GINTSTS_USBRST) { /* set correct state */ sc->sc_flags.status_device_mode = 1; sc->sc_flags.status_bus_reset = 0; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; /* Disable SOF interrupt */ sc->sc_irq_mask &= ~GINTMSK_SOFMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); /* complete root HUB interrupt endpoint */ dwc_otg_root_intr(sc); } /* check for any bus state change interrupts */ if (status & GINTSTS_ENUMDONE) { uint32_t temp; DPRINTFN(5, "end of reset\n"); /* set correct state */ sc->sc_flags.status_device_mode = 1; sc->sc_flags.status_bus_reset = 1; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; sc->sc_flags.status_low_speed = 0; sc->sc_flags.port_enabled = 1; /* reset FIFOs */ (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); /* reset function address */ dwc_otg_set_address(sc, 0); /* figure out enumeration speed */ temp = DWC_OTG_READ_4(sc, DOTG_DSTS); if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) sc->sc_flags.status_high_speed = 1; else sc->sc_flags.status_high_speed = 0; /* * Disable resume and SOF interrupt, and enable * suspend and RX frame interrupt: */ sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); /* complete root HUB interrupt endpoint */ dwc_otg_root_intr(sc); } if (status & GINTSTS_PRTINT) { uint32_t hprt; hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); /* clear change bits */ DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( HPRT_PRTPWR | HPRT_PRTENCHNG | HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | sc->sc_hprt_val); DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); sc->sc_flags.status_device_mode = 0; if (hprt & HPRT_PRTCONNSTS) sc->sc_flags.status_bus_reset = 1; else sc->sc_flags.status_bus_reset = 0; if ((hprt & HPRT_PRTENCHNG) && (hprt & HPRT_PRTENA) == 0) sc->sc_flags.change_enabled = 1; if (hprt & HPRT_PRTENA) sc->sc_flags.port_enabled = 1; else sc->sc_flags.port_enabled = 0; if (hprt & HPRT_PRTOVRCURRCHNG) sc->sc_flags.change_over_current = 1; if (hprt & HPRT_PRTOVRCURRACT) sc->sc_flags.port_over_current = 1; else sc->sc_flags.port_over_current = 0; if (hprt & HPRT_PRTPWR) sc->sc_flags.port_powered = 1; else sc->sc_flags.port_powered = 0; if (((hprt & HPRT_PRTSPD_MASK) >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) sc->sc_flags.status_low_speed = 1; else sc->sc_flags.status_low_speed = 0; if (((hprt & HPRT_PRTSPD_MASK) >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) sc->sc_flags.status_high_speed = 1; else sc->sc_flags.status_high_speed = 0; if (hprt & HPRT_PRTCONNDET) sc->sc_flags.change_connect = 1; if (hprt & HPRT_PRTSUSP) dwc_otg_suspend_irq(sc); else dwc_otg_resume_irq(sc); /* complete root HUB interrupt endpoint */ dwc_otg_root_intr(sc); /* update host frame interval */ dwc_otg_update_host_frame_interval(sc); } /* * If resume and suspend is set at the same time we interpret * that like RESUME. Resume is set when there is at least 3 * milliseconds of inactivity on the USB BUS. */ if (status & GINTSTS_WKUPINT) { DPRINTFN(5, "resume interrupt\n"); dwc_otg_resume_irq(sc); } else if (status & GINTSTS_USBSUSP) { DPRINTFN(5, "suspend interrupt\n"); dwc_otg_suspend_irq(sc); } /* check VBUS */ if (status & (GINTSTS_USBSUSP | GINTSTS_USBRST | GINTMSK_OTGINTMSK | GINTSTS_SESSREQINT)) { uint32_t temp; temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); dwc_otg_vbus_interrupt(sc, (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); } if (sc->sc_xfer_complete != 0) { sc->sc_xfer_complete = 0; /* complete FIFOs, if any */ dwc_otg_interrupt_complete_locked(sc); } USB_BUS_SPIN_UNLOCK(&sc->sc_bus); USB_BUS_UNLOCK(&sc->sc_bus); } static void dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) { struct dwc_otg_td *td; /* get current Transfer Descriptor */ td = temp->td_next; temp->td = td; /* prepare for next TD */ temp->td_next = td->obj_next; /* fill out the Transfer Descriptor */ td->func = temp->func; td->pc = temp->pc; td->offset = temp->offset; td->remainder = temp->len; td->tx_bytes = 0; td->error_any = 0; td->error_stall = 0; td->npkt = 0; td->did_stall = temp->did_stall; td->short_pkt = temp->short_pkt; td->alt_next = temp->setup_alt_next; td->set_toggle = 0; td->got_short = 0; td->did_nak = 0; td->channel[0] = DWC_OTG_MAX_CHANNELS; td->channel[1] = DWC_OTG_MAX_CHANNELS; td->channel[2] = DWC_OTG_MAX_CHANNELS; td->state = 0; td->errcnt = 0; td->tt_scheduled = 0; td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; } static void dwc_otg_setup_standard_chain(struct usb_xfer *xfer) { struct dwc_otg_std_temp temp; struct dwc_otg_td *td; uint32_t x; uint8_t need_sync; uint8_t is_host; DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", xfer->address, UE_GET_ADDR(xfer->endpointno), xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); temp.max_frame_size = xfer->max_frame_size; td = xfer->td_start[0]; xfer->td_transfer_first = td; xfer->td_transfer_cache = td; /* setup temp */ temp.pc = NULL; temp.td = NULL; temp.td_next = xfer->td_start[0]; temp.offset = 0; temp.setup_alt_next = xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr; temp.did_stall = !xfer->flags_int.control_stall; is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); /* check if we should prepend a setup message */ if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { if (is_host) temp.func = &dwc_otg_host_setup_tx; else temp.func = &dwc_otg_setup_rx; temp.len = xfer->frlengths[0]; temp.pc = xfer->frbuffers + 0; temp.short_pkt = temp.len ? 1 : 0; /* check for last frame */ if (xfer->nframes == 1) { /* no STATUS stage yet, SETUP is last */ if (xfer->flags_int.control_act) temp.setup_alt_next = 0; } dwc_otg_setup_standard_chain_sub(&temp); } x = 1; } else { x = 0; } if (x != xfer->nframes) { if (xfer->endpointno & UE_DIR_IN) { if (is_host) { temp.func = &dwc_otg_host_data_rx; need_sync = 0; } else { temp.func = &dwc_otg_data_tx; need_sync = 1; } } else { if (is_host) { temp.func = &dwc_otg_host_data_tx; need_sync = 0; } else { temp.func = &dwc_otg_data_rx; need_sync = 0; } } /* setup "pc" pointer */ temp.pc = xfer->frbuffers + x; } else { need_sync = 0; } while (x != xfer->nframes) { /* DATA0 / DATA1 message */ temp.len = xfer->frlengths[x]; x++; if (x == xfer->nframes) { if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_act) { temp.setup_alt_next = 0; } } else { temp.setup_alt_next = 0; } } if (temp.len == 0) { /* make sure that we send an USB packet */ temp.short_pkt = 0; } else { /* regular data transfer */ temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); } dwc_otg_setup_standard_chain_sub(&temp); if (xfer->flags_int.isochronous_xfr) { temp.offset += temp.len; } else { /* get next Page Cache pointer */ temp.pc = xfer->frbuffers + x; } } if (xfer->flags_int.control_xfr) { /* always setup a valid "pc" pointer for status and sync */ temp.pc = xfer->frbuffers + 0; temp.len = 0; temp.short_pkt = 0; temp.setup_alt_next = 0; /* check if we need to sync */ if (need_sync) { /* we need a SYNC point after TX */ temp.func = &dwc_otg_data_tx_sync; dwc_otg_setup_standard_chain_sub(&temp); } /* check if we should append a status stage */ if (!xfer->flags_int.control_act) { /* * Send a DATA1 message and invert the current * endpoint direction. */ if (xfer->endpointno & UE_DIR_IN) { if (is_host) { temp.func = &dwc_otg_host_data_tx; need_sync = 0; } else { temp.func = &dwc_otg_data_rx; need_sync = 0; } } else { if (is_host) { temp.func = &dwc_otg_host_data_rx; need_sync = 0; } else { temp.func = &dwc_otg_data_tx; need_sync = 1; } } dwc_otg_setup_standard_chain_sub(&temp); /* data toggle should be DATA1 */ td = temp.td; td->set_toggle = 1; if (need_sync) { /* we need a SYNC point after TX */ temp.func = &dwc_otg_data_tx_sync; dwc_otg_setup_standard_chain_sub(&temp); } } } else { /* check if we need to sync */ if (need_sync) { temp.pc = xfer->frbuffers + 0; temp.len = 0; temp.short_pkt = 0; temp.setup_alt_next = 0; /* we need a SYNC point after TX */ temp.func = &dwc_otg_data_tx_sync; dwc_otg_setup_standard_chain_sub(&temp); } } /* must have at least one frame! */ td = temp.td; xfer->td_transfer_last = td; if (is_host) { struct dwc_otg_softc *sc; uint32_t hcchar; uint32_t hcsplt; sc = DWC_OTG_BUS2SC(xfer->xroot->bus); /* get first again */ td = xfer->td_transfer_first; td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); hcchar = (xfer->address << HCCHAR_DEVADDR_SHIFT) | ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | HCCHAR_CHENA; /* * We are not always able to meet the timing * requirements of the USB interrupt endpoint's * complete split token, when doing transfers going * via a transaction translator. Use the CONTROL * transfer type instead of the INTERRUPT transfer * type in general, as a means to workaround * that. This trick should work for both FULL and LOW * speed USB traffic going through a TT. For non-TT * traffic it works as well. The reason for using * CONTROL type instead of BULK is that some TTs might * reject LOW speed BULK traffic. */ if (td->ep_type == UE_INTERRUPT) hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); else hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) hcchar |= HCCHAR_EPDIR_IN; switch (xfer->xroot->udev->speed) { case USB_SPEED_LOW: hcchar |= HCCHAR_LSPDDEV; /* FALLTHROUGH */ case USB_SPEED_FULL: /* check if root HUB port is running High Speed */ if (dwc_otg_uses_split(xfer->xroot->udev)) { hcsplt = HCSPLT_SPLTENA | (xfer->xroot->udev->hs_port_no << HCSPLT_PRTADDR_SHIFT) | (xfer->xroot->udev->hs_hub_addr << HCSPLT_HUBADDR_SHIFT); } else { hcsplt = 0; } if (td->ep_type == UE_INTERRUPT) { uint32_t ival; ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; if (ival == 0) ival = 1; else if (ival > 127) ival = 127; td->tmr_val = sc->sc_tmr_val + ival; td->tmr_res = ival; } else if (td->ep_type == UE_ISOCHRONOUS) { td->tmr_res = 1; td->tmr_val = sc->sc_last_frame_num; if (td->hcchar & HCCHAR_EPDIR_IN) td->tmr_val++; } else { td->tmr_val = 0; td->tmr_res = (uint8_t)sc->sc_last_frame_num; } break; case USB_SPEED_HIGH: hcsplt = 0; if (td->ep_type == UE_INTERRUPT) { uint32_t ival; hcchar |= ((xfer->max_packet_count & 3) << HCCHAR_MC_SHIFT); ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; if (ival == 0) ival = 1; else if (ival > 127) ival = 127; td->tmr_val = sc->sc_tmr_val + ival; td->tmr_res = ival; } else if (td->ep_type == UE_ISOCHRONOUS) { hcchar |= ((xfer->max_packet_count & 3) << HCCHAR_MC_SHIFT); td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); td->tmr_val = sc->sc_last_frame_num; if (td->hcchar & HCCHAR_EPDIR_IN) td->tmr_val += td->tmr_res; } else { td->tmr_val = 0; td->tmr_res = (uint8_t)sc->sc_last_frame_num; } break; default: hcsplt = 0; td->tmr_val = 0; td->tmr_res = 0; break; } /* store configuration in all TD's */ while (1) { td->hcchar = hcchar; td->hcsplt = hcsplt; if (((void *)td) == xfer->td_transfer_last) break; td = td->obj_next; } } } static void dwc_otg_timeout(void *arg) { struct usb_xfer *xfer = arg; DPRINTF("xfer=%p\n", xfer); USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); /* transfer is transferred */ dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); } static void dwc_otg_start_standard_chain(struct usb_xfer *xfer) { struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); DPRINTFN(9, "\n"); /* * Poll one time in device mode, which will turn on the * endpoint interrupts. Else wait for SOF interrupt in host * mode. */ USB_BUS_SPIN_LOCK(&sc->sc_bus); if (sc->sc_flags.status_device_mode != 0) { dwc_otg_xfer_do_fifo(sc, xfer); if (dwc_otg_xfer_do_complete_locked(sc, xfer)) goto done; } else { struct dwc_otg_td *td = xfer->td_transfer_cache; if (td->ep_type == UE_ISOCHRONOUS && (td->hcchar & HCCHAR_EPDIR_IN) == 0) { /* * Need to start ISOCHRONOUS OUT transfer ASAP * because execution is delayed by one 125us * microframe: */ dwc_otg_xfer_do_fifo(sc, xfer); if (dwc_otg_xfer_do_complete_locked(sc, xfer)) goto done; } } /* put transfer on interrupt queue */ usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); /* start timeout, if any */ if (xfer->timeout != 0) { usbd_transfer_timeout_ms(xfer, &dwc_otg_timeout, xfer->timeout); } if (sc->sc_flags.status_device_mode != 0) goto done; /* enable SOF interrupt, if any */ dwc_otg_enable_sof_irq(sc); done: USB_BUS_SPIN_UNLOCK(&sc->sc_bus); } static void dwc_otg_root_intr(struct dwc_otg_softc *sc) { DPRINTFN(9, "\n"); USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* set port bit */ sc->sc_hub_idata[0] = 0x02; /* we only have one port */ uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); } static usb_error_t dwc_otg_standard_done_sub(struct usb_xfer *xfer) { struct dwc_otg_td *td; uint32_t len; usb_error_t error; DPRINTFN(9, "\n"); td = xfer->td_transfer_cache; do { len = td->remainder; /* store last data toggle */ xfer->endpoint->toggle_next = td->toggle; if (xfer->aframes != xfer->nframes) { /* * Verify the length and subtract * the remainder from "frlengths[]": */ if (len > xfer->frlengths[xfer->aframes]) { td->error_any = 1; } else { xfer->frlengths[xfer->aframes] -= len; } } /* Check for transfer error */ if (td->error_any) { /* the transfer is finished */ error = (td->error_stall ? USB_ERR_STALLED : USB_ERR_IOERROR); td = NULL; break; } /* Check for short transfer */ if (len > 0) { if (xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr) { /* follow alt next */ if (td->alt_next) { td = td->obj_next; } else { td = NULL; } } else { /* the transfer is finished */ td = NULL; } error = 0; break; } td = td->obj_next; /* this USB frame is complete */ error = 0; break; } while (0); /* update transfer cache */ xfer->td_transfer_cache = td; return (error); } static void dwc_otg_standard_done(struct usb_xfer *xfer) { usb_error_t err = 0; DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", xfer, xfer->endpoint); /* reset scanner */ xfer->td_transfer_cache = xfer->td_transfer_first; if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { err = dwc_otg_standard_done_sub(xfer); } xfer->aframes = 1; if (xfer->td_transfer_cache == NULL) { goto done; } } while (xfer->aframes != xfer->nframes) { err = dwc_otg_standard_done_sub(xfer); xfer->aframes++; if (xfer->td_transfer_cache == NULL) { goto done; } } if (xfer->flags_int.control_xfr && !xfer->flags_int.control_act) { err = dwc_otg_standard_done_sub(xfer); } done: dwc_otg_device_done(xfer, err); } /*------------------------------------------------------------------------* * dwc_otg_device_done * * NOTE: this function can be called more than one time on the * same USB transfer! *------------------------------------------------------------------------*/ static void dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) { struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", xfer, xfer->endpoint, error); USB_BUS_SPIN_LOCK(&sc->sc_bus); if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { /* Interrupts are cleared by the interrupt handler */ } else { struct dwc_otg_td *td; td = xfer->td_transfer_cache; if (td != NULL) dwc_otg_host_channel_free(sc, td); } /* dequeue transfer and start next transfer */ usbd_transfer_done(xfer, error); USB_BUS_SPIN_UNLOCK(&sc->sc_bus); } static void dwc_otg_xfer_stall(struct usb_xfer *xfer) { dwc_otg_device_done(xfer, USB_ERR_STALLED); } static void dwc_otg_set_stall(struct usb_device *udev, struct usb_endpoint *ep, uint8_t *did_stall) { struct dwc_otg_softc *sc; uint32_t temp; uint32_t reg; uint8_t ep_no; USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); /* check mode */ if (udev->flags.usb_mode != USB_MODE_DEVICE) { /* not supported */ return; } sc = DWC_OTG_BUS2SC(udev->bus); USB_BUS_SPIN_LOCK(&sc->sc_bus); /* get endpoint address */ ep_no = ep->edesc->bEndpointAddress; DPRINTFN(5, "endpoint=0x%x\n", ep_no); if (ep_no & UE_DIR_IN) { reg = DOTG_DIEPCTL(ep_no & UE_ADDR); temp = sc->sc_in_ctl[ep_no & UE_ADDR]; } else { reg = DOTG_DOEPCTL(ep_no & UE_ADDR); temp = sc->sc_out_ctl[ep_no & UE_ADDR]; } /* disable and stall endpoint */ DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); /* clear active OUT ep */ if (!(ep_no & UE_DIR_IN)) { sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); if (sc->sc_last_rx_status != 0 && (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( sc->sc_last_rx_status)) { /* dump data */ dwc_otg_common_rx_ack(sc); /* poll interrupt */ dwc_otg_interrupt_poll_locked(sc); dwc_otg_interrupt_complete_locked(sc); } } USB_BUS_SPIN_UNLOCK(&sc->sc_bus); } static void dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) { uint32_t reg; uint32_t temp; if (ep_type == UE_CONTROL) { /* clearing stall is not needed */ return; } if (ep_dir) { reg = DOTG_DIEPCTL(ep_no); } else { reg = DOTG_DOEPCTL(ep_no); sc->sc_active_rx_ep |= (1U << ep_no); } /* round up and mask away the multiplier count */ mps = (mps + 3) & 0x7FC; if (ep_type == UE_BULK) { temp = DIEPCTL_EPTYPE_SET( DIEPCTL_EPTYPE_BULK) | DIEPCTL_USBACTEP; } else if (ep_type == UE_INTERRUPT) { temp = DIEPCTL_EPTYPE_SET( DIEPCTL_EPTYPE_INTERRUPT) | DIEPCTL_USBACTEP; } else { temp = DIEPCTL_EPTYPE_SET( DIEPCTL_EPTYPE_ISOC) | DIEPCTL_USBACTEP; } temp |= DIEPCTL_MPS_SET(mps); temp |= DIEPCTL_TXFNUM_SET(ep_no); if (ep_dir) sc->sc_in_ctl[ep_no] = temp; else sc->sc_out_ctl[ep_no] = temp; DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); /* we only reset the transmit FIFO */ if (ep_dir) { dwc_otg_tx_fifo_reset(sc, GRSTCTL_TXFIFO(ep_no) | GRSTCTL_TXFFLSH); DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(ep_no), 0); } /* poll interrupt */ dwc_otg_interrupt_poll_locked(sc); dwc_otg_interrupt_complete_locked(sc); } static void dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) { struct dwc_otg_softc *sc; struct usb_endpoint_descriptor *ed; DPRINTFN(5, "endpoint=%p\n", ep); USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); /* check mode */ if (udev->flags.usb_mode != USB_MODE_DEVICE) { /* not supported */ return; } /* get softc */ sc = DWC_OTG_BUS2SC(udev->bus); USB_BUS_SPIN_LOCK(&sc->sc_bus); /* get endpoint descriptor */ ed = ep->edesc; /* reset endpoint */ dwc_otg_clear_stall_sub_locked(sc, UGETW(ed->wMaxPacketSize), (ed->bEndpointAddress & UE_ADDR), (ed->bmAttributes & UE_XFERTYPE), (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); USB_BUS_SPIN_UNLOCK(&sc->sc_bus); } static void dwc_otg_device_state_change(struct usb_device *udev) { struct dwc_otg_softc *sc; uint8_t x; /* check mode */ if (udev->flags.usb_mode != USB_MODE_DEVICE) { /* not supported */ return; } /* get softc */ sc = DWC_OTG_BUS2SC(udev->bus); /* deactivate all other endpoint but the control endpoint */ if (udev->state == USB_STATE_CONFIGURED || udev->state == USB_STATE_ADDRESSED) { USB_BUS_LOCK(&sc->sc_bus); for (x = 1; x != sc->sc_dev_ep_max; x++) { if (x < sc->sc_dev_in_ep_max) { DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), DIEPCTL_EPDIS); DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); } DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), DOEPCTL_EPDIS); DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); } USB_BUS_UNLOCK(&sc->sc_bus); } } int dwc_otg_init(struct dwc_otg_softc *sc) { uint32_t temp; int err; DPRINTF("start\n"); sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); /* set up the bus structure */ sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = DWC_OTG_MAX_DEVICES; sc->sc_bus.dma_bits = 32; sc->sc_bus.usbrev = USB_REV_2_0; sc->sc_bus.methods = &dwc_otg_bus_methods; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(sc->sc_bus.parent), NULL)) { return (ENOMEM); } sc->sc_bus.bdev = device_add_child(sc->sc_bus.parent, "usbus", -1); if (sc->sc_bus.bdev == NULL) return (ENXIO); device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); err = bus_setup_intr(sc->sc_bus.parent, sc->sc_irq_res, INTR_TYPE_TTY | INTR_MPSAFE, &dwc_otg_filter_interrupt, &dwc_otg_interrupt, sc, &sc->sc_intr_hdl); if (err) { sc->sc_intr_hdl = NULL; return (ENXIO); } usb_callout_init_mtx(&sc->sc_timer, &sc->sc_bus.bus_mtx, 0); USB_BUS_LOCK(&sc->sc_bus); /* turn on clocks */ dwc_otg_clocks_on(sc); temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); DPRINTF("Version = 0x%08x\n", temp); /* disconnect */ DWC_OTG_WRITE_4(sc, DOTG_DCTL, DCTL_SFTDISCON); /* wait for host to detect disconnect */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, GRSTCTL_CSFTRST); /* wait a little bit for block to reset */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); switch (sc->sc_mode) { case DWC_MODE_DEVICE: temp = GUSBCFG_FORCEDEVMODE; break; case DWC_MODE_HOST: temp = GUSBCFG_FORCEHOSTMODE; break; default: temp = 0; break; } if (sc->sc_phy_type == 0) sc->sc_phy_type = dwc_otg_phy_type + 1; if (sc->sc_phy_bits == 0) sc->sc_phy_bits = 16; /* select HSIC, ULPI, UTMI+ or internal PHY mode */ switch (sc->sc_phy_type) { case DWC_OTG_PHY_HSIC: DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, GUSBCFG_PHYIF | GUSBCFG_TRD_TIM_SET(5) | temp); DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0x000000EC); temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, temp & ~GLPMCFG_HSIC_CONN); DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, temp | GLPMCFG_HSIC_CONN); break; case DWC_OTG_PHY_ULPI: DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_TRD_TIM_SET(5) | temp); DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, temp & ~GLPMCFG_HSIC_CONN); break; case DWC_OTG_PHY_UTMI: DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, (sc->sc_phy_bits == 16 ? GUSBCFG_PHYIF : 0) | GUSBCFG_TRD_TIM_SET(5) | temp); DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, temp & ~GLPMCFG_HSIC_CONN); break; case DWC_OTG_PHY_INTERNAL: DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, GUSBCFG_PHYSEL | GUSBCFG_TRD_TIM_SET(5) | temp); DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, temp & ~GLPMCFG_HSIC_CONN); temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | DOTG_GGPIO_PWRDWN); DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); break; default: break; } /* clear global nak */ DWC_OTG_WRITE_4(sc, DOTG_DCTL, DCTL_CGOUTNAK | DCTL_CGNPINNAK); /* disable USB port */ DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); /* wait 10ms */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); /* enable USB port */ DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); /* wait 10ms */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, sc->sc_host_ch_max); /* setup FIFO */ if (dwc_otg_init_fifo(sc, sc->sc_mode)) { USB_BUS_UNLOCK(&sc->sc_bus); return (EINVAL); } /* enable interrupts */ sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { /* enable all endpoint interrupts */ temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); if (temp & GHWCFG2_MPI) { uint8_t x; DPRINTF("Disable Multi Process Interrupts\n"); for (x = 0; x != sc->sc_dev_in_ep_max; x++) { DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); } DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); } DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, DIEPMSK_XFERCOMPLMSK); DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); } if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { /* setup clocks */ temp = DWC_OTG_READ_4(sc, DOTG_HCFG); temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); } /* only enable global IRQ */ DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, GAHBCFG_GLBLINTRMSK); /* turn off clocks */ dwc_otg_clocks_off(sc); /* read initial VBUS state */ temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); DPRINTFN(5, "GOTCTL=0x%08x\n", temp); dwc_otg_vbus_interrupt(sc, (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); USB_BUS_UNLOCK(&sc->sc_bus); /* catch any lost interrupts */ dwc_otg_do_poll(&sc->sc_bus); return (0); /* success */ } void dwc_otg_uninit(struct dwc_otg_softc *sc) { USB_BUS_LOCK(&sc->sc_bus); /* stop host timer */ dwc_otg_timer_stop(sc); /* set disconnect */ DWC_OTG_WRITE_4(sc, DOTG_DCTL, DCTL_SFTDISCON); /* turn off global IRQ */ DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); sc->sc_flags.port_enabled = 0; sc->sc_flags.port_powered = 0; sc->sc_flags.status_vbus = 0; sc->sc_flags.status_bus_reset = 0; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; dwc_otg_pull_down(sc); dwc_otg_clocks_off(sc); USB_BUS_UNLOCK(&sc->sc_bus); usb_callout_drain(&sc->sc_timer); } static void dwc_otg_suspend(struct dwc_otg_softc *sc) { return; } static void dwc_otg_resume(struct dwc_otg_softc *sc) { return; } static void dwc_otg_do_poll(struct usb_bus *bus) { struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); USB_BUS_LOCK(&sc->sc_bus); USB_BUS_SPIN_LOCK(&sc->sc_bus); dwc_otg_interrupt_poll_locked(sc); dwc_otg_interrupt_complete_locked(sc); USB_BUS_SPIN_UNLOCK(&sc->sc_bus); USB_BUS_UNLOCK(&sc->sc_bus); } /*------------------------------------------------------------------------* * DWC OTG bulk support * DWC OTG control support * DWC OTG interrupt support *------------------------------------------------------------------------*/ static void dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) { } static void dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) { dwc_otg_device_done(xfer, USB_ERR_CANCELLED); } static void dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) { } static void dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) { /* setup TDs */ dwc_otg_setup_standard_chain(xfer); dwc_otg_start_standard_chain(xfer); } static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = { .open = dwc_otg_device_non_isoc_open, .close = dwc_otg_device_non_isoc_close, .enter = dwc_otg_device_non_isoc_enter, .start = dwc_otg_device_non_isoc_start, }; /*------------------------------------------------------------------------* * DWC OTG full speed isochronous support *------------------------------------------------------------------------*/ static void dwc_otg_device_isoc_open(struct usb_xfer *xfer) { } static void dwc_otg_device_isoc_close(struct usb_xfer *xfer) { dwc_otg_device_done(xfer, USB_ERR_CANCELLED); } static void dwc_otg_device_isoc_enter(struct usb_xfer *xfer) { } static void dwc_otg_device_isoc_start(struct usb_xfer *xfer) { struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); uint32_t temp; uint32_t framenum; DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", xfer, xfer->endpoint->isoc_next, xfer->nframes); if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); /* get the current frame index */ framenum = (temp & HFNUM_FRNUM_MASK); } else { temp = DWC_OTG_READ_4(sc, DOTG_DSTS); /* get the current frame index */ framenum = DSTS_SOFFN_GET(temp); } /* * Check if port is doing 8000 or 1000 frames per second: */ if (sc->sc_flags.status_high_speed) framenum /= 8; if (usbd_xfer_get_isochronous_start_frame( xfer, framenum, 0, 1, DWC_OTG_FRAME_MASK, NULL)) DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); /* setup TDs */ dwc_otg_setup_standard_chain(xfer); /* start TD chain */ dwc_otg_start_standard_chain(xfer); } static const struct usb_pipe_methods dwc_otg_device_isoc_methods = { .open = dwc_otg_device_isoc_open, .close = dwc_otg_device_isoc_close, .enter = dwc_otg_device_isoc_enter, .start = dwc_otg_device_isoc_start, }; /*------------------------------------------------------------------------* * DWC OTG root control support *------------------------------------------------------------------------* * Simulate a hardware HUB by handling all the necessary requests. *------------------------------------------------------------------------*/ static const struct usb_device_descriptor dwc_otg_devd = { .bLength = sizeof(struct usb_device_descriptor), .bDescriptorType = UDESC_DEVICE, .bcdUSB = {0x00, 0x02}, .bDeviceClass = UDCLASS_HUB, .bDeviceSubClass = UDSUBCLASS_HUB, .bDeviceProtocol = UDPROTO_HSHUBSTT, .bMaxPacketSize = 64, .bcdDevice = {0x00, 0x01}, .iManufacturer = 1, .iProduct = 2, .bNumConfigurations = 1, }; static const struct dwc_otg_config_desc dwc_otg_confd = { .confd = { .bLength = sizeof(struct usb_config_descriptor), .bDescriptorType = UDESC_CONFIG, .wTotalLength[0] = sizeof(dwc_otg_confd), .bNumInterface = 1, .bConfigurationValue = 1, .iConfiguration = 0, .bmAttributes = UC_SELF_POWERED, .bMaxPower = 0, }, .ifcd = { .bLength = sizeof(struct usb_interface_descriptor), .bDescriptorType = UDESC_INTERFACE, .bNumEndpoints = 1, .bInterfaceClass = UICLASS_HUB, .bInterfaceSubClass = UISUBCLASS_HUB, .bInterfaceProtocol = 0, }, .endpd = { .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = UDESC_ENDPOINT, .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), .bmAttributes = UE_INTERRUPT, .wMaxPacketSize[0] = 8, .bInterval = 255, }, }; #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } static const struct usb_hub_descriptor_min dwc_otg_hubd = { .bDescLength = sizeof(dwc_otg_hubd), .bDescriptorType = UDESC_HUB, .bNbrPorts = 1, HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), .bPwrOn2PwrGood = 50, .bHubContrCurrent = 0, .DeviceRemovable = {0}, /* port is removable */ }; #define STRING_VENDOR \ "D\0W\0C\0O\0T\0G" #define STRING_PRODUCT \ "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); static usb_error_t dwc_otg_roothub_exec(struct usb_device *udev, struct usb_device_request *req, const void **pptr, uint16_t *plength) { struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); const void *ptr; uint16_t len; uint16_t value; uint16_t index; usb_error_t err; USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* buffer reset */ ptr = (const void *)&sc->sc_hub_temp; len = 0; err = 0; value = UGETW(req->wValue); index = UGETW(req->wIndex); /* demultiplex the control request */ switch (req->bmRequestType) { case UT_READ_DEVICE: switch (req->bRequest) { case UR_GET_DESCRIPTOR: goto tr_handle_get_descriptor; case UR_GET_CONFIG: goto tr_handle_get_config; case UR_GET_STATUS: goto tr_handle_get_status; default: goto tr_stalled; } break; case UT_WRITE_DEVICE: switch (req->bRequest) { case UR_SET_ADDRESS: goto tr_handle_set_address; case UR_SET_CONFIG: goto tr_handle_set_config; case UR_CLEAR_FEATURE: goto tr_valid; /* nop */ case UR_SET_DESCRIPTOR: goto tr_valid; /* nop */ case UR_SET_FEATURE: default: goto tr_stalled; } break; case UT_WRITE_ENDPOINT: switch (req->bRequest) { case UR_CLEAR_FEATURE: switch (UGETW(req->wValue)) { case UF_ENDPOINT_HALT: goto tr_handle_clear_halt; case UF_DEVICE_REMOTE_WAKEUP: goto tr_handle_clear_wakeup; default: goto tr_stalled; } break; case UR_SET_FEATURE: switch (UGETW(req->wValue)) { case UF_ENDPOINT_HALT: goto tr_handle_set_halt; case UF_DEVICE_REMOTE_WAKEUP: goto tr_handle_set_wakeup; default: goto tr_stalled; } break; case UR_SYNCH_FRAME: goto tr_valid; /* nop */ default: goto tr_stalled; } break; case UT_READ_ENDPOINT: switch (req->bRequest) { case UR_GET_STATUS: goto tr_handle_get_ep_status; default: goto tr_stalled; } break; case UT_WRITE_INTERFACE: switch (req->bRequest) { case UR_SET_INTERFACE: goto tr_handle_set_interface; case UR_CLEAR_FEATURE: goto tr_valid; /* nop */ case UR_SET_FEATURE: default: goto tr_stalled; } break; case UT_READ_INTERFACE: switch (req->bRequest) { case UR_GET_INTERFACE: goto tr_handle_get_interface; case UR_GET_STATUS: goto tr_handle_get_iface_status; default: goto tr_stalled; } break; case UT_WRITE_CLASS_INTERFACE: case UT_WRITE_VENDOR_INTERFACE: /* XXX forward */ break; case UT_READ_CLASS_INTERFACE: case UT_READ_VENDOR_INTERFACE: /* XXX forward */ break; case UT_WRITE_CLASS_DEVICE: switch (req->bRequest) { case UR_CLEAR_FEATURE: goto tr_valid; case UR_SET_DESCRIPTOR: case UR_SET_FEATURE: break; default: goto tr_stalled; } break; case UT_WRITE_CLASS_OTHER: switch (req->bRequest) { case UR_CLEAR_FEATURE: goto tr_handle_clear_port_feature; case UR_SET_FEATURE: goto tr_handle_set_port_feature; case UR_CLEAR_TT_BUFFER: case UR_RESET_TT: case UR_STOP_TT: goto tr_valid; default: goto tr_stalled; } break; case UT_READ_CLASS_OTHER: switch (req->bRequest) { case UR_GET_TT_STATE: goto tr_handle_get_tt_state; case UR_GET_STATUS: goto tr_handle_get_port_status; default: goto tr_stalled; } break; case UT_READ_CLASS_DEVICE: switch (req->bRequest) { case UR_GET_DESCRIPTOR: goto tr_handle_get_class_descriptor; case UR_GET_STATUS: goto tr_handle_get_class_status; default: goto tr_stalled; } break; default: goto tr_stalled; } goto tr_valid; tr_handle_get_descriptor: switch (value >> 8) { case UDESC_DEVICE: if (value & 0xff) { goto tr_stalled; } len = sizeof(dwc_otg_devd); ptr = (const void *)&dwc_otg_devd; goto tr_valid; case UDESC_CONFIG: if (value & 0xff) { goto tr_stalled; } len = sizeof(dwc_otg_confd); ptr = (const void *)&dwc_otg_confd; goto tr_valid; case UDESC_STRING: switch (value & 0xff) { case 0: /* Language table */ len = sizeof(usb_string_lang_en); ptr = (const void *)&usb_string_lang_en; goto tr_valid; case 1: /* Vendor */ len = sizeof(dwc_otg_vendor); ptr = (const void *)&dwc_otg_vendor; goto tr_valid; case 2: /* Product */ len = sizeof(dwc_otg_product); ptr = (const void *)&dwc_otg_product; goto tr_valid; default: break; } break; default: goto tr_stalled; } goto tr_stalled; tr_handle_get_config: len = 1; sc->sc_hub_temp.wValue[0] = sc->sc_conf; goto tr_valid; tr_handle_get_status: len = 2; USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); goto tr_valid; tr_handle_set_address: if (value & 0xFF00) { goto tr_stalled; } sc->sc_rt_addr = value; goto tr_valid; tr_handle_set_config: if (value >= 2) { goto tr_stalled; } sc->sc_conf = value; goto tr_valid; tr_handle_get_interface: len = 1; sc->sc_hub_temp.wValue[0] = 0; goto tr_valid; tr_handle_get_tt_state: tr_handle_get_class_status: tr_handle_get_iface_status: tr_handle_get_ep_status: len = 2; USETW(sc->sc_hub_temp.wValue, 0); goto tr_valid; tr_handle_set_halt: tr_handle_set_interface: tr_handle_set_wakeup: tr_handle_clear_wakeup: tr_handle_clear_halt: goto tr_valid; tr_handle_clear_port_feature: if (index != 1) goto tr_stalled; DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); switch (value) { case UHF_PORT_SUSPEND: dwc_otg_wakeup_peer(sc); break; case UHF_PORT_ENABLE: if (sc->sc_flags.status_device_mode == 0) { DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTENA); } sc->sc_flags.port_enabled = 0; break; case UHF_C_PORT_RESET: sc->sc_flags.change_reset = 0; break; case UHF_C_PORT_ENABLE: sc->sc_flags.change_enabled = 0; break; case UHF_C_PORT_OVER_CURRENT: sc->sc_flags.change_over_current = 0; break; case UHF_PORT_TEST: case UHF_PORT_INDICATOR: /* nops */ break; case UHF_PORT_POWER: sc->sc_flags.port_powered = 0; if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { sc->sc_hprt_val = 0; DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); } dwc_otg_pull_down(sc); dwc_otg_clocks_off(sc); break; case UHF_C_PORT_CONNECTION: /* clear connect change flag */ sc->sc_flags.change_connect = 0; break; case UHF_C_PORT_SUSPEND: sc->sc_flags.change_suspend = 0; break; default: err = USB_ERR_IOERROR; goto done; } goto tr_valid; tr_handle_set_port_feature: if (index != 1) { goto tr_stalled; } DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); switch (value) { case UHF_PORT_ENABLE: break; case UHF_PORT_SUSPEND: if (sc->sc_flags.status_device_mode == 0) { /* set suspend BIT */ sc->sc_hprt_val |= HPRT_PRTSUSP; DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); /* generate HUB suspend event */ dwc_otg_suspend_irq(sc); } break; case UHF_PORT_RESET: if (sc->sc_flags.status_device_mode == 0) { DPRINTF("PORT RESET\n"); /* enable PORT reset */ DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); /* Wait 62.5ms for reset to complete */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); /* Wait 62.5ms for reset to complete */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); /* reset FIFOs */ (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); sc->sc_flags.change_reset = 1; } else { err = USB_ERR_IOERROR; } break; case UHF_PORT_TEST: case UHF_PORT_INDICATOR: /* nops */ break; case UHF_PORT_POWER: sc->sc_flags.port_powered = 1; if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { sc->sc_hprt_val |= HPRT_PRTPWR; DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); } if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { /* pull up D+, if any */ dwc_otg_pull_up(sc); } break; default: err = USB_ERR_IOERROR; goto done; } goto tr_valid; tr_handle_get_port_status: DPRINTFN(9, "UR_GET_PORT_STATUS\n"); if (index != 1) goto tr_stalled; if (sc->sc_flags.status_vbus) dwc_otg_clocks_on(sc); else dwc_otg_clocks_off(sc); /* Select Device Side Mode */ if (sc->sc_flags.status_device_mode) { value = UPS_PORT_MODE_DEVICE; dwc_otg_timer_stop(sc); } else { value = 0; dwc_otg_timer_start(sc); } if (sc->sc_flags.status_high_speed) value |= UPS_HIGH_SPEED; else if (sc->sc_flags.status_low_speed) value |= UPS_LOW_SPEED; if (sc->sc_flags.port_powered) value |= UPS_PORT_POWER; if (sc->sc_flags.port_enabled) value |= UPS_PORT_ENABLED; if (sc->sc_flags.port_over_current) value |= UPS_OVERCURRENT_INDICATOR; if (sc->sc_flags.status_vbus && sc->sc_flags.status_bus_reset) value |= UPS_CURRENT_CONNECT_STATUS; if (sc->sc_flags.status_suspend) value |= UPS_SUSPEND; USETW(sc->sc_hub_temp.ps.wPortStatus, value); value = 0; if (sc->sc_flags.change_enabled) value |= UPS_C_PORT_ENABLED; if (sc->sc_flags.change_connect) value |= UPS_C_CONNECT_STATUS; if (sc->sc_flags.change_suspend) value |= UPS_C_SUSPEND; if (sc->sc_flags.change_reset) value |= UPS_C_PORT_RESET; if (sc->sc_flags.change_over_current) value |= UPS_C_OVERCURRENT_INDICATOR; USETW(sc->sc_hub_temp.ps.wPortChange, value); len = sizeof(sc->sc_hub_temp.ps); goto tr_valid; tr_handle_get_class_descriptor: if (value & 0xFF) { goto tr_stalled; } ptr = (const void *)&dwc_otg_hubd; len = sizeof(dwc_otg_hubd); goto tr_valid; tr_stalled: err = USB_ERR_STALLED; tr_valid: done: *plength = len; *pptr = ptr; return (err); } static void dwc_otg_xfer_setup(struct usb_setup_params *parm) { struct usb_xfer *xfer; void *last_obj; uint32_t ntd; uint32_t n; uint8_t ep_no; uint8_t ep_type; xfer = parm->curr_xfer; /* * NOTE: This driver does not use any of the parameters that * are computed from the following values. Just set some * reasonable dummies: */ parm->hc_max_packet_size = 0x500; parm->hc_max_packet_count = 3; parm->hc_max_frame_size = 3 * 0x500; usbd_transfer_setup_sub(parm); /* * compute maximum number of TDs */ ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); if (ep_type == UE_CONTROL) { ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; } else { ntd = xfer->nframes + 1 /* SYNC */ ; } /* * check if "usbd_transfer_setup_sub" set an error */ if (parm->err) return; /* * allocate transfer descriptors */ last_obj = NULL; ep_no = xfer->endpointno & UE_ADDR; /* * Check for a valid endpoint profile in USB device mode: */ if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { const struct usb_hw_ep_profile *pf; dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); if (pf == NULL) { /* should not happen */ parm->err = USB_ERR_INVAL; return; } } /* align data */ parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); for (n = 0; n != ntd; n++) { struct dwc_otg_td *td; if (parm->buf) { td = USB_ADD_BYTES(parm->buf, parm->size[0]); /* compute shared bandwidth resource index for TT */ if (dwc_otg_uses_split(parm->udev)) { if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) td->tt_index = parm->udev->device_index; else td->tt_index = parm->udev->parent_hs_hub->device_index; } else { td->tt_index = parm->udev->device_index; } /* init TD */ td->max_packet_size = xfer->max_packet_size; td->max_packet_count = xfer->max_packet_count; /* range check */ if (td->max_packet_count == 0 || td->max_packet_count > 3) td->max_packet_count = 1; td->ep_no = ep_no; td->ep_type = ep_type; td->obj_next = last_obj; last_obj = td; } parm->size[0] += sizeof(*td); } xfer->td_start[0] = last_obj; } static void dwc_otg_xfer_unsetup(struct usb_xfer *xfer) { return; } static void dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, struct usb_endpoint *ep) { struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode, sc->sc_rt_addr, udev->device_index); if (udev->device_index != sc->sc_rt_addr) { if (udev->flags.usb_mode == USB_MODE_DEVICE) { if (udev->speed != USB_SPEED_FULL && udev->speed != USB_SPEED_HIGH) { /* not supported */ return; } } else { if (udev->speed == USB_SPEED_HIGH && (edesc->wMaxPacketSize[1] & 0x18) != 0 && (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { /* not supported */ DPRINTFN(-1, "Non-isochronous high bandwidth " "endpoint not supported\n"); return; } } if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) ep->methods = &dwc_otg_device_isoc_methods; else ep->methods = &dwc_otg_device_non_isoc_methods; } } static void dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) { struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); switch (state) { case USB_HW_POWER_SUSPEND: dwc_otg_suspend(sc); break; case USB_HW_POWER_SHUTDOWN: dwc_otg_uninit(sc); break; case USB_HW_POWER_RESUME: dwc_otg_resume(sc); break; default: break; } } static void dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) { /* DMA delay - wait until any use of memory is finished */ *pus = (2125); /* microseconds */ } static void dwc_otg_device_resume(struct usb_device *udev) { DPRINTF("\n"); /* poll all transfers again to restart resumed ones */ dwc_otg_do_poll(udev->bus); } static void dwc_otg_device_suspend(struct usb_device *udev) { DPRINTF("\n"); } static const struct usb_bus_methods dwc_otg_bus_methods = { .endpoint_init = &dwc_otg_ep_init, .xfer_setup = &dwc_otg_xfer_setup, .xfer_unsetup = &dwc_otg_xfer_unsetup, .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, .xfer_stall = &dwc_otg_xfer_stall, .set_stall = &dwc_otg_set_stall, .clear_stall = &dwc_otg_clear_stall, .roothub_exec = &dwc_otg_roothub_exec, .xfer_poll = &dwc_otg_do_poll, .device_state_change = &dwc_otg_device_state_change, .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, .get_dma_delay = &dwc_otg_get_dma_delay, .device_resume = &dwc_otg_device_resume, .device_suspend = &dwc_otg_device_suspend, }; diff --git a/sys/dev/usb/controller/musb_otg.c b/sys/dev/usb/controller/musb_otg.c index fd2f7e72c43a..aa24544f8893 100644 --- a/sys/dev/usb/controller/musb_otg.c +++ b/sys/dev/usb/controller/musb_otg.c @@ -1,4195 +1,4194 @@ /* $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Thanks to Mentor Graphics for providing a reference driver for this USB chip * at their homepage. */ /* * This file contains the driver for the Mentor Graphics Inventra USB * 2.0 High Speed Dual-Role controller. * */ #ifdef USB_GLOBAL_INCLUDE_FILE #include USB_GLOBAL_INCLUDE_FILE #else #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define USB_DEBUG_VAR musbotgdebug #include #include #include #include #include #include #include #include #include #include #endif /* USB_GLOBAL_INCLUDE_FILE */ #include #define MUSBOTG_INTR_ENDPT 1 #define MUSBOTG_BUS2SC(bus) \ - ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ - USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) + __containerof(bus, struct musbotg_softc, sc_bus) #define MUSBOTG_PC2SC(pc) \ MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) #ifdef USB_DEBUG static int musbotgdebug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, "USB musbotg"); SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN, &musbotgdebug, 0, "Debug level"); #endif #define MAX_NAK_TO 16 /* prototypes */ static const struct usb_bus_methods musbotg_bus_methods; static const struct usb_pipe_methods musbotg_device_bulk_methods; static const struct usb_pipe_methods musbotg_device_ctrl_methods; static const struct usb_pipe_methods musbotg_device_intr_methods; static const struct usb_pipe_methods musbotg_device_isoc_methods; /* Control transfers: Device mode */ static musbotg_cmd_t musbotg_dev_ctrl_setup_rx; static musbotg_cmd_t musbotg_dev_ctrl_data_rx; static musbotg_cmd_t musbotg_dev_ctrl_data_tx; static musbotg_cmd_t musbotg_dev_ctrl_status; /* Control transfers: Host mode */ static musbotg_cmd_t musbotg_host_ctrl_setup_tx; static musbotg_cmd_t musbotg_host_ctrl_data_rx; static musbotg_cmd_t musbotg_host_ctrl_data_tx; static musbotg_cmd_t musbotg_host_ctrl_status_rx; static musbotg_cmd_t musbotg_host_ctrl_status_tx; /* Bulk, Interrupt, Isochronous: Device mode */ static musbotg_cmd_t musbotg_dev_data_rx; static musbotg_cmd_t musbotg_dev_data_tx; /* Bulk, Interrupt, Isochronous: Host mode */ static musbotg_cmd_t musbotg_host_data_rx; static musbotg_cmd_t musbotg_host_data_tx; static void musbotg_device_done(struct usb_xfer *, usb_error_t); static void musbotg_do_poll(struct usb_bus *); static void musbotg_standard_done(struct usb_xfer *); static void musbotg_interrupt_poll(struct musbotg_softc *); static void musbotg_root_intr(struct musbotg_softc *); static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t); static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td); static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on); /* * Here is a configuration that the chip supports. */ static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { [0] = { .max_in_frame_size = 64,/* fixed */ .max_out_frame_size = 64, /* fixed */ .is_simplex = 1, .support_control = 1, } }; static const struct musb_otg_ep_cfg musbotg_ep_default[] = { { .ep_end = 1, .ep_fifosz_shift = 12, .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_4096 | MUSB2_MASK_FIFODB, }, { .ep_end = 7, .ep_fifosz_shift = 10, .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512 | MUSB2_MASK_FIFODB, }, { .ep_end = 15, .ep_fifosz_shift = 7, .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_128, }, { .ep_end = -1, }, }; static int musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx) { int ch; int ep; ep = td->ep_no; /* In device mode each EP got its own channel */ if (sc->sc_mode == MUSB2_DEVICE_MODE) { musbotg_ep_int_set(sc, ep, 1); return (ep); } /* * All control transactions go through EP0 */ if (ep == 0) { if (sc->sc_channel_mask & (1 << 0)) return (-1); sc->sc_channel_mask |= (1 << 0); musbotg_ep_int_set(sc, ep, 1); return (0); } for (ch = sc->sc_ep_max; ch != 0; ch--) { if (sc->sc_channel_mask & (1 << ch)) continue; /* check FIFO size requirement */ if (is_tx) { if (td->max_frame_size > sc->sc_hw_ep_profile[ch].max_in_frame_size) continue; } else { if (td->max_frame_size > sc->sc_hw_ep_profile[ch].max_out_frame_size) continue; } sc->sc_channel_mask |= (1 << ch); musbotg_ep_int_set(sc, ch, 1); return (ch); } DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask); return (-1); } static void musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td) { DPRINTFN(1, "ep_no=%d\n", td->channel); if (sc->sc_mode == MUSB2_DEVICE_MODE) return; if (td == NULL) return; if (td->channel == -1) return; musbotg_ep_int_set(sc, td->channel, 0); sc->sc_channel_mask &= ~(1 << td->channel); td->channel = -1; } static void musbotg_get_hw_ep_profile(struct usb_device *udev, const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) { struct musbotg_softc *sc; sc = MUSBOTG_BUS2SC(udev->bus); if (ep_addr == 0) { /* control endpoint */ *ppf = musbotg_ep_profile; } else if (ep_addr <= sc->sc_ep_max) { /* other endpoints */ *ppf = sc->sc_hw_ep_profile + ep_addr; } else { *ppf = NULL; } } static void musbotg_clocks_on(struct musbotg_softc *sc) { if (sc->sc_flags.clocks_off && sc->sc_flags.port_powered) { DPRINTFN(4, "\n"); if (sc->sc_clocks_on) { (sc->sc_clocks_on) (sc->sc_clocks_arg); } sc->sc_flags.clocks_off = 0; /* XXX enable Transceiver */ } } static void musbotg_clocks_off(struct musbotg_softc *sc) { if (!sc->sc_flags.clocks_off) { DPRINTFN(4, "\n"); /* XXX disable Transceiver */ if (sc->sc_clocks_off) { (sc->sc_clocks_off) (sc->sc_clocks_arg); } sc->sc_flags.clocks_off = 1; } } static void musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) { uint8_t temp; temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); if (on) temp |= MUSB2_MASK_SOFTC; else temp &= ~MUSB2_MASK_SOFTC; MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); } static void musbotg_pull_up(struct musbotg_softc *sc) { /* pullup D+, if possible */ if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) { sc->sc_flags.d_pulled_up = 1; musbotg_pull_common(sc, 1); } } static void musbotg_pull_down(struct musbotg_softc *sc) { /* pulldown D+, if possible */ if (sc->sc_flags.d_pulled_up) { sc->sc_flags.d_pulled_up = 0; musbotg_pull_common(sc, 0); } } static void musbotg_suspend_host(struct musbotg_softc *sc) { uint8_t temp; if (sc->sc_flags.status_suspend) { return; } temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); temp |= MUSB2_MASK_SUSPMODE; MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); sc->sc_flags.status_suspend = 1; } static void musbotg_wakeup_host(struct musbotg_softc *sc) { uint8_t temp; if (!(sc->sc_flags.status_suspend)) { return; } temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); temp &= ~MUSB2_MASK_SUSPMODE; temp |= MUSB2_MASK_RESUME; MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); /* wait 20 milliseconds */ /* Wait for reset to complete. */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); temp &= ~MUSB2_MASK_RESUME; MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); sc->sc_flags.status_suspend = 0; } static void musbotg_wakeup_peer(struct musbotg_softc *sc) { uint8_t temp; if (!(sc->sc_flags.status_suspend)) { return; } temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); temp |= MUSB2_MASK_RESUME; MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); /* wait 8 milliseconds */ /* Wait for reset to complete. */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); temp &= ~MUSB2_MASK_RESUME; MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); } static void musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) { DPRINTFN(4, "addr=%d\n", addr); addr &= 0x7F; MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); } static uint8_t musbotg_dev_ctrl_setup_rx(struct musbotg_td *td) { struct musbotg_softc *sc; struct usb_device_request req; uint16_t count; uint8_t csr; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); if (td->channel == -1) td->channel = musbotg_channel_alloc(sc, td, 0); /* EP0 is busy, wait */ if (td->channel == -1) return (1); DPRINTFN(1, "ep_no=%d\n", td->channel); /* select endpoint 0 */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); /* * NOTE: If DATAEND is set we should not call the * callback, hence the status stage is not complete. */ if (csr & MUSB2_MASK_CSR0L_DATAEND) { /* do not stall at this point */ td->did_stall = 1; /* wait for interrupt */ DPRINTFN(1, "CSR0 DATAEND\n"); goto not_complete; } if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { /* clear SENTSTALL */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); /* get latest status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); /* update EP0 state */ sc->sc_ep0_busy = 0; } if (csr & MUSB2_MASK_CSR0L_SETUPEND) { /* clear SETUPEND */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_SETUPEND_CLR); /* get latest status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); /* update EP0 state */ sc->sc_ep0_busy = 0; } if (sc->sc_ep0_busy) { DPRINTFN(1, "EP0 BUSY\n"); goto not_complete; } if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { goto not_complete; } /* get the packet byte count */ count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); /* verify data length */ if (count != td->remainder) { DPRINTFN(1, "Invalid SETUP packet " "length, %d bytes\n", count); MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_RXPKTRDY_CLR); /* don't clear stall */ td->did_stall = 1; goto not_complete; } if (count != sizeof(req)) { DPRINTFN(1, "Unsupported SETUP packet " "length, %d bytes\n", count); MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_RXPKTRDY_CLR); /* don't clear stall */ td->did_stall = 1; goto not_complete; } /* clear did stall flag */ td->did_stall = 0; /* receive data */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); /* copy data into real buffer */ usbd_copy_in(td->pc, 0, &req, sizeof(req)); td->offset = sizeof(req); td->remainder = 0; /* set pending command */ sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; /* we need set stall or dataend after this */ sc->sc_ep0_busy = 1; /* sneak peek the set address */ if ((req.bmRequestType == UT_WRITE_DEVICE) && (req.bRequest == UR_SET_ADDRESS)) { sc->sc_dv_addr = req.wValue[0] & 0x7F; } else { sc->sc_dv_addr = 0xFF; } musbotg_channel_free(sc, td); return (0); /* complete */ not_complete: /* abort any ongoing transfer */ if (!td->did_stall) { DPRINTFN(4, "stalling\n"); MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_SENDSTALL); td->did_stall = 1; } return (1); /* not complete */ } static uint8_t musbotg_host_ctrl_setup_tx(struct musbotg_td *td) { struct musbotg_softc *sc; struct usb_device_request req; uint8_t csr, csrh; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); if (td->channel == -1) td->channel = musbotg_channel_alloc(sc, td, 1); /* EP0 is busy, wait */ if (td->channel == -1) return (1); DPRINTFN(1, "ep_no=%d\n", td->channel); /* select endpoint 0 */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); /* Not ready yet yet */ if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) return (1); /* Failed */ if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { /* Clear status bit */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); td->error = 1; } if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { DPRINTFN(1, "NAK timeout\n"); if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); csrh |= MUSB2_MASK_CSR0H_FFLUSH; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); csrh |= MUSB2_MASK_CSR0H_FFLUSH; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); } } csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); td->error = 1; } if (td->error) { musbotg_channel_free(sc, td); return (0); } /* Fifo is not empty and there is no NAK timeout */ if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) return (1); /* check if we are complete */ if (td->remainder == 0) { /* we are complete */ musbotg_channel_free(sc, td); return (0); } /* copy data into real buffer */ usbd_copy_out(td->pc, 0, &req, sizeof(req)); /* send data */ bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); /* update offset and remainder */ td->offset += sizeof(req); td->remainder -= sizeof(req); MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); /* write command */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); /* Just to be consistent, not used above */ td->transaction_started = 1; return (1); /* in progress */ } /* Control endpoint only data handling functions (RX/TX/SYNC) */ static uint8_t musbotg_dev_ctrl_data_rx(struct musbotg_td *td) { struct usb_page_search buf_res; struct musbotg_softc *sc; uint16_t count; uint8_t csr; uint8_t got_short; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); /* select endpoint 0 */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); /* check if a command is pending */ if (sc->sc_ep0_cmd) { MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); sc->sc_ep0_cmd = 0; } /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); got_short = 0; if (csr & (MUSB2_MASK_CSR0L_SETUPEND | MUSB2_MASK_CSR0L_SENTSTALL)) { if (td->remainder == 0) { /* * We are actually complete and have * received the next SETUP */ DPRINTFN(4, "faking complete\n"); return (0); /* complete */ } /* * USB Host Aborted the transfer. */ td->error = 1; return (0); /* complete */ } if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { return (1); /* not complete */ } /* get the packet byte count */ count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); /* verify the packet byte count */ if (count != td->max_frame_size) { if (count < td->max_frame_size) { /* we have a short packet */ td->short_pkt = 1; got_short = 1; } else { /* invalid USB packet */ td->error = 1; return (0); /* we are complete */ } } /* verify the packet byte count */ if (count > td->remainder) { /* invalid USB packet */ td->error = 1; return (0); /* we are complete */ } while (count > 0) { uint32_t temp; usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* check for unaligned memory address */ if (USB_P2U(buf_res.buffer) & 3) { temp = count & ~3; if (temp) { /* receive data 4 bytes at a time */ bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, temp / 4); } temp = count & 3; if (temp) { /* receive data 1 byte at a time */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), (void *)(&sc->sc_bounce_buf[count / 4]), temp); } usbd_copy_in(td->pc, td->offset, sc->sc_bounce_buf, count); /* update offset and remainder */ td->offset += count; td->remainder -= count; break; } /* check if we can optimise */ if (buf_res.length >= 4) { /* receive data 4 bytes at a time */ bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length / 4); temp = buf_res.length & ~3; /* update counters */ count -= temp; td->offset += temp; td->remainder -= temp; continue; } /* receive data */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* check if we are complete */ if ((td->remainder == 0) || got_short) { if (td->short_pkt) { /* we are complete */ sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; return (0); } /* else need to receive a zero length packet */ } /* write command - need more data */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_RXPKTRDY_CLR); return (1); /* not complete */ } static uint8_t musbotg_dev_ctrl_data_tx(struct musbotg_td *td) { struct usb_page_search buf_res; struct musbotg_softc *sc; uint16_t count; uint8_t csr; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); /* select endpoint 0 */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); /* check if a command is pending */ if (sc->sc_ep0_cmd) { MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); sc->sc_ep0_cmd = 0; } /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); if (csr & (MUSB2_MASK_CSR0L_SETUPEND | MUSB2_MASK_CSR0L_SENTSTALL)) { /* * The current transfer was aborted * by the USB Host */ td->error = 1; return (0); /* complete */ } if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { return (1); /* not complete */ } count = td->max_frame_size; if (td->remainder < count) { /* we have a short packet */ td->short_pkt = 1; count = td->remainder; } while (count > 0) { uint32_t temp; usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* check for unaligned memory address */ if (USB_P2U(buf_res.buffer) & 3) { usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buf, count); temp = count & ~3; if (temp) { /* transmit data 4 bytes at a time */ bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, temp / 4); } temp = count & 3; if (temp) { /* receive data 1 byte at a time */ bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), ((void *)&sc->sc_bounce_buf[count / 4]), temp); } /* update offset and remainder */ td->offset += count; td->remainder -= count; break; } /* check if we can optimise */ if (buf_res.length >= 4) { /* transmit data 4 bytes at a time */ bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length / 4); temp = buf_res.length & ~3; /* update counters */ count -= temp; td->offset += temp; td->remainder -= temp; continue; } /* transmit data */ bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* check remainder */ if (td->remainder == 0) { if (td->short_pkt) { sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; return (0); /* complete */ } /* else we need to transmit a short packet */ } /* write command */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); return (1); /* not complete */ } static uint8_t musbotg_host_ctrl_data_rx(struct musbotg_td *td) { struct usb_page_search buf_res; struct musbotg_softc *sc; uint16_t count; uint8_t csr; uint8_t got_short; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); if (td->channel == -1) td->channel = musbotg_channel_alloc(sc, td, 0); /* EP0 is busy, wait */ if (td->channel == -1) return (1); DPRINTFN(1, "ep_no=%d\n", td->channel); /* select endpoint 0 */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); got_short = 0; if (!td->transaction_started) { td->transaction_started = 1; MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), td->dev_addr); MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); return (1); } if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { csr &= ~MUSB2_MASK_CSR0L_REQPKT; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); td->error = 1; } /* Failed */ if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { /* Clear status bit */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); td->error = 1; } if (td->error) { musbotg_channel_free(sc, td); return (0); /* we are complete */ } if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) return (1); /* not yet */ /* get the packet byte count */ count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); /* verify the packet byte count */ if (count != td->max_frame_size) { if (count < td->max_frame_size) { /* we have a short packet */ td->short_pkt = 1; got_short = 1; } else { /* invalid USB packet */ td->error = 1; musbotg_channel_free(sc, td); return (0); /* we are complete */ } } /* verify the packet byte count */ if (count > td->remainder) { /* invalid USB packet */ td->error = 1; musbotg_channel_free(sc, td); return (0); /* we are complete */ } while (count > 0) { uint32_t temp; usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* check for unaligned memory address */ if (USB_P2U(buf_res.buffer) & 3) { temp = count & ~3; if (temp) { /* receive data 4 bytes at a time */ bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, temp / 4); } temp = count & 3; if (temp) { /* receive data 1 byte at a time */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), (void *)(&sc->sc_bounce_buf[count / 4]), temp); } usbd_copy_in(td->pc, td->offset, sc->sc_bounce_buf, count); /* update offset and remainder */ td->offset += count; td->remainder -= count; break; } /* check if we can optimise */ if (buf_res.length >= 4) { /* receive data 4 bytes at a time */ bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length / 4); temp = buf_res.length & ~3; /* update counters */ count -= temp; td->offset += temp; td->remainder -= temp; continue; } /* receive data */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); /* check if we are complete */ if ((td->remainder == 0) || got_short) { if (td->short_pkt) { /* we are complete */ musbotg_channel_free(sc, td); return (0); } /* else need to receive a zero length packet */ } td->transaction_started = 1; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); return (1); /* not complete */ } static uint8_t musbotg_host_ctrl_data_tx(struct musbotg_td *td) { struct usb_page_search buf_res; struct musbotg_softc *sc; uint16_t count; uint8_t csr, csrh; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); if (td->channel == -1) td->channel = musbotg_channel_alloc(sc, td, 1); /* No free EPs */ if (td->channel == -1) return (1); DPRINTFN(1, "ep_no=%d\n", td->channel); /* select endpoint */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { /* clear status bits */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); td->error = 1; } if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) { if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); csrh |= MUSB2_MASK_CSR0H_FFLUSH; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); csrh |= MUSB2_MASK_CSR0H_FFLUSH; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); } } csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); td->error = 1; } if (td->error) { musbotg_channel_free(sc, td); return (0); /* complete */ } /* * Wait while FIFO is empty. * Do not flush it because it will cause transactions * with size more then packet size. It might upset * some devices */ if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) return (1); /* Packet still being processed */ if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) return (1); if (td->transaction_started) { /* check remainder */ if (td->remainder == 0) { if (td->short_pkt) { musbotg_channel_free(sc, td); return (0); /* complete */ } /* else we need to transmit a short packet */ } /* We're not complete - more transactions required */ td->transaction_started = 0; } /* check for short packet */ count = td->max_frame_size; if (td->remainder < count) { /* we have a short packet */ td->short_pkt = 1; count = td->remainder; } while (count > 0) { uint32_t temp; usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* check for unaligned memory address */ if (USB_P2U(buf_res.buffer) & 3) { usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buf, count); temp = count & ~3; if (temp) { /* transmit data 4 bytes at a time */ bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, temp / 4); } temp = count & 3; if (temp) { /* receive data 1 byte at a time */ bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), ((void *)&sc->sc_bounce_buf[count / 4]), temp); } /* update offset and remainder */ td->offset += count; td->remainder -= count; break; } /* check if we can optimise */ if (buf_res.length >= 4) { /* transmit data 4 bytes at a time */ bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length / 4); temp = buf_res.length & ~3; /* update counters */ count -= temp; td->offset += temp; td->remainder -= temp; continue; } /* transmit data */ bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* Function address */ MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); /* TX NAK timeout */ MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); /* write command */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); td->transaction_started = 1; return (1); /* not complete */ } static uint8_t musbotg_dev_ctrl_status(struct musbotg_td *td) { struct musbotg_softc *sc; uint8_t csr; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); /* select endpoint 0 */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); if (sc->sc_ep0_busy) { sc->sc_ep0_busy = 0; sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); sc->sc_ep0_cmd = 0; } /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); if (csr & MUSB2_MASK_CSR0L_DATAEND) { /* wait for interrupt */ return (1); /* not complete */ } if (sc->sc_dv_addr != 0xFF) { /* write function address */ musbotg_set_address(sc, sc->sc_dv_addr); } musbotg_channel_free(sc, td); return (0); /* complete */ } static uint8_t musbotg_host_ctrl_status_rx(struct musbotg_td *td) { struct musbotg_softc *sc; uint8_t csr, csrh; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); if (td->channel == -1) td->channel = musbotg_channel_alloc(sc, td, 0); /* EP0 is busy, wait */ if (td->channel == -1) return (1); DPRINTFN(1, "ep_no=%d\n", td->channel); /* select endpoint 0 */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); if (!td->transaction_started) { MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), td->dev_addr); MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); /* RX NAK timeout */ MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); td->transaction_started = 1; /* Disable PING */ csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); csrh |= MUSB2_MASK_CSR0H_PING_DIS; MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); /* write command */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_STATUSPKT | MUSB2_MASK_CSR0L_REQPKT); return (1); /* Just started */ } csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr); if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) { MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_RXPKTRDY_CLR); musbotg_channel_free(sc, td); return (0); /* complete */ } if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT | MUSB2_MASK_CSR0L_REQPKT); MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); td->error = 1; } /* Failed */ if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { /* Clear status bit */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); td->error = 1; } if (td->error) { musbotg_channel_free(sc, td); return (0); } return (1); /* Not ready yet */ } static uint8_t musbotg_host_ctrl_status_tx(struct musbotg_td *td) { struct musbotg_softc *sc; uint8_t csr; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); if (td->channel == -1) td->channel = musbotg_channel_alloc(sc, td, 1); /* EP0 is busy, wait */ if (td->channel == -1) return (1); DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started, td->dev_addr,td->haddr,td->hport, td->transfer_type); /* select endpoint 0 */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); /* Not yet */ if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) return (1); /* Failed */ if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { /* Clear status bit */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); td->error = 1; musbotg_channel_free(sc, td); return (0); /* complete */ } if (td->transaction_started) { musbotg_channel_free(sc, td); return (0); /* complete */ } MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS); MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); /* TX NAK timeout */ MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); td->transaction_started = 1; /* write command */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_STATUSPKT | MUSB2_MASK_CSR0L_TXPKTRDY); return (1); /* wait for interrupt */ } static uint8_t musbotg_dev_data_rx(struct musbotg_td *td) { struct usb_page_search buf_res; struct musbotg_softc *sc; uint16_t count; uint8_t csr; uint8_t to; uint8_t got_short; to = 8; /* don't loop forever! */ got_short = 0; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); if (td->channel == -1) td->channel = musbotg_channel_alloc(sc, td, 0); /* EP0 is busy, wait */ if (td->channel == -1) return (1); /* select endpoint */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); repeat: /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); /* clear overrun */ if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { /* make sure we don't clear "RXPKTRDY" */ MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXPKTRDY); } /* check status */ if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) return (1); /* not complete */ /* get the packet byte count */ count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); DPRINTFN(4, "count=0x%04x\n", count); /* * Check for short or invalid packet: */ if (count != td->max_frame_size) { if (count < td->max_frame_size) { /* we have a short packet */ td->short_pkt = 1; got_short = 1; } else { /* invalid USB packet */ td->error = 1; musbotg_channel_free(sc, td); return (0); /* we are complete */ } } /* verify the packet byte count */ if (count > td->remainder) { /* invalid USB packet */ td->error = 1; musbotg_channel_free(sc, td); return (0); /* we are complete */ } while (count > 0) { uint32_t temp; usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* check for unaligned memory address */ if (USB_P2U(buf_res.buffer) & 3) { temp = count & ~3; if (temp) { /* receive data 4 bytes at a time */ bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, temp / 4); } temp = count & 3; if (temp) { /* receive data 1 byte at a time */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), ((void *)&sc->sc_bounce_buf[count / 4]), temp); } usbd_copy_in(td->pc, td->offset, sc->sc_bounce_buf, count); /* update offset and remainder */ td->offset += count; td->remainder -= count; break; } /* check if we can optimise */ if (buf_res.length >= 4) { /* receive data 4 bytes at a time */ bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, buf_res.length / 4); temp = buf_res.length & ~3; /* update counters */ count -= temp; td->offset += temp; td->remainder -= temp; continue; } /* receive data */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* clear status bits */ MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); /* check if we are complete */ if ((td->remainder == 0) || got_short) { if (td->short_pkt) { /* we are complete */ musbotg_channel_free(sc, td); return (0); } /* else need to receive a zero length packet */ } if (--to) { goto repeat; } return (1); /* not complete */ } static uint8_t musbotg_dev_data_tx(struct musbotg_td *td) { struct usb_page_search buf_res; struct musbotg_softc *sc; uint16_t count; uint8_t csr; uint8_t to; to = 8; /* don't loop forever! */ /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); if (td->channel == -1) td->channel = musbotg_channel_alloc(sc, td, 1); /* EP0 is busy, wait */ if (td->channel == -1) return (1); /* select endpoint */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); repeat: /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); if (csr & (MUSB2_MASK_CSRL_TXINCOMP | MUSB2_MASK_CSRL_TXUNDERRUN)) { /* clear status bits */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); } if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { return (1); /* not complete */ } /* check for short packet */ count = td->max_frame_size; if (td->remainder < count) { /* we have a short packet */ td->short_pkt = 1; count = td->remainder; } while (count > 0) { uint32_t temp; usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* check for unaligned memory address */ if (USB_P2U(buf_res.buffer) & 3) { usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buf, count); temp = count & ~3; if (temp) { /* transmit data 4 bytes at a time */ bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, temp / 4); } temp = count & 3; if (temp) { /* receive data 1 byte at a time */ bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), ((void *)&sc->sc_bounce_buf[count / 4]), temp); } /* update offset and remainder */ td->offset += count; td->remainder -= count; break; } /* check if we can optimise */ if (buf_res.length >= 4) { /* transmit data 4 bytes at a time */ bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, buf_res.length / 4); temp = buf_res.length & ~3; /* update counters */ count -= temp; td->offset += temp; td->remainder -= temp; continue; } /* transmit data */ bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* Max packet size */ MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); /* write command */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); /* check remainder */ if (td->remainder == 0) { if (td->short_pkt) { musbotg_channel_free(sc, td); return (0); /* complete */ } /* else we need to transmit a short packet */ } if (--to) { goto repeat; } return (1); /* not complete */ } static uint8_t musbotg_host_data_rx(struct musbotg_td *td) { struct usb_page_search buf_res; struct musbotg_softc *sc; uint16_t count; uint8_t csr, csrh; uint8_t to; uint8_t got_short; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); if (td->channel == -1) td->channel = musbotg_channel_alloc(sc, td, 0); /* No free EPs */ if (td->channel == -1) return (1); DPRINTFN(1, "ep_no=%d\n", td->channel); to = 8; /* don't loop forever! */ got_short = 0; /* select endpoint */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); repeat: /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); if (!td->transaction_started) { /* Function address */ MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel), td->dev_addr); /* SPLIT transaction */ MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel), td->haddr); MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel), td->hport); /* RX NAK timeout */ if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0); else MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); /* Protocol, speed, device endpoint */ MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); /* Max packet size */ MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet); /* Data Toggle */ csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); DPRINTFN(4, "csrh=0x%02x\n", csrh); csrh |= MUSB2_MASK_CSRH_RXDT_WREN; if (td->toggle) csrh |= MUSB2_MASK_CSRH_RXDT_VAL; else csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL; /* Set data toggle */ MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); /* write command */ MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); td->transaction_started = 1; return (1); } /* clear NAK timeout */ if (csr & MUSB2_MASK_CSRL_RXNAKTO) { DPRINTFN(4, "NAK Timeout\n"); if (csr & MUSB2_MASK_CSRL_RXREQPKT) { csr &= ~MUSB2_MASK_CSRL_RXREQPKT; MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); csr &= ~MUSB2_MASK_CSRL_RXNAKTO; MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); } td->error = 1; } if (csr & MUSB2_MASK_CSRL_RXERROR) { DPRINTFN(4, "RXERROR\n"); td->error = 1; } if (csr & MUSB2_MASK_CSRL_RXSTALL) { DPRINTFN(4, "RXSTALL\n"); td->error = 1; } if (td->error) { musbotg_channel_free(sc, td); return (0); /* we are complete */ } if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { /* No data available yet */ return (1); } td->toggle ^= 1; /* get the packet byte count */ count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); DPRINTFN(4, "count=0x%04x\n", count); /* * Check for short or invalid packet: */ if (count != td->max_frame_size) { if (count < td->max_frame_size) { /* we have a short packet */ td->short_pkt = 1; got_short = 1; } else { /* invalid USB packet */ td->error = 1; musbotg_channel_free(sc, td); return (0); /* we are complete */ } } /* verify the packet byte count */ if (count > td->remainder) { /* invalid USB packet */ td->error = 1; musbotg_channel_free(sc, td); return (0); /* we are complete */ } while (count > 0) { uint32_t temp; usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* check for unaligned memory address */ if (USB_P2U(buf_res.buffer) & 3) { temp = count & ~3; if (temp) { /* receive data 4 bytes at a time */ bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, temp / 4); } temp = count & 3; if (temp) { /* receive data 1 byte at a time */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), ((void *)&sc->sc_bounce_buf[count / 4]), temp); } usbd_copy_in(td->pc, td->offset, sc->sc_bounce_buf, count); /* update offset and remainder */ td->offset += count; td->remainder -= count; break; } /* check if we can optimise */ if (buf_res.length >= 4) { /* receive data 4 bytes at a time */ bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, buf_res.length / 4); temp = buf_res.length & ~3; /* update counters */ count -= temp; td->offset += temp; td->remainder -= temp; continue; } /* receive data */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* clear status bits */ MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); /* check if we are complete */ if ((td->remainder == 0) || got_short) { if (td->short_pkt) { /* we are complete */ musbotg_channel_free(sc, td); return (0); } /* else need to receive a zero length packet */ } /* Reset transaction state and restart */ td->transaction_started = 0; if (--to) goto repeat; return (1); /* not complete */ } static uint8_t musbotg_host_data_tx(struct musbotg_td *td) { struct usb_page_search buf_res; struct musbotg_softc *sc; uint16_t count; uint8_t csr, csrh; /* get pointer to softc */ sc = MUSBOTG_PC2SC(td->pc); if (td->channel == -1) td->channel = musbotg_channel_alloc(sc, td, 1); /* No free EPs */ if (td->channel == -1) return (1); DPRINTFN(1, "ep_no=%d\n", td->channel); /* select endpoint */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); /* read out FIFO status */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); DPRINTFN(4, "csr=0x%02x\n", csr); if (csr & (MUSB2_MASK_CSRL_TXSTALLED | MUSB2_MASK_CSRL_TXERROR)) { /* clear status bits */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); td->error = 1; musbotg_channel_free(sc, td); return (0); /* complete */ } if (csr & MUSB2_MASK_CSRL_TXNAKTO) { /* * Flush TX FIFO before clearing NAK TO */ if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { csr |= MUSB2_MASK_CSRL_TXFFLUSH; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { csr |= MUSB2_MASK_CSRL_TXFFLUSH; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); } } csr &= ~MUSB2_MASK_CSRL_TXNAKTO; MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); td->error = 1; musbotg_channel_free(sc, td); return (0); /* complete */ } /* * Wait while FIFO is empty. * Do not flush it because it will cause transactions * with size more then packet size. It might upset * some devices */ if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) return (1); /* Packet still being processed */ if (csr & MUSB2_MASK_CSRL_TXPKTRDY) return (1); if (td->transaction_started) { /* check remainder */ if (td->remainder == 0) { if (td->short_pkt) { musbotg_channel_free(sc, td); return (0); /* complete */ } /* else we need to transmit a short packet */ } /* We're not complete - more transactions required */ td->transaction_started = 0; } /* check for short packet */ count = td->max_frame_size; if (td->remainder < count) { /* we have a short packet */ td->short_pkt = 1; count = td->remainder; } while (count > 0) { uint32_t temp; usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* check for unaligned memory address */ if (USB_P2U(buf_res.buffer) & 3) { usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buf, count); temp = count & ~3; if (temp) { /* transmit data 4 bytes at a time */ bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, temp / 4); } temp = count & 3; if (temp) { /* receive data 1 byte at a time */ bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), ((void *)&sc->sc_bounce_buf[count / 4]), temp); } /* update offset and remainder */ td->offset += count; td->remainder -= count; break; } /* check if we can optimise */ if (buf_res.length >= 4) { /* transmit data 4 bytes at a time */ bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, buf_res.length / 4); temp = buf_res.length & ~3; /* update counters */ count -= temp; td->offset += temp; td->remainder -= temp; continue; } /* transmit data */ bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* Function address */ MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel), td->dev_addr); /* SPLIT transaction */ MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel), td->haddr); MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel), td->hport); /* TX NAK timeout */ if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0); else MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); /* Protocol, speed, device endpoint */ MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); /* Max packet size */ MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); if (!td->transaction_started) { csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); DPRINTFN(4, "csrh=0x%02x\n", csrh); csrh |= MUSB2_MASK_CSRH_TXDT_WREN; if (td->toggle) csrh |= MUSB2_MASK_CSRH_TXDT_VAL; else csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL; /* Set data toggle */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); } /* write command */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); /* Update Data Toggle */ td->toggle ^= 1; td->transaction_started = 1; return (1); /* not complete */ } static uint8_t musbotg_xfer_do_fifo(struct usb_xfer *xfer) { struct musbotg_softc *sc; struct musbotg_td *td; DPRINTFN(8, "\n"); sc = MUSBOTG_BUS2SC(xfer->xroot->bus); td = xfer->td_transfer_cache; while (1) { if ((td->func) (td)) { /* operation in progress */ break; } if (((void *)td) == xfer->td_transfer_last) { goto done; } if (td->error) { goto done; } else if (td->remainder > 0) { /* * We had a short transfer. If there is no alternate * next, stop processing ! */ if (!td->alt_next) { goto done; } } /* * Fetch the next transfer descriptor and transfer * some flags to the next transfer descriptor */ td = td->obj_next; xfer->td_transfer_cache = td; } return (1); /* not complete */ done: /* compute all actual lengths */ musbotg_standard_done(xfer); return (0); /* complete */ } static void musbotg_interrupt_poll(struct musbotg_softc *sc) { struct usb_xfer *xfer; repeat: TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { if (!musbotg_xfer_do_fifo(xfer)) { /* queue has been modified */ goto repeat; } } } void musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) { DPRINTFN(4, "vbus = %u\n", is_on); USB_BUS_LOCK(&sc->sc_bus); if (is_on) { if (!sc->sc_flags.status_vbus) { sc->sc_flags.status_vbus = 1; /* complete root HUB interrupt endpoint */ musbotg_root_intr(sc); } } else { if (sc->sc_flags.status_vbus) { sc->sc_flags.status_vbus = 0; sc->sc_flags.status_bus_reset = 0; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; /* complete root HUB interrupt endpoint */ musbotg_root_intr(sc); } } USB_BUS_UNLOCK(&sc->sc_bus); } void musbotg_connect_interrupt(struct musbotg_softc *sc) { USB_BUS_LOCK(&sc->sc_bus); sc->sc_flags.change_connect = 1; /* complete root HUB interrupt endpoint */ musbotg_root_intr(sc); USB_BUS_UNLOCK(&sc->sc_bus); } void musbotg_interrupt(struct musbotg_softc *sc, uint16_t rxstat, uint16_t txstat, uint8_t stat) { uint16_t rx_status; uint16_t tx_status; uint8_t usb_status; uint8_t temp; uint8_t to = 2; USB_BUS_LOCK(&sc->sc_bus); repeat: /* read all interrupt registers */ usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); /* read all FIFO interrupts */ rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); rx_status |= rxstat; tx_status |= txstat; usb_status |= stat; /* Clear platform flags after first time */ rxstat = 0; txstat = 0; stat = 0; /* check for any bus state change interrupts */ if (usb_status & (MUSB2_MASK_IRESET | MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | MUSB2_MASK_ICONN | MUSB2_MASK_IDISC | MUSB2_MASK_IVBUSERR)) { DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); if (usb_status & MUSB2_MASK_IRESET) { /* set correct state */ sc->sc_flags.status_bus_reset = 1; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; /* determine line speed */ temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); if (temp & MUSB2_MASK_HSMODE) sc->sc_flags.status_high_speed = 1; else sc->sc_flags.status_high_speed = 0; /* * After reset all interrupts are on and we need to * turn them off! */ temp = MUSB2_MASK_IRESET; /* disable resume interrupt */ temp &= ~MUSB2_MASK_IRESUME; /* enable suspend interrupt */ temp |= MUSB2_MASK_ISUSP; MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); /* disable TX and RX interrupts */ MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); } /* * If RXRSM and RXSUSP is set at the same time we interpret * that like RESUME. Resume is set when there is at least 3 * milliseconds of inactivity on the USB BUS. */ if (usb_status & MUSB2_MASK_IRESUME) { if (sc->sc_flags.status_suspend) { sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 1; temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); /* disable resume interrupt */ temp &= ~MUSB2_MASK_IRESUME; /* enable suspend interrupt */ temp |= MUSB2_MASK_ISUSP; MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); } } else if (usb_status & MUSB2_MASK_ISUSP) { if (!sc->sc_flags.status_suspend) { sc->sc_flags.status_suspend = 1; sc->sc_flags.change_suspend = 1; temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); /* disable suspend interrupt */ temp &= ~MUSB2_MASK_ISUSP; /* enable resume interrupt */ temp |= MUSB2_MASK_IRESUME; MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); } } if (usb_status & (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) sc->sc_flags.change_connect = 1; /* * Host Mode: There is no IRESET so assume bus is * always in reset state once device is connected. */ if (sc->sc_mode == MUSB2_HOST_MODE) { /* check for VBUS error in USB host mode */ if (usb_status & MUSB2_MASK_IVBUSERR) { temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); temp |= MUSB2_MASK_SESS; MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); } if (usb_status & MUSB2_MASK_ICONN) sc->sc_flags.status_bus_reset = 1; if (usb_status & MUSB2_MASK_IDISC) sc->sc_flags.status_bus_reset = 0; } /* complete root HUB interrupt endpoint */ musbotg_root_intr(sc); } /* check for any endpoint interrupts */ if (rx_status || tx_status) { DPRINTFN(4, "real endpoint interrupt " "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); } /* poll one time regardless of FIFO status */ musbotg_interrupt_poll(sc); if (--to) goto repeat; USB_BUS_UNLOCK(&sc->sc_bus); } static void musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) { struct musbotg_td *td; /* get current Transfer Descriptor */ td = temp->td_next; temp->td = td; /* prepare for next TD */ temp->td_next = td->obj_next; /* fill out the Transfer Descriptor */ td->func = temp->func; td->pc = temp->pc; td->offset = temp->offset; td->remainder = temp->len; td->error = 0; td->transaction_started = 0; td->did_stall = temp->did_stall; td->short_pkt = temp->short_pkt; td->alt_next = temp->setup_alt_next; td->channel = temp->channel; td->dev_addr = temp->dev_addr; td->haddr = temp->haddr; td->hport = temp->hport; td->transfer_type = temp->transfer_type; } static void musbotg_setup_standard_chain(struct usb_xfer *xfer) { struct musbotg_std_temp temp; struct musbotg_softc *sc; struct musbotg_td *td; uint32_t x; uint8_t ep_no; uint8_t xfer_type; enum usb_dev_speed speed; int tx; int dev_addr; DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", xfer->address, UE_GET_ADDR(xfer->endpointno), xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); sc = MUSBOTG_BUS2SC(xfer->xroot->bus); ep_no = (xfer->endpointno & UE_ADDR); temp.max_frame_size = xfer->max_frame_size; td = xfer->td_start[0]; xfer->td_transfer_first = td; xfer->td_transfer_cache = td; /* setup temp */ dev_addr = xfer->address; xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; temp.pc = NULL; temp.td = NULL; temp.td_next = xfer->td_start[0]; temp.offset = 0; temp.setup_alt_next = xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr; temp.did_stall = !xfer->flags_int.control_stall; temp.channel = -1; temp.dev_addr = dev_addr; temp.haddr = xfer->xroot->udev->hs_hub_addr; temp.hport = xfer->xroot->udev->hs_port_no; if (xfer->flags_int.usb_mode == USB_MODE_HOST) { speed = usbd_get_speed(xfer->xroot->udev); switch (speed) { case USB_SPEED_LOW: temp.transfer_type = MUSB2_MASK_TI_SPEED_LO; break; case USB_SPEED_FULL: temp.transfer_type = MUSB2_MASK_TI_SPEED_FS; break; case USB_SPEED_HIGH: temp.transfer_type = MUSB2_MASK_TI_SPEED_HS; break; default: temp.transfer_type = 0; DPRINTFN(-1, "Invalid USB speed: %d\n", speed); break; } switch (xfer_type) { case UE_CONTROL: temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL; break; case UE_ISOCHRONOUS: temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC; break; case UE_BULK: temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK; break; case UE_INTERRUPT: temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR; break; default: DPRINTFN(-1, "Invalid USB transfer type: %d\n", xfer_type); break; } temp.transfer_type |= ep_no; td->toggle = xfer->endpoint->toggle_next; } /* check if we should prepend a setup message */ if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) temp.func = &musbotg_dev_ctrl_setup_rx; else temp.func = &musbotg_host_ctrl_setup_tx; temp.len = xfer->frlengths[0]; temp.pc = xfer->frbuffers + 0; temp.short_pkt = temp.len ? 1 : 0; musbotg_setup_standard_chain_sub(&temp); } x = 1; } else { x = 0; } tx = 0; if (x != xfer->nframes) { if (xfer->endpointno & UE_DIR_IN) tx = 1; if (xfer->flags_int.usb_mode == USB_MODE_HOST) { tx = !tx; if (tx) { if (xfer->flags_int.control_xfr) temp.func = &musbotg_host_ctrl_data_tx; else temp.func = &musbotg_host_data_tx; } else { if (xfer->flags_int.control_xfr) temp.func = &musbotg_host_ctrl_data_rx; else temp.func = &musbotg_host_data_rx; } } else { if (tx) { if (xfer->flags_int.control_xfr) temp.func = &musbotg_dev_ctrl_data_tx; else temp.func = &musbotg_dev_data_tx; } else { if (xfer->flags_int.control_xfr) temp.func = &musbotg_dev_ctrl_data_rx; else temp.func = &musbotg_dev_data_rx; } } /* setup "pc" pointer */ temp.pc = xfer->frbuffers + x; } while (x != xfer->nframes) { /* DATA0 / DATA1 message */ temp.len = xfer->frlengths[x]; x++; if (x == xfer->nframes) { if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_act) { temp.setup_alt_next = 0; } } else { temp.setup_alt_next = 0; } } if (temp.len == 0) { /* make sure that we send an USB packet */ temp.short_pkt = 0; } else { if (xfer->flags_int.isochronous_xfr) { /* isochronous data transfer */ /* don't force short */ temp.short_pkt = 1; } else { /* regular data transfer */ temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); } } musbotg_setup_standard_chain_sub(&temp); if (xfer->flags_int.isochronous_xfr) { temp.offset += temp.len; } else { /* get next Page Cache pointer */ temp.pc = xfer->frbuffers + x; } } /* check for control transfer */ if (xfer->flags_int.control_xfr) { /* always setup a valid "pc" pointer for status and sync */ temp.pc = xfer->frbuffers + 0; temp.len = 0; temp.short_pkt = 0; temp.setup_alt_next = 0; /* check if we should append a status stage */ if (!xfer->flags_int.control_act) { /* * Send a DATA1 message and invert the current * endpoint direction. */ if (sc->sc_mode == MUSB2_DEVICE_MODE) temp.func = &musbotg_dev_ctrl_status; else { if (xfer->endpointno & UE_DIR_IN) temp.func = musbotg_host_ctrl_status_tx; else temp.func = musbotg_host_ctrl_status_rx; } musbotg_setup_standard_chain_sub(&temp); } } /* must have at least one frame! */ td = temp.td; xfer->td_transfer_last = td; } static void musbotg_timeout(void *arg) { struct usb_xfer *xfer = arg; DPRINTFN(1, "xfer=%p\n", xfer); USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); /* transfer is transferred */ musbotg_device_done(xfer, USB_ERR_TIMEOUT); } static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on) { uint16_t temp; /* * Only enable the endpoint interrupt when we are * actually waiting for data, hence we are dealing * with level triggered interrupts ! */ DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on); if (channel == -1) return; if (channel == 0) { temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); if (on) temp |= MUSB2_MASK_EPINT(0); else temp &= ~MUSB2_MASK_EPINT(0); MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); } else { temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); if (on) temp |= MUSB2_MASK_EPINT(channel); else temp &= ~MUSB2_MASK_EPINT(channel); MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); if (on) temp |= MUSB2_MASK_EPINT(channel); else temp &= ~MUSB2_MASK_EPINT(channel); MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); } if (sc->sc_ep_int_set) sc->sc_ep_int_set(sc, channel, on); } static void musbotg_start_standard_chain(struct usb_xfer *xfer) { DPRINTFN(8, "\n"); /* poll one time */ if (musbotg_xfer_do_fifo(xfer)) { DPRINTFN(14, "enabled interrupts on endpoint\n"); /* put transfer on interrupt queue */ usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); /* start timeout, if any */ if (xfer->timeout != 0) { usbd_transfer_timeout_ms(xfer, &musbotg_timeout, xfer->timeout); } } } static void musbotg_root_intr(struct musbotg_softc *sc) { DPRINTFN(8, "\n"); USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* set port bit */ sc->sc_hub_idata[0] = 0x02; /* we only have one port */ uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); } static usb_error_t musbotg_standard_done_sub(struct usb_xfer *xfer) { struct musbotg_td *td; uint32_t len; uint8_t error; DPRINTFN(8, "\n"); td = xfer->td_transfer_cache; do { len = td->remainder; xfer->endpoint->toggle_next = td->toggle; if (xfer->aframes != xfer->nframes) { /* * Verify the length and subtract * the remainder from "frlengths[]": */ if (len > xfer->frlengths[xfer->aframes]) { td->error = 1; } else { xfer->frlengths[xfer->aframes] -= len; } } /* Check for transfer error */ if (td->error) { /* the transfer is finished */ error = 1; td = NULL; break; } /* Check for short transfer */ if (len > 0) { if (xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr) { /* follow alt next */ if (td->alt_next) { td = td->obj_next; } else { td = NULL; } } else { /* the transfer is finished */ td = NULL; } error = 0; break; } td = td->obj_next; /* this USB frame is complete */ error = 0; break; } while (0); /* update transfer cache */ xfer->td_transfer_cache = td; return (error ? USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); } static void musbotg_standard_done(struct usb_xfer *xfer) { usb_error_t err = 0; DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", xfer, xfer->endpoint); /* reset scanner */ xfer->td_transfer_cache = xfer->td_transfer_first; if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { err = musbotg_standard_done_sub(xfer); } xfer->aframes = 1; if (xfer->td_transfer_cache == NULL) { goto done; } } while (xfer->aframes != xfer->nframes) { err = musbotg_standard_done_sub(xfer); xfer->aframes++; if (xfer->td_transfer_cache == NULL) { goto done; } } if (xfer->flags_int.control_xfr && !xfer->flags_int.control_act) { err = musbotg_standard_done_sub(xfer); } done: musbotg_device_done(xfer, err); } /*------------------------------------------------------------------------* * musbotg_device_done * * NOTE: this function can be called more than one time on the * same USB transfer! *------------------------------------------------------------------------*/ static void musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) { struct musbotg_td *td; struct musbotg_softc *sc; USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n", xfer, xfer->endpoint, error); DPRINTFN(14, "disabled interrupts on endpoint\n"); sc = MUSBOTG_BUS2SC(xfer->xroot->bus); td = xfer->td_transfer_cache; if (td && (td->channel != -1)) musbotg_channel_free(sc, td); /* dequeue transfer and start next transfer */ usbd_transfer_done(xfer, error); } static void musbotg_xfer_stall(struct usb_xfer *xfer) { musbotg_device_done(xfer, USB_ERR_STALLED); } static void musbotg_set_stall(struct usb_device *udev, struct usb_endpoint *ep, uint8_t *did_stall) { struct musbotg_softc *sc; uint8_t ep_no; USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); DPRINTFN(4, "endpoint=%p\n", ep); /* set FORCESTALL */ sc = MUSBOTG_BUS2SC(udev->bus); ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); /* select endpoint */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); if (ep->edesc->bEndpointAddress & UE_DIR_IN) { MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXSENDSTALL); } else { MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXSENDSTALL); } } static void musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) { uint16_t mps; uint16_t temp; uint8_t csr; if (ep_type == UE_CONTROL) { /* clearing stall is not needed */ return; } /* select endpoint */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); /* compute max frame size */ mps = wMaxPacket & 0x7FF; switch ((wMaxPacket >> 11) & 3) { case 1: mps *= 2; break; case 2: mps *= 3; break; default: break; } if (ep_dir == UE_DIR_IN) { temp = 0; /* Configure endpoint */ switch (ep_type) { case UE_INTERRUPT: MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, MUSB2_MASK_CSRH_TXMODE | temp); break; case UE_ISOCHRONOUS: MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, MUSB2_MASK_CSRH_TXMODE | MUSB2_MASK_CSRH_TXISO | temp); break; case UE_BULK: MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, MUSB2_MASK_CSRH_TXMODE | temp); break; default: break; } /* Need to flush twice in case of double bufring */ csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXFFLUSH); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXFFLUSH); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); } } /* reset data toggle */ MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXDT_CLR); MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); /* set double/single buffering */ temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); if (mps <= (sc->sc_hw_ep_profile[ep_no]. max_in_frame_size / 2)) { /* double buffer */ temp &= ~(1 << ep_no); } else { /* single buffer */ temp |= (1 << ep_no); } MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); /* clear sent stall */ if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); } } else { temp = 0; /* Configure endpoint */ switch (ep_type) { case UE_INTERRUPT: MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSRH_RXNYET | temp); break; case UE_ISOCHRONOUS: MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSRH_RXNYET | MUSB2_MASK_CSRH_RXISO | temp); break; case UE_BULK: MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); break; default: break; } /* Need to flush twice in case of double bufring */ csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXFFLUSH); csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXFFLUSH); csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); } } /* reset data toggle */ MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXDT_CLR); MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); /* set double/single buffering */ temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); if (mps <= (sc->sc_hw_ep_profile[ep_no]. max_out_frame_size / 2)) { /* double buffer */ temp &= ~(1 << ep_no); } else { /* single buffer */ temp |= (1 << ep_no); } MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); /* clear sent stall */ if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); } } } static void musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) { struct musbotg_softc *sc; struct usb_endpoint_descriptor *ed; DPRINTFN(4, "endpoint=%p\n", ep); USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); /* check mode */ if (udev->flags.usb_mode != USB_MODE_DEVICE) { /* not supported */ return; } /* get softc */ sc = MUSBOTG_BUS2SC(udev->bus); /* get endpoint descriptor */ ed = ep->edesc; /* reset endpoint */ musbotg_clear_stall_sub(sc, UGETW(ed->wMaxPacketSize), (ed->bEndpointAddress & UE_ADDR), (ed->bmAttributes & UE_XFERTYPE), (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); } usb_error_t musbotg_init(struct musbotg_softc *sc) { const struct musb_otg_ep_cfg *cfg; struct usb_hw_ep_profile *pf; int i; uint16_t offset; uint8_t nrx; uint8_t ntx; uint8_t temp; uint8_t fsize; uint8_t frx; uint8_t ftx; uint8_t dynfifo; DPRINTFN(1, "start\n"); /* set up the bus structure */ sc->sc_bus.usbrev = USB_REV_2_0; sc->sc_bus.methods = &musbotg_bus_methods; /* Set a default endpoint configuration */ if (sc->sc_ep_cfg == NULL) sc->sc_ep_cfg = musbotg_ep_default; USB_BUS_LOCK(&sc->sc_bus); /* turn on clocks */ if (sc->sc_clocks_on) { (sc->sc_clocks_on) (sc->sc_clocks_arg); } /* wait a little for things to stabilise */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); /* disable all interrupts */ temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); DPRINTF("pre-DEVCTL=0x%02x\n", temp); MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); /* disable pullup */ musbotg_pull_common(sc, 0); /* wait a little bit (10ms) */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); /* disable double packet buffering */ MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); /* enable HighSpeed and ISO Update flags */ MUSB2_WRITE_1(sc, MUSB2_REG_POWER, MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); if (sc->sc_mode == MUSB2_DEVICE_MODE) { /* clear Session bit, if set */ temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); temp &= ~MUSB2_MASK_SESS; MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); } else { /* Enter session for Host mode */ temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); temp |= MUSB2_MASK_SESS; MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); } /* wait a little for things to stabilise */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); DPRINTF("DEVCTL=0x%02x\n", temp); /* disable testmode */ MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); /* set default value */ MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); /* select endpoint index 0 */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); if (sc->sc_ep_max == 0) { /* read out number of endpoints */ nrx = (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); ntx = (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; } else { nrx = ntx = sc->sc_ep_max; } /* these numbers exclude the control endpoint */ DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); if (sc->sc_ep_max == 0) { DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); } /* read out configuration data */ sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); DPRINTFN(2, "Config Data: 0x%02x\n", sc->sc_conf_data); dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; if (dynfifo) { device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " "assuming 16Kbytes of FIFO RAM\n"); } DPRINTFN(2, "HW version: 0x%04x\n", MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); /* initialise endpoint profiles */ offset = 0; for (temp = 1; temp <= sc->sc_ep_max; temp++) { pf = sc->sc_hw_ep_profile + temp; /* select endpoint */ MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; ftx = (fsize & MUSB2_MASK_TX_FSIZE); DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", temp, ftx, frx, dynfifo); if (dynfifo) { if (frx && (temp <= nrx)) { for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) { cfg = &sc->sc_ep_cfg[i]; if (temp <= cfg->ep_end) { frx = cfg->ep_fifosz_shift; MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, cfg->ep_fifosz_reg); break; } } MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, offset >> 3); offset += (1 << frx); } if (ftx && (temp <= ntx)) { for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) { cfg = &sc->sc_ep_cfg[i]; if (temp <= cfg->ep_end) { ftx = cfg->ep_fifosz_shift; MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, cfg->ep_fifosz_reg); break; } } MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, offset >> 3); offset += (1 << ftx); } } if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { pf->max_in_frame_size = 1 << ftx; pf->max_out_frame_size = 1 << frx; pf->is_simplex = 0; /* duplex */ pf->support_multi_buffer = 1; pf->support_bulk = 1; pf->support_interrupt = 1; pf->support_isochronous = 1; pf->support_in = 1; pf->support_out = 1; } else if (frx && (temp <= nrx)) { pf->max_out_frame_size = 1 << frx; pf->max_in_frame_size = 0; pf->is_simplex = 1; /* simplex */ pf->support_multi_buffer = 1; pf->support_bulk = 1; pf->support_interrupt = 1; pf->support_isochronous = 1; pf->support_out = 1; } else if (ftx && (temp <= ntx)) { pf->max_in_frame_size = 1 << ftx; pf->max_out_frame_size = 0; pf->is_simplex = 1; /* simplex */ pf->support_multi_buffer = 1; pf->support_bulk = 1; pf->support_interrupt = 1; pf->support_isochronous = 1; pf->support_in = 1; } } DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); /* turn on default interrupts */ if (sc->sc_mode == MUSB2_HOST_MODE) MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff); else MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); musbotg_clocks_off(sc); USB_BUS_UNLOCK(&sc->sc_bus); /* catch any lost interrupts */ musbotg_do_poll(&sc->sc_bus); return (0); /* success */ } void musbotg_uninit(struct musbotg_softc *sc) { USB_BUS_LOCK(&sc->sc_bus); /* disable all interrupts */ MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); sc->sc_flags.port_powered = 0; sc->sc_flags.status_vbus = 0; sc->sc_flags.status_bus_reset = 0; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; musbotg_pull_down(sc); musbotg_clocks_off(sc); USB_BUS_UNLOCK(&sc->sc_bus); } static void musbotg_do_poll(struct usb_bus *bus) { struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); USB_BUS_LOCK(&sc->sc_bus); musbotg_interrupt_poll(sc); USB_BUS_UNLOCK(&sc->sc_bus); } /*------------------------------------------------------------------------* * musbotg bulk support *------------------------------------------------------------------------*/ static void musbotg_device_bulk_open(struct usb_xfer *xfer) { return; } static void musbotg_device_bulk_close(struct usb_xfer *xfer) { musbotg_device_done(xfer, USB_ERR_CANCELLED); } static void musbotg_device_bulk_enter(struct usb_xfer *xfer) { return; } static void musbotg_device_bulk_start(struct usb_xfer *xfer) { /* setup TDs */ musbotg_setup_standard_chain(xfer); musbotg_start_standard_chain(xfer); } static const struct usb_pipe_methods musbotg_device_bulk_methods = { .open = musbotg_device_bulk_open, .close = musbotg_device_bulk_close, .enter = musbotg_device_bulk_enter, .start = musbotg_device_bulk_start, }; /*------------------------------------------------------------------------* * musbotg control support *------------------------------------------------------------------------*/ static void musbotg_device_ctrl_open(struct usb_xfer *xfer) { return; } static void musbotg_device_ctrl_close(struct usb_xfer *xfer) { musbotg_device_done(xfer, USB_ERR_CANCELLED); } static void musbotg_device_ctrl_enter(struct usb_xfer *xfer) { return; } static void musbotg_device_ctrl_start(struct usb_xfer *xfer) { /* setup TDs */ musbotg_setup_standard_chain(xfer); musbotg_start_standard_chain(xfer); } static const struct usb_pipe_methods musbotg_device_ctrl_methods = { .open = musbotg_device_ctrl_open, .close = musbotg_device_ctrl_close, .enter = musbotg_device_ctrl_enter, .start = musbotg_device_ctrl_start, }; /*------------------------------------------------------------------------* * musbotg interrupt support *------------------------------------------------------------------------*/ static void musbotg_device_intr_open(struct usb_xfer *xfer) { return; } static void musbotg_device_intr_close(struct usb_xfer *xfer) { musbotg_device_done(xfer, USB_ERR_CANCELLED); } static void musbotg_device_intr_enter(struct usb_xfer *xfer) { return; } static void musbotg_device_intr_start(struct usb_xfer *xfer) { /* setup TDs */ musbotg_setup_standard_chain(xfer); musbotg_start_standard_chain(xfer); } static const struct usb_pipe_methods musbotg_device_intr_methods = { .open = musbotg_device_intr_open, .close = musbotg_device_intr_close, .enter = musbotg_device_intr_enter, .start = musbotg_device_intr_start, }; /*------------------------------------------------------------------------* * musbotg full speed isochronous support *------------------------------------------------------------------------*/ static void musbotg_device_isoc_open(struct usb_xfer *xfer) { return; } static void musbotg_device_isoc_close(struct usb_xfer *xfer) { musbotg_device_done(xfer, USB_ERR_CANCELLED); } static void musbotg_device_isoc_enter(struct usb_xfer *xfer) { struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); uint32_t nframes; DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", xfer, xfer->endpoint->isoc_next, xfer->nframes); /* get the current frame index */ nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); if (usbd_xfer_get_isochronous_start_frame( xfer, nframes, 0, 1, MUSB2_MASK_FRAME, NULL)) DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); /* setup TDs */ musbotg_setup_standard_chain(xfer); } static void musbotg_device_isoc_start(struct usb_xfer *xfer) { /* start TD chain */ musbotg_start_standard_chain(xfer); } static const struct usb_pipe_methods musbotg_device_isoc_methods = { .open = musbotg_device_isoc_open, .close = musbotg_device_isoc_close, .enter = musbotg_device_isoc_enter, .start = musbotg_device_isoc_start, }; /*------------------------------------------------------------------------* * musbotg root control support *------------------------------------------------------------------------* * Simulate a hardware HUB by handling all the necessary requests. *------------------------------------------------------------------------*/ static const struct usb_device_descriptor musbotg_devd = { .bLength = sizeof(struct usb_device_descriptor), .bDescriptorType = UDESC_DEVICE, .bcdUSB = {0x00, 0x02}, .bDeviceClass = UDCLASS_HUB, .bDeviceSubClass = UDSUBCLASS_HUB, .bDeviceProtocol = UDPROTO_HSHUBSTT, .bMaxPacketSize = 64, .bcdDevice = {0x00, 0x01}, .iManufacturer = 1, .iProduct = 2, .bNumConfigurations = 1, }; static const struct usb_device_qualifier musbotg_odevd = { .bLength = sizeof(struct usb_device_qualifier), .bDescriptorType = UDESC_DEVICE_QUALIFIER, .bcdUSB = {0x00, 0x02}, .bDeviceClass = UDCLASS_HUB, .bDeviceSubClass = UDSUBCLASS_HUB, .bDeviceProtocol = UDPROTO_FSHUB, .bMaxPacketSize0 = 0, .bNumConfigurations = 0, }; static const struct musbotg_config_desc musbotg_confd = { .confd = { .bLength = sizeof(struct usb_config_descriptor), .bDescriptorType = UDESC_CONFIG, .wTotalLength[0] = sizeof(musbotg_confd), .bNumInterface = 1, .bConfigurationValue = 1, .iConfiguration = 0, .bmAttributes = UC_SELF_POWERED, .bMaxPower = 0, }, .ifcd = { .bLength = sizeof(struct usb_interface_descriptor), .bDescriptorType = UDESC_INTERFACE, .bNumEndpoints = 1, .bInterfaceClass = UICLASS_HUB, .bInterfaceSubClass = UISUBCLASS_HUB, .bInterfaceProtocol = 0, }, .endpd = { .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = UDESC_ENDPOINT, .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), .bmAttributes = UE_INTERRUPT, .wMaxPacketSize[0] = 8, .bInterval = 255, }, }; #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } static const struct usb_hub_descriptor_min musbotg_hubd = { .bDescLength = sizeof(musbotg_hubd), .bDescriptorType = UDESC_HUB, .bNbrPorts = 1, HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), .bPwrOn2PwrGood = 50, .bHubContrCurrent = 0, .DeviceRemovable = {0}, /* port is removable */ }; #define STRING_VENDOR \ "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s" #define STRING_PRODUCT \ "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); static usb_error_t musbotg_roothub_exec(struct usb_device *udev, struct usb_device_request *req, const void **pptr, uint16_t *plength) { struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); const void *ptr; uint16_t len; uint16_t value; uint16_t index; uint8_t reg; usb_error_t err; USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* buffer reset */ ptr = (const void *)&sc->sc_hub_temp; len = 0; err = 0; value = UGETW(req->wValue); index = UGETW(req->wIndex); /* demultiplex the control request */ switch (req->bmRequestType) { case UT_READ_DEVICE: switch (req->bRequest) { case UR_GET_DESCRIPTOR: goto tr_handle_get_descriptor; case UR_GET_CONFIG: goto tr_handle_get_config; case UR_GET_STATUS: goto tr_handle_get_status; default: goto tr_stalled; } break; case UT_WRITE_DEVICE: switch (req->bRequest) { case UR_SET_ADDRESS: goto tr_handle_set_address; case UR_SET_CONFIG: goto tr_handle_set_config; case UR_CLEAR_FEATURE: goto tr_valid; /* nop */ case UR_SET_DESCRIPTOR: goto tr_valid; /* nop */ case UR_SET_FEATURE: default: goto tr_stalled; } break; case UT_WRITE_ENDPOINT: switch (req->bRequest) { case UR_CLEAR_FEATURE: switch (UGETW(req->wValue)) { case UF_ENDPOINT_HALT: goto tr_handle_clear_halt; case UF_DEVICE_REMOTE_WAKEUP: goto tr_handle_clear_wakeup; default: goto tr_stalled; } break; case UR_SET_FEATURE: switch (UGETW(req->wValue)) { case UF_ENDPOINT_HALT: goto tr_handle_set_halt; case UF_DEVICE_REMOTE_WAKEUP: goto tr_handle_set_wakeup; default: goto tr_stalled; } break; case UR_SYNCH_FRAME: goto tr_valid; /* nop */ default: goto tr_stalled; } break; case UT_READ_ENDPOINT: switch (req->bRequest) { case UR_GET_STATUS: goto tr_handle_get_ep_status; default: goto tr_stalled; } break; case UT_WRITE_INTERFACE: switch (req->bRequest) { case UR_SET_INTERFACE: goto tr_handle_set_interface; case UR_CLEAR_FEATURE: goto tr_valid; /* nop */ case UR_SET_FEATURE: default: goto tr_stalled; } break; case UT_READ_INTERFACE: switch (req->bRequest) { case UR_GET_INTERFACE: goto tr_handle_get_interface; case UR_GET_STATUS: goto tr_handle_get_iface_status; default: goto tr_stalled; } break; case UT_WRITE_CLASS_INTERFACE: case UT_WRITE_VENDOR_INTERFACE: /* XXX forward */ break; case UT_READ_CLASS_INTERFACE: case UT_READ_VENDOR_INTERFACE: /* XXX forward */ break; case UT_WRITE_CLASS_DEVICE: switch (req->bRequest) { case UR_CLEAR_FEATURE: goto tr_valid; case UR_SET_DESCRIPTOR: case UR_SET_FEATURE: break; default: goto tr_stalled; } break; case UT_WRITE_CLASS_OTHER: switch (req->bRequest) { case UR_CLEAR_FEATURE: goto tr_handle_clear_port_feature; case UR_SET_FEATURE: goto tr_handle_set_port_feature; case UR_CLEAR_TT_BUFFER: case UR_RESET_TT: case UR_STOP_TT: goto tr_valid; default: goto tr_stalled; } break; case UT_READ_CLASS_OTHER: switch (req->bRequest) { case UR_GET_TT_STATE: goto tr_handle_get_tt_state; case UR_GET_STATUS: goto tr_handle_get_port_status; default: goto tr_stalled; } break; case UT_READ_CLASS_DEVICE: switch (req->bRequest) { case UR_GET_DESCRIPTOR: goto tr_handle_get_class_descriptor; case UR_GET_STATUS: goto tr_handle_get_class_status; default: goto tr_stalled; } break; default: goto tr_stalled; } goto tr_valid; tr_handle_get_descriptor: switch (value >> 8) { case UDESC_DEVICE: if (value & 0xff) { goto tr_stalled; } len = sizeof(musbotg_devd); ptr = (const void *)&musbotg_devd; goto tr_valid; case UDESC_DEVICE_QUALIFIER: if (value & 0xff) { goto tr_stalled; } len = sizeof(musbotg_odevd); ptr = (const void *)&musbotg_odevd; goto tr_valid; case UDESC_CONFIG: if (value & 0xff) { goto tr_stalled; } len = sizeof(musbotg_confd); ptr = (const void *)&musbotg_confd; goto tr_valid; case UDESC_STRING: switch (value & 0xff) { case 0: /* Language table */ len = sizeof(usb_string_lang_en); ptr = (const void *)&usb_string_lang_en; goto tr_valid; case 1: /* Vendor */ len = sizeof(musbotg_vendor); ptr = (const void *)&musbotg_vendor; goto tr_valid; case 2: /* Product */ len = sizeof(musbotg_product); ptr = (const void *)&musbotg_product; goto tr_valid; default: break; } break; default: goto tr_stalled; } goto tr_stalled; tr_handle_get_config: len = 1; sc->sc_hub_temp.wValue[0] = sc->sc_conf; goto tr_valid; tr_handle_get_status: len = 2; USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); goto tr_valid; tr_handle_set_address: if (value & 0xFF00) { goto tr_stalled; } sc->sc_rt_addr = value; goto tr_valid; tr_handle_set_config: if (value >= 2) { goto tr_stalled; } sc->sc_conf = value; goto tr_valid; tr_handle_get_interface: len = 1; sc->sc_hub_temp.wValue[0] = 0; goto tr_valid; tr_handle_get_tt_state: tr_handle_get_class_status: tr_handle_get_iface_status: tr_handle_get_ep_status: len = 2; USETW(sc->sc_hub_temp.wValue, 0); goto tr_valid; tr_handle_set_halt: tr_handle_set_interface: tr_handle_set_wakeup: tr_handle_clear_wakeup: tr_handle_clear_halt: goto tr_valid; tr_handle_clear_port_feature: if (index != 1) { goto tr_stalled; } DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); switch (value) { case UHF_PORT_SUSPEND: if (sc->sc_mode == MUSB2_HOST_MODE) musbotg_wakeup_host(sc); else musbotg_wakeup_peer(sc); break; case UHF_PORT_ENABLE: sc->sc_flags.port_enabled = 0; break; case UHF_C_PORT_ENABLE: sc->sc_flags.change_enabled = 0; break; case UHF_C_PORT_OVER_CURRENT: sc->sc_flags.change_over_current = 0; break; case UHF_C_PORT_RESET: sc->sc_flags.change_reset = 0; break; case UHF_PORT_TEST: case UHF_PORT_INDICATOR: /* nops */ break; case UHF_PORT_POWER: sc->sc_flags.port_powered = 0; musbotg_pull_down(sc); musbotg_clocks_off(sc); break; case UHF_C_PORT_CONNECTION: sc->sc_flags.change_connect = 0; break; case UHF_C_PORT_SUSPEND: sc->sc_flags.change_suspend = 0; break; default: err = USB_ERR_IOERROR; goto done; } goto tr_valid; tr_handle_set_port_feature: if (index != 1) { goto tr_stalled; } DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); switch (value) { case UHF_PORT_ENABLE: sc->sc_flags.port_enabled = 1; break; case UHF_PORT_SUSPEND: if (sc->sc_mode == MUSB2_HOST_MODE) musbotg_suspend_host(sc); break; case UHF_PORT_RESET: if (sc->sc_mode == MUSB2_HOST_MODE) { reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); reg |= MUSB2_MASK_RESET; MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); /* Wait for 20 msec */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5); reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); reg &= ~MUSB2_MASK_RESET; MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); /* determine line speed */ reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); if (reg & MUSB2_MASK_HSMODE) sc->sc_flags.status_high_speed = 1; else sc->sc_flags.status_high_speed = 0; sc->sc_flags.change_reset = 1; } else err = USB_ERR_IOERROR; break; case UHF_PORT_TEST: case UHF_PORT_INDICATOR: /* nops */ break; case UHF_PORT_POWER: sc->sc_flags.port_powered = 1; break; default: err = USB_ERR_IOERROR; goto done; } goto tr_valid; tr_handle_get_port_status: DPRINTFN(8, "UR_GET_PORT_STATUS\n"); if (index != 1) { goto tr_stalled; } if (sc->sc_flags.status_vbus) { musbotg_clocks_on(sc); musbotg_pull_up(sc); } else { musbotg_pull_down(sc); musbotg_clocks_off(sc); } /* Select Device Side Mode */ if (sc->sc_mode == MUSB2_DEVICE_MODE) value = UPS_PORT_MODE_DEVICE; else value = 0; if (sc->sc_flags.status_high_speed) { value |= UPS_HIGH_SPEED; } if (sc->sc_flags.port_powered) { value |= UPS_PORT_POWER; } if (sc->sc_flags.port_enabled) { value |= UPS_PORT_ENABLED; } if (sc->sc_flags.port_over_current) value |= UPS_OVERCURRENT_INDICATOR; if (sc->sc_flags.status_vbus && sc->sc_flags.status_bus_reset) { value |= UPS_CURRENT_CONNECT_STATUS; } if (sc->sc_flags.status_suspend) { value |= UPS_SUSPEND; } USETW(sc->sc_hub_temp.ps.wPortStatus, value); value = 0; if (sc->sc_flags.change_connect) { value |= UPS_C_CONNECT_STATUS; if (sc->sc_mode == MUSB2_DEVICE_MODE) { if (sc->sc_flags.status_vbus && sc->sc_flags.status_bus_reset) { /* reset EP0 state */ sc->sc_ep0_busy = 0; sc->sc_ep0_cmd = 0; } } } if (sc->sc_flags.change_suspend) value |= UPS_C_SUSPEND; if (sc->sc_flags.change_reset) value |= UPS_C_PORT_RESET; if (sc->sc_flags.change_over_current) value |= UPS_C_OVERCURRENT_INDICATOR; USETW(sc->sc_hub_temp.ps.wPortChange, value); len = sizeof(sc->sc_hub_temp.ps); goto tr_valid; tr_handle_get_class_descriptor: if (value & 0xFF) { goto tr_stalled; } ptr = (const void *)&musbotg_hubd; len = sizeof(musbotg_hubd); goto tr_valid; tr_stalled: err = USB_ERR_STALLED; tr_valid: done: *plength = len; *pptr = ptr; return (err); } static void musbotg_xfer_setup(struct usb_setup_params *parm) { struct musbotg_softc *sc; struct usb_xfer *xfer; void *last_obj; uint32_t ntd; uint32_t n; uint8_t ep_no; sc = MUSBOTG_BUS2SC(parm->udev->bus); xfer = parm->curr_xfer; /* * NOTE: This driver does not use any of the parameters that * are computed from the following values. Just set some * reasonable dummies: */ parm->hc_max_packet_size = 0x400; parm->hc_max_frame_size = 0xc00; if ((parm->methods == &musbotg_device_isoc_methods) || (parm->methods == &musbotg_device_intr_methods)) parm->hc_max_packet_count = 3; else parm->hc_max_packet_count = 1; usbd_transfer_setup_sub(parm); /* * compute maximum number of TDs */ if (parm->methods == &musbotg_device_ctrl_methods) { ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; } else if (parm->methods == &musbotg_device_bulk_methods) { ntd = xfer->nframes + 1 /* SYNC */ ; } else if (parm->methods == &musbotg_device_intr_methods) { ntd = xfer->nframes + 1 /* SYNC */ ; } else if (parm->methods == &musbotg_device_isoc_methods) { ntd = xfer->nframes + 1 /* SYNC */ ; } else { ntd = 0; } /* * check if "usbd_transfer_setup_sub" set an error */ if (parm->err) { return; } /* * allocate transfer descriptors */ last_obj = NULL; ep_no = xfer->endpointno & UE_ADDR; /* * Check for a valid endpoint profile in USB device mode: */ if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { const struct usb_hw_ep_profile *pf; musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); if (pf == NULL) { /* should not happen */ parm->err = USB_ERR_INVAL; return; } } /* align data */ parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); for (n = 0; n != ntd; n++) { struct musbotg_td *td; if (parm->buf) { td = USB_ADD_BYTES(parm->buf, parm->size[0]); /* init TD */ td->max_frame_size = xfer->max_frame_size; td->reg_max_packet = xfer->max_packet_size | ((xfer->max_packet_count - 1) << 11); td->ep_no = ep_no; td->obj_next = last_obj; last_obj = td; } parm->size[0] += sizeof(*td); } xfer->td_start[0] = last_obj; } static void musbotg_xfer_unsetup(struct usb_xfer *xfer) { return; } static void musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus) { struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); if (sc->sc_mode == MUSB2_HOST_MODE) *pus = 2000; /* microseconds */ else *pus = 0; } static void musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, struct usb_endpoint *ep) { struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode, sc->sc_rt_addr); if (udev->device_index != sc->sc_rt_addr) { switch (edesc->bmAttributes & UE_XFERTYPE) { case UE_CONTROL: ep->methods = &musbotg_device_ctrl_methods; break; case UE_INTERRUPT: ep->methods = &musbotg_device_intr_methods; break; case UE_ISOCHRONOUS: ep->methods = &musbotg_device_isoc_methods; break; case UE_BULK: ep->methods = &musbotg_device_bulk_methods; break; default: /* do nothing */ break; } } } static void musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) { struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); switch (state) { case USB_HW_POWER_SUSPEND: musbotg_uninit(sc); break; case USB_HW_POWER_SHUTDOWN: musbotg_uninit(sc); break; case USB_HW_POWER_RESUME: musbotg_init(sc); break; default: break; } } static const struct usb_bus_methods musbotg_bus_methods = { .endpoint_init = &musbotg_ep_init, .get_dma_delay = &musbotg_get_dma_delay, .xfer_setup = &musbotg_xfer_setup, .xfer_unsetup = &musbotg_xfer_unsetup, .get_hw_ep_profile = &musbotg_get_hw_ep_profile, .xfer_stall = &musbotg_xfer_stall, .set_stall = &musbotg_set_stall, .clear_stall = &musbotg_clear_stall, .roothub_exec = &musbotg_roothub_exec, .xfer_poll = &musbotg_do_poll, .set_hw_power_sleep = &musbotg_set_hw_power_sleep, }; diff --git a/sys/dev/usb/controller/uss820dci.c b/sys/dev/usb/controller/uss820dci.c index 0c37a932b2a9..7bbfdace3e72 100644 --- a/sys/dev/usb/controller/uss820dci.c +++ b/sys/dev/usb/controller/uss820dci.c @@ -1,2389 +1,2388 @@ /* $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2008 Hans Petter Selasky * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * This file contains the driver for the USS820 series USB Device * Controller * * NOTE: The datasheet does not document everything. */ #ifdef USB_GLOBAL_INCLUDE_FILE #include USB_GLOBAL_INCLUDE_FILE #else #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define USB_DEBUG_VAR uss820dcidebug #include #include #include #include #include #include #include #include #include #include #endif /* USB_GLOBAL_INCLUDE_FILE */ #include #define USS820_DCI_BUS2SC(bus) \ - ((struct uss820dci_softc *)(((uint8_t *)(bus)) - \ - ((uint8_t *)&(((struct uss820dci_softc *)0)->sc_bus)))) + __containerof(bus, struct uss820dci_softc, sc_bus) #define USS820_DCI_PC2SC(pc) \ USS820_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) #define USS820_DCI_THREAD_IRQ \ (USS820_SSR_SUSPEND | USS820_SSR_RESUME | USS820_SSR_RESET) #ifdef USB_DEBUG static int uss820dcidebug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, uss820dci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, "USB uss820dci"); SYSCTL_INT(_hw_usb_uss820dci, OID_AUTO, debug, CTLFLAG_RWTUN, &uss820dcidebug, 0, "uss820dci debug level"); #endif #define USS820_DCI_INTR_ENDPT 1 /* prototypes */ static const struct usb_bus_methods uss820dci_bus_methods; static const struct usb_pipe_methods uss820dci_device_bulk_methods; static const struct usb_pipe_methods uss820dci_device_ctrl_methods; static const struct usb_pipe_methods uss820dci_device_intr_methods; static const struct usb_pipe_methods uss820dci_device_isoc_fs_methods; static uss820dci_cmd_t uss820dci_setup_rx; static uss820dci_cmd_t uss820dci_data_rx; static uss820dci_cmd_t uss820dci_data_tx; static uss820dci_cmd_t uss820dci_data_tx_sync; static void uss820dci_device_done(struct usb_xfer *, usb_error_t); static void uss820dci_do_poll(struct usb_bus *); static void uss820dci_standard_done(struct usb_xfer *); static void uss820dci_intr_set(struct usb_xfer *, uint8_t); static void uss820dci_update_shared_1(struct uss820dci_softc *, uint8_t, uint8_t, uint8_t); static void uss820dci_root_intr(struct uss820dci_softc *); /* * Here is a list of what the USS820D chip can support. The main * limitation is that the sum of the buffer sizes must be less than * 1120 bytes. */ static const struct usb_hw_ep_profile uss820dci_ep_profile[] = { [0] = { .max_in_frame_size = 32, .max_out_frame_size = 32, .is_simplex = 0, .support_control = 1, }, [1] = { .max_in_frame_size = 64, .max_out_frame_size = 64, .is_simplex = 0, .support_multi_buffer = 1, .support_bulk = 1, .support_interrupt = 1, .support_in = 1, .support_out = 1, }, [2] = { .max_in_frame_size = 8, .max_out_frame_size = 8, .is_simplex = 0, .support_multi_buffer = 1, .support_bulk = 1, .support_interrupt = 1, .support_in = 1, .support_out = 1, }, [3] = { .max_in_frame_size = 256, .max_out_frame_size = 256, .is_simplex = 0, .support_multi_buffer = 1, .support_isochronous = 1, .support_in = 1, .support_out = 1, }, }; static void uss820dci_update_shared_1(struct uss820dci_softc *sc, uint8_t reg, uint8_t keep_mask, uint8_t set_mask) { uint8_t temp; USS820_WRITE_1(sc, USS820_PEND, 1); temp = USS820_READ_1(sc, reg); temp &= (keep_mask); temp |= (set_mask); USS820_WRITE_1(sc, reg, temp); USS820_WRITE_1(sc, USS820_PEND, 0); } static void uss820dci_get_hw_ep_profile(struct usb_device *udev, const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) { if (ep_addr == 0) { *ppf = uss820dci_ep_profile + 0; } else if (ep_addr < 5) { *ppf = uss820dci_ep_profile + 1; } else if (ep_addr < 7) { *ppf = uss820dci_ep_profile + 2; } else if (ep_addr == 7) { *ppf = uss820dci_ep_profile + 3; } else { *ppf = NULL; } } static void uss820dci_pull_up(struct uss820dci_softc *sc) { uint8_t temp; /* pullup D+, if possible */ if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) { sc->sc_flags.d_pulled_up = 1; DPRINTF("\n"); temp = USS820_READ_1(sc, USS820_MCSR); temp |= USS820_MCSR_DPEN; USS820_WRITE_1(sc, USS820_MCSR, temp); } } static void uss820dci_pull_down(struct uss820dci_softc *sc) { uint8_t temp; /* pulldown D+, if possible */ if (sc->sc_flags.d_pulled_up) { sc->sc_flags.d_pulled_up = 0; DPRINTF("\n"); temp = USS820_READ_1(sc, USS820_MCSR); temp &= ~USS820_MCSR_DPEN; USS820_WRITE_1(sc, USS820_MCSR, temp); } } static void uss820dci_wakeup_peer(struct uss820dci_softc *sc) { if (!(sc->sc_flags.status_suspend)) { return; } DPRINTFN(0, "not supported\n"); } static void uss820dci_set_address(struct uss820dci_softc *sc, uint8_t addr) { DPRINTFN(5, "addr=%d\n", addr); USS820_WRITE_1(sc, USS820_FADDR, addr); } static uint8_t uss820dci_setup_rx(struct uss820dci_softc *sc, struct uss820dci_td *td) { struct usb_device_request req; uint16_t count; uint8_t rx_stat; uint8_t temp; /* select the correct endpoint */ USS820_WRITE_1(sc, USS820_EPINDEX, td->ep_index); /* read out FIFO status */ rx_stat = USS820_READ_1(sc, USS820_RXSTAT); DPRINTFN(5, "rx_stat=0x%02x rem=%u\n", rx_stat, td->remainder); if (!(rx_stat & USS820_RXSTAT_RXSETUP)) { goto not_complete; } /* clear did stall */ td->did_stall = 0; /* clear stall and all I/O */ uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF ^ (USS820_EPCON_TXSTL | USS820_EPCON_RXSTL | USS820_EPCON_RXIE | USS820_EPCON_TXOE), 0); /* clear end overwrite flag */ uss820dci_update_shared_1(sc, USS820_RXSTAT, 0xFF ^ USS820_RXSTAT_EDOVW, 0); /* get the packet byte count */ count = USS820_READ_1(sc, USS820_RXCNTL); count |= (USS820_READ_1(sc, USS820_RXCNTH) << 8); count &= 0x3FF; /* verify data length */ if (count != td->remainder) { DPRINTFN(0, "Invalid SETUP packet " "length, %d bytes\n", count); goto setup_not_complete; } if (count != sizeof(req)) { DPRINTFN(0, "Unsupported SETUP packet " "length, %d bytes\n", count); goto setup_not_complete; } /* receive data */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, USS820_RXDAT * USS820_REG_STRIDE, (void *)&req, sizeof(req)); /* read out FIFO status */ rx_stat = USS820_READ_1(sc, USS820_RXSTAT); if (rx_stat & (USS820_RXSTAT_EDOVW | USS820_RXSTAT_STOVW)) { DPRINTF("new SETUP packet received\n"); return (1); /* not complete */ } /* clear receive setup bit */ uss820dci_update_shared_1(sc, USS820_RXSTAT, 0xFF ^ (USS820_RXSTAT_RXSETUP | USS820_RXSTAT_EDOVW | USS820_RXSTAT_STOVW), 0); /* set RXFFRC bit */ temp = USS820_READ_1(sc, USS820_RXCON); temp |= USS820_RXCON_RXFFRC; USS820_WRITE_1(sc, USS820_RXCON, temp); /* copy data into real buffer */ usbd_copy_in(td->pc, 0, &req, sizeof(req)); td->offset = sizeof(req); td->remainder = 0; /* sneak peek the set address */ if ((req.bmRequestType == UT_WRITE_DEVICE) && (req.bRequest == UR_SET_ADDRESS)) { sc->sc_dv_addr = req.wValue[0] & 0x7F; } else { sc->sc_dv_addr = 0xFF; } /* reset TX FIFO */ temp = USS820_READ_1(sc, USS820_TXCON); temp |= USS820_TXCON_TXCLR; USS820_WRITE_1(sc, USS820_TXCON, temp); temp &= ~USS820_TXCON_TXCLR; USS820_WRITE_1(sc, USS820_TXCON, temp); return (0); /* complete */ setup_not_complete: /* set RXFFRC bit */ temp = USS820_READ_1(sc, USS820_RXCON); temp |= USS820_RXCON_RXFFRC; USS820_WRITE_1(sc, USS820_RXCON, temp); /* FALLTHROUGH */ not_complete: /* abort any ongoing transfer */ if (!td->did_stall) { DPRINTFN(5, "stalling\n"); /* set stall */ uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF, (USS820_EPCON_TXSTL | USS820_EPCON_RXSTL)); td->did_stall = 1; } /* clear end overwrite flag, if any */ if (rx_stat & USS820_RXSTAT_RXSETUP) { uss820dci_update_shared_1(sc, USS820_RXSTAT, 0xFF ^ (USS820_RXSTAT_EDOVW | USS820_RXSTAT_STOVW | USS820_RXSTAT_RXSETUP), 0); } return (1); /* not complete */ } static uint8_t uss820dci_data_rx(struct uss820dci_softc *sc, struct uss820dci_td *td) { struct usb_page_search buf_res; uint16_t count; uint8_t rx_flag; uint8_t rx_stat; uint8_t rx_cntl; uint8_t to; uint8_t got_short; to = 2; /* don't loop forever! */ got_short = 0; /* select the correct endpoint */ USS820_WRITE_1(sc, USS820_EPINDEX, td->ep_index); /* check if any of the FIFO banks have data */ repeat: /* read out FIFO flag */ rx_flag = USS820_READ_1(sc, USS820_RXFLG); /* read out FIFO status */ rx_stat = USS820_READ_1(sc, USS820_RXSTAT); DPRINTFN(5, "rx_stat=0x%02x rx_flag=0x%02x rem=%u\n", rx_stat, rx_flag, td->remainder); if (rx_stat & (USS820_RXSTAT_RXSETUP | USS820_RXSTAT_RXSOVW | USS820_RXSTAT_EDOVW)) { if (td->remainder == 0 && td->ep_index == 0) { /* * We are actually complete and have * received the next SETUP */ DPRINTFN(5, "faking complete\n"); return (0); /* complete */ } /* * USB Host Aborted the transfer. */ td->error = 1; return (0); /* complete */ } /* check for errors */ if (rx_flag & (USS820_RXFLG_RXOVF | USS820_RXFLG_RXURF)) { DPRINTFN(5, "overflow or underflow\n"); /* should not happen */ td->error = 1; return (0); /* complete */ } /* check status */ if (!(rx_flag & (USS820_RXFLG_RXFIF0 | USS820_RXFLG_RXFIF1))) { /* read out EPCON register */ /* enable RX input */ if (!td->did_enable) { uss820dci_update_shared_1(USS820_DCI_PC2SC(td->pc), USS820_EPCON, 0xFF, USS820_EPCON_RXIE); td->did_enable = 1; } return (1); /* not complete */ } /* get the packet byte count */ count = USS820_READ_1(sc, USS820_RXCNTL); count |= (USS820_READ_1(sc, USS820_RXCNTH) << 8); count &= 0x3FF; DPRINTFN(5, "count=0x%04x\n", count); /* verify the packet byte count */ if (count != td->max_packet_size) { if (count < td->max_packet_size) { /* we have a short packet */ td->short_pkt = 1; got_short = 1; } else { /* invalid USB packet */ td->error = 1; return (0); /* we are complete */ } } /* verify the packet byte count */ if (count > td->remainder) { /* invalid USB packet */ td->error = 1; return (0); /* we are complete */ } while (count > 0) { usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* receive data */ bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, USS820_RXDAT * USS820_REG_STRIDE, buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* set RXFFRC bit */ rx_cntl = USS820_READ_1(sc, USS820_RXCON); rx_cntl |= USS820_RXCON_RXFFRC; USS820_WRITE_1(sc, USS820_RXCON, rx_cntl); /* check if we are complete */ if ((td->remainder == 0) || got_short) { if (td->short_pkt) { /* we are complete */ return (0); } /* else need to receive a zero length packet */ } if (--to) { goto repeat; } return (1); /* not complete */ } static uint8_t uss820dci_data_tx(struct uss820dci_softc *sc, struct uss820dci_td *td) { struct usb_page_search buf_res; uint16_t count; uint16_t count_copy; uint8_t rx_stat; uint8_t tx_flag; uint8_t to; /* select the correct endpoint */ USS820_WRITE_1(sc, USS820_EPINDEX, td->ep_index); to = 2; /* don't loop forever! */ repeat: /* read out TX FIFO flags */ tx_flag = USS820_READ_1(sc, USS820_TXFLG); DPRINTFN(5, "tx_flag=0x%02x rem=%u\n", tx_flag, td->remainder); if (td->ep_index == 0) { /* read out RX FIFO status last */ rx_stat = USS820_READ_1(sc, USS820_RXSTAT); DPRINTFN(5, "rx_stat=0x%02x\n", rx_stat); if (rx_stat & (USS820_RXSTAT_RXSETUP | USS820_RXSTAT_RXSOVW | USS820_RXSTAT_EDOVW)) { /* * The current transfer was aborted by the USB * Host: */ td->error = 1; return (0); /* complete */ } } if (tx_flag & (USS820_TXFLG_TXOVF | USS820_TXFLG_TXURF)) { td->error = 1; return (0); /* complete */ } if (tx_flag & USS820_TXFLG_TXFIF0) { if (tx_flag & USS820_TXFLG_TXFIF1) { return (1); /* not complete */ } } if ((!td->support_multi_buffer) && (tx_flag & (USS820_TXFLG_TXFIF0 | USS820_TXFLG_TXFIF1))) { return (1); /* not complete */ } count = td->max_packet_size; if (td->remainder < count) { /* we have a short packet */ td->short_pkt = 1; count = td->remainder; } count_copy = count; while (count > 0) { usbd_get_page(td->pc, td->offset, &buf_res); /* get correct length */ if (buf_res.length > count) { buf_res.length = count; } /* transmit data */ bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, USS820_TXDAT * USS820_REG_STRIDE, buf_res.buffer, buf_res.length); /* update counters */ count -= buf_res.length; td->offset += buf_res.length; td->remainder -= buf_res.length; } /* post-write high packet byte count first */ USS820_WRITE_1(sc, USS820_TXCNTH, count_copy >> 8); /* post-write low packet byte count last */ USS820_WRITE_1(sc, USS820_TXCNTL, count_copy); /* * Enable TX output, which must happen after that we have written * data into the FIFO. This is undocumented. */ if (!td->did_enable) { uss820dci_update_shared_1(USS820_DCI_PC2SC(td->pc), USS820_EPCON, 0xFF, USS820_EPCON_TXOE); td->did_enable = 1; } /* check remainder */ if (td->remainder == 0) { if (td->short_pkt) { return (0); /* complete */ } /* else we need to transmit a short packet */ } if (--to) { goto repeat; } return (1); /* not complete */ } static uint8_t uss820dci_data_tx_sync(struct uss820dci_softc *sc, struct uss820dci_td *td) { uint8_t rx_stat; uint8_t tx_flag; /* select the correct endpoint */ USS820_WRITE_1(sc, USS820_EPINDEX, td->ep_index); /* read out TX FIFO flag */ tx_flag = USS820_READ_1(sc, USS820_TXFLG); if (td->ep_index == 0) { /* read out RX FIFO status last */ rx_stat = USS820_READ_1(sc, USS820_RXSTAT); DPRINTFN(5, "rx_stat=0x%02x rem=%u\n", rx_stat, td->remainder); if (rx_stat & (USS820_RXSTAT_RXSETUP | USS820_RXSTAT_RXSOVW | USS820_RXSTAT_EDOVW)) { DPRINTFN(5, "faking complete\n"); /* Race condition */ return (0); /* complete */ } } DPRINTFN(5, "tx_flag=0x%02x rem=%u\n", tx_flag, td->remainder); if (tx_flag & (USS820_TXFLG_TXOVF | USS820_TXFLG_TXURF)) { td->error = 1; return (0); /* complete */ } if (tx_flag & (USS820_TXFLG_TXFIF0 | USS820_TXFLG_TXFIF1)) { return (1); /* not complete */ } if (td->ep_index == 0 && sc->sc_dv_addr != 0xFF) { /* write function address */ uss820dci_set_address(sc, sc->sc_dv_addr); } return (0); /* complete */ } static void uss820dci_xfer_do_fifo(struct usb_xfer *xfer) { struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus); struct uss820dci_td *td; DPRINTFN(9, "\n"); td = xfer->td_transfer_cache; if (td == NULL) return; while (1) { if ((td->func) (sc, td)) { /* operation in progress */ break; } if (((void *)td) == xfer->td_transfer_last) { goto done; } if (td->error) { goto done; } else if (td->remainder > 0) { /* * We had a short transfer. If there is no alternate * next, stop processing ! */ if (!td->alt_next) { goto done; } } /* * Fetch the next transfer descriptor. */ td = td->obj_next; xfer->td_transfer_cache = td; } return; done: /* compute all actual lengths */ xfer->td_transfer_cache = NULL; sc->sc_xfer_complete = 1; } static uint8_t uss820dci_xfer_do_complete(struct usb_xfer *xfer) { struct uss820dci_td *td; DPRINTFN(9, "\n"); td = xfer->td_transfer_cache; if (td == NULL) { /* compute all actual lengths */ uss820dci_standard_done(xfer); return(1); } return (0); } static void uss820dci_interrupt_poll_locked(struct uss820dci_softc *sc) { struct usb_xfer *xfer; TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) uss820dci_xfer_do_fifo(xfer); } static void uss820dci_interrupt_complete_locked(struct uss820dci_softc *sc) { struct usb_xfer *xfer; repeat: TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { if (uss820dci_xfer_do_complete(xfer)) goto repeat; } } static void uss820dci_wait_suspend(struct uss820dci_softc *sc, uint8_t on) { uint8_t scr; uint8_t scratch; scr = USS820_READ_1(sc, USS820_SCR); scratch = USS820_READ_1(sc, USS820_SCRATCH); if (on) { scr |= USS820_SCR_IE_SUSP; scratch &= ~USS820_SCRATCH_IE_RESUME; } else { scr &= ~USS820_SCR_IE_SUSP; scratch |= USS820_SCRATCH_IE_RESUME; } USS820_WRITE_1(sc, USS820_SCR, scr); USS820_WRITE_1(sc, USS820_SCRATCH, scratch); } int uss820dci_filter_interrupt(void *arg) { struct uss820dci_softc *sc = arg; int retval = FILTER_HANDLED; uint8_t ssr; USB_BUS_SPIN_LOCK(&sc->sc_bus); ssr = USS820_READ_1(sc, USS820_SSR); uss820dci_update_shared_1(sc, USS820_SSR, USS820_DCI_THREAD_IRQ, 0); if (ssr & USS820_DCI_THREAD_IRQ) retval = FILTER_SCHEDULE_THREAD; /* poll FIFOs, if any */ uss820dci_interrupt_poll_locked(sc); if (sc->sc_xfer_complete != 0) retval = FILTER_SCHEDULE_THREAD; USB_BUS_SPIN_UNLOCK(&sc->sc_bus); return (retval); } void uss820dci_interrupt(void *arg) { struct uss820dci_softc *sc = arg; uint8_t ssr; uint8_t event; USB_BUS_LOCK(&sc->sc_bus); USB_BUS_SPIN_LOCK(&sc->sc_bus); ssr = USS820_READ_1(sc, USS820_SSR); /* acknowledge all interrupts */ uss820dci_update_shared_1(sc, USS820_SSR, ~USS820_DCI_THREAD_IRQ, 0); /* check for any bus state change interrupts */ if (ssr & USS820_DCI_THREAD_IRQ) { event = 0; if (ssr & USS820_SSR_RESET) { sc->sc_flags.status_bus_reset = 1; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; /* disable resume interrupt */ uss820dci_wait_suspend(sc, 1); event = 1; } /* * If "RESUME" and "SUSPEND" is set at the same time * we interpret that like "RESUME". Resume is set when * there is at least 3 milliseconds of inactivity on * the USB BUS. */ if (ssr & USS820_SSR_RESUME) { if (sc->sc_flags.status_suspend) { sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 1; /* disable resume interrupt */ uss820dci_wait_suspend(sc, 1); event = 1; } } else if (ssr & USS820_SSR_SUSPEND) { if (!sc->sc_flags.status_suspend) { sc->sc_flags.status_suspend = 1; sc->sc_flags.change_suspend = 1; /* enable resume interrupt */ uss820dci_wait_suspend(sc, 0); event = 1; } } if (event) { DPRINTF("real bus interrupt 0x%02x\n", ssr); /* complete root HUB interrupt endpoint */ uss820dci_root_intr(sc); } } /* acknowledge all SBI interrupts */ uss820dci_update_shared_1(sc, USS820_SBI, 0, 0); /* acknowledge all SBI1 interrupts */ uss820dci_update_shared_1(sc, USS820_SBI1, 0, 0); if (sc->sc_xfer_complete != 0) { sc->sc_xfer_complete = 0; /* complete FIFOs, if any */ uss820dci_interrupt_complete_locked(sc); } USB_BUS_SPIN_UNLOCK(&sc->sc_bus); USB_BUS_UNLOCK(&sc->sc_bus); } static void uss820dci_setup_standard_chain_sub(struct uss820_std_temp *temp) { struct uss820dci_td *td; /* get current Transfer Descriptor */ td = temp->td_next; temp->td = td; /* prepare for next TD */ temp->td_next = td->obj_next; /* fill out the Transfer Descriptor */ td->func = temp->func; td->pc = temp->pc; td->offset = temp->offset; td->remainder = temp->len; td->error = 0; td->did_enable = 0; td->did_stall = temp->did_stall; td->short_pkt = temp->short_pkt; td->alt_next = temp->setup_alt_next; } static void uss820dci_setup_standard_chain(struct usb_xfer *xfer) { struct uss820_std_temp temp; struct uss820dci_softc *sc; struct uss820dci_td *td; uint32_t x; uint8_t ep_no; DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", xfer->address, UE_GET_ADDR(xfer->endpointno), xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); temp.max_frame_size = xfer->max_frame_size; td = xfer->td_start[0]; xfer->td_transfer_first = td; xfer->td_transfer_cache = td; /* setup temp */ temp.pc = NULL; temp.td = NULL; temp.td_next = xfer->td_start[0]; temp.offset = 0; temp.setup_alt_next = xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr; temp.did_stall = !xfer->flags_int.control_stall; sc = USS820_DCI_BUS2SC(xfer->xroot->bus); ep_no = (xfer->endpointno & UE_ADDR); /* check if we should prepend a setup message */ if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { temp.func = &uss820dci_setup_rx; temp.len = xfer->frlengths[0]; temp.pc = xfer->frbuffers + 0; temp.short_pkt = temp.len ? 1 : 0; /* check for last frame */ if (xfer->nframes == 1) { /* no STATUS stage yet, SETUP is last */ if (xfer->flags_int.control_act) temp.setup_alt_next = 0; } uss820dci_setup_standard_chain_sub(&temp); } x = 1; } else { x = 0; } if (x != xfer->nframes) { if (xfer->endpointno & UE_DIR_IN) { temp.func = &uss820dci_data_tx; } else { temp.func = &uss820dci_data_rx; } /* setup "pc" pointer */ temp.pc = xfer->frbuffers + x; } while (x != xfer->nframes) { /* DATA0 / DATA1 message */ temp.len = xfer->frlengths[x]; x++; if (x == xfer->nframes) { if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_act) { temp.setup_alt_next = 0; } } else { temp.setup_alt_next = 0; } } if (temp.len == 0) { /* make sure that we send an USB packet */ temp.short_pkt = 0; } else { /* regular data transfer */ temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; } uss820dci_setup_standard_chain_sub(&temp); if (xfer->flags_int.isochronous_xfr) { temp.offset += temp.len; } else { /* get next Page Cache pointer */ temp.pc = xfer->frbuffers + x; } } /* check for control transfer */ if (xfer->flags_int.control_xfr) { uint8_t need_sync; /* always setup a valid "pc" pointer for status and sync */ temp.pc = xfer->frbuffers + 0; temp.len = 0; temp.short_pkt = 0; temp.setup_alt_next = 0; /* check if we should append a status stage */ if (!xfer->flags_int.control_act) { /* * Send a DATA1 message and invert the current * endpoint direction. */ if (xfer->endpointno & UE_DIR_IN) { temp.func = &uss820dci_data_rx; need_sync = 0; } else { temp.func = &uss820dci_data_tx; need_sync = 1; } temp.len = 0; temp.short_pkt = 0; uss820dci_setup_standard_chain_sub(&temp); if (need_sync) { /* we need a SYNC point after TX */ temp.func = &uss820dci_data_tx_sync; uss820dci_setup_standard_chain_sub(&temp); } } } /* must have at least one frame! */ td = temp.td; xfer->td_transfer_last = td; } static void uss820dci_timeout(void *arg) { struct usb_xfer *xfer = arg; DPRINTF("xfer=%p\n", xfer); USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); /* transfer is transferred */ uss820dci_device_done(xfer, USB_ERR_TIMEOUT); } static void uss820dci_intr_set(struct usb_xfer *xfer, uint8_t set) { struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus); uint8_t ep_no = (xfer->endpointno & UE_ADDR); uint8_t ep_reg; uint8_t temp; DPRINTFN(15, "endpoint 0x%02x\n", xfer->endpointno); if (ep_no > 3) { ep_reg = USS820_SBIE1; } else { ep_reg = USS820_SBIE; } ep_no &= 3; ep_no = 1 << (2 * ep_no); if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { ep_no <<= 1; /* RX interrupt only */ } else { ep_no |= (ep_no << 1); /* RX and TX interrupt */ } } else { if (!(xfer->endpointno & UE_DIR_IN)) { ep_no <<= 1; } } temp = USS820_READ_1(sc, ep_reg); if (set) { temp |= ep_no; } else { temp &= ~ep_no; } USS820_WRITE_1(sc, ep_reg, temp); } static void uss820dci_start_standard_chain(struct usb_xfer *xfer) { struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus); DPRINTFN(9, "\n"); USB_BUS_SPIN_LOCK(&sc->sc_bus); /* poll one time */ uss820dci_xfer_do_fifo(xfer); if (uss820dci_xfer_do_complete(xfer) == 0) { /* * Only enable the endpoint interrupt when we are * actually waiting for data, hence we are dealing * with level triggered interrupts ! */ uss820dci_intr_set(xfer, 1); /* put transfer on interrupt queue */ usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); /* start timeout, if any */ if (xfer->timeout != 0) { usbd_transfer_timeout_ms(xfer, &uss820dci_timeout, xfer->timeout); } } USB_BUS_SPIN_UNLOCK(&sc->sc_bus); } static void uss820dci_root_intr(struct uss820dci_softc *sc) { DPRINTFN(9, "\n"); USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* set port bit */ sc->sc_hub_idata[0] = 0x02; /* we only have one port */ uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); } static usb_error_t uss820dci_standard_done_sub(struct usb_xfer *xfer) { struct uss820dci_td *td; uint32_t len; uint8_t error; DPRINTFN(9, "\n"); td = xfer->td_transfer_cache; do { len = td->remainder; if (xfer->aframes != xfer->nframes) { /* * Verify the length and subtract * the remainder from "frlengths[]": */ if (len > xfer->frlengths[xfer->aframes]) { td->error = 1; } else { xfer->frlengths[xfer->aframes] -= len; } } /* Check for transfer error */ if (td->error) { /* the transfer is finished */ error = 1; td = NULL; break; } /* Check for short transfer */ if (len > 0) { if (xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr) { /* follow alt next */ if (td->alt_next) { td = td->obj_next; } else { td = NULL; } } else { /* the transfer is finished */ td = NULL; } error = 0; break; } td = td->obj_next; /* this USB frame is complete */ error = 0; break; } while (0); /* update transfer cache */ xfer->td_transfer_cache = td; return (error ? USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); } static void uss820dci_standard_done(struct usb_xfer *xfer) { usb_error_t err = 0; DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", xfer, xfer->endpoint); /* reset scanner */ xfer->td_transfer_cache = xfer->td_transfer_first; if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) { err = uss820dci_standard_done_sub(xfer); } xfer->aframes = 1; if (xfer->td_transfer_cache == NULL) { goto done; } } while (xfer->aframes != xfer->nframes) { err = uss820dci_standard_done_sub(xfer); xfer->aframes++; if (xfer->td_transfer_cache == NULL) { goto done; } } if (xfer->flags_int.control_xfr && !xfer->flags_int.control_act) { err = uss820dci_standard_done_sub(xfer); } done: uss820dci_device_done(xfer, err); } /*------------------------------------------------------------------------* * uss820dci_device_done * * NOTE: this function can be called more than one time on the * same USB transfer! *------------------------------------------------------------------------*/ static void uss820dci_device_done(struct usb_xfer *xfer, usb_error_t error) { struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus); USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", xfer, xfer->endpoint, error); USB_BUS_SPIN_LOCK(&sc->sc_bus); if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { uss820dci_intr_set(xfer, 0); } /* dequeue transfer and start next transfer */ usbd_transfer_done(xfer, error); USB_BUS_SPIN_UNLOCK(&sc->sc_bus); } static void uss820dci_xfer_stall(struct usb_xfer *xfer) { uss820dci_device_done(xfer, USB_ERR_STALLED); } static void uss820dci_set_stall(struct usb_device *udev, struct usb_endpoint *ep, uint8_t *did_stall) { struct uss820dci_softc *sc; uint8_t ep_no; uint8_t ep_type; uint8_t ep_dir; uint8_t temp; USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); DPRINTFN(5, "endpoint=%p\n", ep); /* set FORCESTALL */ sc = USS820_DCI_BUS2SC(udev->bus); ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); ep_dir = (ep->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)); ep_type = (ep->edesc->bmAttributes & UE_XFERTYPE); if (ep_type == UE_CONTROL) { /* should not happen */ return; } USB_BUS_SPIN_LOCK(&sc->sc_bus); USS820_WRITE_1(sc, USS820_EPINDEX, ep_no); if (ep_dir == UE_DIR_IN) { temp = USS820_EPCON_TXSTL; } else { temp = USS820_EPCON_RXSTL; } uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF, temp); USB_BUS_SPIN_UNLOCK(&sc->sc_bus); } static void uss820dci_clear_stall_sub(struct uss820dci_softc *sc, uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) { uint8_t temp; if (ep_type == UE_CONTROL) { /* clearing stall is not needed */ return; } USB_BUS_SPIN_LOCK(&sc->sc_bus); /* select endpoint index */ USS820_WRITE_1(sc, USS820_EPINDEX, ep_no); /* clear stall and disable I/O transfers */ if (ep_dir == UE_DIR_IN) { temp = 0xFF ^ (USS820_EPCON_TXOE | USS820_EPCON_TXSTL); } else { temp = 0xFF ^ (USS820_EPCON_RXIE | USS820_EPCON_RXSTL); } uss820dci_update_shared_1(sc, USS820_EPCON, temp, 0); if (ep_dir == UE_DIR_IN) { /* reset data toggle */ USS820_WRITE_1(sc, USS820_TXSTAT, USS820_TXSTAT_TXSOVW); /* reset FIFO */ temp = USS820_READ_1(sc, USS820_TXCON); temp |= USS820_TXCON_TXCLR; USS820_WRITE_1(sc, USS820_TXCON, temp); temp &= ~USS820_TXCON_TXCLR; USS820_WRITE_1(sc, USS820_TXCON, temp); } else { /* reset data toggle */ uss820dci_update_shared_1(sc, USS820_RXSTAT, 0, USS820_RXSTAT_RXSOVW); /* reset FIFO */ temp = USS820_READ_1(sc, USS820_RXCON); temp |= USS820_RXCON_RXCLR; temp &= ~USS820_RXCON_RXFFRC; USS820_WRITE_1(sc, USS820_RXCON, temp); temp &= ~USS820_RXCON_RXCLR; USS820_WRITE_1(sc, USS820_RXCON, temp); } USB_BUS_SPIN_UNLOCK(&sc->sc_bus); } static void uss820dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) { struct uss820dci_softc *sc; struct usb_endpoint_descriptor *ed; USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); DPRINTFN(5, "endpoint=%p\n", ep); /* check mode */ if (udev->flags.usb_mode != USB_MODE_DEVICE) { /* not supported */ return; } /* get softc */ sc = USS820_DCI_BUS2SC(udev->bus); /* get endpoint descriptor */ ed = ep->edesc; /* reset endpoint */ uss820dci_clear_stall_sub(sc, (ed->bEndpointAddress & UE_ADDR), (ed->bmAttributes & UE_XFERTYPE), (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); } usb_error_t uss820dci_init(struct uss820dci_softc *sc) { const struct usb_hw_ep_profile *pf; uint8_t n; uint8_t temp; DPRINTF("start\n"); /* set up the bus structure */ sc->sc_bus.usbrev = USB_REV_1_1; sc->sc_bus.methods = &uss820dci_bus_methods; USB_BUS_LOCK(&sc->sc_bus); /* we always have VBUS */ sc->sc_flags.status_vbus = 1; /* reset the chip */ USS820_WRITE_1(sc, USS820_SCR, USS820_SCR_SRESET); DELAY(100); USS820_WRITE_1(sc, USS820_SCR, 0); /* wait for reset to complete */ for (n = 0;; n++) { temp = USS820_READ_1(sc, USS820_MCSR); if (temp & USS820_MCSR_INIT) { break; } if (n == 100) { USB_BUS_UNLOCK(&sc->sc_bus); return (USB_ERR_INVAL); } /* wait a little for things to stabilise */ DELAY(100); } /* do a pulldown */ uss820dci_pull_down(sc); /* wait 10ms for pulldown to stabilise */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); /* check hardware revision */ temp = USS820_READ_1(sc, USS820_REV); if (temp < 0x13) { USB_BUS_UNLOCK(&sc->sc_bus); return (USB_ERR_INVAL); } /* enable interrupts */ USS820_WRITE_1(sc, USS820_SCR, USS820_SCR_T_IRQ | USS820_SCR_IE_RESET | /* USS820_SCR_RWUPE | */ USS820_SCR_IE_SUSP | USS820_SCR_IRQPOL); /* enable interrupts */ USS820_WRITE_1(sc, USS820_SCRATCH, USS820_SCRATCH_IE_RESUME); /* enable features */ USS820_WRITE_1(sc, USS820_MCSR, USS820_MCSR_BDFEAT | USS820_MCSR_FEAT); sc->sc_flags.mcsr_feat = 1; /* disable interrupts */ USS820_WRITE_1(sc, USS820_SBIE, 0); /* disable interrupts */ USS820_WRITE_1(sc, USS820_SBIE1, 0); /* disable all endpoints */ for (n = 0; n != USS820_EP_MAX; n++) { /* select endpoint */ USS820_WRITE_1(sc, USS820_EPINDEX, n); /* disable endpoint */ uss820dci_update_shared_1(sc, USS820_EPCON, 0, 0); } /* * Initialise default values for some registers that cannot be * changed during operation! */ for (n = 0; n != USS820_EP_MAX; n++) { uss820dci_get_hw_ep_profile(NULL, &pf, n); /* the maximum frame sizes should be the same */ if (pf->max_in_frame_size != pf->max_out_frame_size) { DPRINTF("Max frame size mismatch %u != %u\n", pf->max_in_frame_size, pf->max_out_frame_size); } if (pf->support_isochronous) { if (pf->max_in_frame_size <= 64) { temp = (USS820_TXCON_FFSZ_16_64 | USS820_TXCON_TXISO | USS820_TXCON_ATM); } else if (pf->max_in_frame_size <= 256) { temp = (USS820_TXCON_FFSZ_64_256 | USS820_TXCON_TXISO | USS820_TXCON_ATM); } else if (pf->max_in_frame_size <= 512) { temp = (USS820_TXCON_FFSZ_8_512 | USS820_TXCON_TXISO | USS820_TXCON_ATM); } else { /* 1024 bytes */ temp = (USS820_TXCON_FFSZ_32_1024 | USS820_TXCON_TXISO | USS820_TXCON_ATM); } } else { if ((pf->max_in_frame_size <= 8) && (sc->sc_flags.mcsr_feat)) { temp = (USS820_TXCON_FFSZ_8_512 | USS820_TXCON_ATM); } else if (pf->max_in_frame_size <= 16) { temp = (USS820_TXCON_FFSZ_16_64 | USS820_TXCON_ATM); } else if ((pf->max_in_frame_size <= 32) && (sc->sc_flags.mcsr_feat)) { temp = (USS820_TXCON_FFSZ_32_1024 | USS820_TXCON_ATM); } else { /* 64 bytes */ temp = (USS820_TXCON_FFSZ_64_256 | USS820_TXCON_ATM); } } /* need to configure the chip early */ USS820_WRITE_1(sc, USS820_EPINDEX, n); USS820_WRITE_1(sc, USS820_TXCON, temp); USS820_WRITE_1(sc, USS820_RXCON, temp); if (pf->support_control) { temp = USS820_EPCON_CTLEP | USS820_EPCON_RXSPM | USS820_EPCON_RXIE | USS820_EPCON_RXEPEN | USS820_EPCON_TXOE | USS820_EPCON_TXEPEN; } else { temp = USS820_EPCON_RXEPEN | USS820_EPCON_TXEPEN; } uss820dci_update_shared_1(sc, USS820_EPCON, 0, temp); } USB_BUS_UNLOCK(&sc->sc_bus); /* catch any lost interrupts */ uss820dci_do_poll(&sc->sc_bus); return (0); /* success */ } void uss820dci_uninit(struct uss820dci_softc *sc) { uint8_t temp; USB_BUS_LOCK(&sc->sc_bus); /* disable all interrupts */ temp = USS820_READ_1(sc, USS820_SCR); temp &= ~USS820_SCR_T_IRQ; USS820_WRITE_1(sc, USS820_SCR, temp); sc->sc_flags.port_powered = 0; sc->sc_flags.status_vbus = 0; sc->sc_flags.status_bus_reset = 0; sc->sc_flags.status_suspend = 0; sc->sc_flags.change_suspend = 0; sc->sc_flags.change_connect = 1; uss820dci_pull_down(sc); USB_BUS_UNLOCK(&sc->sc_bus); } static void uss820dci_suspend(struct uss820dci_softc *sc) { /* TODO */ } static void uss820dci_resume(struct uss820dci_softc *sc) { /* TODO */ } static void uss820dci_do_poll(struct usb_bus *bus) { struct uss820dci_softc *sc = USS820_DCI_BUS2SC(bus); USB_BUS_LOCK(&sc->sc_bus); USB_BUS_SPIN_LOCK(&sc->sc_bus); uss820dci_interrupt_poll_locked(sc); uss820dci_interrupt_complete_locked(sc); USB_BUS_SPIN_UNLOCK(&sc->sc_bus); USB_BUS_UNLOCK(&sc->sc_bus); } /*------------------------------------------------------------------------* * uss820dci bulk support *------------------------------------------------------------------------*/ static void uss820dci_device_bulk_open(struct usb_xfer *xfer) { return; } static void uss820dci_device_bulk_close(struct usb_xfer *xfer) { uss820dci_device_done(xfer, USB_ERR_CANCELLED); } static void uss820dci_device_bulk_enter(struct usb_xfer *xfer) { return; } static void uss820dci_device_bulk_start(struct usb_xfer *xfer) { /* setup TDs */ uss820dci_setup_standard_chain(xfer); uss820dci_start_standard_chain(xfer); } static const struct usb_pipe_methods uss820dci_device_bulk_methods = { .open = uss820dci_device_bulk_open, .close = uss820dci_device_bulk_close, .enter = uss820dci_device_bulk_enter, .start = uss820dci_device_bulk_start, }; /*------------------------------------------------------------------------* * uss820dci control support *------------------------------------------------------------------------*/ static void uss820dci_device_ctrl_open(struct usb_xfer *xfer) { return; } static void uss820dci_device_ctrl_close(struct usb_xfer *xfer) { uss820dci_device_done(xfer, USB_ERR_CANCELLED); } static void uss820dci_device_ctrl_enter(struct usb_xfer *xfer) { return; } static void uss820dci_device_ctrl_start(struct usb_xfer *xfer) { /* setup TDs */ uss820dci_setup_standard_chain(xfer); uss820dci_start_standard_chain(xfer); } static const struct usb_pipe_methods uss820dci_device_ctrl_methods = { .open = uss820dci_device_ctrl_open, .close = uss820dci_device_ctrl_close, .enter = uss820dci_device_ctrl_enter, .start = uss820dci_device_ctrl_start, }; /*------------------------------------------------------------------------* * uss820dci interrupt support *------------------------------------------------------------------------*/ static void uss820dci_device_intr_open(struct usb_xfer *xfer) { return; } static void uss820dci_device_intr_close(struct usb_xfer *xfer) { uss820dci_device_done(xfer, USB_ERR_CANCELLED); } static void uss820dci_device_intr_enter(struct usb_xfer *xfer) { return; } static void uss820dci_device_intr_start(struct usb_xfer *xfer) { /* setup TDs */ uss820dci_setup_standard_chain(xfer); uss820dci_start_standard_chain(xfer); } static const struct usb_pipe_methods uss820dci_device_intr_methods = { .open = uss820dci_device_intr_open, .close = uss820dci_device_intr_close, .enter = uss820dci_device_intr_enter, .start = uss820dci_device_intr_start, }; /*------------------------------------------------------------------------* * uss820dci full speed isochronous support *------------------------------------------------------------------------*/ static void uss820dci_device_isoc_fs_open(struct usb_xfer *xfer) { return; } static void uss820dci_device_isoc_fs_close(struct usb_xfer *xfer) { uss820dci_device_done(xfer, USB_ERR_CANCELLED); } static void uss820dci_device_isoc_fs_enter(struct usb_xfer *xfer) { struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus); uint32_t nframes; DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", xfer, xfer->endpoint->isoc_next, xfer->nframes); /* get the current frame index - we don't need the high bits */ nframes = USS820_READ_1(sc, USS820_SOFL); if (usbd_xfer_get_isochronous_start_frame( xfer, nframes, 0, 1, USS820_SOFL_MASK, NULL)) DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); /* setup TDs */ uss820dci_setup_standard_chain(xfer); } static void uss820dci_device_isoc_fs_start(struct usb_xfer *xfer) { /* start TD chain */ uss820dci_start_standard_chain(xfer); } static const struct usb_pipe_methods uss820dci_device_isoc_fs_methods = { .open = uss820dci_device_isoc_fs_open, .close = uss820dci_device_isoc_fs_close, .enter = uss820dci_device_isoc_fs_enter, .start = uss820dci_device_isoc_fs_start, }; /*------------------------------------------------------------------------* * uss820dci root control support *------------------------------------------------------------------------* * Simulate a hardware HUB by handling all the necessary requests. *------------------------------------------------------------------------*/ static const struct usb_device_descriptor uss820dci_devd = { .bLength = sizeof(struct usb_device_descriptor), .bDescriptorType = UDESC_DEVICE, .bcdUSB = {0x00, 0x02}, .bDeviceClass = UDCLASS_HUB, .bDeviceSubClass = UDSUBCLASS_HUB, .bDeviceProtocol = UDPROTO_FSHUB, .bMaxPacketSize = 64, .bcdDevice = {0x00, 0x01}, .iManufacturer = 1, .iProduct = 2, .bNumConfigurations = 1, }; static const struct usb_device_qualifier uss820dci_odevd = { .bLength = sizeof(struct usb_device_qualifier), .bDescriptorType = UDESC_DEVICE_QUALIFIER, .bcdUSB = {0x00, 0x02}, .bDeviceClass = UDCLASS_HUB, .bDeviceSubClass = UDSUBCLASS_HUB, .bDeviceProtocol = UDPROTO_FSHUB, .bMaxPacketSize0 = 0, .bNumConfigurations = 0, }; static const struct uss820dci_config_desc uss820dci_confd = { .confd = { .bLength = sizeof(struct usb_config_descriptor), .bDescriptorType = UDESC_CONFIG, .wTotalLength[0] = sizeof(uss820dci_confd), .bNumInterface = 1, .bConfigurationValue = 1, .iConfiguration = 0, .bmAttributes = UC_SELF_POWERED, .bMaxPower = 0, }, .ifcd = { .bLength = sizeof(struct usb_interface_descriptor), .bDescriptorType = UDESC_INTERFACE, .bNumEndpoints = 1, .bInterfaceClass = UICLASS_HUB, .bInterfaceSubClass = UISUBCLASS_HUB, .bInterfaceProtocol = 0, }, .endpd = { .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = UDESC_ENDPOINT, .bEndpointAddress = (UE_DIR_IN | USS820_DCI_INTR_ENDPT), .bmAttributes = UE_INTERRUPT, .wMaxPacketSize[0] = 8, .bInterval = 255, }, }; #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } static const struct usb_hub_descriptor_min uss820dci_hubd = { .bDescLength = sizeof(uss820dci_hubd), .bDescriptorType = UDESC_HUB, .bNbrPorts = 1, HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), .bPwrOn2PwrGood = 50, .bHubContrCurrent = 0, .DeviceRemovable = {0}, /* port is removable */ }; #define STRING_VENDOR \ "A\0G\0E\0R\0E" #define STRING_PRODUCT \ "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" USB_MAKE_STRING_DESC(STRING_VENDOR, uss820dci_vendor); USB_MAKE_STRING_DESC(STRING_PRODUCT, uss820dci_product); static usb_error_t uss820dci_roothub_exec(struct usb_device *udev, struct usb_device_request *req, const void **pptr, uint16_t *plength) { struct uss820dci_softc *sc = USS820_DCI_BUS2SC(udev->bus); const void *ptr; uint16_t len; uint16_t value; uint16_t index; usb_error_t err; USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* buffer reset */ ptr = (const void *)&sc->sc_hub_temp; len = 0; err = 0; value = UGETW(req->wValue); index = UGETW(req->wIndex); /* demultiplex the control request */ switch (req->bmRequestType) { case UT_READ_DEVICE: switch (req->bRequest) { case UR_GET_DESCRIPTOR: goto tr_handle_get_descriptor; case UR_GET_CONFIG: goto tr_handle_get_config; case UR_GET_STATUS: goto tr_handle_get_status; default: goto tr_stalled; } break; case UT_WRITE_DEVICE: switch (req->bRequest) { case UR_SET_ADDRESS: goto tr_handle_set_address; case UR_SET_CONFIG: goto tr_handle_set_config; case UR_CLEAR_FEATURE: goto tr_valid; /* nop */ case UR_SET_DESCRIPTOR: goto tr_valid; /* nop */ case UR_SET_FEATURE: default: goto tr_stalled; } break; case UT_WRITE_ENDPOINT: switch (req->bRequest) { case UR_CLEAR_FEATURE: switch (UGETW(req->wValue)) { case UF_ENDPOINT_HALT: goto tr_handle_clear_halt; case UF_DEVICE_REMOTE_WAKEUP: goto tr_handle_clear_wakeup; default: goto tr_stalled; } break; case UR_SET_FEATURE: switch (UGETW(req->wValue)) { case UF_ENDPOINT_HALT: goto tr_handle_set_halt; case UF_DEVICE_REMOTE_WAKEUP: goto tr_handle_set_wakeup; default: goto tr_stalled; } break; case UR_SYNCH_FRAME: goto tr_valid; /* nop */ default: goto tr_stalled; } break; case UT_READ_ENDPOINT: switch (req->bRequest) { case UR_GET_STATUS: goto tr_handle_get_ep_status; default: goto tr_stalled; } break; case UT_WRITE_INTERFACE: switch (req->bRequest) { case UR_SET_INTERFACE: goto tr_handle_set_interface; case UR_CLEAR_FEATURE: goto tr_valid; /* nop */ case UR_SET_FEATURE: default: goto tr_stalled; } break; case UT_READ_INTERFACE: switch (req->bRequest) { case UR_GET_INTERFACE: goto tr_handle_get_interface; case UR_GET_STATUS: goto tr_handle_get_iface_status; default: goto tr_stalled; } break; case UT_WRITE_CLASS_INTERFACE: case UT_WRITE_VENDOR_INTERFACE: /* XXX forward */ break; case UT_READ_CLASS_INTERFACE: case UT_READ_VENDOR_INTERFACE: /* XXX forward */ break; case UT_WRITE_CLASS_DEVICE: switch (req->bRequest) { case UR_CLEAR_FEATURE: goto tr_valid; case UR_SET_DESCRIPTOR: case UR_SET_FEATURE: break; default: goto tr_stalled; } break; case UT_WRITE_CLASS_OTHER: switch (req->bRequest) { case UR_CLEAR_FEATURE: goto tr_handle_clear_port_feature; case UR_SET_FEATURE: goto tr_handle_set_port_feature; case UR_CLEAR_TT_BUFFER: case UR_RESET_TT: case UR_STOP_TT: goto tr_valid; default: goto tr_stalled; } break; case UT_READ_CLASS_OTHER: switch (req->bRequest) { case UR_GET_TT_STATE: goto tr_handle_get_tt_state; case UR_GET_STATUS: goto tr_handle_get_port_status; default: goto tr_stalled; } break; case UT_READ_CLASS_DEVICE: switch (req->bRequest) { case UR_GET_DESCRIPTOR: goto tr_handle_get_class_descriptor; case UR_GET_STATUS: goto tr_handle_get_class_status; default: goto tr_stalled; } break; default: goto tr_stalled; } goto tr_valid; tr_handle_get_descriptor: switch (value >> 8) { case UDESC_DEVICE: if (value & 0xff) { goto tr_stalled; } len = sizeof(uss820dci_devd); ptr = (const void *)&uss820dci_devd; goto tr_valid; case UDESC_DEVICE_QUALIFIER: if (value & 0xff) { goto tr_stalled; } len = sizeof(uss820dci_odevd); ptr = (const void *)&uss820dci_odevd; goto tr_valid; case UDESC_CONFIG: if (value & 0xff) { goto tr_stalled; } len = sizeof(uss820dci_confd); ptr = (const void *)&uss820dci_confd; goto tr_valid; case UDESC_STRING: switch (value & 0xff) { case 0: /* Language table */ len = sizeof(usb_string_lang_en); ptr = (const void *)&usb_string_lang_en; goto tr_valid; case 1: /* Vendor */ len = sizeof(uss820dci_vendor); ptr = (const void *)&uss820dci_vendor; goto tr_valid; case 2: /* Product */ len = sizeof(uss820dci_product); ptr = (const void *)&uss820dci_product; goto tr_valid; default: break; } break; default: goto tr_stalled; } goto tr_stalled; tr_handle_get_config: len = 1; sc->sc_hub_temp.wValue[0] = sc->sc_conf; goto tr_valid; tr_handle_get_status: len = 2; USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); goto tr_valid; tr_handle_set_address: if (value & 0xFF00) { goto tr_stalled; } sc->sc_rt_addr = value; goto tr_valid; tr_handle_set_config: if (value >= 2) { goto tr_stalled; } sc->sc_conf = value; goto tr_valid; tr_handle_get_interface: len = 1; sc->sc_hub_temp.wValue[0] = 0; goto tr_valid; tr_handle_get_tt_state: tr_handle_get_class_status: tr_handle_get_iface_status: tr_handle_get_ep_status: len = 2; USETW(sc->sc_hub_temp.wValue, 0); goto tr_valid; tr_handle_set_halt: tr_handle_set_interface: tr_handle_set_wakeup: tr_handle_clear_wakeup: tr_handle_clear_halt: goto tr_valid; tr_handle_clear_port_feature: if (index != 1) { goto tr_stalled; } DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); switch (value) { case UHF_PORT_SUSPEND: uss820dci_wakeup_peer(sc); break; case UHF_PORT_ENABLE: sc->sc_flags.port_enabled = 0; break; case UHF_PORT_TEST: case UHF_PORT_INDICATOR: case UHF_C_PORT_ENABLE: case UHF_C_PORT_OVER_CURRENT: case UHF_C_PORT_RESET: /* nops */ break; case UHF_PORT_POWER: sc->sc_flags.port_powered = 0; uss820dci_pull_down(sc); break; case UHF_C_PORT_CONNECTION: sc->sc_flags.change_connect = 0; break; case UHF_C_PORT_SUSPEND: sc->sc_flags.change_suspend = 0; break; default: err = USB_ERR_IOERROR; goto done; } goto tr_valid; tr_handle_set_port_feature: if (index != 1) { goto tr_stalled; } DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); switch (value) { case UHF_PORT_ENABLE: sc->sc_flags.port_enabled = 1; break; case UHF_PORT_SUSPEND: case UHF_PORT_RESET: case UHF_PORT_TEST: case UHF_PORT_INDICATOR: /* nops */ break; case UHF_PORT_POWER: sc->sc_flags.port_powered = 1; break; default: err = USB_ERR_IOERROR; goto done; } goto tr_valid; tr_handle_get_port_status: DPRINTFN(9, "UR_GET_PORT_STATUS\n"); if (index != 1) { goto tr_stalled; } if (sc->sc_flags.status_vbus) { uss820dci_pull_up(sc); } else { uss820dci_pull_down(sc); } /* Select FULL-speed and Device Side Mode */ value = UPS_PORT_MODE_DEVICE; if (sc->sc_flags.port_powered) { value |= UPS_PORT_POWER; } if (sc->sc_flags.port_enabled) { value |= UPS_PORT_ENABLED; } if (sc->sc_flags.status_vbus && sc->sc_flags.status_bus_reset) { value |= UPS_CURRENT_CONNECT_STATUS; } if (sc->sc_flags.status_suspend) { value |= UPS_SUSPEND; } USETW(sc->sc_hub_temp.ps.wPortStatus, value); value = 0; if (sc->sc_flags.change_connect) { value |= UPS_C_CONNECT_STATUS; } if (sc->sc_flags.change_suspend) { value |= UPS_C_SUSPEND; } USETW(sc->sc_hub_temp.ps.wPortChange, value); len = sizeof(sc->sc_hub_temp.ps); goto tr_valid; tr_handle_get_class_descriptor: if (value & 0xFF) { goto tr_stalled; } ptr = (const void *)&uss820dci_hubd; len = sizeof(uss820dci_hubd); goto tr_valid; tr_stalled: err = USB_ERR_STALLED; tr_valid: done: *plength = len; *pptr = ptr; return (err); } static void uss820dci_xfer_setup(struct usb_setup_params *parm) { const struct usb_hw_ep_profile *pf; struct uss820dci_softc *sc; struct usb_xfer *xfer; void *last_obj; uint32_t ntd; uint32_t n; uint8_t ep_no; sc = USS820_DCI_BUS2SC(parm->udev->bus); xfer = parm->curr_xfer; /* * NOTE: This driver does not use any of the parameters that * are computed from the following values. Just set some * reasonable dummies: */ parm->hc_max_packet_size = 0x500; parm->hc_max_packet_count = 1; parm->hc_max_frame_size = 0x500; usbd_transfer_setup_sub(parm); /* * compute maximum number of TDs */ if (parm->methods == &uss820dci_device_ctrl_methods) { ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; } else if (parm->methods == &uss820dci_device_bulk_methods) { ntd = xfer->nframes + 1 /* SYNC */ ; } else if (parm->methods == &uss820dci_device_intr_methods) { ntd = xfer->nframes + 1 /* SYNC */ ; } else if (parm->methods == &uss820dci_device_isoc_fs_methods) { ntd = xfer->nframes + 1 /* SYNC */ ; } else { ntd = 0; } /* * check if "usbd_transfer_setup_sub" set an error */ if (parm->err) { return; } /* * allocate transfer descriptors */ last_obj = NULL; /* * get profile stuff */ if (ntd) { ep_no = xfer->endpointno & UE_ADDR; uss820dci_get_hw_ep_profile(parm->udev, &pf, ep_no); if (pf == NULL) { /* should not happen */ parm->err = USB_ERR_INVAL; return; } } else { ep_no = 0; pf = NULL; } /* align data */ parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); for (n = 0; n != ntd; n++) { struct uss820dci_td *td; if (parm->buf) { td = USB_ADD_BYTES(parm->buf, parm->size[0]); /* init TD */ td->max_packet_size = xfer->max_packet_size; td->ep_index = ep_no; if (pf->support_multi_buffer && (parm->methods != &uss820dci_device_ctrl_methods)) { td->support_multi_buffer = 1; } td->obj_next = last_obj; last_obj = td; } parm->size[0] += sizeof(*td); } xfer->td_start[0] = last_obj; } static void uss820dci_xfer_unsetup(struct usb_xfer *xfer) { return; } static void uss820dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, struct usb_endpoint *ep) { struct uss820dci_softc *sc = USS820_DCI_BUS2SC(udev->bus); DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode, sc->sc_rt_addr); if (udev->device_index != sc->sc_rt_addr) { if (udev->speed != USB_SPEED_FULL) { /* not supported */ return; } switch (edesc->bmAttributes & UE_XFERTYPE) { case UE_CONTROL: ep->methods = &uss820dci_device_ctrl_methods; break; case UE_INTERRUPT: ep->methods = &uss820dci_device_intr_methods; break; case UE_ISOCHRONOUS: ep->methods = &uss820dci_device_isoc_fs_methods; break; case UE_BULK: ep->methods = &uss820dci_device_bulk_methods; break; default: /* do nothing */ break; } } } static void uss820dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) { struct uss820dci_softc *sc = USS820_DCI_BUS2SC(bus); switch (state) { case USB_HW_POWER_SUSPEND: uss820dci_suspend(sc); break; case USB_HW_POWER_SHUTDOWN: uss820dci_uninit(sc); break; case USB_HW_POWER_RESUME: uss820dci_resume(sc); break; default: break; } } static const struct usb_bus_methods uss820dci_bus_methods = { .endpoint_init = &uss820dci_ep_init, .xfer_setup = &uss820dci_xfer_setup, .xfer_unsetup = &uss820dci_xfer_unsetup, .get_hw_ep_profile = &uss820dci_get_hw_ep_profile, .xfer_stall = &uss820dci_xfer_stall, .set_stall = &uss820dci_set_stall, .clear_stall = &uss820dci_clear_stall, .roothub_exec = &uss820dci_roothub_exec, .xfer_poll = &uss820dci_do_poll, .set_hw_power_sleep = uss820dci_set_hw_power_sleep, }; diff --git a/sys/dev/usb/controller/xhci.c b/sys/dev/usb/controller/xhci.c index 0b0d9a7dc7be..febb5f3d82cb 100644 --- a/sys/dev/usb/controller/xhci.c +++ b/sys/dev/usb/controller/xhci.c @@ -1,4332 +1,4332 @@ /* $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. * * The XHCI 1.0 spec can be found at * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf * and the USB 3.0 spec at * http://www.usb.org/developers/docs/usb_30_spec_060910.zip */ /* * A few words about the design implementation: This driver emulates * the concept about TDs which is found in EHCI specification. This * way we achieve that the USB controller drivers look similar to * eachother which makes it easier to understand the code. */ #ifdef USB_GLOBAL_INCLUDE_FILE #include USB_GLOBAL_INCLUDE_FILE #else #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define USB_DEBUG_VAR xhcidebug #include #include #include #include #include #include #include #include #include #include #endif /* USB_GLOBAL_INCLUDE_FILE */ #include #include #define XHCI_BUS2SC(bus) \ __containerof(bus, struct xhci_softc, sc_bus) #define XHCI_GET_CTX(sc, which, field, ptr) \ ((sc)->sc_ctx_is_64_byte ? \ &((struct which##64 *)(ptr))->field.ctx : \ &((struct which *)(ptr))->field) static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, "USB XHCI"); static int xhcistreams; SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, &xhcistreams, 0, "Set to enable streams mode support"); static int xhcictlquirk = 1; SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN, &xhcictlquirk, 0, "Set to enable control endpoint quirk"); #ifdef USB_DEBUG static int xhcidebug; static int xhciroute; static int xhcipolling; static int xhcidma32; static int xhcictlstep; SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, &xhcidebug, 0, "Debug level"); SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN, &xhcictlstep, 0, "Set to enable control endpoint status stage stepping"); #else #define xhciroute 0 #define xhcidma32 0 #define xhcictlstep 0 #endif #define XHCI_INTR_ENDPT 1 struct xhci_std_temp { struct xhci_softc *sc; struct usb_page_cache *pc; struct xhci_td *td; struct xhci_td *td_next; uint32_t len; uint32_t offset; uint32_t max_packet_size; uint32_t average; uint32_t isoc_frame; uint16_t isoc_delta; uint8_t shortpkt; uint8_t multishort; uint8_t last_frame; uint8_t trb_type; uint8_t direction; uint8_t tbc; uint8_t tlbpc; uint8_t step_td; uint8_t do_isoc_sync; }; static void xhci_do_poll(struct usb_bus *); static void xhci_device_done(struct usb_xfer *, usb_error_t); static void xhci_root_intr(struct xhci_softc *); static void xhci_free_device_ext(struct usb_device *); static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, struct usb_endpoint_descriptor *); static usb_proc_callback_t xhci_configure_msg; static usb_error_t xhci_configure_device(struct usb_device *); static usb_error_t xhci_configure_endpoint(struct usb_device *, struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, uint8_t); static usb_error_t xhci_configure_mask(struct usb_device *, uint32_t, uint8_t); static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, uint64_t, uint8_t); static void xhci_endpoint_doorbell(struct usb_xfer *); static const struct usb_bus_methods xhci_bus_methods; #ifdef USB_DEBUG static void xhci_dump_trb(struct xhci_trb *trb) { DPRINTFN(5, "trb = %p\n", trb); DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); } static void xhci_dump_endpoint(struct xhci_endp_ctx *pep) { DPRINTFN(5, "pep = %p\n", pep); DPRINTFN(5, "dwEpCtx0=0x%08x\n", le32toh(pep->dwEpCtx0)); DPRINTFN(5, "dwEpCtx1=0x%08x\n", le32toh(pep->dwEpCtx1)); DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)le64toh(pep->qwEpCtx2)); DPRINTFN(5, "dwEpCtx4=0x%08x\n", le32toh(pep->dwEpCtx4)); DPRINTFN(5, "dwEpCtx5=0x%08x\n", le32toh(pep->dwEpCtx5)); DPRINTFN(5, "dwEpCtx6=0x%08x\n", le32toh(pep->dwEpCtx6)); DPRINTFN(5, "dwEpCtx7=0x%08x\n", le32toh(pep->dwEpCtx7)); } static void xhci_dump_device(struct xhci_slot_ctx *psl) { DPRINTFN(5, "psl = %p\n", psl); DPRINTFN(5, "dwSctx0=0x%08x\n", le32toh(psl->dwSctx0)); DPRINTFN(5, "dwSctx1=0x%08x\n", le32toh(psl->dwSctx1)); DPRINTFN(5, "dwSctx2=0x%08x\n", le32toh(psl->dwSctx2)); DPRINTFN(5, "dwSctx3=0x%08x\n", le32toh(psl->dwSctx3)); } #endif uint8_t xhci_use_polling(void) { #ifdef USB_DEBUG return (xhcipolling != 0); #else return (0); #endif } static void xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) { struct xhci_softc *sc = XHCI_BUS2SC(bus); uint16_t i; cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); for (i = 0; i != sc->sc_noscratch; i++) { cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); } } static int xhci_reset_command_queue_locked(struct xhci_softc *sc) { struct usb_page_search buf_res; struct xhci_hw_root *phwr; uint64_t addr; uint32_t temp; DPRINTF("\n"); temp = XREAD4(sc, oper, XHCI_CRCR_LO); if (temp & XHCI_CRCR_LO_CRR) { DPRINTF("Command ring running\n"); temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); /* * Try to abort the last command as per section * 4.6.1.2 "Aborting a Command" of the XHCI * specification: */ /* stop and cancel */ XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); XWRITE4(sc, oper, XHCI_CRCR_HI, 0); XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); XWRITE4(sc, oper, XHCI_CRCR_HI, 0); /* wait 250ms */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); /* check if command ring is still running */ temp = XREAD4(sc, oper, XHCI_CRCR_LO); if (temp & XHCI_CRCR_LO_CRR) { DPRINTF("Comand ring still running\n"); return (USB_ERR_IOERROR); } } /* reset command ring */ sc->sc_command_ccs = 1; sc->sc_command_idx = 0; usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); /* set up command ring control base address */ addr = buf_res.physaddr; phwr = buf_res.buffer; - addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; + addr += __offsetof(struct xhci_hw_root, hwr_commands[0]); DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); usb_pc_cpu_flush(&sc->sc_hw.root_pc); XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); return (0); } usb_error_t xhci_start_controller(struct xhci_softc *sc) { struct usb_page_search buf_res; struct xhci_hw_root *phwr; struct xhci_dev_ctx_addr *pdctxa; usb_error_t err; uint64_t addr; uint32_t temp; uint16_t i; DPRINTF("\n"); sc->sc_event_ccs = 1; sc->sc_event_idx = 0; sc->sc_command_ccs = 1; sc->sc_command_idx = 0; err = xhci_reset_controller(sc); if (err) return (err); /* set up number of device slots */ DPRINTF("CONFIG=0x%08x -> 0x%08x\n", XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); temp = XREAD4(sc, oper, XHCI_USBSTS); /* clear interrupts */ XWRITE4(sc, oper, XHCI_USBSTS, temp); /* disable all device notifications */ XWRITE4(sc, oper, XHCI_DNCTRL, 0); /* set up device context base address */ usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); pdctxa = buf_res.buffer; memset(pdctxa, 0, sizeof(*pdctxa)); addr = buf_res.physaddr; - addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; + addr += __offsetof(struct xhci_dev_ctx_addr, qwSpBufPtr[0]); /* slot 0 points to the table of scratchpad pointers */ pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); for (i = 0; i != sc->sc_noscratch; i++) { struct usb_page_search buf_scp; usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); } addr = buf_res.physaddr; XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); /* set up event table size */ DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); /* set up interrupt rate */ XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); phwr = buf_res.buffer; addr = buf_res.physaddr; - addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; + addr += __offsetof(struct xhci_hw_root, hwr_events[0]); /* reset hardware root structure */ memset(phwr, 0, sizeof(*phwr)); phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); /* * PR 237666: * * According to the XHCI specification, the XWRITE4's to * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the * qwEvrsTablePtr and dwEvrsTableSize values above at that * time, as the XHCI initializes its event ring support. This * is before the event ring starts to pay attention to the * RUN/STOP bit. Thus, make sure the values are observable to * the XHCI before that point. */ usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); addr = buf_res.physaddr; DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); /* set up interrupter registers */ temp = XREAD4(sc, runt, XHCI_IMAN(0)); temp |= XHCI_IMAN_INTR_ENA; XWRITE4(sc, runt, XHCI_IMAN(0), temp); /* set up command ring control base address */ addr = buf_res.physaddr; - addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; + addr += __offsetof(struct xhci_hw_root, hwr_commands[0]); DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); /* Go! */ XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | XHCI_CMD_INTE | XHCI_CMD_HSEE); for (i = 0; i != 100; i++) { usb_pause_mtx(NULL, hz / 100); temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; if (!temp) break; } if (temp) { XWRITE4(sc, oper, XHCI_USBCMD, 0); device_printf(sc->sc_bus.parent, "Run timeout.\n"); return (USB_ERR_IOERROR); } /* catch any lost interrupts */ xhci_do_poll(&sc->sc_bus); if (sc->sc_port_route != NULL) { /* Route all ports to the XHCI by default */ sc->sc_port_route(sc->sc_bus.parent, ~xhciroute, xhciroute); } return (0); } usb_error_t xhci_halt_controller(struct xhci_softc *sc) { uint32_t temp; uint16_t i; DPRINTF("\n"); sc->sc_capa_off = 0; sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; /* Halt controller */ XWRITE4(sc, oper, XHCI_USBCMD, 0); for (i = 0; i != 100; i++) { usb_pause_mtx(NULL, hz / 100); temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; if (temp) break; } if (!temp) { device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); return (USB_ERR_IOERROR); } return (0); } usb_error_t xhci_reset_controller(struct xhci_softc *sc) { uint32_t temp = 0; uint16_t i; DPRINTF("\n"); /* Reset controller */ XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); for (i = 0; i != 100; i++) { usb_pause_mtx(NULL, hz / 100); temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); if (!temp) break; } if (temp) { device_printf(sc->sc_bus.parent, "Controller " "reset timeout.\n"); return (USB_ERR_IOERROR); } return (0); } usb_error_t xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) { uint32_t temp; DPRINTF("\n"); /* initialize some bus fields */ sc->sc_bus.parent = self; /* set the bus revision */ sc->sc_bus.usbrev = USB_REV_3_0; /* set up the bus struct */ sc->sc_bus.methods = &xhci_bus_methods; /* set up devices array */ sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = XHCI_MAX_DEVICES; /* set default cycle state in case of early interrupts */ sc->sc_event_ccs = 1; sc->sc_command_ccs = 1; /* set up bus space offsets */ sc->sc_capa_off = 0; sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { device_printf(sc->sc_bus.parent, "Controller does " "not support 4K page size.\n"); return (ENXIO); } temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); DPRINTF("HCS0 = 0x%08x\n", temp); /* set up context size */ if (XHCI_HCS0_CSZ(temp)) { sc->sc_ctx_is_64_byte = 1; } else { sc->sc_ctx_is_64_byte = 0; } /* get DMA bits */ sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && xhcidma32 == 0 && dma32 == 0) ? 64 : 32; device_printf(self, "%d bytes context size, %d-bit DMA\n", sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); /* enable 64Kbyte control endpoint quirk */ sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0); temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); /* get number of device slots */ sc->sc_noport = XHCI_HCS1_N_PORTS(temp); if (sc->sc_noport == 0) { device_printf(sc->sc_bus.parent, "Invalid number " "of ports: %u\n", sc->sc_noport); return (ENXIO); } sc->sc_noport = sc->sc_noport; sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); DPRINTF("Max slots: %u\n", sc->sc_noslot); if (sc->sc_noslot > XHCI_MAX_DEVICES) sc->sc_noslot = XHCI_MAX_DEVICES; temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); DPRINTF("HCS2=0x%08x\n", temp); /* get isochronous scheduling threshold */ sc->sc_ist = XHCI_HCS2_IST(temp); /* get number of scratchpads */ sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { device_printf(sc->sc_bus.parent, "XHCI request " "too many scratchpads\n"); return (ENOMEM); } DPRINTF("Max scratch: %u\n", sc->sc_noscratch); /* get event table size */ sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); if (sc->sc_erst_max > XHCI_MAX_RSEG) sc->sc_erst_max = XHCI_MAX_RSEG; temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); /* get maximum exit latency */ sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + XHCI_HCS3_U2_DEL(temp) + 250 /* us */; /* Check if we should use the default IMOD value. */ if (sc->sc_imod_default == 0) sc->sc_imod_default = XHCI_IMOD_DEFAULT; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { return (ENOMEM); } /* set up command queue mutex and condition varible */ cv_init(&sc->sc_cmd_cv, "CMDQ"); sx_init(&sc->sc_cmd_sx, "CMDQ lock"); sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; sc->sc_config_msg[0].bus = &sc->sc_bus; sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; sc->sc_config_msg[1].bus = &sc->sc_bus; return (0); } void xhci_uninit(struct xhci_softc *sc) { /* * NOTE: At this point the control transfer process is gone * and "xhci_configure_msg" is no longer called. Consequently * waiting for the configuration messages to complete is not * needed. */ usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); cv_destroy(&sc->sc_cmd_cv); sx_destroy(&sc->sc_cmd_sx); } static void xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) { struct xhci_softc *sc = XHCI_BUS2SC(bus); switch (state) { case USB_HW_POWER_SUSPEND: DPRINTF("Stopping the XHCI\n"); xhci_halt_controller(sc); xhci_reset_controller(sc); break; case USB_HW_POWER_SHUTDOWN: DPRINTF("Stopping the XHCI\n"); xhci_halt_controller(sc); xhci_reset_controller(sc); break; case USB_HW_POWER_RESUME: DPRINTF("Starting the XHCI\n"); xhci_start_controller(sc); break; default: break; } } static usb_error_t xhci_generic_done_sub(struct usb_xfer *xfer) { struct xhci_td *td; struct xhci_td *td_alt_next; uint32_t len; uint8_t status; td = xfer->td_transfer_cache; td_alt_next = td->alt_next; if (xfer->aframes != xfer->nframes) usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); while (1) { usb_pc_cpu_invalidate(td->page_cache); status = td->status; len = td->remainder; DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", xfer, (unsigned int)xfer->aframes, (unsigned int)xfer->nframes, (unsigned int)len, (unsigned int)td->len, (unsigned int)status); /* * Verify the status length and * add the length to "frlengths[]": */ if (len > td->len) { /* should not happen */ DPRINTF("Invalid status length, " "0x%04x/0x%04x bytes\n", len, td->len); status = XHCI_TRB_ERROR_LENGTH; } else if (xfer->aframes != xfer->nframes) { xfer->frlengths[xfer->aframes] += td->len - len; } /* Check for last transfer */ if (((void *)td) == xfer->td_transfer_last) { td = NULL; break; } /* Check for transfer error */ if (status != XHCI_TRB_ERROR_SHORT_PKT && status != XHCI_TRB_ERROR_SUCCESS) { /* the transfer is finished */ td = NULL; break; } /* Check for short transfer */ if (len > 0) { if (xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr || xfer->flags_int.control_xfr) { /* follow alt next */ td = td->alt_next; } else { /* the transfer is finished */ td = NULL; } break; } td = td->obj_next; if (td->alt_next != td_alt_next) { /* this USB frame is complete */ break; } } /* update transfer cache */ xfer->td_transfer_cache = td; return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : (status != XHCI_TRB_ERROR_SHORT_PKT && status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : USB_ERR_NORMAL_COMPLETION); } static void xhci_generic_done(struct usb_xfer *xfer) { usb_error_t err = 0; DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", xfer, xfer->endpoint); /* reset scanner */ xfer->td_transfer_cache = xfer->td_transfer_first; if (xfer->flags_int.control_xfr) { if (xfer->flags_int.control_hdr) err = xhci_generic_done_sub(xfer); xfer->aframes = 1; if (xfer->td_transfer_cache == NULL) goto done; } while (xfer->aframes != xfer->nframes) { err = xhci_generic_done_sub(xfer); xfer->aframes++; if (xfer->td_transfer_cache == NULL) goto done; } if (xfer->flags_int.control_xfr && !xfer->flags_int.control_act) err = xhci_generic_done_sub(xfer); done: /* transfer is complete */ xhci_device_done(xfer, err); } static void xhci_activate_transfer(struct usb_xfer *xfer) { struct xhci_td *td; td = xfer->td_transfer_cache; usb_pc_cpu_invalidate(td->page_cache); if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { /* activate the transfer */ td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); usb_pc_cpu_flush(td->page_cache); xhci_endpoint_doorbell(xfer); } } static void xhci_skip_transfer(struct usb_xfer *xfer) { struct xhci_td *td; struct xhci_td *td_last; td = xfer->td_transfer_cache; td_last = xfer->td_transfer_last; td = td->alt_next; usb_pc_cpu_invalidate(td->page_cache); if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { usb_pc_cpu_invalidate(td_last->page_cache); /* copy LINK TRB to current waiting location */ td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; usb_pc_cpu_flush(td->page_cache); td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; usb_pc_cpu_flush(td->page_cache); xhci_endpoint_doorbell(xfer); } } /*------------------------------------------------------------------------* * xhci_check_transfer *------------------------------------------------------------------------*/ static void xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) { struct xhci_endpoint_ext *pepext; int64_t offset; uint64_t td_event; uint32_t temp; uint32_t remainder; uint16_t stream_id = 0; uint16_t i; uint8_t status; uint8_t halted; uint8_t epno; uint8_t index; /* decode TRB */ td_event = le64toh(trb->qwTrb0); temp = le32toh(trb->dwTrb2); remainder = XHCI_TRB_2_REM_GET(temp); status = XHCI_TRB_2_ERROR_GET(temp); temp = le32toh(trb->dwTrb3); epno = XHCI_TRB_3_EP_GET(temp); index = XHCI_TRB_3_SLOT_GET(temp); /* check if error means halted */ halted = (status != XHCI_TRB_ERROR_SHORT_PKT && status != XHCI_TRB_ERROR_SUCCESS); DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", index, epno, remainder, status); if (index > sc->sc_noslot) { DPRINTF("Invalid slot.\n"); return; } if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { DPRINTF("Invalid endpoint.\n"); return; } pepext = &sc->sc_hw.devs[index].endp[epno]; /* try to find the USB transfer that generated the event */ for (i = 0;; i++) { struct usb_xfer *xfer; struct xhci_td *td; if (i == (XHCI_MAX_TRANSFERS - 1)) { if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS || stream_id == (XHCI_MAX_STREAMS - 1)) break; stream_id++; i = 0; DPRINTFN(5, "stream_id=%u\n", stream_id); } xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; if (xfer == NULL) continue; td = xfer->td_transfer_cache; DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", (long long)td_event, (long long)td->td_self, (long long)td->td_self + sizeof(td->td_trb)); /* * NOTE: Some XHCI implementations might not trigger * an event on the last LINK TRB so we need to * consider both the last and second last event * address as conditions for a successful transfer. * * NOTE: We assume that the XHCI will only trigger one * event per chain of TRBs. */ offset = td_event - td->td_self; if (offset >= 0 && offset < (int64_t)sizeof(td->td_trb)) { usb_pc_cpu_invalidate(td->page_cache); /* compute rest of remainder, if any */ for (i = (offset / 16) + 1; i < td->ntrb; i++) { temp = le32toh(td->td_trb[i].dwTrb2); remainder += XHCI_TRB_2_BYTES_GET(temp); } DPRINTFN(5, "New remainder: %u\n", remainder); /* clear isochronous transfer errors */ if (xfer->flags_int.isochronous_xfr) { if (halted) { halted = 0; status = XHCI_TRB_ERROR_SUCCESS; remainder = td->len; } } /* "td->remainder" is verified later */ td->remainder = remainder; td->status = status; usb_pc_cpu_flush(td->page_cache); /* * 1) Last transfer descriptor makes the * transfer done */ if (((void *)td) == xfer->td_transfer_last) { DPRINTF("TD is last\n"); xhci_generic_done(xfer); break; } /* * 2) Any kind of error makes the transfer * done */ if (halted) { DPRINTF("TD has I/O error\n"); xhci_generic_done(xfer); break; } /* * 3) If there is no alternate next transfer, * a short packet also makes the transfer done */ if (td->remainder > 0) { if (td->alt_next == NULL) { DPRINTF( "short TD has no alternate next\n"); xhci_generic_done(xfer); break; } DPRINTF("TD has short pkt\n"); if (xfer->flags_int.short_frames_ok || xfer->flags_int.isochronous_xfr || xfer->flags_int.control_xfr) { /* follow the alt next */ xfer->td_transfer_cache = td->alt_next; xhci_activate_transfer(xfer); break; } xhci_skip_transfer(xfer); xhci_generic_done(xfer); break; } /* * 4) Transfer complete - go to next TD */ DPRINTF("Following next TD\n"); xfer->td_transfer_cache = td->obj_next; xhci_activate_transfer(xfer); break; /* there should only be one match */ } } } static int xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) { if (sc->sc_cmd_addr == trb->qwTrb0) { DPRINTF("Received command event\n"); sc->sc_cmd_result[0] = trb->dwTrb2; sc->sc_cmd_result[1] = trb->dwTrb3; cv_signal(&sc->sc_cmd_cv); return (1); /* command match */ } return (0); } static int xhci_interrupt_poll(struct xhci_softc *sc) { struct usb_page_search buf_res; struct xhci_hw_root *phwr; uint64_t addr; uint32_t temp; int retval = 0; uint16_t i; uint8_t event; uint8_t j; uint8_t k; uint8_t t; usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); phwr = buf_res.buffer; /* Receive any events */ usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); i = sc->sc_event_idx; j = sc->sc_event_ccs; t = 2; while (1) { temp = le32toh(phwr->hwr_events[i].dwTrb3); k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; if (j != k) break; event = XHCI_TRB_3_TYPE_GET(temp); DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), (long)le32toh(phwr->hwr_events[i].dwTrb2), (long)le32toh(phwr->hwr_events[i].dwTrb3)); switch (event) { case XHCI_TRB_EVENT_TRANSFER: xhci_check_transfer(sc, &phwr->hwr_events[i]); break; case XHCI_TRB_EVENT_CMD_COMPLETE: retval |= xhci_check_command(sc, &phwr->hwr_events[i]); break; default: DPRINTF("Unhandled event = %u\n", event); break; } i++; if (i == XHCI_MAX_EVENTS) { i = 0; j ^= 1; /* check for timeout */ if (!--t) break; } } sc->sc_event_idx = i; sc->sc_event_ccs = j; /* * NOTE: The Event Ring Dequeue Pointer Register is 64-bit * latched. That means to activate the register we need to * write both the low and high double word of the 64-bit * register. */ addr = buf_res.physaddr; - addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; + addr += __offsetof(struct xhci_hw_root, hwr_events[i]); /* try to clear busy bit */ addr |= XHCI_ERDP_LO_BUSY; XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); return (retval); } static usb_error_t xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, uint16_t timeout_ms) { struct usb_page_search buf_res; struct xhci_hw_root *phwr; uint64_t addr; uint32_t temp; uint8_t i; uint8_t j; uint8_t timeout = 0; int err; XHCI_CMD_ASSERT_LOCKED(sc); /* get hardware root structure */ usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); phwr = buf_res.buffer; /* Queue command */ USB_BUS_LOCK(&sc->sc_bus); retry: i = sc->sc_command_idx; j = sc->sc_command_ccs; DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), (long long)le64toh(trb->qwTrb0), (long)le32toh(trb->dwTrb2), (long)le32toh(trb->dwTrb3)); phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; usb_pc_cpu_flush(&sc->sc_hw.root_pc); temp = trb->dwTrb3; if (j) temp |= htole32(XHCI_TRB_3_CYCLE_BIT); else temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); temp &= ~htole32(XHCI_TRB_3_TC_BIT); phwr->hwr_commands[i].dwTrb3 = temp; usb_pc_cpu_flush(&sc->sc_hw.root_pc); addr = buf_res.physaddr; - addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; + addr += __offsetof(struct xhci_hw_root, hwr_commands[i]); sc->sc_cmd_addr = htole64(addr); i++; if (i == (XHCI_MAX_COMMANDS - 1)) { if (j) { temp = htole32(XHCI_TRB_3_TC_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | XHCI_TRB_3_CYCLE_BIT); } else { temp = htole32(XHCI_TRB_3_TC_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); } phwr->hwr_commands[i].dwTrb3 = temp; usb_pc_cpu_flush(&sc->sc_hw.root_pc); i = 0; j ^= 1; } sc->sc_command_idx = i; sc->sc_command_ccs = j; XWRITE4(sc, door, XHCI_DOORBELL(0), 0); err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, USB_MS_TO_TICKS(timeout_ms)); /* * In some error cases event interrupts are not generated. * Poll one time to see if the command has completed. */ if (err != 0 && xhci_interrupt_poll(sc) != 0) { DPRINTF("Command was completed when polling\n"); err = 0; } if (err != 0) { DPRINTF("Command timeout!\n"); /* * After some weeks of continuous operation, it has * been observed that the ASMedia Technology, ASM1042 * SuperSpeed USB Host Controller can suddenly stop * accepting commands via the command queue. Try to * first reset the command queue. If that fails do a * host controller reset. */ if (timeout == 0 && xhci_reset_command_queue_locked(sc) == 0) { temp = le32toh(trb->dwTrb3); /* * Avoid infinite XHCI reset loops if the set * address command fails to respond due to a * non-enumerating device: */ if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && (temp & XHCI_TRB_3_BSR_BIT) == 0) { DPRINTF("Set address timeout\n"); } else { timeout = 1; goto retry; } } else { DPRINTF("Controller reset!\n"); usb_bus_reset_async_locked(&sc->sc_bus); } err = USB_ERR_TIMEOUT; trb->dwTrb2 = 0; trb->dwTrb3 = 0; } else { temp = le32toh(sc->sc_cmd_result[0]); if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) err = USB_ERR_IOERROR; trb->dwTrb2 = sc->sc_cmd_result[0]; trb->dwTrb3 = sc->sc_cmd_result[1]; } USB_BUS_UNLOCK(&sc->sc_bus); return (err); } #if 0 static usb_error_t xhci_cmd_nop(struct xhci_softc *sc) { struct xhci_trb trb; uint32_t temp; DPRINTF("\n"); trb.qwTrb0 = 0; trb.dwTrb2 = 0; temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); trb.dwTrb3 = htole32(temp); return (xhci_do_command(sc, &trb, 100 /* ms */)); } #endif static usb_error_t xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) { struct xhci_trb trb; uint32_t temp; usb_error_t err; DPRINTF("\n"); trb.qwTrb0 = 0; trb.dwTrb2 = 0; trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); err = xhci_do_command(sc, &trb, 100 /* ms */); if (err) goto done; temp = le32toh(trb.dwTrb3); *pslot = XHCI_TRB_3_SLOT_GET(temp); done: return (err); } static usb_error_t xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) { struct xhci_trb trb; uint32_t temp; DPRINTF("\n"); trb.qwTrb0 = 0; trb.dwTrb2 = 0; temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | XHCI_TRB_3_SLOT_SET(slot_id); trb.dwTrb3 = htole32(temp); return (xhci_do_command(sc, &trb, 100 /* ms */)); } static usb_error_t xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, uint8_t bsr, uint8_t slot_id) { struct xhci_trb trb; uint32_t temp; DPRINTF("\n"); trb.qwTrb0 = htole64(input_ctx); trb.dwTrb2 = 0; temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | XHCI_TRB_3_SLOT_SET(slot_id); if (bsr) temp |= XHCI_TRB_3_BSR_BIT; trb.dwTrb3 = htole32(temp); return (xhci_do_command(sc, &trb, 500 /* ms */)); } static usb_error_t xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) { struct usb_page_search buf_inp; struct usb_page_search buf_dev; struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); struct xhci_hw_dev *hdev; struct xhci_slot_ctx *slot; struct xhci_endpoint_ext *pepext; uint32_t temp; uint16_t mps; usb_error_t err; uint8_t index; /* the root HUB case is not handled here */ if (udev->parent_hub == NULL) return (USB_ERR_INVAL); index = udev->controller_slot_id; hdev = &sc->sc_hw.devs[index]; if (mtx != NULL) mtx_unlock(mtx); XHCI_CMD_LOCK(sc); switch (hdev->state) { case XHCI_ST_DEFAULT: case XHCI_ST_ENABLED: hdev->state = XHCI_ST_ENABLED; /* set configure mask to slot and EP0 */ xhci_configure_mask(udev, 3, 0); /* configure input slot context structure */ err = xhci_configure_device(udev); if (err != 0) { DPRINTF("Could not configure device\n"); break; } /* configure input endpoint context structure */ switch (udev->speed) { case USB_SPEED_LOW: case USB_SPEED_FULL: mps = 8; break; case USB_SPEED_HIGH: mps = 64; break; default: mps = 512; break; } pepext = xhci_get_endpoint_ext(udev, &udev->ctrl_ep_desc); /* ensure the control endpoint is setup again */ USB_BUS_LOCK(udev->bus); pepext->trb_halted = 1; pepext->trb_running = 0; USB_BUS_UNLOCK(udev->bus); err = xhci_configure_endpoint(udev, &udev->ctrl_ep_desc, pepext, 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); if (err != 0) { DPRINTF("Could not configure default endpoint\n"); break; } /* execute set address command */ usbd_get_page(&hdev->input_pc, 0, &buf_inp); err = xhci_cmd_set_address(sc, buf_inp.physaddr, (address == 0), index); if (err != 0) { temp = le32toh(sc->sc_cmd_result[0]); if (address == 0 && sc->sc_port_route != NULL && XHCI_TRB_2_ERROR_GET(temp) == XHCI_TRB_ERROR_PARAMETER) { /* LynxPoint XHCI - ports are not switchable */ /* Un-route all ports from the XHCI */ sc->sc_port_route(sc->sc_bus.parent, 0, ~0); } DPRINTF("Could not set address " "for slot %u.\n", index); if (address != 0) break; } /* update device address to new value */ usbd_get_page(&hdev->device_pc, 0, &buf_dev); slot = XHCI_GET_CTX(sc, xhci_dev_ctx, ctx_slot, buf_dev.buffer); usb_pc_cpu_invalidate(&hdev->device_pc); temp = le32toh(slot->dwSctx3); udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); /* update device state to new value */ if (address != 0) hdev->state = XHCI_ST_ADDRESSED; else hdev->state = XHCI_ST_DEFAULT; break; default: DPRINTF("Wrong state for set address.\n"); err = USB_ERR_IOERROR; break; } XHCI_CMD_UNLOCK(sc); if (mtx != NULL) mtx_lock(mtx); return (err); } static usb_error_t xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, uint8_t deconfigure, uint8_t slot_id) { struct xhci_trb trb; uint32_t temp; DPRINTF("\n"); trb.qwTrb0 = htole64(input_ctx); trb.dwTrb2 = 0; temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | XHCI_TRB_3_SLOT_SET(slot_id); if (deconfigure) temp |= XHCI_TRB_3_DCEP_BIT; trb.dwTrb3 = htole32(temp); return (xhci_do_command(sc, &trb, 100 /* ms */)); } static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, uint8_t slot_id) { struct xhci_trb trb; uint32_t temp; DPRINTF("\n"); trb.qwTrb0 = htole64(input_ctx); trb.dwTrb2 = 0; temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | XHCI_TRB_3_SLOT_SET(slot_id); trb.dwTrb3 = htole32(temp); return (xhci_do_command(sc, &trb, 100 /* ms */)); } static usb_error_t xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, uint8_t ep_id, uint8_t slot_id) { struct xhci_trb trb; uint32_t temp; DPRINTF("\n"); trb.qwTrb0 = 0; trb.dwTrb2 = 0; temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | XHCI_TRB_3_SLOT_SET(slot_id) | XHCI_TRB_3_EP_SET(ep_id); if (preserve) temp |= XHCI_TRB_3_PRSV_BIT; trb.dwTrb3 = htole32(temp); return (xhci_do_command(sc, &trb, 100 /* ms */)); } static usb_error_t xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) { struct xhci_trb trb; uint32_t temp; DPRINTF("\n"); trb.qwTrb0 = htole64(dequeue_ptr); temp = XHCI_TRB_2_STREAM_SET(stream_id); trb.dwTrb2 = htole32(temp); temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | XHCI_TRB_3_SLOT_SET(slot_id) | XHCI_TRB_3_EP_SET(ep_id); trb.dwTrb3 = htole32(temp); return (xhci_do_command(sc, &trb, 100 /* ms */)); } static usb_error_t xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, uint8_t ep_id, uint8_t slot_id) { struct xhci_trb trb; uint32_t temp; DPRINTF("\n"); trb.qwTrb0 = 0; trb.dwTrb2 = 0; temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | XHCI_TRB_3_SLOT_SET(slot_id) | XHCI_TRB_3_EP_SET(ep_id); if (suspend) temp |= XHCI_TRB_3_SUSP_EP_BIT; trb.dwTrb3 = htole32(temp); return (xhci_do_command(sc, &trb, 100 /* ms */)); } static usb_error_t xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) { struct xhci_trb trb; uint32_t temp; DPRINTF("\n"); trb.qwTrb0 = 0; trb.dwTrb2 = 0; temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | XHCI_TRB_3_SLOT_SET(slot_id); trb.dwTrb3 = htole32(temp); return (xhci_do_command(sc, &trb, 100 /* ms */)); } /*------------------------------------------------------------------------* * xhci_interrupt - XHCI interrupt handler *------------------------------------------------------------------------*/ void xhci_interrupt(struct xhci_softc *sc) { uint32_t status; uint32_t temp; USB_BUS_LOCK(&sc->sc_bus); status = XREAD4(sc, oper, XHCI_USBSTS); /* acknowledge interrupts, if any */ if (status != 0) { XWRITE4(sc, oper, XHCI_USBSTS, status); DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); } temp = XREAD4(sc, runt, XHCI_IMAN(0)); /* force clearing of pending interrupts */ if (temp & XHCI_IMAN_INTR_PEND) XWRITE4(sc, runt, XHCI_IMAN(0), temp); /* check for event(s) */ xhci_interrupt_poll(sc); if (status & (XHCI_STS_PCD | XHCI_STS_HCH | XHCI_STS_HSE | XHCI_STS_HCE)) { if (status & XHCI_STS_PCD) { xhci_root_intr(sc); } if (status & XHCI_STS_HCH) { printf("%s: host controller halted\n", __FUNCTION__); } if (status & XHCI_STS_HSE) { printf("%s: host system error\n", __FUNCTION__); } if (status & XHCI_STS_HCE) { printf("%s: host controller error\n", __FUNCTION__); } } USB_BUS_UNLOCK(&sc->sc_bus); } /*------------------------------------------------------------------------* * xhci_timeout - XHCI timeout handler *------------------------------------------------------------------------*/ static void xhci_timeout(void *arg) { struct usb_xfer *xfer = arg; DPRINTF("xfer=%p\n", xfer); USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); /* transfer is transferred */ xhci_device_done(xfer, USB_ERR_TIMEOUT); } static void xhci_do_poll(struct usb_bus *bus) { struct xhci_softc *sc = XHCI_BUS2SC(bus); USB_BUS_LOCK(&sc->sc_bus); xhci_interrupt_poll(sc); USB_BUS_UNLOCK(&sc->sc_bus); } static void xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) { struct usb_page_search buf_res; struct xhci_td *td; struct xhci_td *td_next; struct xhci_td *td_alt_next; struct xhci_td *td_first; uint32_t buf_offset; uint32_t average; uint32_t len_old; uint32_t npkt_off; uint32_t dword; uint8_t shortpkt_old; uint8_t precompute; uint8_t x; td_alt_next = NULL; buf_offset = 0; shortpkt_old = temp->shortpkt; len_old = temp->len; npkt_off = 0; precompute = 1; restart: td = temp->td; td_next = td_first = temp->td_next; while (1) { if (temp->len == 0) { if (temp->shortpkt) break; /* send a Zero Length Packet, ZLP, last */ temp->shortpkt = 1; average = 0; } else { average = temp->average; if (temp->len < average) { if (temp->len % temp->max_packet_size) { temp->shortpkt = 1; } average = temp->len; } } if (td_next == NULL) panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); /* get next TD */ td = td_next; td_next = td->obj_next; /* check if we are pre-computing */ if (precompute) { /* update remaining length */ temp->len -= average; continue; } /* fill out current TD */ td->len = average; td->remainder = 0; td->status = 0; /* update remaining length */ temp->len -= average; /* reset TRB index */ x = 0; if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { /* immediate data */ if (average > 8) average = 8; td->td_trb[0].qwTrb0 = 0; usbd_copy_out(temp->pc, temp->offset + buf_offset, (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, average); dword = XHCI_TRB_2_BYTES_SET(8) | XHCI_TRB_2_TDSZ_SET(0) | XHCI_TRB_2_IRQ_SET(0); td->td_trb[0].dwTrb2 = htole32(dword); dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; /* check wLength */ if (td->td_trb[0].qwTrb0 & htole64(XHCI_TRB_0_WLENGTH_MASK)) { if (td->td_trb[0].qwTrb0 & htole64(XHCI_TRB_0_DIR_IN_MASK)) dword |= XHCI_TRB_3_TRT_IN; else dword |= XHCI_TRB_3_TRT_OUT; } td->td_trb[0].dwTrb3 = htole32(dword); #ifdef USB_DEBUG xhci_dump_trb(&td->td_trb[x]); #endif x++; } else do { uint32_t npkt; /* fill out buffer pointers */ if (average == 0) { memset(&buf_res, 0, sizeof(buf_res)); } else { usbd_get_page(temp->pc, temp->offset + buf_offset, &buf_res); /* get length to end of page */ if (buf_res.length > average) buf_res.length = average; /* check for maximum length */ if (buf_res.length > XHCI_TD_PAGE_SIZE) buf_res.length = XHCI_TD_PAGE_SIZE; npkt_off += buf_res.length; } /* set up npkt */ npkt = howmany(len_old - npkt_off, temp->max_packet_size); if (npkt == 0) npkt = 1; else if (npkt > 31) npkt = 31; /* fill out TRB's */ td->td_trb[x].qwTrb0 = htole64((uint64_t)buf_res.physaddr); dword = XHCI_TRB_2_BYTES_SET(buf_res.length) | XHCI_TRB_2_TDSZ_SET(npkt) | XHCI_TRB_2_IRQ_SET(0); td->td_trb[x].dwTrb2 = htole32(dword); switch (temp->trb_type) { case XHCI_TRB_TYPE_ISOCH: dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TBC_SET(temp->tbc) | XHCI_TRB_3_TLBPC_SET(temp->tlbpc); if (td != td_first) { dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); } else if (temp->do_isoc_sync != 0) { temp->do_isoc_sync = 0; /* wait until "isoc_frame" */ dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); } else { /* start data transfer at next interval */ dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | XHCI_TRB_3_ISO_SIA_BIT; } if (temp->direction == UE_DIR_IN) dword |= XHCI_TRB_3_ISP_BIT; break; case XHCI_TRB_TYPE_DATA_STAGE: dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); if (temp->direction == UE_DIR_IN) dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; /* * Section 3.2.9 in the XHCI * specification about control * transfers says that we should use a * normal-TRB if there are more TRBs * extending the data-stage * TRB. Update the "trb_type". */ temp->trb_type = XHCI_TRB_TYPE_NORMAL; break; case XHCI_TRB_TYPE_STATUS_STAGE: dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); if (temp->direction == UE_DIR_IN) dword |= XHCI_TRB_3_DIR_IN; break; default: /* XHCI_TRB_TYPE_NORMAL */ dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); if (temp->direction == UE_DIR_IN) dword |= XHCI_TRB_3_ISP_BIT; break; } td->td_trb[x].dwTrb3 = htole32(dword); average -= buf_res.length; buf_offset += buf_res.length; #ifdef USB_DEBUG xhci_dump_trb(&td->td_trb[x]); #endif x++; } while (average != 0); td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); /* store number of data TRB's */ td->ntrb = x; DPRINTF("NTRB=%u\n", x); /* fill out link TRB */ if (td_next != NULL) { /* link the current TD with the next one */ td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); } else { /* this field will get updated later */ DPRINTF("NOLINK\n"); } dword = XHCI_TRB_2_IRQ_SET(0); td->td_trb[x].dwTrb2 = htole32(dword); dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | /* * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint * frame only receives a single short packet event * by setting the CHAIN bit in the LINK field. In * addition some XHCI controllers have problems * sending a ZLP unless the CHAIN-BIT is set in * the LINK TRB. */ XHCI_TRB_3_CHAIN_BIT; td->td_trb[x].dwTrb3 = htole32(dword); td->alt_next = td_alt_next; #ifdef USB_DEBUG xhci_dump_trb(&td->td_trb[x]); #endif usb_pc_cpu_flush(td->page_cache); } if (precompute) { precompute = 0; /* set up alt next pointer, if any */ if (temp->last_frame) { td_alt_next = NULL; } else { /* we use this field internally */ td_alt_next = td_next; } /* restore */ temp->shortpkt = shortpkt_old; temp->len = len_old; goto restart; } /* * Remove cycle bit from the first TRB if we are * stepping them: */ if (temp->step_td != 0) { td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); usb_pc_cpu_flush(td_first->page_cache); } /* clear TD SIZE to zero, hence this is the last TRB */ /* remove chain bit because this is the last data TRB in the chain */ td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); /* remove CHAIN-BIT from last LINK TRB */ td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); usb_pc_cpu_flush(td->page_cache); temp->td = td; temp->td_next = td_next; } static void xhci_setup_generic_chain(struct usb_xfer *xfer) { struct xhci_std_temp temp; struct xhci_td *td; uint32_t x; uint32_t y; uint8_t mult; temp.do_isoc_sync = 0; temp.step_td = 0; temp.tbc = 0; temp.tlbpc = 0; temp.average = xfer->max_hc_frame_size; temp.max_packet_size = xfer->max_packet_size; temp.sc = XHCI_BUS2SC(xfer->xroot->bus); temp.pc = NULL; temp.last_frame = 0; temp.offset = 0; temp.multishort = xfer->flags_int.isochronous_xfr || xfer->flags_int.control_xfr || xfer->flags_int.short_frames_ok; /* toggle the DMA set we are using */ xfer->flags_int.curr_dma_set ^= 1; /* get next DMA set */ td = xfer->td_start[xfer->flags_int.curr_dma_set]; temp.td = NULL; temp.td_next = td; xfer->td_transfer_first = td; xfer->td_transfer_cache = td; if (xfer->flags_int.isochronous_xfr) { uint8_t shift; /* compute multiplier for ISOCHRONOUS transfers */ mult = xfer->endpoint->ecomp ? UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) : 0; /* check for USB 2.0 multiplier */ if (mult == 0) { mult = (xfer->endpoint->edesc-> wMaxPacketSize[1] >> 3) & 3; } /* range check */ if (mult > 2) mult = 3; else mult++; x = XREAD4(temp.sc, runt, XHCI_MFINDEX); DPRINTF("MFINDEX=0x%08x IST=0x%x\n", x, temp.sc->sc_ist); switch (usbd_get_speed(xfer->xroot->udev)) { case USB_SPEED_FULL: shift = 3; temp.isoc_delta = 8; /* 1ms */ break; default: shift = usbd_xfer_get_fps_shift(xfer); temp.isoc_delta = 1U << shift; break; } /* Compute isochronous scheduling threshold. */ if (temp.sc->sc_ist & 8) y = (temp.sc->sc_ist & 7) << 3; else y = (temp.sc->sc_ist & 7); /* Range check the IST. */ if (y < 8) { y = 0; } else if (y > 15) { DPRINTFN(3, "IST(%d) is too big!\n", temp.sc->sc_ist); /* * The USB stack minimum isochronous transfer * size is typically 2x2 ms of payload. If the * IST makes is above 15 microframes, we have * an effective scheduling delay of more than * or equal to 2 milliseconds, which is too * much. */ y = 7; } else { /* * Subtract one millisecond, because the * generic code adds that to the latency. */ y -= 8; } if (usbd_xfer_get_isochronous_start_frame( xfer, x, y, 8, XHCI_MFINDEX_GET(-1), &temp.isoc_frame)) { /* Start isochronous transfer at specified time. */ temp.do_isoc_sync = 1; DPRINTFN(3, "start next=%d\n", temp.isoc_frame); } x = 0; temp.trb_type = XHCI_TRB_TYPE_ISOCH; } else if (xfer->flags_int.control_xfr) { /* check if we should prepend a setup message */ if (xfer->flags_int.control_hdr) { temp.len = xfer->frlengths[0]; temp.pc = xfer->frbuffers + 0; temp.shortpkt = temp.len ? 1 : 0; temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; temp.direction = 0; /* check for last frame */ if (xfer->nframes == 1) { /* no STATUS stage yet, SETUP is last */ if (xfer->flags_int.control_act) temp.last_frame = 1; } xhci_setup_generic_chain_sub(&temp); } x = 1; mult = 1; temp.isoc_delta = 0; temp.isoc_frame = 0; temp.trb_type = xfer->flags_int.control_did_data ? XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; } else { x = 0; mult = 1; temp.isoc_delta = 0; temp.isoc_frame = 0; temp.trb_type = XHCI_TRB_TYPE_NORMAL; } if (x != xfer->nframes) { /* set up page_cache pointer */ temp.pc = xfer->frbuffers + x; /* set endpoint direction */ temp.direction = UE_GET_DIR(xfer->endpointno); } while (x != xfer->nframes) { /* DATA0 / DATA1 message */ temp.len = xfer->frlengths[x]; temp.step_td = ((xfer->endpointno & UE_DIR_IN) && x != 0 && temp.multishort == 0); x++; if (x == xfer->nframes) { if (xfer->flags_int.control_xfr) { /* no STATUS stage yet, DATA is last */ if (xfer->flags_int.control_act) temp.last_frame = 1; } else { temp.last_frame = 1; } } if (temp.len == 0) { /* make sure that we send an USB packet */ temp.shortpkt = 0; temp.tbc = 0; temp.tlbpc = mult - 1; } else if (xfer->flags_int.isochronous_xfr) { uint8_t tdpc; /* * Isochronous transfers don't have short * packet termination: */ temp.shortpkt = 1; /* isochronous transfers have a transfer limit */ if (temp.len > xfer->max_frame_size) temp.len = xfer->max_frame_size; /* compute TD packet count */ tdpc = howmany(temp.len, xfer->max_packet_size); temp.tbc = howmany(tdpc, mult) - 1; temp.tlbpc = (tdpc % mult); if (temp.tlbpc == 0) temp.tlbpc = mult - 1; else temp.tlbpc--; } else { /* regular data transfer */ temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; } xhci_setup_generic_chain_sub(&temp); if (xfer->flags_int.isochronous_xfr) { temp.offset += xfer->frlengths[x - 1]; temp.isoc_frame += temp.isoc_delta; } else { /* get next Page Cache pointer */ temp.pc = xfer->frbuffers + x; } } /* check if we should append a status stage */ if (xfer->flags_int.control_xfr && !xfer->flags_int.control_act) { /* * Send a DATA1 message and invert the current * endpoint direction. */ if (xhcictlstep || temp.sc->sc_ctlstep) { /* * Some XHCI controllers will not delay the * status stage until the next SOF. Force this * behaviour to avoid failed control * transfers. */ temp.step_td = (xfer->nframes != 0); } else { temp.step_td = 0; } temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; temp.len = 0; temp.pc = NULL; temp.shortpkt = 0; temp.last_frame = 1; temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; xhci_setup_generic_chain_sub(&temp); } td = temp.td; /* must have at least one frame! */ xfer->td_transfer_last = td; DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); } static void xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) { struct usb_page_search buf_res; struct xhci_dev_ctx_addr *pdctxa; usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); pdctxa = buf_res.buffer; DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); } static usb_error_t xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); struct usb_page_search buf_inp; struct xhci_input_ctx *input; struct xhci_slot_ctx *slot; uint32_t temp; uint8_t index; uint8_t x; index = udev->controller_slot_id; usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); input = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_input, buf_inp.buffer); slot = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_slot, buf_inp.buffer); if (drop) { mask &= XHCI_INCTX_NON_CTRL_MASK; input->dwInCtx0 = htole32(mask); input->dwInCtx1 = htole32(0); } else { /* * Some hardware requires that we drop the endpoint * context before adding it again: */ input->dwInCtx0 = htole32(mask & XHCI_INCTX_NON_CTRL_MASK); /* Add new endpoint context */ input->dwInCtx1 = htole32(mask); /* find most significant set bit */ for (x = 31; x != 1; x--) { if (mask & (1 << x)) break; } /* adjust */ x--; /* figure out the maximum number of contexts */ if (x > sc->sc_hw.devs[index].context_num) sc->sc_hw.devs[index].context_num = x; else x = sc->sc_hw.devs[index].context_num; /* update number of contexts */ temp = le32toh(slot->dwSctx0); temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); slot->dwSctx0 = htole32(temp); } usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); return (0); } static usb_error_t xhci_configure_endpoint(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, uint16_t interval, uint8_t max_packet_count, uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size, uint8_t ep_mode) { struct usb_page_search buf_inp; struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); struct xhci_endp_ctx *endp; uint64_t ring_addr = pepext->physaddr; uint32_t temp; uint8_t index; uint8_t epno; uint8_t type; index = udev->controller_slot_id; usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); epno = edesc->bEndpointAddress; type = edesc->bmAttributes & UE_XFERTYPE; if (type == UE_CONTROL) epno |= UE_DIR_IN; epno = XHCI_EPNO2EPID(epno); if (epno == 0) return (USB_ERR_NO_PIPE); /* invalid */ if (max_packet_count == 0) return (USB_ERR_BAD_BUFSIZE); max_packet_count--; if (mult == 0) return (USB_ERR_BAD_BUFSIZE); endp = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_ep[epno - 1], buf_inp.buffer); /* store endpoint mode */ pepext->trb_ep_mode = ep_mode; /* store bMaxPacketSize for control endpoints */ pepext->trb_ep_maxp = edesc->wMaxPacketSize[0]; usb_pc_cpu_flush(pepext->page_cache); if (ep_mode == USB_EP_MODE_STREAMS) { temp = XHCI_EPCTX_0_EPSTATE_SET(0) | XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | XHCI_EPCTX_0_LSA_SET(1); ring_addr += sizeof(struct xhci_trb) * XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; } else { temp = XHCI_EPCTX_0_EPSTATE_SET(0) | XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | XHCI_EPCTX_0_LSA_SET(0); ring_addr |= XHCI_EPCTX_2_DCS_SET(1); } switch (udev->speed) { case USB_SPEED_FULL: case USB_SPEED_LOW: /* 1ms -> 125us */ fps_shift += 3; break; default: break; } switch (type) { case UE_INTERRUPT: if (fps_shift > 3) fps_shift--; temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); break; case UE_ISOCHRONOUS: temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); switch (udev->speed) { case USB_SPEED_SUPER: if (mult > 3) mult = 3; temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); max_packet_count /= mult; break; default: break; } break; default: break; } endp->dwEpCtx0 = htole32(temp); temp = XHCI_EPCTX_1_HID_SET(0) | XHCI_EPCTX_1_MAXB_SET(max_packet_count) | XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); /* * Always enable the "three strikes and you are gone" feature * except for ISOCHRONOUS endpoints. This is suggested by * section 4.3.3 in the XHCI specification about device slot * initialisation. */ if (type != UE_ISOCHRONOUS) temp |= XHCI_EPCTX_1_CERR_SET(3); switch (type) { case UE_CONTROL: temp |= XHCI_EPCTX_1_EPTYPE_SET(4); break; case UE_ISOCHRONOUS: temp |= XHCI_EPCTX_1_EPTYPE_SET(1); break; case UE_BULK: temp |= XHCI_EPCTX_1_EPTYPE_SET(2); break; default: temp |= XHCI_EPCTX_1_EPTYPE_SET(3); break; } /* check for IN direction */ if (epno & 1) temp |= XHCI_EPCTX_1_EPTYPE_SET(4); endp->dwEpCtx1 = htole32(temp); endp->qwEpCtx2 = htole64(ring_addr); switch (edesc->bmAttributes & UE_XFERTYPE) { case UE_INTERRUPT: case UE_ISOCHRONOUS: temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, max_frame_size)); break; case UE_CONTROL: temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); break; default: temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); break; } endp->dwEpCtx4 = htole32(temp); #ifdef USB_DEBUG xhci_dump_endpoint(endp); #endif usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); return (0); /* success */ } static usb_error_t xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) { struct xhci_endpoint_ext *pepext; struct usb_endpoint_ss_comp_descriptor *ecomp; usb_stream_t x; pepext = xhci_get_endpoint_ext(xfer->xroot->udev, xfer->endpoint->edesc); ecomp = xfer->endpoint->ecomp; for (x = 0; x != XHCI_MAX_STREAMS; x++) { uint64_t temp; /* halt any transfers */ pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; /* compute start of TRB ring for stream "x" */ temp = pepext->physaddr + (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + XHCI_SCTX_0_SCT_SEC_TR_RING; /* make tree structure */ pepext->trb[(XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); /* reserved fields */ pepext->trb[(XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS) + x].dwTrb2 = 0; pepext->trb[(XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS) + x].dwTrb3 = 0; } usb_pc_cpu_flush(pepext->page_cache); return (xhci_configure_endpoint(xfer->xroot->udev, xfer->endpoint->edesc, pepext, xfer->interval, xfer->max_packet_count, (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, xfer->max_frame_size, xfer->endpoint->ep_mode)); } static usb_error_t xhci_configure_device(struct usb_device *udev) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); struct usb_page_search buf_inp; struct usb_page_cache *pcinp; struct xhci_slot_ctx *slot; struct usb_device *hubdev; uint32_t temp; uint32_t route; uint32_t rh_port; uint8_t is_hub; uint8_t index; uint8_t depth; index = udev->controller_slot_id; DPRINTF("index=%u\n", index); pcinp = &sc->sc_hw.devs[index].input_pc; usbd_get_page(pcinp, 0, &buf_inp); slot = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_slot, buf_inp.buffer); rh_port = 0; route = 0; /* figure out route string and root HUB port number */ for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { if (hubdev->parent_hub == NULL) break; depth = hubdev->parent_hub->depth; /* * NOTE: HS/FS/LS devices and the SS root HUB can have * more than 15 ports */ rh_port = hubdev->port_no; if (depth == 0) break; if (rh_port > 15) rh_port = 15; if (depth < 6) route |= rh_port << (4 * (depth - 1)); } DPRINTF("Route=0x%08x\n", route); temp = XHCI_SCTX_0_ROUTE_SET(route) | XHCI_SCTX_0_CTX_NUM_SET( sc->sc_hw.devs[index].context_num + 1); switch (udev->speed) { case USB_SPEED_LOW: temp |= XHCI_SCTX_0_SPEED_SET(2); if (udev->parent_hs_hub != NULL && udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { DPRINTF("Device inherits MTT\n"); temp |= XHCI_SCTX_0_MTT_SET(1); } break; case USB_SPEED_HIGH: temp |= XHCI_SCTX_0_SPEED_SET(3); if (sc->sc_hw.devs[index].nports != 0 && udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { DPRINTF("HUB supports MTT\n"); temp |= XHCI_SCTX_0_MTT_SET(1); } break; case USB_SPEED_FULL: temp |= XHCI_SCTX_0_SPEED_SET(1); if (udev->parent_hs_hub != NULL && udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { DPRINTF("Device inherits MTT\n"); temp |= XHCI_SCTX_0_MTT_SET(1); } break; default: temp |= XHCI_SCTX_0_SPEED_SET(4); break; } is_hub = sc->sc_hw.devs[index].nports != 0 && (udev->speed == USB_SPEED_SUPER || udev->speed == USB_SPEED_HIGH); if (is_hub) temp |= XHCI_SCTX_0_HUB_SET(1); slot->dwSctx0 = htole32(temp); temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); if (is_hub) { temp |= XHCI_SCTX_1_NUM_PORTS_SET( sc->sc_hw.devs[index].nports); } slot->dwSctx1 = htole32(temp); temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); if (is_hub) { temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( sc->sc_hw.devs[index].tt); } hubdev = udev->parent_hs_hub; /* check if we should activate the transaction translator */ switch (udev->speed) { case USB_SPEED_FULL: case USB_SPEED_LOW: if (hubdev != NULL) { temp |= XHCI_SCTX_2_TT_HUB_SID_SET( hubdev->controller_slot_id); temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( udev->hs_port_no); } break; default: break; } slot->dwSctx2 = htole32(temp); /* * These fields should be initialized to zero, according to * XHCI section 6.2.2 - slot context: */ temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | XHCI_SCTX_3_SLOT_STATE_SET(0); slot->dwSctx3 = htole32(temp); #ifdef USB_DEBUG xhci_dump_device(slot); #endif usb_pc_cpu_flush(pcinp); return (0); /* success */ } static usb_error_t xhci_alloc_device_ext(struct usb_device *udev) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); struct usb_page_search buf_dev; struct usb_page_search buf_ep; struct xhci_trb *trb; struct usb_page_cache *pc; struct usb_page *pg; uint64_t addr; uint8_t index; uint8_t i; index = udev->controller_slot_id; pc = &sc->sc_hw.devs[index].device_pc; pg = &sc->sc_hw.devs[index].device_pg; /* need to initialize the page cache */ pc->tag_parent = sc->sc_bus.dma_parent_tag; if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? sizeof(struct xhci_dev_ctx64) : sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) goto error; usbd_get_page(pc, 0, &buf_dev); pc = &sc->sc_hw.devs[index].input_pc; pg = &sc->sc_hw.devs[index].input_pg; /* need to initialize the page cache */ pc->tag_parent = sc->sc_bus.dma_parent_tag; if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? sizeof(struct xhci_input_dev_ctx64) : sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { goto error; } /* initialize all endpoint LINK TRBs */ for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { pc = &sc->sc_hw.devs[index].endpoint_pc[i]; pg = &sc->sc_hw.devs[index].endpoint_pg[i]; /* need to initialize the page cache */ pc->tag_parent = sc->sc_bus.dma_parent_tag; if (usb_pc_alloc_mem(pc, pg, sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { goto error; } /* lookup endpoint TRB ring */ usbd_get_page(pc, 0, &buf_ep); /* get TRB pointer */ trb = buf_ep.buffer; trb += XHCI_MAX_TRANSFERS - 1; /* get TRB start address */ addr = buf_ep.physaddr; /* create LINK TRB */ trb->qwTrb0 = htole64(addr); trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); usb_pc_cpu_flush(pc); } xhci_set_slot_pointer(sc, index, buf_dev.physaddr); return (0); error: xhci_free_device_ext(udev); return (USB_ERR_NOMEM); } static void xhci_free_device_ext(struct usb_device *udev) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); uint8_t index; uint8_t i; index = udev->controller_slot_id; xhci_set_slot_pointer(sc, index, 0); usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); } static struct xhci_endpoint_ext * xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); struct xhci_endpoint_ext *pepext; struct usb_page_cache *pc; struct usb_page_search buf_ep; uint8_t epno; uint8_t index; epno = edesc->bEndpointAddress; if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) epno |= UE_DIR_IN; epno = XHCI_EPNO2EPID(epno); index = udev->controller_slot_id; pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; usbd_get_page(pc, 0, &buf_ep); pepext = &sc->sc_hw.devs[index].endp[epno]; pepext->page_cache = pc; pepext->trb = buf_ep.buffer; pepext->physaddr = buf_ep.physaddr; return (pepext); } static void xhci_endpoint_doorbell(struct usb_xfer *xfer) { struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); uint8_t epno; uint8_t index; epno = xfer->endpointno; if (xfer->flags_int.control_xfr) epno |= UE_DIR_IN; epno = XHCI_EPNO2EPID(epno); index = xfer->xroot->udev->controller_slot_id; if (xfer->xroot->udev->flags.self_suspended == 0) { XWRITE4(sc, door, XHCI_DOORBELL(index), epno | XHCI_DB_SID_SET(xfer->stream_id)); } } static void xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) { struct xhci_endpoint_ext *pepext; if (xfer->flags_int.bandwidth_reclaimed) { xfer->flags_int.bandwidth_reclaimed = 0; pepext = xhci_get_endpoint_ext(xfer->xroot->udev, xfer->endpoint->edesc); pepext->trb_used[xfer->stream_id]--; pepext->xfer[xfer->qh_pos] = NULL; if (error && pepext->trb_running != 0) { pepext->trb_halted = 1; pepext->trb_running = 0; } } } static usb_error_t xhci_transfer_insert(struct usb_xfer *xfer) { struct xhci_td *td_first; struct xhci_td *td_last; struct xhci_trb *trb_link; struct xhci_endpoint_ext *pepext; uint64_t addr; usb_stream_t id; uint8_t i; uint8_t inext; uint8_t trb_limit; DPRINTFN(8, "\n"); id = xfer->stream_id; /* check if already inserted */ if (xfer->flags_int.bandwidth_reclaimed) { DPRINTFN(8, "Already in schedule\n"); return (0); } pepext = xhci_get_endpoint_ext(xfer->xroot->udev, xfer->endpoint->edesc); td_first = xfer->td_transfer_first; td_last = xfer->td_transfer_last; addr = pepext->physaddr; switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { case UE_CONTROL: case UE_INTERRUPT: /* single buffered */ trb_limit = 1; break; default: /* multi buffered */ trb_limit = (XHCI_MAX_TRANSFERS - 2); break; } if (pepext->trb_used[id] >= trb_limit) { DPRINTFN(8, "Too many TDs queued.\n"); return (USB_ERR_NOMEM); } /* check if bMaxPacketSize changed */ if (xfer->flags_int.control_xfr != 0 && pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) { DPRINTFN(8, "Reconfigure control endpoint\n"); /* force driver to reconfigure endpoint */ pepext->trb_halted = 1; pepext->trb_running = 0; } /* check for stopped condition, after putting transfer on interrupt queue */ if (pepext->trb_running == 0) { struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); DPRINTFN(8, "Not running\n"); /* start configuration */ (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), &sc->sc_config_msg[0], &sc->sc_config_msg[1]); return (0); } pepext->trb_used[id]++; /* get current TRB index */ i = pepext->trb_index[id]; /* get next TRB index */ inext = (i + 1); /* the last entry of the ring is a hardcoded link TRB */ if (inext >= (XHCI_MAX_TRANSFERS - 1)) inext = 0; /* store next TRB index, before stream ID offset is added */ pepext->trb_index[id] = inext; /* offset for stream */ i += id * XHCI_MAX_TRANSFERS; inext += id * XHCI_MAX_TRANSFERS; /* compute terminating return address */ addr += (inext * sizeof(struct xhci_trb)); /* compute link TRB pointer */ trb_link = td_last->td_trb + td_last->ntrb; /* update next pointer of last link TRB */ trb_link->qwTrb0 = htole64(addr); trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); #ifdef USB_DEBUG xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); #endif usb_pc_cpu_flush(td_last->page_cache); /* write ahead chain end marker */ pepext->trb[inext].qwTrb0 = 0; pepext->trb[inext].dwTrb2 = 0; pepext->trb[inext].dwTrb3 = 0; /* update next pointer of link TRB */ pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); #ifdef USB_DEBUG xhci_dump_trb(&pepext->trb[i]); #endif usb_pc_cpu_flush(pepext->page_cache); /* toggle cycle bit which activates the transfer chain */ pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); usb_pc_cpu_flush(pepext->page_cache); DPRINTF("qh_pos = %u\n", i); pepext->xfer[i] = xfer; xfer->qh_pos = i; xfer->flags_int.bandwidth_reclaimed = 1; xhci_endpoint_doorbell(xfer); return (0); } static void xhci_root_intr(struct xhci_softc *sc) { uint16_t i; USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* clear any old interrupt data */ memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); for (i = 1; i <= sc->sc_noport; i++) { /* pick out CHANGE bits from the status register */ if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( XHCI_PS_CSC | XHCI_PS_PEC | XHCI_PS_OCC | XHCI_PS_WRC | XHCI_PS_PRC | XHCI_PS_PLC | XHCI_PS_CEC)) { sc->sc_hub_idata[i / 8] |= 1 << (i % 8); DPRINTF("port %d changed\n", i); } } uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); } /*------------------------------------------------------------------------* * xhci_device_done - XHCI done handler * * NOTE: This function can be called two times in a row on * the same USB transfer. From close and from interrupt. *------------------------------------------------------------------------*/ static void xhci_device_done(struct usb_xfer *xfer, usb_error_t error) { DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", xfer, xfer->endpoint, error); /* remove transfer from HW queue */ xhci_transfer_remove(xfer, error); /* dequeue transfer and start next transfer */ usbd_transfer_done(xfer, error); } /*------------------------------------------------------------------------* * XHCI data transfer support (generic type) *------------------------------------------------------------------------*/ static void xhci_device_generic_open(struct usb_xfer *xfer) { DPRINTF("\n"); } static void xhci_device_generic_close(struct usb_xfer *xfer) { DPRINTF("\n"); xhci_device_done(xfer, USB_ERR_CANCELLED); } static void xhci_device_generic_multi_enter(struct usb_endpoint *ep, usb_stream_t stream_id, struct usb_xfer *enter_xfer) { struct usb_xfer *xfer; /* check if there is a current transfer */ xfer = ep->endpoint_q[stream_id].curr; if (xfer == NULL) return; /* * Check if the current transfer is started and then pickup * the next one, if any. Else wait for next start event due to * block on failure feature. */ if (!xfer->flags_int.bandwidth_reclaimed) return; xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); if (xfer == NULL) { /* * In case of enter we have to consider that the * transfer is queued by the USB core after the enter * method is called. */ xfer = enter_xfer; if (xfer == NULL) return; } /* try to multi buffer */ xhci_transfer_insert(xfer); } static void xhci_device_generic_enter(struct usb_xfer *xfer) { DPRINTF("\n"); /* set up TD's and QH */ xhci_setup_generic_chain(xfer); xhci_device_generic_multi_enter(xfer->endpoint, xfer->stream_id, xfer); } static void xhci_device_generic_start(struct usb_xfer *xfer) { DPRINTF("\n"); /* try to insert xfer on HW queue */ xhci_transfer_insert(xfer); /* try to multi buffer */ xhci_device_generic_multi_enter(xfer->endpoint, xfer->stream_id, NULL); /* add transfer last on interrupt queue */ usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); /* start timeout, if any */ if (xfer->timeout != 0) usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); } static const struct usb_pipe_methods xhci_device_generic_methods = { .open = xhci_device_generic_open, .close = xhci_device_generic_close, .enter = xhci_device_generic_enter, .start = xhci_device_generic_start, }; /*------------------------------------------------------------------------* * xhci root HUB support *------------------------------------------------------------------------* * Simulate a hardware HUB by handling all the necessary requests. *------------------------------------------------------------------------*/ #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } static const struct usb_device_descriptor xhci_devd = { .bLength = sizeof(xhci_devd), .bDescriptorType = UDESC_DEVICE, /* type */ HSETW(.bcdUSB, 0x0300), /* USB version */ .bDeviceClass = UDCLASS_HUB, /* class */ .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ .bMaxPacketSize = 9, /* max packet size */ HSETW(.idVendor, 0x0000), /* vendor */ HSETW(.idProduct, 0x0000), /* product */ HSETW(.bcdDevice, 0x0100), /* device version */ .iManufacturer = 1, .iProduct = 2, .iSerialNumber = 0, .bNumConfigurations = 1, /* # of configurations */ }; static const struct xhci_bos_desc xhci_bosd = { .bosd = { .bLength = sizeof(xhci_bosd.bosd), .bDescriptorType = UDESC_BOS, HSETW(.wTotalLength, sizeof(xhci_bosd)), .bNumDeviceCaps = 3, }, .usb2extd = { .bLength = sizeof(xhci_bosd.usb2extd), .bDescriptorType = 1, .bDevCapabilityType = 2, .bmAttributes[0] = 2, }, .usbdcd = { .bLength = sizeof(xhci_bosd.usbdcd), .bDescriptorType = UDESC_DEVICE_CAPABILITY, .bDevCapabilityType = 3, .bmAttributes = 0, /* XXX */ HSETW(.wSpeedsSupported, 0x000C), .bFunctionalitySupport = 8, .bU1DevExitLat = 255, /* dummy - not used */ .wU2DevExitLat = { 0x00, 0x08 }, }, .cidd = { .bLength = sizeof(xhci_bosd.cidd), .bDescriptorType = 1, .bDevCapabilityType = 4, .bReserved = 0, .bContainerID = 0, /* XXX */ }, }; static const struct xhci_config_desc xhci_confd = { .confd = { .bLength = sizeof(xhci_confd.confd), .bDescriptorType = UDESC_CONFIG, .wTotalLength[0] = sizeof(xhci_confd), .bNumInterface = 1, .bConfigurationValue = 1, .iConfiguration = 0, .bmAttributes = UC_SELF_POWERED, .bMaxPower = 0 /* max power */ }, .ifcd = { .bLength = sizeof(xhci_confd.ifcd), .bDescriptorType = UDESC_INTERFACE, .bNumEndpoints = 1, .bInterfaceClass = UICLASS_HUB, .bInterfaceSubClass = UISUBCLASS_HUB, .bInterfaceProtocol = 0, }, .endpd = { .bLength = sizeof(xhci_confd.endpd), .bDescriptorType = UDESC_ENDPOINT, .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, .bmAttributes = UE_INTERRUPT, .wMaxPacketSize[0] = 2, /* max 15 ports */ .bInterval = 255, }, .endpcd = { .bLength = sizeof(xhci_confd.endpcd), .bDescriptorType = UDESC_ENDPOINT_SS_COMP, .bMaxBurst = 0, .bmAttributes = 0, }, }; static const struct usb_hub_ss_descriptor xhci_hubd = { .bLength = sizeof(xhci_hubd), .bDescriptorType = UDESC_SS_HUB, }; static usb_error_t xhci_roothub_exec(struct usb_device *udev, struct usb_device_request *req, const void **pptr, uint16_t *plength) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); const char *str_ptr; const void *ptr; uint32_t port; uint32_t v; uint16_t len; uint16_t i; uint16_t value; uint16_t index; uint8_t j; usb_error_t err; USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); /* buffer reset */ ptr = (const void *)&sc->sc_hub_desc; len = 0; err = 0; value = UGETW(req->wValue); index = UGETW(req->wIndex); DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " "wValue=0x%04x wIndex=0x%04x\n", req->bmRequestType, req->bRequest, UGETW(req->wLength), value, index); #define C(x,y) ((x) | ((y) << 8)) switch (C(req->bRequest, req->bmRequestType)) { case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): /* * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops * for the integrated root hub. */ break; case C(UR_GET_CONFIG, UT_READ_DEVICE): len = 1; sc->sc_hub_desc.temp[0] = sc->sc_conf; break; case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): switch (value >> 8) { case UDESC_DEVICE: if ((value & 0xff) != 0) { err = USB_ERR_IOERROR; goto done; } len = sizeof(xhci_devd); ptr = (const void *)&xhci_devd; break; case UDESC_BOS: if ((value & 0xff) != 0) { err = USB_ERR_IOERROR; goto done; } len = sizeof(xhci_bosd); ptr = (const void *)&xhci_bosd; break; case UDESC_CONFIG: if ((value & 0xff) != 0) { err = USB_ERR_IOERROR; goto done; } len = sizeof(xhci_confd); ptr = (const void *)&xhci_confd; break; case UDESC_STRING: switch (value & 0xff) { case 0: /* Language table */ str_ptr = "\001"; break; case 1: /* Vendor */ str_ptr = sc->sc_vendor; break; case 2: /* Product */ str_ptr = "XHCI root HUB"; break; default: str_ptr = ""; break; } len = usb_make_str_desc( sc->sc_hub_desc.temp, sizeof(sc->sc_hub_desc.temp), str_ptr); break; default: err = USB_ERR_IOERROR; goto done; } break; case C(UR_GET_INTERFACE, UT_READ_INTERFACE): len = 1; sc->sc_hub_desc.temp[0] = 0; break; case C(UR_GET_STATUS, UT_READ_DEVICE): len = 2; USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); break; case C(UR_GET_STATUS, UT_READ_INTERFACE): case C(UR_GET_STATUS, UT_READ_ENDPOINT): len = 2; USETW(sc->sc_hub_desc.stat.wStatus, 0); break; case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): if (value >= XHCI_MAX_DEVICES) { err = USB_ERR_IOERROR; goto done; } break; case C(UR_SET_CONFIG, UT_WRITE_DEVICE): if (value != 0 && value != 1) { err = USB_ERR_IOERROR; goto done; } sc->sc_conf = value; break; case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): break; case C(UR_SET_FEATURE, UT_WRITE_DEVICE): case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): err = USB_ERR_IOERROR; goto done; case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): break; case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): break; /* Hub requests */ case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): break; case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); if ((index < 1) || (index > sc->sc_noport)) { err = USB_ERR_IOERROR; goto done; } port = XHCI_PORTSC(index); v = XREAD4(sc, oper, port); i = XHCI_PS_PLS_GET(v); v &= ~XHCI_PS_CLEAR; switch (value) { case UHF_C_BH_PORT_RESET: XWRITE4(sc, oper, port, v | XHCI_PS_WRC); break; case UHF_C_PORT_CONFIG_ERROR: XWRITE4(sc, oper, port, v | XHCI_PS_CEC); break; case UHF_C_PORT_SUSPEND: case UHF_C_PORT_LINK_STATE: XWRITE4(sc, oper, port, v | XHCI_PS_PLC); break; case UHF_C_PORT_CONNECTION: XWRITE4(sc, oper, port, v | XHCI_PS_CSC); break; case UHF_C_PORT_ENABLE: XWRITE4(sc, oper, port, v | XHCI_PS_PEC); break; case UHF_C_PORT_OVER_CURRENT: XWRITE4(sc, oper, port, v | XHCI_PS_OCC); break; case UHF_C_PORT_RESET: XWRITE4(sc, oper, port, v | XHCI_PS_PRC); break; case UHF_PORT_ENABLE: XWRITE4(sc, oper, port, v | XHCI_PS_PED); break; case UHF_PORT_POWER: XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); break; case UHF_PORT_INDICATOR: XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); break; case UHF_PORT_SUSPEND: /* U3 -> U15 */ if (i == 3) { XWRITE4(sc, oper, port, v | XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); } /* wait 20ms for resume sequence to complete */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); /* U0 */ XWRITE4(sc, oper, port, v | XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); break; default: err = USB_ERR_IOERROR; goto done; } break; case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): if ((value & 0xff) != 0) { err = USB_ERR_IOERROR; goto done; } v = XREAD4(sc, capa, XHCI_HCSPARAMS0); sc->sc_hub_desc.hubd = xhci_hubd; sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; if (XHCI_HCS0_PPC(v)) i = UHD_PWR_INDIVIDUAL; else i = UHD_PWR_GANGED; if (XHCI_HCS0_PIND(v)) i |= UHD_PORT_IND; i |= UHD_OC_INDIVIDUAL; USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); /* see XHCI section 5.4.9: */ sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; for (j = 1; j <= sc->sc_noport; j++) { v = XREAD4(sc, oper, XHCI_PORTSC(j)); if (v & XHCI_PS_DR) { sc->sc_hub_desc.hubd. DeviceRemovable[j / 8] |= 1U << (j % 8); } } len = sc->sc_hub_desc.hubd.bLength; break; case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): len = 16; memset(sc->sc_hub_desc.temp, 0, 16); break; case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); if ((index < 1) || (index > sc->sc_noport)) { err = USB_ERR_IOERROR; goto done; } v = XREAD4(sc, oper, XHCI_PORTSC(index)); DPRINTFN(9, "port status=0x%08x\n", v); i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); switch (XHCI_PS_SPEED_GET(v)) { case 3: i |= UPS_HIGH_SPEED; break; case 2: i |= UPS_LOW_SPEED; break; case 1: /* FULL speed */ break; default: i |= UPS_OTHER_SPEED; break; } if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; if (v & XHCI_PS_PR) i |= UPS_RESET; #if 0 if (v & XHCI_PS_PP) /* XXX undefined */ #endif USETW(sc->sc_hub_desc.ps.wPortStatus, i); i = 0; if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; USETW(sc->sc_hub_desc.ps.wPortChange, i); len = sizeof(sc->sc_hub_desc.ps); break; case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): err = USB_ERR_IOERROR; goto done; case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): break; case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): i = index >> 8; index &= 0x00FF; if ((index < 1) || (index > sc->sc_noport)) { err = USB_ERR_IOERROR; goto done; } port = XHCI_PORTSC(index); v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; switch (value) { case UHF_PORT_U1_TIMEOUT: if (XHCI_PS_SPEED_GET(v) != 4) { err = USB_ERR_IOERROR; goto done; } port = XHCI_PORTPMSC(index); v = XREAD4(sc, oper, port); v &= ~XHCI_PM3_U1TO_SET(0xFF); v |= XHCI_PM3_U1TO_SET(i); XWRITE4(sc, oper, port, v); break; case UHF_PORT_U2_TIMEOUT: if (XHCI_PS_SPEED_GET(v) != 4) { err = USB_ERR_IOERROR; goto done; } port = XHCI_PORTPMSC(index); v = XREAD4(sc, oper, port); v &= ~XHCI_PM3_U2TO_SET(0xFF); v |= XHCI_PM3_U2TO_SET(i); XWRITE4(sc, oper, port, v); break; case UHF_BH_PORT_RESET: XWRITE4(sc, oper, port, v | XHCI_PS_WPR); break; case UHF_PORT_LINK_STATE: XWRITE4(sc, oper, port, v | XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); /* 4ms settle time */ usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); break; case UHF_PORT_ENABLE: DPRINTFN(3, "set port enable %d\n", index); break; case UHF_PORT_SUSPEND: DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); j = XHCI_PS_SPEED_GET(v); if ((j < 1) || (j > 3)) { /* non-supported speed */ err = USB_ERR_IOERROR; goto done; } XWRITE4(sc, oper, port, v | XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); break; case UHF_PORT_RESET: DPRINTFN(6, "reset port %d\n", index); XWRITE4(sc, oper, port, v | XHCI_PS_PR); break; case UHF_PORT_POWER: DPRINTFN(3, "set port power %d\n", index); XWRITE4(sc, oper, port, v | XHCI_PS_PP); break; case UHF_PORT_TEST: DPRINTFN(3, "set port test %d\n", index); break; case UHF_PORT_INDICATOR: DPRINTFN(3, "set port indicator %d\n", index); v &= ~XHCI_PS_PIC_SET(3); v |= XHCI_PS_PIC_SET(1); XWRITE4(sc, oper, port, v); break; default: err = USB_ERR_IOERROR; goto done; } break; case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): break; default: err = USB_ERR_IOERROR; goto done; } done: *plength = len; *pptr = ptr; return (err); } static void xhci_xfer_setup(struct usb_setup_params *parm) { struct usb_page_search page_info; struct usb_page_cache *pc; struct usb_xfer *xfer; void *last_obj; uint32_t ntd; uint32_t n; xfer = parm->curr_xfer; /* * The proof for the "ntd" formula is illustrated like this: * * +------------------------------------+ * | | * | |remainder -> | * | +-----+---+ | * | | xxx | x | frm 0 | * | +-----+---++ | * | | xxx | xx | frm 1 | * | +-----+----+ | * | ... | * +------------------------------------+ * * "xxx" means a completely full USB transfer descriptor * * "x" and "xx" means a short USB packet * * For the remainder of an USB transfer modulo * "max_data_length" we need two USB transfer descriptors. * One to transfer the remaining data and one to finalise with * a zero length packet in case the "force_short_xfer" flag is * set. We only need two USB transfer descriptors in the case * where the transfer length of the first one is a factor of * "max_frame_size". The rest of the needed USB transfer * descriptors is given by the buffer size divided by the * maximum data payload. */ parm->hc_max_packet_size = 0x400; parm->hc_max_packet_count = 16 * 3; parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; xfer->flags_int.bdma_enable = 1; usbd_transfer_setup_sub(parm); if (xfer->flags_int.isochronous_xfr) { ntd = ((1 * xfer->nframes) + (xfer->max_data_length / xfer->max_hc_frame_size)); } else if (xfer->flags_int.control_xfr) { ntd = ((2 * xfer->nframes) + 1 /* STATUS */ + (xfer->max_data_length / xfer->max_hc_frame_size)); } else { ntd = ((2 * xfer->nframes) + (xfer->max_data_length / xfer->max_hc_frame_size)); } alloc_dma_set: if (parm->err) return; /* * Allocate queue heads and transfer descriptors */ last_obj = NULL; if (usbd_transfer_setup_sub_malloc( parm, &pc, sizeof(struct xhci_td), XHCI_TD_ALIGN, ntd)) { parm->err = USB_ERR_NOMEM; return; } if (parm->buf) { for (n = 0; n != ntd; n++) { struct xhci_td *td; usbd_get_page(pc + n, 0, &page_info); td = page_info.buffer; /* init TD */ td->td_self = page_info.physaddr; td->obj_next = last_obj; td->page_cache = pc + n; last_obj = td; usb_pc_cpu_flush(pc + n); } } xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; if (!xfer->flags_int.curr_dma_set) { xfer->flags_int.curr_dma_set = 1; goto alloc_dma_set; } } static uint8_t xhci_get_endpoint_state(struct usb_device *udev, uint8_t epno) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); struct usb_page_search buf_dev; struct xhci_hw_dev *hdev; struct xhci_endp_ctx *endp; uint32_t temp; MPASS(epno != 0); hdev = &sc->sc_hw.devs[udev->controller_slot_id]; usbd_get_page(&hdev->device_pc, 0, &buf_dev); endp = XHCI_GET_CTX(sc, xhci_dev_ctx, ctx_ep[epno - 1], buf_dev.buffer); usb_pc_cpu_invalidate(&hdev->device_pc); temp = le32toh(endp->dwEpCtx0); return (XHCI_EPCTX_0_EPSTATE_GET(temp)); } static usb_error_t xhci_configure_reset_endpoint(struct usb_xfer *xfer) { struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); struct usb_page_search buf_inp; struct usb_device *udev; struct xhci_endpoint_ext *pepext; struct usb_endpoint_descriptor *edesc; struct usb_page_cache *pcinp; usb_error_t err; usb_stream_t stream_id; uint32_t mask; uint8_t index; uint8_t epno; pepext = xhci_get_endpoint_ext(xfer->xroot->udev, xfer->endpoint->edesc); udev = xfer->xroot->udev; index = udev->controller_slot_id; pcinp = &sc->sc_hw.devs[index].input_pc; usbd_get_page(pcinp, 0, &buf_inp); edesc = xfer->endpoint->edesc; epno = edesc->bEndpointAddress; stream_id = xfer->stream_id; if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) epno |= UE_DIR_IN; epno = XHCI_EPNO2EPID(epno); if (epno == 0) return (USB_ERR_NO_PIPE); /* invalid */ XHCI_CMD_LOCK(sc); /* configure endpoint */ err = xhci_configure_endpoint_by_xfer(xfer); if (err != 0) { XHCI_CMD_UNLOCK(sc); return (err); } /* * Get the endpoint into the stopped state according to the * endpoint context state diagram in the XHCI specification: */ switch (xhci_get_endpoint_state(udev, epno)) { case XHCI_EPCTX_0_EPSTATE_DISABLED: break; case XHCI_EPCTX_0_EPSTATE_STOPPED: break; case XHCI_EPCTX_0_EPSTATE_HALTED: err = xhci_cmd_reset_ep(sc, 0, epno, index); if (err != 0) DPRINTF("Could not reset endpoint %u\n", epno); break; default: err = xhci_cmd_stop_ep(sc, 0, epno, index); if (err != 0) DPRINTF("Could not stop endpoint %u\n", epno); break; } err = xhci_cmd_set_tr_dequeue_ptr(sc, (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), stream_id, epno, index); if (err != 0) DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); /* * Get the endpoint into the running state according to the * endpoint context state diagram in the XHCI specification: */ mask = (1U << epno); xhci_configure_mask(udev, mask | 1U, 0); if (!(sc->sc_hw.devs[index].ep_configured & mask)) { sc->sc_hw.devs[index].ep_configured |= mask; err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); } else { err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); } if (err != 0) { DPRINTF("Could not configure " "endpoint %u at slot %u.\n", epno, index); } XHCI_CMD_UNLOCK(sc); return (0); } static void xhci_xfer_unsetup(struct usb_xfer *xfer) { return; } static void xhci_start_dma_delay(struct usb_xfer *xfer) { struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); /* put transfer on interrupt queue (again) */ usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), &sc->sc_config_msg[0], &sc->sc_config_msg[1]); } static void xhci_configure_msg(struct usb_proc_msg *pm) { struct xhci_softc *sc; struct xhci_endpoint_ext *pepext; struct usb_xfer *xfer; sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); restart: TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { pepext = xhci_get_endpoint_ext(xfer->xroot->udev, xfer->endpoint->edesc); if ((pepext->trb_halted != 0) || (pepext->trb_running == 0)) { uint16_t i; /* clear halted and running */ pepext->trb_halted = 0; pepext->trb_running = 0; /* nuke remaining buffered transfers */ for (i = 0; i != (XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS); i++) { /* * NOTE: We need to use the timeout * error code here else existing * isochronous clients can get * confused: */ if (pepext->xfer[i] != NULL) { xhci_device_done(pepext->xfer[i], USB_ERR_TIMEOUT); } } /* * NOTE: The USB transfer cannot vanish in * this state! */ USB_BUS_UNLOCK(&sc->sc_bus); xhci_configure_reset_endpoint(xfer); USB_BUS_LOCK(&sc->sc_bus); /* check if halted is still cleared */ if (pepext->trb_halted == 0) { pepext->trb_running = 1; memset(pepext->trb_index, 0, sizeof(pepext->trb_index)); } goto restart; } if (xfer->flags_int.did_dma_delay) { /* remove transfer from interrupt queue (again) */ usbd_transfer_dequeue(xfer); /* we are finally done */ usb_dma_delay_done_cb(xfer); /* queue changed - restart */ goto restart; } } TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { /* try to insert xfer on HW queue */ xhci_transfer_insert(xfer); /* try to multi buffer */ xhci_device_generic_multi_enter(xfer->endpoint, xfer->stream_id, NULL); } } static void xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, struct usb_endpoint *ep) { struct xhci_endpoint_ext *pepext; struct xhci_softc *sc; uint8_t index; uint8_t epno; DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); if (udev->parent_hub == NULL) { /* root HUB has special endpoint handling */ return; } ep->methods = &xhci_device_generic_methods; pepext = xhci_get_endpoint_ext(udev, edesc); USB_BUS_LOCK(udev->bus); pepext->trb_halted = 1; pepext->trb_running = 0; /* * When doing an alternate setting, except for control * endpoints, we need to re-configure the XHCI endpoint * context: */ if ((edesc->bEndpointAddress & UE_ADDR) != 0) { sc = XHCI_BUS2SC(udev->bus); index = udev->controller_slot_id; epno = XHCI_EPNO2EPID(edesc->bEndpointAddress); sc->sc_hw.devs[index].ep_configured &= ~(1U << epno); } USB_BUS_UNLOCK(udev->bus); } static void xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) { } static void xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) { struct xhci_endpoint_ext *pepext; DPRINTF("\n"); if (udev->flags.usb_mode != USB_MODE_HOST) { /* not supported */ return; } if (udev->parent_hub == NULL) { /* root HUB has special endpoint handling */ return; } pepext = xhci_get_endpoint_ext(udev, ep->edesc); USB_BUS_LOCK(udev->bus); pepext->trb_halted = 1; pepext->trb_running = 0; USB_BUS_UNLOCK(udev->bus); } static usb_error_t xhci_device_init(struct usb_device *udev) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); usb_error_t err; uint8_t temp; /* no init for root HUB */ if (udev->parent_hub == NULL) return (0); XHCI_CMD_LOCK(sc); /* set invalid default */ udev->controller_slot_id = sc->sc_noslot + 1; /* try to get a new slot ID from the XHCI */ err = xhci_cmd_enable_slot(sc, &temp); if (err) { XHCI_CMD_UNLOCK(sc); return (err); } if (temp > sc->sc_noslot) { XHCI_CMD_UNLOCK(sc); return (USB_ERR_BAD_ADDRESS); } if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { DPRINTF("slot %u already allocated.\n", temp); XHCI_CMD_UNLOCK(sc); return (USB_ERR_BAD_ADDRESS); } /* store slot ID for later reference */ udev->controller_slot_id = temp; /* reset data structure */ memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); /* set mark slot allocated */ sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; err = xhci_alloc_device_ext(udev); XHCI_CMD_UNLOCK(sc); /* get device into default state */ if (err == 0) err = xhci_set_address(udev, NULL, 0); return (err); } static void xhci_device_uninit(struct usb_device *udev) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); uint8_t index; /* no init for root HUB */ if (udev->parent_hub == NULL) return; XHCI_CMD_LOCK(sc); index = udev->controller_slot_id; if (index <= sc->sc_noslot) { xhci_cmd_disable_slot(sc, index); sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; /* free device extension */ xhci_free_device_ext(udev); } XHCI_CMD_UNLOCK(sc); } static void xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) { /* * Wait until the hardware has finished any possible use of * the transfer descriptor(s) */ *pus = 2048; /* microseconds */ } static void xhci_device_resume(struct usb_device *udev) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); uint8_t index; uint8_t n; uint8_t p; DPRINTF("\n"); /* check for root HUB */ if (udev->parent_hub == NULL) return; index = udev->controller_slot_id; XHCI_CMD_LOCK(sc); /* blindly resume all endpoints */ USB_BUS_LOCK(udev->bus); for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { for (p = 0; p != XHCI_MAX_STREAMS; p++) { XWRITE4(sc, door, XHCI_DOORBELL(index), n | XHCI_DB_SID_SET(p)); } } USB_BUS_UNLOCK(udev->bus); XHCI_CMD_UNLOCK(sc); } static void xhci_device_suspend(struct usb_device *udev) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); uint8_t index; uint8_t n; usb_error_t err; DPRINTF("\n"); /* check for root HUB */ if (udev->parent_hub == NULL) return; index = udev->controller_slot_id; XHCI_CMD_LOCK(sc); /* blindly suspend all endpoints */ for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { err = xhci_cmd_stop_ep(sc, 1, n, index); if (err != 0) { DPRINTF("Failed to suspend endpoint " "%u on slot %u (ignored).\n", n, index); } } XHCI_CMD_UNLOCK(sc); } static void xhci_set_hw_power(struct usb_bus *bus) { DPRINTF("\n"); } static void xhci_device_state_change(struct usb_device *udev) { struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); struct usb_page_search buf_inp; usb_error_t err; uint8_t index; /* check for root HUB */ if (udev->parent_hub == NULL) return; index = udev->controller_slot_id; DPRINTF("\n"); if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, &sc->sc_hw.devs[index].tt); if (err != 0) sc->sc_hw.devs[index].nports = 0; } XHCI_CMD_LOCK(sc); switch (usb_get_device_state(udev)) { case USB_STATE_POWERED: if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) break; /* set default state */ sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; sc->sc_hw.devs[index].ep_configured = 3U; /* reset number of contexts */ sc->sc_hw.devs[index].context_num = 0; err = xhci_cmd_reset_dev(sc, index); if (err != 0) { DPRINTF("Device reset failed " "for slot %u.\n", index); } break; case USB_STATE_ADDRESSED: if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) break; sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; sc->sc_hw.devs[index].ep_configured = 3U; /* set configure mask to slot only */ xhci_configure_mask(udev, 1, 0); /* deconfigure all endpoints, except EP0 */ err = xhci_cmd_configure_ep(sc, 0, 1, index); if (err) { DPRINTF("Failed to deconfigure " "slot %u.\n", index); } break; case USB_STATE_CONFIGURED: if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) { /* deconfigure all endpoints, except EP0 */ err = xhci_cmd_configure_ep(sc, 0, 1, index); if (err) { DPRINTF("Failed to deconfigure " "slot %u.\n", index); } } /* set configured state */ sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; sc->sc_hw.devs[index].ep_configured = 3U; /* reset number of contexts */ sc->sc_hw.devs[index].context_num = 0; usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); xhci_configure_mask(udev, 3, 0); err = xhci_configure_device(udev); if (err != 0) { DPRINTF("Could not configure device " "at slot %u.\n", index); } err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); if (err != 0) { DPRINTF("Could not evaluate device " "context at slot %u.\n", index); } break; default: break; } XHCI_CMD_UNLOCK(sc); } static usb_error_t xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, uint8_t ep_mode) { switch (ep_mode) { case USB_EP_MODE_DEFAULT: return (0); case USB_EP_MODE_STREAMS: if (xhcistreams == 0 || (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || udev->speed != USB_SPEED_SUPER) return (USB_ERR_INVAL); return (0); default: return (USB_ERR_INVAL); } } static const struct usb_bus_methods xhci_bus_methods = { .endpoint_init = xhci_ep_init, .endpoint_uninit = xhci_ep_uninit, .xfer_setup = xhci_xfer_setup, .xfer_unsetup = xhci_xfer_unsetup, .get_dma_delay = xhci_get_dma_delay, .device_init = xhci_device_init, .device_uninit = xhci_device_uninit, .device_resume = xhci_device_resume, .device_suspend = xhci_device_suspend, .set_hw_power = xhci_set_hw_power, .roothub_exec = xhci_roothub_exec, .xfer_poll = xhci_do_poll, .start_dma_delay = xhci_start_dma_delay, .set_address = xhci_set_address, .clear_stall = xhci_ep_clear_stall, .device_state_change = xhci_device_state_change, .set_hw_power_sleep = xhci_set_hw_power_sleep, .set_endpoint_mode = xhci_set_endpoint_mode, };