diff --git a/sys/arm/arm/identcpu-v4.c b/sys/arm/arm/identcpu-v4.c index af760799d938..0be39020d27a 100644 --- a/sys/arm/arm/identcpu-v4.c +++ b/sys/arm/arm/identcpu-v4.c @@ -1,384 +1,384 @@ /* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ /*- * Copyright (c) 1995 Mark Brinicombe. * Copyright (c) 1995 Brini. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * cpu.c * * Probing and configuration for the master CPU * * Created : 10/10/95 */ #include __FBSDID("$FreeBSD$"); -#include #include +#include #include #include #include #include #include #include char machine[] = "arm"; SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "Machine class"); static const char * const generic_steppings[16] = { "rev 0", "rev 1", "rev 2", "rev 3", "rev 4", "rev 5", "rev 6", "rev 7", "rev 8", "rev 9", "rev 10", "rev 11", "rev 12", "rev 13", "rev 14", "rev 15", }; static const char * const xscale_steppings[16] = { "step A-0", "step A-1", "step B-0", "step C-0", "step D-0", "rev 5", "rev 6", "rev 7", "rev 8", "rev 9", "rev 10", "rev 11", "rev 12", "rev 13", "rev 14", "rev 15", }; static const char * const i80219_steppings[16] = { "step A-0", "rev 1", "rev 2", "rev 3", "rev 4", "rev 5", "rev 6", "rev 7", "rev 8", "rev 9", "rev 10", "rev 11", "rev 12", "rev 13", "rev 14", "rev 15", }; static const char * const i80321_steppings[16] = { "step A-0", "step B-0", "rev 2", "rev 3", "rev 4", "rev 5", "rev 6", "rev 7", "rev 8", "rev 9", "rev 10", "rev 11", "rev 12", "rev 13", "rev 14", "rev 15", }; static const char * const i81342_steppings[16] = { "step A-0", "rev 1", "rev 2", "rev 3", "rev 4", "rev 5", "rev 6", "rev 7", "rev 8", "rev 9", "rev 10", "rev 11", "rev 12", "rev 13", "rev 14", "rev 15", }; /* Steppings for PXA2[15]0 */ static const char * const pxa2x0_steppings[16] = { "step A-0", "step A-1", "step B-0", "step B-1", "step B-2", "step C-0", "rev 6", "rev 7", "rev 8", "rev 9", "rev 10", "rev 11", "rev 12", "rev 13", "rev 14", "rev 15", }; /* Steppings for PXA255/26x. * rev 5: PXA26x B0, rev 6: PXA255 A0 */ static const char * const pxa255_steppings[16] = { "rev 0", "rev 1", "rev 2", "step A-0", "rev 4", "step B-0", "step A-0", "rev 7", "rev 8", "rev 9", "rev 10", "rev 11", "rev 12", "rev 13", "rev 14", "rev 15", }; /* Stepping for PXA27x */ static const char * const pxa27x_steppings[16] = { "step A-0", "step A-1", "step B-0", "step B-1", "step C-0", "rev 5", "rev 6", "rev 7", "rev 8", "rev 9", "rev 10", "rev 11", "rev 12", "rev 13", "rev 14", "rev 15", }; static const char * const ixp425_steppings[16] = { "step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3", "rev 4", "rev 5", "rev 6", "rev 7", "rev 8", "rev 9", "rev 10", "rev 11", "rev 12", "rev 13", "rev 14", "rev 15", }; struct cpuidtab { u_int32_t cpuid; enum cpu_class cpu_class; const char *cpu_name; const char * const *cpu_steppings; }; const struct cpuidtab cpuids[] = { { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", generic_steppings }, { CPU_ID_ARM920T_ALT, CPU_CLASS_ARM9TDMI, "ARM920T", generic_steppings }, { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", generic_steppings }, { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", generic_steppings }, { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", generic_steppings }, { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", generic_steppings }, { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", generic_steppings }, { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", generic_steppings }, { CPU_ID_FA526, CPU_CLASS_ARM9TDMI, "FA526", generic_steppings }, { CPU_ID_FA626TE, CPU_CLASS_ARM9ES, "FA626TE", generic_steppings }, { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", generic_steppings }, { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", generic_steppings }, { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", generic_steppings }, { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", generic_steppings }, { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", xscale_steppings }, { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", i80321_steppings }, { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", i80321_steppings }, { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", i80321_steppings }, { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", i80321_steppings }, { CPU_ID_81342, CPU_CLASS_XSCALE, "i81342", i81342_steppings }, { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", i80219_steppings }, { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", i80219_steppings }, { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", pxa27x_steppings }, { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", pxa2x0_steppings }, { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", pxa2x0_steppings }, { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", pxa2x0_steppings }, { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", pxa2x0_steppings }, { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255", pxa255_steppings }, { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", pxa2x0_steppings }, { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", ixp425_steppings }, { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", ixp425_steppings }, { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", ixp425_steppings }, /* XXX ixp435 steppings? */ { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435", ixp425_steppings }, { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131", generic_steppings }, { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", generic_steppings }, { 0, CPU_CLASS_NONE, NULL, NULL } }; struct cpu_classtab { const char *class_name; const char *class_option; }; const struct cpu_classtab cpu_classes[] = { { "unknown", NULL }, /* CPU_CLASS_NONE */ { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */ { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ { "Marvell", "CPU_MARVELL" }, /* CPU_CLASS_MARVELL */ }; /* * Report the type of the specified arm processor. This uses the generic and * arm specific information in the cpu structure to identify the processor. * The remaining fields in the cpu structure are filled in appropriately. */ static const char * const wtnames[] = { "write-through", "write-back", "write-back", "**unknown 3**", "**unknown 4**", "write-back-locking", /* XXX XScale-specific? */ "write-back-locking-A", "write-back-locking-B", "**unknown 8**", "**unknown 9**", "**unknown 10**", "**unknown 11**", "**unknown 12**", "**unknown 13**", "write-back-locking-C", "**unknown 15**", }; static void print_enadis(int enadis, char *s) { printf(" %s %sabled", s, (enadis == 0) ? "dis" : "en"); } enum cpu_class cpu_class = CPU_CLASS_NONE; u_int cpu_pfr(int num) { u_int feat; switch (num) { case 0: __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (feat)); break; case 1: __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (feat)); break; default: panic("Processor Feature Register %d not implemented", num); break; } return (feat); } void identify_arm_cpu(void) { u_int cpuid, ctrl; int i; ctrl = cpu_get_control(); cpuid = cpu_ident(); if (cpuid == 0) { printf("Processor failed probe - no CPU ID\n"); return; } for (i = 0; cpuids[i].cpuid != 0; i++) if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { cpu_class = cpuids[i].cpu_class; printf("CPU: %s %s (%s core)\n", cpuids[i].cpu_name, cpuids[i].cpu_steppings[cpuid & CPU_ID_REVISION_MASK], cpu_classes[cpu_class].class_name); break; } if (cpuids[i].cpuid == 0) printf("unknown CPU (ID = 0x%x)\n", cpuid); printf(" "); if (ctrl & CPU_CONTROL_BEND_ENABLE) printf(" Big-endian"); else printf(" Little-endian"); switch (cpu_class) { case CPU_CLASS_ARM9TDMI: case CPU_CLASS_ARM9ES: case CPU_CLASS_ARM9EJS: case CPU_CLASS_ARM10E: case CPU_CLASS_ARM10EJ: case CPU_CLASS_XSCALE: case CPU_CLASS_MARVELL: print_enadis(ctrl & CPU_CONTROL_DC_ENABLE, "DC"); print_enadis(ctrl & CPU_CONTROL_IC_ENABLE, "IC"); #ifdef CPU_XSCALE_81342 print_enadis(ctrl & CPU_CONTROL_L2_ENABLE, "L2"); #endif #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) i = sheeva_control_ext(0, 0); print_enadis(i & MV_WA_ENABLE, "WA"); print_enadis(i & MV_DC_STREAM_ENABLE, "DC streaming"); printf("\n "); print_enadis((i & MV_BTB_DISABLE) == 0, "BTB"); print_enadis(i & MV_L2_ENABLE, "L2"); print_enadis((i & MV_L2_PREFETCH_DISABLE) == 0, "L2 prefetch"); printf("\n "); #endif break; default: break; } print_enadis(ctrl & CPU_CONTROL_WBUF_ENABLE, "WB"); if (ctrl & CPU_CONTROL_LABT_ENABLE) printf(" LABT"); else printf(" EABT"); print_enadis(ctrl & CPU_CONTROL_BPRD_ENABLE, "branch prediction"); printf("\n"); /* Print cache info. */ if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) return; if (arm_pcache_unified) { printf(" %dKB/%dB %d-way %s unified cache\n", arm_pdcache_size / 1024, arm_pdcache_line_size, arm_pdcache_ways, wtnames[arm_pcache_type]); } else { printf(" %dKB/%dB %d-way instruction cache\n", arm_picache_size / 1024, arm_picache_line_size, arm_picache_ways); printf(" %dKB/%dB %d-way %s data cache\n", arm_pdcache_size / 1024, arm_pdcache_line_size, arm_pdcache_ways, wtnames[arm_pcache_type]); } } diff --git a/sys/arm/arm/identcpu-v6.c b/sys/arm/arm/identcpu-v6.c index 55d331c2ffba..7cc8170325cb 100644 --- a/sys/arm/arm/identcpu-v6.c +++ b/sys/arm/arm/identcpu-v6.c @@ -1,360 +1,360 @@ /* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ /*- * Copyright (c) 1995 Mark Brinicombe. * Copyright (c) 1995 Brini. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * cpu.c * * Probing and configuration for the master CPU * * Created : 10/10/95 */ #include __FBSDID("$FreeBSD$"); -#include #include +#include #include #include #include #include #include char machine[] = "arm"; SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "Machine class"); static char hw_buf[81]; static int hw_buf_idx; static bool hw_buf_newline; static struct { int implementer; int part_number; char *impl_name; char *core_name; } cpu_names[] = { {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176, "ARM", "ARM1176"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72"}, {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73"}, {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marwell", "PJ4 v7"}, {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marwell", "PJ4MP v7"}, {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300"}, }; static void print_v5_cache(void) { uint32_t isize, dsize; uint32_t multiplier; int pcache_type; int pcache_unified; int picache_size; int picache_line_size; int picache_ways; int pdcache_size; int pdcache_line_size; int pdcache_ways; pcache_unified = 0; picache_size = 0 ; picache_line_size = 0 ; picache_ways = 0 ; pdcache_size = 0; pdcache_line_size = 0; pdcache_ways = 0; if ((cpuinfo.ctr & CPU_CT_S) == 0) pcache_unified = 1; /* * If you want to know how this code works, go read the ARM ARM. */ pcache_type = CPU_CT_CTYPE(cpuinfo.ctr); if (pcache_unified == 0) { isize = CPU_CT_ISIZE(cpuinfo.ctr); multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2; picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3); if (CPU_CT_xSIZE_ASSOC(isize) == 0) { if (isize & CPU_CT_xSIZE_M) picache_line_size = 0; /* not present */ else picache_ways = 1; } else { picache_ways = multiplier << (CPU_CT_xSIZE_ASSOC(isize) - 1); } picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8); } dsize = CPU_CT_DSIZE(cpuinfo.ctr); multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2; pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3); if (CPU_CT_xSIZE_ASSOC(dsize) == 0) { if (dsize & CPU_CT_xSIZE_M) pdcache_line_size = 0; /* not present */ else pdcache_ways = 1; } else { pdcache_ways = multiplier << (CPU_CT_xSIZE_ASSOC(dsize) - 1); } pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8); /* Print cache info. */ if (picache_line_size == 0 && pdcache_line_size == 0) return; if (pcache_unified) { printf(" %dKB/%dB %d-way %s unified cache\n", pdcache_size / 1024, pdcache_line_size, pdcache_ways, pcache_type == 0 ? "WT" : "WB"); } else { printf(" %dKB/%dB %d-way instruction cache\n", picache_size / 1024, picache_line_size, picache_ways); printf(" %dKB/%dB %d-way %s data cache\n", pdcache_size / 1024, pdcache_line_size, pdcache_ways, pcache_type == 0 ? "WT" : "WB"); } } static void print_v7_cache(void ) { uint32_t type, val, size, sets, ways, linesize; int i; printf("LoUU:%d LoC:%d LoUIS:%d \n", CPU_CLIDR_LOUU(cpuinfo.clidr) + 1, CPU_CLIDR_LOC(cpuinfo.clidr) + 1, CPU_CLIDR_LOUIS(cpuinfo.clidr) + 1); for (i = 0; i < 7; i++) { type = CPU_CLIDR_CTYPE(cpuinfo.clidr, i); if (type == 0) break; printf("Cache level %d:\n", i + 1); if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE || type == CACHE_SEP_CACHE) { cp15_csselr_set(i << 1); val = cp15_ccsidr_get(); ways = CPUV7_CT_xSIZE_ASSOC(val) + 1; sets = CPUV7_CT_xSIZE_SET(val) + 1; linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4); size = (ways * sets * linesize) / 1024; if (type == CACHE_UNI_CACHE) printf(" %dKB/%dB %d-way unified cache", size, linesize,ways); else printf(" %dKB/%dB %d-way data cache", size, linesize, ways); if (val & CPUV7_CT_CTYPE_WT) printf(" WT"); if (val & CPUV7_CT_CTYPE_WB) printf(" WB"); if (val & CPUV7_CT_CTYPE_RA) printf(" Read-Alloc"); if (val & CPUV7_CT_CTYPE_WA) printf(" Write-Alloc"); printf("\n"); } if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) { cp15_csselr_set(i << 1 | 1); val = cp15_ccsidr_get(); ways = CPUV7_CT_xSIZE_ASSOC(val) + 1; sets = CPUV7_CT_xSIZE_SET(val) + 1; linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4); size = (ways * sets * linesize) / 1024; printf(" %dKB/%dB %d-way instruction cache", size, linesize, ways); if (val & CPUV7_CT_CTYPE_WT) printf(" WT"); if (val & CPUV7_CT_CTYPE_WB) printf(" WB"); if (val & CPUV7_CT_CTYPE_RA) printf(" Read-Alloc"); if (val & CPUV7_CT_CTYPE_WA) printf(" Write-Alloc"); printf("\n"); } } cp15_csselr_set(0); } static void add_cap(char *cap) { int len; len = strlen(cap); if ((hw_buf_idx + len + 2) >= 79) { printf("%s,\n", hw_buf); hw_buf_idx = 0; hw_buf_newline = true; } if (hw_buf_newline) hw_buf_idx += sprintf(hw_buf + hw_buf_idx, " "); else hw_buf_idx += sprintf(hw_buf + hw_buf_idx, ", "); hw_buf_newline = false; hw_buf_idx += sprintf(hw_buf + hw_buf_idx, "%s", cap); } void identify_arm_cpu(void) { int i; u_int val; /* * CPU */ for(i = 0; i < nitems(cpu_names); i++) { if (cpu_names[i].implementer == cpuinfo.implementer && cpu_names[i].part_number == cpuinfo.part_number) { printf("CPU: %s %s r%dp%d (ECO: 0x%08X)\n", cpu_names[i].impl_name, cpu_names[i].core_name, cpuinfo.revision, cpuinfo.patch, cpuinfo.midr != cpuinfo.revidr ? cpuinfo.revidr : 0); break; } } if (i >= nitems(cpu_names)) printf("unknown CPU (ID = 0x%x)\n", cpuinfo.midr); printf("CPU Features: \n"); hw_buf_idx = 0; hw_buf_newline = true; val = (cpuinfo.mpidr >> 4)& 0xF; if (cpuinfo.mpidr & (1 << 31U)) add_cap("Multiprocessing"); val = (cpuinfo.id_pfr0 >> 4)& 0xF; if (val == 1) add_cap("Thumb"); else if (val == 3) add_cap("Thumb2"); val = (cpuinfo.id_pfr1 >> 4)& 0xF; if (val == 1 || val == 2) add_cap("Security"); val = (cpuinfo.id_pfr1 >> 12)& 0xF; if (val == 1) add_cap("Virtualization"); val = (cpuinfo.id_pfr1 >> 16)& 0xF; if (val == 1) add_cap("Generic Timer"); val = (cpuinfo.id_mmfr0 >> 0)& 0xF; if (val == 2) { add_cap("VMSAv6"); } else if (val >= 3) { add_cap("VMSAv7"); if (val >= 4) add_cap("PXN"); if (val >= 5) add_cap("LPAE"); } val = (cpuinfo.id_mmfr3 >> 20)& 0xF; if (val == 1) add_cap("Coherent Walk"); if (hw_buf_idx != 0) printf("%s\n", hw_buf); printf("Optional instructions: \n"); hw_buf_idx = 0; hw_buf_newline = true; val = (cpuinfo.id_isar0 >> 24)& 0xF; if (val == 1) add_cap("SDIV/UDIV (Thumb)"); else if (val == 2) add_cap("SDIV/UDIV"); val = (cpuinfo.id_isar2 >> 20)& 0xF; if (val == 1 || val == 2) add_cap("UMULL"); val = (cpuinfo.id_isar2 >> 16)& 0xF; if (val == 1 || val == 2 || val == 3) add_cap("SMULL"); val = (cpuinfo.id_isar2 >> 12)& 0xF; if (val == 1) add_cap("MLA"); val = (cpuinfo.id_isar3 >> 4)& 0xF; if (val == 1) add_cap("SIMD"); else if (val == 3) add_cap("SIMD(ext)"); if (hw_buf_idx != 0) printf("%s\n", hw_buf); /* * Cache */ if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7) print_v7_cache(); else print_v5_cache(); } diff --git a/sys/arm/arm/stack_machdep.c b/sys/arm/arm/stack_machdep.c index 6d23be6edc7e..df232a957978 100644 --- a/sys/arm/arm/stack_machdep.c +++ b/sys/arm/arm/stack_machdep.c @@ -1,89 +1,89 @@ /*- * Copyright (c) 2005 Antoine Brodin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); -#include #include +#include #include #include #include #include #include /* * This code makes assumptions about the stack layout. These are correct * when using APCS (the old ABI), but are no longer true with AAPCS and the * ARM EABI. There is also an issue with clang and llvm when building for * APCS where it lays out the stack incorrectly. Because of this we disable * this when building for ARM EABI or when building with clang. */ extern vm_offset_t kernel_vm_end; static void stack_capture(struct stack *st, u_int32_t *frame) { } void stack_save_td(struct stack *st, struct thread *td) { u_int32_t *frame; if (TD_IS_SWAPPED(td)) panic("stack_save_td: swapped"); if (TD_IS_RUNNING(td)) panic("stack_save_td: running"); /* * This register, the frame pointer, is incorrect for the ARM EABI * as it doesn't have a frame pointer, however it's value is not used * when building for EABI. */ frame = (u_int32_t *)td->td_pcb->pcb_regs.sf_r11; stack_zero(st); stack_capture(st, frame); } int stack_save_td_running(struct stack *st, struct thread *td) { return (EOPNOTSUPP); } void stack_save(struct stack *st) { u_int32_t *frame; frame = (u_int32_t *)__builtin_frame_address(0); stack_zero(st); stack_capture(st, frame); } diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h index 4c404dc4bf74..ed87fb402b1b 100644 --- a/sys/arm/include/atomic.h +++ b/sys/arm/include/atomic.h @@ -1,123 +1,122 @@ /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */ /*- * Copyright (C) 2003-2004 Olivier Houchard * Copyright (C) 1994-1997 Mark Brinicombe * Copyright (C) 1994 Brini * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of Brini may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_ATOMIC_H_ #define _MACHINE_ATOMIC_H_ -#include #include #ifndef _KERNEL #include #endif #if __ARM_ARCH >= 6 #include #else /* < armv6 */ #include #endif /* Arch >= v6 */ static __inline int atomic_load_32(volatile uint32_t *v) { return (*v); } static __inline void atomic_store_32(volatile uint32_t *dst, uint32_t src) { *dst = src; } static __inline int atomic_load_long(volatile u_long *v) { return (*v); } static __inline void atomic_store_long(volatile u_long *dst, u_long src) { *dst = src; } #define atomic_clear_ptr atomic_clear_32 #define atomic_clear_acq_ptr atomic_clear_acq_32 #define atomic_clear_rel_ptr atomic_clear_rel_32 #define atomic_set_ptr atomic_set_32 #define atomic_set_acq_ptr atomic_set_acq_32 #define atomic_set_rel_ptr atomic_set_rel_32 #define atomic_fcmpset_ptr atomic_fcmpset_32 #define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_32 #define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_32 #define atomic_cmpset_ptr atomic_cmpset_32 #define atomic_cmpset_acq_ptr atomic_cmpset_acq_32 #define atomic_cmpset_rel_ptr atomic_cmpset_rel_32 #define atomic_load_acq_ptr atomic_load_acq_32 #define atomic_store_ptr atomic_store_32 #define atomic_store_rel_ptr atomic_store_rel_32 #define atomic_swap_ptr atomic_swap_32 #define atomic_readandclear_ptr atomic_readandclear_32 #define atomic_add_int atomic_add_32 #define atomic_add_acq_int atomic_add_acq_32 #define atomic_add_rel_int atomic_add_rel_32 #define atomic_subtract_int atomic_subtract_32 #define atomic_subtract_acq_int atomic_subtract_acq_32 #define atomic_subtract_rel_int atomic_subtract_rel_32 #define atomic_clear_int atomic_clear_32 #define atomic_clear_acq_int atomic_clear_acq_32 #define atomic_clear_rel_int atomic_clear_rel_32 #define atomic_set_int atomic_set_32 #define atomic_set_acq_int atomic_set_acq_32 #define atomic_set_rel_int atomic_set_rel_32 #define atomic_fcmpset_int atomic_fcmpset_32 #define atomic_fcmpset_acq_int atomic_fcmpset_acq_32 #define atomic_fcmpset_rel_int atomic_fcmpset_rel_32 #define atomic_cmpset_int atomic_cmpset_32 #define atomic_cmpset_acq_int atomic_cmpset_acq_32 #define atomic_cmpset_rel_int atomic_cmpset_rel_32 #define atomic_fetchadd_int atomic_fetchadd_32 #define atomic_readandclear_int atomic_readandclear_32 #define atomic_load_acq_int atomic_load_acq_32 #define atomic_store_rel_int atomic_store_rel_32 #define atomic_swap_int atomic_swap_32 #endif /* _MACHINE_ATOMIC_H_ */ diff --git a/sys/contrib/vchiq/interface/compat/vchi_bsd.h b/sys/contrib/vchiq/interface/compat/vchi_bsd.h index d2991a9085f0..107041ac37b9 100644 --- a/sys/contrib/vchiq/interface/compat/vchi_bsd.h +++ b/sys/contrib/vchiq/interface/compat/vchi_bsd.h @@ -1,436 +1,436 @@ /*- * Copyright (c) 2010 Max Khon * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2013 Jared D. McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef __VCHI_BSD_H__ #define __VCHI_BSD_H__ -#include #include +#include #include #include #include #include #include #include #include #include #include #include #include #include #include /* * Copy from/to user API */ #define copy_from_user(to, from, n) copyin((from), (to), (n)) #define copy_to_user(to, from, n) copyout((from), (to), (n)) /* * Bit API */ static __inline int test_and_set_bit(int nr, volatile void *addr) { int val; do { val = *(volatile int *) addr; } while (atomic_cmpset_int(addr, val, val | (1 << nr)) == 0); return (val & (1 << nr)); } static __inline__ int test_and_clear_bit(int nr, volatile void *addr) { int val; do { val = *(volatile int *) addr; } while (atomic_cmpset_int(addr, val, val & ~(1 << nr)) == 0); return (val & (1 << nr)); } /* * Atomic API */ typedef volatile unsigned atomic_t; #define atomic_set(p, v) (*(p) = (v)) #define atomic_read(p) (*(p)) #define atomic_inc(p) atomic_add_int(p, 1) #define atomic_dec(p) atomic_subtract_int(p, 1) #define atomic_dec_and_test(p) (atomic_fetchadd_int(p, -1) == 1) #define atomic_inc_return(v) atomic_add_return(1, (v)) #define atomic_dec_return(v) atomic_sub_return(1, (v)) #define atomic_add(v, p) atomic_add_int(p, v) #define atomic_sub(v, p) atomic_subtract_int(p, v) #define ATOMIC_INIT(v) (v) static inline int atomic_add_return(int i, atomic_t *v) { return i + atomic_fetchadd_int(v, i); } static inline int atomic_sub_return(int i, atomic_t *v) { return atomic_fetchadd_int(v, -i) - i; } static inline int atomic_cmpxchg(atomic_t *v, int oldv, int newv) { if (atomic_cmpset_rel_int(v, oldv, newv)) return newv; else return *v; } static inline int atomic_xchg(atomic_t *v, int newv) { int oldv; if (newv == 0) return atomic_readandclear_int(v); else { do { oldv = atomic_load_acq_int(v); } while (!atomic_cmpset_rel_int(v, oldv, newv)); } return (oldv); } /* * Spinlock API */ typedef struct mtx spinlock_t; #define DEFINE_SPINLOCK(name) \ struct mtx name #define spin_lock_init(lock) mtx_init(lock, "VCHI spinlock " # lock, NULL, MTX_DEF) #define spin_lock_destroy(lock) mtx_destroy(lock) #define spin_lock(lock) mtx_lock(lock) #define spin_unlock(lock) mtx_unlock(lock) #define spin_lock_bh(lock) spin_lock(lock) #define spin_unlock_bh(lock) spin_unlock(lock) /* * Mutex API */ struct mutex { struct sx mtx; }; #define lmutex_init(lock) sx_init(&(lock)->mtx, #lock) #define lmutex_lock(lock) sx_xlock(&(lock)->mtx) #define lmutex_unlock(lock) sx_unlock(&(lock)->mtx) #define lmutex_destroy(lock) sx_destroy(&(lock)->mtx) #define lmutex_lock_interruptible(lock) sx_xlock_sig(&(lock)->mtx) /* * Rwlock API */ typedef struct rwlock rwlock_t; #if defined(SX_ADAPTIVESPIN) && !defined(SX_NOADAPTIVE) #define SX_NOADAPTIVE SX_ADAPTIVESPIN #endif #define DEFINE_RWLOCK(name) \ struct rwlock name; \ SX_SYSINIT(name, &name, #name) #define rwlock_init(rwlock) rw_init(rwlock, "VCHI rwlock") #define read_lock(rwlock) rw_rlock(rwlock) #define read_unlock(rwlock) rw_unlock(rwlock) #define write_lock(rwlock) rw_wlock(rwlock) #define write_unlock(rwlock) rw_unlock(rwlock) #define write_lock_irqsave(rwlock, flags) \ do { \ rw_wlock(rwlock); \ (void) &(flags); \ } while (0) #define write_unlock_irqrestore(rwlock, flags) \ rw_unlock(rwlock) #define read_lock_bh(rwlock) rw_rlock(rwlock) #define read_unlock_bh(rwlock) rw_unlock(rwlock) #define write_lock_bh(rwlock) rw_wlock(rwlock) #define write_unlock_bh(rwlock) rw_unlock(rwlock) /* * Timer API */ struct timer_list { struct mtx mtx; struct callout callout; unsigned long expires; void (*function)(unsigned long); unsigned long data; }; void init_timer(struct timer_list *t); void setup_timer(struct timer_list *t, void (*function)(unsigned long), unsigned long data); void mod_timer(struct timer_list *t, unsigned long expires); void add_timer(struct timer_list *t); int del_timer(struct timer_list *t); int del_timer_sync(struct timer_list *t); /* * Completion API */ struct completion { struct cv cv; struct mtx lock; int done; }; void init_completion(struct completion *c); void destroy_completion(struct completion *c); int try_wait_for_completion(struct completion *); int wait_for_completion_interruptible(struct completion *); int wait_for_completion_interruptible_timeout(struct completion *, unsigned long ticks); int wait_for_completion_killable(struct completion *); void wait_for_completion(struct completion *c); void complete(struct completion *c); void complete_all(struct completion *c); void INIT_COMPLETION_locked(struct completion *c); #define INIT_COMPLETION(x) INIT_COMPLETION_locked(&(x)) /* * Semaphore API */ struct semaphore { struct mtx mtx; struct cv cv; int value; int waiters; }; #define DEFINE_SEMAPHORE(name) \ struct semaphore name; \ SYSINIT(name##_sema_sysinit, SI_SUB_LOCK, SI_ORDER_MIDDLE, \ sema_sysinit, &name); \ SYSUNINIT(name##_sema_sysuninit, SI_SUB_LOCK, SI_ORDER_MIDDLE, \ _sema_destroy, __DEVOLATILE(void *, &(name))) void sema_sysinit(void *arg); void _sema_init(struct semaphore *s, int value); void _sema_destroy(struct semaphore *s); void down(struct semaphore *s); int down_interruptible(struct semaphore *s); int down_trylock(struct semaphore *s); void up(struct semaphore *s); /* * Logging and assertions API */ void rlprintf(int pps, const char *fmt, ...) __printflike(2, 3); void device_rlprintf(int pps, device_t dev, const char *fmt, ...) __printflike(3, 4); #define might_sleep() #define WARN(condition, msg) \ ({ \ int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on)) \ printf((msg)); \ unlikely(__ret_warn_on); \ }) #define WARN_ON(condition) \ ({ \ int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on)) \ printf("WARN_ON: " #condition "\n"); \ unlikely(__ret_warn_on); \ }) #define WARN_ON_ONCE(condition) ({ \ static int __warned; \ int __ret_warn_once = !!(condition); \ \ if (unlikely(__ret_warn_once)) \ if (WARN_ON(!__warned)) \ __warned = 1; \ unlikely(__ret_warn_once); \ }) #define BUG_ON(cond) \ do { \ if (cond) \ panic("BUG_ON: " #cond); \ } while (0) #define BUG() \ do { \ panic("BUG: %s:%d", __FILE__, __LINE__); \ } while (0) #define vchiq_static_assert(cond) CTASSERT(cond) #define KERN_EMERG "<0>" /* system is unusable */ #define KERN_ALERT "<1>" /* action must be taken immediately */ #define KERN_CRIT "<2>" /* critical conditions */ #define KERN_ERR "<3>" /* error conditions */ #define KERN_WARNING "<4>" /* warning conditions */ #define KERN_NOTICE "<5>" /* normal but significant condition */ #define KERN_INFO "<6>" /* informational */ #define KERN_DEBUG "<7>" /* debug-level messages */ #define KERN_CONT "" #define printk(fmt, args...) printf(fmt, ##args) #define vprintk(fmt, args) vprintf(fmt, args) /* * Malloc API */ #define GFP_KERNEL 0 #define GFP_ATOMIC 0 MALLOC_DECLARE(M_VCHI); #define kmalloc(size, flags) malloc((size), M_VCHI, M_NOWAIT | M_ZERO) #define kcalloc(n, size, flags) malloc((n) * (size), M_VCHI, M_NOWAIT | M_ZERO) #define kzalloc(a, b) kcalloc(1, (a), (b)) #define kfree(p) free(p, M_VCHI) /* * Kernel module API */ #define __init #define __exit #define __devinit #define __devexit #define __devinitdata /* * Time API */ #if 1 /* emulate jiffies */ static inline unsigned long _jiffies(void) { struct timeval tv; microuptime(&tv); return tvtohz(&tv); } static inline unsigned long msecs_to_jiffies(unsigned long msecs) { struct timeval tv; tv.tv_sec = msecs / 1000000UL; tv.tv_usec = msecs % 1000000UL; return tvtohz(&tv); } #define jiffies _jiffies() #else #define jiffies ticks #endif #define HZ hz #define udelay(usec) DELAY(usec) #define mdelay(msec) DELAY((msec) * 1000) #define schedule_timeout(jiff) pause("dhdslp", jiff) #if defined(msleep) #undef msleep #endif #define msleep(msec) mdelay(msec) #define time_after(a, b) ((a) > (b)) #define time_after_eq(a, b) ((a) >= (b)) #define time_before(a, b) time_after((b), (a)) /* * kthread API (we use proc) */ typedef struct proc * VCHIQ_THREAD_T; VCHIQ_THREAD_T vchiq_thread_create(int (*threadfn)(void *data), void *data, const char namefmt[], ...); void set_user_nice(VCHIQ_THREAD_T p, int nice); void wake_up_process(VCHIQ_THREAD_T p); /* * Proc APIs */ void flush_signals(VCHIQ_THREAD_T); int fatal_signal_pending(VCHIQ_THREAD_T); /* * mbox API */ void bcm_mbox_write(int channel, uint32_t data); /* * Misc API */ #define ENODATA EINVAL #define __user #define likely(x) __builtin_expect(!!(x), 1) #define unlikely(x) __builtin_expect(!!(x), 0) #define current curproc #define EXPORT_SYMBOL(x) #define PAGE_ALIGN(addr) round_page(addr) typedef void irqreturn_t; typedef off_t loff_t; #define BCM2835_MBOX_CHAN_VCHIQ 3 #define smp_mb wmb #define smp_rmb rmb #define smp_wmb wmb #define device_print_prettyname(dev) device_printf((dev), "") #endif /* __VCHI_BSD_H__ */