diff --git a/sys/dev/ixgbe/ixgbe_82599.c b/sys/dev/ixgbe/ixgbe_82599.c index 15febd08352e..1f81f6109f1b 100644 --- a/sys/dev/ixgbe/ixgbe_82599.c +++ b/sys/dev/ixgbe/ixgbe_82599.c @@ -1,2640 +1,2640 @@ /****************************************************************************** SPDX-License-Identifier: BSD-3-Clause Copyright (c) 2001-2017, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ /*$FreeBSD$*/ #include "ixgbe_type.h" #include "ixgbe_82599.h" #include "ixgbe_api.h" #include "ixgbe_common.h" #include "ixgbe_phy.h" #define IXGBE_82599_MAX_TX_QUEUES 128 #define IXGBE_82599_MAX_RX_QUEUES 128 #define IXGBE_82599_RAR_ENTRIES 128 #define IXGBE_82599_MC_TBL_SIZE 128 #define IXGBE_82599_VFT_TBL_SIZE 128 #define IXGBE_82599_RX_PB_SIZE 512 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete); static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, u16 offset, u16 *data); static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data); static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data); static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data); void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) { struct ixgbe_mac_info *mac = &hw->mac; DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); /* * enable the laser control functions for SFP+ fiber * and MNG not enabled */ if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && !ixgbe_mng_enabled(hw)) { mac->ops.disable_tx_laser = ixgbe_disable_tx_laser_multispeed_fiber; mac->ops.enable_tx_laser = ixgbe_enable_tx_laser_multispeed_fiber; mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber; } else { mac->ops.disable_tx_laser = NULL; mac->ops.enable_tx_laser = NULL; mac->ops.flap_tx_laser = NULL; } if (hw->phy.multispeed_fiber) { /* Set up dual speed SFP+ support */ mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; mac->ops.set_rate_select_speed = ixgbe_set_hard_rate_select_speed; if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed) mac->ops.set_rate_select_speed = ixgbe_set_soft_rate_select_speed; } else { if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && (hw->phy.smart_speed == ixgbe_smart_speed_auto || hw->phy.smart_speed == ixgbe_smart_speed_on) && !ixgbe_verify_lesm_fw_enabled_82599(hw)) { mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed; } else { mac->ops.setup_link = ixgbe_setup_mac_link_82599; } } } /** * ixgbe_init_phy_ops_82599 - PHY/SFP specific init * @hw: pointer to hardware structure * * Initialize any function pointers that were not able to be * set during init_shared_code because the PHY/SFP type was * not known. Perform the SFP init if necessary. * **/ s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) { struct ixgbe_mac_info *mac = &hw->mac; struct ixgbe_phy_info *phy = &hw->phy; s32 ret_val = IXGBE_SUCCESS; u32 esdp; DEBUGFUNC("ixgbe_init_phy_ops_82599"); if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { /* Store flag indicating I2C bus access control unit. */ hw->phy.qsfp_shared_i2c_bus = TRUE; /* Initialize access to QSFP+ I2C bus */ esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); esdp |= IXGBE_ESDP_SDP0_DIR; esdp &= ~IXGBE_ESDP_SDP1_DIR; esdp &= ~IXGBE_ESDP_SDP0; esdp &= ~IXGBE_ESDP_SDP0_NATIVE; esdp &= ~IXGBE_ESDP_SDP1_NATIVE; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599; phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599; } /* Identify the PHY or SFP module */ ret_val = phy->ops.identify(hw); if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) goto init_phy_ops_out; /* Setup function pointers based on detected SFP module and speeds */ ixgbe_init_mac_link_ops_82599(hw); if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) hw->phy.ops.reset = NULL; /* If copper media, overwrite with copper function pointers */ if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { mac->ops.setup_link = ixgbe_setup_copper_link_82599; mac->ops.get_link_capabilities = ixgbe_get_copper_link_capabilities_generic; } /* Set necessary function pointers based on PHY type */ switch (hw->phy.type) { case ixgbe_phy_tn: phy->ops.setup_link = ixgbe_setup_phy_link_tnx; phy->ops.check_link = ixgbe_check_phy_link_tnx; phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_tnx; break; default: break; } init_phy_ops_out: return ret_val; } s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) { s32 ret_val = IXGBE_SUCCESS; u16 list_offset, data_offset, data_value; DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { ixgbe_init_mac_link_ops_82599(hw); hw->phy.ops.reset = NULL; ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, &data_offset); if (ret_val != IXGBE_SUCCESS) goto setup_sfp_out; /* PHY config will finish before releasing the semaphore */ ret_val = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); if (ret_val != IXGBE_SUCCESS) { ret_val = IXGBE_ERR_SWFW_SYNC; goto setup_sfp_out; } if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) goto setup_sfp_err; while (data_value != 0xffff) { IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); IXGBE_WRITE_FLUSH(hw); if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) goto setup_sfp_err; } /* Release the semaphore */ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); /* Delay obtaining semaphore again to allow FW access * prot_autoc_write uses the semaphore too. */ msec_delay(hw->eeprom.semaphore_delay); /* Restart DSP and set SFI mode */ ret_val = hw->mac.ops.prot_autoc_write(hw, hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, FALSE); if (ret_val) { DEBUGOUT("sfp module setup not complete\n"); ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; goto setup_sfp_out; } } setup_sfp_out: return ret_val; setup_sfp_err: /* Release the semaphore */ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); /* Delay obtaining semaphore again to allow FW access */ msec_delay(hw->eeprom.semaphore_delay); ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, "eeprom read at offset %d failed", data_offset); return IXGBE_ERR_PHY; } /** * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read * @hw: pointer to hardware structure * @locked: Return the if we locked for this read. * @reg_val: Value we read from AUTOC * * For this part (82599) we need to wrap read-modify-writes with a possible * FW/SW lock. It is assumed this lock will be freed with the next * prot_autoc_write_82599(). */ s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) { s32 ret_val; *locked = FALSE; /* If LESM is on then we need to hold the SW/FW semaphore. */ if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { ret_val = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); if (ret_val != IXGBE_SUCCESS) return IXGBE_ERR_SWFW_SYNC; *locked = TRUE; } *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); return IXGBE_SUCCESS; } /** * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write * @hw: pointer to hardware structure * @autoc: value to write to AUTOC * @locked: bool to indicate whether the SW/FW lock was already taken by * previous proc_autoc_read_82599. * * This part (82599) may need to hold the SW/FW lock around all writes to * AUTOC. Likewise after a write we need to do a pipeline reset. */ s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) { s32 ret_val = IXGBE_SUCCESS; /* Blocked by MNG FW so bail */ if (ixgbe_check_reset_blocked(hw)) goto out; /* We only need to get the lock if: * - We didn't do it already (in the read part of a read-modify-write) * - LESM is enabled. */ if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { ret_val = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); if (ret_val != IXGBE_SUCCESS) return IXGBE_ERR_SWFW_SYNC; locked = TRUE; } IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); ret_val = ixgbe_reset_pipeline_82599(hw); out: /* Free the SW/FW semaphore as we either grabbed it here or * already had it when this function was called. */ if (locked) hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); return ret_val; } /** * ixgbe_init_ops_82599 - Inits func ptrs and MAC type * @hw: pointer to hardware structure * * Initialize the function pointers and assign the MAC type for 82599. * Does not touch the hardware. **/ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) { struct ixgbe_mac_info *mac = &hw->mac; struct ixgbe_phy_info *phy = &hw->phy; struct ixgbe_eeprom_info *eeprom = &hw->eeprom; s32 ret_val; DEBUGFUNC("ixgbe_init_ops_82599"); ixgbe_init_phy_ops_generic(hw); ret_val = ixgbe_init_ops_generic(hw); /* PHY */ phy->ops.identify = ixgbe_identify_phy_82599; phy->ops.init = ixgbe_init_phy_ops_82599; /* MAC */ mac->ops.reset_hw = ixgbe_reset_hw_82599; mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; mac->ops.get_media_type = ixgbe_get_media_type_82599; mac->ops.get_supported_physical_layer = ixgbe_get_supported_physical_layer_82599; mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599; mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599; mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599; mac->ops.start_hw = ixgbe_start_hw_82599; mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; mac->ops.get_device_caps = ixgbe_get_device_caps_generic; mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; mac->ops.prot_autoc_read = prot_autoc_read_82599; mac->ops.prot_autoc_write = prot_autoc_write_82599; /* RAR, Multicast, VLAN */ mac->ops.set_vmdq = ixgbe_set_vmdq_generic; mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; mac->rar_highwater = 1; mac->ops.set_vfta = ixgbe_set_vfta_generic; mac->ops.set_vlvf = ixgbe_set_vlvf_generic; mac->ops.clear_vfta = ixgbe_clear_vfta_generic; mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599; mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; /* Link */ mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599; mac->ops.check_link = ixgbe_check_mac_link_generic; mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; ixgbe_init_mac_link_ops_82599(hw); mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) & IXGBE_FWSM_MODE_MASK); hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; /* EEPROM */ eeprom->ops.read = ixgbe_read_eeprom_82599; eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599; /* Manageability interface */ mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; mac->ops.bypass_rw = ixgbe_bypass_rw_generic; mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; mac->ops.bypass_set = ixgbe_bypass_set_generic; mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; return ret_val; } /** * ixgbe_get_link_capabilities_82599 - Determines link capabilities * @hw: pointer to hardware structure * @speed: pointer to link speed * @autoneg: TRUE when autoneg or autotry is enabled * * Determines the link capabilities by reading the AUTOC register. **/ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg) { s32 status = IXGBE_SUCCESS; u32 autoc = 0; DEBUGFUNC("ixgbe_get_link_capabilities_82599"); /* Check if 1G SFP module. */ if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { *speed = IXGBE_LINK_SPEED_1GB_FULL; *autoneg = TRUE; goto out; } /* * Determine link capabilities based on the stored value of AUTOC, * which represents EEPROM defaults. If AUTOC value has not * been stored, use the current register values. */ if (hw->mac.orig_link_settings_stored) autoc = hw->mac.orig_autoc; else autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); switch (autoc & IXGBE_AUTOC_LMS_MASK) { case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: *speed = IXGBE_LINK_SPEED_1GB_FULL; *autoneg = FALSE; break; case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: *speed = IXGBE_LINK_SPEED_10GB_FULL; *autoneg = FALSE; break; case IXGBE_AUTOC_LMS_1G_AN: *speed = IXGBE_LINK_SPEED_1GB_FULL; *autoneg = TRUE; break; case IXGBE_AUTOC_LMS_10G_SERIAL: *speed = IXGBE_LINK_SPEED_10GB_FULL; *autoneg = FALSE; break; case IXGBE_AUTOC_LMS_KX4_KX_KR: case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: *speed = IXGBE_LINK_SPEED_UNKNOWN; if (autoc & IXGBE_AUTOC_KR_SUPP) *speed |= IXGBE_LINK_SPEED_10GB_FULL; if (autoc & IXGBE_AUTOC_KX4_SUPP) *speed |= IXGBE_LINK_SPEED_10GB_FULL; if (autoc & IXGBE_AUTOC_KX_SUPP) *speed |= IXGBE_LINK_SPEED_1GB_FULL; *autoneg = TRUE; break; case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: *speed = IXGBE_LINK_SPEED_100_FULL; if (autoc & IXGBE_AUTOC_KR_SUPP) *speed |= IXGBE_LINK_SPEED_10GB_FULL; if (autoc & IXGBE_AUTOC_KX4_SUPP) *speed |= IXGBE_LINK_SPEED_10GB_FULL; if (autoc & IXGBE_AUTOC_KX_SUPP) *speed |= IXGBE_LINK_SPEED_1GB_FULL; *autoneg = TRUE; break; case IXGBE_AUTOC_LMS_SGMII_1G_100M: *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; *autoneg = FALSE; break; default: status = IXGBE_ERR_LINK_SETUP; goto out; break; } if (hw->phy.multispeed_fiber) { *speed |= IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL; /* QSFP must not enable full auto-negotiation * Limited autoneg is enabled at 1G */ if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) *autoneg = FALSE; else *autoneg = TRUE; } out: return status; } /** * ixgbe_get_media_type_82599 - Get media type * @hw: pointer to hardware structure * * Returns the media type (fiber, copper, backplane) **/ enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) { enum ixgbe_media_type media_type; DEBUGFUNC("ixgbe_get_media_type_82599"); /* Detect if there is a copper PHY attached. */ switch (hw->phy.type) { case ixgbe_phy_cu_unknown: case ixgbe_phy_tn: media_type = ixgbe_media_type_copper; goto out; default: break; } switch (hw->device_id) { case IXGBE_DEV_ID_82599_KX4: case IXGBE_DEV_ID_82599_KX4_MEZZ: case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: case IXGBE_DEV_ID_82599_KR: case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: case IXGBE_DEV_ID_82599_XAUI_LOM: /* Default device ID is mezzanine card KX/KX4 */ media_type = ixgbe_media_type_backplane; break; case IXGBE_DEV_ID_82599_SFP: case IXGBE_DEV_ID_82599_SFP_FCOE: case IXGBE_DEV_ID_82599_SFP_EM: case IXGBE_DEV_ID_82599_SFP_SF2: case IXGBE_DEV_ID_82599_SFP_SF_QP: case IXGBE_DEV_ID_82599EN_SFP: media_type = ixgbe_media_type_fiber; break; case IXGBE_DEV_ID_82599_CX4: media_type = ixgbe_media_type_cx4; break; case IXGBE_DEV_ID_82599_T3_LOM: media_type = ixgbe_media_type_copper; break; case IXGBE_DEV_ID_82599_QSFP_SF_QP: media_type = ixgbe_media_type_fiber_qsfp; break; case IXGBE_DEV_ID_82599_BYPASS: media_type = ixgbe_media_type_fiber_fixed; hw->phy.multispeed_fiber = TRUE; break; default: media_type = ixgbe_media_type_unknown; break; } out: return media_type; } /** * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 * @hw: pointer to hardware structure * * Disables link during D3 power down sequence. * **/ void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) { u32 autoc2_reg; u16 ee_ctrl_2 = 0; DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599"); ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); if (!ixgbe_mng_present(hw) && !hw->wol_enabled && ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); } } /** * ixgbe_start_mac_link_82599 - Setup MAC link settings * @hw: pointer to hardware structure * @autoneg_wait_to_complete: TRUE when waiting for completion is needed * * Configures link settings based on values in the ixgbe_hw struct. * Restarts the link. Performs autonegotiation if needed. **/ s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, bool autoneg_wait_to_complete) { u32 autoc_reg; u32 links_reg; u32 i; s32 status = IXGBE_SUCCESS; bool got_lock = FALSE; DEBUGFUNC("ixgbe_start_mac_link_82599"); /* reset_pipeline requires us to hold this lock as it writes to * AUTOC. */ if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); if (status != IXGBE_SUCCESS) goto out; got_lock = TRUE; } /* Restart link */ ixgbe_reset_pipeline_82599(hw); if (got_lock) hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); /* Only poll for autoneg to complete if specified to do so */ if (autoneg_wait_to_complete) { autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == IXGBE_AUTOC_LMS_KX4_KX_KR || (autoc_reg & IXGBE_AUTOC_LMS_MASK) == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || (autoc_reg & IXGBE_AUTOC_LMS_MASK) == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { links_reg = 0; /* Just in case Autoneg time = 0 */ for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); if (links_reg & IXGBE_LINKS_KX_AN_COMP) break; msec_delay(100); } if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; DEBUGOUT("Autoneg did not complete.\n"); } } } /* Add delay to filter out noises during initial link setup */ msec_delay(50); out: return status; } /** * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser * @hw: pointer to hardware structure * * The base drivers may require better control over SFP+ module * PHY states. This includes selectively shutting down the Tx * laser on the PHY, effectively halting physical link. **/ void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) { u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); /* Blocked by MNG FW so bail */ if (ixgbe_check_reset_blocked(hw)) return; /* Disable Tx laser; allow 100us to go dark per spec */ esdp_reg |= IXGBE_ESDP_SDP3; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); IXGBE_WRITE_FLUSH(hw); usec_delay(100); } /** * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser * @hw: pointer to hardware structure * * The base drivers may require better control over SFP+ module * PHY states. This includes selectively turning on the Tx * laser on the PHY, effectively starting physical link. **/ void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) { u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); /* Enable Tx laser; allow 100ms to light up */ esdp_reg &= ~IXGBE_ESDP_SDP3; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); IXGBE_WRITE_FLUSH(hw); msec_delay(100); } /** * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser * @hw: pointer to hardware structure * * When the driver changes the link speeds that it can support, * it sets autotry_restart to TRUE to indicate that we need to * initiate a new autotry session with the link partner. To do * so, we set the speed then disable and re-enable the Tx laser, to * alert the link partner that it also needs to restart autotry on its * end. This is consistent with TRUE clause 37 autoneg, which also * involves a loss of signal. **/ void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) { DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); /* Blocked by MNG FW so bail */ if (ixgbe_check_reset_blocked(hw)) return; if (hw->mac.autotry_restart) { ixgbe_disable_tx_laser_multispeed_fiber(hw); ixgbe_enable_tx_laser_multispeed_fiber(hw); hw->mac.autotry_restart = FALSE; } } /** * ixgbe_set_hard_rate_select_speed - Set module link speed * @hw: pointer to hardware structure * @speed: link speed to set * * Set module link speed via RS0/RS1 rate select pins. */ void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) { u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); switch (speed) { case IXGBE_LINK_SPEED_10GB_FULL: esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); break; case IXGBE_LINK_SPEED_1GB_FULL: esdp_reg &= ~IXGBE_ESDP_SDP5; esdp_reg |= IXGBE_ESDP_SDP5_DIR; break; default: DEBUGOUT("Invalid fixed module speed\n"); return; } IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); IXGBE_WRITE_FLUSH(hw); } /** * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed * @hw: pointer to hardware structure * @speed: new link speed * @autoneg_wait_to_complete: TRUE when waiting for completion is needed * * Implements the Intel SmartSpeed algorithm. **/ s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete) { s32 status = IXGBE_SUCCESS; ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; s32 i, j; bool link_up = FALSE; u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); /* Set autoneg_advertised value based on input link speed */ hw->phy.autoneg_advertised = 0; if (speed & IXGBE_LINK_SPEED_10GB_FULL) hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; if (speed & IXGBE_LINK_SPEED_1GB_FULL) hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; if (speed & IXGBE_LINK_SPEED_100_FULL) hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; /* * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the * autoneg advertisement if link is unable to be established at the * highest negotiated rate. This can sometimes happen due to integrity * issues with the physical media connection. */ /* First, try to get link with full advertisement */ hw->phy.smart_speed_active = FALSE; for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { status = ixgbe_setup_mac_link_82599(hw, speed, autoneg_wait_to_complete); if (status != IXGBE_SUCCESS) goto out; /* * Wait for the controller to acquire link. Per IEEE 802.3ap, * Section 73.10.2, we may have to wait up to 500ms if KR is * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per * Table 9 in the AN MAS. */ for (i = 0; i < 5; i++) { msec_delay(100); /* If we have link, just jump out */ status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); if (status != IXGBE_SUCCESS) goto out; if (link_up) goto out; } } /* * We didn't get link. If we advertised KR plus one of KX4/KX * (or BX4/BX), then disable KR and try again. */ if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) goto out; /* Turn SmartSpeed on to disable KR support */ hw->phy.smart_speed_active = TRUE; status = ixgbe_setup_mac_link_82599(hw, speed, autoneg_wait_to_complete); if (status != IXGBE_SUCCESS) goto out; /* * Wait for the controller to acquire link. 600ms will allow for * the AN link_fail_inhibit_timer as well for multiple cycles of * parallel detect, both 10g and 1g. This allows for the maximum * connect attempts as defined in the AN MAS table 73-7. */ for (i = 0; i < 6; i++) { msec_delay(100); /* If we have link, just jump out */ status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); if (status != IXGBE_SUCCESS) goto out; if (link_up) goto out; } /* We didn't get link. Turn SmartSpeed back off. */ hw->phy.smart_speed_active = FALSE; status = ixgbe_setup_mac_link_82599(hw, speed, autoneg_wait_to_complete); out: if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) DEBUGOUT("Smartspeed has downgraded the link speed " "from the maximum advertised\n"); return status; } /** * ixgbe_setup_mac_link_82599 - Set MAC link speed * @hw: pointer to hardware structure * @speed: new link speed * @autoneg_wait_to_complete: TRUE when waiting for completion is needed * * Set the link speed in the AUTOC register and restarts link. **/ s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete) { bool autoneg = FALSE; s32 status = IXGBE_SUCCESS; u32 pma_pmd_1g, link_mode; u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */ u32 orig_autoc = 0; /* holds the cached value of AUTOC register */ u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */ u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; u32 links_reg; u32 i; ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; DEBUGFUNC("ixgbe_setup_mac_link_82599"); /* Check to see if speed passed in is supported. */ status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); if (status) goto out; speed &= link_capabilities; if (speed == IXGBE_LINK_SPEED_UNKNOWN) { status = IXGBE_ERR_LINK_SETUP; goto out; } /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ if (hw->mac.orig_link_settings_stored) orig_autoc = hw->mac.orig_autoc; else orig_autoc = autoc; link_mode = autoc & IXGBE_AUTOC_LMS_MASK; pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { /* Set KX4/KX/KR support according to speed requested */ autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); if (speed & IXGBE_LINK_SPEED_10GB_FULL) { if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) autoc |= IXGBE_AUTOC_KX4_SUPP; if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && (hw->phy.smart_speed_active == FALSE)) autoc |= IXGBE_AUTOC_KR_SUPP; } if (speed & IXGBE_LINK_SPEED_1GB_FULL) autoc |= IXGBE_AUTOC_KX_SUPP; } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || link_mode == IXGBE_AUTOC_LMS_1G_AN)) { /* Switch from 1G SFI to 10G SFI if requested */ if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { autoc &= ~IXGBE_AUTOC_LMS_MASK; autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; } } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { /* Switch from 10G SFI to 1G SFI if requested */ if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { autoc &= ~IXGBE_AUTOC_LMS_MASK; if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel) autoc |= IXGBE_AUTOC_LMS_1G_AN; else autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; } } if (autoc != current_autoc) { /* Restart link */ status = hw->mac.ops.prot_autoc_write(hw, autoc, FALSE); if (status != IXGBE_SUCCESS) goto out; /* Only poll for autoneg to complete if specified to do so */ if (autoneg_wait_to_complete) { if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { links_reg = 0; /*Just in case Autoneg time=0*/ for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); if (links_reg & IXGBE_LINKS_KX_AN_COMP) break; msec_delay(100); } if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; DEBUGOUT("Autoneg did not complete.\n"); } } } /* Add delay to filter out noises during initial link setup */ msec_delay(50); } out: return status; } /** * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field * @hw: pointer to hardware structure * @speed: new link speed * @autoneg_wait_to_complete: TRUE if waiting is needed to complete * * Restarts link on PHY and MAC based on settings passed in. **/ static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete) { s32 status; DEBUGFUNC("ixgbe_setup_copper_link_82599"); /* Setup the PHY according to input speed */ status = hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); /* Set up MAC */ ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); return status; } /** * ixgbe_reset_hw_82599 - Perform hardware reset * @hw: pointer to hardware structure * * Resets the hardware by resetting the transmit and receive units, masks * and clears all interrupts, perform a PHY reset, and perform a link (MAC) * reset. **/ s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) { ixgbe_link_speed link_speed; s32 status; u32 ctrl = 0; u32 i, autoc, autoc2; u32 curr_lms; bool link_up = FALSE; DEBUGFUNC("ixgbe_reset_hw_82599"); /* Call adapter stop to disable tx/rx and clear interrupts */ status = hw->mac.ops.stop_adapter(hw); if (status != IXGBE_SUCCESS) goto reset_hw_out; /* flush pending Tx transactions */ ixgbe_clear_tx_pending(hw); /* PHY ops must be identified and initialized prior to reset */ /* Identify PHY and related function pointers */ status = hw->phy.ops.init(hw); if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) goto reset_hw_out; /* Setup SFP module if there is one present. */ if (hw->phy.sfp_setup_needed) { status = hw->mac.ops.setup_sfp(hw); hw->phy.sfp_setup_needed = FALSE; } if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) goto reset_hw_out; /* Reset PHY */ if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) hw->phy.ops.reset(hw); /* remember AUTOC from before we reset */ curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; mac_reset_top: /* * Issue global reset to the MAC. Needs to be SW reset if link is up. * If link reset is used when link is up, it might reset the PHY when * mng is using it. If link is down or the flag to force full link * reset is set, then perform link reset. */ ctrl = IXGBE_CTRL_LNK_RST; if (!hw->force_full_reset) { hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); if (link_up) ctrl = IXGBE_CTRL_RST; } ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); IXGBE_WRITE_FLUSH(hw); /* Poll for reset bit to self-clear meaning reset is complete */ for (i = 0; i < 10; i++) { usec_delay(1); ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); if (!(ctrl & IXGBE_CTRL_RST_MASK)) break; } if (ctrl & IXGBE_CTRL_RST_MASK) { status = IXGBE_ERR_RESET_FAILED; DEBUGOUT("Reset polling failed to complete.\n"); } msec_delay(50); /* * Double resets are required for recovery from certain error * conditions. Between resets, it is necessary to stall to * allow time for any pending HW events to complete. */ if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; goto mac_reset_top; } /* * Store the original AUTOC/AUTOC2 values if they have not been * stored off yet. Otherwise restore the stored original * values since the reset operation sets back to defaults. */ autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); /* Enable link if disabled in NVM */ if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); IXGBE_WRITE_FLUSH(hw); } if (hw->mac.orig_link_settings_stored == FALSE) { hw->mac.orig_autoc = autoc; hw->mac.orig_autoc2 = autoc2; hw->mac.orig_link_settings_stored = TRUE; } else { /* If MNG FW is running on a multi-speed device that * doesn't autoneg with out driver support we need to * leave LMS in the state it was before we MAC reset. * Likewise if we support WoL we don't want change the * LMS state. */ if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || hw->wol_enabled) hw->mac.orig_autoc = (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | curr_lms; if (autoc != hw->mac.orig_autoc) { status = hw->mac.ops.prot_autoc_write(hw, hw->mac.orig_autoc, FALSE); if (status != IXGBE_SUCCESS) goto reset_hw_out; } if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; autoc2 |= (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK); IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); } } /* Store the permanent mac address */ hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); /* * Store MAC address from RAR0, clear receive address registers, and * clear the multicast table. Also reset num_rar_entries to 128, * since we modify this value when programming the SAN MAC address. */ hw->mac.num_rar_entries = 128; hw->mac.ops.init_rx_addrs(hw); /* Store the permanent SAN mac address */ hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); /* Add the SAN MAC address to the RAR only if it's a valid address */ if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { /* Save the SAN MAC RAR index */ hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, hw->mac.san_addr, 0, IXGBE_RAH_AV); /* clear VMDq pool/queue selection for this RAR */ hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, IXGBE_CLEAR_VMDQ_ALL); /* Reserve the last RAR for the SAN MAC address */ hw->mac.num_rar_entries--; } /* Store the alternative WWNN/WWPN prefix */ hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, &hw->mac.wwpn_prefix); reset_hw_out: return status; } /** * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete * @hw: pointer to hardware structure * @fdircmd: current value of FDIRCMD register */ static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) { int i; for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) return IXGBE_SUCCESS; usec_delay(10); } return IXGBE_ERR_FDIR_CMD_INCOMPLETE; } /** * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. * @hw: pointer to hardware structure **/ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) { s32 err; int i; u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); u32 fdircmd; fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); /* * Before starting reinitialization process, * FDIRCMD.CMD must be zero. */ err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); if (err) { DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n"); return err; } IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); IXGBE_WRITE_FLUSH(hw); /* * 82599 adapters flow director init flow cannot be restarted, * Workaround 82599 silicon errata by performing the following steps * before re-writing the FDIRCTRL control register with the same value. * - write 1 to bit 8 of FDIRCMD register & * - write 0 to bit 8 of FDIRCMD register */ IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | IXGBE_FDIRCMD_CLEARHT)); IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & ~IXGBE_FDIRCMD_CLEARHT)); IXGBE_WRITE_FLUSH(hw); /* * Clear FDIR Hash register to clear any leftover hashes * waiting to be programmed. */ IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); IXGBE_WRITE_FLUSH(hw); /* Poll init-done after we write FDIRCTRL register */ for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & IXGBE_FDIRCTRL_INIT_DONE) break; msec_delay(1); } if (i >= IXGBE_FDIR_INIT_DONE_POLL) { DEBUGOUT("Flow Director Signature poll time exceeded!\n"); return IXGBE_ERR_FDIR_REINIT_FAILED; } /* Clear FDIR statistics registers (read to clear) */ IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); IXGBE_READ_REG(hw, IXGBE_FDIRMISS); IXGBE_READ_REG(hw, IXGBE_FDIRLEN); return IXGBE_SUCCESS; } /** * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers * @hw: pointer to hardware structure * @fdirctrl: value to write to flow director control register **/ static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) { int i; DEBUGFUNC("ixgbe_fdir_enable_82599"); /* Prime the keys for hashing */ IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); /* * Poll init-done after we write the register. Estimated times: * 10G: PBALLOC = 11b, timing is 60us * 1G: PBALLOC = 11b, timing is 600us * 100M: PBALLOC = 11b, timing is 6ms * * Multiple these timings by 4 if under full Rx load * * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for * 1 msec per poll time. If we're at line rate and drop to 100M, then * this might not finish in our poll time, but we can live with that * for now. */ IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); IXGBE_WRITE_FLUSH(hw); for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & IXGBE_FDIRCTRL_INIT_DONE) break; msec_delay(1); } if (i >= IXGBE_FDIR_INIT_DONE_POLL) DEBUGOUT("Flow Director poll time exceeded!\n"); } /** * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters * @hw: pointer to hardware structure * @fdirctrl: value to write to flow director control register, initially * contains just the value of the Rx packet buffer allocation **/ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) { DEBUGFUNC("ixgbe_init_fdir_signature_82599"); /* * Continue setup of fdirctrl register bits: * Move the flexible bytes to use the ethertype - shift 6 words * Set the maximum length per hash bucket to 0xA filters * Send interrupt when 64 filters are left */ fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); /* write hashes and fdirctrl register, poll for completion */ ixgbe_fdir_enable_82599(hw, fdirctrl); return IXGBE_SUCCESS; } /** * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters * @hw: pointer to hardware structure * @fdirctrl: value to write to flow director control register, initially * contains just the value of the Rx packet buffer allocation * @cloud_mode: TRUE - cloud mode, FALSE - other mode **/ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl, bool cloud_mode) { UNREFERENCED_1PARAMETER(cloud_mode); DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); /* * Continue setup of fdirctrl register bits: * Turn perfect match filtering on * Report hash in RSS field of Rx wb descriptor * Initialize the drop queue to queue 127 * Move the flexible bytes to use the ethertype - shift 6 words * Set the maximum length per hash bucket to 0xA filters * Send interrupt when 64 (0x4 * 16) filters are left */ fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | IXGBE_FDIRCTRL_REPORT_STATUS | (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); if (cloud_mode) fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD << IXGBE_FDIRCTRL_FILTERMODE_SHIFT); /* write hashes and fdirctrl register, poll for completion */ ixgbe_fdir_enable_82599(hw, fdirctrl); return IXGBE_SUCCESS; } /** * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue * @hw: pointer to hardware structure * @dropqueue: Rx queue index used for the dropped packets **/ void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue) { u32 fdirctrl; DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599"); /* Clear init done bit and drop queue field */ fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE); /* Set drop queue */ fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT); if ((hw->mac.type == ixgbe_mac_X550) || (hw->mac.type == ixgbe_mac_X550EM_x) || (hw->mac.type == ixgbe_mac_X550EM_a)) fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH; IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | IXGBE_FDIRCMD_CLEARHT)); IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & ~IXGBE_FDIRCMD_CLEARHT)); IXGBE_WRITE_FLUSH(hw); /* write hashes and fdirctrl register, poll for completion */ ixgbe_fdir_enable_82599(hw, fdirctrl); } /* * These defines allow us to quickly generate all of the necessary instructions * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION * for values 0 through 15 */ #define IXGBE_ATR_COMMON_HASH_KEY \ (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ do { \ u32 n = (_n); \ if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ common_hash ^= lo_hash_dword >> n; \ else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ bucket_hash ^= lo_hash_dword >> n; \ else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ sig_hash ^= lo_hash_dword << (16 - n); \ if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ common_hash ^= hi_hash_dword >> n; \ else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ bucket_hash ^= hi_hash_dword >> n; \ else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ sig_hash ^= hi_hash_dword << (16 - n); \ } while (0) /** * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash * @input: input bitstream to compute the hash on * @common: compressed common input dword * * This function is almost identical to the function above but contains * several optimizations such as unwinding all of the loops, letting the * compiler work out all of the conditional ifs since the keys are static * defines, and computing two keys at once since the hashed dword stream * will be the same for both keys. **/ u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, union ixgbe_atr_hash_dword common) { u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; /* record the flow_vm_vlan bits as they are a key part to the hash */ flow_vm_vlan = IXGBE_NTOHL(input.dword); /* generate common hash dword */ hi_hash_dword = IXGBE_NTOHL(common.dword); /* low dword is word swapped version of common */ lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); /* apply flow ID/VM pool/VLAN ID bits to hash words */ hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); /* Process bits 0 and 16 */ IXGBE_COMPUTE_SIG_HASH_ITERATION(0); /* * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to * delay this because bit 0 of the stream should not be processed * so we do not add the VLAN until after bit 0 was processed */ lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); /* Process remaining 30 bit of the key */ IXGBE_COMPUTE_SIG_HASH_ITERATION(1); IXGBE_COMPUTE_SIG_HASH_ITERATION(2); IXGBE_COMPUTE_SIG_HASH_ITERATION(3); IXGBE_COMPUTE_SIG_HASH_ITERATION(4); IXGBE_COMPUTE_SIG_HASH_ITERATION(5); IXGBE_COMPUTE_SIG_HASH_ITERATION(6); IXGBE_COMPUTE_SIG_HASH_ITERATION(7); IXGBE_COMPUTE_SIG_HASH_ITERATION(8); IXGBE_COMPUTE_SIG_HASH_ITERATION(9); IXGBE_COMPUTE_SIG_HASH_ITERATION(10); IXGBE_COMPUTE_SIG_HASH_ITERATION(11); IXGBE_COMPUTE_SIG_HASH_ITERATION(12); IXGBE_COMPUTE_SIG_HASH_ITERATION(13); IXGBE_COMPUTE_SIG_HASH_ITERATION(14); IXGBE_COMPUTE_SIG_HASH_ITERATION(15); /* combine common_hash result with signature and bucket hashes */ bucket_hash ^= common_hash; bucket_hash &= IXGBE_ATR_HASH_MASK; sig_hash ^= common_hash << 16; sig_hash &= IXGBE_ATR_HASH_MASK << 16; /* return completed signature hash */ return sig_hash ^ bucket_hash; } /** * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter * @hw: pointer to hardware structure * @input: unique input dword * @common: compressed common input dword * @queue: queue index to direct traffic to * * Note that the tunnel bit in input must not be set when the hardware * tunneling support does not exist. **/ void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, union ixgbe_atr_hash_dword input, union ixgbe_atr_hash_dword common, u8 queue) { u64 fdirhashcmd; u8 flow_type; bool tunnel; u32 fdircmd; DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); /* * Get the flow_type in order to program FDIRCMD properly * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 * fifth is FDIRCMD.TUNNEL_FILTER */ tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); flow_type = input.formatted.flow_type & (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); switch (flow_type) { case IXGBE_ATR_FLOW_TYPE_TCPV4: case IXGBE_ATR_FLOW_TYPE_UDPV4: case IXGBE_ATR_FLOW_TYPE_SCTPV4: case IXGBE_ATR_FLOW_TYPE_TCPV6: case IXGBE_ATR_FLOW_TYPE_UDPV6: case IXGBE_ATR_FLOW_TYPE_SCTPV6: break; default: DEBUGOUT(" Error on flow type input\n"); return; } /* configure FDIRCMD register */ fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; if (tunnel) fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; /* * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. */ fdirhashcmd = (u64)fdircmd << 32; - fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); + fdirhashcmd |= (u64)ixgbe_atr_compute_sig_hash_82599(input, common); IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); return; } #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ do { \ u32 n = (_n); \ if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ bucket_hash ^= lo_hash_dword >> n; \ if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ bucket_hash ^= hi_hash_dword >> n; \ } while (0) /** * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash * @input: input bitstream to compute the hash on * @input_mask: mask for the input bitstream * * This function serves two main purposes. First it applies the input_mask * to the atr_input resulting in a cleaned up atr_input data stream. * Secondly it computes the hash and stores it in the bkt_hash field at * the end of the input byte stream. This way it will be available for * future use without needing to recompute the hash. **/ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, union ixgbe_atr_input *input_mask) { u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; u32 bucket_hash = 0; u32 hi_dword = 0; u32 i = 0; /* Apply masks to input data */ for (i = 0; i < 14; i++) input->dword_stream[i] &= input_mask->dword_stream[i]; /* record the flow_vm_vlan bits as they are a key part to the hash */ flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]); /* generate common hash dword */ for (i = 1; i <= 13; i++) hi_dword ^= input->dword_stream[i]; hi_hash_dword = IXGBE_NTOHL(hi_dword); /* low dword is word swapped version of common */ lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); /* apply flow ID/VM pool/VLAN ID bits to hash words */ hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); /* Process bits 0 and 16 */ IXGBE_COMPUTE_BKT_HASH_ITERATION(0); /* * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to * delay this because bit 0 of the stream should not be processed * so we do not add the VLAN until after bit 0 was processed */ lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); /* Process remaining 30 bit of the key */ for (i = 1; i <= 15; i++) IXGBE_COMPUTE_BKT_HASH_ITERATION(i); /* * Limit hash to 13 bits since max bucket count is 8K. * Store result at the end of the input stream. */ input->formatted.bkt_hash = bucket_hash & 0x1FFF; } /** * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks * @input_mask: mask to be bit swapped * * The source and destination port masks for flow director are bit swapped * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to * generate a correctly swapped value we need to bit swap the mask and that * is what is accomplished by this function. **/ static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) { u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port); mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; - mask |= IXGBE_NTOHS(input_mask->formatted.src_port); + mask |= (u32)IXGBE_NTOHS(input_mask->formatted.src_port); mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); } /* * These two macros are meant to address the fact that we have registers * that are either all or in part big-endian. As a result on big-endian * systems we will end up byte swapping the value to little-endian before * it is byte swapped again and written to the hardware in the original * big-endian format. */ #define IXGBE_STORE_AS_BE32(_value) \ (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) #define IXGBE_WRITE_REG_BE32(a, reg, value) \ IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value))) #define IXGBE_STORE_AS_BE16(_value) \ IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8)) s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, union ixgbe_atr_input *input_mask, bool cloud_mode) { /* mask IPv6 since it is currently not supported */ u32 fdirm = IXGBE_FDIRM_DIPv6; u32 fdirtcpm; u32 fdirip6m; UNREFERENCED_1PARAMETER(cloud_mode); DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599"); /* * Program the relevant mask registers. If src/dst_port or src/dst_addr * are zero, then assume a full mask for that field. Also assume that * a VLAN of 0 is unspecified, so mask that out as well. L4type * cannot be masked out in this implementation. * * This also assumes IPv4 only. IPv6 masking isn't supported at this * point in time. */ /* verify bucket hash is cleared on hash generation */ if (input_mask->formatted.bkt_hash) DEBUGOUT(" bucket hash should always be 0 in mask\n"); /* Program FDIRM and verify partial masks */ switch (input_mask->formatted.vm_pool & 0x7F) { case 0x0: fdirm |= IXGBE_FDIRM_POOL; case 0x7F: break; default: DEBUGOUT(" Error on vm pool mask\n"); return IXGBE_ERR_CONFIG; } switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { case 0x0: fdirm |= IXGBE_FDIRM_L4P; if (input_mask->formatted.dst_port || input_mask->formatted.src_port) { DEBUGOUT(" Error on src/dst port mask\n"); return IXGBE_ERR_CONFIG; } case IXGBE_ATR_L4TYPE_MASK: break; default: DEBUGOUT(" Error on flow type mask\n"); return IXGBE_ERR_CONFIG; } switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) { case 0x0000: /* mask VLAN ID */ fdirm |= IXGBE_FDIRM_VLANID; /* FALLTHROUGH */ case 0x0FFF: /* mask VLAN priority */ fdirm |= IXGBE_FDIRM_VLANP; break; case 0xE000: /* mask VLAN ID only */ fdirm |= IXGBE_FDIRM_VLANID; /* fall through */ case 0xEFFF: /* no VLAN fields masked */ break; default: DEBUGOUT(" Error on VLAN mask\n"); return IXGBE_ERR_CONFIG; } switch (input_mask->formatted.flex_bytes & 0xFFFF) { case 0x0000: /* Mask Flex Bytes */ fdirm |= IXGBE_FDIRM_FLEX; /* fall through */ case 0xFFFF: break; default: DEBUGOUT(" Error on flexible byte mask\n"); return IXGBE_ERR_CONFIG; } if (cloud_mode) { fdirm |= IXGBE_FDIRM_L3P; fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT); fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK; switch (input_mask->formatted.inner_mac[0] & 0xFF) { case 0x00: /* Mask inner MAC, fall through */ fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC; case 0xFF: break; default: DEBUGOUT(" Error on inner_mac byte mask\n"); return IXGBE_ERR_CONFIG; } switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) { case 0x0: /* Mask vxlan id */ fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI; break; case 0x00FFFFFF: fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24; break; case 0xFFFFFFFF: break; default: DEBUGOUT(" Error on TNI/VNI byte mask\n"); return IXGBE_ERR_CONFIG; } switch (input_mask->formatted.tunnel_type & 0xFFFF) { case 0x0: /* Mask turnnel type, fall through */ fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE; case 0xFFFF: break; default: DEBUGOUT(" Error on tunnel type byte mask\n"); return IXGBE_ERR_CONFIG; } IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m); /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM, * FDIRSIP4M and FDIRDIP4M in cloud mode to allow * L3/L3 packets to tunnel. */ IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); switch (hw->mac.type) { case ixgbe_mac_X550: case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_a: IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF); break; default: break; } } /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); if (!cloud_mode) { /* store the TCP/UDP port masks, bit reversed from port * layout */ fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); /* write both the same so that UDP and TCP use the same mask */ IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); /* also use it for SCTP */ switch (hw->mac.type) { case ixgbe_mac_X550: case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_a: IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); break; default: break; } /* store source and destination IP masks (big-enian) */ IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, ~input_mask->formatted.src_ip[0]); IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, ~input_mask->formatted.dst_ip[0]); IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, 0xFFFFFFFF); } return IXGBE_SUCCESS; } s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, union ixgbe_atr_input *input, u16 soft_id, u8 queue, bool cloud_mode) { u32 fdirport, fdirvlan, fdirhash, fdircmd; u32 addr_low, addr_high; u32 cloud_type = 0; s32 err; UNREFERENCED_1PARAMETER(cloud_mode); DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599"); if (!cloud_mode) { /* currently IPv6 is not supported, must be programmed with 0 */ IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), input->formatted.src_ip[0]); IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), input->formatted.src_ip[1]); IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.src_ip[2]); /* record the source address (big-endian) */ IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); /* record the first 32 bits of the destination address * (big-endian) */ IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); /* record source and destination port (little-endian)*/ fdirport = IXGBE_NTOHS(input->formatted.dst_port); fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; - fdirport |= IXGBE_NTOHS(input->formatted.src_port); + fdirport |= (u32)IXGBE_NTOHS(input->formatted.src_port); IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); } /* record VLAN (little-endian) and flex_bytes(big-endian) */ fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; - fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); + fdirvlan |= (u32)IXGBE_NTOHS(input->formatted.vlan_id); IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); if (cloud_mode) { if (input->formatted.tunnel_type != 0) cloud_type = 0x80000000; addr_low = ((u32)input->formatted.inner_mac[0] | ((u32)input->formatted.inner_mac[1] << 8) | ((u32)input->formatted.inner_mac[2] << 16) | ((u32)input->formatted.inner_mac[3] << 24)); addr_high = ((u32)input->formatted.inner_mac[4] | ((u32)input->formatted.inner_mac[5] << 8)); cloud_type |= addr_high; IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low); IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type); IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni); } /* configure FDIRHASH register */ fdirhash = input->formatted.bkt_hash; fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); /* * flush all previous writes to make certain registers are * programmed prior to issuing the command */ IXGBE_WRITE_FLUSH(hw); /* configure FDIRCMD register */ fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; if (queue == IXGBE_FDIR_DROP_QUEUE) fdircmd |= IXGBE_FDIRCMD_DROP; if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK) fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); if (err) { DEBUGOUT("Flow Director command did not complete!\n"); return err; } return IXGBE_SUCCESS; } s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, union ixgbe_atr_input *input, u16 soft_id) { u32 fdirhash; u32 fdircmd; s32 err; /* configure FDIRHASH register */ fdirhash = input->formatted.bkt_hash; fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); /* flush hash to HW */ IXGBE_WRITE_FLUSH(hw); /* Query if filter is present */ IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); if (err) { DEBUGOUT("Flow Director command did not complete!\n"); return err; } /* if filter exists in hardware then remove it */ if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_REMOVE_FLOW); } return IXGBE_SUCCESS; } /** * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter * @hw: pointer to hardware structure * @input: input bitstream * @input_mask: mask for the input bitstream * @soft_id: software index for the filters * @queue: queue index to direct traffic to * @cloud_mode: unused * * Note that the caller to this function must lock before calling, since the * hardware writes must be protected from one another. **/ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, union ixgbe_atr_input *input, union ixgbe_atr_input *input_mask, u16 soft_id, u8 queue, bool cloud_mode) { s32 err = IXGBE_ERR_CONFIG; UNREFERENCED_1PARAMETER(cloud_mode); DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); /* * Check flow_type formatting, and bail out before we touch the hardware * if there's a configuration issue */ switch (input->formatted.flow_type) { case IXGBE_ATR_FLOW_TYPE_IPV4: case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4: input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK; if (input->formatted.dst_port || input->formatted.src_port) { DEBUGOUT(" Error on src/dst port\n"); return IXGBE_ERR_CONFIG; } break; case IXGBE_ATR_FLOW_TYPE_SCTPV4: case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4: if (input->formatted.dst_port || input->formatted.src_port) { DEBUGOUT(" Error on src/dst port\n"); return IXGBE_ERR_CONFIG; } /* FALLTHROUGH */ case IXGBE_ATR_FLOW_TYPE_TCPV4: case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4: case IXGBE_ATR_FLOW_TYPE_UDPV4: case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4: input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | IXGBE_ATR_L4TYPE_MASK; break; default: DEBUGOUT(" Error on flow type input\n"); return err; } /* program input mask into the HW */ err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode); if (err) return err; /* apply mask and compute/store hash */ ixgbe_atr_compute_perfect_hash_82599(input, input_mask); /* program filters to filter memory */ return ixgbe_fdir_write_perfect_filter_82599(hw, input, soft_id, queue, cloud_mode); } /** * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register * @hw: pointer to hardware structure * @reg: analog register to read * @val: read value * * Performs read operation to Omer analog register specified. **/ s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) { u32 core_ctl; DEBUGFUNC("ixgbe_read_analog_reg8_82599"); IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | (reg << 8)); IXGBE_WRITE_FLUSH(hw); usec_delay(10); core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); *val = (u8)core_ctl; return IXGBE_SUCCESS; } /** * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register * @hw: pointer to hardware structure * @reg: atlas register to write * @val: value to write * * Performs write operation to Omer analog register specified. **/ s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) { u32 core_ctl; DEBUGFUNC("ixgbe_write_analog_reg8_82599"); core_ctl = (reg << 8) | val; IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); IXGBE_WRITE_FLUSH(hw); usec_delay(10); return IXGBE_SUCCESS; } /** * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx * @hw: pointer to hardware structure * * Starts the hardware using the generic start_hw function * and the generation start_hw function. * Then performs revision-specific operations, if any. **/ s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) { s32 ret_val = IXGBE_SUCCESS; DEBUGFUNC("ixgbe_start_hw_82599"); ret_val = ixgbe_start_hw_generic(hw); if (ret_val != IXGBE_SUCCESS) goto out; ret_val = ixgbe_start_hw_gen2(hw); if (ret_val != IXGBE_SUCCESS) goto out; /* We need to run link autotry after the driver loads */ hw->mac.autotry_restart = TRUE; if (ret_val == IXGBE_SUCCESS) ret_val = ixgbe_verify_fw_version_82599(hw); out: return ret_val; } /** * ixgbe_identify_phy_82599 - Get physical layer module * @hw: pointer to hardware structure * * Determines the physical layer module found on the current adapter. * If PHY already detected, maintains current PHY type in hw struct, * otherwise executes the PHY detection routine. **/ s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) { s32 status; DEBUGFUNC("ixgbe_identify_phy_82599"); /* Detect PHY if not unknown - returns success if already detected. */ status = ixgbe_identify_phy_generic(hw); if (status != IXGBE_SUCCESS) { /* 82599 10GBASE-T requires an external PHY */ if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) return status; else status = ixgbe_identify_module_generic(hw); } /* Set PHY type none if no PHY detected */ if (hw->phy.type == ixgbe_phy_unknown) { hw->phy.type = ixgbe_phy_none; return IXGBE_SUCCESS; } /* Return error if SFP module has been detected but is not supported */ if (hw->phy.type == ixgbe_phy_sfp_unsupported) return IXGBE_ERR_SFP_NOT_SUPPORTED; return status; } /** * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type * @hw: pointer to hardware structure * * Determines physical layer capabilities of the current configuration. **/ u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) { u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; u16 ext_ability = 0; DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); hw->phy.ops.identify(hw); switch (hw->phy.type) { case ixgbe_phy_tn: case ixgbe_phy_cu_unknown: hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; goto out; default: break; } switch (autoc & IXGBE_AUTOC_LMS_MASK) { case IXGBE_AUTOC_LMS_1G_AN: case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | IXGBE_PHYSICAL_LAYER_1000BASE_BX; goto out; } else /* SFI mode so read SFP module */ goto sfp_check; break; case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; goto out; break; case IXGBE_AUTOC_LMS_10G_SERIAL: if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; goto out; } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) goto sfp_check; break; case IXGBE_AUTOC_LMS_KX4_KX_KR: case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: if (autoc & IXGBE_AUTOC_KX_SUPP) physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; if (autoc & IXGBE_AUTOC_KX4_SUPP) physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; if (autoc & IXGBE_AUTOC_KR_SUPP) physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; goto out; break; default: goto out; break; } sfp_check: /* SFP check must be done last since DA modules are sometimes used to * test KR mode - we need to id KR mode correctly before SFP module. * Call identify_sfp because the pluggable module may have changed */ physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); out: return physical_layer; } /** * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 * @hw: pointer to hardware structure * @regval: register value to write to RXCTRL * * Enables the Rx DMA unit for 82599 **/ s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) { DEBUGFUNC("ixgbe_enable_rx_dma_82599"); /* * Workaround for 82599 silicon errata when enabling the Rx datapath. * If traffic is incoming before we enable the Rx unit, it could hang * the Rx DMA unit. Therefore, make sure the security engine is * completely disabled prior to enabling the Rx unit. */ hw->mac.ops.disable_sec_rx_path(hw); if (regval & IXGBE_RXCTRL_RXEN) ixgbe_enable_rx(hw); else ixgbe_disable_rx(hw); hw->mac.ops.enable_sec_rx_path(hw); return IXGBE_SUCCESS; } /** * ixgbe_verify_fw_version_82599 - verify FW version for 82599 * @hw: pointer to hardware structure * * Verifies that installed the firmware version is 0.6 or higher * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. * * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or * if the FW version is not supported. **/ static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) { s32 status = IXGBE_ERR_EEPROM_VERSION; u16 fw_offset, fw_ptp_cfg_offset; u16 fw_version; DEBUGFUNC("ixgbe_verify_fw_version_82599"); /* firmware check is only necessary for SFI devices */ if (hw->phy.media_type != ixgbe_media_type_fiber) { status = IXGBE_SUCCESS; goto fw_version_out; } /* get the offset to the Firmware Module block */ if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) { ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, "eeprom read at offset %d failed", IXGBE_FW_PTR); return IXGBE_ERR_EEPROM_VERSION; } if ((fw_offset == 0) || (fw_offset == 0xFFFF)) goto fw_version_out; /* get the offset to the Pass Through Patch Configuration block */ if (hw->eeprom.ops.read(hw, (fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), &fw_ptp_cfg_offset)) { ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, "eeprom read at offset %d failed", fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR); return IXGBE_ERR_EEPROM_VERSION; } if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) goto fw_version_out; /* get the firmware version */ if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4), &fw_version)) { ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, "eeprom read at offset %d failed", fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4); return IXGBE_ERR_EEPROM_VERSION; } if (fw_version > 0x5) status = IXGBE_SUCCESS; fw_version_out: return status; } /** * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. * @hw: pointer to hardware structure * * Returns TRUE if the LESM FW module is present and enabled. Otherwise * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. **/ bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) { bool lesm_enabled = FALSE; u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; s32 status; DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); /* get the offset to the Firmware Module block */ status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); if ((status != IXGBE_SUCCESS) || (fw_offset == 0) || (fw_offset == 0xFFFF)) goto out; /* get the offset to the LESM Parameters block */ status = hw->eeprom.ops.read(hw, (fw_offset + IXGBE_FW_LESM_PARAMETERS_PTR), &fw_lesm_param_offset); if ((status != IXGBE_SUCCESS) || (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) goto out; /* get the LESM state word */ status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + IXGBE_FW_LESM_STATE_1), &fw_lesm_state); if ((status == IXGBE_SUCCESS) && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) lesm_enabled = TRUE; out: return lesm_enabled; } /** * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using * fastest available method * * @hw: pointer to hardware structure * @offset: offset of word in EEPROM to read * @words: number of words * @data: word(s) read from the EEPROM * * Retrieves 16 bit word(s) read from EEPROM **/ static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data) { struct ixgbe_eeprom_info *eeprom = &hw->eeprom; s32 ret_val = IXGBE_ERR_CONFIG; DEBUGFUNC("ixgbe_read_eeprom_buffer_82599"); /* * If EEPROM is detected and can be addressed using 14 bits, * use EERD otherwise use bit bang */ if ((eeprom->type == ixgbe_eeprom_spi) && (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, data); else ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words, data); return ret_val; } /** * ixgbe_read_eeprom_82599 - Read EEPROM word using * fastest available method * * @hw: pointer to hardware structure * @offset: offset of word in the EEPROM to read * @data: word read from the EEPROM * * Reads a 16 bit word from the EEPROM **/ static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, u16 offset, u16 *data) { struct ixgbe_eeprom_info *eeprom = &hw->eeprom; s32 ret_val = IXGBE_ERR_CONFIG; DEBUGFUNC("ixgbe_read_eeprom_82599"); /* * If EEPROM is detected and can be addressed using 14 bits, * use EERD otherwise use bit bang */ if ((eeprom->type == ixgbe_eeprom_spi) && (offset <= IXGBE_EERD_MAX_ADDR)) ret_val = ixgbe_read_eerd_generic(hw, offset, data); else ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); return ret_val; } /** * ixgbe_reset_pipeline_82599 - perform pipeline reset * * @hw: pointer to hardware structure * * Reset pipeline by asserting Restart_AN together with LMS change to ensure * full pipeline reset. This function assumes the SW/FW lock is held. **/ s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) { s32 ret_val; u32 anlp1_reg = 0; u32 i, autoc_reg, autoc2_reg; /* Enable link if disabled in NVM */ autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); IXGBE_WRITE_FLUSH(hw); } autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); autoc_reg |= IXGBE_AUTOC_AN_RESTART; /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); /* Wait for AN to leave state 0 */ for (i = 0; i < 10; i++) { msec_delay(4); anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) break; } if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { DEBUGOUT("auto negotiation not completed\n"); ret_val = IXGBE_ERR_RESET_FAILED; goto reset_pipeline_out; } ret_val = IXGBE_SUCCESS; reset_pipeline_out: /* Write AUTOC register with original LMS field and Restart_AN */ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); IXGBE_WRITE_FLUSH(hw); return ret_val; } /** * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C * @hw: pointer to hardware structure * @byte_offset: byte offset to read * @dev_addr: address to read from * @data: value read * * Performs byte read operation to SFP module's EEPROM over I2C interface at * a specified device address. **/ static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data) { u32 esdp; s32 status; s32 timeout = 200; DEBUGFUNC("ixgbe_read_i2c_byte_82599"); if (hw->phy.qsfp_shared_i2c_bus == TRUE) { /* Acquire I2C bus ownership. */ esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); esdp |= IXGBE_ESDP_SDP0; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); while (timeout) { esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); if (esdp & IXGBE_ESDP_SDP1) break; msec_delay(5); timeout--; } if (!timeout) { DEBUGOUT("Driver can't access resource," " acquiring I2C bus timeout.\n"); status = IXGBE_ERR_I2C; goto release_i2c_access; } } status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); release_i2c_access: if (hw->phy.qsfp_shared_i2c_bus == TRUE) { /* Release I2C bus ownership. */ esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); esdp &= ~IXGBE_ESDP_SDP0; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); } return status; } /** * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C * @hw: pointer to hardware structure * @byte_offset: byte offset to write * @dev_addr: address to read from * @data: value to write * * Performs byte write operation to SFP module's EEPROM over I2C interface at * a specified device address. **/ static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data) { u32 esdp; s32 status; s32 timeout = 200; DEBUGFUNC("ixgbe_write_i2c_byte_82599"); if (hw->phy.qsfp_shared_i2c_bus == TRUE) { /* Acquire I2C bus ownership. */ esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); esdp |= IXGBE_ESDP_SDP0; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); while (timeout) { esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); if (esdp & IXGBE_ESDP_SDP1) break; msec_delay(5); timeout--; } if (!timeout) { DEBUGOUT("Driver can't access resource," " acquiring I2C bus timeout.\n"); status = IXGBE_ERR_I2C; goto release_i2c_access; } } status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); release_i2c_access: if (hw->phy.qsfp_shared_i2c_bus == TRUE) { /* Release I2C bus ownership. */ esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); esdp &= ~IXGBE_ESDP_SDP0; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); } return status; } diff --git a/sys/dev/ixgbe/ixgbe_common.c b/sys/dev/ixgbe/ixgbe_common.c index 7f32c112f74c..573f7684e959 100644 --- a/sys/dev/ixgbe/ixgbe_common.c +++ b/sys/dev/ixgbe/ixgbe_common.c @@ -1,5529 +1,5529 @@ /****************************************************************************** SPDX-License-Identifier: BSD-3-Clause Copyright (c) 2001-2017, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ /*$FreeBSD$*/ #include "ixgbe_common.h" #include "ixgbe_phy.h" #include "ixgbe_dcb.h" #include "ixgbe_dcb_82599.h" #include "ixgbe_api.h" static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, u16 count); static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); static void ixgbe_release_eeprom(struct ixgbe_hw *hw); static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, u16 *san_mac_offset); static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data); static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data); static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, u16 offset); /** * ixgbe_init_ops_generic - Inits function ptrs * @hw: pointer to the hardware structure * * Initialize the function pointers. **/ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) { struct ixgbe_eeprom_info *eeprom = &hw->eeprom; struct ixgbe_mac_info *mac = &hw->mac; u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); DEBUGFUNC("ixgbe_init_ops_generic"); /* EEPROM */ eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ if (eec & IXGBE_EEC_PRES) { eeprom->ops.read = ixgbe_read_eerd_generic; eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; } else { eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_bit_bang_generic; } eeprom->ops.write = ixgbe_write_eeprom_generic; eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_generic; eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; /* MAC */ mac->ops.init_hw = ixgbe_init_hw_generic; mac->ops.reset_hw = NULL; mac->ops.start_hw = ixgbe_start_hw_generic; mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; mac->ops.get_media_type = NULL; mac->ops.get_supported_physical_layer = NULL; mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; mac->ops.stop_adapter = ixgbe_stop_adapter_generic; mac->ops.get_bus_info = ixgbe_get_bus_info_generic; mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; mac->ops.prot_autoc_read = prot_autoc_read_generic; mac->ops.prot_autoc_write = prot_autoc_write_generic; /* LEDs */ mac->ops.led_on = ixgbe_led_on_generic; mac->ops.led_off = ixgbe_led_off_generic; mac->ops.blink_led_start = ixgbe_blink_led_start_generic; mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; /* RAR, Multicast, VLAN */ mac->ops.set_rar = ixgbe_set_rar_generic; mac->ops.clear_rar = ixgbe_clear_rar_generic; mac->ops.insert_mac_addr = NULL; mac->ops.set_vmdq = NULL; mac->ops.clear_vmdq = NULL; mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; mac->ops.enable_mc = ixgbe_enable_mc_generic; mac->ops.disable_mc = ixgbe_disable_mc_generic; mac->ops.clear_vfta = NULL; mac->ops.set_vfta = NULL; mac->ops.set_vlvf = NULL; mac->ops.init_uta_tables = NULL; mac->ops.enable_rx = ixgbe_enable_rx_generic; mac->ops.disable_rx = ixgbe_disable_rx_generic; /* Flow Control */ mac->ops.fc_enable = ixgbe_fc_enable_generic; mac->ops.setup_fc = ixgbe_setup_fc_generic; mac->ops.fc_autoneg = ixgbe_fc_autoneg; /* Link */ mac->ops.get_link_capabilities = NULL; mac->ops.setup_link = NULL; mac->ops.check_link = NULL; mac->ops.dmac_config = NULL; mac->ops.dmac_update_tcs = NULL; mac->ops.dmac_config_tcs = NULL; return IXGBE_SUCCESS; } /** * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation * of flow control * @hw: pointer to hardware structure * * This function returns TRUE if the device supports flow control * autonegotiation, and FALSE if it does not. * **/ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) { bool supported = FALSE; ixgbe_link_speed speed; bool link_up; DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); switch (hw->phy.media_type) { case ixgbe_media_type_fiber_fixed: case ixgbe_media_type_fiber_qsfp: case ixgbe_media_type_fiber: /* flow control autoneg black list */ switch (hw->device_id) { case IXGBE_DEV_ID_X550EM_A_SFP: case IXGBE_DEV_ID_X550EM_A_SFP_N: case IXGBE_DEV_ID_X550EM_A_QSFP: case IXGBE_DEV_ID_X550EM_A_QSFP_N: supported = FALSE; break; default: hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); /* if link is down, assume supported */ if (link_up) supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? TRUE : FALSE; else supported = TRUE; } break; case ixgbe_media_type_backplane: if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) supported = FALSE; else supported = TRUE; break; case ixgbe_media_type_copper: /* only some copper devices support flow control autoneg */ switch (hw->device_id) { case IXGBE_DEV_ID_82599_T3_LOM: case IXGBE_DEV_ID_X540T: case IXGBE_DEV_ID_X540T1: case IXGBE_DEV_ID_X540_BYPASS: case IXGBE_DEV_ID_X550T: case IXGBE_DEV_ID_X550T1: case IXGBE_DEV_ID_X550EM_X_10G_T: case IXGBE_DEV_ID_X550EM_A_10G_T: case IXGBE_DEV_ID_X550EM_A_1G_T: case IXGBE_DEV_ID_X550EM_A_1G_T_L: supported = TRUE; break; default: supported = FALSE; } default: break; } if (!supported) ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, "Device %x does not support flow control autoneg", hw->device_id); return supported; } /** * ixgbe_setup_fc_generic - Set up flow control * @hw: pointer to hardware structure * * Called at init time to set up flow control. **/ s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) { s32 ret_val = IXGBE_SUCCESS; u32 reg = 0, reg_bp = 0; u16 reg_cu = 0; bool locked = FALSE; DEBUGFUNC("ixgbe_setup_fc_generic"); /* Validate the requested mode */ if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; goto out; } /* * 10gig parts do not have a word in the EEPROM to determine the * default flow control setting, so we explicitly set it to full. */ if (hw->fc.requested_mode == ixgbe_fc_default) hw->fc.requested_mode = ixgbe_fc_full; /* * Set up the 1G and 10G flow control advertisement registers so the * HW will be able to do fc autoneg once the cable is plugged in. If * we link at 10G, the 1G advertisement is harmless and vice versa. */ switch (hw->phy.media_type) { case ixgbe_media_type_backplane: /* some MAC's need RMW protection on AUTOC */ ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); if (ret_val != IXGBE_SUCCESS) goto out; /* only backplane uses autoc */ /* FALLTHROUGH */ case ixgbe_media_type_fiber_fixed: case ixgbe_media_type_fiber_qsfp: case ixgbe_media_type_fiber: reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); break; case ixgbe_media_type_copper: hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); break; default: break; } /* * The possible values of fc.requested_mode are: * 0: Flow control is completely disabled * 1: Rx flow control is enabled (we can receive pause frames, * but not send pause frames). * 2: Tx flow control is enabled (we can send pause frames but * we do not support receiving pause frames). * 3: Both Rx and Tx flow control (symmetric) are enabled. * other: Invalid. */ switch (hw->fc.requested_mode) { case ixgbe_fc_none: /* Flow control completely disabled by software override. */ reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); if (hw->phy.media_type == ixgbe_media_type_backplane) reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); else if (hw->phy.media_type == ixgbe_media_type_copper) reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); break; case ixgbe_fc_tx_pause: /* * Tx Flow control is enabled, and Rx Flow control is * disabled by software override. */ reg |= IXGBE_PCS1GANA_ASM_PAUSE; reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; if (hw->phy.media_type == ixgbe_media_type_backplane) { reg_bp |= IXGBE_AUTOC_ASM_PAUSE; reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; } else if (hw->phy.media_type == ixgbe_media_type_copper) { reg_cu |= IXGBE_TAF_ASM_PAUSE; reg_cu &= ~IXGBE_TAF_SYM_PAUSE; } break; case ixgbe_fc_rx_pause: /* * Rx Flow control is enabled and Tx Flow control is * disabled by software override. Since there really * isn't a way to advertise that we are capable of RX * Pause ONLY, we will advertise that we support both * symmetric and asymmetric Rx PAUSE, as such we fall * through to the fc_full statement. Later, we will * disable the adapter's ability to send PAUSE frames. */ case ixgbe_fc_full: /* Flow control (both Rx and Tx) is enabled by SW override. */ reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; if (hw->phy.media_type == ixgbe_media_type_backplane) reg_bp |= IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE; else if (hw->phy.media_type == ixgbe_media_type_copper) reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; break; default: ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Flow control param set incorrectly\n"); ret_val = IXGBE_ERR_CONFIG; goto out; break; } if (hw->mac.type < ixgbe_mac_X540) { /* * Enable auto-negotiation between the MAC & PHY; * the MAC will advertise clause 37 flow control. */ IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); /* Disable AN timeout */ if (hw->fc.strict_ieee) reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); } /* * AUTOC restart handles negotiation of 1G and 10G on backplane * and copper. There is no need to set the PCS1GCTL register. * */ if (hw->phy.media_type == ixgbe_media_type_backplane) { reg_bp |= IXGBE_AUTOC_AN_RESTART; ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); if (ret_val) goto out; } else if ((hw->phy.media_type == ixgbe_media_type_copper) && (ixgbe_device_supports_autoneg_fc(hw))) { hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); } DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); out: return ret_val; } /** * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx * @hw: pointer to hardware structure * * Starts the hardware by filling the bus info structure and media type, clears * all on chip counters, initializes receive address registers, multicast * table, VLAN filter table, calls routine to set up link and flow control * settings, and leaves transmit and receive units disabled and uninitialized **/ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) { s32 ret_val; u32 ctrl_ext; u16 device_caps; DEBUGFUNC("ixgbe_start_hw_generic"); /* Set the media type */ hw->phy.media_type = hw->mac.ops.get_media_type(hw); /* PHY ops initialization must be done in reset_hw() */ /* Clear the VLAN filter table */ hw->mac.ops.clear_vfta(hw); /* Clear statistics registers */ hw->mac.ops.clear_hw_cntrs(hw); /* Set No Snoop Disable */ ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); IXGBE_WRITE_FLUSH(hw); /* Setup flow control */ ret_val = ixgbe_setup_fc(hw); if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); return ret_val; } /* Cache bit indicating need for crosstalk fix */ switch (hw->mac.type) { case ixgbe_mac_82599EB: case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_a: hw->mac.ops.get_device_caps(hw, &device_caps); if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) hw->need_crosstalk_fix = FALSE; else hw->need_crosstalk_fix = TRUE; break; default: hw->need_crosstalk_fix = FALSE; break; } /* Clear adapter stopped flag */ hw->adapter_stopped = FALSE; return IXGBE_SUCCESS; } /** * ixgbe_start_hw_gen2 - Init sequence for common device family * @hw: pointer to hw structure * * Performs the init sequence common to the second generation * of 10 GbE devices. * Devices in the second generation: * 82599 * X540 **/ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) { u32 i; u32 regval; /* Clear the rate limiters */ for (i = 0; i < hw->mac.max_tx_queues; i++) { IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); } IXGBE_WRITE_FLUSH(hw); /* Disable relaxed ordering */ for (i = 0; i < hw->mac.max_tx_queues; i++) { regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); } for (i = 0; i < hw->mac.max_rx_queues; i++) { regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | IXGBE_DCA_RXCTRL_HEAD_WRO_EN); IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); } return IXGBE_SUCCESS; } /** * ixgbe_init_hw_generic - Generic hardware initialization * @hw: pointer to hardware structure * * Initialize the hardware by resetting the hardware, filling the bus info * structure and media type, clears all on chip counters, initializes receive * address registers, multicast table, VLAN filter table, calls routine to set * up link and flow control settings, and leaves transmit and receive units * disabled and uninitialized **/ s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) { s32 status; DEBUGFUNC("ixgbe_init_hw_generic"); /* Reset the hardware */ status = hw->mac.ops.reset_hw(hw); if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { /* Start the HW */ status = hw->mac.ops.start_hw(hw); } /* Initialize the LED link active for LED blink support */ if (hw->mac.ops.init_led_link_act) hw->mac.ops.init_led_link_act(hw); if (status != IXGBE_SUCCESS) DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); return status; } /** * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters * @hw: pointer to hardware structure * * Clears all hardware statistics counters by reading them from the hardware * Statistics counters are clear on read. **/ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) { u16 i = 0; DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); IXGBE_READ_REG(hw, IXGBE_CRCERRS); IXGBE_READ_REG(hw, IXGBE_ILLERRC); IXGBE_READ_REG(hw, IXGBE_ERRBC); IXGBE_READ_REG(hw, IXGBE_MSPDC); for (i = 0; i < 8; i++) IXGBE_READ_REG(hw, IXGBE_MPC(i)); IXGBE_READ_REG(hw, IXGBE_MLFC); IXGBE_READ_REG(hw, IXGBE_MRFC); IXGBE_READ_REG(hw, IXGBE_RLEC); IXGBE_READ_REG(hw, IXGBE_LXONTXC); IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); if (hw->mac.type >= ixgbe_mac_82599EB) { IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); } else { IXGBE_READ_REG(hw, IXGBE_LXONRXC); IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); } for (i = 0; i < 8; i++) { IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); if (hw->mac.type >= ixgbe_mac_82599EB) { IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); } else { IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); } } if (hw->mac.type >= ixgbe_mac_82599EB) for (i = 0; i < 8; i++) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); IXGBE_READ_REG(hw, IXGBE_PRC64); IXGBE_READ_REG(hw, IXGBE_PRC127); IXGBE_READ_REG(hw, IXGBE_PRC255); IXGBE_READ_REG(hw, IXGBE_PRC511); IXGBE_READ_REG(hw, IXGBE_PRC1023); IXGBE_READ_REG(hw, IXGBE_PRC1522); IXGBE_READ_REG(hw, IXGBE_GPRC); IXGBE_READ_REG(hw, IXGBE_BPRC); IXGBE_READ_REG(hw, IXGBE_MPRC); IXGBE_READ_REG(hw, IXGBE_GPTC); IXGBE_READ_REG(hw, IXGBE_GORCL); IXGBE_READ_REG(hw, IXGBE_GORCH); IXGBE_READ_REG(hw, IXGBE_GOTCL); IXGBE_READ_REG(hw, IXGBE_GOTCH); if (hw->mac.type == ixgbe_mac_82598EB) for (i = 0; i < 8; i++) IXGBE_READ_REG(hw, IXGBE_RNBC(i)); IXGBE_READ_REG(hw, IXGBE_RUC); IXGBE_READ_REG(hw, IXGBE_RFC); IXGBE_READ_REG(hw, IXGBE_ROC); IXGBE_READ_REG(hw, IXGBE_RJC); IXGBE_READ_REG(hw, IXGBE_MNGPRC); IXGBE_READ_REG(hw, IXGBE_MNGPDC); IXGBE_READ_REG(hw, IXGBE_MNGPTC); IXGBE_READ_REG(hw, IXGBE_TORL); IXGBE_READ_REG(hw, IXGBE_TORH); IXGBE_READ_REG(hw, IXGBE_TPR); IXGBE_READ_REG(hw, IXGBE_TPT); IXGBE_READ_REG(hw, IXGBE_PTC64); IXGBE_READ_REG(hw, IXGBE_PTC127); IXGBE_READ_REG(hw, IXGBE_PTC255); IXGBE_READ_REG(hw, IXGBE_PTC511); IXGBE_READ_REG(hw, IXGBE_PTC1023); IXGBE_READ_REG(hw, IXGBE_PTC1522); IXGBE_READ_REG(hw, IXGBE_MPTC); IXGBE_READ_REG(hw, IXGBE_BPTC); for (i = 0; i < 16; i++) { IXGBE_READ_REG(hw, IXGBE_QPRC(i)); IXGBE_READ_REG(hw, IXGBE_QPTC(i)); if (hw->mac.type >= ixgbe_mac_82599EB) { IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); } else { IXGBE_READ_REG(hw, IXGBE_QBRC(i)); IXGBE_READ_REG(hw, IXGBE_QBTC(i)); } } if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { if (hw->phy.id == 0) ixgbe_identify_phy(hw); hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, IXGBE_MDIO_PCS_DEV_TYPE, &i); hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, IXGBE_MDIO_PCS_DEV_TYPE, &i); hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, IXGBE_MDIO_PCS_DEV_TYPE, &i); hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, IXGBE_MDIO_PCS_DEV_TYPE, &i); } return IXGBE_SUCCESS; } /** * ixgbe_read_pba_string_generic - Reads part number string from EEPROM * @hw: pointer to hardware structure * @pba_num: stores the part number string from the EEPROM * @pba_num_size: part number string buffer length * * Reads the part number string from the EEPROM. **/ s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) { s32 ret_val; u16 data; u16 pba_ptr; u16 offset; u16 length; DEBUGFUNC("ixgbe_read_pba_string_generic"); if (pba_num == NULL) { DEBUGOUT("PBA string buffer was null\n"); return IXGBE_ERR_INVALID_ARGUMENT; } ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); return ret_val; } ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); if (ret_val) { DEBUGOUT("NVM Read Error\n"); return ret_val; } /* * if data is not ptr guard the PBA must be in legacy format which * means pba_ptr is actually our second data word for the PBA number * and we can decode it into an ascii string */ if (data != IXGBE_PBANUM_PTR_GUARD) { DEBUGOUT("NVM PBA number is not stored as string\n"); /* we will need 11 characters to store the PBA */ if (pba_num_size < 11) { DEBUGOUT("PBA string buffer too small\n"); return IXGBE_ERR_NO_SPACE; } /* extract hex string from data and pba_ptr */ pba_num[0] = (data >> 12) & 0xF; pba_num[1] = (data >> 8) & 0xF; pba_num[2] = (data >> 4) & 0xF; pba_num[3] = data & 0xF; pba_num[4] = (pba_ptr >> 12) & 0xF; pba_num[5] = (pba_ptr >> 8) & 0xF; pba_num[6] = '-'; pba_num[7] = 0; pba_num[8] = (pba_ptr >> 4) & 0xF; pba_num[9] = pba_ptr & 0xF; /* put a null character on the end of our string */ pba_num[10] = '\0'; /* switch all the data but the '-' to hex char */ for (offset = 0; offset < 10; offset++) { if (pba_num[offset] < 0xA) pba_num[offset] += '0'; else if (pba_num[offset] < 0x10) pba_num[offset] += 'A' - 0xA; } return IXGBE_SUCCESS; } ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); if (ret_val) { DEBUGOUT("NVM Read Error\n"); return ret_val; } if (length == 0xFFFF || length == 0) { DEBUGOUT("NVM PBA number section invalid length\n"); return IXGBE_ERR_PBA_SECTION; } /* check if pba_num buffer is big enough */ if (pba_num_size < (((u32)length * 2) - 1)) { DEBUGOUT("PBA string buffer too small\n"); return IXGBE_ERR_NO_SPACE; } /* trim pba length from start of string */ pba_ptr++; length--; for (offset = 0; offset < length; offset++) { ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); return ret_val; } pba_num[offset * 2] = (u8)(data >> 8); pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); } pba_num[offset * 2] = '\0'; return IXGBE_SUCCESS; } /** * ixgbe_read_pba_num_generic - Reads part number from EEPROM * @hw: pointer to hardware structure * @pba_num: stores the part number from the EEPROM * * Reads the part number from the EEPROM. **/ s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) { s32 ret_val; u16 data; DEBUGFUNC("ixgbe_read_pba_num_generic"); ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); return ret_val; } else if (data == IXGBE_PBANUM_PTR_GUARD) { DEBUGOUT("NVM Not supported\n"); return IXGBE_NOT_IMPLEMENTED; } *pba_num = (u32)(data << 16); ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); return ret_val; } - *pba_num |= data; + *pba_num |= (u32)data; return IXGBE_SUCCESS; } /** * ixgbe_read_pba_raw * @hw: pointer to the HW structure * @eeprom_buf: optional pointer to EEPROM image * @eeprom_buf_size: size of EEPROM image in words * @max_pba_block_size: PBA block size limit * @pba: pointer to output PBA structure * * Reads PBA from EEPROM image when eeprom_buf is not NULL. * Reads PBA from physical EEPROM device when eeprom_buf is NULL. * **/ s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, u32 eeprom_buf_size, u16 max_pba_block_size, struct ixgbe_pba *pba) { s32 ret_val; u16 pba_block_size; if (pba == NULL) return IXGBE_ERR_PARAM; if (eeprom_buf == NULL) { ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, &pba->word[0]); if (ret_val) return ret_val; } else { if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; } else { return IXGBE_ERR_PARAM; } } if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { if (pba->pba_block == NULL) return IXGBE_ERR_PARAM; ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, eeprom_buf_size, &pba_block_size); if (ret_val) return ret_val; if (pba_block_size > max_pba_block_size) return IXGBE_ERR_PARAM; if (eeprom_buf == NULL) { ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], pba_block_size, pba->pba_block); if (ret_val) return ret_val; } else { if (eeprom_buf_size > (u32)(pba->word[1] + pba_block_size)) { memcpy(pba->pba_block, &eeprom_buf[pba->word[1]], pba_block_size * sizeof(u16)); } else { return IXGBE_ERR_PARAM; } } } return IXGBE_SUCCESS; } /** * ixgbe_write_pba_raw * @hw: pointer to the HW structure * @eeprom_buf: optional pointer to EEPROM image * @eeprom_buf_size: size of EEPROM image in words * @pba: pointer to PBA structure * * Writes PBA to EEPROM image when eeprom_buf is not NULL. * Writes PBA to physical EEPROM device when eeprom_buf is NULL. * **/ s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, u32 eeprom_buf_size, struct ixgbe_pba *pba) { s32 ret_val; if (pba == NULL) return IXGBE_ERR_PARAM; if (eeprom_buf == NULL) { ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, &pba->word[0]); if (ret_val) return ret_val; } else { if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; } else { return IXGBE_ERR_PARAM; } } if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { if (pba->pba_block == NULL) return IXGBE_ERR_PARAM; if (eeprom_buf == NULL) { ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], pba->pba_block[0], pba->pba_block); if (ret_val) return ret_val; } else { if (eeprom_buf_size > (u32)(pba->word[1] + pba->pba_block[0])) { memcpy(&eeprom_buf[pba->word[1]], pba->pba_block, pba->pba_block[0] * sizeof(u16)); } else { return IXGBE_ERR_PARAM; } } } return IXGBE_SUCCESS; } /** * ixgbe_get_pba_block_size * @hw: pointer to the HW structure * @eeprom_buf: optional pointer to EEPROM image * @eeprom_buf_size: size of EEPROM image in words * @pba_data_size: pointer to output variable * * Returns the size of the PBA block in words. Function operates on EEPROM * image if the eeprom_buf pointer is not NULL otherwise it accesses physical * EEPROM device. * **/ s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, u32 eeprom_buf_size, u16 *pba_block_size) { s32 ret_val; u16 pba_word[2]; u16 length; DEBUGFUNC("ixgbe_get_pba_block_size"); if (eeprom_buf == NULL) { ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, &pba_word[0]); if (ret_val) return ret_val; } else { if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; } else { return IXGBE_ERR_PARAM; } } if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { if (eeprom_buf == NULL) { ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, &length); if (ret_val) return ret_val; } else { if (eeprom_buf_size > pba_word[1]) length = eeprom_buf[pba_word[1] + 0]; else return IXGBE_ERR_PARAM; } if (length == 0xFFFF || length == 0) return IXGBE_ERR_PBA_SECTION; } else { /* PBA number in legacy format, there is no PBA Block. */ length = 0; } if (pba_block_size != NULL) *pba_block_size = length; return IXGBE_SUCCESS; } /** * ixgbe_get_mac_addr_generic - Generic get MAC address * @hw: pointer to hardware structure * @mac_addr: Adapter MAC address * * Reads the adapter's MAC address from first Receive Address Register (RAR0) * A reset of the adapter must be performed prior to calling this function * in order for the MAC address to have been loaded from the EEPROM into RAR0 **/ s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) { u32 rar_high; u32 rar_low; u16 i; DEBUGFUNC("ixgbe_get_mac_addr_generic"); rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); for (i = 0; i < 4; i++) mac_addr[i] = (u8)(rar_low >> (i*8)); for (i = 0; i < 2; i++) mac_addr[i+4] = (u8)(rar_high >> (i*8)); return IXGBE_SUCCESS; } /** * ixgbe_set_pci_config_data_generic - Generic store PCI bus info * @hw: pointer to hardware structure * @link_status: the link status returned by the PCI config space * * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure **/ void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) { struct ixgbe_mac_info *mac = &hw->mac; if (hw->bus.type == ixgbe_bus_type_unknown) hw->bus.type = ixgbe_bus_type_pci_express; switch (link_status & IXGBE_PCI_LINK_WIDTH) { case IXGBE_PCI_LINK_WIDTH_1: hw->bus.width = ixgbe_bus_width_pcie_x1; break; case IXGBE_PCI_LINK_WIDTH_2: hw->bus.width = ixgbe_bus_width_pcie_x2; break; case IXGBE_PCI_LINK_WIDTH_4: hw->bus.width = ixgbe_bus_width_pcie_x4; break; case IXGBE_PCI_LINK_WIDTH_8: hw->bus.width = ixgbe_bus_width_pcie_x8; break; default: hw->bus.width = ixgbe_bus_width_unknown; break; } switch (link_status & IXGBE_PCI_LINK_SPEED) { case IXGBE_PCI_LINK_SPEED_2500: hw->bus.speed = ixgbe_bus_speed_2500; break; case IXGBE_PCI_LINK_SPEED_5000: hw->bus.speed = ixgbe_bus_speed_5000; break; case IXGBE_PCI_LINK_SPEED_8000: hw->bus.speed = ixgbe_bus_speed_8000; break; default: hw->bus.speed = ixgbe_bus_speed_unknown; break; } mac->ops.set_lan_id(hw); } /** * ixgbe_get_bus_info_generic - Generic set PCI bus info * @hw: pointer to hardware structure * * Gets the PCI bus info (speed, width, type) then calls helper function to * store this data within the ixgbe_hw structure. **/ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) { u16 link_status; DEBUGFUNC("ixgbe_get_bus_info_generic"); /* Get the negotiated link width and speed from PCI config space */ link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); ixgbe_set_pci_config_data_generic(hw, link_status); return IXGBE_SUCCESS; } /** * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices * @hw: pointer to the HW structure * * Determines the LAN function id by reading memory-mapped registers and swaps * the port value if requested, and set MAC instance for devices that share * CS4227. **/ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) { struct ixgbe_bus_info *bus = &hw->bus; u32 reg; u16 ee_ctrl_4; DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); reg = IXGBE_READ_REG(hw, IXGBE_STATUS); bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; bus->lan_id = (u8)bus->func; /* check for a port swap */ reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); if (reg & IXGBE_FACTPS_LFS) bus->func ^= 0x1; /* Get MAC instance from EEPROM for configuring CS4227 */ if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> IXGBE_EE_CTRL_4_INST_ID_SHIFT; } } /** * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units * @hw: pointer to hardware structure * * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, * disables transmit and receive units. The adapter_stopped flag is used by * the shared code and drivers to determine if the adapter is in a stopped * state and should not touch the hardware. **/ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) { u32 reg_val; u16 i; DEBUGFUNC("ixgbe_stop_adapter_generic"); /* * Set the adapter_stopped flag so other driver functions stop touching * the hardware */ hw->adapter_stopped = TRUE; /* Disable the receive unit */ ixgbe_disable_rx(hw); /* Clear interrupt mask to stop interrupts from being generated */ IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); /* Clear any pending interrupts, flush previous writes */ IXGBE_READ_REG(hw, IXGBE_EICR); /* Disable the transmit unit. Each queue must be disabled. */ for (i = 0; i < hw->mac.max_tx_queues; i++) IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); /* Disable the receive unit by stopping each queue */ for (i = 0; i < hw->mac.max_rx_queues; i++) { reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); reg_val &= ~IXGBE_RXDCTL_ENABLE; reg_val |= IXGBE_RXDCTL_SWFLSH; IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); } /* flush all queues disables */ IXGBE_WRITE_FLUSH(hw); msec_delay(2); /* * Prevent the PCI-E bus from hanging by disabling PCI-E master * access and verify no pending requests */ return ixgbe_disable_pcie_master(hw); } /** * ixgbe_init_led_link_act_generic - Store the LED index link/activity. * @hw: pointer to hardware structure * * Store the index for the link active LED. This will be used to support * blinking the LED. **/ s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) { struct ixgbe_mac_info *mac = &hw->mac; u32 led_reg, led_mode; u8 i; led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); /* Get LED link active from the LEDCTL register */ for (i = 0; i < 4; i++) { led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == IXGBE_LED_LINK_ACTIVE) { mac->led_link_act = i; return IXGBE_SUCCESS; } } /* * If LEDCTL register does not have the LED link active set, then use * known MAC defaults. */ switch (hw->mac.type) { case ixgbe_mac_X550EM_a: case ixgbe_mac_X550EM_x: mac->led_link_act = 1; break; default: mac->led_link_act = 2; } return IXGBE_SUCCESS; } /** * ixgbe_led_on_generic - Turns on the software controllable LEDs. * @hw: pointer to hardware structure * @index: led number to turn on **/ s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) { u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); DEBUGFUNC("ixgbe_led_on_generic"); if (index > 3) return IXGBE_ERR_PARAM; /* To turn on the LED, set mode to ON. */ led_reg &= ~IXGBE_LED_MODE_MASK(index); led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); IXGBE_WRITE_FLUSH(hw); return IXGBE_SUCCESS; } /** * ixgbe_led_off_generic - Turns off the software controllable LEDs. * @hw: pointer to hardware structure * @index: led number to turn off **/ s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) { u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); DEBUGFUNC("ixgbe_led_off_generic"); if (index > 3) return IXGBE_ERR_PARAM; /* To turn off the LED, set mode to OFF. */ led_reg &= ~IXGBE_LED_MODE_MASK(index); led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); IXGBE_WRITE_FLUSH(hw); return IXGBE_SUCCESS; } /** * ixgbe_init_eeprom_params_generic - Initialize EEPROM params * @hw: pointer to hardware structure * * Initializes the EEPROM parameters ixgbe_eeprom_info within the * ixgbe_hw struct in order to set up EEPROM access. **/ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) { struct ixgbe_eeprom_info *eeprom = &hw->eeprom; u32 eec; u16 eeprom_size; DEBUGFUNC("ixgbe_init_eeprom_params_generic"); if (eeprom->type == ixgbe_eeprom_uninitialized) { eeprom->type = ixgbe_eeprom_none; /* Set default semaphore delay to 10ms which is a well * tested value */ eeprom->semaphore_delay = 10; /* Clear EEPROM page size, it will be initialized as needed */ eeprom->word_page_size = 0; /* * Check for EEPROM present first. * If not present leave as none */ eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); if (eec & IXGBE_EEC_PRES) { eeprom->type = ixgbe_eeprom_spi; /* * SPI EEPROM is assumed here. This code would need to * change if a future EEPROM is not SPI. */ eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> IXGBE_EEC_SIZE_SHIFT); eeprom->word_size = 1 << (eeprom_size + IXGBE_EEPROM_WORD_SIZE_SHIFT); } if (eec & IXGBE_EEC_ADDR_SIZE) eeprom->address_bits = 16; else eeprom->address_bits = 8; DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " "%d\n", eeprom->type, eeprom->word_size, eeprom->address_bits); } return IXGBE_SUCCESS; } /** * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang * @hw: pointer to hardware structure * @offset: offset within the EEPROM to write * @words: number of word(s) * @data: 16 bit word(s) to write to EEPROM * * Reads 16 bit word(s) from EEPROM through bit-bang method **/ s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data) { s32 status = IXGBE_SUCCESS; u16 i, count; DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); hw->eeprom.ops.init_params(hw); if (words == 0) { status = IXGBE_ERR_INVALID_ARGUMENT; goto out; } if (offset + words > hw->eeprom.word_size) { status = IXGBE_ERR_EEPROM; goto out; } /* * The EEPROM page size cannot be queried from the chip. We do lazy * initialization. It is worth to do that when we write large buffer. */ if ((hw->eeprom.word_page_size == 0) && (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) ixgbe_detect_eeprom_page_size_generic(hw, offset); /* * We cannot hold synchronization semaphores for too long * to avoid other entity starvation. However it is more efficient * to read in bursts than synchronizing access for each word. */ for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, count, &data[i]); if (status != IXGBE_SUCCESS) break; } out: return status; } /** * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM * @hw: pointer to hardware structure * @offset: offset within the EEPROM to be written to * @words: number of word(s) * @data: 16 bit word(s) to be written to the EEPROM * * If ixgbe_eeprom_update_checksum is not called after this function, the * EEPROM will most likely contain an invalid checksum. **/ static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data) { s32 status; u16 word; u16 page_size; u16 i; u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); /* Prepare the EEPROM for writing */ status = ixgbe_acquire_eeprom(hw); if (status == IXGBE_SUCCESS) { if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { ixgbe_release_eeprom(hw); status = IXGBE_ERR_EEPROM; } } if (status == IXGBE_SUCCESS) { for (i = 0; i < words; i++) { ixgbe_standby_eeprom(hw); /* Send the WRITE ENABLE command (8 bit opcode ) */ ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, IXGBE_EEPROM_OPCODE_BITS); ixgbe_standby_eeprom(hw); /* * Some SPI eeproms use the 8th address bit embedded * in the opcode */ if ((hw->eeprom.address_bits == 8) && ((offset + i) >= 128)) write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; /* Send the Write command (8-bit opcode + addr) */ ixgbe_shift_out_eeprom_bits(hw, write_opcode, IXGBE_EEPROM_OPCODE_BITS); ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), hw->eeprom.address_bits); page_size = hw->eeprom.word_page_size; /* Send the data in burst via SPI*/ do { word = data[i]; word = (word >> 8) | (word << 8); ixgbe_shift_out_eeprom_bits(hw, word, 16); if (page_size == 0) break; /* do not wrap around page */ if (((offset + i) & (page_size - 1)) == (page_size - 1)) break; } while (++i < words); ixgbe_standby_eeprom(hw); msec_delay(10); } /* Done with writing - release the EEPROM */ ixgbe_release_eeprom(hw); } return status; } /** * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM * @hw: pointer to hardware structure * @offset: offset within the EEPROM to be written to * @data: 16 bit word to be written to the EEPROM * * If ixgbe_eeprom_update_checksum is not called after this function, the * EEPROM will most likely contain an invalid checksum. **/ s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) { s32 status; DEBUGFUNC("ixgbe_write_eeprom_generic"); hw->eeprom.ops.init_params(hw); if (offset >= hw->eeprom.word_size) { status = IXGBE_ERR_EEPROM; goto out; } status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); out: return status; } /** * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang * @hw: pointer to hardware structure * @offset: offset within the EEPROM to be read * @data: read 16 bit words(s) from EEPROM * @words: number of word(s) * * Reads 16 bit word(s) from EEPROM through bit-bang method **/ s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data) { s32 status = IXGBE_SUCCESS; u16 i, count; DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); hw->eeprom.ops.init_params(hw); if (words == 0) { status = IXGBE_ERR_INVALID_ARGUMENT; goto out; } if (offset + words > hw->eeprom.word_size) { status = IXGBE_ERR_EEPROM; goto out; } /* * We cannot hold synchronization semaphores for too long * to avoid other entity starvation. However it is more efficient * to read in bursts than synchronizing access for each word. */ for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, count, &data[i]); if (status != IXGBE_SUCCESS) break; } out: return status; } /** * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang * @hw: pointer to hardware structure * @offset: offset within the EEPROM to be read * @words: number of word(s) * @data: read 16 bit word(s) from EEPROM * * Reads 16 bit word(s) from EEPROM through bit-bang method **/ static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data) { s32 status; u16 word_in; u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; u16 i; DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); /* Prepare the EEPROM for reading */ status = ixgbe_acquire_eeprom(hw); if (status == IXGBE_SUCCESS) { if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { ixgbe_release_eeprom(hw); status = IXGBE_ERR_EEPROM; } } if (status == IXGBE_SUCCESS) { for (i = 0; i < words; i++) { ixgbe_standby_eeprom(hw); /* * Some SPI eeproms use the 8th address bit embedded * in the opcode */ if ((hw->eeprom.address_bits == 8) && ((offset + i) >= 128)) read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; /* Send the READ command (opcode + addr) */ ixgbe_shift_out_eeprom_bits(hw, read_opcode, IXGBE_EEPROM_OPCODE_BITS); ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), hw->eeprom.address_bits); /* Read the data. */ word_in = ixgbe_shift_in_eeprom_bits(hw, 16); data[i] = (word_in >> 8) | (word_in << 8); } /* End this read operation */ ixgbe_release_eeprom(hw); } return status; } /** * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang * @hw: pointer to hardware structure * @offset: offset within the EEPROM to be read * @data: read 16 bit value from EEPROM * * Reads 16 bit value from EEPROM through bit-bang method **/ s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) { s32 status; DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); hw->eeprom.ops.init_params(hw); if (offset >= hw->eeprom.word_size) { status = IXGBE_ERR_EEPROM; goto out; } status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); out: return status; } /** * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD * @hw: pointer to hardware structure * @offset: offset of word in the EEPROM to read * @words: number of word(s) * @data: 16 bit word(s) from the EEPROM * * Reads a 16 bit word(s) from the EEPROM using the EERD register. **/ s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data) { u32 eerd; s32 status = IXGBE_SUCCESS; u32 i; DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); hw->eeprom.ops.init_params(hw); if (words == 0) { status = IXGBE_ERR_INVALID_ARGUMENT; ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); goto out; } if (offset >= hw->eeprom.word_size) { status = IXGBE_ERR_EEPROM; ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); goto out; } for (i = 0; i < words; i++) { eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | IXGBE_EEPROM_RW_REG_START; IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); if (status == IXGBE_SUCCESS) { data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> IXGBE_EEPROM_RW_REG_DATA); } else { DEBUGOUT("Eeprom read timed out\n"); goto out; } } out: return status; } /** * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size * @hw: pointer to hardware structure * @offset: offset within the EEPROM to be used as a scratch pad * * Discover EEPROM page size by writing marching data at given offset. * This function is called only when we are writing a new large buffer * at given offset so the data would be overwritten anyway. **/ static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, u16 offset) { u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; s32 status = IXGBE_SUCCESS; u16 i; DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) data[i] = i; hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, IXGBE_EEPROM_PAGE_SIZE_MAX, data); hw->eeprom.word_page_size = 0; if (status != IXGBE_SUCCESS) goto out; status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); if (status != IXGBE_SUCCESS) goto out; /* * When writing in burst more than the actual page size * EEPROM address wraps around current page. */ hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; DEBUGOUT1("Detected EEPROM page size = %d words.", hw->eeprom.word_page_size); out: return status; } /** * ixgbe_read_eerd_generic - Read EEPROM word using EERD * @hw: pointer to hardware structure * @offset: offset of word in the EEPROM to read * @data: word read from the EEPROM * * Reads a 16 bit word from the EEPROM using the EERD register. **/ s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) { return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); } /** * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR * @hw: pointer to hardware structure * @offset: offset of word in the EEPROM to write * @words: number of word(s) * @data: word(s) write to the EEPROM * * Write a 16 bit word(s) to the EEPROM using the EEWR register. **/ s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data) { u32 eewr; s32 status = IXGBE_SUCCESS; u16 i; DEBUGFUNC("ixgbe_write_eewr_generic"); hw->eeprom.ops.init_params(hw); if (words == 0) { status = IXGBE_ERR_INVALID_ARGUMENT; ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); goto out; } if (offset >= hw->eeprom.word_size) { status = IXGBE_ERR_EEPROM; ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); goto out; } for (i = 0; i < words; i++) { eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | (data[i] << IXGBE_EEPROM_RW_REG_DATA) | IXGBE_EEPROM_RW_REG_START; status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); if (status != IXGBE_SUCCESS) { DEBUGOUT("Eeprom write EEWR timed out\n"); goto out; } IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); if (status != IXGBE_SUCCESS) { DEBUGOUT("Eeprom write EEWR timed out\n"); goto out; } } out: return status; } /** * ixgbe_write_eewr_generic - Write EEPROM word using EEWR * @hw: pointer to hardware structure * @offset: offset of word in the EEPROM to write * @data: word write to the EEPROM * * Write a 16 bit word to the EEPROM using the EEWR register. **/ s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) { return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); } /** * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status * @hw: pointer to hardware structure * @ee_reg: EEPROM flag for polling * * Polls the status bit (bit 1) of the EERD or EEWR to determine when the * read or write is done respectively. **/ s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) { u32 i; u32 reg; s32 status = IXGBE_ERR_EEPROM; DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { if (ee_reg == IXGBE_NVM_POLL_READ) reg = IXGBE_READ_REG(hw, IXGBE_EERD); else reg = IXGBE_READ_REG(hw, IXGBE_EEWR); if (reg & IXGBE_EEPROM_RW_REG_DONE) { status = IXGBE_SUCCESS; break; } usec_delay(5); } if (i == IXGBE_EERD_EEWR_ATTEMPTS) ERROR_REPORT1(IXGBE_ERROR_POLLING, "EEPROM read/write done polling timed out"); return status; } /** * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang * @hw: pointer to hardware structure * * Prepares EEPROM for access using bit-bang method. This function should * be called before issuing a command to the EEPROM. **/ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) { s32 status = IXGBE_SUCCESS; u32 eec; u32 i; DEBUGFUNC("ixgbe_acquire_eeprom"); if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) status = IXGBE_ERR_SWFW_SYNC; if (status == IXGBE_SUCCESS) { eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); /* Request EEPROM Access */ eec |= IXGBE_EEC_REQ; IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); if (eec & IXGBE_EEC_GNT) break; usec_delay(5); } /* Release if grant not acquired */ if (!(eec & IXGBE_EEC_GNT)) { eec &= ~IXGBE_EEC_REQ; IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); DEBUGOUT("Could not acquire EEPROM grant\n"); hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); status = IXGBE_ERR_EEPROM; } /* Setup EEPROM for Read/Write */ if (status == IXGBE_SUCCESS) { /* Clear CS and SK */ eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); IXGBE_WRITE_FLUSH(hw); usec_delay(1); } } return status; } /** * ixgbe_get_eeprom_semaphore - Get hardware semaphore * @hw: pointer to hardware structure * * Sets the hardware semaphores so EEPROM access can occur for bit-bang method **/ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) { s32 status = IXGBE_ERR_EEPROM; u32 timeout = 2000; u32 i; u32 swsm; DEBUGFUNC("ixgbe_get_eeprom_semaphore"); /* Get SMBI software semaphore between device drivers first */ for (i = 0; i < timeout; i++) { /* * If the SMBI bit is 0 when we read it, then the bit will be * set and we have the semaphore */ swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); if (!(swsm & IXGBE_SWSM_SMBI)) { status = IXGBE_SUCCESS; break; } usec_delay(50); } if (i == timeout) { DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " "not granted.\n"); /* * this release is particularly important because our attempts * above to get the semaphore may have succeeded, and if there * was a timeout, we should unconditionally clear the semaphore * bits to free the driver to make progress */ ixgbe_release_eeprom_semaphore(hw); usec_delay(50); /* * one last try * If the SMBI bit is 0 when we read it, then the bit will be * set and we have the semaphore */ swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); if (!(swsm & IXGBE_SWSM_SMBI)) status = IXGBE_SUCCESS; } /* Now get the semaphore between SW/FW through the SWESMBI bit */ if (status == IXGBE_SUCCESS) { for (i = 0; i < timeout; i++) { swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); /* Set the SW EEPROM semaphore bit to request access */ swsm |= IXGBE_SWSM_SWESMBI; IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); /* * If we set the bit successfully then we got the * semaphore. */ swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); if (swsm & IXGBE_SWSM_SWESMBI) break; usec_delay(50); } /* * Release semaphores and return error if SW EEPROM semaphore * was not granted because we don't have access to the EEPROM */ if (i >= timeout) { ERROR_REPORT1(IXGBE_ERROR_POLLING, "SWESMBI Software EEPROM semaphore not granted.\n"); ixgbe_release_eeprom_semaphore(hw); status = IXGBE_ERR_EEPROM; } } else { ERROR_REPORT1(IXGBE_ERROR_POLLING, "Software semaphore SMBI between device drivers " "not granted.\n"); } return status; } /** * ixgbe_release_eeprom_semaphore - Release hardware semaphore * @hw: pointer to hardware structure * * This function clears hardware semaphore bits. **/ static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) { u32 swsm; DEBUGFUNC("ixgbe_release_eeprom_semaphore"); swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); IXGBE_WRITE_FLUSH(hw); } /** * ixgbe_ready_eeprom - Polls for EEPROM ready * @hw: pointer to hardware structure **/ static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) { s32 status = IXGBE_SUCCESS; u16 i; u8 spi_stat_reg; DEBUGFUNC("ixgbe_ready_eeprom"); /* * Read "Status Register" repeatedly until the LSB is cleared. The * EEPROM will signal that the command has been completed by clearing * bit 0 of the internal status register. If it's not cleared within * 5 milliseconds, then error out. */ for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, IXGBE_EEPROM_OPCODE_BITS); spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) break; usec_delay(5); ixgbe_standby_eeprom(hw); } /* * On some parts, SPI write time could vary from 0-20mSec on 3.3V * devices (and only 0-5mSec on 5V devices) */ if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { DEBUGOUT("SPI EEPROM Status error\n"); status = IXGBE_ERR_EEPROM; } return status; } /** * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state * @hw: pointer to hardware structure **/ static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) { u32 eec; DEBUGFUNC("ixgbe_standby_eeprom"); eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); /* Toggle CS to flush commands */ eec |= IXGBE_EEC_CS; IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); IXGBE_WRITE_FLUSH(hw); usec_delay(1); eec &= ~IXGBE_EEC_CS; IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); IXGBE_WRITE_FLUSH(hw); usec_delay(1); } /** * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. * @hw: pointer to hardware structure * @data: data to send to the EEPROM * @count: number of bits to shift out **/ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, u16 count) { u32 eec; u32 mask; u32 i; DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); /* * Mask is used to shift "count" bits of "data" out to the EEPROM * one bit at a time. Determine the starting bit based on count */ mask = 0x01 << (count - 1); for (i = 0; i < count; i++) { /* * A "1" is shifted out to the EEPROM by setting bit "DI" to a * "1", and then raising and then lowering the clock (the SK * bit controls the clock input to the EEPROM). A "0" is * shifted out to the EEPROM by setting "DI" to "0" and then * raising and then lowering the clock. */ if (data & mask) eec |= IXGBE_EEC_DI; else eec &= ~IXGBE_EEC_DI; IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); IXGBE_WRITE_FLUSH(hw); usec_delay(1); ixgbe_raise_eeprom_clk(hw, &eec); ixgbe_lower_eeprom_clk(hw, &eec); /* * Shift mask to signify next bit of data to shift in to the * EEPROM */ mask = mask >> 1; } /* We leave the "DI" bit set to "0" when we leave this routine. */ eec &= ~IXGBE_EEC_DI; IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); IXGBE_WRITE_FLUSH(hw); } /** * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM * @hw: pointer to hardware structure * @count: number of bits to shift **/ static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) { u32 eec; u32 i; u16 data = 0; DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); /* * In order to read a register from the EEPROM, we need to shift * 'count' bits in from the EEPROM. Bits are "shifted in" by raising * the clock input to the EEPROM (setting the SK bit), and then reading * the value of the "DO" bit. During this "shifting in" process the * "DI" bit should always be clear. */ eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); for (i = 0; i < count; i++) { data = data << 1; ixgbe_raise_eeprom_clk(hw, &eec); eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); eec &= ~(IXGBE_EEC_DI); if (eec & IXGBE_EEC_DO) data |= 1; ixgbe_lower_eeprom_clk(hw, &eec); } return data; } /** * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. * @hw: pointer to hardware structure * @eec: EEC register's current value **/ static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) { DEBUGFUNC("ixgbe_raise_eeprom_clk"); /* * Raise the clock input to the EEPROM * (setting the SK bit), then delay */ *eec = *eec | IXGBE_EEC_SK; IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); IXGBE_WRITE_FLUSH(hw); usec_delay(1); } /** * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. * @hw: pointer to hardware structure * @eec: EEC's current value **/ static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) { DEBUGFUNC("ixgbe_lower_eeprom_clk"); /* * Lower the clock input to the EEPROM (clearing the SK bit), then * delay */ *eec = *eec & ~IXGBE_EEC_SK; IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); IXGBE_WRITE_FLUSH(hw); usec_delay(1); } /** * ixgbe_release_eeprom - Release EEPROM, release semaphores * @hw: pointer to hardware structure **/ static void ixgbe_release_eeprom(struct ixgbe_hw *hw) { u32 eec; DEBUGFUNC("ixgbe_release_eeprom"); eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); eec |= IXGBE_EEC_CS; /* Pull CS high */ eec &= ~IXGBE_EEC_SK; /* Lower SCK */ IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); IXGBE_WRITE_FLUSH(hw); usec_delay(1); /* Stop requesting EEPROM access */ eec &= ~IXGBE_EEC_REQ; IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); /* Delay before attempt to obtain semaphore again to allow FW access */ msec_delay(hw->eeprom.semaphore_delay); } /** * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum * @hw: pointer to hardware structure * * Returns a negative error code on error, or the 16-bit checksum **/ s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) { u16 i; u16 j; u16 checksum = 0; u16 length = 0; u16 pointer = 0; u16 word = 0; DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); /* Include 0x0-0x3F in the checksum */ for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { if (hw->eeprom.ops.read(hw, i, &word)) { DEBUGOUT("EEPROM read failed\n"); return IXGBE_ERR_EEPROM; } checksum += word; } /* Include all data from pointers except for the fw pointer */ for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { if (hw->eeprom.ops.read(hw, i, &pointer)) { DEBUGOUT("EEPROM read failed\n"); return IXGBE_ERR_EEPROM; } /* If the pointer seems invalid */ if (pointer == 0xFFFF || pointer == 0) continue; if (hw->eeprom.ops.read(hw, pointer, &length)) { DEBUGOUT("EEPROM read failed\n"); return IXGBE_ERR_EEPROM; } if (length == 0xFFFF || length == 0) continue; for (j = pointer + 1; j <= pointer + length; j++) { if (hw->eeprom.ops.read(hw, j, &word)) { DEBUGOUT("EEPROM read failed\n"); return IXGBE_ERR_EEPROM; } checksum += word; } } checksum = (u16)IXGBE_EEPROM_SUM - checksum; return (s32)checksum; } /** * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum * @hw: pointer to hardware structure * @checksum_val: calculated checksum * * Performs checksum calculation and validates the EEPROM checksum. If the * caller does not need checksum_val, the value can be NULL. **/ s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, u16 *checksum_val) { s32 status; u16 checksum; u16 read_checksum = 0; DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); /* Read the first word from the EEPROM. If this times out or fails, do * not continue or we could be in for a very long wait while every * EEPROM read fails */ status = hw->eeprom.ops.read(hw, 0, &checksum); if (status) { DEBUGOUT("EEPROM read failed\n"); return status; } status = hw->eeprom.ops.calc_checksum(hw); if (status < 0) return status; checksum = (u16)(status & 0xffff); status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); if (status) { DEBUGOUT("EEPROM read failed\n"); return status; } /* Verify read checksum from EEPROM is the same as * calculated checksum */ if (read_checksum != checksum) status = IXGBE_ERR_EEPROM_CHECKSUM; /* If the user cares, return the calculated checksum */ if (checksum_val) *checksum_val = checksum; return status; } /** * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum * @hw: pointer to hardware structure **/ s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) { s32 status; u16 checksum; DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); /* Read the first word from the EEPROM. If this times out or fails, do * not continue or we could be in for a very long wait while every * EEPROM read fails */ status = hw->eeprom.ops.read(hw, 0, &checksum); if (status) { DEBUGOUT("EEPROM read failed\n"); return status; } status = hw->eeprom.ops.calc_checksum(hw); if (status < 0) return status; checksum = (u16)(status & 0xffff); status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); return status; } /** * ixgbe_validate_mac_addr - Validate MAC address * @mac_addr: pointer to MAC address. * * Tests a MAC address to ensure it is a valid Individual Address. **/ s32 ixgbe_validate_mac_addr(u8 *mac_addr) { s32 status = IXGBE_SUCCESS; DEBUGFUNC("ixgbe_validate_mac_addr"); /* Make sure it is not a multicast address */ if (IXGBE_IS_MULTICAST(mac_addr)) { status = IXGBE_ERR_INVALID_MAC_ADDR; /* Not a broadcast address */ } else if (IXGBE_IS_BROADCAST(mac_addr)) { status = IXGBE_ERR_INVALID_MAC_ADDR; /* Reject the zero address */ } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { status = IXGBE_ERR_INVALID_MAC_ADDR; } return status; } /** * ixgbe_set_rar_generic - Set Rx address register * @hw: pointer to hardware structure * @index: Receive address register to write * @addr: Address to put into receive address register * @vmdq: VMDq "set" or "pool" index * @enable_addr: set flag that address is active * * Puts an ethernet address into a receive address register. **/ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, u32 enable_addr) { u32 rar_low, rar_high; u32 rar_entries = hw->mac.num_rar_entries; DEBUGFUNC("ixgbe_set_rar_generic"); /* Make sure we are using a valid rar index range */ if (index >= rar_entries) { ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, "RAR index %d is out of range.\n", index); return IXGBE_ERR_INVALID_ARGUMENT; } /* setup VMDq pool selection before this RAR gets enabled */ hw->mac.ops.set_vmdq(hw, index, vmdq); /* * HW expects these in little endian so we reverse the byte * order from network order (big endian) to little endian */ rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); /* * Some parts put the VMDq setting in the extra RAH bits, * so save everything except the lower 16 bits that hold part * of the address and the address valid bit. */ rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); if (enable_addr != 0) rar_high |= IXGBE_RAH_AV; IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); return IXGBE_SUCCESS; } /** * ixgbe_clear_rar_generic - Remove Rx address register * @hw: pointer to hardware structure * @index: Receive address register to write * * Clears an ethernet address from a receive address register. **/ s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) { u32 rar_high; u32 rar_entries = hw->mac.num_rar_entries; DEBUGFUNC("ixgbe_clear_rar_generic"); /* Make sure we are using a valid rar index range */ if (index >= rar_entries) { ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, "RAR index %d is out of range.\n", index); return IXGBE_ERR_INVALID_ARGUMENT; } /* * Some parts put the VMDq setting in the extra RAH bits, * so save everything except the lower 16 bits that hold part * of the address and the address valid bit. */ rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); /* clear VMDq pool/queue selection for this RAR */ hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); return IXGBE_SUCCESS; } /** * ixgbe_init_rx_addrs_generic - Initializes receive address filters. * @hw: pointer to hardware structure * * Places the MAC address in receive address register 0 and clears the rest * of the receive address registers. Clears the multicast table. Assumes * the receiver is in reset when the routine is called. **/ s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) { u32 i; u32 rar_entries = hw->mac.num_rar_entries; DEBUGFUNC("ixgbe_init_rx_addrs_generic"); /* * If the current mac address is valid, assume it is a software override * to the permanent address. * Otherwise, use the permanent address from the eeprom. */ if (ixgbe_validate_mac_addr(hw->mac.addr) == IXGBE_ERR_INVALID_MAC_ADDR) { /* Get the MAC address from the RAR0 for later reference */ hw->mac.ops.get_mac_addr(hw, hw->mac.addr); DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", hw->mac.addr[0], hw->mac.addr[1], hw->mac.addr[2]); DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], hw->mac.addr[4], hw->mac.addr[5]); } else { /* Setup the receive address. */ DEBUGOUT("Overriding MAC Address in RAR[0]\n"); DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", hw->mac.addr[0], hw->mac.addr[1], hw->mac.addr[2]); DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], hw->mac.addr[4], hw->mac.addr[5]); hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); } /* clear VMDq pool/queue selection for RAR 0 */ hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); hw->addr_ctrl.overflow_promisc = 0; hw->addr_ctrl.rar_used_count = 1; /* Zero out the other receive addresses. */ DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); for (i = 1; i < rar_entries; i++) { IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); } /* Clear the MTA */ hw->addr_ctrl.mta_in_use = 0; IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); DEBUGOUT(" Clearing MTA\n"); for (i = 0; i < hw->mac.mcft_size; i++) IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); ixgbe_init_uta_tables(hw); return IXGBE_SUCCESS; } /** * ixgbe_add_uc_addr - Adds a secondary unicast address. * @hw: pointer to hardware structure * @addr: new address * @vmdq: VMDq "set" or "pool" index * * Adds it to unused receive address register or goes into promiscuous mode. **/ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) { u32 rar_entries = hw->mac.num_rar_entries; u32 rar; DEBUGFUNC("ixgbe_add_uc_addr"); DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); /* * Place this address in the RAR if there is room, * else put the controller into promiscuous mode */ if (hw->addr_ctrl.rar_used_count < rar_entries) { rar = hw->addr_ctrl.rar_used_count; hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); hw->addr_ctrl.rar_used_count++; } else { hw->addr_ctrl.overflow_promisc++; } DEBUGOUT("ixgbe_add_uc_addr Complete\n"); } /** * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses * @hw: pointer to hardware structure * @addr_list: the list of new addresses * @addr_count: number of addresses * @next: iterator function to walk the address list * * The given list replaces any existing list. Clears the secondary addrs from * receive address registers. Uses unused receive address registers for the * first secondary addresses, and falls back to promiscuous mode as needed. * * Drivers using secondary unicast addresses must set user_set_promisc when * manually putting the device into promiscuous mode. **/ s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, u32 addr_count, ixgbe_mc_addr_itr next) { u8 *addr; u32 i; u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; u32 uc_addr_in_use; u32 fctrl; u32 vmdq; DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); /* * Clear accounting of old secondary address list, * don't count RAR[0] */ uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; hw->addr_ctrl.rar_used_count -= uc_addr_in_use; hw->addr_ctrl.overflow_promisc = 0; /* Zero out the other receive addresses */ DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); for (i = 0; i < uc_addr_in_use; i++) { IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); } /* Add the new addresses */ for (i = 0; i < addr_count; i++) { DEBUGOUT(" Adding the secondary addresses:\n"); addr = next(hw, &addr_list, &vmdq); ixgbe_add_uc_addr(hw, addr, vmdq); } if (hw->addr_ctrl.overflow_promisc) { /* enable promisc if not already in overflow or set by user */ if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { DEBUGOUT(" Entering address overflow promisc mode\n"); fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); fctrl |= IXGBE_FCTRL_UPE; IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); } } else { /* only disable if set by overflow, not by user */ if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { DEBUGOUT(" Leaving address overflow promisc mode\n"); fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); fctrl &= ~IXGBE_FCTRL_UPE; IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); } } DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); return IXGBE_SUCCESS; } /** * ixgbe_mta_vector - Determines bit-vector in multicast table to set * @hw: pointer to hardware structure * @mc_addr: the multicast address * * Extracts the 12 bits, from a multicast address, to determine which * bit-vector to set in the multicast table. The hardware uses 12 bits, from * incoming rx multicast addresses, to determine the bit-vector to check in * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set * by the MO field of the MCSTCTRL. The MO field is set during initialization * to mc_filter_type. **/ static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) { u32 vector = 0; DEBUGFUNC("ixgbe_mta_vector"); switch (hw->mac.mc_filter_type) { case 0: /* use bits [47:36] of the address */ vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); break; case 1: /* use bits [46:35] of the address */ vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); break; case 2: /* use bits [45:34] of the address */ vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); break; case 3: /* use bits [43:32] of the address */ vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); break; default: /* Invalid mc_filter_type */ DEBUGOUT("MC filter type param set incorrectly\n"); ASSERT(0); break; } /* vector can only be 12-bits or boundary will be exceeded */ vector &= 0xFFF; return vector; } /** * ixgbe_set_mta - Set bit-vector in multicast table * @hw: pointer to hardware structure * @mc_addr: Multicast address * * Sets the bit-vector in the multicast table. **/ void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) { u32 vector; u32 vector_bit; u32 vector_reg; DEBUGFUNC("ixgbe_set_mta"); hw->addr_ctrl.mta_in_use++; vector = ixgbe_mta_vector(hw, mc_addr); DEBUGOUT1(" bit-vector = 0x%03X\n", vector); /* * The MTA is a register array of 128 32-bit registers. It is treated * like an array of 4096 bits. We want to set bit * BitArray[vector_value]. So we figure out what register the bit is * in, read it, OR in the new bit, then write back the new value. The * register is determined by the upper 7 bits of the vector value and * the bit within that register are determined by the lower 5 bits of * the value. */ vector_reg = (vector >> 5) & 0x7F; vector_bit = vector & 0x1F; hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); } /** * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses * @hw: pointer to hardware structure * @mc_addr_list: the list of new multicast addresses * @mc_addr_count: number of addresses * @next: iterator function to walk the multicast address list * @clear: flag, when set clears the table beforehand * * When the clear flag is set, the given list replaces any existing list. * Hashes the given addresses into the multicast table. **/ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, u32 mc_addr_count, ixgbe_mc_addr_itr next, bool clear) { u32 i; u32 vmdq; DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); /* * Set the new number of MC addresses that we are being requested to * use. */ hw->addr_ctrl.num_mc_addrs = mc_addr_count; hw->addr_ctrl.mta_in_use = 0; /* Clear mta_shadow */ if (clear) { DEBUGOUT(" Clearing MTA\n"); memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); } /* Update mta_shadow */ for (i = 0; i < mc_addr_count; i++) { DEBUGOUT(" Adding the multicast addresses:\n"); ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); } /* Enable mta */ for (i = 0; i < hw->mac.mcft_size; i++) IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, hw->mac.mta_shadow[i]); if (hw->addr_ctrl.mta_in_use > 0) IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); return IXGBE_SUCCESS; } /** * ixgbe_enable_mc_generic - Enable multicast address in RAR * @hw: pointer to hardware structure * * Enables multicast address in RAR and the use of the multicast hash table. **/ s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) { struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; DEBUGFUNC("ixgbe_enable_mc_generic"); if (a->mta_in_use > 0) IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); return IXGBE_SUCCESS; } /** * ixgbe_disable_mc_generic - Disable multicast address in RAR * @hw: pointer to hardware structure * * Disables multicast address in RAR and the use of the multicast hash table. **/ s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) { struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; DEBUGFUNC("ixgbe_disable_mc_generic"); if (a->mta_in_use > 0) IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); return IXGBE_SUCCESS; } /** * ixgbe_fc_enable_generic - Enable flow control * @hw: pointer to hardware structure * * Enable flow control according to the current settings. **/ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) { s32 ret_val = IXGBE_SUCCESS; u32 mflcn_reg, fccfg_reg; u32 reg; u32 fcrtl, fcrth; int i; DEBUGFUNC("ixgbe_fc_enable_generic"); /* Validate the water mark configuration */ if (!hw->fc.pause_time) { ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; goto out; } /* Low water mark of zero causes XOFF floods */ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && hw->fc.high_water[i]) { if (!hw->fc.low_water[i] || hw->fc.low_water[i] >= hw->fc.high_water[i]) { DEBUGOUT("Invalid water mark configuration\n"); ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; goto out; } } } /* Negotiate the fc mode to use */ hw->mac.ops.fc_autoneg(hw); /* Disable any previous flow control settings */ mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); /* * The possible values of fc.current_mode are: * 0: Flow control is completely disabled * 1: Rx flow control is enabled (we can receive pause frames, * but not send pause frames). * 2: Tx flow control is enabled (we can send pause frames but * we do not support receiving pause frames). * 3: Both Rx and Tx flow control (symmetric) are enabled. * other: Invalid. */ switch (hw->fc.current_mode) { case ixgbe_fc_none: /* * Flow control is disabled by software override or autoneg. * The code below will actually disable it in the HW. */ break; case ixgbe_fc_rx_pause: /* * Rx Flow control is enabled and Tx Flow control is * disabled by software override. Since there really * isn't a way to advertise that we are capable of RX * Pause ONLY, we will advertise that we support both * symmetric and asymmetric Rx PAUSE. Later, we will * disable the adapter's ability to send PAUSE frames. */ mflcn_reg |= IXGBE_MFLCN_RFCE; break; case ixgbe_fc_tx_pause: /* * Tx Flow control is enabled, and Rx Flow control is * disabled by software override. */ fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; break; case ixgbe_fc_full: /* Flow control (both Rx and Tx) is enabled by SW override. */ mflcn_reg |= IXGBE_MFLCN_RFCE; fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; break; default: ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Flow control param set incorrectly\n"); ret_val = IXGBE_ERR_CONFIG; goto out; break; } /* Set 802.3x based flow control settings. */ mflcn_reg |= IXGBE_MFLCN_DPF; IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); /* Set up and enable Rx high/low water mark thresholds, enable XON. */ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && hw->fc.high_water[i]) { fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; } else { IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); /* * In order to prevent Tx hangs when the internal Tx * switch is enabled we must set the high water mark * to the Rx packet buffer size - 24KB. This allows * the Tx switch to function even under heavy Rx * workloads. */ fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; } IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); } /* Configure pause time (2 TCs per register) */ reg = hw->fc.pause_time * 0x00010001; for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); /* Configure flow control refresh threshold value */ IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); out: return ret_val; } /** * ixgbe_negotiate_fc - Negotiate flow control * @hw: pointer to hardware structure * @adv_reg: flow control advertised settings * @lp_reg: link partner's flow control settings * @adv_sym: symmetric pause bit in advertisement * @adv_asm: asymmetric pause bit in advertisement * @lp_sym: symmetric pause bit in link partner advertisement * @lp_asm: asymmetric pause bit in link partner advertisement * * Find the intersection between advertised settings and link partner's * advertised settings **/ s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) { if ((!(adv_reg)) || (!(lp_reg))) { ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, "Local or link partner's advertised flow control " "settings are NULL. Local: %x, link partner: %x\n", adv_reg, lp_reg); return IXGBE_ERR_FC_NOT_NEGOTIATED; } if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { /* * Now we need to check if the user selected Rx ONLY * of pause frames. In this case, we had to advertise * FULL flow control because we could not advertise RX * ONLY. Hence, we must now check to see if we need to * turn OFF the TRANSMISSION of PAUSE frames. */ if (hw->fc.requested_mode == ixgbe_fc_full) { hw->fc.current_mode = ixgbe_fc_full; DEBUGOUT("Flow Control = FULL.\n"); } else { hw->fc.current_mode = ixgbe_fc_rx_pause; DEBUGOUT("Flow Control=RX PAUSE frames only\n"); } } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && (lp_reg & lp_sym) && (lp_reg & lp_asm)) { hw->fc.current_mode = ixgbe_fc_tx_pause; DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { hw->fc.current_mode = ixgbe_fc_rx_pause; DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); } else { hw->fc.current_mode = ixgbe_fc_none; DEBUGOUT("Flow Control = NONE.\n"); } return IXGBE_SUCCESS; } /** * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber * @hw: pointer to hardware structure * * Enable flow control according on 1 gig fiber. **/ static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) { u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; /* * On multispeed fiber at 1g, bail out if * - link is up but AN did not complete, or if * - link is up and AN completed but timed out */ linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); goto out; } pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, IXGBE_PCS1GANA_ASM_PAUSE, IXGBE_PCS1GANA_SYM_PAUSE, IXGBE_PCS1GANA_ASM_PAUSE); out: return ret_val; } /** * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 * @hw: pointer to hardware structure * * Enable flow control according to IEEE clause 37. **/ static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) { u32 links2, anlp1_reg, autoc_reg, links; s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; /* * On backplane, bail out if * - backplane autoneg was not completed, or if * - we are 82599 and link partner is not AN enabled */ links = IXGBE_READ_REG(hw, IXGBE_LINKS); if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { DEBUGOUT("Auto-Negotiation did not complete\n"); goto out; } if (hw->mac.type == ixgbe_mac_82599EB) { links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { DEBUGOUT("Link partner is not AN enabled\n"); goto out; } } /* * Read the 10g AN autoc and LP ability registers and resolve * local flow control settings accordingly */ autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); ret_val = ixgbe_negotiate_fc(hw, autoc_reg, anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); out: return ret_val; } /** * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 * @hw: pointer to hardware structure * * Enable flow control according to IEEE clause 37. **/ static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) { u16 technology_ability_reg = 0; u16 lp_technology_ability_reg = 0; hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &technology_ability_reg); hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &lp_technology_ability_reg); return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, (u32)lp_technology_ability_reg, IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); } /** * ixgbe_fc_autoneg - Configure flow control * @hw: pointer to hardware structure * * Compares our advertised flow control capabilities to those advertised by * our link partner, and determines the proper flow control mode to use. **/ void ixgbe_fc_autoneg(struct ixgbe_hw *hw) { s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; ixgbe_link_speed speed; bool link_up; DEBUGFUNC("ixgbe_fc_autoneg"); /* * AN should have completed when the cable was plugged in. * Look for reasons to bail out. Bail out if: * - FC autoneg is disabled, or if * - link is not up. */ if (hw->fc.disable_fc_autoneg) { /* TODO: This should be just an informative log */ ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Flow control autoneg is disabled"); goto out; } hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); if (!link_up) { ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); goto out; } switch (hw->phy.media_type) { /* Autoneg flow control on fiber adapters */ case ixgbe_media_type_fiber_fixed: case ixgbe_media_type_fiber_qsfp: case ixgbe_media_type_fiber: if (speed == IXGBE_LINK_SPEED_1GB_FULL) ret_val = ixgbe_fc_autoneg_fiber(hw); break; /* Autoneg flow control on backplane adapters */ case ixgbe_media_type_backplane: ret_val = ixgbe_fc_autoneg_backplane(hw); break; /* Autoneg flow control on copper adapters */ case ixgbe_media_type_copper: if (ixgbe_device_supports_autoneg_fc(hw)) ret_val = ixgbe_fc_autoneg_copper(hw); break; default: break; } out: if (ret_val == IXGBE_SUCCESS) { hw->fc.fc_was_autonegged = TRUE; } else { hw->fc.fc_was_autonegged = FALSE; hw->fc.current_mode = hw->fc.requested_mode; } } /* * ixgbe_pcie_timeout_poll - Return number of times to poll for completion * @hw: pointer to hardware structure * * System-wide timeout range is encoded in PCIe Device Control2 register. * * Add 10% to specified maximum and return the number of times to poll for * completion timeout, in units of 100 microsec. Never return less than * 800 = 80 millisec. */ static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) { s16 devctl2; u32 pollcnt; devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; switch (devctl2) { case IXGBE_PCIDEVCTRL2_65_130ms: pollcnt = 1300; /* 130 millisec */ break; case IXGBE_PCIDEVCTRL2_260_520ms: pollcnt = 5200; /* 520 millisec */ break; case IXGBE_PCIDEVCTRL2_1_2s: pollcnt = 20000; /* 2 sec */ break; case IXGBE_PCIDEVCTRL2_4_8s: pollcnt = 80000; /* 8 sec */ break; case IXGBE_PCIDEVCTRL2_17_34s: pollcnt = 34000; /* 34 sec */ break; case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ default: pollcnt = 800; /* 80 millisec minimum */ break; } /* add 10% to spec maximum */ return (pollcnt * 11) / 10; } /** * ixgbe_disable_pcie_master - Disable PCI-express master access * @hw: pointer to hardware structure * * Disables PCI-Express master access and verifies there are no pending * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS * is returned signifying master requests disabled. **/ s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) { s32 status = IXGBE_SUCCESS; u32 i, poll; u16 value; DEBUGFUNC("ixgbe_disable_pcie_master"); /* Always set this bit to ensure any future transactions are blocked */ IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); /* Exit if master requests are blocked */ if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || IXGBE_REMOVED(hw->hw_addr)) goto out; /* Poll for master request bit to clear */ for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { usec_delay(100); if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) goto out; } /* * Two consecutive resets are required via CTRL.RST per datasheet * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine * of this need. The first reset prevents new master requests from * being issued by our device. We then must wait 1usec or more for any * remaining completions from the PCIe bus to trickle in, and then reset * again to clear out any effects they may have had on our device. */ DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; if (hw->mac.type >= ixgbe_mac_X550) goto out; /* * Before proceeding, make sure that the PCIe block does not have * transactions pending. */ poll = ixgbe_pcie_timeout_poll(hw); for (i = 0; i < poll; i++) { usec_delay(100); value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); if (IXGBE_REMOVED(hw->hw_addr)) goto out; if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) goto out; } ERROR_REPORT1(IXGBE_ERROR_POLLING, "PCIe transaction pending bit also did not clear.\n"); status = IXGBE_ERR_MASTER_REQUESTS_PENDING; out: return status; } /** * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore * @hw: pointer to hardware structure * @mask: Mask to specify which semaphore to acquire * * Acquires the SWFW semaphore through the GSSR register for the specified * function (CSR, PHY0, PHY1, EEPROM, Flash) **/ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) { u32 gssr = 0; u32 swmask = mask; u32 fwmask = mask << 5; u32 timeout = 200; u32 i; DEBUGFUNC("ixgbe_acquire_swfw_sync"); for (i = 0; i < timeout; i++) { /* * SW NVM semaphore bit is used for access to all * SW_FW_SYNC bits (not just NVM) */ if (ixgbe_get_eeprom_semaphore(hw)) return IXGBE_ERR_SWFW_SYNC; gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); if (!(gssr & (fwmask | swmask))) { gssr |= swmask; IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); ixgbe_release_eeprom_semaphore(hw); return IXGBE_SUCCESS; } else { /* Resource is currently in use by FW or SW */ ixgbe_release_eeprom_semaphore(hw); msec_delay(5); } } /* If time expired clear the bits holding the lock and retry */ if (gssr & (fwmask | swmask)) ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); msec_delay(5); return IXGBE_ERR_SWFW_SYNC; } /** * ixgbe_release_swfw_sync - Release SWFW semaphore * @hw: pointer to hardware structure * @mask: Mask to specify which semaphore to release * * Releases the SWFW semaphore through the GSSR register for the specified * function (CSR, PHY0, PHY1, EEPROM, Flash) **/ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) { u32 gssr; u32 swmask = mask; DEBUGFUNC("ixgbe_release_swfw_sync"); ixgbe_get_eeprom_semaphore(hw); gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); gssr &= ~swmask; IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); ixgbe_release_eeprom_semaphore(hw); } /** * ixgbe_disable_sec_rx_path_generic - Stops the receive data path * @hw: pointer to hardware structure * * Stops the receive data path and waits for the HW to internally empty * the Rx security block **/ s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) { #define IXGBE_MAX_SECRX_POLL 40 int i; int secrxreg; DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); secrxreg |= IXGBE_SECRXCTRL_RX_DIS; IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) break; else /* Use interrupt-safe sleep just in case */ usec_delay(1000); } /* For informational purposes only */ if (i >= IXGBE_MAX_SECRX_POLL) DEBUGOUT("Rx unit being enabled before security " "path fully disabled. Continuing with init.\n"); return IXGBE_SUCCESS; } /** * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read * @hw: pointer to hardware structure * @locked: bool to indicate whether the SW/FW lock was taken * @reg_val: Value we read from AUTOC * * The default case requires no protection so just to the register read. */ s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) { *locked = FALSE; *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); return IXGBE_SUCCESS; } /** * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write * @hw: pointer to hardware structure * @reg_val: value to write to AUTOC * @locked: bool to indicate whether the SW/FW lock was already taken by * previous read. * * The default case requires no protection so just to the register write. */ s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) { UNREFERENCED_1PARAMETER(locked); IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); return IXGBE_SUCCESS; } /** * ixgbe_enable_sec_rx_path_generic - Enables the receive data path * @hw: pointer to hardware structure * * Enables the receive data path. **/ s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) { u32 secrxreg; DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); IXGBE_WRITE_FLUSH(hw); return IXGBE_SUCCESS; } /** * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit * @hw: pointer to hardware structure * @regval: register value to write to RXCTRL * * Enables the Rx DMA unit **/ s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) { DEBUGFUNC("ixgbe_enable_rx_dma_generic"); if (regval & IXGBE_RXCTRL_RXEN) ixgbe_enable_rx(hw); else ixgbe_disable_rx(hw); return IXGBE_SUCCESS; } /** * ixgbe_blink_led_start_generic - Blink LED based on index. * @hw: pointer to hardware structure * @index: led number to blink **/ s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) { ixgbe_link_speed speed = 0; bool link_up = 0; u32 autoc_reg = 0; u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); s32 ret_val = IXGBE_SUCCESS; bool locked = FALSE; DEBUGFUNC("ixgbe_blink_led_start_generic"); if (index > 3) return IXGBE_ERR_PARAM; /* * Link must be up to auto-blink the LEDs; * Force it if link is down. */ hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); if (!link_up) { ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); if (ret_val != IXGBE_SUCCESS) goto out; autoc_reg |= IXGBE_AUTOC_AN_RESTART; autoc_reg |= IXGBE_AUTOC_FLU; ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); if (ret_val != IXGBE_SUCCESS) goto out; IXGBE_WRITE_FLUSH(hw); msec_delay(10); } led_reg &= ~IXGBE_LED_MODE_MASK(index); led_reg |= IXGBE_LED_BLINK(index); IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); IXGBE_WRITE_FLUSH(hw); out: return ret_val; } /** * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. * @hw: pointer to hardware structure * @index: led number to stop blinking **/ s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) { u32 autoc_reg = 0; u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); s32 ret_val = IXGBE_SUCCESS; bool locked = FALSE; DEBUGFUNC("ixgbe_blink_led_stop_generic"); if (index > 3) return IXGBE_ERR_PARAM; ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); if (ret_val != IXGBE_SUCCESS) goto out; autoc_reg &= ~IXGBE_AUTOC_FLU; autoc_reg |= IXGBE_AUTOC_AN_RESTART; ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); if (ret_val != IXGBE_SUCCESS) goto out; led_reg &= ~IXGBE_LED_MODE_MASK(index); led_reg &= ~IXGBE_LED_BLINK(index); led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); IXGBE_WRITE_FLUSH(hw); out: return ret_val; } /** * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM * @hw: pointer to hardware structure * @san_mac_offset: SAN MAC address offset * * This function will read the EEPROM location for the SAN MAC address * pointer, and returns the value at that location. This is used in both * get and set mac_addr routines. **/ static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, u16 *san_mac_offset) { s32 ret_val; DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); /* * First read the EEPROM pointer to see if the MAC addresses are * available. */ ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); if (ret_val) { ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, "eeprom at offset %d failed", IXGBE_SAN_MAC_ADDR_PTR); } return ret_val; } /** * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM * @hw: pointer to hardware structure * @san_mac_addr: SAN MAC address * * Reads the SAN MAC address from the EEPROM, if it's available. This is * per-port, so set_lan_id() must be called before reading the addresses. * set_lan_id() is called by identify_sfp(), but this cannot be relied * upon for non-SFP connections, so we must call it here. **/ s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) { u16 san_mac_data, san_mac_offset; u8 i; s32 ret_val; DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); /* * First read the EEPROM pointer to see if the MAC addresses are * available. If they're not, no point in calling set_lan_id() here. */ ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) goto san_mac_addr_out; /* make sure we know which port we need to program */ hw->mac.ops.set_lan_id(hw); /* apply the port offset to the address offset */ (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); for (i = 0; i < 3; i++) { ret_val = hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); if (ret_val) { ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, "eeprom read at offset %d failed", san_mac_offset); goto san_mac_addr_out; } san_mac_addr[i * 2] = (u8)(san_mac_data); san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); san_mac_offset++; } return IXGBE_SUCCESS; san_mac_addr_out: /* * No addresses available in this EEPROM. It's not an * error though, so just wipe the local address and return. */ for (i = 0; i < 6; i++) san_mac_addr[i] = 0xFF; return IXGBE_SUCCESS; } /** * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM * @hw: pointer to hardware structure * @san_mac_addr: SAN MAC address * * Write a SAN MAC address to the EEPROM. **/ s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) { s32 ret_val; u16 san_mac_data, san_mac_offset; u8 i; DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); /* Look for SAN mac address pointer. If not defined, return */ ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) return IXGBE_ERR_NO_SAN_ADDR_PTR; /* Make sure we know which port we need to write */ hw->mac.ops.set_lan_id(hw); /* Apply the port offset to the address offset */ (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); for (i = 0; i < 3; i++) { san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); san_mac_data |= (u16)(san_mac_addr[i * 2]); hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); san_mac_offset++; } return IXGBE_SUCCESS; } /** * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count * @hw: pointer to hardware structure * * Read PCIe configuration space, and get the MSI-X vector count from * the capabilities table. **/ u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) { u16 msix_count = 1; u16 max_msix_count; u16 pcie_offset; switch (hw->mac.type) { case ixgbe_mac_82598EB: pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; break; case ixgbe_mac_82599EB: case ixgbe_mac_X540: case ixgbe_mac_X550: case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_a: pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; break; default: return msix_count; } DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); if (IXGBE_REMOVED(hw->hw_addr)) msix_count = 0; msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; /* MSI-X count is zero-based in HW */ msix_count++; if (msix_count > max_msix_count) msix_count = max_msix_count; return msix_count; } /** * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address * @hw: pointer to hardware structure * @addr: Address to put into receive address register * @vmdq: VMDq pool to assign * * Puts an ethernet address into a receive address register, or * finds the rar that it is already in; adds to the pool list **/ s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) { static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; u32 first_empty_rar = NO_EMPTY_RAR_FOUND; u32 rar; u32 rar_low, rar_high; u32 addr_low, addr_high; DEBUGFUNC("ixgbe_insert_mac_addr_generic"); /* swap bytes for HW little endian */ addr_low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); addr_high = addr[4] | (addr[5] << 8); /* * Either find the mac_id in rar or find the first empty space. * rar_highwater points to just after the highest currently used * rar in order to shorten the search. It grows when we add a new * rar to the top. */ for (rar = 0; rar < hw->mac.rar_highwater; rar++) { rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); if (((IXGBE_RAH_AV & rar_high) == 0) && first_empty_rar == NO_EMPTY_RAR_FOUND) { first_empty_rar = rar; } else if ((rar_high & 0xFFFF) == addr_high) { rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); if (rar_low == addr_low) break; /* found it already in the rars */ } } if (rar < hw->mac.rar_highwater) { /* already there so just add to the pool bits */ ixgbe_set_vmdq(hw, rar, vmdq); } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { /* stick it into first empty RAR slot we found */ rar = first_empty_rar; ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); } else if (rar == hw->mac.rar_highwater) { /* add it to the top of the list and inc the highwater mark */ ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); hw->mac.rar_highwater++; } else if (rar >= hw->mac.num_rar_entries) { return IXGBE_ERR_INVALID_MAC_ADDR; } /* * If we found rar[0], make sure the default pool bit (we use pool 0) * remains cleared to be sure default pool packets will get delivered */ if (rar == 0) ixgbe_clear_vmdq(hw, rar, 0); return rar; } /** * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address * @hw: pointer to hardware struct * @rar: receive address register index to disassociate * @vmdq: VMDq pool index to remove from the rar **/ s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) { u32 mpsar_lo, mpsar_hi; u32 rar_entries = hw->mac.num_rar_entries; DEBUGFUNC("ixgbe_clear_vmdq_generic"); /* Make sure we are using a valid rar index range */ if (rar >= rar_entries) { ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, "RAR index %d is out of range.\n", rar); return IXGBE_ERR_INVALID_ARGUMENT; } mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); if (IXGBE_REMOVED(hw->hw_addr)) goto done; if (!mpsar_lo && !mpsar_hi) goto done; if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { if (mpsar_lo) { IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); } if (mpsar_hi) { IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); } } else if (vmdq < 32) { mpsar_lo &= ~(1 << vmdq); IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); } else { mpsar_hi &= ~(1 << (vmdq - 32)); IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); } /* was that the last pool using this rar? */ if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0 && rar != hw->mac.san_mac_rar_index) hw->mac.ops.clear_rar(hw, rar); done: return IXGBE_SUCCESS; } /** * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address * @hw: pointer to hardware struct * @rar: receive address register index to associate with a VMDq index * @vmdq: VMDq pool index **/ s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) { u32 mpsar; u32 rar_entries = hw->mac.num_rar_entries; DEBUGFUNC("ixgbe_set_vmdq_generic"); /* Make sure we are using a valid rar index range */ if (rar >= rar_entries) { ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, "RAR index %d is out of range.\n", rar); return IXGBE_ERR_INVALID_ARGUMENT; } if (vmdq < 32) { mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); mpsar |= 1 << vmdq; IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); } else { mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); mpsar |= 1 << (vmdq - 32); IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); } return IXGBE_SUCCESS; } /** * This function should only be involved in the IOV mode. * In IOV mode, Default pool is next pool after the number of * VFs advertized and not 0. * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] * * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address * @hw: pointer to hardware struct * @vmdq: VMDq pool index **/ s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) { u32 rar = hw->mac.san_mac_rar_index; DEBUGFUNC("ixgbe_set_vmdq_san_mac"); if (vmdq < 32) { IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); } else { IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); } return IXGBE_SUCCESS; } /** * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array * @hw: pointer to hardware structure **/ s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) { int i; DEBUGFUNC("ixgbe_init_uta_tables_generic"); DEBUGOUT(" Clearing UTA\n"); for (i = 0; i < 128; i++) IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); return IXGBE_SUCCESS; } /** * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot * @hw: pointer to hardware structure * @vlan: VLAN id to write to VLAN filter * @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if * vlanid not found * * * return the VLVF index where this VLAN id should be placed * **/ s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) { s32 regindex, first_empty_slot; u32 bits; /* short cut the special case */ if (vlan == 0) return 0; /* if vlvf_bypass is set we don't want to use an empty slot, we * will simply bypass the VLVF if there are no entries present in the * VLVF that contain our VLAN */ first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; /* add VLAN enable bit for comparison */ vlan |= IXGBE_VLVF_VIEN; /* Search for the vlan id in the VLVF entries. Save off the first empty * slot found along the way. * * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 */ for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); if (bits == vlan) return regindex; if (!first_empty_slot && !bits) first_empty_slot = regindex; } /* If we are here then we didn't find the VLAN. Return first empty * slot we found during our search, else error. */ if (!first_empty_slot) ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; } /** * ixgbe_set_vfta_generic - Set VLAN filter table * @hw: pointer to hardware structure * @vlan: VLAN id to write to VLAN filter * @vind: VMDq output index that maps queue to VLAN id in VLVFB * @vlan_on: boolean flag to turn on/off VLAN * @vlvf_bypass: boolean flag indicating updating default pool is okay * * Turn on/off specified VLAN in the VLAN filter table. **/ s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, bool vlvf_bypass) { u32 regidx, vfta_delta, vfta; s32 ret_val; DEBUGFUNC("ixgbe_set_vfta_generic"); if (vlan > 4095 || vind > 63) return IXGBE_ERR_PARAM; /* * this is a 2 part operation - first the VFTA, then the * VLVF and VLVFB if VT Mode is set * We don't write the VFTA until we know the VLVF part succeeded. */ /* Part 1 * The VFTA is a bitstring made up of 128 32-bit registers * that enable the particular VLAN id, much like the MTA: * bits[11-5]: which register * bits[4-0]: which bit in the register */ regidx = vlan / 32; vfta_delta = 1 << (vlan % 32); vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); /* * vfta_delta represents the difference between the current value * of vfta and the value we want in the register. Since the diff * is an XOR mask we can just update the vfta using an XOR */ vfta_delta &= vlan_on ? ~vfta : vfta; vfta ^= vfta_delta; /* Part 2 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF */ ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, vfta, vlvf_bypass); if (ret_val != IXGBE_SUCCESS) { if (vlvf_bypass) goto vfta_update; return ret_val; } vfta_update: /* Update VFTA now that we are ready for traffic */ if (vfta_delta) IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); return IXGBE_SUCCESS; } /** * ixgbe_set_vlvf_generic - Set VLAN Pool Filter * @hw: pointer to hardware structure * @vlan: VLAN id to write to VLAN filter * @vind: VMDq output index that maps queue to VLAN id in VLVFB * @vlan_on: boolean flag to turn on/off VLAN in VLVF * @vfta_delta: pointer to the difference between the current value of VFTA * and the desired value * @vfta: the desired value of the VFTA * @vlvf_bypass: boolean flag indicating updating default pool is okay * * Turn on/off specified bit in VLVF table. **/ s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, u32 *vfta_delta, u32 vfta, bool vlvf_bypass) { u32 bits; s32 vlvf_index; DEBUGFUNC("ixgbe_set_vlvf_generic"); if (vlan > 4095 || vind > 63) return IXGBE_ERR_PARAM; /* If VT Mode is set * Either vlan_on * make sure the vlan is in VLVF * set the vind bit in the matching VLVFB * Or !vlan_on * clear the pool bit and possibly the vind */ if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) return IXGBE_SUCCESS; vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); if (vlvf_index < 0) return vlvf_index; bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); /* set the pool bit */ bits |= 1 << (vind % 32); if (vlan_on) goto vlvf_update; /* clear the pool bit */ bits ^= 1 << (vind % 32); if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { /* Clear VFTA first, then disable VLVF. Otherwise * we run the risk of stray packets leaking into * the PF via the default pool */ if (*vfta_delta) IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); /* disable VLVF and clear remaining bit from pool */ IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); return IXGBE_SUCCESS; } /* If there are still bits set in the VLVFB registers * for the VLAN ID indicated we need to see if the * caller is requesting that we clear the VFTA entry bit. * If the caller has requested that we clear the VFTA * entry bit but there are still pools/VFs using this VLAN * ID entry then ignore the request. We're not worried * about the case where we're turning the VFTA VLAN ID * entry bit on, only when requested to turn it off as * there may be multiple pools and/or VFs using the * VLAN ID entry. In that case we cannot clear the * VFTA bit until all pools/VFs using that VLAN ID have also * been cleared. This will be indicated by "bits" being * zero. */ *vfta_delta = 0; vlvf_update: /* record pool change and enable VLAN ID if not already enabled */ IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); return IXGBE_SUCCESS; } /** * ixgbe_clear_vfta_generic - Clear VLAN filter table * @hw: pointer to hardware structure * * Clears the VLAN filer table, and the VMDq index associated with the filter **/ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) { u32 offset; DEBUGFUNC("ixgbe_clear_vfta_generic"); for (offset = 0; offset < hw->mac.vft_size; offset++) IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); } return IXGBE_SUCCESS; } /** * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix * @hw: pointer to hardware structure * * Contains the logic to identify if we need to verify link for the * crosstalk fix **/ static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) { /* Does FW say we need the fix */ if (!hw->need_crosstalk_fix) return FALSE; /* Only consider SFP+ PHYs i.e. media type fiber */ switch (hw->mac.ops.get_media_type(hw)) { case ixgbe_media_type_fiber: case ixgbe_media_type_fiber_qsfp: break; default: return FALSE; } return TRUE; } /** * ixgbe_check_mac_link_generic - Determine link and speed status * @hw: pointer to hardware structure * @speed: pointer to link speed * @link_up: TRUE when link is up * @link_up_wait_to_complete: bool used to wait for link up or not * * Reads the links register to determine if link is up and the current speed **/ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete) { u32 links_reg, links_orig; u32 i; DEBUGFUNC("ixgbe_check_mac_link_generic"); /* If Crosstalk fix enabled do the sanity check of making sure * the SFP+ cage is full. */ if (ixgbe_need_crosstalk_fix(hw)) { u32 sfp_cage_full; switch (hw->mac.type) { case ixgbe_mac_82599EB: sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & IXGBE_ESDP_SDP2; break; case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_a: sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & IXGBE_ESDP_SDP0; break; default: /* sanity check - No SFP+ devices here */ sfp_cage_full = FALSE; break; } if (!sfp_cage_full) { *link_up = FALSE; *speed = IXGBE_LINK_SPEED_UNKNOWN; return IXGBE_SUCCESS; } } /* clear the old state */ links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); if (links_orig != links_reg) { DEBUGOUT2("LINKS changed from %08X to %08X\n", links_orig, links_reg); } if (link_up_wait_to_complete) { for (i = 0; i < hw->mac.max_link_up_time; i++) { if (links_reg & IXGBE_LINKS_UP) { *link_up = TRUE; break; } else { *link_up = FALSE; } msec_delay(100); links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); } } else { if (links_reg & IXGBE_LINKS_UP) *link_up = TRUE; else *link_up = FALSE; } switch (links_reg & IXGBE_LINKS_SPEED_82599) { case IXGBE_LINKS_SPEED_10G_82599: *speed = IXGBE_LINK_SPEED_10GB_FULL; if (hw->mac.type >= ixgbe_mac_X550) { if (links_reg & IXGBE_LINKS_SPEED_NON_STD) *speed = IXGBE_LINK_SPEED_2_5GB_FULL; } break; case IXGBE_LINKS_SPEED_1G_82599: *speed = IXGBE_LINK_SPEED_1GB_FULL; break; case IXGBE_LINKS_SPEED_100_82599: *speed = IXGBE_LINK_SPEED_100_FULL; if (hw->mac.type == ixgbe_mac_X550) { if (links_reg & IXGBE_LINKS_SPEED_NON_STD) *speed = IXGBE_LINK_SPEED_5GB_FULL; } break; case IXGBE_LINKS_SPEED_10_X550EM_A: *speed = IXGBE_LINK_SPEED_UNKNOWN; if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) *speed = IXGBE_LINK_SPEED_10_FULL; break; default: *speed = IXGBE_LINK_SPEED_UNKNOWN; } return IXGBE_SUCCESS; } /** * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from * the EEPROM * @hw: pointer to hardware structure * @wwnn_prefix: the alternative WWNN prefix * @wwpn_prefix: the alternative WWPN prefix * * This function will read the EEPROM from the alternative SAN MAC address * block to check the support for the alternative WWNN/WWPN prefix support. **/ s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, u16 *wwpn_prefix) { u16 offset, caps; u16 alt_san_mac_blk_offset; DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); /* clear output first */ *wwnn_prefix = 0xFFFF; *wwpn_prefix = 0xFFFF; /* check if alternative SAN MAC is supported */ offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) goto wwn_prefix_err; if ((alt_san_mac_blk_offset == 0) || (alt_san_mac_blk_offset == 0xFFFF)) goto wwn_prefix_out; /* check capability in alternative san mac address block */ offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; if (hw->eeprom.ops.read(hw, offset, &caps)) goto wwn_prefix_err; if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) goto wwn_prefix_out; /* get the corresponding prefix for WWNN/WWPN */ offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, "eeprom read at offset %d failed", offset); } offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) goto wwn_prefix_err; wwn_prefix_out: return IXGBE_SUCCESS; wwn_prefix_err: ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, "eeprom read at offset %d failed", offset); return IXGBE_SUCCESS; } /** * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM * @hw: pointer to hardware structure * @bs: the fcoe boot status * * This function will read the FCOE boot status from the iSCSI FCOE block **/ s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) { u16 offset, caps, flags; s32 status; DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); /* clear output first */ *bs = ixgbe_fcoe_bootstatus_unavailable; /* check if FCOE IBA block is present */ offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; status = hw->eeprom.ops.read(hw, offset, &caps); if (status != IXGBE_SUCCESS) goto out; if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) goto out; /* check if iSCSI FCOE block is populated */ status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); if (status != IXGBE_SUCCESS) goto out; if ((offset == 0) || (offset == 0xFFFF)) goto out; /* read fcoe flags in iSCSI FCOE block */ offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; status = hw->eeprom.ops.read(hw, offset, &flags); if (status != IXGBE_SUCCESS) goto out; if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) *bs = ixgbe_fcoe_bootstatus_enabled; else *bs = ixgbe_fcoe_bootstatus_disabled; out: return status; } /** * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing * @hw: pointer to hardware structure * @enable: enable or disable switch for MAC anti-spoofing * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing * **/ void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) { int vf_target_reg = vf >> 3; int vf_target_shift = vf % 8; u32 pfvfspoof; if (hw->mac.type == ixgbe_mac_82598EB) return; pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); if (enable) pfvfspoof |= (1 << vf_target_shift); else pfvfspoof &= ~(1 << vf_target_shift); IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); } /** * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing * @hw: pointer to hardware structure * @enable: enable or disable switch for VLAN anti-spoofing * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing * **/ void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) { int vf_target_reg = vf >> 3; int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; u32 pfvfspoof; if (hw->mac.type == ixgbe_mac_82598EB) return; pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); if (enable) pfvfspoof |= (1 << vf_target_shift); else pfvfspoof &= ~(1 << vf_target_shift); IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); } /** * ixgbe_get_device_caps_generic - Get additional device capabilities * @hw: pointer to hardware structure * @device_caps: the EEPROM word with the extra device capabilities * * This function will read the EEPROM location for the device capabilities, * and return the word through device_caps. **/ s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) { DEBUGFUNC("ixgbe_get_device_caps_generic"); hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); return IXGBE_SUCCESS; } /** * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering * @hw: pointer to hardware structure * **/ void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) { u32 regval; u32 i; DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); /* Enable relaxed ordering */ for (i = 0; i < hw->mac.max_tx_queues; i++) { regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); } for (i = 0; i < hw->mac.max_rx_queues; i++) { regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | IXGBE_DCA_RXCTRL_HEAD_WRO_EN; IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); } } /** * ixgbe_calculate_checksum - Calculate checksum for buffer * @buffer: pointer to EEPROM * @length: size of EEPROM to calculate a checksum for * Calculates the checksum for some buffer on a specified length. The * checksum calculated is returned. **/ u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) { u32 i; u8 sum = 0; DEBUGFUNC("ixgbe_calculate_checksum"); if (!buffer) return 0; for (i = 0; i < length; i++) sum += buffer[i]; return (u8) (0 - sum); } /** * ixgbe_hic_unlocked - Issue command to manageability block unlocked * @hw: pointer to the HW structure * @buffer: command to write and where the return status will be placed * @length: length of buffer, must be multiple of 4 bytes * @timeout: time in ms to wait for command completion * * Communicates with the manageability block. On success return IXGBE_SUCCESS * else returns semaphore error when encountering an error acquiring * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. * * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held * by the caller. **/ s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, u32 timeout) { u32 hicr, i, fwsts; u16 dword_len; DEBUGFUNC("ixgbe_hic_unlocked"); if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); return IXGBE_ERR_HOST_INTERFACE_COMMAND; } /* Set bit 9 of FWSTS clearing FW reset indication */ fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); /* Check that the host interface is enabled. */ hicr = IXGBE_READ_REG(hw, IXGBE_HICR); if (!(hicr & IXGBE_HICR_EN)) { DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); return IXGBE_ERR_HOST_INTERFACE_COMMAND; } /* Calculate length in DWORDs. We must be DWORD aligned */ if (length % sizeof(u32)) { DEBUGOUT("Buffer length failure, not aligned to dword"); return IXGBE_ERR_INVALID_ARGUMENT; } dword_len = length >> 2; /* The device driver writes the relevant command block * into the ram area. */ for (i = 0; i < dword_len; i++) IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, i, IXGBE_CPU_TO_LE32(buffer[i])); /* Setting this bit tells the ARC that a new command is pending. */ IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); for (i = 0; i < timeout; i++) { hicr = IXGBE_READ_REG(hw, IXGBE_HICR); if (!(hicr & IXGBE_HICR_C)) break; msec_delay(1); } /* For each command except "Apply Update" perform * status checks in the HICR registry. */ if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) == IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD) return IXGBE_SUCCESS; /* Check command completion */ if ((timeout && i == timeout) || !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Command has failed with no status valid.\n"); return IXGBE_ERR_HOST_INTERFACE_COMMAND; } return IXGBE_SUCCESS; } /** * ixgbe_host_interface_command - Issue command to manageability block * @hw: pointer to the HW structure * @buffer: contains the command to write and where the return status will * be placed * @length: length of buffer, must be multiple of 4 bytes * @timeout: time in ms to wait for command completion * @return_data: read and return data from the buffer (TRUE) or not (FALSE) * Needed because FW structures are big endian and decoding of * these fields can be 8 bit or 16 bit based on command. Decoding * is not easily understood without making a table of commands. * So we will leave this up to the caller to read back the data * in these cases. * * Communicates with the manageability block. On success return IXGBE_SUCCESS * else returns semaphore error when encountering an error acquiring * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. **/ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, u32 length, u32 timeout, bool return_data) { u32 hdr_size = sizeof(struct ixgbe_hic_hdr); struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer; u16 buf_len; s32 status; u32 bi; u32 dword_len; DEBUGFUNC("ixgbe_host_interface_command"); if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); return IXGBE_ERR_HOST_INTERFACE_COMMAND; } /* Take management host interface semaphore */ status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); if (status) return status; status = ixgbe_hic_unlocked(hw, buffer, length, timeout); if (status) goto rel_out; if (!return_data) goto rel_out; /* Calculate length in DWORDs */ dword_len = hdr_size >> 2; /* first pull in the header so we know the buffer length */ for (bi = 0; bi < dword_len; bi++) { buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); IXGBE_LE32_TO_CPUS(&buffer[bi]); } /* * If there is any thing in data position pull it in * Read Flash command requires reading buffer length from * two byes instead of one byte */ if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD || resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) { for (; bi < dword_len + 2; bi++) { buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); IXGBE_LE32_TO_CPUS(&buffer[bi]); } buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3) & 0xF00) | resp->buf_len; hdr_size += (2 << 2); } else { buf_len = resp->buf_len; } if (!buf_len) goto rel_out; if (length < buf_len + hdr_size) { DEBUGOUT("Buffer not large enough for reply message.\n"); status = IXGBE_ERR_HOST_INTERFACE_COMMAND; goto rel_out; } /* Calculate length in DWORDs, add 3 for odd lengths */ dword_len = (buf_len + 3) >> 2; /* Pull in the rest of the buffer (bi is where we left off) */ for (; bi <= dword_len; bi++) { buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); IXGBE_LE32_TO_CPUS(&buffer[bi]); } rel_out: hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); return status; } /** * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware * @hw: pointer to the HW structure * @maj: driver version major number * @min: driver version minor number * @build: driver version build number * @sub: driver version sub build number * @len: unused * @driver_ver: unused * * Sends driver version number to firmware through the manageability * block. On success return IXGBE_SUCCESS * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. **/ s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, u8 sub, u16 len, const char *driver_ver) { struct ixgbe_hic_drv_info fw_cmd; int i; s32 ret_val = IXGBE_SUCCESS; DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); UNREFERENCED_2PARAMETER(len, driver_ver); fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; fw_cmd.port_num = (u8)hw->bus.func; fw_cmd.ver_maj = maj; fw_cmd.ver_min = min; fw_cmd.ver_build = build; fw_cmd.ver_sub = sub; fw_cmd.hdr.checksum = 0; fw_cmd.pad = 0; fw_cmd.pad2 = 0; fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, sizeof(fw_cmd), IXGBE_HI_COMMAND_TIMEOUT, TRUE); if (ret_val != IXGBE_SUCCESS) continue; if (fw_cmd.hdr.cmd_or_resp.ret_status == FW_CEM_RESP_STATUS_SUCCESS) ret_val = IXGBE_SUCCESS; else ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; break; } return ret_val; } /** * ixgbe_set_rxpba_generic - Initialize Rx packet buffer * @hw: pointer to hardware structure * @num_pb: number of packet buffers to allocate * @headroom: reserve n KB of headroom * @strategy: packet buffer allocation strategy **/ void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, int strategy) { u32 pbsize = hw->mac.rx_pb_size; int i = 0; u32 rxpktsize, txpktsize, txpbthresh; /* Reserve headroom */ pbsize -= headroom; if (!num_pb) num_pb = 1; /* Divide remaining packet buffer space amongst the number of packet * buffers requested using supplied strategy. */ switch (strategy) { case PBA_STRATEGY_WEIGHTED: /* ixgbe_dcb_pba_80_48 strategy weight first half of packet * buffer with 5/8 of the packet buffer space. */ rxpktsize = (pbsize * 5) / (num_pb * 4); pbsize -= rxpktsize * (num_pb / 2); rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; for (; i < (num_pb / 2); i++) IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); /* configure remaining packet buffers */ /* FALLTHROUGH */ case PBA_STRATEGY_EQUAL: rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; for (; i < num_pb; i++) IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); break; default: break; } /* Only support an equally distributed Tx packet buffer strategy. */ txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; for (i = 0; i < num_pb; i++) { IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); } /* Clear unused TCs, if any, to zero buffer size*/ for (; i < IXGBE_MAX_PB; i++) { IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); } } /** * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo * @hw: pointer to the hardware structure * * The 82599 and x540 MACs can experience issues if TX work is still pending * when a reset occurs. This function prevents this by flushing the PCIe * buffers on the system. **/ void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) { u32 gcr_ext, hlreg0, i, poll; u16 value; /* * If double reset is not requested then all transactions should * already be clear and as such there is no work to do */ if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) return; /* * Set loopback enable to prevent any transmits from being sent * should the link come up. This assumes that the RXCTRL.RXEN bit * has already been cleared. */ hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); /* Wait for a last completion before clearing buffers */ IXGBE_WRITE_FLUSH(hw); msec_delay(3); /* * Before proceeding, make sure that the PCIe block does not have * transactions pending. */ poll = ixgbe_pcie_timeout_poll(hw); for (i = 0; i < poll; i++) { usec_delay(100); value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); if (IXGBE_REMOVED(hw->hw_addr)) goto out; if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) goto out; } out: /* initiate cleaning flow for buffers in the PCIe transaction layer */ gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); /* Flush all writes and allow 20usec for all transactions to clear */ IXGBE_WRITE_FLUSH(hw); usec_delay(20); /* restore previous register values */ IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); } /** * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW * * @hw: pointer to hardware structure * @cmd: Command we send to the FW * @status: The reply from the FW * * Bit-bangs the cmd to the by_pass FW status points to what is returned. **/ #define IXGBE_BYPASS_BB_WAIT 1 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) { int i; u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; u32 esdp; if (!status) return IXGBE_ERR_PARAM; *status = 0; /* SDP vary by MAC type */ switch (hw->mac.type) { case ixgbe_mac_82599EB: sck = IXGBE_ESDP_SDP7; sdi = IXGBE_ESDP_SDP0; sdo = IXGBE_ESDP_SDP6; dir_sck = IXGBE_ESDP_SDP7_DIR; dir_sdi = IXGBE_ESDP_SDP0_DIR; dir_sdo = IXGBE_ESDP_SDP6_DIR; break; case ixgbe_mac_X540: sck = IXGBE_ESDP_SDP2; sdi = IXGBE_ESDP_SDP0; sdo = IXGBE_ESDP_SDP1; dir_sck = IXGBE_ESDP_SDP2_DIR; dir_sdi = IXGBE_ESDP_SDP0_DIR; dir_sdo = IXGBE_ESDP_SDP1_DIR; break; default: return IXGBE_ERR_DEVICE_NOT_SUPPORTED; } /* Set SDP pins direction */ esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); esdp |= dir_sck; /* SCK as output */ esdp |= dir_sdi; /* SDI as output */ esdp &= ~dir_sdo; /* SDO as input */ esdp |= sck; esdp |= sdi; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); msec_delay(IXGBE_BYPASS_BB_WAIT); /* Generate start condition */ esdp &= ~sdi; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); msec_delay(IXGBE_BYPASS_BB_WAIT); esdp &= ~sck; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); msec_delay(IXGBE_BYPASS_BB_WAIT); /* Clock out the new control word and clock in the status */ for (i = 0; i < 32; i++) { if ((cmd >> (31 - i)) & 0x01) { esdp |= sdi; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); } else { esdp &= ~sdi; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); } IXGBE_WRITE_FLUSH(hw); msec_delay(IXGBE_BYPASS_BB_WAIT); esdp |= sck; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); msec_delay(IXGBE_BYPASS_BB_WAIT); esdp &= ~sck; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); msec_delay(IXGBE_BYPASS_BB_WAIT); esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); if (esdp & sdo) *status = (*status << 1) | 0x01; else *status = (*status << 1) | 0x00; msec_delay(IXGBE_BYPASS_BB_WAIT); } /* stop condition */ esdp |= sck; esdp &= ~sdi; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); msec_delay(IXGBE_BYPASS_BB_WAIT); esdp |= sdi; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); /* set the page bits to match the cmd that the status it belongs to */ *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); return IXGBE_SUCCESS; } /** * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. * * If we send a write we can't be sure it took until we can read back * that same register. It can be a problem as some of the feilds may * for valid reasons change inbetween the time wrote the register and * we read it again to verify. So this function check everything we * can check and then assumes it worked. * * @u32 in_reg - The register cmd for the bit-bang read. * @u32 out_reg - The register returned from a bit-bang read. **/ bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) { u32 mask; /* Page must match for all control pages */ if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) return FALSE; switch (in_reg & BYPASS_PAGE_M) { case BYPASS_PAGE_CTL0: /* All the following can't change since the last write * - All the event actions * - The timeout value */ mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | BYPASS_WDTIMEOUT_M | BYPASS_WDT_VALUE_M; if ((out_reg & mask) != (in_reg & mask)) return FALSE; /* 0x0 is never a valid value for bypass status */ if (!(out_reg & BYPASS_STATUS_OFF_M)) return FALSE; break; case BYPASS_PAGE_CTL1: /* All the following can't change since the last write * - time valid bit * - time we last sent */ mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; if ((out_reg & mask) != (in_reg & mask)) return FALSE; break; case BYPASS_PAGE_CTL2: /* All we can check in this page is control number * which is already done above. */ break; } /* We are as sure as we can be return TRUE */ return TRUE; } /** * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter. * * @hw: pointer to hardware structure * @cmd: The control word we are setting. * @event: The event we are setting in the FW. This also happens to * be the mask for the event we are setting (handy) * @action: The action we set the event to in the FW. This is in a * bit field that happens to be what we want to put in * the event spot (also handy) **/ s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, u32 action) { u32 by_ctl = 0; u32 cmd, verify; u32 count = 0; /* Get current values */ cmd = ctrl; /* just reading only need control number */ if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) return IXGBE_ERR_INVALID_ARGUMENT; /* Set to new action */ cmd = (by_ctl & ~event) | BYPASS_WE | action; if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) return IXGBE_ERR_INVALID_ARGUMENT; /* Page 0 force a FW eeprom write which is slow so verify */ if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { verify = BYPASS_PAGE_CTL0; do { if (count++ > 5) return IXGBE_BYPASS_FW_WRITE_FAILURE; if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) return IXGBE_ERR_INVALID_ARGUMENT; } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); } else { /* We have give the FW time for the write to stick */ msec_delay(100); } return IXGBE_SUCCESS; } /** * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres. * * @hw: pointer to hardware structure * @addr: The bypass eeprom address to read. * @value: The 8b of data at the address above. **/ s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) { u32 cmd; u32 status; /* send the request */ cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; if (ixgbe_bypass_rw_generic(hw, cmd, &status)) return IXGBE_ERR_INVALID_ARGUMENT; /* We have give the FW time for the write to stick */ msec_delay(100); /* now read the results */ cmd &= ~BYPASS_WE; if (ixgbe_bypass_rw_generic(hw, cmd, &status)) return IXGBE_ERR_INVALID_ARGUMENT; *value = status & BYPASS_CTL2_DATA_M; return IXGBE_SUCCESS; } /** * ixgbe_get_orom_version - Return option ROM from EEPROM * * @hw: pointer to hardware structure * @nvm_ver: pointer to output structure * * if valid option ROM version, nvm_ver->or_valid set to TRUE * else nvm_ver->or_valid is FALSE. **/ void ixgbe_get_orom_version(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) { u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; nvm_ver->or_valid = FALSE; /* Option Rom may or may not be present. Start with pointer */ hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); /* make sure offset is valid */ if ((offset == 0x0) || (offset == NVM_INVALID_PTR)) return; hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); /* option rom exists and is valid */ if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || eeprom_cfg_blkl == NVM_VER_INVALID || eeprom_cfg_blkh == NVM_VER_INVALID) return; nvm_ver->or_valid = TRUE; nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | (eeprom_cfg_blkh >> NVM_OROM_SHIFT); nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; } /** * ixgbe_get_oem_prod_version - Return OEM Product version * * @hw: pointer to hardware structure * @nvm_ver: pointer to output structure * * if valid OEM product version, nvm_ver->oem_valid set to TRUE * else nvm_ver->oem_valid is FALSE. **/ void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) { u16 rel_num, prod_ver, mod_len, cap, offset; nvm_ver->oem_valid = FALSE; hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); /* Return if offset to OEM Product Version block is invalid */ if (offset == 0x0 || offset == NVM_INVALID_PTR) return; /* Read product version block */ hw->eeprom.ops.read(hw, offset, &mod_len); hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); /* Return if OEM product version block is invalid */ if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) return; hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); /* Return if version is invalid */ if ((rel_num | prod_ver) == 0x0 || rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) return; nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; nvm_ver->oem_release = rel_num; nvm_ver->oem_valid = TRUE; } /** * ixgbe_get_etk_id - Return Etrack ID from EEPROM * * @hw: pointer to hardware structure * @nvm_ver: pointer to output structure * * word read errors will return 0xFFFF **/ void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) { u16 etk_id_l, etk_id_h; if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) etk_id_l = NVM_VER_INVALID; if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) etk_id_h = NVM_VER_INVALID; /* The word order for the version format is determined by high order * word bit 15. */ if ((etk_id_h & NVM_ETK_VALID) == 0) { nvm_ver->etk_id = etk_id_h; nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); } else { nvm_ver->etk_id = etk_id_l; nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); } } /** * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg * @hw: pointer to hardware structure * @map: pointer to u8 arr for returning map * * Read the rtrup2tc HW register and resolve its content into map **/ void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) { u32 reg, i; reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) map[i] = IXGBE_RTRUP2TC_UP_MASK & (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); return; } void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) { u32 pfdtxgswc; u32 rxctrl; rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); if (rxctrl & IXGBE_RXCTRL_RXEN) { if (hw->mac.type != ixgbe_mac_82598EB) { pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); hw->mac.set_lben = TRUE; } else { hw->mac.set_lben = FALSE; } } rxctrl &= ~IXGBE_RXCTRL_RXEN; IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); } } void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) { u32 pfdtxgswc; u32 rxctrl; rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); if (hw->mac.type != ixgbe_mac_82598EB) { if (hw->mac.set_lben) { pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); hw->mac.set_lben = FALSE; } } } /** * ixgbe_mng_present - returns TRUE when management capability is present * @hw: pointer to hardware structure */ bool ixgbe_mng_present(struct ixgbe_hw *hw) { u32 fwsm; if (hw->mac.type < ixgbe_mac_82599EB) return FALSE; fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); } /** * ixgbe_mng_enabled - Is the manageability engine enabled? * @hw: pointer to hardware structure * * Returns TRUE if the manageability engine is enabled. **/ bool ixgbe_mng_enabled(struct ixgbe_hw *hw) { u32 fwsm, manc, factps; fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) return FALSE; manc = IXGBE_READ_REG(hw, IXGBE_MANC); if (!(manc & IXGBE_MANC_RCV_TCO_EN)) return FALSE; if (hw->mac.type <= ixgbe_mac_X540) { factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); if (factps & IXGBE_FACTPS_MNGCG) return FALSE; } return TRUE; } /** * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed * @hw: pointer to hardware structure * @speed: new link speed * @autoneg_wait_to_complete: TRUE when waiting for completion is needed * * Set the link speed in the MAC and/or PHY register and restarts link. **/ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete) { ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; s32 status = IXGBE_SUCCESS; u32 speedcnt = 0; u32 i = 0; bool autoneg, link_up = FALSE; DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); /* Mask off requested but non-supported speeds */ status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); if (status != IXGBE_SUCCESS) return status; speed &= link_speed; /* Try each speed one by one, highest priority first. We do this in * software because 10Gb fiber doesn't support speed autonegotiation. */ if (speed & IXGBE_LINK_SPEED_10GB_FULL) { speedcnt++; highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; /* Set the module link speed */ switch (hw->phy.media_type) { case ixgbe_media_type_fiber_fixed: case ixgbe_media_type_fiber: ixgbe_set_rate_select_speed(hw, IXGBE_LINK_SPEED_10GB_FULL); break; case ixgbe_media_type_fiber_qsfp: /* QSFP module automatically detects MAC link speed */ break; default: DEBUGOUT("Unexpected media type.\n"); break; } /* Allow module to change analog characteristics (1G->10G) */ msec_delay(40); status = ixgbe_setup_mac_link(hw, IXGBE_LINK_SPEED_10GB_FULL, autoneg_wait_to_complete); if (status != IXGBE_SUCCESS) return status; /* Flap the Tx laser if it has not already been done */ ixgbe_flap_tx_laser(hw); /* Wait for the controller to acquire link. Per IEEE 802.3ap, * Section 73.10.2, we may have to wait up to 1000ms if KR is * attempted. 82599 uses the same timing for 10g SFI. */ for (i = 0; i < 10; i++) { /* Wait for the link partner to also set speed */ msec_delay(100); /* If we have link, just jump out */ status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); if (status != IXGBE_SUCCESS) return status; if (link_up) goto out; } } if (speed & IXGBE_LINK_SPEED_1GB_FULL) { speedcnt++; if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; /* Set the module link speed */ switch (hw->phy.media_type) { case ixgbe_media_type_fiber_fixed: case ixgbe_media_type_fiber: ixgbe_set_rate_select_speed(hw, IXGBE_LINK_SPEED_1GB_FULL); break; case ixgbe_media_type_fiber_qsfp: /* QSFP module automatically detects link speed */ break; default: DEBUGOUT("Unexpected media type.\n"); break; } /* Allow module to change analog characteristics (10G->1G) */ msec_delay(40); status = ixgbe_setup_mac_link(hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg_wait_to_complete); if (status != IXGBE_SUCCESS) return status; /* Flap the Tx laser if it has not already been done */ ixgbe_flap_tx_laser(hw); /* Wait for the link partner to also set speed */ msec_delay(100); /* If we have link, just jump out */ status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); if (status != IXGBE_SUCCESS) return status; if (link_up) goto out; } /* We didn't get link. Configure back to the highest speed we tried, * (if there was more than one). We call ourselves back with just the * single highest speed that the user requested. */ if (speedcnt > 1) status = ixgbe_setup_mac_link_multispeed_fiber(hw, highest_link_speed, autoneg_wait_to_complete); out: /* Set autoneg_advertised value based on input link speed */ hw->phy.autoneg_advertised = 0; if (speed & IXGBE_LINK_SPEED_10GB_FULL) hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; if (speed & IXGBE_LINK_SPEED_1GB_FULL) hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; return status; } /** * ixgbe_set_soft_rate_select_speed - Set module link speed * @hw: pointer to hardware structure * @speed: link speed to set * * Set module link speed via the soft rate select. */ void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) { s32 status; u8 rs, eeprom_data; switch (speed) { case IXGBE_LINK_SPEED_10GB_FULL: /* one bit mask same as setting on */ rs = IXGBE_SFF_SOFT_RS_SELECT_10G; break; case IXGBE_LINK_SPEED_1GB_FULL: rs = IXGBE_SFF_SOFT_RS_SELECT_1G; break; default: DEBUGOUT("Invalid fixed module speed\n"); return; } /* Set RS0 */ status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, IXGBE_I2C_EEPROM_DEV_ADDR2, &eeprom_data); if (status) { DEBUGOUT("Failed to read Rx Rate Select RS0\n"); goto out; } eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, IXGBE_I2C_EEPROM_DEV_ADDR2, eeprom_data); if (status) { DEBUGOUT("Failed to write Rx Rate Select RS0\n"); goto out; } /* Set RS1 */ status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, IXGBE_I2C_EEPROM_DEV_ADDR2, &eeprom_data); if (status) { DEBUGOUT("Failed to read Rx Rate Select RS1\n"); goto out; } eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, IXGBE_I2C_EEPROM_DEV_ADDR2, eeprom_data); if (status) { DEBUGOUT("Failed to write Rx Rate Select RS1\n"); goto out; } out: return; } diff --git a/sys/dev/ixgbe/ixgbe_dcb_82598.c b/sys/dev/ixgbe/ixgbe_dcb_82598.c index 0845ba872a1d..37744462bc07 100644 --- a/sys/dev/ixgbe/ixgbe_dcb_82598.c +++ b/sys/dev/ixgbe/ixgbe_dcb_82598.c @@ -1,374 +1,374 @@ /****************************************************************************** SPDX-License-Identifier: BSD-3-Clause Copyright (c) 2001-2017, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ /*$FreeBSD$*/ #include "ixgbe_type.h" #include "ixgbe_dcb.h" #include "ixgbe_dcb_82598.h" /** * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class * @hw: pointer to hardware structure * @stats: pointer to statistics structure * @tc_count: Number of elements in bwg_array. * * This function returns the status data for each of the Traffic Classes in use. */ s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, u8 tc_count) { int tc; DEBUGFUNC("dcb_get_tc_stats"); if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS) return IXGBE_ERR_PARAM; /* Statistics pertaining to each traffic class */ for (tc = 0; tc < tc_count; tc++) { /* Transmitted Packets */ stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc)); /* Transmitted Bytes */ stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc)); /* Received Packets */ stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); /* Received Bytes */ stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc)); #if 0 /* Can we get rid of these?? Consequently, getting rid * of the tc_stats structure. */ tc_stats_array[up]->in_overflow_discards = 0; tc_stats_array[up]->out_overflow_discards = 0; #endif } return IXGBE_SUCCESS; } /** * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data * @hw: pointer to hardware structure * @stats: pointer to statistics structure * @tc_count: Number of elements in bwg_array. * * This function returns the CBFC status data for each of the Traffic Classes. */ s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, u8 tc_count) { int tc; DEBUGFUNC("dcb_get_pfc_stats"); if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS) return IXGBE_ERR_PARAM; for (tc = 0; tc < tc_count; tc++) { /* Priority XOFF Transmitted */ stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc)); /* Priority XOFF Received */ stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc)); } return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter * @hw: pointer to hardware structure * @refill: refill credits index by traffic class * @max: max credits index by traffic class * @tsa: transmission selection algorithm indexed by traffic class * * Configure Rx Data Arbiter and credits for each traffic class. */ s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *tsa) { u32 reg = 0; u32 credit_refill = 0; u32 credit_max = 0; u8 i = 0; reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); reg = IXGBE_READ_REG(hw, IXGBE_RMCS); /* Enable Arbiter */ reg &= ~IXGBE_RMCS_ARBDIS; /* Enable Receive Recycle within the BWG */ reg |= IXGBE_RMCS_RRM; /* Enable Deficit Fixed Priority arbitration*/ reg |= IXGBE_RMCS_DFP; IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); /* Configure traffic class credits and priority */ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { credit_refill = refill[i]; credit_max = max[i]; reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); if (tsa[i] == ixgbe_dcb_tsa_strict) reg |= IXGBE_RT2CR_LSP; IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); } reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); reg |= IXGBE_RDRXCTL_RDMTS_1_2; reg |= IXGBE_RDRXCTL_MPBEN; reg |= IXGBE_RDRXCTL_MCEN; IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); /* Make sure there is enough descriptors before arbitration */ reg &= ~IXGBE_RXCTRL_DMBYPS; IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter * @hw: pointer to hardware structure * @refill: refill credits index by traffic class * @max: max credits index by traffic class * @bwg_id: bandwidth grouping indexed by traffic class * @tsa: transmission selection algorithm indexed by traffic class * * Configure Tx Descriptor Arbiter and credits for each traffic class. */ s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa) { u32 reg, max_credits; u8 i; reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); /* Enable arbiter */ reg &= ~IXGBE_DPMCS_ARBDIS; reg |= IXGBE_DPMCS_TSOEF; /* Configure Max TSO packet size 34KB including payload and headers */ reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); /* Configure traffic class credits and priority */ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { max_credits = max[i]; reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; - reg |= refill[i]; + reg |= (u32)(refill[i]); reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee) reg |= IXGBE_TDTQ2TCCR_GSP; if (tsa[i] == ixgbe_dcb_tsa_strict) reg |= IXGBE_TDTQ2TCCR_LSP; IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); } return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter * @hw: pointer to hardware structure * @refill: refill credits index by traffic class * @max: max credits index by traffic class * @bwg_id: bandwidth grouping indexed by traffic class * @tsa: transmission selection algorithm indexed by traffic class * * Configure Tx Data Arbiter and credits for each traffic class. */ s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa) { u32 reg; u8 i; reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* Enable Data Plane Arbiter */ reg &= ~IXGBE_PDPMCS_ARBDIS; /* Enable DFP and Transmit Recycle Mode */ reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); /* Configure traffic class credits and priority */ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { reg = refill[i]; reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee) reg |= IXGBE_TDPT2TCCR_GSP; if (tsa[i] == ixgbe_dcb_tsa_strict) reg |= IXGBE_TDPT2TCCR_LSP; IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); } /* Enable Tx packet buffer division */ reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); reg |= IXGBE_DTXCTL_ENDBUBD; IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_pfc_82598 - Config priority flow control * @hw: pointer to hardware structure * @pfc_en: enabled pfc bitmask * * Configure Priority Flow Control for each traffic class. */ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) { u32 fcrtl, reg; u8 i; /* Enable Transmit Priority Flow Control */ reg = IXGBE_READ_REG(hw, IXGBE_RMCS); reg &= ~IXGBE_RMCS_TFCE_802_3X; reg |= IXGBE_RMCS_TFCE_PRIORITY; IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); /* Enable Receive Priority Flow Control */ reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); if (pfc_en) reg |= IXGBE_FCTRL_RPFCE; IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); /* Configure PFC Tx thresholds per TC */ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { if (!(pfc_en & (1 << i))) { IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); continue; } fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); } /* Configure pause time */ reg = hw->fc.pause_time | (hw->fc.pause_time << 16); for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); /* Configure flow control refresh threshold value */ IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics * @hw: pointer to hardware structure * * Configure queue statistics registers, all queues belonging to same traffic * class uses a single set of queue statistics counters. */ s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) { u32 reg = 0; u8 i = 0; u8 j = 0; /* Receive Queues stats setting - 8 queues per statistics reg */ for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) { reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); reg |= ((0x1010101) * j); IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); reg |= ((0x1010101) * j); IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); } /* Transmit Queues stats setting - 4 queues per statistics reg*/ for (i = 0; i < 8; i++) { reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); reg |= ((0x1010101) * i); IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); } return IXGBE_SUCCESS; } /** * ixgbe_dcb_hw_config_82598 - Config and enable DCB * @hw: pointer to hardware structure * @link_speed: unused * @refill: refill credits index by traffic class * @max: max credits index by traffic class * @bwg_id: bandwidth grouping indexed by traffic class * @tsa: transmission selection algorithm indexed by traffic class * * Configure dcb settings and enable dcb mode. */ s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa) { UNREFERENCED_1PARAMETER(link_speed); ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa); ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa); ixgbe_dcb_config_tc_stats_82598(hw); return IXGBE_SUCCESS; } diff --git a/sys/dev/ixgbe/ixgbe_dcb_82599.c b/sys/dev/ixgbe/ixgbe_dcb_82599.c index 4799fe1d943a..3056cbf5c2f3 100644 --- a/sys/dev/ixgbe/ixgbe_dcb_82599.c +++ b/sys/dev/ixgbe/ixgbe_dcb_82599.c @@ -1,612 +1,612 @@ /****************************************************************************** SPDX-License-Identifier: BSD-3-Clause Copyright (c) 2001-2017, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ /*$FreeBSD$*/ #include "ixgbe_type.h" #include "ixgbe_dcb.h" #include "ixgbe_dcb_82599.h" /** * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class * @hw: pointer to hardware structure * @stats: pointer to statistics structure * @tc_count: Number of elements in bwg_array. * * This function returns the status data for each of the Traffic Classes in use. */ s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, u8 tc_count) { int tc; DEBUGFUNC("dcb_get_tc_stats"); if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS) return IXGBE_ERR_PARAM; /* Statistics pertaining to each traffic class */ for (tc = 0; tc < tc_count; tc++) { /* Transmitted Packets */ stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc)); /* Transmitted Bytes (read low first to prevent missed carry) */ stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc)); stats->qbtc[tc] += (((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32); /* Received Packets */ stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); /* Received Bytes (read low first to prevent missed carry) */ stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc)); stats->qbrc[tc] += (((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32); /* Received Dropped Packet */ stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc)); } return IXGBE_SUCCESS; } /** * ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data * @hw: pointer to hardware structure * @stats: pointer to statistics structure * @tc_count: Number of elements in bwg_array. * * This function returns the CBFC status data for each of the Traffic Classes. */ s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, u8 tc_count) { int tc; DEBUGFUNC("dcb_get_pfc_stats"); if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS) return IXGBE_ERR_PARAM; for (tc = 0; tc < tc_count; tc++) { /* Priority XOFF Transmitted */ stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc)); /* Priority XOFF Received */ stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc)); } return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter * @hw: pointer to hardware structure * @refill: refill credits index by traffic class * @max: max credits index by traffic class * @bwg_id: bandwidth grouping indexed by traffic class * @tsa: transmission selection algorithm indexed by traffic class * @map: priority to tc assignments indexed by priority * * Configure Rx Packet Arbiter and credits for each traffic class. */ s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa, u8 *map) { u32 reg = 0; u32 credit_refill = 0; u32 credit_max = 0; u8 i = 0; /* * Disable the arbiter before changing parameters * (always enable recycle mode; WSP) */ reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); /* * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding * bits sets for the UPs that needs to be mappped to that TC. * e.g if priorities 6 and 7 are to be mapped to a TC then the * up_to_tc_bitmap value for that TC will be 11000000 in binary. */ reg = 0; for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); /* Configure traffic class credits and priority */ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { credit_refill = refill[i]; credit_max = max[i]; reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; if (tsa[i] == ixgbe_dcb_tsa_strict) reg |= IXGBE_RTRPT4C_LSP; IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); } /* * Configure Rx packet plane (recycle mode; WSP) and * enable arbiter */ reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC; IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter * @hw: pointer to hardware structure * @refill: refill credits index by traffic class * @max: max credits index by traffic class * @bwg_id: bandwidth grouping indexed by traffic class * @tsa: transmission selection algorithm indexed by traffic class * * Configure Tx Descriptor Arbiter and credits for each traffic class. */ s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa) { u32 reg, max_credits; u8 i; /* Clear the per-Tx queue credits; we use per-TC instead */ for (i = 0; i < 128; i++) { IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0); } /* Configure traffic class credits and priority */ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { max_credits = max[i]; reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; - reg |= refill[i]; + reg |= (u32)(refill[i]); reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT; if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee) reg |= IXGBE_RTTDT2C_GSP; if (tsa[i] == ixgbe_dcb_tsa_strict) reg |= IXGBE_RTTDT2C_LSP; IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); } /* * Configure Tx descriptor plane (recycle mode; WSP) and * enable arbiter */ reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM; IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter * @hw: pointer to hardware structure * @refill: refill credits index by traffic class * @max: max credits index by traffic class * @bwg_id: bandwidth grouping indexed by traffic class * @tsa: transmission selection algorithm indexed by traffic class * @map: priority to tc assignments indexed by priority * * Configure Tx Packet Arbiter and credits for each traffic class. */ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa, u8 *map) { u32 reg; u8 i; /* * Disable the arbiter before changing parameters * (always enable recycle mode; SP; arb delay) */ reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) | IXGBE_RTTPCS_ARBDIS; IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); /* * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding * bits sets for the UPs that needs to be mappped to that TC. * e.g if priorities 6 and 7 are to be mapped to a TC then the * up_to_tc_bitmap value for that TC will be 11000000 in binary. */ reg = 0; for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT)); IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); /* Configure traffic class credits and priority */ for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { reg = refill[i]; reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT; reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT; if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee) reg |= IXGBE_RTTPT2C_GSP; if (tsa[i] == ixgbe_dcb_tsa_strict) reg |= IXGBE_RTTPT2C_LSP; IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); } /* * Configure Tx packet plane (recycle mode; SP; arb delay) and * enable arbiter */ reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT); IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_pfc_82599 - Configure priority flow control * @hw: pointer to hardware structure * @pfc_en: enabled pfc bitmask * @map: priority to tc assignments indexed by priority * * Configure Priority Flow Control (PFC) for each traffic class. */ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map) { u32 i, j, fcrtl, reg; u8 max_tc = 0; /* Enable Transmit Priority Flow Control */ IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY); /* Enable Receive Priority Flow Control */ reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); reg |= IXGBE_MFLCN_DPF; /* * X540 supports per TC Rx priority flow control. So * clear all TCs and only enable those that should be * enabled. */ reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); if (hw->mac.type >= ixgbe_mac_X540) reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT; if (pfc_en) reg |= IXGBE_MFLCN_RPFCE; IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) { if (map[i] > max_tc) max_tc = map[i]; } /* Configure PFC Tx thresholds per TC */ for (i = 0; i <= max_tc; i++) { int enabled = 0; for (j = 0; j < IXGBE_DCB_MAX_USER_PRIORITY; j++) { if ((map[j] == i) && (pfc_en & (1 << j))) { enabled = 1; break; } } if (enabled) { reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); } else { /* * In order to prevent Tx hangs when the internal Tx * switch is enabled we must set the high water mark * to the Rx packet buffer size - 24KB. This allows * the Tx switch to function even under heavy Rx * workloads. */ reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); } IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); } for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0); } /* Configure pause time (2 TCs per register) */ reg = hw->fc.pause_time | (hw->fc.pause_time << 16); for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); /* Configure flow control refresh threshold value */ IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics * @hw: pointer to hardware structure * @dcb_config: pointer to ixgbe_dcb_config structure * * Configure queue statistics registers, all queues belonging to same traffic * class uses a single set of queue statistics counters. */ s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) { u32 reg = 0; u8 i = 0; u8 tc_count = 8; bool vt_mode = FALSE; if (dcb_config != NULL) { tc_count = dcb_config->num_tcs.pg_tcs; vt_mode = dcb_config->vt_mode; } if (!((tc_count == 8 && vt_mode == FALSE) || tc_count == 4)) return IXGBE_ERR_PARAM; if (tc_count == 8 && vt_mode == FALSE) { /* * Receive Queues stats setting * 32 RQSMR registers, each configuring 4 queues. * * Set all 16 queues of each TC to the same stat * with TC 'n' going to stat 'n'. */ for (i = 0; i < 32; i++) { reg = 0x01010101 * (i / 4); IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); } /* * Transmit Queues stats setting * 32 TQSM registers, each controlling 4 queues. * * Set all queues of each TC to the same stat * with TC 'n' going to stat 'n'. * Tx queues are allocated non-uniformly to TCs: * 32, 32, 16, 16, 8, 8, 8, 8. */ for (i = 0; i < 32; i++) { if (i < 8) reg = 0x00000000; else if (i < 16) reg = 0x01010101; else if (i < 20) reg = 0x02020202; else if (i < 24) reg = 0x03030303; else if (i < 26) reg = 0x04040404; else if (i < 28) reg = 0x05050505; else if (i < 30) reg = 0x06060606; else reg = 0x07070707; IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); } } else if (tc_count == 4 && vt_mode == FALSE) { /* * Receive Queues stats setting * 32 RQSMR registers, each configuring 4 queues. * * Set all 16 queues of each TC to the same stat * with TC 'n' going to stat 'n'. */ for (i = 0; i < 32; i++) { if (i % 8 > 3) /* In 4 TC mode, odd 16-queue ranges are * not used. */ continue; reg = 0x01010101 * (i / 8); IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); } /* * Transmit Queues stats setting * 32 TQSM registers, each controlling 4 queues. * * Set all queues of each TC to the same stat * with TC 'n' going to stat 'n'. * Tx queues are allocated non-uniformly to TCs: * 64, 32, 16, 16. */ for (i = 0; i < 32; i++) { if (i < 16) reg = 0x00000000; else if (i < 24) reg = 0x01010101; else if (i < 28) reg = 0x02020202; else reg = 0x03030303; IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); } } else if (tc_count == 4 && vt_mode == TRUE) { /* * Receive Queues stats setting * 32 RQSMR registers, each configuring 4 queues. * * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each * pool. Set all 32 queues of each TC across pools to the same * stat with TC 'n' going to stat 'n'. */ for (i = 0; i < 32; i++) IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0x03020100); /* * Transmit Queues stats setting * 32 TQSM registers, each controlling 4 queues. * * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each * pool. Set all 32 queues of each TC across pools to the same * stat with TC 'n' going to stat 'n'. */ for (i = 0; i < 32; i++) IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0x03020100); } return IXGBE_SUCCESS; } /** * ixgbe_dcb_config_82599 - Configure general DCB parameters * @hw: pointer to hardware structure * @dcb_config: pointer to ixgbe_dcb_config structure * * Configure general DCB parameters. */ s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) { u32 reg; u32 q; /* Disable the Tx desc arbiter so that MTQC can be changed */ reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS); reg |= IXGBE_RTTDCS_ARBDIS; IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); reg = IXGBE_READ_REG(hw, IXGBE_MRQC); if (dcb_config->num_tcs.pg_tcs == 8) { /* Enable DCB for Rx with 8 TCs */ switch (reg & IXGBE_MRQC_MRQE_MASK) { case 0: case IXGBE_MRQC_RT4TCEN: /* RSS disabled cases */ reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN; break; case IXGBE_MRQC_RSSEN: case IXGBE_MRQC_RTRSS4TCEN: /* RSS enabled cases */ reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RTRSS8TCEN; break; default: /* * Unsupported value, assume stale data, * overwrite no RSS */ ASSERT(0); reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN; } } if (dcb_config->num_tcs.pg_tcs == 4) { /* We support both VT-on and VT-off with 4 TCs. */ if (dcb_config->vt_mode) reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_VMDQRT4TCEN; else reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RTRSS4TCEN; } IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg); /* Enable DCB for Tx with 8 TCs */ if (dcb_config->num_tcs.pg_tcs == 8) reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; else { /* We support both VT-on and VT-off with 4 TCs. */ reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; if (dcb_config->vt_mode) reg |= IXGBE_MTQC_VT_ENA; } IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg); /* Disable drop for all queues */ for (q = 0; q < 128; q++) IXGBE_WRITE_REG(hw, IXGBE_QDE, (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT))); /* Enable the Tx desc arbiter */ reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS); reg &= ~IXGBE_RTTDCS_ARBDIS; IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); /* Enable Security TX Buffer IFG for DCB */ reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); reg |= IXGBE_SECTX_DCB; IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); return IXGBE_SUCCESS; } /** * ixgbe_dcb_hw_config_82599 - Configure and enable DCB * @hw: pointer to hardware structure * @link_speed: unused * @refill: refill credits index by traffic class * @max: max credits index by traffic class * @bwg_id: bandwidth grouping indexed by traffic class * @tsa: transmission selection algorithm indexed by traffic class * @map: priority to tc assignments indexed by priority * * Configure dcb settings and enable dcb mode. */ s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa, u8 *map) { UNREFERENCED_1PARAMETER(link_speed); ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa, map); ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa); ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map); return IXGBE_SUCCESS; } diff --git a/sys/dev/ixgbe/ixgbe_x550.c b/sys/dev/ixgbe/ixgbe_x550.c index a7759117f5b5..6edeeb178289 100644 --- a/sys/dev/ixgbe/ixgbe_x550.c +++ b/sys/dev/ixgbe/ixgbe_x550.c @@ -1,4678 +1,4678 @@ /****************************************************************************** Copyright (c) 2001-2017, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ /*$FreeBSD$*/ #include "ixgbe_x550.h" #include "ixgbe_x540.h" #include "ixgbe_type.h" #include "ixgbe_api.h" #include "ixgbe_common.h" #include "ixgbe_phy.h" static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed); static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask); static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask); static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw); /** * ixgbe_init_ops_X550 - Inits func ptrs and MAC type * @hw: pointer to hardware structure * * Initialize the function pointers and assign the MAC type for X550. * Does not touch the hardware. **/ s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw) { struct ixgbe_mac_info *mac = &hw->mac; struct ixgbe_eeprom_info *eeprom = &hw->eeprom; s32 ret_val; DEBUGFUNC("ixgbe_init_ops_X550"); ret_val = ixgbe_init_ops_X540(hw); mac->ops.dmac_config = ixgbe_dmac_config_X550; mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; mac->ops.setup_eee = NULL; mac->ops.set_source_address_pruning = ixgbe_set_source_address_pruning_X550; mac->ops.set_ethertype_anti_spoofing = ixgbe_set_ethertype_anti_spoofing_X550; mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; eeprom->ops.init_params = ixgbe_init_eeprom_params_X550; eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; eeprom->ops.read = ixgbe_read_ee_hostif_X550; eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; eeprom->ops.write = ixgbe_write_ee_hostif_X550; eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; mac->ops.disable_mdd = ixgbe_disable_mdd_X550; mac->ops.enable_mdd = ixgbe_enable_mdd_X550; mac->ops.mdd_event = ixgbe_mdd_event_X550; mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550; mac->ops.disable_rx = ixgbe_disable_rx_x550; /* Manageability interface */ mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550; switch (hw->device_id) { case IXGBE_DEV_ID_X550EM_X_1G_T: hw->mac.ops.led_on = NULL; hw->mac.ops.led_off = NULL; break; case IXGBE_DEV_ID_X550EM_X_10G_T: case IXGBE_DEV_ID_X550EM_A_10G_T: hw->mac.ops.led_on = ixgbe_led_on_t_X550em; hw->mac.ops.led_off = ixgbe_led_off_t_X550em; break; default: break; } return ret_val; } /** * ixgbe_read_cs4227 - Read CS4227 register * @hw: pointer to hardware structure * @reg: register number to write * @value: pointer to receive value read * * Returns status code **/ static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) { return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); } /** * ixgbe_write_cs4227 - Write CS4227 register * @hw: pointer to hardware structure * @reg: register number to write * @value: value to write to register * * Returns status code **/ static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) { return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); } /** * ixgbe_read_pe - Read register from port expander * @hw: pointer to hardware structure * @reg: register number to read * @value: pointer to receive read value * * Returns status code **/ static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) { s32 status; status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); if (status != IXGBE_SUCCESS) ERROR_REPORT2(IXGBE_ERROR_CAUTION, "port expander access failed with %d\n", status); return status; } /** * ixgbe_write_pe - Write register to port expander * @hw: pointer to hardware structure * @reg: register number to write * @value: value to write * * Returns status code **/ static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) { s32 status; status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); if (status != IXGBE_SUCCESS) ERROR_REPORT2(IXGBE_ERROR_CAUTION, "port expander access failed with %d\n", status); return status; } /** * ixgbe_reset_cs4227 - Reset CS4227 using port expander * @hw: pointer to hardware structure * * This function assumes that the caller has acquired the proper semaphore. * Returns error code **/ static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) { s32 status; u32 retry; u16 value; u8 reg; /* Trigger hard reset. */ status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); if (status != IXGBE_SUCCESS) return status; reg |= IXGBE_PE_BIT1; status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); if (status != IXGBE_SUCCESS) return status; status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); if (status != IXGBE_SUCCESS) return status; reg &= ~IXGBE_PE_BIT1; status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); if (status != IXGBE_SUCCESS) return status; status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); if (status != IXGBE_SUCCESS) return status; reg &= ~IXGBE_PE_BIT1; status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); if (status != IXGBE_SUCCESS) return status; usec_delay(IXGBE_CS4227_RESET_HOLD); status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); if (status != IXGBE_SUCCESS) return status; reg |= IXGBE_PE_BIT1; status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); if (status != IXGBE_SUCCESS) return status; /* Wait for the reset to complete. */ msec_delay(IXGBE_CS4227_RESET_DELAY); for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, &value); if (status == IXGBE_SUCCESS && value == IXGBE_CS4227_EEPROM_LOAD_OK) break; msec_delay(IXGBE_CS4227_CHECK_DELAY); } if (retry == IXGBE_CS4227_RETRIES) { ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, "CS4227 reset did not complete."); return IXGBE_ERR_PHY; } status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); if (status != IXGBE_SUCCESS || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, "CS4227 EEPROM did not load successfully."); return IXGBE_ERR_PHY; } return IXGBE_SUCCESS; } /** * ixgbe_check_cs4227 - Check CS4227 and reset as needed * @hw: pointer to hardware structure **/ static void ixgbe_check_cs4227(struct ixgbe_hw *hw) { s32 status = IXGBE_SUCCESS; u32 swfw_mask = hw->phy.phy_semaphore_mask; u16 value = 0; u8 retry; for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); if (status != IXGBE_SUCCESS) { ERROR_REPORT2(IXGBE_ERROR_CAUTION, "semaphore failed with %d", status); msec_delay(IXGBE_CS4227_CHECK_DELAY); continue; } /* Get status of reset flow. */ status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); if (status == IXGBE_SUCCESS && value == IXGBE_CS4227_RESET_COMPLETE) goto out; if (status != IXGBE_SUCCESS || value != IXGBE_CS4227_RESET_PENDING) break; /* Reset is pending. Wait and check again. */ hw->mac.ops.release_swfw_sync(hw, swfw_mask); msec_delay(IXGBE_CS4227_CHECK_DELAY); } /* If still pending, assume other instance failed. */ if (retry == IXGBE_CS4227_RETRIES) { status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); if (status != IXGBE_SUCCESS) { ERROR_REPORT2(IXGBE_ERROR_CAUTION, "semaphore failed with %d", status); return; } } /* Reset the CS4227. */ status = ixgbe_reset_cs4227(hw); if (status != IXGBE_SUCCESS) { ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, "CS4227 reset failed: %d", status); goto out; } /* Reset takes so long, temporarily release semaphore in case the * other driver instance is waiting for the reset indication. */ ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, IXGBE_CS4227_RESET_PENDING); hw->mac.ops.release_swfw_sync(hw, swfw_mask); msec_delay(10); status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); if (status != IXGBE_SUCCESS) { ERROR_REPORT2(IXGBE_ERROR_CAUTION, "semaphore failed with %d", status); return; } /* Record completion for next time. */ status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, IXGBE_CS4227_RESET_COMPLETE); out: hw->mac.ops.release_swfw_sync(hw, swfw_mask); msec_delay(hw->eeprom.semaphore_delay); } /** * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control * @hw: pointer to hardware structure **/ static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) { u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); if (hw->bus.lan_id) { esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); esdp |= IXGBE_ESDP_SDP1_DIR; } esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); } /** * ixgbe_identify_phy_x550em - Get PHY type based on device id * @hw: pointer to hardware structure * * Returns error code */ static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) { hw->mac.ops.set_lan_id(hw); ixgbe_read_mng_if_sel_x550em(hw); switch (hw->device_id) { case IXGBE_DEV_ID_X550EM_A_SFP: return ixgbe_identify_module_generic(hw); case IXGBE_DEV_ID_X550EM_X_SFP: /* set up for CS4227 usage */ ixgbe_setup_mux_ctl(hw); ixgbe_check_cs4227(hw); /* Fallthrough */ case IXGBE_DEV_ID_X550EM_A_SFP_N: return ixgbe_identify_module_generic(hw); break; case IXGBE_DEV_ID_X550EM_X_KX4: hw->phy.type = ixgbe_phy_x550em_kx4; break; case IXGBE_DEV_ID_X550EM_X_XFI: hw->phy.type = ixgbe_phy_x550em_xfi; break; case IXGBE_DEV_ID_X550EM_X_KR: case IXGBE_DEV_ID_X550EM_A_KR: case IXGBE_DEV_ID_X550EM_A_KR_L: hw->phy.type = ixgbe_phy_x550em_kr; break; case IXGBE_DEV_ID_X550EM_A_10G_T: case IXGBE_DEV_ID_X550EM_X_10G_T: return ixgbe_identify_phy_generic(hw); case IXGBE_DEV_ID_X550EM_X_1G_T: hw->phy.type = ixgbe_phy_ext_1g_t; break; case IXGBE_DEV_ID_X550EM_A_1G_T: case IXGBE_DEV_ID_X550EM_A_1G_T_L: hw->phy.type = ixgbe_phy_fw; if (hw->bus.lan_id) hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; else hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; break; default: break; } return IXGBE_SUCCESS; } /** * ixgbe_fw_phy_activity - Perform an activity on a PHY * @hw: pointer to hardware structure * @activity: activity to perform * @data: Pointer to 4 32-bit words of data */ s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, u32 (*data)[FW_PHY_ACT_DATA_COUNT]) { union { struct ixgbe_hic_phy_activity_req cmd; struct ixgbe_hic_phy_activity_resp rsp; } hic; u16 retries = FW_PHY_ACT_RETRIES; s32 rc; u16 i; do { memset(&hic, 0, sizeof(hic)); hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; hic.cmd.port_number = hw->bus.lan_id; hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity); for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]); rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd, sizeof(hic.cmd), IXGBE_HI_COMMAND_TIMEOUT, TRUE); if (rc != IXGBE_SUCCESS) return rc; if (hic.rsp.hdr.cmd_or_resp.ret_status == FW_CEM_RESP_STATUS_SUCCESS) { for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]); return IXGBE_SUCCESS; } usec_delay(20); --retries; } while (retries > 0); return IXGBE_ERR_HOST_INTERFACE_COMMAND; } static const struct { u16 fw_speed; ixgbe_link_speed phy_speed; } ixgbe_fw_map[] = { { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, }; /** * ixgbe_get_phy_id_fw - Get the phy ID via firmware command * @hw: pointer to hardware structure * * Returns error code */ static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) { u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; u16 phy_speeds; u16 phy_id_lo; s32 rc; u16 i; rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); if (rc) return rc; hw->phy.speeds_supported = 0; phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) { if (phy_speeds & ixgbe_fw_map[i].fw_speed) hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; } if (!hw->phy.autoneg_advertised) hw->phy.autoneg_advertised = hw->phy.speeds_supported; hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) return IXGBE_ERR_PHY_ADDR_INVALID; return IXGBE_SUCCESS; } /** * ixgbe_identify_phy_fw - Get PHY type based on firmware command * @hw: pointer to hardware structure * * Returns error code */ static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) { if (hw->bus.lan_id) hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; else hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; hw->phy.type = ixgbe_phy_fw; hw->phy.ops.read_reg = NULL; hw->phy.ops.write_reg = NULL; return ixgbe_get_phy_id_fw(hw); } /** * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY * @hw: pointer to hardware structure * * Returns error code */ s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) { u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); } static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data) { UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); return IXGBE_NOT_IMPLEMENTED; } static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data) { UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); return IXGBE_NOT_IMPLEMENTED; } /** * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation * @hw: pointer to the hardware structure * @addr: I2C bus address to read from * @reg: I2C device register to read from * @val: pointer to location to receive read value * * Returns an error code on error. **/ static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) { return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); } /** * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation * @hw: pointer to the hardware structure * @addr: I2C bus address to read from * @reg: I2C device register to read from * @val: pointer to location to receive read value * * Returns an error code on error. **/ static s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) { return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); } /** * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation * @hw: pointer to the hardware structure * @addr: I2C bus address to write to * @reg: I2C device register to write to * @val: value to write * * Returns an error code on error. **/ static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) { return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); } /** * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation * @hw: pointer to the hardware structure * @addr: I2C bus address to write to * @reg: I2C device register to write to * @val: value to write * * Returns an error code on error. **/ static s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) { return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); } /** * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type * @hw: pointer to hardware structure * * Initialize the function pointers and for MAC type X550EM. * Does not touch the hardware. **/ s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) { struct ixgbe_mac_info *mac = &hw->mac; struct ixgbe_eeprom_info *eeprom = &hw->eeprom; struct ixgbe_phy_info *phy = &hw->phy; s32 ret_val; DEBUGFUNC("ixgbe_init_ops_X550EM"); /* Similar to X550 so start there. */ ret_val = ixgbe_init_ops_X550(hw); /* Since this function eventually calls * ixgbe_init_ops_540 by design, we are setting * the pointers to NULL explicitly here to overwrite * the values being set in the x540 function. */ /* Bypass not supported in x550EM */ mac->ops.bypass_rw = NULL; mac->ops.bypass_valid_rd = NULL; mac->ops.bypass_set = NULL; mac->ops.bypass_rd_eep = NULL; /* FCOE not supported in x550EM */ mac->ops.get_san_mac_addr = NULL; mac->ops.set_san_mac_addr = NULL; mac->ops.get_wwn_prefix = NULL; mac->ops.get_fcoe_boot_status = NULL; /* IPsec not supported in x550EM */ mac->ops.disable_sec_rx_path = NULL; mac->ops.enable_sec_rx_path = NULL; /* AUTOC register is not present in x550EM. */ mac->ops.prot_autoc_read = NULL; mac->ops.prot_autoc_write = NULL; /* X550EM bus type is internal*/ hw->bus.type = ixgbe_bus_type_internal; mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; mac->ops.get_media_type = ixgbe_get_media_type_X550em; mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; mac->ops.reset_hw = ixgbe_reset_hw_X550em; mac->ops.get_supported_physical_layer = ixgbe_get_supported_physical_layer_X550em; if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) mac->ops.setup_fc = ixgbe_setup_fc_generic; else mac->ops.setup_fc = ixgbe_setup_fc_X550em; /* PHY */ phy->ops.init = ixgbe_init_phy_ops_X550em; switch (hw->device_id) { case IXGBE_DEV_ID_X550EM_A_1G_T: case IXGBE_DEV_ID_X550EM_A_1G_T_L: mac->ops.setup_fc = NULL; phy->ops.identify = ixgbe_identify_phy_fw; phy->ops.set_phy_power = NULL; phy->ops.get_firmware_version = NULL; break; case IXGBE_DEV_ID_X550EM_X_1G_T: mac->ops.setup_fc = NULL; phy->ops.identify = ixgbe_identify_phy_x550em; phy->ops.set_phy_power = NULL; break; default: phy->ops.identify = ixgbe_identify_phy_x550em; } if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) phy->ops.set_phy_power = NULL; /* EEPROM */ eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; eeprom->ops.read = ixgbe_read_ee_hostif_X550; eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; eeprom->ops.write = ixgbe_write_ee_hostif_X550; eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; return ret_val; } /** * ixgbe_setup_fw_link - Setup firmware-controlled PHYs * @hw: pointer to hardware structure */ static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) { u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; s32 rc; u16 i; if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) return 0; if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); return IXGBE_ERR_INVALID_LINK_SETTINGS; } switch (hw->fc.requested_mode) { case ixgbe_fc_full: setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; break; case ixgbe_fc_rx_pause: setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; break; case ixgbe_fc_tx_pause: setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; break; default: break; } for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) { if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) - setup[0] |= ixgbe_fw_map[i].fw_speed; + setup[0] |= (u32)(ixgbe_fw_map[i].fw_speed); } setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; if (hw->phy.eee_speeds_advertised) setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); if (rc) return rc; if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) return IXGBE_ERR_OVERTEMP; return IXGBE_SUCCESS; } /** * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs * @hw: pointer to hardware structure * * Called at init time to set up flow control. */ static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) { if (hw->fc.requested_mode == ixgbe_fc_default) hw->fc.requested_mode = ixgbe_fc_full; return ixgbe_setup_fw_link(hw); } /** * ixgbe_setup_eee_fw - Enable/disable EEE support * @hw: pointer to the HW structure * @enable_eee: boolean flag to enable EEE * * Enable/disable EEE based on enable_eee flag. * This function controls EEE for firmware-based PHY implementations. */ static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee) { if (!!hw->phy.eee_speeds_advertised == enable_eee) return IXGBE_SUCCESS; if (enable_eee) hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; else hw->phy.eee_speeds_advertised = 0; return hw->phy.ops.setup_link(hw); } /** * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type * @hw: pointer to hardware structure * * Initialize the function pointers and for MAC type X550EM_a. * Does not touch the hardware. **/ s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw) { struct ixgbe_mac_info *mac = &hw->mac; s32 ret_val; DEBUGFUNC("ixgbe_init_ops_X550EM_a"); /* Start with generic X550EM init */ ret_val = ixgbe_init_ops_X550EM(hw); if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) { mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; } else { mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a; mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a; } mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a; mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a; switch (mac->ops.get_media_type(hw)) { case ixgbe_media_type_fiber: mac->ops.setup_fc = NULL; mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; break; case ixgbe_media_type_backplane: mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; break; default: break; } switch (hw->device_id) { case IXGBE_DEV_ID_X550EM_A_1G_T: case IXGBE_DEV_ID_X550EM_A_1G_T_L: mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; mac->ops.setup_fc = ixgbe_fc_autoneg_fw; mac->ops.setup_eee = ixgbe_setup_eee_fw; hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | IXGBE_LINK_SPEED_1GB_FULL; hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; break; default: break; } return ret_val; } /** * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type * @hw: pointer to hardware structure * * Initialize the function pointers and for MAC type X550EM_x. * Does not touch the hardware. **/ s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw) { struct ixgbe_mac_info *mac = &hw->mac; struct ixgbe_link_info *link = &hw->link; s32 ret_val; DEBUGFUNC("ixgbe_init_ops_X550EM_x"); /* Start with generic X550EM init */ ret_val = ixgbe_init_ops_X550EM(hw); mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; link->ops.read_link = ixgbe_read_i2c_combined_generic; link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked; link->ops.write_link = ixgbe_write_i2c_combined_generic; link->ops.write_link_unlocked = ixgbe_write_i2c_combined_generic_unlocked; link->addr = IXGBE_CS4227; if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) { mac->ops.setup_fc = NULL; mac->ops.setup_eee = NULL; mac->ops.init_led_link_act = NULL; } return ret_val; } /** * ixgbe_dmac_config_X550 * @hw: pointer to hardware structure * * Configure DMA coalescing. If enabling dmac, dmac is activated. * When disabling dmac, dmac enable dmac bit is cleared. **/ s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw) { u32 reg, high_pri_tc; DEBUGFUNC("ixgbe_dmac_config_X550"); /* Disable DMA coalescing before configuring */ reg = IXGBE_READ_REG(hw, IXGBE_DMACR); reg &= ~IXGBE_DMACR_DMAC_EN; IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); /* Disable DMA Coalescing if the watchdog timer is 0 */ if (!hw->mac.dmac_config.watchdog_timer) goto out; ixgbe_dmac_config_tcs_X550(hw); /* Configure DMA Coalescing Control Register */ reg = IXGBE_READ_REG(hw, IXGBE_DMACR); /* Set the watchdog timer in units of 40.96 usec */ reg &= ~IXGBE_DMACR_DMACWT_MASK; reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096; reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK; /* If fcoe is enabled, set high priority traffic class */ if (hw->mac.dmac_config.fcoe_en) { high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc; reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) & IXGBE_DMACR_HIGH_PRI_TC_MASK); } reg |= IXGBE_DMACR_EN_MNG_IND; /* Enable DMA coalescing after configuration */ reg |= IXGBE_DMACR_DMAC_EN; IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); out: return IXGBE_SUCCESS; } /** * ixgbe_dmac_config_tcs_X550 * @hw: pointer to hardware structure * * Configure DMA coalescing threshold per TC. The dmac enable bit must * be cleared before configuring. **/ s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw) { u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; DEBUGFUNC("ixgbe_dmac_config_tcs_X550"); /* Configure DMA coalescing enabled */ switch (hw->mac.dmac_config.link_speed) { case IXGBE_LINK_SPEED_10_FULL: case IXGBE_LINK_SPEED_100_FULL: pb_headroom = IXGBE_DMACRXT_100M; break; case IXGBE_LINK_SPEED_1GB_FULL: pb_headroom = IXGBE_DMACRXT_1G; break; default: pb_headroom = IXGBE_DMACRXT_10G; break; } maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >> IXGBE_MHADD_MFS_SHIFT) / 1024); /* Set the per Rx packet buffer receive threshold */ for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) { reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc)); reg &= ~IXGBE_DMCTH_DMACRXT_MASK; if (tc < hw->mac.dmac_config.num_tcs) { /* Get Rx PB size */ rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc)); rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >> IXGBE_RXPBSIZE_SHIFT; /* Calculate receive buffer threshold in kilobytes */ if (rx_pb_size > pb_headroom) rx_pb_size = rx_pb_size - pb_headroom; else rx_pb_size = 0; /* Minimum of MFS shall be set for DMCTH */ reg |= (rx_pb_size > maxframe_size_kb) ? rx_pb_size : maxframe_size_kb; } IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); } return IXGBE_SUCCESS; } /** * ixgbe_dmac_update_tcs_X550 * @hw: pointer to hardware structure * * Disables dmac, updates per TC settings, and then enables dmac. **/ s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw) { u32 reg; DEBUGFUNC("ixgbe_dmac_update_tcs_X550"); /* Disable DMA coalescing before configuring */ reg = IXGBE_READ_REG(hw, IXGBE_DMACR); reg &= ~IXGBE_DMACR_DMAC_EN; IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); ixgbe_dmac_config_tcs_X550(hw); /* Enable DMA coalescing after configuration */ reg = IXGBE_READ_REG(hw, IXGBE_DMACR); reg |= IXGBE_DMACR_DMAC_EN; IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); return IXGBE_SUCCESS; } /** * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params * @hw: pointer to hardware structure * * Initializes the EEPROM parameters ixgbe_eeprom_info within the * ixgbe_hw struct in order to set up EEPROM access. **/ s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) { struct ixgbe_eeprom_info *eeprom = &hw->eeprom; u32 eec; u16 eeprom_size; DEBUGFUNC("ixgbe_init_eeprom_params_X550"); if (eeprom->type == ixgbe_eeprom_uninitialized) { eeprom->semaphore_delay = 10; eeprom->type = ixgbe_flash; eec = IXGBE_READ_REG(hw, IXGBE_EEC); eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> IXGBE_EEC_SIZE_SHIFT); eeprom->word_size = 1 << (eeprom_size + IXGBE_EEPROM_WORD_SIZE_SHIFT); DEBUGOUT2("Eeprom params: type = %d, size = %d\n", eeprom->type, eeprom->word_size); } return IXGBE_SUCCESS; } /** * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning * @hw: pointer to hardware structure * @enable: enable or disable source address pruning * @pool: Rx pool to set source address pruning for **/ void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, unsigned int pool) { u64 pfflp; /* max rx pool is 63 */ if (pool > 63) return; pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; if (enable) pfflp |= (1ULL << pool); else pfflp &= ~(1ULL << pool); IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); } /** * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing * @hw: pointer to hardware structure * @enable: enable or disable switch for Ethertype anti-spoofing * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing * **/ void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, bool enable, int vf) { int vf_target_reg = vf >> 3; int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; u32 pfvfspoof; DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550"); pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); if (enable) pfvfspoof |= (1 << vf_target_shift); else pfvfspoof &= ~(1 << vf_target_shift); IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); } /** * ixgbe_iosf_wait - Wait for IOSF command completion * @hw: pointer to hardware structure * @ctrl: pointer to location to receive final IOSF control value * * Returns failing status on timeout * * Note: ctrl can be NULL if the IOSF control register value is not needed **/ static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) { u32 i, command = 0; /* Check every 10 usec to see if the address cycle completed. * The SB IOSF BUSY bit will clear when the operation is * complete */ for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) break; usec_delay(10); } if (ctrl) *ctrl = command; if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); return IXGBE_ERR_PHY; } return IXGBE_SUCCESS; } /** * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register * of the IOSF device * @hw: pointer to hardware structure * @reg_addr: 32 bit PHY register to write * @device_type: 3 bit device type * @data: Data to write to the register **/ s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u32 data) { u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; u32 command, error __unused; s32 ret; ret = ixgbe_acquire_swfw_semaphore(hw, gssr); if (ret != IXGBE_SUCCESS) return ret; ret = ixgbe_iosf_wait(hw, NULL); if (ret != IXGBE_SUCCESS) goto out; command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); /* Write IOSF control register */ IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); /* Write IOSF data register */ IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); ret = ixgbe_iosf_wait(hw, &command); if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; ERROR_REPORT2(IXGBE_ERROR_POLLING, "Failed to write, error %x\n", error); ret = IXGBE_ERR_PHY; } out: ixgbe_release_swfw_semaphore(hw, gssr); return ret; } /** * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device * @hw: pointer to hardware structure * @reg_addr: 32 bit PHY register to write * @device_type: 3 bit device type * @data: Pointer to read data from the register **/ s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u32 *data) { u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; u32 command, error __unused; s32 ret; ret = ixgbe_acquire_swfw_semaphore(hw, gssr); if (ret != IXGBE_SUCCESS) return ret; ret = ixgbe_iosf_wait(hw, NULL); if (ret != IXGBE_SUCCESS) goto out; command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); /* Write IOSF control register */ IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); ret = ixgbe_iosf_wait(hw, &command); if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; ERROR_REPORT2(IXGBE_ERROR_POLLING, "Failed to read, error %x\n", error); ret = IXGBE_ERR_PHY; } if (ret == IXGBE_SUCCESS) *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); out: ixgbe_release_swfw_semaphore(hw, gssr); return ret; } /** * ixgbe_get_phy_token - Get the token for shared phy access * @hw: Pointer to hardware structure */ s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) { struct ixgbe_hic_phy_token_req token_cmd; s32 status; token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; token_cmd.hdr.cmd_or_resp.cmd_resv = 0; token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; token_cmd.port_number = hw->bus.lan_id; token_cmd.command_type = FW_PHY_TOKEN_REQ; token_cmd.pad = 0; status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd, sizeof(token_cmd), IXGBE_HI_COMMAND_TIMEOUT, TRUE); if (status) { DEBUGOUT1("Issuing host interface command failed with Status = %d\n", status); return status; } if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) return IXGBE_SUCCESS; if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) { DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n", token_cmd.hdr.cmd_or_resp.ret_status); return IXGBE_ERR_FW_RESP_INVALID; } DEBUGOUT("Returning IXGBE_ERR_TOKEN_RETRY\n"); return IXGBE_ERR_TOKEN_RETRY; } /** * ixgbe_put_phy_token - Put the token for shared phy access * @hw: Pointer to hardware structure */ s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) { struct ixgbe_hic_phy_token_req token_cmd; s32 status; token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; token_cmd.hdr.cmd_or_resp.cmd_resv = 0; token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; token_cmd.port_number = hw->bus.lan_id; token_cmd.command_type = FW_PHY_TOKEN_REL; token_cmd.pad = 0; status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd, sizeof(token_cmd), IXGBE_HI_COMMAND_TIMEOUT, TRUE); if (status) return status; if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) return IXGBE_SUCCESS; DEBUGOUT("Put PHY Token host interface command failed"); return IXGBE_ERR_FW_RESP_INVALID; } /** * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register * of the IOSF device * @hw: pointer to hardware structure * @reg_addr: 32 bit PHY register to write * @device_type: 3 bit device type * @data: Data to write to the register **/ s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u32 data) { struct ixgbe_hic_internal_phy_req write_cmd; s32 status; UNREFERENCED_1PARAMETER(device_type); memset(&write_cmd, 0, sizeof(write_cmd)); write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; write_cmd.port_number = hw->bus.lan_id; write_cmd.command_type = FW_INT_PHY_REQ_WRITE; write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr); write_cmd.write_data = IXGBE_CPU_TO_BE32(data); status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd, sizeof(write_cmd), IXGBE_HI_COMMAND_TIMEOUT, FALSE); return status; } /** * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device * @hw: pointer to hardware structure * @reg_addr: 32 bit PHY register to write * @device_type: 3 bit device type * @data: Pointer to read data from the register **/ s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u32 *data) { union { struct ixgbe_hic_internal_phy_req cmd; struct ixgbe_hic_internal_phy_resp rsp; } hic; s32 status; UNREFERENCED_1PARAMETER(device_type); memset(&hic, 0, sizeof(hic)); hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; hic.cmd.port_number = hw->bus.lan_id; hic.cmd.command_type = FW_INT_PHY_REQ_READ; hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr); status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd, sizeof(hic.cmd), IXGBE_HI_COMMAND_TIMEOUT, TRUE); /* Extract the register value from the response. */ *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data); return status; } /** * ixgbe_disable_mdd_X550 * @hw: pointer to hardware structure * * Disable malicious driver detection **/ void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw) { u32 reg; DEBUGFUNC("ixgbe_disable_mdd_X550"); /* Disable MDD for TX DMA and interrupt */ reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); /* Disable MDD for RX and interrupt */ reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); } /** * ixgbe_enable_mdd_X550 * @hw: pointer to hardware structure * * Enable malicious driver detection **/ void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw) { u32 reg; DEBUGFUNC("ixgbe_enable_mdd_X550"); /* Enable MDD for TX DMA and interrupt */ reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); /* Enable MDD for RX and interrupt */ reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); } /** * ixgbe_restore_mdd_vf_X550 * @hw: pointer to hardware structure * @vf: vf index * * Restore VF that was disabled during malicious driver detection event **/ void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf) { u32 idx, reg, num_qs, start_q, bitmask; DEBUGFUNC("ixgbe_restore_mdd_vf_X550"); /* Map VF to queues */ reg = IXGBE_READ_REG(hw, IXGBE_MRQC); switch (reg & IXGBE_MRQC_MRQE_MASK) { case IXGBE_MRQC_VMDQRT8TCEN: num_qs = 8; /* 16 VFs / pools */ bitmask = 0x000000FF; break; case IXGBE_MRQC_VMDQRSS32EN: case IXGBE_MRQC_VMDQRT4TCEN: num_qs = 4; /* 32 VFs / pools */ bitmask = 0x0000000F; break; default: /* 64 VFs / pools */ num_qs = 2; bitmask = 0x00000003; break; } start_q = vf * num_qs; /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */ idx = start_q / 32; reg = 0; reg |= (bitmask << (start_q % 32)); IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg); IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg); } /** * ixgbe_mdd_event_X550 * @hw: pointer to hardware structure * @vf_bitmap: vf bitmap of malicious vfs * * Handle malicious driver detection event. **/ void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap) { u32 wqbr; u32 i, j, reg, q, shift, vf, idx; DEBUGFUNC("ixgbe_mdd_event_X550"); /* figure out pool size for mapping to vf's */ reg = IXGBE_READ_REG(hw, IXGBE_MRQC); switch (reg & IXGBE_MRQC_MRQE_MASK) { case IXGBE_MRQC_VMDQRT8TCEN: shift = 3; /* 16 VFs / pools */ break; case IXGBE_MRQC_VMDQRSS32EN: case IXGBE_MRQC_VMDQRT4TCEN: shift = 2; /* 32 VFs / pools */ break; default: shift = 1; /* 64 VFs / pools */ break; } /* Read WQBR_TX and WQBR_RX and check for malicious queues */ for (i = 0; i < 4; i++) { wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i)); wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i)); if (!wqbr) continue; /* Get malicious queue */ for (j = 0; j < 32 && wqbr; j++) { if (!(wqbr & (1 << j))) continue; /* Get queue from bitmask */ q = j + (i * 32); /* Map queue to vf */ vf = (q >> shift); /* Set vf bit in vf_bitmap */ idx = vf / 32; vf_bitmap[idx] |= (1 << (vf % 32)); wqbr &= ~(1 << j); } } } /** * ixgbe_get_media_type_X550em - Get media type * @hw: pointer to hardware structure * * Returns the media type (fiber, copper, backplane) */ enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) { enum ixgbe_media_type media_type; DEBUGFUNC("ixgbe_get_media_type_X550em"); /* Detect if there is a copper PHY attached. */ switch (hw->device_id) { case IXGBE_DEV_ID_X550EM_X_KR: case IXGBE_DEV_ID_X550EM_X_KX4: case IXGBE_DEV_ID_X550EM_X_XFI: case IXGBE_DEV_ID_X550EM_A_KR: case IXGBE_DEV_ID_X550EM_A_KR_L: media_type = ixgbe_media_type_backplane; break; case IXGBE_DEV_ID_X550EM_X_SFP: case IXGBE_DEV_ID_X550EM_A_SFP: case IXGBE_DEV_ID_X550EM_A_SFP_N: case IXGBE_DEV_ID_X550EM_A_QSFP: case IXGBE_DEV_ID_X550EM_A_QSFP_N: media_type = ixgbe_media_type_fiber; break; case IXGBE_DEV_ID_X550EM_X_1G_T: case IXGBE_DEV_ID_X550EM_X_10G_T: case IXGBE_DEV_ID_X550EM_A_10G_T: media_type = ixgbe_media_type_copper; break; case IXGBE_DEV_ID_X550EM_A_SGMII: case IXGBE_DEV_ID_X550EM_A_SGMII_L: media_type = ixgbe_media_type_backplane; hw->phy.type = ixgbe_phy_sgmii; break; case IXGBE_DEV_ID_X550EM_A_1G_T: case IXGBE_DEV_ID_X550EM_A_1G_T_L: media_type = ixgbe_media_type_copper; break; default: media_type = ixgbe_media_type_unknown; break; } return media_type; } /** * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported * @hw: pointer to hardware structure * @linear: TRUE if SFP module is linear */ static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) { DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); switch (hw->phy.sfp_type) { case ixgbe_sfp_type_not_present: return IXGBE_ERR_SFP_NOT_PRESENT; case ixgbe_sfp_type_da_cu_core0: case ixgbe_sfp_type_da_cu_core1: *linear = TRUE; break; case ixgbe_sfp_type_srlr_core0: case ixgbe_sfp_type_srlr_core1: case ixgbe_sfp_type_da_act_lmt_core0: case ixgbe_sfp_type_da_act_lmt_core1: case ixgbe_sfp_type_1g_sx_core0: case ixgbe_sfp_type_1g_sx_core1: case ixgbe_sfp_type_1g_lx_core0: case ixgbe_sfp_type_1g_lx_core1: *linear = FALSE; break; case ixgbe_sfp_type_unknown: case ixgbe_sfp_type_1g_cu_core0: case ixgbe_sfp_type_1g_cu_core1: default: return IXGBE_ERR_SFP_NOT_SUPPORTED; } return IXGBE_SUCCESS; } /** * ixgbe_identify_sfp_module_X550em - Identifies SFP modules * @hw: pointer to hardware structure * * Searches for and identifies the SFP module and assigns appropriate PHY type. **/ s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) { s32 status; bool linear; DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); status = ixgbe_identify_module_generic(hw); if (status != IXGBE_SUCCESS) return status; /* Check if SFP module is supported */ status = ixgbe_supported_sfp_modules_X550em(hw, &linear); return status; } /** * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops * @hw: pointer to hardware structure */ s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) { s32 status; bool linear; DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); /* Check if SFP module is supported */ status = ixgbe_supported_sfp_modules_X550em(hw, &linear); if (status != IXGBE_SUCCESS) return status; ixgbe_init_mac_link_ops_X550em(hw); hw->phy.ops.reset = NULL; return IXGBE_SUCCESS; } /** * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the * internal PHY * @hw: pointer to hardware structure **/ static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) { s32 status; u32 link_ctrl; /* Restart auto-negotiation. */ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); if (status) { DEBUGOUT("Auto-negotiation did not complete\n"); return status; } link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); if (hw->mac.type == ixgbe_mac_X550EM_a) { u32 flx_mask_st20; /* Indicate to FW that AN restart has been asserted */ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); if (status) { DEBUGOUT("Auto-negotiation did not complete\n"); return status; } flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); } return status; } /** * ixgbe_setup_sgmii - Set up link for sgmii * @hw: pointer to hardware structure * @speed: new link speed * @autoneg_wait: TRUE when waiting for completion is needed */ static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait) { struct ixgbe_mac_info *mac = &hw->mac; u32 lval, sval, flx_val; s32 rc; rc = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); if (rc) return rc; lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; rc = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, lval); if (rc) return rc; rc = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); if (rc) return rc; sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; rc = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, sval); if (rc) return rc; rc = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); if (rc) return rc; flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; rc = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); if (rc) return rc; rc = ixgbe_restart_an_internal_phy_x550em(hw); if (rc) return rc; return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); } /** * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation * @hw: pointer to hardware structure * @speed: new link speed * @autoneg_wait: TRUE when waiting for completion is needed */ static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait) { struct ixgbe_mac_info *mac = &hw->mac; u32 lval, sval, flx_val; s32 rc; rc = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); if (rc) return rc; lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; rc = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, lval); if (rc) return rc; rc = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); if (rc) return rc; sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; rc = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, sval); if (rc) return rc; rc = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, lval); if (rc) return rc; rc = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); if (rc) return rc; flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; rc = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); if (rc) return rc; rc = ixgbe_restart_an_internal_phy_x550em(hw); return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); } /** * ixgbe_init_mac_link_ops_X550em - init mac link function pointers * @hw: pointer to hardware structure */ void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) { struct ixgbe_mac_info *mac = &hw->mac; DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); switch (hw->mac.ops.get_media_type(hw)) { case ixgbe_media_type_fiber: /* CS4227 does not support autoneg, so disable the laser control * functions for SFP+ fiber */ mac->ops.disable_tx_laser = NULL; mac->ops.enable_tx_laser = NULL; mac->ops.flap_tx_laser = NULL; mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; mac->ops.set_rate_select_speed = ixgbe_set_soft_rate_select_speed; if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) || (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP)) mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550a; else mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em; break; case ixgbe_media_type_copper: if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) break; if (hw->mac.type == ixgbe_mac_X550EM_a) { if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { mac->ops.setup_link = ixgbe_setup_sgmii_fw; mac->ops.check_link = ixgbe_check_mac_link_generic; } else { mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; } } else { mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; mac->ops.check_link = ixgbe_check_link_t_X550em; } break; case ixgbe_media_type_backplane: if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) mac->ops.setup_link = ixgbe_setup_sgmii; break; default: break; } } /** * ixgbe_get_link_capabilities_x550em - Determines link capabilities * @hw: pointer to hardware structure * @speed: pointer to link speed * @autoneg: TRUE when autoneg or autotry is enabled */ s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg) { DEBUGFUNC("ixgbe_get_link_capabilities_X550em"); if (hw->phy.type == ixgbe_phy_fw) { *autoneg = TRUE; *speed = hw->phy.speeds_supported; return 0; } /* SFP */ if (hw->phy.media_type == ixgbe_media_type_fiber) { /* CS4227 SFP must not enable auto-negotiation */ *autoneg = FALSE; /* Check if 1G SFP module. */ if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { *speed = IXGBE_LINK_SPEED_1GB_FULL; return IXGBE_SUCCESS; } /* Link capabilities are based on SFP */ if (hw->phy.multispeed_fiber) *speed = IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL; else *speed = IXGBE_LINK_SPEED_10GB_FULL; } else { *autoneg = true; switch (hw->phy.type) { case ixgbe_phy_x550em_xfi: *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_10GB_FULL; *autoneg = false; break; case ixgbe_phy_ext_1g_t: case ixgbe_phy_sgmii: *speed = IXGBE_LINK_SPEED_1GB_FULL; break; case ixgbe_phy_x550em_kr: if (hw->mac.type == ixgbe_mac_X550EM_a) { /* check different backplane modes */ if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { *speed = IXGBE_LINK_SPEED_2_5GB_FULL; break; } else if (hw->device_id == IXGBE_DEV_ID_X550EM_A_KR_L) { *speed = IXGBE_LINK_SPEED_1GB_FULL; break; } } /* fall through */ default: *speed = IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL; break; } } return IXGBE_SUCCESS; } /** * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause * @hw: pointer to hardware structure * @lsc: pointer to boolean flag which indicates whether external Base T * PHY interrupt is lsc * * Determime if external Base T PHY interrupt cause is high temperature * failure alarm or link status change. * * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature * failure alarm, else return PHY access status. */ static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) { u32 status; u16 reg; *lsc = FALSE; /* Vendor alarm triggered */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®); if (status != IXGBE_SUCCESS || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) return status; /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®); if (status != IXGBE_SUCCESS || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | IXGBE_MDIO_GLOBAL_ALARM_1_INT))) return status; /* Global alarm triggered */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®); if (status != IXGBE_SUCCESS) return status; /* If high temperature failure, then return over temp error and exit */ if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { /* power down the PHY in case the PHY FW didn't already */ ixgbe_set_copper_phy_power(hw, FALSE); return IXGBE_ERR_OVERTEMP; } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { /* device fault alarm triggered */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®); if (status != IXGBE_SUCCESS) return status; /* if device fault was due to high temp alarm handle and exit */ if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { /* power down the PHY in case the PHY FW didn't */ ixgbe_set_copper_phy_power(hw, FALSE); return IXGBE_ERR_OVERTEMP; } } /* Vendor alarm 2 triggered */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); if (status != IXGBE_SUCCESS || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) return status; /* link connect/disconnect event occurred */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); if (status != IXGBE_SUCCESS) return status; /* Indicate LSC */ if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) *lsc = TRUE; return IXGBE_SUCCESS; } /** * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts * @hw: pointer to hardware structure * * Enable link status change and temperature failure alarm for the external * Base T PHY * * Returns PHY access status */ static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) { u32 status; u16 reg; bool lsc; /* Clear interrupt flags */ status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); /* Enable link status change alarm */ /* Enable the LASI interrupts on X552 devices to receive notifications * of the link configurations of the external PHY and correspondingly * support the configuration of the internal iXFI link, since iXFI does * not support auto-negotiation. This is not required for X553 devices * having KR support, which performs auto-negotiations and which is used * as the internal link to the external PHY. Hence adding a check here * to avoid enabling LASI interrupts for X553 devices. */ if (hw->mac.type != ixgbe_mac_X550EM_a) { status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); if (status != IXGBE_SUCCESS) return status; reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); if (status != IXGBE_SUCCESS) return status; } /* Enable high temperature failure and global fault alarms */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®); if (status != IXGBE_SUCCESS) return status; reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, reg); if (status != IXGBE_SUCCESS) return status; /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®); if (status != IXGBE_SUCCESS) return status; reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | IXGBE_MDIO_GLOBAL_ALARM_1_INT); status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, reg); if (status != IXGBE_SUCCESS) return status; /* Enable chip-wide vendor alarm */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®); if (status != IXGBE_SUCCESS) return status; reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, reg); return status; } /** * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. * @hw: pointer to hardware structure * @speed: link speed * * Configures the integrated KR PHY. **/ static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, ixgbe_link_speed speed) { s32 status; u32 reg_val; status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status) return status; reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); /* Advertise 10G support. */ if (speed & IXGBE_LINK_SPEED_10GB_FULL) reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; /* Advertise 1G support. */ if (speed & IXGBE_LINK_SPEED_1GB_FULL) reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); if (hw->mac.type == ixgbe_mac_X550EM_a) { /* Set lane mode to KR auto negotiation */ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status) return status; reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); } return ixgbe_restart_an_internal_phy_x550em(hw); } /** * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs * @hw: pointer to hardware structure */ static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) { u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; s32 rc; if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) return IXGBE_SUCCESS; rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); if (rc) return rc; memset(store, 0, sizeof(store)); rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); if (rc) return rc; return ixgbe_setup_fw_link(hw); } /** * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp * @hw: pointer to hardware structure */ static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) { u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; s32 rc; rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); if (rc) return rc; if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { ixgbe_shutdown_fw_phy(hw); return IXGBE_ERR_OVERTEMP; } return IXGBE_SUCCESS; } /** * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register * @hw: pointer to hardware structure * * Read NW_MNG_IF_SEL register and save field values, and check for valid field * values. **/ static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) { /* Save NW management interface connected on board. This is used * to determine internal PHY mode. */ hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set * PHY address. This register field was has only been used for X552. */ if (hw->mac.type == ixgbe_mac_X550EM_a && hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { hw->phy.addr = (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; } return IXGBE_SUCCESS; } /** * ixgbe_init_phy_ops_X550em - PHY/SFP specific init * @hw: pointer to hardware structure * * Initialize any function pointers that were not able to be * set during init_shared_code because the PHY/SFP type was * not known. Perform the SFP init if necessary. */ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) { struct ixgbe_phy_info *phy = &hw->phy; s32 ret_val; DEBUGFUNC("ixgbe_init_phy_ops_X550em"); hw->mac.ops.set_lan_id(hw); ixgbe_read_mng_if_sel_x550em(hw); if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; ixgbe_setup_mux_ctl(hw); phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; } switch (hw->device_id) { case IXGBE_DEV_ID_X550EM_A_1G_T: case IXGBE_DEV_ID_X550EM_A_1G_T_L: phy->ops.read_reg_mdi = NULL; phy->ops.write_reg_mdi = NULL; hw->phy.ops.read_reg = NULL; hw->phy.ops.write_reg = NULL; phy->ops.check_overtemp = ixgbe_check_overtemp_fw; if (hw->bus.lan_id) hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; else hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; break; case IXGBE_DEV_ID_X550EM_A_10G_T: case IXGBE_DEV_ID_X550EM_A_SFP: hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; if (hw->bus.lan_id) hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; else hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; break; case IXGBE_DEV_ID_X550EM_X_SFP: /* set up for CS4227 usage */ hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; break; case IXGBE_DEV_ID_X550EM_X_1G_T: phy->ops.read_reg_mdi = NULL; phy->ops.write_reg_mdi = NULL; default: break; } /* Identify the PHY or SFP module */ ret_val = phy->ops.identify(hw); if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || ret_val == IXGBE_ERR_PHY_ADDR_INVALID) return ret_val; /* Setup function pointers based on detected hardware */ ixgbe_init_mac_link_ops_X550em(hw); if (phy->sfp_type != ixgbe_sfp_type_unknown) phy->ops.reset = NULL; /* Set functions pointers based on phy type */ switch (hw->phy.type) { case ixgbe_phy_x550em_kx4: phy->ops.setup_link = NULL; phy->ops.read_reg = ixgbe_read_phy_reg_x550em; phy->ops.write_reg = ixgbe_write_phy_reg_x550em; break; case ixgbe_phy_x550em_kr: phy->ops.setup_link = ixgbe_setup_kr_x550em; phy->ops.read_reg = ixgbe_read_phy_reg_x550em; phy->ops.write_reg = ixgbe_write_phy_reg_x550em; break; case ixgbe_phy_ext_1g_t: /* link is managed by FW */ phy->ops.setup_link = NULL; phy->ops.reset = NULL; break; case ixgbe_phy_x550em_xfi: /* link is managed by HW */ phy->ops.setup_link = NULL; phy->ops.read_reg = ixgbe_read_phy_reg_x550em; phy->ops.write_reg = ixgbe_write_phy_reg_x550em; break; case ixgbe_phy_x550em_ext_t: /* If internal link mode is XFI, then setup iXFI internal link, * else setup KR now. */ phy->ops.setup_internal_link = ixgbe_setup_internal_phy_t_x550em; /* setup SW LPLU only for first revision of X550EM_x */ if ((hw->mac.type == ixgbe_mac_X550EM_x) && !(IXGBE_FUSES0_REV_MASK & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))) phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; phy->ops.reset = ixgbe_reset_phy_t_X550em; break; case ixgbe_phy_sgmii: phy->ops.setup_link = NULL; break; case ixgbe_phy_fw: phy->ops.setup_link = ixgbe_setup_fw_link; phy->ops.reset = ixgbe_reset_phy_fw; break; default: break; } return ret_val; } /** * ixgbe_set_mdio_speed - Set MDIO clock speed * @hw: pointer to hardware structure */ static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) { u32 hlreg0; switch (hw->device_id) { case IXGBE_DEV_ID_X550EM_X_10G_T: case IXGBE_DEV_ID_X550EM_A_SGMII: case IXGBE_DEV_ID_X550EM_A_SGMII_L: case IXGBE_DEV_ID_X550EM_A_10G_T: case IXGBE_DEV_ID_X550EM_A_SFP: case IXGBE_DEV_ID_X550EM_A_QSFP: /* Config MDIO clock speed before the first MDIO PHY access */ hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); hlreg0 &= ~IXGBE_HLREG0_MDCSPD; IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); break; case IXGBE_DEV_ID_X550EM_A_1G_T: case IXGBE_DEV_ID_X550EM_A_1G_T_L: /* Select fast MDIO clock speed for these devices */ hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); hlreg0 |= IXGBE_HLREG0_MDCSPD; IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); break; default: break; } } /** * ixgbe_reset_hw_X550em - Perform hardware reset * @hw: pointer to hardware structure * * Resets the hardware by resetting the transmit and receive units, masks * and clears all interrupts, perform a PHY reset, and perform a link (MAC) * reset. */ s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) { ixgbe_link_speed link_speed; s32 status; u32 ctrl = 0; u32 i; bool link_up = FALSE; u32 swfw_mask = hw->phy.phy_semaphore_mask; DEBUGFUNC("ixgbe_reset_hw_X550em"); /* Call adapter stop to disable Tx/Rx and clear interrupts */ status = hw->mac.ops.stop_adapter(hw); if (status != IXGBE_SUCCESS) { DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status); return status; } /* flush pending Tx transactions */ ixgbe_clear_tx_pending(hw); ixgbe_set_mdio_speed(hw); /* PHY ops must be identified and initialized prior to reset */ status = hw->phy.ops.init(hw); if (status) DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n", status); if (status == IXGBE_ERR_SFP_NOT_SUPPORTED || status == IXGBE_ERR_PHY_ADDR_INVALID) { DEBUGOUT("Returning from reset HW due to PHY init failure\n"); return status; } /* start the external PHY */ if (hw->phy.type == ixgbe_phy_x550em_ext_t) { status = ixgbe_init_ext_t_x550em(hw); if (status) { DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n", status); return status; } } /* Setup SFP module if there is one present. */ if (hw->phy.sfp_setup_needed) { status = hw->mac.ops.setup_sfp(hw); hw->phy.sfp_setup_needed = FALSE; } if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) return status; /* Reset PHY */ if (!hw->phy.reset_disable && hw->phy.ops.reset) { if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP) return IXGBE_ERR_OVERTEMP; } mac_reset_top: /* Issue global reset to the MAC. Needs to be SW reset if link is up. * If link reset is used when link is up, it might reset the PHY when * mng is using it. If link is down or the flag to force full link * reset is set, then perform link reset. */ ctrl = IXGBE_CTRL_LNK_RST; if (!hw->force_full_reset) { hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); if (link_up) ctrl = IXGBE_CTRL_RST; } status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); if (status != IXGBE_SUCCESS) { ERROR_REPORT2(IXGBE_ERROR_CAUTION, "semaphore failed with %d", status); return IXGBE_ERR_SWFW_SYNC; } ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); IXGBE_WRITE_FLUSH(hw); hw->mac.ops.release_swfw_sync(hw, swfw_mask); /* Poll for reset bit to self-clear meaning reset is complete */ for (i = 0; i < 10; i++) { usec_delay(1); ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); if (!(ctrl & IXGBE_CTRL_RST_MASK)) break; } if (ctrl & IXGBE_CTRL_RST_MASK) { status = IXGBE_ERR_RESET_FAILED; DEBUGOUT("Reset polling failed to complete.\n"); } msec_delay(50); /* Double resets are required for recovery from certain error * conditions. Between resets, it is necessary to stall to * allow time for any pending HW events to complete. */ if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; goto mac_reset_top; } /* Store the permanent mac address */ hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); /* Store MAC address from RAR0, clear receive address registers, and * clear the multicast table. Also reset num_rar_entries to 128, * since we modify this value when programming the SAN MAC address. */ hw->mac.num_rar_entries = 128; hw->mac.ops.init_rx_addrs(hw); ixgbe_set_mdio_speed(hw); if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) ixgbe_setup_mux_ctl(hw); if (status != IXGBE_SUCCESS) DEBUGOUT1("Reset HW failed, STATUS = %d\n", status); return status; } /** * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. * @hw: pointer to hardware structure */ s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) { u32 status; u16 reg; status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_TX_VENDOR_ALARMS_3, IXGBE_MDIO_PMA_PMD_DEV_TYPE, ®); if (status != IXGBE_SUCCESS) return status; /* If PHY FW reset completed bit is set then this is the first * SW instance after a power on so the PHY FW must be un-stalled. */ if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_RES_PR_10, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®); if (status != IXGBE_SUCCESS) return status; reg &= ~IXGBE_MDIO_POWER_UP_STALL; status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_RES_PR_10, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, reg); if (status != IXGBE_SUCCESS) return status; } return status; } /** * ixgbe_setup_kr_x550em - Configure the KR PHY. * @hw: pointer to hardware structure **/ s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) { /* leave link alone for 2.5G */ if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) return IXGBE_SUCCESS; if (ixgbe_check_reset_blocked(hw)) return 0; return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); } /** * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP * @hw: pointer to hardware structure * @speed: new link speed * @autoneg_wait_to_complete: unused * * Configure the external PHY and the integrated KR PHY for SFP support. **/ s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete) { s32 ret_val; u16 reg_slice, reg_val; bool setup_linear = FALSE; UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); /* Check if SFP module is supported and linear */ ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); /* If no SFP module present, then return success. Return success since * there is no reason to configure CS4227 and SFP not present error is * not excepted in the setup MAC link flow. */ if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) return IXGBE_SUCCESS; if (ret_val != IXGBE_SUCCESS) return ret_val; /* Configure internal PHY for KR/KX. */ ixgbe_setup_kr_speed_x550em(hw, speed); /* Configure CS4227 LINE side to proper mode. */ reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); if (setup_linear) reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; else reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, reg_val); return ret_val; } /** * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode * @hw: pointer to hardware structure * @speed: the link speed to force * * Configures the integrated PHY for native SFI mode. Used to connect the * internal PHY directly to an SFP cage, without autonegotiation. **/ static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) { struct ixgbe_mac_info *mac = &hw->mac; s32 status; u32 reg_val; /* Disable all AN and force speed to 10G Serial. */ status = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status != IXGBE_SUCCESS) return status; reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; /* Select forced link speed for internal PHY. */ switch (*speed) { case IXGBE_LINK_SPEED_10GB_FULL: reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; break; case IXGBE_LINK_SPEED_1GB_FULL: reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; break; default: /* Other link speeds are not supported by internal PHY. */ return IXGBE_ERR_LINK_SETUP; } status = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); /* Toggle port SW reset by AN reset. */ status = ixgbe_restart_an_internal_phy_x550em(hw); return status; } /** * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP * @hw: pointer to hardware structure * @speed: new link speed * @autoneg_wait_to_complete: unused * * Configure the the integrated PHY for SFP support. **/ s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete) { s32 ret_val; u16 reg_phy_ext; bool setup_linear = FALSE; u32 reg_slice, reg_phy_int, slice_offset; UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); /* Check if SFP module is supported and linear */ ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); /* If no SFP module present, then return success. Return success since * SFP not present error is not excepted in the setup MAC link flow. */ if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) return IXGBE_SUCCESS; if (ret_val != IXGBE_SUCCESS) return ret_val; if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) { /* Configure internal PHY for native SFI based on module type */ ret_val = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); if (ret_val != IXGBE_SUCCESS) return ret_val; reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; if (!setup_linear) reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; ret_val = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); if (ret_val != IXGBE_SUCCESS) return ret_val; /* Setup SFI internal link. */ ret_val = ixgbe_setup_sfi_x550a(hw, &speed); } else { /* Configure internal PHY for KR/KX. */ ixgbe_setup_kr_speed_x550em(hw, speed); if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) { /* Find Address */ DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n"); return IXGBE_ERR_PHY_ADDR_INVALID; } /* Get external PHY SKU id */ ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); if (ret_val != IXGBE_SUCCESS) return ret_val; /* When configuring quad port CS4223, the MAC instance is part * of the slice offset. */ if (reg_phy_ext == IXGBE_CS4223_SKU_ID) slice_offset = (hw->bus.lan_id + (hw->bus.instance_id << 1)) << 12; else slice_offset = hw->bus.lan_id << 12; /* Configure CS4227/CS4223 LINE side to proper mode. */ reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; ret_val = hw->phy.ops.read_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); if (ret_val != IXGBE_SUCCESS) return ret_val; reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | (IXGBE_CS4227_EDC_MODE_SR << 1)); if (setup_linear) reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; else reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; ret_val = hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); /* Flush previous write with a read */ ret_val = hw->phy.ops.read_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); } return ret_val; } /** * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration * @hw: pointer to hardware structure * * iXfI configuration needed for ixgbe_mac_X550EM_x devices. **/ static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) { struct ixgbe_mac_info *mac = &hw->mac; s32 status; u32 reg_val; /* Disable training protocol FSM. */ status = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status != IXGBE_SUCCESS) return status; reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; status = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); if (status != IXGBE_SUCCESS) return status; /* Disable Flex from training TXFFE. */ status = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status != IXGBE_SUCCESS) return status; reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; status = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); if (status != IXGBE_SUCCESS) return status; status = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status != IXGBE_SUCCESS) return status; reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; status = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); if (status != IXGBE_SUCCESS) return status; /* Enable override for coefficients. */ status = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status != IXGBE_SUCCESS) return status; reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; status = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); return status; } /** * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. * @hw: pointer to hardware structure * @speed: the link speed to force * * Configures the integrated KR PHY to use iXFI mode. Used to connect an * internal and external PHY at a specific speed, without autonegotiation. **/ static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) { struct ixgbe_mac_info *mac = &hw->mac; s32 status; u32 reg_val; /* iXFI is only supported with X552 */ if (mac->type != ixgbe_mac_X550EM_x) return IXGBE_ERR_LINK_SETUP; /* Disable AN and force speed to 10G Serial. */ status = mac->ops.read_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status != IXGBE_SUCCESS) return status; reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; /* Select forced link speed for internal PHY. */ switch (*speed) { case IXGBE_LINK_SPEED_10GB_FULL: reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; break; case IXGBE_LINK_SPEED_1GB_FULL: reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; break; default: /* Other link speeds are not supported by internal KR PHY. */ return IXGBE_ERR_LINK_SETUP; } status = mac->ops.write_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); if (status != IXGBE_SUCCESS) return status; /* Additional configuration needed for x550em_x */ if (hw->mac.type == ixgbe_mac_X550EM_x) { status = ixgbe_setup_ixfi_x550em_x(hw); if (status != IXGBE_SUCCESS) return status; } /* Toggle port SW reset by AN reset. */ status = ixgbe_restart_an_internal_phy_x550em(hw); return status; } /** * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status * @hw: address of hardware structure * @link_up: address of boolean to indicate link status * * Returns error code if unable to get link status. */ static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) { u32 ret; u16 autoneg_status; *link_up = FALSE; /* read this twice back to back to indicate current status */ ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_status); if (ret != IXGBE_SUCCESS) return ret; ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_status); if (ret != IXGBE_SUCCESS) return ret; *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); return IXGBE_SUCCESS; } /** * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link * @hw: point to hardware structure * * Configures the link between the integrated KR PHY and the external X557 PHY * The driver will call this function when it gets a link status change * interrupt from the X557 PHY. This function configures the link speed * between the PHYs to match the link speed of the BASE-T link. * * A return of a non-zero value indicates an error, and the base driver should * not report link up. */ s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) { ixgbe_link_speed force_speed; bool link_up; u32 status; u16 speed; if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) return IXGBE_ERR_CONFIG; if (hw->mac.type == ixgbe_mac_X550EM_x && !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { /* If link is down, there is no setup necessary so return */ status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); if (status != IXGBE_SUCCESS) return status; if (!link_up) return IXGBE_SUCCESS; status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &speed); if (status != IXGBE_SUCCESS) return status; /* If link is still down - no setup is required so return */ status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); if (status != IXGBE_SUCCESS) return status; if (!link_up) return IXGBE_SUCCESS; /* clear everything but the speed and duplex bits */ speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; switch (speed) { case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: force_speed = IXGBE_LINK_SPEED_10GB_FULL; break; case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: force_speed = IXGBE_LINK_SPEED_1GB_FULL; break; default: /* Internal PHY does not support anything else */ return IXGBE_ERR_INVALID_LINK_SETTINGS; } return ixgbe_setup_ixfi_x550em(hw, &force_speed); } else { speed = IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL; return ixgbe_setup_kr_speed_x550em(hw, speed); } } /** * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback. * @hw: pointer to hardware structure * * Configures the integrated KR PHY to use internal loopback mode. **/ s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw) { s32 status; u32 reg_val; /* Disable AN and force speed to 10G Serial. */ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status != IXGBE_SUCCESS) return status; reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); if (status != IXGBE_SUCCESS) return status; /* Set near-end loopback clocks. */ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status != IXGBE_SUCCESS) return status; reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B; reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS; status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); if (status != IXGBE_SUCCESS) return status; /* Set loopback enable. */ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status != IXGBE_SUCCESS) return status; reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK; status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); if (status != IXGBE_SUCCESS) return status; /* Training bypass. */ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (status != IXGBE_SUCCESS) return status; reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); return status; } /** * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command * assuming that the semaphore is already obtained. * @hw: pointer to hardware structure * @offset: offset of word in the EEPROM to read * @data: word read from the EEPROM * * Reads a 16 bit word from the EEPROM using the hostif. **/ s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) { const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; struct ixgbe_hic_read_shadow_ram buffer; s32 status; DEBUGFUNC("ixgbe_read_ee_hostif_X550"); buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; buffer.hdr.req.buf_lenh = 0; buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; /* convert offset from words to bytes */ buffer.address = IXGBE_CPU_TO_BE32(offset * 2); /* one word */ buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); buffer.pad2 = 0; buffer.data = 0; buffer.pad3 = 0; status = hw->mac.ops.acquire_swfw_sync(hw, mask); if (status) return status; status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), IXGBE_HI_COMMAND_TIMEOUT); if (!status) { *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, FW_NVM_DATA_OFFSET); } hw->mac.ops.release_swfw_sync(hw, mask); return status; } /** * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif * @hw: pointer to hardware structure * @offset: offset of word in the EEPROM to read * @words: number of words * @data: word(s) read from the EEPROM * * Reads a 16 bit word(s) from the EEPROM using the hostif. **/ s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data) { const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; struct ixgbe_hic_read_shadow_ram buffer; u32 current_word = 0; u16 words_to_read; s32 status; u32 i; DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550"); /* Take semaphore for the entire operation. */ status = hw->mac.ops.acquire_swfw_sync(hw, mask); if (status) { DEBUGOUT("EEPROM read buffer - semaphore failed\n"); return status; } while (words) { if (words > FW_MAX_READ_BUFFER_SIZE / 2) words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; else words_to_read = words; buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; buffer.hdr.req.buf_lenh = 0; buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; /* convert offset from words to bytes */ buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); buffer.pad2 = 0; buffer.data = 0; buffer.pad3 = 0; status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), IXGBE_HI_COMMAND_TIMEOUT); if (status) { DEBUGOUT("Host interface command failed\n"); goto out; } for (i = 0; i < words_to_read; i++) { u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 2 * i; u32 value = IXGBE_READ_REG(hw, reg); data[current_word] = (u16)(value & 0xffff); current_word++; i++; if (i < words_to_read) { value >>= 16; data[current_word] = (u16)(value & 0xffff); current_word++; } } words -= words_to_read; } out: hw->mac.ops.release_swfw_sync(hw, mask); return status; } /** * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif * @hw: pointer to hardware structure * @offset: offset of word in the EEPROM to write * @data: word write to the EEPROM * * Write a 16 bit word to the EEPROM using the hostif. **/ s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, u16 data) { s32 status; struct ixgbe_hic_write_shadow_ram buffer; DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; buffer.hdr.req.buf_lenh = 0; buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; /* one word */ buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); buffer.data = data; buffer.address = IXGBE_CPU_TO_BE32(offset * 2); status = ixgbe_host_interface_command(hw, (u32 *)&buffer, sizeof(buffer), IXGBE_HI_COMMAND_TIMEOUT, TRUE); if (status != IXGBE_SUCCESS) { DEBUGOUT2("for offset %04x failed with status %d\n", offset, status); return status; } if (buffer.hdr.rsp.buf_lenh_status != FW_CEM_RESP_STATUS_SUCCESS) { DEBUGOUT2("for offset %04x host interface return status %02x\n", offset, buffer.hdr.rsp.buf_lenh_status); return IXGBE_ERR_HOST_INTERFACE_COMMAND; } return status; } /** * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif * @hw: pointer to hardware structure * @offset: offset of word in the EEPROM to write * @data: word write to the EEPROM * * Write a 16 bit word to the EEPROM using the hostif. **/ s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) { s32 status = IXGBE_SUCCESS; DEBUGFUNC("ixgbe_write_ee_hostif_X550"); if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == IXGBE_SUCCESS) { status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); } else { DEBUGOUT("write ee hostif failed to get semaphore"); status = IXGBE_ERR_SWFW_SYNC; } return status; } /** * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif * @hw: pointer to hardware structure * @offset: offset of word in the EEPROM to write * @words: number of words * @data: word(s) write to the EEPROM * * Write a 16 bit word(s) to the EEPROM using the hostif. **/ s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data) { s32 status = IXGBE_SUCCESS; u32 i = 0; DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550"); /* Take semaphore for the entire operation. */ status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); if (status != IXGBE_SUCCESS) { DEBUGOUT("EEPROM write buffer - semaphore failed\n"); goto out; } for (i = 0; i < words; i++) { status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, data[i]); if (status != IXGBE_SUCCESS) { DEBUGOUT("Eeprom buffered write failed\n"); break; } } hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); out: return status; } /** * ixgbe_checksum_ptr_x550 - Checksum one pointer region * @hw: pointer to hardware structure * @ptr: pointer offset in eeprom * @size: size of section pointed by ptr, if 0 first word will be used as size * @csum: address of checksum to update * @buffer: pointer to buffer containing calculated checksum * @buffer_size: size of buffer * * Returns error status for any failure */ static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, u16 size, u16 *csum, u16 *buffer, u32 buffer_size) { u16 buf[256]; s32 status; u16 length, bufsz, i, start; u16 *local_buffer; bufsz = sizeof(buf) / sizeof(buf[0]); /* Read a chunk at the pointer location */ if (!buffer) { status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); if (status) { DEBUGOUT("Failed to read EEPROM image\n"); return status; } local_buffer = buf; } else { if (buffer_size < ptr) return IXGBE_ERR_PARAM; local_buffer = &buffer[ptr]; } if (size) { start = 0; length = size; } else { start = 1; length = local_buffer[0]; /* Skip pointer section if length is invalid. */ if (length == 0xFFFF || length == 0 || (ptr + length) >= hw->eeprom.word_size) return IXGBE_SUCCESS; } if (buffer && ((u32)start + (u32)length > buffer_size)) return IXGBE_ERR_PARAM; for (i = start; length; i++, length--) { if (i == bufsz && !buffer) { ptr += bufsz; i = 0; if (length < bufsz) bufsz = length; /* Read a chunk at the pointer location */ status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); if (status) { DEBUGOUT("Failed to read EEPROM image\n"); return status; } } *csum += local_buffer[i]; } return IXGBE_SUCCESS; } /** * ixgbe_calc_checksum_X550 - Calculates and returns the checksum * @hw: pointer to hardware structure * @buffer: pointer to buffer containing calculated checksum * @buffer_size: size of buffer * * Returns a negative error code on error, or the 16-bit checksum **/ s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) { u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; u16 *local_buffer; s32 status; u16 checksum = 0; u16 pointer, i, size; DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550"); hw->eeprom.ops.init_params(hw); if (!buffer) { /* Read pointer area */ status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, IXGBE_EEPROM_LAST_WORD + 1, eeprom_ptrs); if (status) { DEBUGOUT("Failed to read EEPROM image\n"); return status; } local_buffer = eeprom_ptrs; } else { if (buffer_size < IXGBE_EEPROM_LAST_WORD) return IXGBE_ERR_PARAM; local_buffer = buffer; } /* * For X550 hardware include 0x0-0x41 in the checksum, skip the * checksum word itself */ for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) if (i != IXGBE_EEPROM_CHECKSUM) checksum += local_buffer[i]; /* * Include all data from pointers 0x3, 0x6-0xE. This excludes the * FW, PHY module, and PCIe Expansion/Option ROM pointers. */ for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) continue; pointer = local_buffer[i]; /* Skip pointer section if the pointer is invalid. */ if (pointer == 0xFFFF || pointer == 0 || pointer >= hw->eeprom.word_size) continue; switch (i) { case IXGBE_PCIE_GENERAL_PTR: size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; break; case IXGBE_PCIE_CONFIG0_PTR: case IXGBE_PCIE_CONFIG1_PTR: size = IXGBE_PCIE_CONFIG_SIZE; break; default: size = 0; break; } status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, buffer, buffer_size); if (status) return status; } checksum = (u16)IXGBE_EEPROM_SUM - checksum; return (s32)checksum; } /** * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum * @hw: pointer to hardware structure * * Returns a negative error code on error, or the 16-bit checksum **/ s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) { return ixgbe_calc_checksum_X550(hw, NULL, 0); } /** * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum * @hw: pointer to hardware structure * @checksum_val: calculated checksum * * Performs checksum calculation and validates the EEPROM checksum. If the * caller does not need checksum_val, the value can be NULL. **/ s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) { s32 status; u16 checksum; u16 read_checksum = 0; DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550"); /* Read the first word from the EEPROM. If this times out or fails, do * not continue or we could be in for a very long wait while every * EEPROM read fails */ status = hw->eeprom.ops.read(hw, 0, &checksum); if (status) { DEBUGOUT("EEPROM read failed\n"); return status; } status = hw->eeprom.ops.calc_checksum(hw); if (status < 0) return status; checksum = (u16)(status & 0xffff); status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); if (status) return status; /* Verify read checksum from EEPROM is the same as * calculated checksum */ if (read_checksum != checksum) { status = IXGBE_ERR_EEPROM_CHECKSUM; ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, "Invalid EEPROM checksum"); } /* If the user cares, return the calculated checksum */ if (checksum_val) *checksum_val = checksum; return status; } /** * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash * @hw: pointer to hardware structure * * After writing EEPROM to shadow RAM using EEWR register, software calculates * checksum and updates the EEPROM and instructs the hardware to update * the flash. **/ s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) { s32 status; u16 checksum = 0; DEBUGFUNC("ixgbe_update_eeprom_checksum_X550"); /* Read the first word from the EEPROM. If this times out or fails, do * not continue or we could be in for a very long wait while every * EEPROM read fails */ status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); if (status) { DEBUGOUT("EEPROM read failed\n"); return status; } status = ixgbe_calc_eeprom_checksum_X550(hw); if (status < 0) return status; checksum = (u16)(status & 0xffff); status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, checksum); if (status) return status; status = ixgbe_update_flash_X550(hw); return status; } /** * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device * @hw: pointer to hardware structure * * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. **/ s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) { s32 status = IXGBE_SUCCESS; union ixgbe_hic_hdr2 buffer; DEBUGFUNC("ixgbe_update_flash_X550"); buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; buffer.req.buf_lenh = 0; buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; buffer.req.checksum = FW_DEFAULT_CHECKSUM; status = ixgbe_host_interface_command(hw, (u32 *)&buffer, sizeof(buffer), IXGBE_HI_COMMAND_TIMEOUT, FALSE); return status; } /** * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type * @hw: pointer to hardware structure * * Determines physical layer capabilities of the current configuration. **/ u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw) { u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; u16 ext_ability = 0; DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em"); hw->phy.ops.identify(hw); switch (hw->phy.type) { case ixgbe_phy_x550em_kr: if (hw->mac.type == ixgbe_mac_X550EM_a) { if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { physical_layer = IXGBE_PHYSICAL_LAYER_2500BASE_KX; break; } else if (hw->device_id == IXGBE_DEV_ID_X550EM_A_KR_L) { physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; break; } } /* fall through */ case ixgbe_phy_x550em_xfi: physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR | IXGBE_PHYSICAL_LAYER_1000BASE_KX; break; case ixgbe_phy_x550em_kx4: physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | IXGBE_PHYSICAL_LAYER_1000BASE_KX; break; case ixgbe_phy_x550em_ext_t: hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; break; case ixgbe_phy_fw: if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL) physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL) physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL) physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T; break; case ixgbe_phy_sgmii: physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; break; case ixgbe_phy_ext_1g_t: physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; break; default: break; } if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); return physical_layer; } /** * ixgbe_get_bus_info_x550em - Set PCI bus info * @hw: pointer to hardware structure * * Sets bus link width and speed to unknown because X550em is * not a PCI device. **/ s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) { DEBUGFUNC("ixgbe_get_bus_info_x550em"); hw->bus.width = ixgbe_bus_width_unknown; hw->bus.speed = ixgbe_bus_speed_unknown; hw->mac.ops.set_lan_id(hw); return IXGBE_SUCCESS; } /** * ixgbe_disable_rx_x550 - Disable RX unit * @hw: pointer to hardware structure * * Enables the Rx DMA unit for x550 **/ void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) { u32 rxctrl, pfdtxgswc; s32 status; struct ixgbe_hic_disable_rxen fw_cmd; DEBUGFUNC("ixgbe_enable_rx_dma_x550"); rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); if (rxctrl & IXGBE_RXCTRL_RXEN) { pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); hw->mac.set_lben = TRUE; } else { hw->mac.set_lben = FALSE; } fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; fw_cmd.port_number = (u8)hw->bus.lan_id; status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, sizeof(struct ixgbe_hic_disable_rxen), IXGBE_HI_COMMAND_TIMEOUT, TRUE); /* If we fail - disable RX using register write */ if (status) { rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); if (rxctrl & IXGBE_RXCTRL_RXEN) { rxctrl &= ~IXGBE_RXCTRL_RXEN; IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); } } } } /** * ixgbe_enter_lplu_x550em - Transition to low power states * @hw: pointer to hardware structure * * Configures Low Power Link Up on transition to low power states * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the * X557 PHY immediately prior to entering LPLU. **/ s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) { u16 an_10g_cntl_reg, autoneg_reg, speed; s32 status; ixgbe_link_speed lcd_speed; u32 save_autoneg; bool link_up; /* SW LPLU not required on later HW revisions. */ if ((hw->mac.type == ixgbe_mac_X550EM_x) && (IXGBE_FUSES0_REV_MASK & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))) return IXGBE_SUCCESS; /* If blocked by MNG FW, then don't restart AN */ if (ixgbe_check_reset_blocked(hw)) return IXGBE_SUCCESS; status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); if (status != IXGBE_SUCCESS) return status; status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3); if (status != IXGBE_SUCCESS) return status; /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability * disabled, then force link down by entering low power mode. */ if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || !(hw->wol_enabled || ixgbe_mng_present(hw))) return ixgbe_set_copper_phy_power(hw, FALSE); /* Determine LCD */ status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); if (status != IXGBE_SUCCESS) return status; /* If no valid LCD link speed, then force link down and exit. */ if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) return ixgbe_set_copper_phy_power(hw, FALSE); status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &speed); if (status != IXGBE_SUCCESS) return status; /* If no link now, speed is invalid so take link down */ status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); if (status != IXGBE_SUCCESS) return ixgbe_set_copper_phy_power(hw, FALSE); /* clear everything but the speed bits */ speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; /* If current speed is already LCD, then exit. */ if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) return status; /* Clear AN completed indication */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); if (status != IXGBE_SUCCESS) return status; status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_10g_cntl_reg); if (status != IXGBE_SUCCESS) return status; status = hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); if (status != IXGBE_SUCCESS) return status; save_autoneg = hw->phy.autoneg_advertised; /* Setup link at least common link speed */ status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE); /* restore autoneg from before setting lplu speed */ hw->phy.autoneg_advertised = save_autoneg; return status; } /** * ixgbe_get_lcd_x550em - Determine lowest common denominator * @hw: pointer to hardware structure * @lcd_speed: pointer to lowest common link speed * * Determine lowest common link speed with link partner. **/ s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed) { u16 an_lp_status; s32 status; u16 word = hw->eeprom.ctrl_word_3; *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_lp_status); if (status != IXGBE_SUCCESS) return status; /* If link partner advertised 1G, return 1G */ if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; return status; } /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) return status; /* Link partner not capable of lower speeds, return 10G */ *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; return status; } /** * ixgbe_setup_fc_X550em - Set up flow control * @hw: pointer to hardware structure * * Called at init time to set up flow control. **/ s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw) { s32 ret_val = IXGBE_SUCCESS; u32 pause, asm_dir, reg_val; DEBUGFUNC("ixgbe_setup_fc_X550em"); /* Validate the requested mode */ if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; goto out; } /* 10gig parts do not have a word in the EEPROM to determine the * default flow control setting, so we explicitly set it to full. */ if (hw->fc.requested_mode == ixgbe_fc_default) hw->fc.requested_mode = ixgbe_fc_full; /* Determine PAUSE and ASM_DIR bits. */ switch (hw->fc.requested_mode) { case ixgbe_fc_none: pause = 0; asm_dir = 0; break; case ixgbe_fc_tx_pause: pause = 0; asm_dir = 1; break; case ixgbe_fc_rx_pause: /* Rx Flow control is enabled and Tx Flow control is * disabled by software override. Since there really * isn't a way to advertise that we are capable of RX * Pause ONLY, we will advertise that we support both * symmetric and asymmetric Rx PAUSE, as such we fall * through to the fc_full statement. Later, we will * disable the adapter's ability to send PAUSE frames. */ case ixgbe_fc_full: pause = 1; asm_dir = 1; break; default: ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Flow control param set incorrectly\n"); ret_val = IXGBE_ERR_CONFIG; goto out; } switch (hw->device_id) { case IXGBE_DEV_ID_X550EM_X_KR: case IXGBE_DEV_ID_X550EM_A_KR: case IXGBE_DEV_ID_X550EM_A_KR_L: ret_val = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); if (ret_val != IXGBE_SUCCESS) goto out; reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); if (pause) reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; if (asm_dir) reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; ret_val = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); /* This device does not fully support AN. */ hw->fc.disable_fc_autoneg = TRUE; break; case IXGBE_DEV_ID_X550EM_X_XFI: hw->fc.disable_fc_autoneg = TRUE; break; default: break; } out: return ret_val; } /** * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 * @hw: pointer to hardware structure * * Enable flow control according to IEEE clause 37. **/ void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) { u32 link_s1, lp_an_page_low, an_cntl_1; s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; ixgbe_link_speed speed; bool link_up; /* AN should have completed when the cable was plugged in. * Look for reasons to bail out. Bail out if: * - FC autoneg is disabled, or if * - link is not up. */ if (hw->fc.disable_fc_autoneg) { ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, "Flow control autoneg is disabled"); goto out; } hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); if (!link_up) { ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); goto out; } /* Check at auto-negotiation has completed */ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_LINK_S1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); if (status != IXGBE_SUCCESS || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { DEBUGOUT("Auto-Negotiation did not complete\n"); status = IXGBE_ERR_FC_NOT_NEGOTIATED; goto out; } /* Read the 10g AN autoc and LP ability registers and resolve * local flow control settings accordingly */ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); if (status != IXGBE_SUCCESS) { DEBUGOUT("Auto-Negotiation did not complete\n"); goto out; } status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); if (status != IXGBE_SUCCESS) { DEBUGOUT("Auto-Negotiation did not complete\n"); goto out; } status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); out: if (status == IXGBE_SUCCESS) { hw->fc.fc_was_autonegged = TRUE; } else { hw->fc.fc_was_autonegged = FALSE; hw->fc.current_mode = hw->fc.requested_mode; } } /** * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings * @hw: pointer to hardware structure * **/ void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) { hw->fc.fc_was_autonegged = FALSE; hw->fc.current_mode = hw->fc.requested_mode; } /** * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 * @hw: pointer to hardware structure * * Enable flow control according to IEEE clause 37. **/ void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) { s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; ixgbe_link_speed speed; bool link_up; /* AN should have completed when the cable was plugged in. * Look for reasons to bail out. Bail out if: * - FC autoneg is disabled, or if * - link is not up. */ if (hw->fc.disable_fc_autoneg) { ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, "Flow control autoneg is disabled"); goto out; } hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); if (!link_up) { ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); goto out; } /* Check if auto-negotiation has completed */ status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); if (status != IXGBE_SUCCESS || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { DEBUGOUT("Auto-Negotiation did not complete\n"); status = IXGBE_ERR_FC_NOT_NEGOTIATED; goto out; } /* Negotiate the flow control */ status = ixgbe_negotiate_fc(hw, info[0], info[0], FW_PHY_ACT_GET_LINK_INFO_FC_RX, FW_PHY_ACT_GET_LINK_INFO_FC_TX, FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); out: if (status == IXGBE_SUCCESS) { hw->fc.fc_was_autonegged = TRUE; } else { hw->fc.fc_was_autonegged = FALSE; hw->fc.current_mode = hw->fc.requested_mode; } } /** * ixgbe_setup_fc_backplane_x550em_a - Set up flow control * @hw: pointer to hardware structure * * Called at init time to set up flow control. **/ s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) { s32 status = IXGBE_SUCCESS; u32 an_cntl = 0; DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a"); /* Validate the requested mode */ if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); return IXGBE_ERR_INVALID_LINK_SETTINGS; } if (hw->fc.requested_mode == ixgbe_fc_default) hw->fc.requested_mode = ixgbe_fc_full; /* Set up the 1G and 10G flow control advertisement registers so the * HW will be able to do FC autoneg once the cable is plugged in. If * we link at 10G, the 1G advertisement is harmless and vice versa. */ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); if (status != IXGBE_SUCCESS) { DEBUGOUT("Auto-Negotiation did not complete\n"); return status; } /* The possible values of fc.requested_mode are: * 0: Flow control is completely disabled * 1: Rx flow control is enabled (we can receive pause frames, * but not send pause frames). * 2: Tx flow control is enabled (we can send pause frames but * we do not support receiving pause frames). * 3: Both Rx and Tx flow control (symmetric) are enabled. * other: Invalid. */ switch (hw->fc.requested_mode) { case ixgbe_fc_none: /* Flow control completely disabled by software override. */ an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); break; case ixgbe_fc_tx_pause: /* Tx Flow control is enabled, and Rx Flow control is * disabled by software override. */ an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; break; case ixgbe_fc_rx_pause: /* Rx Flow control is enabled and Tx Flow control is * disabled by software override. Since there really * isn't a way to advertise that we are capable of RX * Pause ONLY, we will advertise that we support both * symmetric and asymmetric Rx PAUSE, as such we fall * through to the fc_full statement. Later, we will * disable the adapter's ability to send PAUSE frames. */ case ixgbe_fc_full: /* Flow control (both Rx and Tx) is enabled by SW override. */ an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; break; default: ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Flow control param set incorrectly\n"); return IXGBE_ERR_CONFIG; } status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); /* Restart auto-negotiation. */ status = ixgbe_restart_an_internal_phy_x550em(hw); return status; } /** * ixgbe_set_mux - Set mux for port 1 access with CS4227 * @hw: pointer to hardware structure * @state: set mux if 1, clear if 0 */ static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) { u32 esdp; if (!hw->bus.lan_id) return; esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); if (state) esdp |= IXGBE_ESDP_SDP1; else esdp &= ~IXGBE_ESDP_SDP1; IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); IXGBE_WRITE_FLUSH(hw); } /** * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore * @hw: pointer to hardware structure * @mask: Mask to specify which semaphore to acquire * * Acquires the SWFW semaphore and sets the I2C MUX **/ s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) { s32 status; DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em"); status = ixgbe_acquire_swfw_sync_X540(hw, mask); if (status) return status; if (mask & IXGBE_GSSR_I2C_MASK) ixgbe_set_mux(hw, 1); return IXGBE_SUCCESS; } /** * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore * @hw: pointer to hardware structure * @mask: Mask to specify which semaphore to release * * Releases the SWFW semaphore and sets the I2C MUX **/ void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) { DEBUGFUNC("ixgbe_release_swfw_sync_X550em"); if (mask & IXGBE_GSSR_I2C_MASK) ixgbe_set_mux(hw, 0); ixgbe_release_swfw_sync_X540(hw, mask); } /** * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore * @hw: pointer to hardware structure * @mask: Mask to specify which semaphore to acquire * * Acquires the SWFW semaphore and get the shared phy token as needed */ static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) { u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; int retries = FW_PHY_TOKEN_RETRIES; s32 status = IXGBE_SUCCESS; DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a"); while (--retries) { status = IXGBE_SUCCESS; if (hmask) status = ixgbe_acquire_swfw_sync_X540(hw, hmask); if (status) { DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n", status); return status; } if (!(mask & IXGBE_GSSR_TOKEN_SM)) return IXGBE_SUCCESS; status = ixgbe_get_phy_token(hw); if (status == IXGBE_ERR_TOKEN_RETRY) DEBUGOUT1("Could not acquire PHY token, Status = %d\n", status); if (status == IXGBE_SUCCESS) return IXGBE_SUCCESS; if (hmask) ixgbe_release_swfw_sync_X540(hw, hmask); if (status != IXGBE_ERR_TOKEN_RETRY) { DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n", status); return status; } } DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n", hw->phy.id); return status; } /** * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore * @hw: pointer to hardware structure * @mask: Mask to specify which semaphore to release * * Releases the SWFW semaphore and puts the shared phy token as needed */ static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) { u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; DEBUGFUNC("ixgbe_release_swfw_sync_X550a"); if (mask & IXGBE_GSSR_TOKEN_SM) ixgbe_put_phy_token(hw); if (hmask) ixgbe_release_swfw_sync_X540(hw, hmask); } /** * ixgbe_read_phy_reg_x550a - Reads specified PHY register * @hw: pointer to hardware structure * @reg_addr: 32 bit address of PHY register to read * @device_type: 5 bit device type * @phy_data: Pointer to read data from PHY register * * Reads a value from a specified PHY register using the SWFW lock and PHY * Token. The PHY Token is needed since the MDIO is shared between to MAC * instances. **/ s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data) { s32 status; u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; DEBUGFUNC("ixgbe_read_phy_reg_x550a"); if (hw->mac.ops.acquire_swfw_sync(hw, mask)) return IXGBE_ERR_SWFW_SYNC; status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); hw->mac.ops.release_swfw_sync(hw, mask); return status; } /** * ixgbe_write_phy_reg_x550a - Writes specified PHY register * @hw: pointer to hardware structure * @reg_addr: 32 bit PHY register to write * @device_type: 5 bit device type * @phy_data: Data to write to the PHY register * * Writes a value to specified PHY register using the SWFW lock and PHY Token. * The PHY Token is needed since the MDIO is shared between to MAC instances. **/ s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data) { s32 status; u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; DEBUGFUNC("ixgbe_write_phy_reg_x550a"); if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) { status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, phy_data); hw->mac.ops.release_swfw_sync(hw, mask); } else { status = IXGBE_ERR_SWFW_SYNC; } return status; } /** * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt * @hw: pointer to hardware structure * * Handle external Base T PHY interrupt. If high temperature * failure alarm then return error, else if link status change * then setup internal/external PHY link * * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature * failure alarm, else return PHY access status. */ s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) { bool lsc; u32 status; status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); if (status != IXGBE_SUCCESS) return status; if (lsc) return ixgbe_setup_internal_phy(hw); return IXGBE_SUCCESS; } /** * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed * @hw: pointer to hardware structure * @speed: new link speed * @autoneg_wait_to_complete: TRUE when waiting for completion is needed * * Setup internal/external PHY link speed based on link speed, then set * external PHY auto advertised link speed. * * Returns error status for any failure **/ s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete) { s32 status; ixgbe_link_speed force_speed; u32 i; bool link_up = false; DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); /* Setup internal/external PHY link speed to iXFI (10G), unless * only 1G is auto advertised then setup KX link. */ if (speed & IXGBE_LINK_SPEED_10GB_FULL) force_speed = IXGBE_LINK_SPEED_10GB_FULL; else force_speed = IXGBE_LINK_SPEED_1GB_FULL; /* If X552 and internal link mode is XFI, then setup XFI internal link. */ if (hw->mac.type == ixgbe_mac_X550EM_x && !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { status = ixgbe_setup_ixfi_x550em(hw, &force_speed); if (status != IXGBE_SUCCESS) return status; /* Wait for the controller to acquire link */ for (i = 0; i < 10; i++) { msec_delay(100); status = ixgbe_check_link(hw, &force_speed, &link_up, false); if (status != IXGBE_SUCCESS) return status; if (link_up) break; } } return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); } /** * ixgbe_check_link_t_X550em - Determine link and speed status * @hw: pointer to hardware structure * @speed: pointer to link speed * @link_up: TRUE when link is up * @link_up_wait_to_complete: bool used to wait for link up or not * * Check that both the MAC and X557 external PHY have link. **/ s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete) { u32 status; u16 i, autoneg_status = 0; if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) return IXGBE_ERR_CONFIG; status = ixgbe_check_mac_link_generic(hw, speed, link_up, link_up_wait_to_complete); /* If check link fails or MAC link is not up, then return */ if (status != IXGBE_SUCCESS || !(*link_up)) return status; /* MAC link is up, so check external PHY link. * X557 PHY. Link status is latching low, and can only be used to detect * link drop, and not the current status of the link without performing * back-to-back reads. */ for (i = 0; i < 2; i++) { status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_status); if (status != IXGBE_SUCCESS) return status; } /* If external PHY link is not up, then indicate link not up */ if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) *link_up = FALSE; return IXGBE_SUCCESS; } /** * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI * @hw: pointer to hardware structure **/ s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) { s32 status; status = ixgbe_reset_phy_generic(hw); if (status != IXGBE_SUCCESS) return status; /* Configure Link Status Alarm and Temperature Threshold interrupts */ return ixgbe_enable_lasi_ext_t_x550em(hw); } /** * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs. * @hw: pointer to hardware structure * @led_idx: led number to turn on **/ s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx) { u16 phy_data; DEBUGFUNC("ixgbe_led_on_t_X550em"); if (led_idx >= IXGBE_X557_MAX_LED_INDEX) return IXGBE_ERR_PARAM; /* To turn on the LED, set mode to ON. */ ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); /* Some designs have the LEDs wired to the MAC */ return ixgbe_led_on_generic(hw, led_idx); } /** * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs. * @hw: pointer to hardware structure * @led_idx: led number to turn off **/ s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx) { u16 phy_data; DEBUGFUNC("ixgbe_led_off_t_X550em"); if (led_idx >= IXGBE_X557_MAX_LED_INDEX) return IXGBE_ERR_PARAM; /* To turn on the LED, set mode to ON. */ ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); /* Some designs have the LEDs wired to the MAC */ return ixgbe_led_off_generic(hw, led_idx); } /** * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware * @hw: pointer to the HW structure * @maj: driver version major number * @min: driver version minor number * @build: driver version build number * @sub: driver version sub build number * @len: length of driver_ver string * @driver_ver: driver string * * Sends driver version number to firmware through the manageability * block. On success return IXGBE_SUCCESS * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. **/ s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, u8 sub, u16 len, const char *driver_ver) { struct ixgbe_hic_drv_info2 fw_cmd; s32 ret_val = IXGBE_SUCCESS; int i; DEBUGFUNC("ixgbe_set_fw_drv_ver_x550"); if ((len == 0) || (driver_ver == NULL) || (len > sizeof(fw_cmd.driver_string))) return IXGBE_ERR_INVALID_ARGUMENT; fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; fw_cmd.port_num = (u8)hw->bus.func; fw_cmd.ver_maj = maj; fw_cmd.ver_min = min; fw_cmd.ver_build = build; fw_cmd.ver_sub = sub; fw_cmd.hdr.checksum = 0; memcpy(fw_cmd.driver_string, driver_ver, len); fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, sizeof(fw_cmd), IXGBE_HI_COMMAND_TIMEOUT, TRUE); if (ret_val != IXGBE_SUCCESS) continue; if (fw_cmd.hdr.cmd_or_resp.ret_status == FW_CEM_RESP_STATUS_SUCCESS) ret_val = IXGBE_SUCCESS; else ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; break; } return ret_val; }