diff --git a/sys/amd64/isa/icu.h b/sys/amd64/isa/icu.h index b5f2de4356d8..6423551784f5 100644 --- a/sys/amd64/isa/icu.h +++ b/sys/amd64/isa/icu.h @@ -1,128 +1,128 @@ /*- * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)icu.h 5.6 (Berkeley) 5/9/91 * $FreeBSD$ */ /* * AT/386 Interrupt Control constants * W. Jolitz 8/89 */ #ifndef _I386_ISA_ICU_H_ #define _I386_ISA_ICU_H_ #ifndef LOCORE /* #define MP_SAFE * Note: * Most of the SMP equivilants of the icu macros are coded * elsewhere in an MP-safe fashion. * In particular note that the 'imen' variable is opaque. * DO NOT access imen directly, use INTREN()/INTRDIS(). */ void INTREN __P((u_int)); void INTRDIS __P((u_int)); #ifdef APIC_IO extern unsigned apic_imen; /* APIC interrupt mask enable */ #define APIC_IMEN_BITS 32 /* number of bits in apic_imen */ #else extern unsigned imen; /* interrupt mask enable */ #define IMEN_BITS 16 /* number of bits in imen */ #endif #endif /* LOCORE */ #ifdef APIC_IO /* * Note: The APIC uses different values for IRQxxx. * Unfortunately many drivers use the 8259 values as indexes * into tables, etc. The APIC equivilants are kept as APIC_IRQxxx. * The 8259 versions have to be used in SMP for legacy operation * of the drivers. */ #endif /* APIC_IO */ /* * Interrupt enable bits - in normal order of priority (which we change) */ #define IRQ0 0x0001 /* highest priority - timer */ #define IRQ1 0x0002 #define IRQ_SLAVE 0x0004 #define IRQ8 0x0100 #define IRQ9 0x0200 #define IRQ2 IRQ9 #define IRQ10 0x0400 #define IRQ11 0x0800 #define IRQ12 0x1000 #define IRQ13 0x2000 #define IRQ14 0x4000 #define IRQ15 0x8000 #define IRQ3 0x0008 /* this is highest after rotation */ #define IRQ4 0x0010 #define IRQ5 0x0020 #define IRQ6 0x0040 #define IRQ7 0x0080 /* lowest - parallel printer */ #ifdef PC98 #undef IRQ2 #define IRQ2 0x0004 #undef IRQ_SLAVE #define IRQ_SLAVE 0x0080 #endif /* * Interrupt Control offset into Interrupt descriptor table (IDT) */ #define ICU_OFFSET 32 /* 0-31 are processor exceptions */ #ifdef APIC_IO -/* 32-47: ISA IRQ0-IRQ15, 48-55: IO APIC IRQ16-IRQ23 */ -#define ICU_LEN 24 +/* 32-47: ISA IRQ0-IRQ15, 48-55: IO APIC IRQ16-IRQ31 */ +#define ICU_LEN 32 #else #define ICU_LEN 16 /* 32-47 are ISA interrupts */ #endif /* APIC_IO */ #endif /* !_I386_ISA_ICU_H_ */ diff --git a/sys/amd64/isa/intr_machdep.c b/sys/amd64/isa/intr_machdep.c index 5a669d237caa..00f5f23d359f 100644 --- a/sys/amd64/isa/intr_machdep.c +++ b/sys/amd64/isa/intr_machdep.c @@ -1,715 +1,721 @@ /*- * Copyright (c) 1991 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 * $FreeBSD$ */ #include "opt_auto_eoi.h" #include "isa.h" #include #include #ifndef SMP #include #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(APIC_IO) #include /** FAST_HI */ #include #include #endif /* APIC_IO */ #ifdef PC98 #include #include #include #else #include #endif #include #if NISA > 0 #include #endif #include #include #ifdef APIC_IO #include #endif #include "mca.h" #if NMCA > 0 #include #endif /* * Per-interrupt data. */ u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */ driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */ struct ithd *ithds[ICU_LEN]; /* real interrupt handler */ void *intr_unit[ICU_LEN]; static inthand_t *fastintr[ICU_LEN] = { &IDTVEC(fastintr0), &IDTVEC(fastintr1), &IDTVEC(fastintr2), &IDTVEC(fastintr3), &IDTVEC(fastintr4), &IDTVEC(fastintr5), &IDTVEC(fastintr6), &IDTVEC(fastintr7), &IDTVEC(fastintr8), &IDTVEC(fastintr9), &IDTVEC(fastintr10), &IDTVEC(fastintr11), &IDTVEC(fastintr12), &IDTVEC(fastintr13), &IDTVEC(fastintr14), &IDTVEC(fastintr15), #if defined(APIC_IO) &IDTVEC(fastintr16), &IDTVEC(fastintr17), &IDTVEC(fastintr18), &IDTVEC(fastintr19), &IDTVEC(fastintr20), &IDTVEC(fastintr21), &IDTVEC(fastintr22), &IDTVEC(fastintr23), + &IDTVEC(fastintr24), &IDTVEC(fastintr25), + &IDTVEC(fastintr26), &IDTVEC(fastintr27), + &IDTVEC(fastintr28), &IDTVEC(fastintr29), + &IDTVEC(fastintr30), &IDTVEC(fastintr31), #endif /* APIC_IO */ }; static inthand_t *slowintr[ICU_LEN] = { &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3), &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7), &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11), &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15), #if defined(APIC_IO) &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19), &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23), + &IDTVEC(intr24), &IDTVEC(intr25), &IDTVEC(intr26), &IDTVEC(intr27), + &IDTVEC(intr28), &IDTVEC(intr29), &IDTVEC(intr30), &IDTVEC(intr31), #endif /* APIC_IO */ }; static driver_intr_t isa_strayintr; #ifdef PC98 #define NMI_PARITY 0x04 #define NMI_EPARITY 0x02 #else #define NMI_PARITY (1 << 7) #define NMI_IOCHAN (1 << 6) #define ENMI_WATCHDOG (1 << 7) #define ENMI_BUSTIMER (1 << 6) #define ENMI_IOSTATUS (1 << 5) #endif /* * Bus attachment for the ISA PIC. */ static struct isa_pnp_id atpic_ids[] = { { 0x0000d041 /* PNP0000 */, "AT interrupt controller" }, { 0 } }; static int atpic_probe(device_t dev) { int result; if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0) device_quiet(dev); return(result); } /* * In the APIC_IO case we might be granted IRQ 2, as this is typically * consumed by chaining between the two PIC components. If we're using * the APIC, however, this may not be the case, and as such we should * free the resource. (XXX untested) * * The generic ISA attachment code will handle allocating any other resources * that we don't explicitly claim here. */ static int atpic_attach(device_t dev) { #ifdef APIC_IO int rid; struct resource *res; /* try to allocate our IRQ and then free it */ rid = 0; res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0); if (res != NULL) bus_release_resource(dev, SYS_RES_IRQ, rid, res); #endif return(0); } static device_method_t atpic_methods[] = { /* Device interface */ DEVMETHOD(device_probe, atpic_probe), DEVMETHOD(device_attach, atpic_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), { 0, 0 } }; static driver_t atpic_driver = { "atpic", atpic_methods, 1, /* no softc */ }; static devclass_t atpic_devclass; DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0); /* * Handle a NMI, possibly a machine check. * return true to panic system, false to ignore. */ int isa_nmi(cd) int cd; { int retval = 0; #ifdef PC98 int port = inb(0x33); log(LOG_CRIT, "NMI PC98 port = %x\n", port); if (epson_machine_id == 0x20) epson_outb(0xc16, epson_inb(0xc16) | 0x1); if (port & NMI_PARITY) { log(LOG_CRIT, "BASE RAM parity error, likely hardware failure."); retval = 1; } else if (port & NMI_EPARITY) { log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure."); retval = 1; } else { log(LOG_CRIT, "\nNMI Resume ??\n"); } #else /* IBM-PC */ int isa_port = inb(0x61); int eisa_port = inb(0x461); log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port); #if NMCA > 0 if (MCA_system && mca_bus_nmi()) return(0); #endif if (isa_port & NMI_PARITY) { log(LOG_CRIT, "RAM parity error, likely hardware failure."); retval = 1; } if (isa_port & NMI_IOCHAN) { log(LOG_CRIT, "I/O channel check, likely hardware failure."); retval = 1; } /* * On a real EISA machine, this will never happen. However it can * happen on ISA machines which implement XT style floating point * error handling (very rare). Save them from a meaningless panic. */ if (eisa_port == 0xff) return(retval); if (eisa_port & ENMI_WATCHDOG) { log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure."); retval = 1; } if (eisa_port & ENMI_BUSTIMER) { log(LOG_CRIT, "EISA bus timeout, likely hardware failure."); retval = 1; } if (eisa_port & ENMI_IOSTATUS) { log(LOG_CRIT, "EISA I/O port status error."); retval = 1; } #endif return(retval); } /* * Create a default interrupt table to avoid problems caused by * spurious interrupts during configuration of kernel, then setup * interrupt control unit. */ void isa_defaultirq() { int i; /* icu vectors */ for (i = 0; i < ICU_LEN; i++) icu_unset(i, (driver_intr_t *)NULL); /* initialize 8259's */ #if NMCA > 0 if (MCA_system) outb(IO_ICU1, 0x19); /* reset; program device, four bytes */ else #endif outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */ outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */ #ifdef PC98 #ifdef AUTO_EOI_1 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */ #else outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */ #endif #else /* IBM-PC */ #ifdef AUTO_EOI_1 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ #else outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */ #endif #endif /* PC98 */ outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ outb(IO_ICU1, 0x0a); /* default to IRR on read */ #ifndef PC98 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ #endif /* !PC98 */ #if NMCA > 0 if (MCA_system) outb(IO_ICU2, 0x19); /* reset; program device, four bytes */ else #endif outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */ outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */ #ifdef PC98 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */ #else /* IBM-PC */ #ifdef AUTO_EOI_2 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ #else outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */ #endif #endif /* PC98 */ outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ outb(IO_ICU2, 0x0a); /* default to IRR on read */ } /* * Caught a stray interrupt, notify */ static void isa_strayintr(vcookiep) void *vcookiep; { int intr = (void **)vcookiep - &intr_unit[0]; /* * XXX TODO print a different message for #7 if it is for a * glitch. Glitches can be distinguished from real #7's by * testing that the in-service bit is _not_ set. The test * must be done before sending an EOI so it can't be done if * we are using AUTO_EOI_1. */ if (intrcnt[1 + intr] <= 5) log(LOG_ERR, "stray irq %d\n", intr); if (intrcnt[1 + intr] == 5) log(LOG_CRIT, "too many stray irq %d's; not logging any more\n", intr); } #if NISA > 0 /* * Return a bitmap of the current interrupt requests. This is 8259-specific * and is only suitable for use at probe time. */ intrmask_t isa_irq_pending() { u_char irr1; u_char irr2; irr1 = inb(IO_ICU1); irr2 = inb(IO_ICU2); return ((irr2 << 8) | irr1); } #endif /* * Update intrnames array with the specified name. This is used by * vmstat(8) and the like. */ static void update_intrname(int intr, char *name) { char buf[32]; char *cp; int name_index, off, strayintr; /* * Initialise strings for bitbucket and stray interrupt counters. * These have statically allocated indices 0 and 1 through ICU_LEN. */ if (intrnames[0] == '\0') { off = sprintf(intrnames, "???") + 1; for (strayintr = 0; strayintr < ICU_LEN; strayintr++) off += sprintf(intrnames + off, "stray irq%d", strayintr) + 1; } if (name == NULL) name = "???"; if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf)) goto use_bitbucket; /* * Search for `buf' in `intrnames'. In the usual case when it is * not found, append it to the end if there is enough space (the \0 * terminator for the previous string, if any, becomes a separator). */ for (cp = intrnames, name_index = 0; cp != eintrnames && name_index < NR_INTRNAMES; cp += strlen(cp) + 1, name_index++) { if (*cp == '\0') { if (strlen(buf) >= eintrnames - cp) break; strcpy(cp, buf); goto found; } if (strcmp(cp, buf) == 0) goto found; } use_bitbucket: printf("update_intrname: counting %s irq%d as %s\n", name, intr, intrnames); name_index = 0; found: intr_countp[intr] = &intrcnt[name_index]; } int icu_setup(int intr, driver_intr_t *handler, void *arg, int flags) { #ifdef FAST_HI int select; /* the select register is 8 bits */ int vector; u_int32_t value; /* the window register is 32 bits */ #endif /* FAST_HI */ u_long ef; #if defined(APIC_IO) if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */ #else if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID) #endif /* APIC_IO */ if (intr_handler[intr] != isa_strayintr) return (EBUSY); ef = read_eflags(); disable_intr(); intr_handler[intr] = handler; intr_unit[intr] = arg; #ifdef FAST_HI if (flags & INTR_FAST) { vector = TPR_FAST_INTS + intr; setidt(vector, fastintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); } else { vector = TPR_SLOW_INTS + intr; #ifdef APIC_INTR_REORDER #ifdef APIC_INTR_HIGHPRI_CLOCK /* XXX: Hack (kludge?) for more accurate clock. */ if (intr == apic_8254_intr || intr == 8) { vector = TPR_FAST_INTS + intr; } #endif #endif setidt(vector, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); } #ifdef APIC_INTR_REORDER set_lapic_isrloc(intr, vector); #endif /* * Reprogram the vector in the IO APIC. */ if (int_to_apicintpin[intr].ioapic >= 0) { select = int_to_apicintpin[intr].redirindex; value = io_apic_read(int_to_apicintpin[intr].ioapic, select) & ~IOART_INTVEC; io_apic_write(int_to_apicintpin[intr].ioapic, select, value | vector); } #else setidt(ICU_OFFSET + intr, flags & INTR_FAST ? fastintr[intr] : slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /* FAST_HI */ INTREN(1 << intr); write_eflags(ef); return (0); } /* * Dissociate an interrupt handler from an IRQ and set the handler to * the stray interrupt handler. The 'handler' parameter is used only * for consistency checking. */ int icu_unset(intr, handler) int intr; driver_intr_t *handler; { u_long ef; if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr]) return (EINVAL); INTRDIS(1 << intr); ef = read_eflags(); disable_intr(); intr_countp[intr] = &intrcnt[1 + intr]; intr_handler[intr] = isa_strayintr; intr_unit[intr] = &intr_unit[intr]; #ifdef FAST_HI_XXX /* XXX how do I re-create dvp here? */ setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #else /* FAST_HI */ #ifdef APIC_INTR_REORDER set_lapic_isrloc(intr, ICU_OFFSET + intr); #endif setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /* FAST_HI */ write_eflags(ef); return (0); } struct intrhand * inthand_add(const char *name, int irq, driver_intr_t handler, void *arg, int pri, int flags) { struct ithd *ithd = ithds[irq]; /* descriptor for the IRQ */ struct intrhand *head; /* chain of handlers for IRQ */ struct intrhand *idesc; /* descriptor for this handler */ struct proc *p; /* interrupt thread */ int errcode = 0; if (name == NULL) /* no name? */ panic ("anonymous interrupt"); if (ithd == NULL || ithd->it_ih == NULL) { /* first handler for this irq. */ if (ithd == NULL) { ithd = malloc(sizeof (struct ithd), M_DEVBUF, M_WAITOK | M_ZERO); if (ithd == NULL) return (NULL); ithd->irq = irq; ithds[irq] = ithd; } /* * If we have a fast interrupt, we need to set the * handler address directly. Do that below. For a * slow interrupt, we don't need to know more details, * so do it here because it's tidier. */ if ((flags & INTR_FAST) == 0) { /* * Only create a kernel thread if we don't already * have one. */ if (ithd->it_proc == NULL) { errcode = kthread_create(ithd_loop, NULL, &p, RFSTOPPED | RFHIGHPID, "irq%d: %s", irq, name); if (errcode) panic("inthand_add: Can't create " "interrupt thread"); p->p_rtprio.type = RTP_PRIO_ITHREAD; p->p_stat = SWAIT; /* we're idle */ /* Put in linkages. */ ithd->it_proc = p; p->p_ithd = ithd; } else snprintf(ithd->it_proc->p_comm, MAXCOMLEN, "irq%d: %s", irq, name); p->p_rtprio.prio = pri; /* * The interrupt process must be in place, but * not necessarily schedulable, before we * initialize the ICU, since it may cause an * immediate interrupt. */ if (icu_setup(irq, &sched_ithd, arg, flags) != 0) panic("inthand_add: Can't initialize ICU"); } } else if ((flags & INTR_EXCL) != 0 || (ithd->it_ih->ih_flags & INTR_EXCL) != 0) { /* * We can't append the new handler if either * list ithd or new handler do not allow * interrupts to be shared. */ if (bootverbose) printf("\tdevice combination %s and %s " "doesn't support shared irq%d\n", ithd->it_ih->ih_name, name, irq); return(NULL); } else if (flags & INTR_FAST) { /* We can only have one fast interrupt by itself. */ if (bootverbose) printf("\tCan't add fast interrupt %s" " to normal interrupt %s on irq%d", name, ithd->it_ih->ih_name, irq); return (NULL); } else { /* update p_comm */ p = ithd->it_proc; if (strlen(p->p_comm) + strlen(name) < MAXCOMLEN) { strcat(p->p_comm, " "); strcat(p->p_comm, name); } else if (strlen(p->p_comm) == MAXCOMLEN) p->p_comm[MAXCOMLEN - 1] = '+'; else strcat(p->p_comm, "+"); } idesc = malloc(sizeof (struct intrhand), M_DEVBUF, M_WAITOK | M_ZERO); if (idesc == NULL) return (NULL); idesc->ih_handler = handler; idesc->ih_argument = arg; idesc->ih_flags = flags; idesc->ih_ithd = ithd; idesc->ih_name = malloc(strlen(name) + 1, M_DEVBUF, M_WAITOK); if (idesc->ih_name == NULL) { free(idesc, M_DEVBUF); return (NULL); } strcpy(idesc->ih_name, name); /* Slow interrupts got set up above. */ if ((flags & INTR_FAST) && (icu_setup(irq, idesc->ih_handler, idesc->ih_argument, idesc->ih_flags) != 0) ) { if (bootverbose) printf("\tinthand_add(irq%d) failed, result=%d\n", irq, errcode); free(idesc->ih_name, M_DEVBUF); free(idesc, M_DEVBUF); return NULL; } head = ithd->it_ih; /* look at chain of handlers */ if (head) { while (head->ih_next != NULL) head = head->ih_next; /* find the end */ head->ih_next = idesc; /* hook it in there */ } else ithd->it_ih = idesc; /* put it up front */ update_intrname(irq, idesc->ih_name); return (idesc); } /* * Deactivate and remove linked list the interrupt handler descriptor * data connected created by an earlier call of inthand_add(), then * adjust the interrupt masks if necessary. * * Return the memory held by the interrupt handler descriptor data * structure to the system. First ensure the handler is not actively * in use. */ int inthand_remove(struct intrhand *idesc) { struct ithd *ithd; /* descriptor for the IRQ */ struct intrhand *ih; /* chain of handlers */ if (idesc == NULL) return (-1); ithd = idesc->ih_ithd; ih = ithd->it_ih; if (ih == idesc) /* first in the chain */ ithd->it_ih = idesc->ih_next; /* unhook it */ else { while ((ih != NULL) && (ih->ih_next != idesc) ) ih = ih->ih_next; if (ih->ih_next != idesc) return (-1); ih->ih_next = ih->ih_next->ih_next; } if (ithd->it_ih == NULL) { /* no handlers left, */ icu_unset(ithd->irq, idesc->ih_handler); ithds[ithd->irq] = NULL; if ((idesc->ih_flags & INTR_FAST) == 0) { mtx_enter(&sched_lock, MTX_SPIN); if (ithd->it_proc->p_stat == SWAIT) { ithd->it_proc->p_stat = SRUN; setrunqueue(ithd->it_proc); /* * We don't do an ast here because we really * don't care when it runs next. * * XXX: should we lower the threads priority? */ } mtx_exit(&sched_lock, MTX_SPIN); } } free(idesc->ih_name, M_DEVBUF); free(idesc, M_DEVBUF); return (0); } diff --git a/sys/amd64/isa/nmi.c b/sys/amd64/isa/nmi.c index 5a669d237caa..00f5f23d359f 100644 --- a/sys/amd64/isa/nmi.c +++ b/sys/amd64/isa/nmi.c @@ -1,715 +1,721 @@ /*- * Copyright (c) 1991 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 * $FreeBSD$ */ #include "opt_auto_eoi.h" #include "isa.h" #include #include #ifndef SMP #include #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(APIC_IO) #include /** FAST_HI */ #include #include #endif /* APIC_IO */ #ifdef PC98 #include #include #include #else #include #endif #include #if NISA > 0 #include #endif #include #include #ifdef APIC_IO #include #endif #include "mca.h" #if NMCA > 0 #include #endif /* * Per-interrupt data. */ u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */ driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */ struct ithd *ithds[ICU_LEN]; /* real interrupt handler */ void *intr_unit[ICU_LEN]; static inthand_t *fastintr[ICU_LEN] = { &IDTVEC(fastintr0), &IDTVEC(fastintr1), &IDTVEC(fastintr2), &IDTVEC(fastintr3), &IDTVEC(fastintr4), &IDTVEC(fastintr5), &IDTVEC(fastintr6), &IDTVEC(fastintr7), &IDTVEC(fastintr8), &IDTVEC(fastintr9), &IDTVEC(fastintr10), &IDTVEC(fastintr11), &IDTVEC(fastintr12), &IDTVEC(fastintr13), &IDTVEC(fastintr14), &IDTVEC(fastintr15), #if defined(APIC_IO) &IDTVEC(fastintr16), &IDTVEC(fastintr17), &IDTVEC(fastintr18), &IDTVEC(fastintr19), &IDTVEC(fastintr20), &IDTVEC(fastintr21), &IDTVEC(fastintr22), &IDTVEC(fastintr23), + &IDTVEC(fastintr24), &IDTVEC(fastintr25), + &IDTVEC(fastintr26), &IDTVEC(fastintr27), + &IDTVEC(fastintr28), &IDTVEC(fastintr29), + &IDTVEC(fastintr30), &IDTVEC(fastintr31), #endif /* APIC_IO */ }; static inthand_t *slowintr[ICU_LEN] = { &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3), &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7), &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11), &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15), #if defined(APIC_IO) &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19), &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23), + &IDTVEC(intr24), &IDTVEC(intr25), &IDTVEC(intr26), &IDTVEC(intr27), + &IDTVEC(intr28), &IDTVEC(intr29), &IDTVEC(intr30), &IDTVEC(intr31), #endif /* APIC_IO */ }; static driver_intr_t isa_strayintr; #ifdef PC98 #define NMI_PARITY 0x04 #define NMI_EPARITY 0x02 #else #define NMI_PARITY (1 << 7) #define NMI_IOCHAN (1 << 6) #define ENMI_WATCHDOG (1 << 7) #define ENMI_BUSTIMER (1 << 6) #define ENMI_IOSTATUS (1 << 5) #endif /* * Bus attachment for the ISA PIC. */ static struct isa_pnp_id atpic_ids[] = { { 0x0000d041 /* PNP0000 */, "AT interrupt controller" }, { 0 } }; static int atpic_probe(device_t dev) { int result; if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0) device_quiet(dev); return(result); } /* * In the APIC_IO case we might be granted IRQ 2, as this is typically * consumed by chaining between the two PIC components. If we're using * the APIC, however, this may not be the case, and as such we should * free the resource. (XXX untested) * * The generic ISA attachment code will handle allocating any other resources * that we don't explicitly claim here. */ static int atpic_attach(device_t dev) { #ifdef APIC_IO int rid; struct resource *res; /* try to allocate our IRQ and then free it */ rid = 0; res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0); if (res != NULL) bus_release_resource(dev, SYS_RES_IRQ, rid, res); #endif return(0); } static device_method_t atpic_methods[] = { /* Device interface */ DEVMETHOD(device_probe, atpic_probe), DEVMETHOD(device_attach, atpic_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), { 0, 0 } }; static driver_t atpic_driver = { "atpic", atpic_methods, 1, /* no softc */ }; static devclass_t atpic_devclass; DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0); /* * Handle a NMI, possibly a machine check. * return true to panic system, false to ignore. */ int isa_nmi(cd) int cd; { int retval = 0; #ifdef PC98 int port = inb(0x33); log(LOG_CRIT, "NMI PC98 port = %x\n", port); if (epson_machine_id == 0x20) epson_outb(0xc16, epson_inb(0xc16) | 0x1); if (port & NMI_PARITY) { log(LOG_CRIT, "BASE RAM parity error, likely hardware failure."); retval = 1; } else if (port & NMI_EPARITY) { log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure."); retval = 1; } else { log(LOG_CRIT, "\nNMI Resume ??\n"); } #else /* IBM-PC */ int isa_port = inb(0x61); int eisa_port = inb(0x461); log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port); #if NMCA > 0 if (MCA_system && mca_bus_nmi()) return(0); #endif if (isa_port & NMI_PARITY) { log(LOG_CRIT, "RAM parity error, likely hardware failure."); retval = 1; } if (isa_port & NMI_IOCHAN) { log(LOG_CRIT, "I/O channel check, likely hardware failure."); retval = 1; } /* * On a real EISA machine, this will never happen. However it can * happen on ISA machines which implement XT style floating point * error handling (very rare). Save them from a meaningless panic. */ if (eisa_port == 0xff) return(retval); if (eisa_port & ENMI_WATCHDOG) { log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure."); retval = 1; } if (eisa_port & ENMI_BUSTIMER) { log(LOG_CRIT, "EISA bus timeout, likely hardware failure."); retval = 1; } if (eisa_port & ENMI_IOSTATUS) { log(LOG_CRIT, "EISA I/O port status error."); retval = 1; } #endif return(retval); } /* * Create a default interrupt table to avoid problems caused by * spurious interrupts during configuration of kernel, then setup * interrupt control unit. */ void isa_defaultirq() { int i; /* icu vectors */ for (i = 0; i < ICU_LEN; i++) icu_unset(i, (driver_intr_t *)NULL); /* initialize 8259's */ #if NMCA > 0 if (MCA_system) outb(IO_ICU1, 0x19); /* reset; program device, four bytes */ else #endif outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */ outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */ #ifdef PC98 #ifdef AUTO_EOI_1 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */ #else outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */ #endif #else /* IBM-PC */ #ifdef AUTO_EOI_1 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ #else outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */ #endif #endif /* PC98 */ outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ outb(IO_ICU1, 0x0a); /* default to IRR on read */ #ifndef PC98 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ #endif /* !PC98 */ #if NMCA > 0 if (MCA_system) outb(IO_ICU2, 0x19); /* reset; program device, four bytes */ else #endif outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */ outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */ #ifdef PC98 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */ #else /* IBM-PC */ #ifdef AUTO_EOI_2 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ #else outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */ #endif #endif /* PC98 */ outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ outb(IO_ICU2, 0x0a); /* default to IRR on read */ } /* * Caught a stray interrupt, notify */ static void isa_strayintr(vcookiep) void *vcookiep; { int intr = (void **)vcookiep - &intr_unit[0]; /* * XXX TODO print a different message for #7 if it is for a * glitch. Glitches can be distinguished from real #7's by * testing that the in-service bit is _not_ set. The test * must be done before sending an EOI so it can't be done if * we are using AUTO_EOI_1. */ if (intrcnt[1 + intr] <= 5) log(LOG_ERR, "stray irq %d\n", intr); if (intrcnt[1 + intr] == 5) log(LOG_CRIT, "too many stray irq %d's; not logging any more\n", intr); } #if NISA > 0 /* * Return a bitmap of the current interrupt requests. This is 8259-specific * and is only suitable for use at probe time. */ intrmask_t isa_irq_pending() { u_char irr1; u_char irr2; irr1 = inb(IO_ICU1); irr2 = inb(IO_ICU2); return ((irr2 << 8) | irr1); } #endif /* * Update intrnames array with the specified name. This is used by * vmstat(8) and the like. */ static void update_intrname(int intr, char *name) { char buf[32]; char *cp; int name_index, off, strayintr; /* * Initialise strings for bitbucket and stray interrupt counters. * These have statically allocated indices 0 and 1 through ICU_LEN. */ if (intrnames[0] == '\0') { off = sprintf(intrnames, "???") + 1; for (strayintr = 0; strayintr < ICU_LEN; strayintr++) off += sprintf(intrnames + off, "stray irq%d", strayintr) + 1; } if (name == NULL) name = "???"; if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf)) goto use_bitbucket; /* * Search for `buf' in `intrnames'. In the usual case when it is * not found, append it to the end if there is enough space (the \0 * terminator for the previous string, if any, becomes a separator). */ for (cp = intrnames, name_index = 0; cp != eintrnames && name_index < NR_INTRNAMES; cp += strlen(cp) + 1, name_index++) { if (*cp == '\0') { if (strlen(buf) >= eintrnames - cp) break; strcpy(cp, buf); goto found; } if (strcmp(cp, buf) == 0) goto found; } use_bitbucket: printf("update_intrname: counting %s irq%d as %s\n", name, intr, intrnames); name_index = 0; found: intr_countp[intr] = &intrcnt[name_index]; } int icu_setup(int intr, driver_intr_t *handler, void *arg, int flags) { #ifdef FAST_HI int select; /* the select register is 8 bits */ int vector; u_int32_t value; /* the window register is 32 bits */ #endif /* FAST_HI */ u_long ef; #if defined(APIC_IO) if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */ #else if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID) #endif /* APIC_IO */ if (intr_handler[intr] != isa_strayintr) return (EBUSY); ef = read_eflags(); disable_intr(); intr_handler[intr] = handler; intr_unit[intr] = arg; #ifdef FAST_HI if (flags & INTR_FAST) { vector = TPR_FAST_INTS + intr; setidt(vector, fastintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); } else { vector = TPR_SLOW_INTS + intr; #ifdef APIC_INTR_REORDER #ifdef APIC_INTR_HIGHPRI_CLOCK /* XXX: Hack (kludge?) for more accurate clock. */ if (intr == apic_8254_intr || intr == 8) { vector = TPR_FAST_INTS + intr; } #endif #endif setidt(vector, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); } #ifdef APIC_INTR_REORDER set_lapic_isrloc(intr, vector); #endif /* * Reprogram the vector in the IO APIC. */ if (int_to_apicintpin[intr].ioapic >= 0) { select = int_to_apicintpin[intr].redirindex; value = io_apic_read(int_to_apicintpin[intr].ioapic, select) & ~IOART_INTVEC; io_apic_write(int_to_apicintpin[intr].ioapic, select, value | vector); } #else setidt(ICU_OFFSET + intr, flags & INTR_FAST ? fastintr[intr] : slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /* FAST_HI */ INTREN(1 << intr); write_eflags(ef); return (0); } /* * Dissociate an interrupt handler from an IRQ and set the handler to * the stray interrupt handler. The 'handler' parameter is used only * for consistency checking. */ int icu_unset(intr, handler) int intr; driver_intr_t *handler; { u_long ef; if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr]) return (EINVAL); INTRDIS(1 << intr); ef = read_eflags(); disable_intr(); intr_countp[intr] = &intrcnt[1 + intr]; intr_handler[intr] = isa_strayintr; intr_unit[intr] = &intr_unit[intr]; #ifdef FAST_HI_XXX /* XXX how do I re-create dvp here? */ setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #else /* FAST_HI */ #ifdef APIC_INTR_REORDER set_lapic_isrloc(intr, ICU_OFFSET + intr); #endif setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /* FAST_HI */ write_eflags(ef); return (0); } struct intrhand * inthand_add(const char *name, int irq, driver_intr_t handler, void *arg, int pri, int flags) { struct ithd *ithd = ithds[irq]; /* descriptor for the IRQ */ struct intrhand *head; /* chain of handlers for IRQ */ struct intrhand *idesc; /* descriptor for this handler */ struct proc *p; /* interrupt thread */ int errcode = 0; if (name == NULL) /* no name? */ panic ("anonymous interrupt"); if (ithd == NULL || ithd->it_ih == NULL) { /* first handler for this irq. */ if (ithd == NULL) { ithd = malloc(sizeof (struct ithd), M_DEVBUF, M_WAITOK | M_ZERO); if (ithd == NULL) return (NULL); ithd->irq = irq; ithds[irq] = ithd; } /* * If we have a fast interrupt, we need to set the * handler address directly. Do that below. For a * slow interrupt, we don't need to know more details, * so do it here because it's tidier. */ if ((flags & INTR_FAST) == 0) { /* * Only create a kernel thread if we don't already * have one. */ if (ithd->it_proc == NULL) { errcode = kthread_create(ithd_loop, NULL, &p, RFSTOPPED | RFHIGHPID, "irq%d: %s", irq, name); if (errcode) panic("inthand_add: Can't create " "interrupt thread"); p->p_rtprio.type = RTP_PRIO_ITHREAD; p->p_stat = SWAIT; /* we're idle */ /* Put in linkages. */ ithd->it_proc = p; p->p_ithd = ithd; } else snprintf(ithd->it_proc->p_comm, MAXCOMLEN, "irq%d: %s", irq, name); p->p_rtprio.prio = pri; /* * The interrupt process must be in place, but * not necessarily schedulable, before we * initialize the ICU, since it may cause an * immediate interrupt. */ if (icu_setup(irq, &sched_ithd, arg, flags) != 0) panic("inthand_add: Can't initialize ICU"); } } else if ((flags & INTR_EXCL) != 0 || (ithd->it_ih->ih_flags & INTR_EXCL) != 0) { /* * We can't append the new handler if either * list ithd or new handler do not allow * interrupts to be shared. */ if (bootverbose) printf("\tdevice combination %s and %s " "doesn't support shared irq%d\n", ithd->it_ih->ih_name, name, irq); return(NULL); } else if (flags & INTR_FAST) { /* We can only have one fast interrupt by itself. */ if (bootverbose) printf("\tCan't add fast interrupt %s" " to normal interrupt %s on irq%d", name, ithd->it_ih->ih_name, irq); return (NULL); } else { /* update p_comm */ p = ithd->it_proc; if (strlen(p->p_comm) + strlen(name) < MAXCOMLEN) { strcat(p->p_comm, " "); strcat(p->p_comm, name); } else if (strlen(p->p_comm) == MAXCOMLEN) p->p_comm[MAXCOMLEN - 1] = '+'; else strcat(p->p_comm, "+"); } idesc = malloc(sizeof (struct intrhand), M_DEVBUF, M_WAITOK | M_ZERO); if (idesc == NULL) return (NULL); idesc->ih_handler = handler; idesc->ih_argument = arg; idesc->ih_flags = flags; idesc->ih_ithd = ithd; idesc->ih_name = malloc(strlen(name) + 1, M_DEVBUF, M_WAITOK); if (idesc->ih_name == NULL) { free(idesc, M_DEVBUF); return (NULL); } strcpy(idesc->ih_name, name); /* Slow interrupts got set up above. */ if ((flags & INTR_FAST) && (icu_setup(irq, idesc->ih_handler, idesc->ih_argument, idesc->ih_flags) != 0) ) { if (bootverbose) printf("\tinthand_add(irq%d) failed, result=%d\n", irq, errcode); free(idesc->ih_name, M_DEVBUF); free(idesc, M_DEVBUF); return NULL; } head = ithd->it_ih; /* look at chain of handlers */ if (head) { while (head->ih_next != NULL) head = head->ih_next; /* find the end */ head->ih_next = idesc; /* hook it in there */ } else ithd->it_ih = idesc; /* put it up front */ update_intrname(irq, idesc->ih_name); return (idesc); } /* * Deactivate and remove linked list the interrupt handler descriptor * data connected created by an earlier call of inthand_add(), then * adjust the interrupt masks if necessary. * * Return the memory held by the interrupt handler descriptor data * structure to the system. First ensure the handler is not actively * in use. */ int inthand_remove(struct intrhand *idesc) { struct ithd *ithd; /* descriptor for the IRQ */ struct intrhand *ih; /* chain of handlers */ if (idesc == NULL) return (-1); ithd = idesc->ih_ithd; ih = ithd->it_ih; if (ih == idesc) /* first in the chain */ ithd->it_ih = idesc->ih_next; /* unhook it */ else { while ((ih != NULL) && (ih->ih_next != idesc) ) ih = ih->ih_next; if (ih->ih_next != idesc) return (-1); ih->ih_next = ih->ih_next->ih_next; } if (ithd->it_ih == NULL) { /* no handlers left, */ icu_unset(ithd->irq, idesc->ih_handler); ithds[ithd->irq] = NULL; if ((idesc->ih_flags & INTR_FAST) == 0) { mtx_enter(&sched_lock, MTX_SPIN); if (ithd->it_proc->p_stat == SWAIT) { ithd->it_proc->p_stat = SRUN; setrunqueue(ithd->it_proc); /* * We don't do an ast here because we really * don't care when it runs next. * * XXX: should we lower the threads priority? */ } mtx_exit(&sched_lock, MTX_SPIN); } } free(idesc->ih_name, M_DEVBUF); free(idesc, M_DEVBUF); return (0); } diff --git a/sys/i386/include/asnames.h b/sys/i386/include/asnames.h index 891f30b9b02f..2cad36b1f093 100644 --- a/sys/i386/include/asnames.h +++ b/sys/i386/include/asnames.h @@ -1,316 +1,332 @@ /*- * Copyright (c) 1997 John D. Polstra * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_ASNAMES_H_ #define _MACHINE_ASNAMES_H_ /* * This file is used by the kernel assembly language sources to provide * the proper mapping between the global names used in assembly language * code and the corresponding C symbols. By convention, all C symbols * that are referenced from assembly language are prefixed with `_'. * That happens to be the same prefix that the a.out compiler attaches * to each C symbol. * * When using the ELF compiler, C symbols are identical to the corresponding * assembly language symbols. Thus the extra underscores cause problems. * The defines in this file map the underscore names back to the proper * unadorned names. * * Every global symbol that is referenced from both C source and assembly * language source must have an entry in this file, or the kernel will * not build properly using the ELF compiler. * * This file is included by , and it is OK to rely * on that. */ #ifdef __ELF__ #define _APTD APTD #define _APTDpde APTDpde #define _APTmap APTmap #define _CONST_QNaN CONST_QNaN #define _IdlePTD IdlePTD #define _KPTphys KPTphys #define _MP_GDT MP_GDT #define _PTD PTD #define _PTDpde PTDpde #define _PTmap PTmap #define _SMP_prvspace SMP_prvspace #define _SMPpt SMPpt #define _Xalign Xalign #define _Xbnd Xbnd #define _Xbpt Xbpt #define _Xcpuast Xcpuast #define _Xcpucheckstate Xcpucheckstate #define _Xcpustop Xcpustop #define _Xdbg Xdbg #define _Xdiv Xdiv #define _Xdna Xdna #define _Xfastintr0 Xfastintr0 #define _Xfastintr1 Xfastintr1 #define _Xfastintr10 Xfastintr10 #define _Xfastintr11 Xfastintr11 #define _Xfastintr12 Xfastintr12 #define _Xfastintr13 Xfastintr13 #define _Xfastintr14 Xfastintr14 #define _Xfastintr15 Xfastintr15 #define _Xfastintr16 Xfastintr16 #define _Xfastintr17 Xfastintr17 #define _Xfastintr18 Xfastintr18 #define _Xfastintr19 Xfastintr19 #define _Xfastintr2 Xfastintr2 #define _Xfastintr20 Xfastintr20 #define _Xfastintr21 Xfastintr21 #define _Xfastintr22 Xfastintr22 #define _Xfastintr23 Xfastintr23 +#define _Xfastintr24 Xfastintr24 +#define _Xfastintr25 Xfastintr25 +#define _Xfastintr26 Xfastintr26 +#define _Xfastintr27 Xfastintr27 +#define _Xfastintr28 Xfastintr28 +#define _Xfastintr29 Xfastintr29 #define _Xfastintr3 Xfastintr3 +#define _Xfastintr30 Xfastintr30 +#define _Xfastintr31 Xfastintr31 #define _Xfastintr4 Xfastintr4 #define _Xfastintr5 Xfastintr5 #define _Xfastintr6 Xfastintr6 #define _Xfastintr7 Xfastintr7 #define _Xfastintr8 Xfastintr8 #define _Xfastintr9 Xfastintr9 #define _Xforward_irq Xforward_irq #define _Xfpu Xfpu #define _Xfpusegm Xfpusegm #define _Xill Xill #define _Xint0x80_syscall Xint0x80_syscall #define _Xintr0 Xintr0 #define _Xintr1 Xintr1 #define _Xintr10 Xintr10 #define _Xintr11 Xintr11 #define _Xintr12 Xintr12 #define _Xintr13 Xintr13 #define _Xintr14 Xintr14 #define _Xintr15 Xintr15 #define _Xintr16 Xintr16 #define _Xintr17 Xintr17 #define _Xintr18 Xintr18 #define _Xintr19 Xintr19 #define _Xintr2 Xintr2 #define _Xintr20 Xintr20 #define _Xintr21 Xintr21 #define _Xintr22 Xintr22 #define _Xintr23 Xintr23 +#define _Xintr24 Xintr24 +#define _Xintr25 Xintr25 +#define _Xintr26 Xintr26 +#define _Xintr27 Xintr27 +#define _Xintr28 Xintr28 +#define _Xintr29 Xintr29 #define _Xintr3 Xintr3 +#define _Xintr30 Xintr30 +#define _Xintr31 Xintr31 #define _Xintr4 Xintr4 #define _Xintr5 Xintr5 #define _Xintr6 Xintr6 #define _Xintr7 Xintr7 #define _Xintr8 Xintr8 #define _Xintr9 Xintr9 #define _Xtintr0 Xtintr0 #define _Xinvltlb Xinvltlb #define _Xrendezvous Xrendezvous #define _Xmchk Xmchk #define _Xmissing Xmissing #define _Xnmi Xnmi #define _Xofl Xofl #define _Xpage Xpage #define _Xprot Xprot #define _Xrsvd Xrsvd #define _Xspuriousint Xspuriousint #define _Xstk Xstk #define _Xsyscall Xsyscall #define _Xtss Xtss #define __default_ldt _default_ldt #define __ucodesel _ucodesel #define __udatasel _udatasel #define _alltraps alltraps #define _ap_init ap_init #define _apic_imen apic_imen #define _apic_isrbit_location apic_isrbit_location #define _apic_pin_trigger apic_pin_trigger #define _arith_invalid arith_invalid #define _arith_overflow arith_overflow #define _arith_underflow arith_underflow #define _ast ast #define _bcopy bcopy #define _bcopy_vector bcopy_vector #define _bigJump bigJump #define _bintr bintr #define _bioscall_vector bioscall_vector #define _bootCodeSeg bootCodeSeg #define _bootDataSeg bootDataSeg #define _bootMP bootMP #define _bootMP_size bootMP_size #define _bootSTK bootSTK #define _boot_get_mplock boot_get_mplock #define _bootdev bootdev #define _boothowto boothowto #define _bootinfo bootinfo #define _btrap btrap #define _bzero bzero #define _checkstate_cpus checkstate_cpus #define _checkstate_cpustate checkstate_cpustate #define _checkstate_curproc checkstate_curproc #define _checkstate_need_ast checkstate_need_ast #define _checkstate_pc checkstate_pc #define _checkstate_pending_ast checkstate_pending_ast #define _checkstate_probed_cpus checkstate_probed_cpus #define _chooseproc chooseproc #define _cnt cnt #define _copyin_vector copyin_vector #define _copyout_vector copyout_vector #define _cpl_lock cpl_lock #define _cpu cpu #define _cpu0prvpage cpu0prvpage #define _cpu_apic_versions cpu_apic_versions #define _cpu_class cpu_class #define _cpu_feature cpu_feature #define _cpu_high cpu_high #define _cpu_id cpu_id #define _cpu_num_to_apic_id cpu_num_to_apic_id #define _cpu_switch cpu_switch #define _cpu_vendor cpu_vendor #define _default_halt default_halt #define _denormal_operand denormal_operand #define _div_small div_small #define _divide_by_zero divide_by_zero #define _divide_kernel divide_kernel #define _do_page_zero_idle do_page_zero_idle #define _doreti doreti #define _edata edata #define _eintrcnt eintrcnt #define _eintrnames eintrnames #define _end end #define _etext etext #define _exception exception #define _fast_intr_lock fast_intr_lock #define _fastmove fastmove #define _gdt gdt #define _generic_bcopy generic_bcopy #define _generic_bzero generic_bzero #define _generic_copyin generic_copyin #define _generic_copyout generic_copyout #define _get_align_lock get_align_lock #define _get_altsyscall_lock get_altsyscall_lock #define _get_fpu_lock get_fpu_lock #define _get_isrlock get_isrlock #define _get_mplock get_mplock #define _get_syscall_lock get_syscall_lock #define _Giant Giant #define _idle idle #define _imen imen #define _imen_lock imen_lock #define _in_vm86call in_vm86call #define _init386 init386 #define _init_secondary init_secondary #define _intr_countp intr_countp #define _intr_handler intr_handler #define _intr_mask intr_mask #define _intr_unit intr_unit #define _intrcnt intrcnt #define _intrnames intrnames #define _invltlb_ok invltlb_ok #define _ioapic ioapic #define _isr_lock isr_lock #define _kernelname kernelname #define _lapic lapic #define _linux_sigcode linux_sigcode #define _linux_szsigcode linux_szsigcode #define _mi_startup mi_startup #define _microuptime microuptime #define _mp_gdtbase mp_gdtbase #define _mp_lock mp_lock #define _mp_ncpus mp_ncpus #define __mtx_enter_giant_def _mtx_enter_giant_def #define __mtx_exit_giant_def _mtx_exit_giant_def #define _mul64 mul64 #define _nfs_diskless nfs_diskless #define _nfs_diskless_valid nfs_diskless_valid #define _normalize normalize #define _normalize_nuo normalize_nuo #define _npx_intr npx_intr #define _npxsave npxsave #define _szosigcode szosigcode #define _ovbcopy_vector ovbcopy_vector #define _panic panic #define _pc98_system_parameter pc98_system_parameter #define _poly_div16 poly_div16 #define _poly_div2 poly_div2 #define _poly_div4 poly_div4 #define _polynomial polynomial #define _private_tss private_tss #define _proc0 proc0 #define _proc0paddr proc0paddr #define _procrunnable procrunnable #define _real_2op_NaN real_2op_NaN #define _reg_div reg_div #define _reg_u_add reg_u_add #define _reg_u_div reg_u_div #define _reg_u_mul reg_u_mul #define _reg_u_sub reg_u_sub #define _rel_mplock rel_mplock #define _round_reg round_reg #define _s_lock s_lock #define _s_unlock s_unlock #define _sched_ithd sched_ithd #define _sched_lock sched_lock #define _set_precision_flag_down set_precision_flag_down #define _set_precision_flag_up set_precision_flag_up #define _set_user_ldt set_user_ldt #define _shrx shrx #define _shrxs shrxs #define _sigcode sigcode #define _smp_active smp_active #define _smp_rendezvous_action smp_rendezvous_action #define _softclock softclock #define _spending spending #define _ss_lock ss_lock #define _ss_unlock ss_unlock #define _started_cpus started_cpus #define _stopped_cpus stopped_cpus #define _svr4_sigcode svr4_sigcode #define _svr4_sys_context svr4_sys_context #define _svr4_szsigcode svr4_szsigcode #define _swi_dispatcher swi_dispatcher #define _swi_generic swi_generic #define _swi_net swi_net #define _swi_null swi_null #define _swi_vm swi_vm #define _syscall2 syscall2 #define _szsigcode szsigcode #define _ticks ticks #define _time time #define _trap trap #define _trapwrite trapwrite #define _vec vec #define _vec8254 vec8254 #define _vm86_prepcall vm86_prepcall #define _vm86pa vm86pa #define _vm86paddr vm86paddr #define _vm86pcb vm86pcb #define _vm_page_zero_idle vm_page_zero_idle #define _wm_sqrt wm_sqrt #endif /* __ELF__ */ #endif /* !_MACHINE_ASNAMES_H_ */ diff --git a/sys/i386/isa/icu.h b/sys/i386/isa/icu.h index b5f2de4356d8..6423551784f5 100644 --- a/sys/i386/isa/icu.h +++ b/sys/i386/isa/icu.h @@ -1,128 +1,128 @@ /*- * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)icu.h 5.6 (Berkeley) 5/9/91 * $FreeBSD$ */ /* * AT/386 Interrupt Control constants * W. Jolitz 8/89 */ #ifndef _I386_ISA_ICU_H_ #define _I386_ISA_ICU_H_ #ifndef LOCORE /* #define MP_SAFE * Note: * Most of the SMP equivilants of the icu macros are coded * elsewhere in an MP-safe fashion. * In particular note that the 'imen' variable is opaque. * DO NOT access imen directly, use INTREN()/INTRDIS(). */ void INTREN __P((u_int)); void INTRDIS __P((u_int)); #ifdef APIC_IO extern unsigned apic_imen; /* APIC interrupt mask enable */ #define APIC_IMEN_BITS 32 /* number of bits in apic_imen */ #else extern unsigned imen; /* interrupt mask enable */ #define IMEN_BITS 16 /* number of bits in imen */ #endif #endif /* LOCORE */ #ifdef APIC_IO /* * Note: The APIC uses different values for IRQxxx. * Unfortunately many drivers use the 8259 values as indexes * into tables, etc. The APIC equivilants are kept as APIC_IRQxxx. * The 8259 versions have to be used in SMP for legacy operation * of the drivers. */ #endif /* APIC_IO */ /* * Interrupt enable bits - in normal order of priority (which we change) */ #define IRQ0 0x0001 /* highest priority - timer */ #define IRQ1 0x0002 #define IRQ_SLAVE 0x0004 #define IRQ8 0x0100 #define IRQ9 0x0200 #define IRQ2 IRQ9 #define IRQ10 0x0400 #define IRQ11 0x0800 #define IRQ12 0x1000 #define IRQ13 0x2000 #define IRQ14 0x4000 #define IRQ15 0x8000 #define IRQ3 0x0008 /* this is highest after rotation */ #define IRQ4 0x0010 #define IRQ5 0x0020 #define IRQ6 0x0040 #define IRQ7 0x0080 /* lowest - parallel printer */ #ifdef PC98 #undef IRQ2 #define IRQ2 0x0004 #undef IRQ_SLAVE #define IRQ_SLAVE 0x0080 #endif /* * Interrupt Control offset into Interrupt descriptor table (IDT) */ #define ICU_OFFSET 32 /* 0-31 are processor exceptions */ #ifdef APIC_IO -/* 32-47: ISA IRQ0-IRQ15, 48-55: IO APIC IRQ16-IRQ23 */ -#define ICU_LEN 24 +/* 32-47: ISA IRQ0-IRQ15, 48-55: IO APIC IRQ16-IRQ31 */ +#define ICU_LEN 32 #else #define ICU_LEN 16 /* 32-47 are ISA interrupts */ #endif /* APIC_IO */ #endif /* !_I386_ISA_ICU_H_ */ diff --git a/sys/i386/isa/intr_machdep.c b/sys/i386/isa/intr_machdep.c index 5a669d237caa..00f5f23d359f 100644 --- a/sys/i386/isa/intr_machdep.c +++ b/sys/i386/isa/intr_machdep.c @@ -1,715 +1,721 @@ /*- * Copyright (c) 1991 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 * $FreeBSD$ */ #include "opt_auto_eoi.h" #include "isa.h" #include #include #ifndef SMP #include #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(APIC_IO) #include /** FAST_HI */ #include #include #endif /* APIC_IO */ #ifdef PC98 #include #include #include #else #include #endif #include #if NISA > 0 #include #endif #include #include #ifdef APIC_IO #include #endif #include "mca.h" #if NMCA > 0 #include #endif /* * Per-interrupt data. */ u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */ driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */ struct ithd *ithds[ICU_LEN]; /* real interrupt handler */ void *intr_unit[ICU_LEN]; static inthand_t *fastintr[ICU_LEN] = { &IDTVEC(fastintr0), &IDTVEC(fastintr1), &IDTVEC(fastintr2), &IDTVEC(fastintr3), &IDTVEC(fastintr4), &IDTVEC(fastintr5), &IDTVEC(fastintr6), &IDTVEC(fastintr7), &IDTVEC(fastintr8), &IDTVEC(fastintr9), &IDTVEC(fastintr10), &IDTVEC(fastintr11), &IDTVEC(fastintr12), &IDTVEC(fastintr13), &IDTVEC(fastintr14), &IDTVEC(fastintr15), #if defined(APIC_IO) &IDTVEC(fastintr16), &IDTVEC(fastintr17), &IDTVEC(fastintr18), &IDTVEC(fastintr19), &IDTVEC(fastintr20), &IDTVEC(fastintr21), &IDTVEC(fastintr22), &IDTVEC(fastintr23), + &IDTVEC(fastintr24), &IDTVEC(fastintr25), + &IDTVEC(fastintr26), &IDTVEC(fastintr27), + &IDTVEC(fastintr28), &IDTVEC(fastintr29), + &IDTVEC(fastintr30), &IDTVEC(fastintr31), #endif /* APIC_IO */ }; static inthand_t *slowintr[ICU_LEN] = { &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3), &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7), &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11), &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15), #if defined(APIC_IO) &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19), &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23), + &IDTVEC(intr24), &IDTVEC(intr25), &IDTVEC(intr26), &IDTVEC(intr27), + &IDTVEC(intr28), &IDTVEC(intr29), &IDTVEC(intr30), &IDTVEC(intr31), #endif /* APIC_IO */ }; static driver_intr_t isa_strayintr; #ifdef PC98 #define NMI_PARITY 0x04 #define NMI_EPARITY 0x02 #else #define NMI_PARITY (1 << 7) #define NMI_IOCHAN (1 << 6) #define ENMI_WATCHDOG (1 << 7) #define ENMI_BUSTIMER (1 << 6) #define ENMI_IOSTATUS (1 << 5) #endif /* * Bus attachment for the ISA PIC. */ static struct isa_pnp_id atpic_ids[] = { { 0x0000d041 /* PNP0000 */, "AT interrupt controller" }, { 0 } }; static int atpic_probe(device_t dev) { int result; if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0) device_quiet(dev); return(result); } /* * In the APIC_IO case we might be granted IRQ 2, as this is typically * consumed by chaining between the two PIC components. If we're using * the APIC, however, this may not be the case, and as such we should * free the resource. (XXX untested) * * The generic ISA attachment code will handle allocating any other resources * that we don't explicitly claim here. */ static int atpic_attach(device_t dev) { #ifdef APIC_IO int rid; struct resource *res; /* try to allocate our IRQ and then free it */ rid = 0; res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0); if (res != NULL) bus_release_resource(dev, SYS_RES_IRQ, rid, res); #endif return(0); } static device_method_t atpic_methods[] = { /* Device interface */ DEVMETHOD(device_probe, atpic_probe), DEVMETHOD(device_attach, atpic_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), { 0, 0 } }; static driver_t atpic_driver = { "atpic", atpic_methods, 1, /* no softc */ }; static devclass_t atpic_devclass; DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0); /* * Handle a NMI, possibly a machine check. * return true to panic system, false to ignore. */ int isa_nmi(cd) int cd; { int retval = 0; #ifdef PC98 int port = inb(0x33); log(LOG_CRIT, "NMI PC98 port = %x\n", port); if (epson_machine_id == 0x20) epson_outb(0xc16, epson_inb(0xc16) | 0x1); if (port & NMI_PARITY) { log(LOG_CRIT, "BASE RAM parity error, likely hardware failure."); retval = 1; } else if (port & NMI_EPARITY) { log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure."); retval = 1; } else { log(LOG_CRIT, "\nNMI Resume ??\n"); } #else /* IBM-PC */ int isa_port = inb(0x61); int eisa_port = inb(0x461); log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port); #if NMCA > 0 if (MCA_system && mca_bus_nmi()) return(0); #endif if (isa_port & NMI_PARITY) { log(LOG_CRIT, "RAM parity error, likely hardware failure."); retval = 1; } if (isa_port & NMI_IOCHAN) { log(LOG_CRIT, "I/O channel check, likely hardware failure."); retval = 1; } /* * On a real EISA machine, this will never happen. However it can * happen on ISA machines which implement XT style floating point * error handling (very rare). Save them from a meaningless panic. */ if (eisa_port == 0xff) return(retval); if (eisa_port & ENMI_WATCHDOG) { log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure."); retval = 1; } if (eisa_port & ENMI_BUSTIMER) { log(LOG_CRIT, "EISA bus timeout, likely hardware failure."); retval = 1; } if (eisa_port & ENMI_IOSTATUS) { log(LOG_CRIT, "EISA I/O port status error."); retval = 1; } #endif return(retval); } /* * Create a default interrupt table to avoid problems caused by * spurious interrupts during configuration of kernel, then setup * interrupt control unit. */ void isa_defaultirq() { int i; /* icu vectors */ for (i = 0; i < ICU_LEN; i++) icu_unset(i, (driver_intr_t *)NULL); /* initialize 8259's */ #if NMCA > 0 if (MCA_system) outb(IO_ICU1, 0x19); /* reset; program device, four bytes */ else #endif outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */ outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */ #ifdef PC98 #ifdef AUTO_EOI_1 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */ #else outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */ #endif #else /* IBM-PC */ #ifdef AUTO_EOI_1 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ #else outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */ #endif #endif /* PC98 */ outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ outb(IO_ICU1, 0x0a); /* default to IRR on read */ #ifndef PC98 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ #endif /* !PC98 */ #if NMCA > 0 if (MCA_system) outb(IO_ICU2, 0x19); /* reset; program device, four bytes */ else #endif outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */ outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */ #ifdef PC98 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */ #else /* IBM-PC */ #ifdef AUTO_EOI_2 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ #else outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */ #endif #endif /* PC98 */ outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ outb(IO_ICU2, 0x0a); /* default to IRR on read */ } /* * Caught a stray interrupt, notify */ static void isa_strayintr(vcookiep) void *vcookiep; { int intr = (void **)vcookiep - &intr_unit[0]; /* * XXX TODO print a different message for #7 if it is for a * glitch. Glitches can be distinguished from real #7's by * testing that the in-service bit is _not_ set. The test * must be done before sending an EOI so it can't be done if * we are using AUTO_EOI_1. */ if (intrcnt[1 + intr] <= 5) log(LOG_ERR, "stray irq %d\n", intr); if (intrcnt[1 + intr] == 5) log(LOG_CRIT, "too many stray irq %d's; not logging any more\n", intr); } #if NISA > 0 /* * Return a bitmap of the current interrupt requests. This is 8259-specific * and is only suitable for use at probe time. */ intrmask_t isa_irq_pending() { u_char irr1; u_char irr2; irr1 = inb(IO_ICU1); irr2 = inb(IO_ICU2); return ((irr2 << 8) | irr1); } #endif /* * Update intrnames array with the specified name. This is used by * vmstat(8) and the like. */ static void update_intrname(int intr, char *name) { char buf[32]; char *cp; int name_index, off, strayintr; /* * Initialise strings for bitbucket and stray interrupt counters. * These have statically allocated indices 0 and 1 through ICU_LEN. */ if (intrnames[0] == '\0') { off = sprintf(intrnames, "???") + 1; for (strayintr = 0; strayintr < ICU_LEN; strayintr++) off += sprintf(intrnames + off, "stray irq%d", strayintr) + 1; } if (name == NULL) name = "???"; if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf)) goto use_bitbucket; /* * Search for `buf' in `intrnames'. In the usual case when it is * not found, append it to the end if there is enough space (the \0 * terminator for the previous string, if any, becomes a separator). */ for (cp = intrnames, name_index = 0; cp != eintrnames && name_index < NR_INTRNAMES; cp += strlen(cp) + 1, name_index++) { if (*cp == '\0') { if (strlen(buf) >= eintrnames - cp) break; strcpy(cp, buf); goto found; } if (strcmp(cp, buf) == 0) goto found; } use_bitbucket: printf("update_intrname: counting %s irq%d as %s\n", name, intr, intrnames); name_index = 0; found: intr_countp[intr] = &intrcnt[name_index]; } int icu_setup(int intr, driver_intr_t *handler, void *arg, int flags) { #ifdef FAST_HI int select; /* the select register is 8 bits */ int vector; u_int32_t value; /* the window register is 32 bits */ #endif /* FAST_HI */ u_long ef; #if defined(APIC_IO) if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */ #else if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID) #endif /* APIC_IO */ if (intr_handler[intr] != isa_strayintr) return (EBUSY); ef = read_eflags(); disable_intr(); intr_handler[intr] = handler; intr_unit[intr] = arg; #ifdef FAST_HI if (flags & INTR_FAST) { vector = TPR_FAST_INTS + intr; setidt(vector, fastintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); } else { vector = TPR_SLOW_INTS + intr; #ifdef APIC_INTR_REORDER #ifdef APIC_INTR_HIGHPRI_CLOCK /* XXX: Hack (kludge?) for more accurate clock. */ if (intr == apic_8254_intr || intr == 8) { vector = TPR_FAST_INTS + intr; } #endif #endif setidt(vector, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); } #ifdef APIC_INTR_REORDER set_lapic_isrloc(intr, vector); #endif /* * Reprogram the vector in the IO APIC. */ if (int_to_apicintpin[intr].ioapic >= 0) { select = int_to_apicintpin[intr].redirindex; value = io_apic_read(int_to_apicintpin[intr].ioapic, select) & ~IOART_INTVEC; io_apic_write(int_to_apicintpin[intr].ioapic, select, value | vector); } #else setidt(ICU_OFFSET + intr, flags & INTR_FAST ? fastintr[intr] : slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /* FAST_HI */ INTREN(1 << intr); write_eflags(ef); return (0); } /* * Dissociate an interrupt handler from an IRQ and set the handler to * the stray interrupt handler. The 'handler' parameter is used only * for consistency checking. */ int icu_unset(intr, handler) int intr; driver_intr_t *handler; { u_long ef; if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr]) return (EINVAL); INTRDIS(1 << intr); ef = read_eflags(); disable_intr(); intr_countp[intr] = &intrcnt[1 + intr]; intr_handler[intr] = isa_strayintr; intr_unit[intr] = &intr_unit[intr]; #ifdef FAST_HI_XXX /* XXX how do I re-create dvp here? */ setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #else /* FAST_HI */ #ifdef APIC_INTR_REORDER set_lapic_isrloc(intr, ICU_OFFSET + intr); #endif setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /* FAST_HI */ write_eflags(ef); return (0); } struct intrhand * inthand_add(const char *name, int irq, driver_intr_t handler, void *arg, int pri, int flags) { struct ithd *ithd = ithds[irq]; /* descriptor for the IRQ */ struct intrhand *head; /* chain of handlers for IRQ */ struct intrhand *idesc; /* descriptor for this handler */ struct proc *p; /* interrupt thread */ int errcode = 0; if (name == NULL) /* no name? */ panic ("anonymous interrupt"); if (ithd == NULL || ithd->it_ih == NULL) { /* first handler for this irq. */ if (ithd == NULL) { ithd = malloc(sizeof (struct ithd), M_DEVBUF, M_WAITOK | M_ZERO); if (ithd == NULL) return (NULL); ithd->irq = irq; ithds[irq] = ithd; } /* * If we have a fast interrupt, we need to set the * handler address directly. Do that below. For a * slow interrupt, we don't need to know more details, * so do it here because it's tidier. */ if ((flags & INTR_FAST) == 0) { /* * Only create a kernel thread if we don't already * have one. */ if (ithd->it_proc == NULL) { errcode = kthread_create(ithd_loop, NULL, &p, RFSTOPPED | RFHIGHPID, "irq%d: %s", irq, name); if (errcode) panic("inthand_add: Can't create " "interrupt thread"); p->p_rtprio.type = RTP_PRIO_ITHREAD; p->p_stat = SWAIT; /* we're idle */ /* Put in linkages. */ ithd->it_proc = p; p->p_ithd = ithd; } else snprintf(ithd->it_proc->p_comm, MAXCOMLEN, "irq%d: %s", irq, name); p->p_rtprio.prio = pri; /* * The interrupt process must be in place, but * not necessarily schedulable, before we * initialize the ICU, since it may cause an * immediate interrupt. */ if (icu_setup(irq, &sched_ithd, arg, flags) != 0) panic("inthand_add: Can't initialize ICU"); } } else if ((flags & INTR_EXCL) != 0 || (ithd->it_ih->ih_flags & INTR_EXCL) != 0) { /* * We can't append the new handler if either * list ithd or new handler do not allow * interrupts to be shared. */ if (bootverbose) printf("\tdevice combination %s and %s " "doesn't support shared irq%d\n", ithd->it_ih->ih_name, name, irq); return(NULL); } else if (flags & INTR_FAST) { /* We can only have one fast interrupt by itself. */ if (bootverbose) printf("\tCan't add fast interrupt %s" " to normal interrupt %s on irq%d", name, ithd->it_ih->ih_name, irq); return (NULL); } else { /* update p_comm */ p = ithd->it_proc; if (strlen(p->p_comm) + strlen(name) < MAXCOMLEN) { strcat(p->p_comm, " "); strcat(p->p_comm, name); } else if (strlen(p->p_comm) == MAXCOMLEN) p->p_comm[MAXCOMLEN - 1] = '+'; else strcat(p->p_comm, "+"); } idesc = malloc(sizeof (struct intrhand), M_DEVBUF, M_WAITOK | M_ZERO); if (idesc == NULL) return (NULL); idesc->ih_handler = handler; idesc->ih_argument = arg; idesc->ih_flags = flags; idesc->ih_ithd = ithd; idesc->ih_name = malloc(strlen(name) + 1, M_DEVBUF, M_WAITOK); if (idesc->ih_name == NULL) { free(idesc, M_DEVBUF); return (NULL); } strcpy(idesc->ih_name, name); /* Slow interrupts got set up above. */ if ((flags & INTR_FAST) && (icu_setup(irq, idesc->ih_handler, idesc->ih_argument, idesc->ih_flags) != 0) ) { if (bootverbose) printf("\tinthand_add(irq%d) failed, result=%d\n", irq, errcode); free(idesc->ih_name, M_DEVBUF); free(idesc, M_DEVBUF); return NULL; } head = ithd->it_ih; /* look at chain of handlers */ if (head) { while (head->ih_next != NULL) head = head->ih_next; /* find the end */ head->ih_next = idesc; /* hook it in there */ } else ithd->it_ih = idesc; /* put it up front */ update_intrname(irq, idesc->ih_name); return (idesc); } /* * Deactivate and remove linked list the interrupt handler descriptor * data connected created by an earlier call of inthand_add(), then * adjust the interrupt masks if necessary. * * Return the memory held by the interrupt handler descriptor data * structure to the system. First ensure the handler is not actively * in use. */ int inthand_remove(struct intrhand *idesc) { struct ithd *ithd; /* descriptor for the IRQ */ struct intrhand *ih; /* chain of handlers */ if (idesc == NULL) return (-1); ithd = idesc->ih_ithd; ih = ithd->it_ih; if (ih == idesc) /* first in the chain */ ithd->it_ih = idesc->ih_next; /* unhook it */ else { while ((ih != NULL) && (ih->ih_next != idesc) ) ih = ih->ih_next; if (ih->ih_next != idesc) return (-1); ih->ih_next = ih->ih_next->ih_next; } if (ithd->it_ih == NULL) { /* no handlers left, */ icu_unset(ithd->irq, idesc->ih_handler); ithds[ithd->irq] = NULL; if ((idesc->ih_flags & INTR_FAST) == 0) { mtx_enter(&sched_lock, MTX_SPIN); if (ithd->it_proc->p_stat == SWAIT) { ithd->it_proc->p_stat = SRUN; setrunqueue(ithd->it_proc); /* * We don't do an ast here because we really * don't care when it runs next. * * XXX: should we lower the threads priority? */ } mtx_exit(&sched_lock, MTX_SPIN); } } free(idesc->ih_name, M_DEVBUF); free(idesc, M_DEVBUF); return (0); } diff --git a/sys/i386/isa/nmi.c b/sys/i386/isa/nmi.c index 5a669d237caa..00f5f23d359f 100644 --- a/sys/i386/isa/nmi.c +++ b/sys/i386/isa/nmi.c @@ -1,715 +1,721 @@ /*- * Copyright (c) 1991 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 * $FreeBSD$ */ #include "opt_auto_eoi.h" #include "isa.h" #include #include #ifndef SMP #include #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(APIC_IO) #include /** FAST_HI */ #include #include #endif /* APIC_IO */ #ifdef PC98 #include #include #include #else #include #endif #include #if NISA > 0 #include #endif #include #include #ifdef APIC_IO #include #endif #include "mca.h" #if NMCA > 0 #include #endif /* * Per-interrupt data. */ u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */ driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */ struct ithd *ithds[ICU_LEN]; /* real interrupt handler */ void *intr_unit[ICU_LEN]; static inthand_t *fastintr[ICU_LEN] = { &IDTVEC(fastintr0), &IDTVEC(fastintr1), &IDTVEC(fastintr2), &IDTVEC(fastintr3), &IDTVEC(fastintr4), &IDTVEC(fastintr5), &IDTVEC(fastintr6), &IDTVEC(fastintr7), &IDTVEC(fastintr8), &IDTVEC(fastintr9), &IDTVEC(fastintr10), &IDTVEC(fastintr11), &IDTVEC(fastintr12), &IDTVEC(fastintr13), &IDTVEC(fastintr14), &IDTVEC(fastintr15), #if defined(APIC_IO) &IDTVEC(fastintr16), &IDTVEC(fastintr17), &IDTVEC(fastintr18), &IDTVEC(fastintr19), &IDTVEC(fastintr20), &IDTVEC(fastintr21), &IDTVEC(fastintr22), &IDTVEC(fastintr23), + &IDTVEC(fastintr24), &IDTVEC(fastintr25), + &IDTVEC(fastintr26), &IDTVEC(fastintr27), + &IDTVEC(fastintr28), &IDTVEC(fastintr29), + &IDTVEC(fastintr30), &IDTVEC(fastintr31), #endif /* APIC_IO */ }; static inthand_t *slowintr[ICU_LEN] = { &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3), &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7), &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11), &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15), #if defined(APIC_IO) &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19), &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23), + &IDTVEC(intr24), &IDTVEC(intr25), &IDTVEC(intr26), &IDTVEC(intr27), + &IDTVEC(intr28), &IDTVEC(intr29), &IDTVEC(intr30), &IDTVEC(intr31), #endif /* APIC_IO */ }; static driver_intr_t isa_strayintr; #ifdef PC98 #define NMI_PARITY 0x04 #define NMI_EPARITY 0x02 #else #define NMI_PARITY (1 << 7) #define NMI_IOCHAN (1 << 6) #define ENMI_WATCHDOG (1 << 7) #define ENMI_BUSTIMER (1 << 6) #define ENMI_IOSTATUS (1 << 5) #endif /* * Bus attachment for the ISA PIC. */ static struct isa_pnp_id atpic_ids[] = { { 0x0000d041 /* PNP0000 */, "AT interrupt controller" }, { 0 } }; static int atpic_probe(device_t dev) { int result; if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0) device_quiet(dev); return(result); } /* * In the APIC_IO case we might be granted IRQ 2, as this is typically * consumed by chaining between the two PIC components. If we're using * the APIC, however, this may not be the case, and as such we should * free the resource. (XXX untested) * * The generic ISA attachment code will handle allocating any other resources * that we don't explicitly claim here. */ static int atpic_attach(device_t dev) { #ifdef APIC_IO int rid; struct resource *res; /* try to allocate our IRQ and then free it */ rid = 0; res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0); if (res != NULL) bus_release_resource(dev, SYS_RES_IRQ, rid, res); #endif return(0); } static device_method_t atpic_methods[] = { /* Device interface */ DEVMETHOD(device_probe, atpic_probe), DEVMETHOD(device_attach, atpic_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), { 0, 0 } }; static driver_t atpic_driver = { "atpic", atpic_methods, 1, /* no softc */ }; static devclass_t atpic_devclass; DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0); /* * Handle a NMI, possibly a machine check. * return true to panic system, false to ignore. */ int isa_nmi(cd) int cd; { int retval = 0; #ifdef PC98 int port = inb(0x33); log(LOG_CRIT, "NMI PC98 port = %x\n", port); if (epson_machine_id == 0x20) epson_outb(0xc16, epson_inb(0xc16) | 0x1); if (port & NMI_PARITY) { log(LOG_CRIT, "BASE RAM parity error, likely hardware failure."); retval = 1; } else if (port & NMI_EPARITY) { log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure."); retval = 1; } else { log(LOG_CRIT, "\nNMI Resume ??\n"); } #else /* IBM-PC */ int isa_port = inb(0x61); int eisa_port = inb(0x461); log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port); #if NMCA > 0 if (MCA_system && mca_bus_nmi()) return(0); #endif if (isa_port & NMI_PARITY) { log(LOG_CRIT, "RAM parity error, likely hardware failure."); retval = 1; } if (isa_port & NMI_IOCHAN) { log(LOG_CRIT, "I/O channel check, likely hardware failure."); retval = 1; } /* * On a real EISA machine, this will never happen. However it can * happen on ISA machines which implement XT style floating point * error handling (very rare). Save them from a meaningless panic. */ if (eisa_port == 0xff) return(retval); if (eisa_port & ENMI_WATCHDOG) { log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure."); retval = 1; } if (eisa_port & ENMI_BUSTIMER) { log(LOG_CRIT, "EISA bus timeout, likely hardware failure."); retval = 1; } if (eisa_port & ENMI_IOSTATUS) { log(LOG_CRIT, "EISA I/O port status error."); retval = 1; } #endif return(retval); } /* * Create a default interrupt table to avoid problems caused by * spurious interrupts during configuration of kernel, then setup * interrupt control unit. */ void isa_defaultirq() { int i; /* icu vectors */ for (i = 0; i < ICU_LEN; i++) icu_unset(i, (driver_intr_t *)NULL); /* initialize 8259's */ #if NMCA > 0 if (MCA_system) outb(IO_ICU1, 0x19); /* reset; program device, four bytes */ else #endif outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */ outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */ #ifdef PC98 #ifdef AUTO_EOI_1 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */ #else outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */ #endif #else /* IBM-PC */ #ifdef AUTO_EOI_1 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ #else outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */ #endif #endif /* PC98 */ outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ outb(IO_ICU1, 0x0a); /* default to IRR on read */ #ifndef PC98 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ #endif /* !PC98 */ #if NMCA > 0 if (MCA_system) outb(IO_ICU2, 0x19); /* reset; program device, four bytes */ else #endif outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */ outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */ #ifdef PC98 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */ #else /* IBM-PC */ #ifdef AUTO_EOI_2 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ #else outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */ #endif #endif /* PC98 */ outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ outb(IO_ICU2, 0x0a); /* default to IRR on read */ } /* * Caught a stray interrupt, notify */ static void isa_strayintr(vcookiep) void *vcookiep; { int intr = (void **)vcookiep - &intr_unit[0]; /* * XXX TODO print a different message for #7 if it is for a * glitch. Glitches can be distinguished from real #7's by * testing that the in-service bit is _not_ set. The test * must be done before sending an EOI so it can't be done if * we are using AUTO_EOI_1. */ if (intrcnt[1 + intr] <= 5) log(LOG_ERR, "stray irq %d\n", intr); if (intrcnt[1 + intr] == 5) log(LOG_CRIT, "too many stray irq %d's; not logging any more\n", intr); } #if NISA > 0 /* * Return a bitmap of the current interrupt requests. This is 8259-specific * and is only suitable for use at probe time. */ intrmask_t isa_irq_pending() { u_char irr1; u_char irr2; irr1 = inb(IO_ICU1); irr2 = inb(IO_ICU2); return ((irr2 << 8) | irr1); } #endif /* * Update intrnames array with the specified name. This is used by * vmstat(8) and the like. */ static void update_intrname(int intr, char *name) { char buf[32]; char *cp; int name_index, off, strayintr; /* * Initialise strings for bitbucket and stray interrupt counters. * These have statically allocated indices 0 and 1 through ICU_LEN. */ if (intrnames[0] == '\0') { off = sprintf(intrnames, "???") + 1; for (strayintr = 0; strayintr < ICU_LEN; strayintr++) off += sprintf(intrnames + off, "stray irq%d", strayintr) + 1; } if (name == NULL) name = "???"; if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf)) goto use_bitbucket; /* * Search for `buf' in `intrnames'. In the usual case when it is * not found, append it to the end if there is enough space (the \0 * terminator for the previous string, if any, becomes a separator). */ for (cp = intrnames, name_index = 0; cp != eintrnames && name_index < NR_INTRNAMES; cp += strlen(cp) + 1, name_index++) { if (*cp == '\0') { if (strlen(buf) >= eintrnames - cp) break; strcpy(cp, buf); goto found; } if (strcmp(cp, buf) == 0) goto found; } use_bitbucket: printf("update_intrname: counting %s irq%d as %s\n", name, intr, intrnames); name_index = 0; found: intr_countp[intr] = &intrcnt[name_index]; } int icu_setup(int intr, driver_intr_t *handler, void *arg, int flags) { #ifdef FAST_HI int select; /* the select register is 8 bits */ int vector; u_int32_t value; /* the window register is 32 bits */ #endif /* FAST_HI */ u_long ef; #if defined(APIC_IO) if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */ #else if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID) #endif /* APIC_IO */ if (intr_handler[intr] != isa_strayintr) return (EBUSY); ef = read_eflags(); disable_intr(); intr_handler[intr] = handler; intr_unit[intr] = arg; #ifdef FAST_HI if (flags & INTR_FAST) { vector = TPR_FAST_INTS + intr; setidt(vector, fastintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); } else { vector = TPR_SLOW_INTS + intr; #ifdef APIC_INTR_REORDER #ifdef APIC_INTR_HIGHPRI_CLOCK /* XXX: Hack (kludge?) for more accurate clock. */ if (intr == apic_8254_intr || intr == 8) { vector = TPR_FAST_INTS + intr; } #endif #endif setidt(vector, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); } #ifdef APIC_INTR_REORDER set_lapic_isrloc(intr, vector); #endif /* * Reprogram the vector in the IO APIC. */ if (int_to_apicintpin[intr].ioapic >= 0) { select = int_to_apicintpin[intr].redirindex; value = io_apic_read(int_to_apicintpin[intr].ioapic, select) & ~IOART_INTVEC; io_apic_write(int_to_apicintpin[intr].ioapic, select, value | vector); } #else setidt(ICU_OFFSET + intr, flags & INTR_FAST ? fastintr[intr] : slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /* FAST_HI */ INTREN(1 << intr); write_eflags(ef); return (0); } /* * Dissociate an interrupt handler from an IRQ and set the handler to * the stray interrupt handler. The 'handler' parameter is used only * for consistency checking. */ int icu_unset(intr, handler) int intr; driver_intr_t *handler; { u_long ef; if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr]) return (EINVAL); INTRDIS(1 << intr); ef = read_eflags(); disable_intr(); intr_countp[intr] = &intrcnt[1 + intr]; intr_handler[intr] = isa_strayintr; intr_unit[intr] = &intr_unit[intr]; #ifdef FAST_HI_XXX /* XXX how do I re-create dvp here? */ setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #else /* FAST_HI */ #ifdef APIC_INTR_REORDER set_lapic_isrloc(intr, ICU_OFFSET + intr); #endif setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /* FAST_HI */ write_eflags(ef); return (0); } struct intrhand * inthand_add(const char *name, int irq, driver_intr_t handler, void *arg, int pri, int flags) { struct ithd *ithd = ithds[irq]; /* descriptor for the IRQ */ struct intrhand *head; /* chain of handlers for IRQ */ struct intrhand *idesc; /* descriptor for this handler */ struct proc *p; /* interrupt thread */ int errcode = 0; if (name == NULL) /* no name? */ panic ("anonymous interrupt"); if (ithd == NULL || ithd->it_ih == NULL) { /* first handler for this irq. */ if (ithd == NULL) { ithd = malloc(sizeof (struct ithd), M_DEVBUF, M_WAITOK | M_ZERO); if (ithd == NULL) return (NULL); ithd->irq = irq; ithds[irq] = ithd; } /* * If we have a fast interrupt, we need to set the * handler address directly. Do that below. For a * slow interrupt, we don't need to know more details, * so do it here because it's tidier. */ if ((flags & INTR_FAST) == 0) { /* * Only create a kernel thread if we don't already * have one. */ if (ithd->it_proc == NULL) { errcode = kthread_create(ithd_loop, NULL, &p, RFSTOPPED | RFHIGHPID, "irq%d: %s", irq, name); if (errcode) panic("inthand_add: Can't create " "interrupt thread"); p->p_rtprio.type = RTP_PRIO_ITHREAD; p->p_stat = SWAIT; /* we're idle */ /* Put in linkages. */ ithd->it_proc = p; p->p_ithd = ithd; } else snprintf(ithd->it_proc->p_comm, MAXCOMLEN, "irq%d: %s", irq, name); p->p_rtprio.prio = pri; /* * The interrupt process must be in place, but * not necessarily schedulable, before we * initialize the ICU, since it may cause an * immediate interrupt. */ if (icu_setup(irq, &sched_ithd, arg, flags) != 0) panic("inthand_add: Can't initialize ICU"); } } else if ((flags & INTR_EXCL) != 0 || (ithd->it_ih->ih_flags & INTR_EXCL) != 0) { /* * We can't append the new handler if either * list ithd or new handler do not allow * interrupts to be shared. */ if (bootverbose) printf("\tdevice combination %s and %s " "doesn't support shared irq%d\n", ithd->it_ih->ih_name, name, irq); return(NULL); } else if (flags & INTR_FAST) { /* We can only have one fast interrupt by itself. */ if (bootverbose) printf("\tCan't add fast interrupt %s" " to normal interrupt %s on irq%d", name, ithd->it_ih->ih_name, irq); return (NULL); } else { /* update p_comm */ p = ithd->it_proc; if (strlen(p->p_comm) + strlen(name) < MAXCOMLEN) { strcat(p->p_comm, " "); strcat(p->p_comm, name); } else if (strlen(p->p_comm) == MAXCOMLEN) p->p_comm[MAXCOMLEN - 1] = '+'; else strcat(p->p_comm, "+"); } idesc = malloc(sizeof (struct intrhand), M_DEVBUF, M_WAITOK | M_ZERO); if (idesc == NULL) return (NULL); idesc->ih_handler = handler; idesc->ih_argument = arg; idesc->ih_flags = flags; idesc->ih_ithd = ithd; idesc->ih_name = malloc(strlen(name) + 1, M_DEVBUF, M_WAITOK); if (idesc->ih_name == NULL) { free(idesc, M_DEVBUF); return (NULL); } strcpy(idesc->ih_name, name); /* Slow interrupts got set up above. */ if ((flags & INTR_FAST) && (icu_setup(irq, idesc->ih_handler, idesc->ih_argument, idesc->ih_flags) != 0) ) { if (bootverbose) printf("\tinthand_add(irq%d) failed, result=%d\n", irq, errcode); free(idesc->ih_name, M_DEVBUF); free(idesc, M_DEVBUF); return NULL; } head = ithd->it_ih; /* look at chain of handlers */ if (head) { while (head->ih_next != NULL) head = head->ih_next; /* find the end */ head->ih_next = idesc; /* hook it in there */ } else ithd->it_ih = idesc; /* put it up front */ update_intrname(irq, idesc->ih_name); return (idesc); } /* * Deactivate and remove linked list the interrupt handler descriptor * data connected created by an earlier call of inthand_add(), then * adjust the interrupt masks if necessary. * * Return the memory held by the interrupt handler descriptor data * structure to the system. First ensure the handler is not actively * in use. */ int inthand_remove(struct intrhand *idesc) { struct ithd *ithd; /* descriptor for the IRQ */ struct intrhand *ih; /* chain of handlers */ if (idesc == NULL) return (-1); ithd = idesc->ih_ithd; ih = ithd->it_ih; if (ih == idesc) /* first in the chain */ ithd->it_ih = idesc->ih_next; /* unhook it */ else { while ((ih != NULL) && (ih->ih_next != idesc) ) ih = ih->ih_next; if (ih->ih_next != idesc) return (-1); ih->ih_next = ih->ih_next->ih_next; } if (ithd->it_ih == NULL) { /* no handlers left, */ icu_unset(ithd->irq, idesc->ih_handler); ithds[ithd->irq] = NULL; if ((idesc->ih_flags & INTR_FAST) == 0) { mtx_enter(&sched_lock, MTX_SPIN); if (ithd->it_proc->p_stat == SWAIT) { ithd->it_proc->p_stat = SRUN; setrunqueue(ithd->it_proc); /* * We don't do an ast here because we really * don't care when it runs next. * * XXX: should we lower the threads priority? */ } mtx_exit(&sched_lock, MTX_SPIN); } } free(idesc->ih_name, M_DEVBUF); free(idesc, M_DEVBUF); return (0); }