diff --git a/sys/dev/mpi3mr/mpi/mpi30_api.h b/sys/dev/mpi3mr/mpi/mpi30_api.h index 0c070672a16b..8b05deb7717c 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_api.h +++ b/sys/dev/mpi3mr/mpi/mpi30_api.h @@ -1,57 +1,57 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ #ifndef MPI30_API_H #define MPI30_API_H 1 #include "mpi30_type.h" #include "mpi30_transport.h" #include "mpi30_cnfg.h" #include "mpi30_image.h" #include "mpi30_init.h" #include "mpi30_ioc.h" #include "mpi30_pci.h" #include "mpi30_raid.h" #include "mpi30_sas.h" #include "mpi30_targ.h" #include "mpi30_tool.h" #endif /* MPI30_API_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_cnfg.h b/sys/dev/mpi3mr/mpi/mpi30_cnfg.h index 410ed0471f78..d4cec3330a56 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_cnfg.h +++ b/sys/dev/mpi3mr/mpi/mpi30_cnfg.h @@ -1,3935 +1,4125 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ #ifndef MPI30_CNFG_H #define MPI30_CNFG_H 1 /***************************************************************************** * Configuration Page Types * ****************************************************************************/ #define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00) #define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01) #define MPI3_CONFIG_PAGETYPE_IOC (0x02) #define MPI3_CONFIG_PAGETYPE_DRIVER (0x03) #define MPI3_CONFIG_PAGETYPE_SECURITY (0x04) #define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11) #define MPI3_CONFIG_PAGETYPE_DEVICE (0x12) #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20) #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21) #define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23) #define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24) #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30) #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31) #define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33) /***************************************************************************** * Configuration Page Attributes * ****************************************************************************/ #define MPI3_CONFIG_PAGEATTR_MASK (0xF0) +#define MPI3_CONFIG_PAGEATTR_SHIFT (4) #define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00) #define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10) #define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20) /***************************************************************************** * Configuration Page Actions * ****************************************************************************/ #define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00) #define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01) #define MPI3_CONFIG_ACTION_READ_CURRENT (0x02) #define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03) #define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04) #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05) /***************************************************************************** * Configuration Page Addressing * ****************************************************************************/ /**** Device PageAddress Format ****/ #define MPI3_DEVICE_PGAD_FORM_MASK (0xF0000000) +#define MPI3_DEVICE_PGAD_FORM_SHIFT (28) #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) #define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000) #define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) +#define MPI3_DEVICE_PGAD_HANDLE_SHIFT (0) /**** SAS Expander PageAddress Format ****/ #define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SAS_EXPAND_PGAD_FORM_SHIFT (28) #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000) #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000) #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) +#define MPI3_SAS_EXPAND_PGAD_HANDLE_SHIFT (0) /**** SAS Phy PageAddress Format ****/ #define MPI3_SAS_PHY_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SAS_PHY_PGAD_FORM_SHIFT (28) #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) +#define MPI3_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0) /**** SAS Port PageAddress Format ****/ #define MPI3_SASPORT_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SASPORT_PGAD_FORM_SHIFT (28) #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) #define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000FF) +#define MPI3_SASPORT_PGAD_PORT_NUMBER_SHIFT (0) /**** Enclosure PageAddress Format ****/ #define MPI3_ENCLOS_PGAD_FORM_MASK (0xF0000000) +#define MPI3_ENCLOS_PGAD_FORM_SHIFT (28) #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) #define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000) #define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) +#define MPI3_ENCLOS_PGAD_HANDLE_SHIFT (0) /**** PCIe Switch PageAddress Format ****/ #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) +#define MPI3_PCIE_SWITCH_PGAD_FORM_SHIFT (28) #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000) #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000) #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) +#define MPI3_PCIE_SWITCH_PGAD_HANDLE_SHIFT (0) /**** PCIe Link PageAddress Format ****/ #define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) +#define MPI3_PCIE_LINK_PGAD_FORM_SHIFT (28) #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000FF) +#define MPI3_PCIE_LINK_PGAD_LINKNUM_SHIFT (0) /**** Security PageAddress Format ****/ #define MPI3_SECURITY_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SECURITY_PGAD_FORM_SHIFT (28) #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000) #define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000) #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000FF00) #define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8) #define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000FF) +#define MPI3_SECURITY_PGAD_SLOT_SHIFT (0) + +/**** Instance PageAddress Format ****/ +#define MPI3_INSTANCE_PGAD_INSTANCE_MASK (0x0000FFFF) +#define MPI3_INSTANCE_PGAD_INSTANCE_SHIFT (0) + /***************************************************************************** * Configuration Request Message * ****************************************************************************/ typedef struct _MPI3_CONFIG_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ - U16 Reserved0A; /* 0x0A */ + U8 ProxyIOCNumber; /* 0x0A */ + U8 Reserved0B; /* 0x0B */ U8 PageVersion; /* 0x0C */ U8 PageNumber; /* 0x0D */ U8 PageType; /* 0x0E */ U8 Action; /* 0x0F */ U32 PageAddress; /* 0x10 */ U16 PageLength; /* 0x14 */ U16 Reserved16; /* 0x16 */ U32 Reserved18[2]; /* 0x18 */ MPI3_SGE_UNION SGL; /* 0x20 */ } MPI3_CONFIG_REQUEST, MPI3_POINTER PTR_MPI3_CONFIG_REQUEST, Mpi3ConfigRequest_t, MPI3_POINTER pMpi3ConfigRequest_t; /***************************************************************************** * Configuration Pages * ****************************************************************************/ /***************************************************************************** * Configuration Page Header * ****************************************************************************/ typedef struct _MPI3_CONFIG_PAGE_HEADER { U8 PageVersion; /* 0x00 */ U8 Reserved01; /* 0x01 */ U8 PageNumber; /* 0x02 */ U8 PageAttribute; /* 0x03 */ U16 PageLength; /* 0x04 */ U8 PageType; /* 0x06 */ U8 Reserved07; /* 0x07 */ } MPI3_CONFIG_PAGE_HEADER, MPI3_POINTER PTR_MPI3_CONFIG_PAGE_HEADER, Mpi3ConfigPageHeader_t, MPI3_POINTER pMpi3ConfigPageHeader_t; /***************************************************************************** * Common definitions used by Configuration Pages * ****************************************************************************/ /**** Defines for NegotiatedLinkRates ****/ #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xF0) #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4) #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0F) #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0) /*** Below defines are used in both the PhysicalLinkRate and ***/ /*** LogicalLinkRate fields above. ***/ /*** (by applying the proper _SHIFT value) ***/ #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) #define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08) #define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09) #define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0A) #define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0B) #define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0C) /**** Defines for the AttachedPhyInfo field ****/ #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) #define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000F) +#define MPI3_SAS_APHYINFO_REASON_SHIFT (0) #define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) #define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001) #define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009) /**** Defines for the PhyInfo field ****/ #define MPI3_SAS_PHYINFO_STATUS_MASK (0xC0000000) #define MPI3_SAS_PHYINFO_STATUS_SHIFT (30) #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000) #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000) #define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000) #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) +#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SHIFT (27) #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000) #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000) #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000) #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000) #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26) #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000) #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT (25) #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK (0x01000000) #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT (24) #define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN (0x00200000) #define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000) #define MPI3_SAS_PHYINFO_REASON_MASK (0x000F0000) +#define MPI3_SAS_PHYINFO_REASON_SHIFT (16) #define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) #define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000) #define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000) #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) #define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000F00) #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8) #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000F0) +#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SHIFT (4) #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000) #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010) #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020) /**** Defines for the ProgrammedLinkRate field ****/ #define MPI3_SAS_PRATE_MAX_RATE_MASK (0xF0) +#define MPI3_SAS_PRATE_MAX_RATE_SHIFT (4) #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) #define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80) #define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90) #define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xA0) #define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xB0) #define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xC0) #define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0F) +#define MPI3_SAS_PRATE_MIN_RATE_SHIFT (0) #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) #define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08) #define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09) #define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0A) #define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0B) #define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0C) /**** Defines for the HwLinkRate field ****/ #define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xF0) +#define MPI3_SAS_HWRATE_MAX_RATE_SHIFT (4) #define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80) #define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90) #define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xA0) #define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xB0) #define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xC0) #define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0F) +#define MPI3_SAS_HWRATE_MIN_RATE_SHIFT (0) #define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08) #define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09) #define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0A) #define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0B) #define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0C) /**** Defines for the Slot field ****/ #define MPI3_SLOT_INVALID (0xFFFF) /**** Defines for the SlotIndex field ****/ #define MPI3_SLOT_INDEX_INVALID (0xFFFF) /**** Defines for the LinkChangeCount fields ****/ #define MPI3_LINK_CHANGE_COUNT_INVALID (0xFFFF) /**** Defines for the RateChangeCount fields ****/ #define MPI3_RATE_CHANGE_COUNT_INVALID (0xFFFF) /**** Defines for the Temp Sensor Location field ****/ #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL (0x0) #define MPI3_TEMP_SENSOR_LOCATION_INLET (0x1) #define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2) #define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3) /***************************************************************************** * Manufacturing Configuration Pages * ****************************************************************************/ #define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000) /* MPI v3.0 SAS Products */ #define MPI3_MFGPAGE_DEVID_SAS4116 (0x00A5) #define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00B3) #define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00B4) #define MPI3_MFGPAGE_DEVID_SAS5116_MPI_NS (0x00B5) #define MPI3_MFGPAGE_DEVID_SAS5116_NVME_NS (0x00B6) #define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00B8) +#define MPI3_MFGPAGE_DEVID_SAS5248_MPI (0x00F0) +#define MPI3_MFGPAGE_DEVID_SAS5248_MPI_NS (0x00F1) +#define MPI3_MFGPAGE_DEVID_SAS5248_PCIE_SWITCH (0x00F2) /***************************************************************************** * Manufacturing Page 0 * ****************************************************************************/ typedef struct _MPI3_MAN_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 ChipRevision[8]; /* 0x08 */ U8 ChipName[32]; /* 0x10 */ U8 BoardName[32]; /* 0x30 */ U8 BoardAssembly[32]; /* 0x50 */ U8 BoardTracerNumber[32]; /* 0x70 */ U32 BoardPower; /* 0x90 */ U32 Reserved94; /* 0x94 */ U32 Reserved98; /* 0x98 */ U8 OEM; /* 0x9C */ U8 ProfileIdentifier; /* 0x9D */ U16 Flags; /* 0x9E */ U8 BoardMfgDay; /* 0xA0 */ U8 BoardMfgMonth; /* 0xA1 */ U16 BoardMfgYear; /* 0xA2 */ U8 BoardReworkDay; /* 0xA4 */ U8 BoardReworkMonth; /* 0xA5 */ U16 BoardReworkYear; /* 0xA6 */ U8 BoardRevision[8]; /* 0xA8 */ U8 EPackFRU[16]; /* 0xB0 */ U8 ProductName[256]; /* 0xC0 */ } MPI3_MAN_PAGE0, MPI3_POINTER PTR_MPI3_MAN_PAGE0, Mpi3ManPage0_t, MPI3_POINTER pMpi3ManPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN0_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_MAN0_FLAGS_SWITCH_PRESENT (0x0002) #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT (0x0001) /***************************************************************************** * Manufacturing Page 1 * ****************************************************************************/ #define MPI3_MAN1_VPD_SIZE (512) typedef struct _MPI3_MAN_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08[2]; /* 0x08 */ U8 VPD[MPI3_MAN1_VPD_SIZE]; /* 0x10 */ } MPI3_MAN_PAGE1, MPI3_POINTER PTR_MPI3_MAN_PAGE1, Mpi3ManPage1_t, MPI3_POINTER pMpi3ManPage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN1_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Page 2 * ****************************************************************************/ typedef struct _MPI3_MAN_PAGE2 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 Flags; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U32 Reserved0C[3]; /* 0x0C */ U8 OEMBoardTracerNumber[32]; /* 0x18 */ } MPI3_MAN_PAGE2, MPI3_POINTER PTR_MPI3_MAN_PAGE2, Mpi3ManPage2_t, MPI3_POINTER pMpi3ManPage2_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN2_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_MAN2_FLAGS_TRACER_PRESENT (0x01) /***************************************************************************** * Manufacturing Page 5 * ****************************************************************************/ typedef struct _MPI3_MAN5_PHY_ENTRY { U64 IOC_WWID; /* 0x00 */ U64 DeviceName; /* 0x08 */ U64 SATA_WWID; /* 0x10 */ } MPI3_MAN5_PHY_ENTRY, MPI3_POINTER PTR_MPI3_MAN5_PHY_ENTRY, Mpi3Man5PhyEntry_t, MPI3_POINTER pMpi3Man5PhyEntry_t; #ifndef MPI3_MAN5_PHY_MAX #define MPI3_MAN5_PHY_MAX (1) #endif /* MPI3_MAN5_PHY_MAX */ typedef struct _MPI3_MAN_PAGE5 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 NumPhys; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U32 Reserved0C; /* 0x0C */ MPI3_MAN5_PHY_ENTRY Phy[MPI3_MAN5_PHY_MAX]; /* 0x10 */ } MPI3_MAN_PAGE5, MPI3_POINTER PTR_MPI3_MAN_PAGE5, Mpi3ManPage5_t, MPI3_POINTER pMpi3ManPage5_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN5_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Page 6 * ****************************************************************************/ typedef struct _MPI3_MAN6_GPIO_ENTRY { U8 FunctionCode; /* 0x00 */ U8 FunctionFlags; /* 0x01 */ U16 Flags; /* 0x02 */ U8 Param1; /* 0x04 */ U8 Param2; /* 0x05 */ U16 Reserved06; /* 0x06 */ U32 Param3; /* 0x08 */ } MPI3_MAN6_GPIO_ENTRY, MPI3_POINTER PTR_MPI3_MAN6_GPIO_ENTRY, Mpi3Man6GpioEntry_t, MPI3_POINTER pMpi3Man6GpioEntry_t; /**** Defines for the FunctionCode field ****/ #define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00) #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01) #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02) #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03) #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04) #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05) #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06) #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07) #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08) #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0A) #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0B) #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0C) #define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE (0x0D) #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0E) #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0F) #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10) #define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11) #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12) #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP (0x13) #define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER (0x14) #define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY (0x15) #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL (0x16) #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT (0x17) #define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE (0x18) #define MPI3_MAN6_GPIO_FUNCTION_MGMT_CONTROLLER_RESET (0x19) /**** Defines for FunctionFlags when FunctionCode is ISTWI_RESET ****/ #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01) +#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_SHIFT (0) #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00) #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01) /**** Defines for Param1 (Flags) when FunctionCode is EXT_INTERRUPT ****/ #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xF0) +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_SHIFT (4) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED (0x02) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_SHIFT (0) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) +/**** Defines for Param1 (LEVEL) when FunctionCode is OVER_TEMPERATURE ****/ +#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_WARNING (0x00) +#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_CRITICAL (0x01) +#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_FATAL (0x02) + /**** Defines for Param1 (PHY STATE) when FunctionCode is PORT_STATUS_GREEN ****/ #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00) #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01) /**** Defines for Param1 (INTERFACE_SIGNAL) when FunctionCode is CABLE_MANAGEMENT ****/ #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00) #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01) #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02) /**** Defines for Param1 (LICENSE_TYPE) when FunctionCode is LICENSE ****/ #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00) /**** Defines for the Flags field ****/ #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100) +#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SHIFT (8) #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100) #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000) #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00C0) +#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_SHIFT (6) #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000) #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040) #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080) #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00C0) #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030) #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4) #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008) #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004) #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003) +#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_SHIFT (0) #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000) #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001) #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002) #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003) #ifndef MPI3_MAN6_GPIO_MAX #define MPI3_MAN6_GPIO_MAX (1) #endif /* MPI3_MAN6_GPIO_MAX */ typedef struct _MPI3_MAN_PAGE6 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U16 Flags; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U8 NumGPIO; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_MAN6_GPIO_ENTRY GPIO[MPI3_MAN6_GPIO_MAX]; /* 0x10 */ } MPI3_MAN_PAGE6, MPI3_POINTER PTR_MPI3_MAN_PAGE6, Mpi3ManPage6_t, MPI3_POINTER pMpi3ManPage6_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN6_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001) /***************************************************************************** * Manufacturing Page 7 * ****************************************************************************/ typedef struct _MPI3_MAN7_RECEPTACLE_INFO { U32 Name[4]; /* 0x00 */ U8 Location; /* 0x10 */ U8 ConnectorType; /* 0x11 */ U8 PEDClk; /* 0x12 */ U8 ConnectorID; /* 0x13 */ U32 Reserved14; /* 0x14 */ } MPI3_MAN7_RECEPTACLE_INFO, MPI3_POINTER PTR_MPI3_MAN7_RECEPTACLE_INFO, Mpi3Man7ReceptacleInfo_t, MPI3_POINTER pMpi3Man7ReceptacleInfo_t; /**** Defines for Location field ****/ #define MPI3_MAN7_LOCATION_UNKNOWN (0x00) #define MPI3_MAN7_LOCATION_INTERNAL (0x01) #define MPI3_MAN7_LOCATION_EXTERNAL (0x02) #define MPI3_MAN7_LOCATION_VIRTUAL (0x03) #define MPI3_MAN7_LOCATION_HOST (0x04) /**** Defines for ConnectorType - Use definitions from SES-4 ****/ #define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO (0x00) /**** Defines for PEDClk field ****/ #define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10) +#define MPI3_MAN7_PEDCLK_ROUTING_SHIFT (4) #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00) #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10) #define MPI3_MAN7_PEDCLK_ID_MASK (0x0F) +#define MPI3_MAN7_PEDCLK_ID_SHIFT (0) #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX #define MPI3_MAN7_RECEPTACLE_INFO_MAX (1) #endif /* MPI3_MAN7_RECEPTACLE_INFO_MAX */ typedef struct _MPI3_MAN_PAGE7 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Flags; /* 0x08 */ U8 NumReceptacles; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ U32 EnclosureName[4]; /* 0x10 */ MPI3_MAN7_RECEPTACLE_INFO ReceptacleInfo[MPI3_MAN7_RECEPTACLE_INFO_MAX]; /* 0x20 */ /* variable length array */ } MPI3_MAN_PAGE7, MPI3_POINTER PTR_MPI3_MAN_PAGE7, Mpi3ManPage7_t, MPI3_POINTER pMpi3ManPage7_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN7_PAGEVERSION (0x00) /**** Defines for Flags field ****/ #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01) +#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_SHIFT (0) #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00) #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01) /***************************************************************************** * Manufacturing Page 8 * ****************************************************************************/ typedef struct _MPI3_MAN8_PHY_INFO { U8 ReceptacleID; /* 0x00 */ U8 ConnectorLane; /* 0x01 */ U16 Reserved02; /* 0x02 */ U16 Slotx1; /* 0x04 */ U16 Slotx2; /* 0x06 */ U16 Slotx4; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U32 Reserved0C; /* 0x0C */ } MPI3_MAN8_PHY_INFO, MPI3_POINTER PTR_MPI3_MAN8_PHY_INFO, Mpi3Man8PhyInfo_t, MPI3_POINTER pMpi3Man8PhyInfo_t; /**** Defines for ReceptacleID field ****/ #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED (0xFF) /**** Defines for ConnectorLane field ****/ #define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED (0xFF) #ifndef MPI3_MAN8_PHY_INFO_MAX #define MPI3_MAN8_PHY_INFO_MAX (1) #endif /* MPI3_MAN8_PHY_INFO_MAX */ typedef struct _MPI3_MAN_PAGE8 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumPhys; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_MAN8_PHY_INFO PhyInfo[MPI3_MAN8_PHY_INFO_MAX]; /* 0x10 */ /* variable length array */ } MPI3_MAN_PAGE8, MPI3_POINTER PTR_MPI3_MAN_PAGE8, Mpi3ManPage8_t, MPI3_POINTER pMpi3ManPage8_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN8_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Page 9 * ****************************************************************************/ typedef struct _MPI3_MAN9_RSRC_ENTRY { U32 Maximum; /* 0x00 */ U32 Decrement; /* 0x04 */ U32 Minimum; /* 0x08 */ U32 Actual; /* 0x0C */ } MPI3_MAN9_RSRC_ENTRY, MPI3_POINTER PTR_MPI3_MAN9_RSRC_ENTRY, Mpi3Man9RsrcEntry_t, MPI3_POINTER pMpi3Man9RsrcEntry_t; typedef enum _MPI3_MAN9_RESOURCES { MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0, MPI3_MAN9_RSRC_TARGET_CMDS = 1, MPI3_MAN9_RSRC_RESERVED02 = 2, MPI3_MAN9_RSRC_NVME = 3, MPI3_MAN9_RSRC_INITIATORS = 4, MPI3_MAN9_RSRC_VDS = 5, MPI3_MAN9_RSRC_ENCLOSURES = 6, MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7, MPI3_MAN9_RSRC_EXPANDERS = 8, MPI3_MAN9_RSRC_PCIE_SWITCHES = 9, MPI3_MAN9_RSRC_RESERVED10 = 10, MPI3_MAN9_RSRC_HOST_PD_DRIVES = 11, MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES = 12, MPI3_MAN9_RSRC_RAID_PD_DRIVES = 13, MPI3_MAN9_RSRC_DRV_DIAG_BUF = 14, MPI3_MAN9_RSRC_NAMESPACE_COUNT = 15, MPI3_MAN9_RSRC_NUM_RESOURCES } MPI3_MAN9_RESOURCES; #define MPI3_MAN9_MIN_OUTSTANDING_REQS (1) #define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000) #define MPI3_MAN9_MIN_TARGET_CMDS (0) #define MPI3_MAN9_MAX_TARGET_CMDS (65535) #define MPI3_MAN9_MIN_NVME_TARGETS (0) /* Max NVMe Targets is product specific */ #define MPI3_MAN9_MIN_INITIATORS (0) /* Max Initiators is product specific */ #define MPI3_MAN9_MIN_VDS (0) /* Max VDs is product specific */ #define MPI3_MAN9_MIN_ENCLOSURES (1) #define MPI3_MAN9_MAX_ENCLOSURES (65535) #define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0) /* Max Enclosure Phys is product specific */ #define MPI3_MAN9_MIN_EXPANDERS (0) #define MPI3_MAN9_MAX_EXPANDERS (65535) #define MPI3_MAN9_MIN_PCIE_SWITCHES (0) /* Max PCIe Switches is product specific */ #define MPI3_MAN9_MIN_HOST_PD_DRIVES (0) /* Max Host PD Drives is product specific */ #define MPI3_MAN9_ADV_HOST_PD_DRIVES (0) /* Max Advanced Host PD Drives is product specific */ #define MPI3_MAN9_RAID_PD_DRIVES (0) /* Max RAID PD Drives is product specific */ #define MPI3_MAN9_DRIVER_DIAG_BUFFER (0) /* Max Driver Diag Buffer is product specific */ #define MPI3_MAN9_MIN_NAMESPACE_COUNT (1) #define MPI3_MAN9_MIN_EXPANDERS (0) #define MPI3_MAN9_MAX_EXPANDERS (65535) typedef struct _MPI3_MAN_PAGE9 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 NumResources; /* 0x08 */ U8 Reserved09; /* 0x09 */ U16 Reserved0A; /* 0x0A */ U32 Reserved0C; /* 0x0C */ U32 Reserved10; /* 0x10 */ U32 Reserved14; /* 0x14 */ U32 Reserved18; /* 0x18 */ U32 Reserved1C; /* 0x1C */ MPI3_MAN9_RSRC_ENTRY Resource[MPI3_MAN9_RSRC_NUM_RESOURCES]; /* 0x20 */ } MPI3_MAN_PAGE9, MPI3_POINTER PTR_MPI3_MAN_PAGE9, Mpi3ManPage9_t, MPI3_POINTER pMpi3ManPage9_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN9_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Page 10 * ****************************************************************************/ typedef struct _MPI3_MAN10_ISTWI_CTRLR_ENTRY { U16 TargetAddress; /* 0x00 */ U16 Flags; /* 0x02 */ U8 SCLLowOverride; /* 0x04 */ U8 SCLHighOverride; /* 0x05 */ U16 Reserved06; /* 0x06 */ } MPI3_MAN10_ISTWI_CTRLR_ENTRY, MPI3_POINTER PTR_MPI3_MAN10_ISTWI_CTRLR_ENTRY, Mpi3Man10IstwiCtrlrEntry_t, MPI3_POINTER pMpi3Man10IstwiCtrlrEntry_t; /**** Defines for the Flags field ****/ #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_MASK (0xC000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_SHIFT (14) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_50_NS (0x0000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_10_NS (0x4000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_5_NS (0x8000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_0_NS (0xC000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_MASK (0x3000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_SHIFT (12) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_I2C (0x0000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_I3C (0x1000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_AUTO (0x2000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_MASK (0x0E00) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_SHIFT (9) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_12_5_MHZ (0x0000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_8_MHZ (0x0200) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_6_MHZ (0x0400) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_4_MHZ (0x0600) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_2_MHZ (0x0800) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000C) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT (0) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100_KHZ (0x0000) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400_KHZ (0x0004) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002) #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001) #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX #define MPI3_MAN10_ISTWI_CTRLR_MAX (1) #endif /* MPI3_MAN10_ISTWI_CTRLR_MAX */ typedef struct _MPI3_MAN_PAGE10 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumISTWICtrl; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_MAN10_ISTWI_CTRLR_ENTRY ISTWIController[MPI3_MAN10_ISTWI_CTRLR_MAX]; /* 0x10 */ } MPI3_MAN_PAGE10, MPI3_POINTER PTR_MPI3_MAN_PAGE10, Mpi3ManPage10_t, MPI3_POINTER pMpi3ManPage10_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN10_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Page 11 * ****************************************************************************/ typedef struct _MPI3_MAN11_MUX_DEVICE_FORMAT { U8 MaxChannel; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U32 Reserved04; /* 0x04 */ } MPI3_MAN11_MUX_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_MUX_DEVICE_FORMAT, Mpi3Man11MuxDeviceFormat_t, MPI3_POINTER pMpi3Man11MuxDeviceFormat_t; typedef struct _MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT { U8 Type; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U8 TempChannel[4]; /* 0x04 */ } MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT, Mpi3Man11TempSensorDeviceFormat_t, MPI3_POINTER pMpi3Man11TempSensorDeviceFormat_t; /**** Defines for the Type field ****/ #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00) #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01) #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02) #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B (0x03) /**** Define for the TempChannel field ****/ #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK (0xE0) #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT (5) /**** for the Location field values - use MPI3_TEMP_SENSOR_LOCATION_ defines ****/ #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01) typedef struct _MPI3_MAN11_SEEPROM_DEVICE_FORMAT { U8 Size; /* 0x00 */ U8 PageWriteSize; /* 0x01 */ U16 Reserved02; /* 0x02 */ U32 Reserved04; /* 0x04 */ } MPI3_MAN11_SEEPROM_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_SEEPROM_DEVICE_FORMAT, Mpi3Man11SeepromDeviceFormat_t, MPI3_POINTER pMpi3Man11SeepromDeviceFormat_t; /**** Defines for the Size field ****/ #define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01) #define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02) #define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03) #define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04) #define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05) #define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06) #define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07) #define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08) typedef struct _MPI3_MAN11_DDR_SPD_DEVICE_FORMAT { U8 Channel; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U32 Reserved04; /* 0x04 */ } MPI3_MAN11_DDR_SPD_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_DDR_SPD_DEVICE_FORMAT, Mpi3Man11DdrSpdDeviceFormat_t, MPI3_POINTER pMpi3Man11DdrSpdDeviceFormat_t; typedef struct _MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT { U8 Type; /* 0x00 */ U8 ReceptacleID; /* 0x01 */ U16 Reserved02; /* 0x02 */ U32 Reserved04; /* 0x04 */ } MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT, Mpi3Man11CableMgmtDeviceFormat_t, MPI3_POINTER pMpi3Man11CableMgmtDeviceFormat_t; /**** Defines for the Type field ****/ #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00) typedef struct _MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT { U16 Flags; /* 0x00 */ U16 Reserved02; /* 0x02 */ } MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT, Mpi3Man11BkplaneSpecUBMFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecUBMFormat_t; /**** Defines for the Flags field ****/ #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING (0x0100) #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK (0x00F0) #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT (4) #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK (0x000F) #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) typedef struct _MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT { U16 Flags; /* 0x00 */ U8 Reserved02; /* 0x02 */ U8 Type; /* 0x03 */ } MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT, Mpi3Man11BkplaneSpecNonUBMFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecNonUBMFormat_t; /**** Defines for the Flags field ****/ #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK (0xF000) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT (12) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_MASK (0x0600) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_SHIFT (9) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_DEVICE_PRESENT (0x0000) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_SRIS (0x0400) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK (0x00C0) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_SHIFT (6) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4 (0x0000) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2 (0x0040) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1 (0x0080) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK (0x0030) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_SHIFT (4) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO (0x0000) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG (0x0010) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK (0x000F) #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) /**** Defines for the Type field ****/ #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP (0x00) typedef union _MPI3_MAN11_BKPLANE_SPEC_FORMAT { MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT Ubm; MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT NonUbm; } MPI3_MAN11_BKPLANE_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_FORMAT, Mpi3Man11BkplaneSpecFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecFormat_t; typedef struct _MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT { U8 Type; /* 0x00 */ U8 ReceptacleID; /* 0x01 */ U8 ResetInfo; /* 0x02 */ U8 Reserved03; /* 0x03 */ MPI3_MAN11_BKPLANE_SPEC_FORMAT BackplaneMgmtSpecific; /* 0x04 */ } MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT, Mpi3Man11BkplaneMgmtDeviceFormat_t, MPI3_POINTER pMpi3Man11BkplaneMgmtDeviceFormat_t; /**** Defines for the Type field ****/ #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM (0x00) #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM (0x01) /**** Defines for the ResetInfo field ****/ #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK (0xF0) #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT (4) #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK (0x0F) #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT (0) typedef struct _MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT { U8 Type; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U32 Reserved04; /* 0x04 */ } MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT, Mpi3Man11GasGaugeDeviceFormat_t, MPI3_POINTER pMpi3Man11GasGaugeDeviceFormat_t; /**** Defines for the Type field ****/ #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD (0x00) typedef struct _MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT { U32 Reserved00; /* 0x00 */ U32 Reserved04; /* 0x04 */ } MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT, Mpi3Man11MgmtCtrlrDeviceFormat_t, MPI3_POINTER pMpi3Man11MgmtCtrlrDeviceFormat_t; typedef struct _MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT { U8 Flags; /* 0x00 */ U8 Reserved01; /* 0x01 */ U8 MinFanSpeed; /* 0x02 */ U8 MaxFanSpeed; /* 0x03 */ U32 Reserved04; /* 0x04 */ } MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT, Mpi3Man11BoardFanDeviceFormat_t, MPI3_POINTER pMpi3Man11BoardFanDeviceFormat_t; /**** Defines for the Flags field ****/ #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK (0x07) +#define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_SHIFT (0) #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 (0x00) typedef union _MPI3_MAN11_DEVICE_SPECIFIC_FORMAT { MPI3_MAN11_MUX_DEVICE_FORMAT Mux; MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT TempSensor; MPI3_MAN11_SEEPROM_DEVICE_FORMAT Seeprom; MPI3_MAN11_DDR_SPD_DEVICE_FORMAT DdrSpd; MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT CableMgmt; MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT BkplaneMgmt; MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT GasGauge; MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT MgmtController; MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT BoardFan; U32 Words[2]; } MPI3_MAN11_DEVICE_SPECIFIC_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_DEVICE_SPECIFIC_FORMAT, Mpi3Man11DeviceSpecificFormat_t, MPI3_POINTER pMpi3Man11DeviceSpecificFormat_t; typedef struct _MPI3_MAN11_ISTWI_DEVICE_FORMAT { U8 DeviceType; /* 0x00 */ U8 Controller; /* 0x01 */ U8 Reserved02; /* 0x02 */ U8 Flags; /* 0x03 */ U16 DeviceAddress; /* 0x04 */ U8 MuxChannel; /* 0x06 */ U8 MuxIndex; /* 0x07 */ MPI3_MAN11_DEVICE_SPECIFIC_FORMAT DeviceSpecific; /* 0x08 */ } MPI3_MAN11_ISTWI_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_ISTWI_DEVICE_FORMAT, Mpi3Man11IstwiDeviceFormat_t, MPI3_POINTER pMpi3Man11IstwiDeviceFormat_t; /**** Defines for the DeviceType field ****/ #define MPI3_MAN11_ISTWI_DEVTYPE_MUX (0x00) #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR (0x01) #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM (0x02) #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD (0x03) #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT (0x04) #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT (0x05) #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE (0x06) #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER (0x07) #define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN (0x08) /**** Defines for the Flags field ****/ #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT (0x01) #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX #define MPI3_MAN11_ISTWI_DEVICE_MAX (1) #endif /* MPI3_MAN11_ISTWI_DEVICE_MAX */ typedef struct _MPI3_MAN_PAGE11 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumISTWIDev; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_MAN11_ISTWI_DEVICE_FORMAT ISTWIDevice[MPI3_MAN11_ISTWI_DEVICE_MAX]; /* 0x10 */ } MPI3_MAN_PAGE11, MPI3_POINTER PTR_MPI3_MAN_PAGE11, Mpi3ManPage11_t, MPI3_POINTER pMpi3ManPage11_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN11_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Page 12 * ****************************************************************************/ #ifndef MPI3_MAN12_NUM_SGPIO_MAX #define MPI3_MAN12_NUM_SGPIO_MAX (1) #endif /* MPI3_MAN12_NUM_SGPIO_MAX */ typedef struct _MPI3_MAN12_SGPIO_INFO { U8 SlotCount; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U32 Reserved04; /* 0x04 */ U8 PhyOrder[32]; /* 0x08 */ } MPI3_MAN12_SGPIO_INFO, MPI3_POINTER PTR_MPI3_MAN12_SGPIO_INFO, Mpi3Man12SGPIOInfo_t, MPI3_POINTER pMpi3Man12SGPIOInfo_t; typedef struct _MPI3_MAN_PAGE12 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Flags; /* 0x08 */ U32 SClockFreq; /* 0x0C */ U32 ActivityModulation; /* 0x10 */ U8 NumSGPIO; /* 0x14 */ U8 Reserved15[3]; /* 0x15 */ U32 Reserved18; /* 0x18 */ U32 Reserved1C; /* 0x1C */ U32 Pattern[8]; /* 0x20 */ MPI3_MAN12_SGPIO_INFO SGPIOInfo[MPI3_MAN12_NUM_SGPIO_MAX]; /* 0x40 */ /* variable length */ } MPI3_MAN_PAGE12, MPI3_POINTER PTR_MPI3_MAN_PAGE12, Mpi3ManPage12_t, MPI3_POINTER pMpi3ManPage12_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN12_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED (0x0400) #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED (0x0200) #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100) #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004) #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002) +#define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_SHIFT (1) #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000) #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002) #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001) +#define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_SHIFT (0) #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000) #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001) /**** Defines for the SClockFreq field ****/ #define MPI3_MAN12_SIO_CLK_FREQ_MIN (32) /* 32 Hz min SIO Clk Freq */ #define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000) /* 100 KHz max SIO Clk Freq */ /**** Defines for the ActivityModulation field ****/ #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK (0x0000F000) #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT (12) #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK (0x00000F00) #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT (8) #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK (0x000000F0) #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT (4) #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK (0x0000000F) #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT (0) /*** Defines for the Pattern field ****/ #define MPI3_MAN12_PATTERN_RATE_MASK (0xE0000000) +#define MPI3_MAN12_PATTERN_RATE_SHIFT (29) #define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000) #define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000) #define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000) #define MPI3_MAN12_PATTERN_RATE_16_HZ (0x60000000) #define MPI3_MAN12_PATTERN_RATE_10_HZ (0x80000000) #define MPI3_MAN12_PATTERN_RATE_20_HZ (0xA0000000) #define MPI3_MAN12_PATTERN_RATE_40_HZ (0xC0000000) #define MPI3_MAN12_PATTERN_LENGTH_MASK (0x1F000000) #define MPI3_MAN12_PATTERN_LENGTH_SHIFT (24) #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK (0x00FFFFFF) #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT (0) /***************************************************************************** * Manufacturing Page 13 * ****************************************************************************/ #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX #define MPI3_MAN13_NUM_TRANSLATION_MAX (1) #endif /* MPI3_MAN13_NUM_TRANSLATION_MAX */ typedef struct _MPI3_MAN13_TRANSLATION_INFO { U32 SlotStatus; /* 0x00 */ U32 Mask; /* 0x04 */ U8 Activity; /* 0x08 */ U8 Locate; /* 0x09 */ U8 Error; /* 0x0A */ U8 Reserved0B; /* 0x0B */ } MPI3_MAN13_TRANSLATION_INFO, MPI3_POINTER PTR_MPI3_MAN13_TRANSLATION_INFO, Mpi3Man13TranslationInfo_t, MPI3_POINTER pMpi3Man13TranslationInfo_t; /**** Defines for the SlotStatus field ****/ #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT (0x20000000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF (0x10000000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY (0x00800000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING (0x00100000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT (0x00080000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL (0x00040000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY (0x00020000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK (0x00008000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE (0x00004000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE (0x00002000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000800) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY (0x00000400) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP (0x00000200) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT (0x00000100) #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE (0x00000040) /**** Defines for the Mask field - use MPI3_MAN13_TRANSLATION_SLOTSTATUS_ defines ****/ /**** Defines for the Activity, Locate, and Error fields ****/ #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF (0x00) #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON (0x01) #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 (0x02) #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 (0x03) #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 (0x04) #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 (0x05) #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 (0x06) #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 (0x07) #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 (0x08) #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 (0x09) #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY (0x0A) #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL (0x0B) typedef struct _MPI3_MAN_PAGE13 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 NumTrans; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U32 Reserved0C; /* 0x0C */ MPI3_MAN13_TRANSLATION_INFO Translation[MPI3_MAN13_NUM_TRANSLATION_MAX]; /* 0x10 */ /* variable length */ } MPI3_MAN_PAGE13, MPI3_POINTER PTR_MPI3_MAN_PAGE13, Mpi3ManPage13_t, MPI3_POINTER pMpi3ManPage13_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN13_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Page 14 * ****************************************************************************/ typedef struct _MPI3_MAN_PAGE14 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumSlotGroups; /* 0x0C */ U8 NumSlots; /* 0x0D */ U16 MaxCertChainLength; /* 0x0E */ U32 SealedSlots; /* 0x10 */ U32 PopulatedSlots; /* 0x14 */ U32 MgmtPTUpdatableSlots; /* 0x18 */ } MPI3_MAN_PAGE14, MPI3_POINTER PTR_MPI3_MAN_PAGE14, Mpi3ManPage14_t, MPI3_POINTER pMpi3ManPage14_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN14_PAGEVERSION (0x00) /**** Defines for the NumSlots field ****/ #define MPI3_MAN14_NUMSLOTS_MAX (32) /***************************************************************************** * Manufacturing Page 15 * ****************************************************************************/ #ifndef MPI3_MAN15_VERSION_RECORD_MAX #define MPI3_MAN15_VERSION_RECORD_MAX 1 #endif /* MPI3_MAN15_VERSION_RECORD_MAX */ typedef struct _MPI3_MAN15_VERSION_RECORD { U16 SPDMVersion; /* 0x00 */ U16 Reserved02; /* 0x02 */ } MPI3_MAN15_VERSION_RECORD, MPI3_POINTER PTR_MPI3_MAN15_VERSION_RECORD, Mpi3Man15VersionRecord_t, MPI3_POINTER pMpi3Man15VersionRecord_t; typedef struct _MPI3_MAN_PAGE15 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 NumVersionRecords; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U32 Reserved0C; /* 0x0C */ MPI3_MAN15_VERSION_RECORD VersionRecord[MPI3_MAN15_VERSION_RECORD_MAX]; /* 0x10 */ } MPI3_MAN_PAGE15, MPI3_POINTER PTR_MPI3_MAN_PAGE15, Mpi3ManPage15_t, MPI3_POINTER pMpi3ManPage15_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN15_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Page 16 * ****************************************************************************/ #ifndef MPI3_MAN16_CERT_ALGO_MAX #define MPI3_MAN16_CERT_ALGO_MAX 1 #endif /* MPI3_MAN16_CERT_ALGO_MAX */ typedef struct _MPI3_MAN16_CERTIFICATE_ALGORITHM { U8 SlotGroup; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U32 BaseAsymAlgo; /* 0x04 */ U32 BaseHashAlgo; /* 0x08 */ U32 Reserved0C[3]; /* 0x0C */ } MPI3_MAN16_CERTIFICATE_ALGORITHM, MPI3_POINTER PTR_MPI3_MAN16_CERTIFICATE_ALGORITHM, Mpi3Man16CertificateAlgorithm_t, MPI3_POINTER pMpi3Man16CertificateAlgorithm_t; typedef struct _MPI3_MAN_PAGE16 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumCertAlgos; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_MAN16_CERTIFICATE_ALGORITHM CertificateAlgorithm[MPI3_MAN16_CERT_ALGO_MAX]; /* 0x10 */ } MPI3_MAN_PAGE16, MPI3_POINTER PTR_MPI3_MAN_PAGE16, Mpi3ManPage16_t, MPI3_POINTER pMpi3ManPage16_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN16_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Page 17 * ****************************************************************************/ #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX #define MPI3_MAN17_HASH_ALGORITHM_MAX 1 #endif /* MPI3_MAN17_HASH_ALGORITHM_MAX */ typedef struct _MPI3_MAN17_HASH_ALGORITHM { U8 MeasSpecification; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U32 MeasurementHashAlgo; /* 0x04 */ U32 Reserved08[2]; /* 0x08 */ } MPI3_MAN17_HASH_ALGORITHM, MPI3_POINTER PTR_MPI3_MAN17_HASH_ALGORITHM, Mpi3Man17HashAlgorithm_t, MPI3_POINTER pMpi3Man17HashAlgorithm_t; typedef struct _MPI3_MAN_PAGE17 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumHashAlgos; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_MAN17_HASH_ALGORITHM HashAlgorithm[MPI3_MAN17_HASH_ALGORITHM_MAX]; /* 0x10 */ } MPI3_MAN_PAGE17, MPI3_POINTER PTR_MPI3_MAN_PAGE17, Mpi3ManPage17_t, MPI3_POINTER pMpi3ManPage17_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN17_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Page 20 * ****************************************************************************/ typedef struct _MPI3_MAN_PAGE20 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U32 NonpremiumFeatures; /* 0x0C */ U8 AllowedPersonalities; /* 0x10 */ U8 Reserved11[3]; /* 0x11 */ } MPI3_MAN_PAGE20, MPI3_POINTER PTR_MPI3_MAN_PAGE20, Mpi3ManPage20_t, MPI3_POINTER pMpi3ManPage20_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN20_PAGEVERSION (0x00) /**** Defines for the AllowedPersonalities field ****/ #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02) +#define MPI3_MAN20_ALLOWEDPERSON_RAID_SHIFT (1) #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02) #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00) #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01) +#define MPI3_MAN20_ALLOWEDPERSON_EHBA_SHIFT (0) #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01) #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00) /**** Defines for the NonpremiumFeatures field ****/ #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01) +#define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_SHIFT (0) #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00) #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01) /***************************************************************************** * Manufacturing Page 21 * ****************************************************************************/ typedef struct _MPI3_MAN_PAGE21 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U32 Flags; /* 0x0C */ } MPI3_MAN_PAGE21, MPI3_POINTER PTR_MPI3_MAN_PAGE21, Mpi3ManPage21_t, MPI3_POINTER pMpi3ManPage21_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN21_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x00000060) +#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_SHIFT (5) #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00000000) #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x00000020) #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x00000040) #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x00000008) +#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_SHIFT (3) #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00000000) #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x00000008) #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x00000001) +#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_SHIFT (0) #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00000000) #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x00000001) /***************************************************************************** * Manufacturing Page 22 * ****************************************************************************/ typedef struct _MPI3_MAN_PAGE22 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U16 NumEUI64; /* 0x0C */ U16 Reserved0E; /* 0x0E */ U64 BaseEUI64; /* 0x10 */ } MPI3_MAN_PAGE22, MPI3_POINTER PTR_MPI3_MAN_PAGE22, Mpi3ManPage22_t, MPI3_POINTER pMpi3ManPage22_t; /**** Defines for the PageVersion field ****/ #define MPI3_MAN22_PAGEVERSION (0x00) /***************************************************************************** * Manufacturing Pages 32-63 (ProductSpecific) * ****************************************************************************/ #ifndef MPI3_MAN_PROD_SPECIFIC_MAX #define MPI3_MAN_PROD_SPECIFIC_MAX (1) #endif /* MPI3_MAN_PROD_SPECIFIC_MAX */ typedef struct _MPI3_MAN_PAGE_PRODUCT_SPECIFIC { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 ProductSpecificInfo[MPI3_MAN_PROD_SPECIFIC_MAX]; /* 0x08 */ /* variable length array */ } MPI3_MAN_PAGE_PRODUCT_SPECIFIC, MPI3_POINTER PTR_MPI3_MAN_PAGE_PRODUCT_SPECIFIC, Mpi3ManPageProductSpecific_t, MPI3_POINTER pMpi3ManPageProductSpecific_t; /***************************************************************************** * IO Unit Configuration Pages * ****************************************************************************/ /***************************************************************************** * IO Unit Page 0 * ****************************************************************************/ typedef struct _MPI3_IO_UNIT_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U64 UniqueValue; /* 0x08 */ U32 NvdataVersionDefault; /* 0x10 */ U32 NvdataVersionPersistent; /* 0x14 */ } MPI3_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE0, Mpi3IOUnitPage0_t, MPI3_POINTER pMpi3IOUnitPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT0_PAGEVERSION (0x00) /***************************************************************************** * IO Unit Page 1 * ****************************************************************************/ typedef struct _MPI3_IO_UNIT_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Flags; /* 0x08 */ U8 DMDIoDelay; /* 0x0C */ U8 DMDReportPCIe; /* 0x0D */ U8 DMDReportSATA; /* 0x0E */ U8 DMDReportSAS; /* 0x0F */ } MPI3_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE1, Mpi3IOUnitPage1_t, MPI3_POINTER pMpi3IOUnitPage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT1_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030) +#define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_SHIFT (4) #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000) #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010) #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020) #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008) #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004) #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003) +#define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_SHIFT (0) #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000) #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001) #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002) /**** Defines for the DMDReport PCIe/SATA/SAS fields ****/ #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7F) +#define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_SHIFT (0) #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80) /***************************************************************************** * IO Unit Page 2 * ****************************************************************************/ #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX #define MPI3_IO_UNIT2_GPIO_VAL_MAX (1) #endif /* MPI3_IO_UNIT2_GPIO_VAL_MAX */ typedef struct _MPI3_IO_UNIT_PAGE2 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 GPIOCount; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U16 GPIOVal[MPI3_IO_UNIT2_GPIO_VAL_MAX]; /* 0x0C */ } MPI3_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE2, Mpi3IOUnitPage2_t, MPI3_POINTER pMpi3IOUnitPage2_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT2_PAGEVERSION (0x00) /**** Define for the GPIOVal field ****/ #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xFFFC) #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2) #define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001) +#define MPI3_IOUNIT2_GPIO_SETTING_SHIFT (0) #define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000) #define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001) /***************************************************************************** * IO Unit Page 3 * ****************************************************************************/ typedef enum _MPI3_IOUNIT3_THRESHOLD { MPI3_IOUNIT3_THRESHOLD_WARNING = 0, MPI3_IOUNIT3_THRESHOLD_CRITICAL = 1, MPI3_IOUNIT3_THRESHOLD_FATAL = 2, MPI3_IOUNIT3_THRESHOLD_LOW = 3, MPI3_IOUNIT3_NUM_THRESHOLDS } MPI3_IOUNIT3_THRESHOLD; typedef struct _MPI3_IO_UNIT3_SENSOR { U16 Flags; /* 0x00 */ U8 ThresholdMargin; /* 0x02 */ U8 Reserved03; /* 0x03 */ U16 Threshold[MPI3_IOUNIT3_NUM_THRESHOLDS]; /* 0x04 */ U32 Reserved0C; /* 0x0C */ U32 Reserved10; /* 0x10 */ U32 Reserved14; /* 0x14 */ } MPI3_IO_UNIT3_SENSOR, MPI3_POINTER PTR_MPI3_IO_UNIT3_SENSOR, Mpi3IOUnit3Sensor_t, MPI3_POINTER pMpi3IOUnit3Sensor_t; /**** Defines for the Flags field ****/ #define MPI3_IOUNIT3_SENSOR_FLAGS_LOW_THRESHOLD_VALID (0x0020) #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED (0x0010) #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED (0x0008) #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED (0x0004) #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED (0x0002) #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED (0x0001) #ifndef MPI3_IO_UNIT3_SENSOR_MAX #define MPI3_IO_UNIT3_SENSOR_MAX (1) #endif /* MPI3_IO_UNIT3_SENSOR_MAX */ typedef struct _MPI3_IO_UNIT_PAGE3 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumSensors; /* 0x0C */ U8 NominalPollInterval; /* 0x0D */ U8 WarningPollInterval; /* 0x0E */ U8 Reserved0F; /* 0x0F */ MPI3_IO_UNIT3_SENSOR Sensor[MPI3_IO_UNIT3_SENSOR_MAX]; /* 0x10 */ } MPI3_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE3, Mpi3IOUnitPage3_t, MPI3_POINTER pMpi3IOUnitPage3_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT3_PAGEVERSION (0x00) /***************************************************************************** * IO Unit Page 4 * ****************************************************************************/ typedef struct _MPI3_IO_UNIT4_SENSOR { U16 CurrentTemperature; /* 0x00 */ U16 Reserved02; /* 0x02 */ U8 Flags; /* 0x04 */ U8 Reserved05[3]; /* 0x05 */ U16 ISTWIIndex; /* 0x08 */ U8 Channel; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 Reserved0C; /* 0x0C */ } MPI3_IO_UNIT4_SENSOR, MPI3_POINTER PTR_MPI3_IO_UNIT4_SENSOR, Mpi3IOUnit4Sensor_t, MPI3_POINTER pMpi3IOUnit4Sensor_t; /**** Defines for the Flags field ****/ #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK (0xE0) #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT (5) /**** for the Location field values - use MPI3_TEMP_SENSOR_LOCATION_ defines ****/ #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID (0x01) /**** Defines for the ISTWIIndex field ****/ #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL (0xFFFF) /**** Defines for the Channel field ****/ #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED (0xFF) #ifndef MPI3_IO_UNIT4_SENSOR_MAX #define MPI3_IO_UNIT4_SENSOR_MAX (1) #endif /* MPI3_IO_UNIT4_SENSOR_MAX */ typedef struct _MPI3_IO_UNIT_PAGE4 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumSensors; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_IO_UNIT4_SENSOR Sensor[MPI3_IO_UNIT4_SENSOR_MAX]; /* 0x10 */ } MPI3_IO_UNIT_PAGE4, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE4, Mpi3IOUnitPage4_t, MPI3_POINTER pMpi3IOUnitPage4_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT4_PAGEVERSION (0x00) /***************************************************************************** * IO Unit Page 5 * ****************************************************************************/ typedef struct _MPI3_IO_UNIT5_SPINUP_GROUP { U8 MaxTargetSpinup; /* 0x00 */ U8 SpinupDelay; /* 0x01 */ U8 SpinupFlags; /* 0x02 */ U8 Reserved03; /* 0x03 */ } MPI3_IO_UNIT5_SPINUP_GROUP, MPI3_POINTER PTR_MPI3_IO_UNIT5_SPINUP_GROUP, Mpi3IOUnit5SpinupGroup_t, MPI3_POINTER pMpi3IOUnit5SpinupGroup_t; /**** Defines for the SpinupFlags field ****/ #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE (0x01) #ifndef MPI3_IO_UNIT5_PHY_MAX #define MPI3_IO_UNIT5_PHY_MAX (4) #endif /* MPI3_IO_UNIT5_PHY_MAX */ typedef struct _MPI3_IO_UNIT_PAGE5 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ MPI3_IO_UNIT5_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ U32 Reserved18; /* 0x18 */ U32 Reserved1C; /* 0x1C */ U16 DeviceShutdown; /* 0x20 */ U16 Reserved22; /* 0x22 */ U8 PCIeDeviceWaitTime; /* 0x24 */ U8 SATADeviceWaitTime; /* 0x25 */ U8 SpinupEnclDriveCount; /* 0x26 */ U8 SpinupEnclDelay; /* 0x27 */ U8 NumPhys; /* 0x28 */ U8 PEInitialSpinupDelay; /* 0x29 */ U8 TopologyStableTime; /* 0x2A */ U8 Flags; /* 0x2B */ U8 Phy[MPI3_IO_UNIT5_PHY_MAX]; /* 0x2C */ } MPI3_IO_UNIT_PAGE5, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE5, Mpi3IOUnitPage5_t, MPI3_POINTER pMpi3IOUnitPage5_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT5_PAGEVERSION (0x00) /**** Defines for the DeviceShutdown field ****/ #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION (0x00) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED (0x01) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED (0x02) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED (0x02) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER (0x03) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH (0x03) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK (0x0300) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT (8) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK (0x00C0) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT (6) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK (0x0030) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT (4) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK (0x000C) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT (2) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK (0x0003) #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT (0) /**** Defines for the Flags field ****/ #define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK (0x0C) #define MPI3_IOUNIT5_FLAGS_SATAPUIS_SHIFT (2) #define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED (0x00) #define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED (0x04) #define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED (0x08) #define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED (0x0C) #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02) #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01) /**** Defines for the Phy field ****/ #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03) +#define MPI3_IOUNIT5_PHY_SPINUP_GROUP_SHIFT (0) /***************************************************************************** * IO Unit Page 6 * ****************************************************************************/ typedef struct _MPI3_IO_UNIT_PAGE6 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 BoardPowerRequirement; /* 0x08 */ U32 PCISlotPowerAllocation; /* 0x0C */ U8 Flags; /* 0x10 */ U8 Reserved11[3]; /* 0x11 */ } MPI3_IO_UNIT_PAGE6, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE6, Mpi3IOUnitPage6_t, MPI3_POINTER pMpi3IOUnitPage6_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT6_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC (0x01) /***************************************************************************** * IO Unit Page 8 * ****************************************************************************/ #ifndef MPI3_IOUNIT8_DIGEST_MAX #define MPI3_IOUNIT8_DIGEST_MAX (1) #endif /* MPI3_IOUNIT8_DIGEST_MAX */ typedef union _MPI3_IOUNIT8_RAW_DIGEST { U32 Dword[16]; U16 Word[32]; U8 Byte[64]; } MPI3_IOUNIT8_RAW_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_RAW_DIGEST, Mpi3IOUnit8RawDigest_t, MPI3_POINTER pMpi3IOUnit8RawDigest_t; typedef struct _MPI3_IOUNIT8_METADATA_DIGEST { U8 SlotStatus; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U32 Reserved04[3]; /* 0x04 */ MPI3_IOUNIT8_RAW_DIGEST DigestData; /* 0x10 */ } MPI3_IOUNIT8_METADATA_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_METADATA_DIGEST, Mpi3IOUnit8MetadataDigest_t, MPI3_POINTER pMpi3IOUnit8MetadataDigest_t; /**** Defines for the SlotStatus field ****/ #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_UNUSED (0x00) #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_UPDATE_PENDING (0x01) #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_VALID (0x03) #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_INVALID (0x07) typedef union _MPI3_IOUNIT8_DIGEST { MPI3_IOUNIT8_RAW_DIGEST RawDigest[MPI3_IOUNIT8_DIGEST_MAX]; MPI3_IOUNIT8_METADATA_DIGEST MetadataDigest[MPI3_IOUNIT8_DIGEST_MAX]; } MPI3_IOUNIT8_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_DIGEST, Mpi3IOUnit8Digest_t, MPI3_POINTER pMpi3IOUnit8Digest_t; typedef struct _MPI3_IO_UNIT_PAGE8 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 SBMode; /* 0x08 */ U8 SBState; /* 0x09 */ U8 Flags; /* 0x0A */ U8 Reserved0A; /* 0x0B */ U8 NumSlots; /* 0x0C */ U8 SlotsAvailable; /* 0x0D */ U8 CurrentKeyEncryptionAlgo; /* 0x0E */ U8 KeyDigestHashAlgo; /* 0x0F */ MPI3_VERSION_UNION CurrentSvn; /* 0x10 */ U32 Reserved14; /* 0x14 */ U32 CurrentKey[128]; /* 0x18 */ MPI3_IOUNIT8_DIGEST Digest; /* 0x218 */ /* variable length */ } MPI3_IO_UNIT_PAGE8, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE8, Mpi3IOUnitPage8_t, MPI3_POINTER pMpi3IOUnitPage8_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT8_PAGEVERSION (0x00) /**** Defines for the SBMode field ****/ +#define MPI3_IOUNIT8_SBMODE_HARD_SECURE_RECERTIFIED (0x08) #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04) #define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02) #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01) /**** Defines for the SBState field ****/ #define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04) #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02) #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01) /**** Defines for the Flags field ****/ +#define MPI3_IOUNIT8_FLAGS_CURRENT_KEY_IOUNIT17 (0x08) #define MPI3_IOUNIT8_FLAGS_DIGESTFORM_MASK (0x07) +#define MPI3_IOUNIT8_FLAGS_DIGESTFORM_SHIFT (0) #define MPI3_IOUNIT8_FLAGS_DIGESTFORM_RAW (0x00) #define MPI3_IOUNIT8_FLAGS_DIGESTFORM_DIGEST_WITH_METADATA (0x01) +/**** Use MPI3_ENCRYPTION_ALGORITHM_ defines (see mpi30_image.h) for the CurrentKeyEncryptionAlgo field ****/ +/**** Use MPI3_HASH_ALGORITHM defines (see mpi30_image.h) for the KeyDigestHashAlgo field ****/ + /***************************************************************************** * IO Unit Page 9 * ****************************************************************************/ typedef struct _MPI3_IO_UNIT_PAGE9 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Flags; /* 0x08 */ U16 FirstDevice; /* 0x0C */ U16 Reserved0E; /* 0x0E */ } MPI3_IO_UNIT_PAGE9, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE9, Mpi3IOUnitPage9_t, MPI3_POINTER pMpi3IOUnitPage9_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT9_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK (0x00000006) #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT (1) #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE (0x00000000) #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE (0x00000002) #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE (0x00000004) #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x00000001) /**** Defines for the FirstDevice field ****/ #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xFFFF) +#define MPI3_IOUNIT9_FIRSTDEVICE_IN_DRIVER_PAGE_0 (0xFFFE) /***************************************************************************** * IO Unit Page 10 * ****************************************************************************/ typedef struct _MPI3_IO_UNIT_PAGE10 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 Flags; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U32 SiliconID; /* 0x0C */ U8 FWVersionMinor; /* 0x10 */ U8 FWVersionMajor; /* 0x11 */ U8 HWVersionMinor; /* 0x12 */ U8 HWVersionMajor; /* 0x13 */ U8 PartNumber[16]; /* 0x14 */ } MPI3_IO_UNIT_PAGE10, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE10, Mpi3IOUnitPage10_t, MPI3_POINTER pMpi3IOUnitPage10_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT10_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_IOUNIT10_FLAGS_VALID (0x01) #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK (0x02) +#define MPI3_IOUNIT10_FLAGS_ACTIVEID_SHIFT (1) #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION (0x00) #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02) #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED (0x80) /***************************************************************************** * IO Unit Page 11 * ****************************************************************************/ #ifndef MPI3_IOUNIT11_PROFILE_MAX #define MPI3_IOUNIT11_PROFILE_MAX (1) #endif /* MPI3_IOUNIT11_PROFILE_MAX */ typedef struct _MPI3_IOUNIT11_PROFILE { U8 ProfileIdentifier; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U16 MaxVDs; /* 0x04 */ U16 MaxHostPDs; /* 0x06 */ U16 MaxAdvHostPDs; /* 0x08 */ U16 MaxRAIDPDs; /* 0x0A */ U16 MaxNVMe; /* 0x0C */ U16 MaxOutstandingRequests; /* 0x0E */ U16 SubsystemID; /* 0x10 */ U16 Reserved12; /* 0x12 */ U32 Reserved14[2]; /* 0x14 */ } MPI3_IOUNIT11_PROFILE, MPI3_POINTER PTR_MPI3_IOUNIT11_PROFILE, Mpi3IOUnit11Profile_t, MPI3_POINTER pMpi3IOUnit11Profile_t; typedef struct _MPI3_IO_UNIT_PAGE11 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumProfiles; /* 0x0C */ U8 CurrentProfileIdentifier; /* 0x0D */ U16 Reserved0E; /* 0x0E */ MPI3_IOUNIT11_PROFILE Profile[MPI3_IOUNIT11_PROFILE_MAX]; /* 0x10 */ /* variable length */ } MPI3_IO_UNIT_PAGE11, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE11, Mpi3IOUnitPage11_t, MPI3_POINTER pMpi3IOUnitPage11_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT11_PAGEVERSION (0x00) /***************************************************************************** * IO Unit Page 12 * ****************************************************************************/ #ifndef MPI3_IOUNIT12_BUCKET_MAX #define MPI3_IOUNIT12_BUCKET_MAX (1) #endif /* MPI3_IOUNIT12_BUCKET_MAX */ typedef struct _MPI3_IOUNIT12_BUCKET { U8 CoalescingDepth; /* 0x00 */ U8 CoalescingTimeout; /* 0x01 */ U16 IOCountLowBoundary; /* 0x02 */ U32 Reserved04; /* 0x04 */ } MPI3_IOUNIT12_BUCKET, MPI3_POINTER PTR_MPI3_IOUNIT12_BUCKET, Mpi3IOUnit12Bucket_t, MPI3_POINTER pMpi3IOUnit12Bucket_t; typedef struct _MPI3_IO_UNIT_PAGE12 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Flags; /* 0x08 */ U32 Reserved0C[4]; /* 0x0C */ U8 NumBuckets; /* 0x1C */ U8 Reserved1D[3]; /* 0x1D */ MPI3_IOUNIT12_BUCKET Bucket[MPI3_IOUNIT12_BUCKET_MAX]; /* 0x20 */ /* variable length */ } MPI3_IO_UNIT_PAGE12, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE12, Mpi3IOUnitPage12_t, MPI3_POINTER pMpi3IOUnitPage12_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT12_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK (0x00000300) #define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT (8) #define MPI3_IOUNIT12_FLAGS_NUMPASSES_8 (0x00000000) #define MPI3_IOUNIT12_FLAGS_NUMPASSES_16 (0x00000100) #define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 (0x00000200) #define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 (0x00000300) #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK (0x00000003) +#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_SHIFT (0) #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED (0x00000000) #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US (0x00000001) #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS (0x00000002) #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS (0x00000003) /***************************************************************************** * IO Unit Page 13 * ****************************************************************************/ #ifndef MPI3_IOUNIT13_FUNC_MAX #define MPI3_IOUNIT13_FUNC_MAX (1) #endif /* MPI3_IOUNIT13_FUNC_MAX */ typedef struct _MPI3_IOUNIT13_ALLOWED_FUNCTION { U16 SubFunction; /* 0x00 */ U8 FunctionCode; /* 0x02 */ U8 FunctionFlags; /* 0x03 */ } MPI3_IOUNIT13_ALLOWED_FUNCTION, MPI3_POINTER PTR_MPI3_IOUNIT13_ALLOWED_FUNCTION, Mpi3IOUnit13AllowedFunction_t, MPI3_POINTER pMpi3IOUnit13AllowedFunction_t; /**** Defines for the FunctionFlags field ****/ #define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED (0x04) #define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED (0x02) #define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED (0x01) typedef struct _MPI3_IO_UNIT_PAGE13 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U16 Flags; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U8 NumAllowedFunctions; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_IOUNIT13_ALLOWED_FUNCTION AllowedFunction[MPI3_IOUNIT13_FUNC_MAX]; /* 0x10 */ /* variable length */ } MPI3_IO_UNIT_PAGE13, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE13, Mpi3IOUnitPage13_t, MPI3_POINTER pMpi3IOUnitPage13_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT13_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED (0x0002) #define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED (0x0001) /***************************************************************************** * IO Unit Page 14 * ****************************************************************************/ #ifndef MPI3_IOUNIT14_MD_MAX #define MPI3_IOUNIT14_MD_MAX (1) #endif /* MPI3_IOUNIT14_MD_MAX */ typedef struct _MPI3_IOUNIT14_PAGEMETADATA { U8 PageType; /* 0x00 */ U8 PageNumber; /* 0x01 */ U8 Reserved02; /* 0x02 */ U8 PageFlags; /* 0x03 */ } MPI3_IOUNIT14_PAGEMETADATA, MPI3_POINTER PTR_MPI3_IOUNIT14_PAGEMETADATA, Mpi3IOUnit14PageMetadata_t, MPI3_POINTER pMpi3IOUnit14PageMetadata_t; /**** Defines for the PageFlags field ****/ #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED (0x02) #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED (0x01) typedef struct _MPI3_IO_UNIT_PAGE14 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 Flags; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U8 NumPages; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_IOUNIT14_PAGEMETADATA PageMetadata[MPI3_IOUNIT14_MD_MAX]; /* 0x10 */ /* variable length */ } MPI3_IO_UNIT_PAGE14, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE14, Mpi3IOUnitPage14_t, MPI3_POINTER pMpi3IOUnitPage14_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT14_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_IOUNIT14_FLAGS_READONLY (0x01) /***************************************************************************** * IO Unit Page 15 * ****************************************************************************/ #ifndef MPI3_IOUNIT15_PBD_MAX #define MPI3_IOUNIT15_PBD_MAX (1) #endif /* MPI3_IOUNIT15_PBD_MAX */ typedef struct _MPI3_IO_UNIT_PAGE15 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 Flags; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U32 Reserved0C; /* 0x0C */ U8 PowerBudgetingCapability; /* 0x10 */ U8 Reserved11[3]; /* 0x11 */ U8 NumPowerBudgetData; /* 0x14 */ U8 Reserved15[3]; /* 0x15 */ U32 PowerBudgetData[MPI3_IOUNIT15_PBD_MAX]; /* 0x18 */ /* variable length */ } MPI3_IO_UNIT_PAGE15, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE15, Mpi3IOUnitPage15_t, MPI3_POINTER pMpi3IOUnitPage15_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT15_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED (0x04) #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK (0x03) +#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_SHIFT (0) #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED (0x00) #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01) #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02) /**** Defines for the NumPowerBudgetData field ****/ #define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00) /***************************************************************************** * IO Unit Page 16 * ****************************************************************************/ #ifndef MPI3_IOUNIT16_ERROR_MAX #define MPI3_IOUNIT16_ERROR_MAX (1) #endif /* MPI3_IOUNIT16_ERROR_MAX */ typedef struct _MPI3_IOUNIT16_ERROR { U32 Offset; /* 0x00 */ U32 Reserved04; /* 0x04 */ U64 Count; /* 0x08 */ U64 Timestamp; /* 0x10 */ } MPI3_IOUNIT16_ERROR, MPI3_POINTER PTR_MPI3_IOUNIT16_ERROR, Mpi3IOUnit16Error_t, MPI3_POINTER pMpi3IOUnit16Error_t; typedef struct _MPI3_IO_UNIT_PAGE16 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U64 TotalErrorCount; /* 0x08 */ U32 Reserved10[3]; /* 0x10 */ U8 NumErrors; /* 0x1C */ U8 MaxErrorsTracked; /* 0x1D */ U16 Reserved1E; /* 0x1E */ MPI3_IOUNIT16_ERROR Error[MPI3_IOUNIT16_ERROR_MAX]; /* 0x20 */ /* variable length */ } MPI3_IO_UNIT_PAGE16, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE16, Mpi3IOUnitPage16_t, MPI3_POINTER pMpi3IOUnitPage16_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOUNIT16_PAGEVERSION (0x00) +/***************************************************************************** + * IO Unit Page 17 * + ****************************************************************************/ + +#ifndef MPI3_IOUNIT17_CURRENTKEY_MAX +#define MPI3_IOUNIT17_CURRENTKEY_MAX (1) +#endif /* MPI3_IOUNIT17_CURRENTKEY_MAX */ + +typedef struct _MPI3_IO_UNIT_PAGE17 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U8 NumInstances; /* 0x08 */ + U8 Instance; /* 0x09 */ + U16 Reserved0A; /* 0x0A */ + U32 Reserved0C[4]; /* 0x0C */ + U16 KeyLength; /* 0x1C */ + U8 EncryptionAlgorithm; /* 0x1E */ + U8 Reserved1F; /* 0x1F */ + U32 CurrentKey[MPI3_IOUNIT17_CURRENTKEY_MAX]; /* 0x20 */ /* variable length */ +} MPI3_IO_UNIT_PAGE17, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE17, + Mpi3IOUnitPage17_t, MPI3_POINTER pMpi3IOUnitPage17_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_IOUNIT17_PAGEVERSION (0x00) + +/**** Use MPI3_ENCRYPTION_ALGORITHM_ defines (see mpi30_image.h) for the EncryptionAlgorithm field ****/ + +/***************************************************************************** + * IO Unit Page 18 * + ****************************************************************************/ + +typedef struct _MPI3_IO_UNIT_PAGE18 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U8 Flags; /* 0x08 */ + U8 PollInterval; /* 0x09 */ + U16 Reserved0A; /* 0x0A */ + U32 Reserved0C; /* 0x0C */ +} MPI3_IO_UNIT_PAGE18, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE18, + Mpi3IOUnitPage18_t, MPI3_POINTER pMpi3IOUnitPage18_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_IOUNIT18_PAGEVERSION (0x00) + +/**** Defines for the Flags field ****/ +#define MPI3_IOUNIT18_FLAGS_DIRECTATTACHED_ENABLE (0x01) + +/**** Defines for the PollInterval field ****/ +#define MPI3_IOUNIT18_POLLINTERVAL_DISABLE (0x00) + +/***************************************************************************** + * IO Unit Page 19 * + ****************************************************************************/ + +#ifndef MPI3_IOUNIT19_DEVICE_MAX +#define MPI3_IOUNIT19_DEVICE_MAX (1) +#endif /* MPI3_IOUNIT19_DEVICE_MAX */ + +typedef struct _MPI3_IOUNIT19_DEVICE_ +{ + U16 Temperature; /* 0x00 */ + U16 DevHandle; /* 0x02 */ + U16 PersistentID; /* 0x04 */ + U16 Reserved06; /* 0x06 */ +} MPI3_IOUNIT19_DEVICE, MPI3_POINTER PTR_MPI3_IOUNIT19_DEVICE, + Mpi3IOUnit19Device_t, MPI3_POINTER pMpi3IOUnit19Device_t; + +/**** Defines for the Temperature field ****/ +#define MPI3_IOUNIT19_DEVICE_TEMPERATURE_UNAVAILABLE (0x8000) + +typedef struct _MPI3_IO_UNIT_PAGE19 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U16 NumDevices; /* 0x08 */ + U16 Reserved0A; /* 0x0A */ + U32 Reserved0C; /* 0x0C */ + MPI3_IOUNIT19_DEVICE Device[MPI3_IOUNIT19_DEVICE_MAX]; /* 0x10 */ +} MPI3_IO_UNIT_PAGE19, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE19, + Mpi3IOUnitPage19_t, MPI3_POINTER pMpi3IOUnitPage19_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_IOUNIT19_PAGEVERSION (0x00) + + /***************************************************************************** * IOC Configuration Pages * ****************************************************************************/ /***************************************************************************** * IOC Page 0 * ****************************************************************************/ typedef struct _MPI3_IOC_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U16 VendorID; /* 0x0C */ U16 DeviceID; /* 0x0E */ U8 RevisionID; /* 0x10 */ U8 Reserved11[3]; /* 0x11 */ U32 ClassCode; /* 0x14 */ U16 SubsystemVendorID; /* 0x18 */ U16 SubsystemID; /* 0x1A */ } MPI3_IOC_PAGE0, MPI3_POINTER PTR_MPI3_IOC_PAGE0, Mpi3IOCPage0_t, MPI3_POINTER pMpi3IOCPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOC0_PAGEVERSION (0x00) /***************************************************************************** * IOC Page 1 * ****************************************************************************/ typedef struct _MPI3_IOC_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 CoalescingTimeout; /* 0x08 */ U8 CoalescingDepth; /* 0x0C */ U8 Obsolete; /* 0x0D */ U16 Reserved0E; /* 0x0E */ } MPI3_IOC_PAGE1, MPI3_POINTER PTR_MPI3_IOC_PAGE1, Mpi3IOCPage1_t, MPI3_POINTER pMpi3IOCPage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOC1_PAGEVERSION (0x00) /***************************************************************************** * IOC Page 2 * ****************************************************************************/ #ifndef MPI3_IOC2_EVENTMASK_WORDS #define MPI3_IOC2_EVENTMASK_WORDS (4) #endif /* MPI3_IOC2_EVENTMASK_WORDS */ typedef struct _MPI3_IOC_PAGE2 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U16 SASBroadcastPrimitiveMasks; /* 0x0C */ U16 SASNotifyPrimitiveMasks; /* 0x0E */ U32 EventMasks[MPI3_IOC2_EVENTMASK_WORDS]; /* 0x10 */ } MPI3_IOC_PAGE2, MPI3_POINTER PTR_MPI3_IOC_PAGE2, Mpi3IOCPage2_t, MPI3_POINTER pMpi3IOCPage2_t; /**** Defines for the PageVersion field ****/ #define MPI3_IOC2_PAGEVERSION (0x00) /***************************************************************************** * Driver Configuration Pages * ****************************************************************************/ /**** Defines for the Flags field in Driver Pages 10, 20, and 30 ****/ /**** NOT used in Driver Page 1 Flags field ****/ #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED (0x0010) #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED (0x0008) #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED (0x0004) #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED (0x0002) #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED (0x0001) typedef struct _MPI3_ALLOWED_CMD_SCSI { U16 ServiceAction; /* 0x00 */ U8 OperationCode; /* 0x02 */ U8 CommandFlags; /* 0x03 */ } MPI3_ALLOWED_CMD_SCSI, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_SCSI, Mpi3AllowedCmdScsi_t, MPI3_POINTER pMpi3AllowedCmdScsi_t; typedef struct _MPI3_ALLOWED_CMD_ATA { U8 Subcommand; /* 0x00 */ U8 Reserved01; /* 0x01 */ U8 Command; /* 0x02 */ U8 CommandFlags; /* 0x03 */ } MPI3_ALLOWED_CMD_ATA, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_ATA, Mpi3AllowedCmdAta_t, MPI3_POINTER pMpi3AllowedCmdAta_t; typedef struct _MPI3_ALLOWED_CMD_NVME { U8 Reserved00; /* 0x00 */ U8 NVMeCmdFlags; /* 0x01 */ U8 OpCode; /* 0x02 */ U8 CommandFlags; /* 0x03 */ } MPI3_ALLOWED_CMD_NVME, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_NVME, Mpi3AllowedCmdNvme_t, MPI3_POINTER pMpi3AllowedCmdNvme_t; /**** Defines for the NVMeCmdFlags field ****/ #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK (0x80) +#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_SHIFT (7) #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO (0x00) #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN (0x80) #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK (0x3F) +#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_SHIFT (0) #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM (0x00) typedef union _MPI3_ALLOWED_CMD { MPI3_ALLOWED_CMD_SCSI Scsi; MPI3_ALLOWED_CMD_ATA Ata; MPI3_ALLOWED_CMD_NVME NVMe; } MPI3_ALLOWED_CMD, MPI3_POINTER PTR_MPI3_ALLOWED_CMD, Mpi3AllowedCmd_t, MPI3_POINTER pMpi3AllowedCmd_t; /**** Defines for the CommandFlags field ****/ #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED (0x20) #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED (0x10) #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED (0x08) #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED (0x04) #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED (0x02) #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED (0x01) #ifndef MPI3_ALLOWED_CMDS_MAX #define MPI3_ALLOWED_CMDS_MAX (1) #endif /* MPI3_ALLOWED_CMDS_MAX */ /***************************************************************************** * Driver Page 0 * ****************************************************************************/ typedef struct _MPI3_DRIVER_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 BSDOptions; /* 0x08 */ U8 SSUTimeout; /* 0x0C */ U8 IOTimeout; /* 0x0D */ U8 TURRetries; /* 0x0E */ U8 TURInterval; /* 0x0F */ U8 Reserved10; /* 0x10 */ U8 SecurityKeyTimeout; /* 0x11 */ - U16 Reserved12; /* 0x12 */ + U16 FirstDevice; /* 0x12 */ U32 Reserved14; /* 0x14 */ U32 Reserved18; /* 0x18 */ } MPI3_DRIVER_PAGE0, MPI3_POINTER PTR_MPI3_DRIVER_PAGE0, Mpi3DriverPage0_t, MPI3_POINTER pMpi3DriverPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_DRIVER0_PAGEVERSION (0x00) /**** Defines for the BSDOptions field ****/ #define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE (0x00000020) #define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE (0x00000010) #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008) #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004) #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003) +#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_SHIFT (0) #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000) #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001) #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002) +/**** Defines for the FirstDevice field ****/ +#define MPI3_DRIVER0_FIRSTDEVICE_IGNORE1 (0x0000) +#define MPI3_DRIVER0_FIRSTDEVICE_IGNORE2 (0xFFFF) + /***************************************************************************** * Driver Page 1 * ****************************************************************************/ typedef struct _MPI3_DRIVER_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Flags; /* 0x08 */ - U32 Reserved0C; /* 0x0C */ + U8 TimeStampUpdate; /* 0x0C */ + U8 Reserved0D[3]; /* 0x0D */ U16 HostDiagTraceMaxSize; /* 0x10 */ U16 HostDiagTraceMinSize; /* 0x12 */ U16 HostDiagTraceDecrementSize; /* 0x14 */ U16 Reserved16; /* 0x16 */ U16 HostDiagFwMaxSize; /* 0x18 */ U16 HostDiagFwMinSize; /* 0x1A */ U16 HostDiagFwDecrementSize; /* 0x1C */ U16 Reserved1E; /* 0x1E */ U16 HostDiagDriverMaxSize; /* 0x20 */ U16 HostDiagDriverMinSize; /* 0x22 */ U16 HostDiagDriverDecrementSize; /* 0x24 */ U16 Reserved26; /* 0x26 */ } MPI3_DRIVER_PAGE1, MPI3_POINTER PTR_MPI3_DRIVER_PAGE1, Mpi3DriverPage1_t, MPI3_POINTER pMpi3DriverPage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_DRIVER1_PAGEVERSION (0x00) /***************************************************************************** * Driver Page 2 * ****************************************************************************/ #ifndef MPI3_DRIVER2_TRIGGER_MAX #define MPI3_DRIVER2_TRIGGER_MAX (1) #endif /* MPI3_DRIVER2_TRIGGER_MAX */ typedef struct _MPI3_DRIVER2_TRIGGER_EVENT { U8 Type; /* 0x00 */ U8 Flags; /* 0x01 */ U8 Reserved02; /* 0x02 */ U8 Event; /* 0x03 */ U32 Reserved04[3]; /* 0x04 */ } MPI3_DRIVER2_TRIGGER_EVENT, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_EVENT, Mpi3Driver2TriggerEvent_t, MPI3_POINTER pMpi3Driver2TriggerEvent_t; typedef struct _MPI3_DRIVER2_TRIGGER_SCSI_SENSE { U8 Type; /* 0x00 */ U8 Flags; /* 0x01 */ U16 Reserved02; /* 0x02 */ U8 ASCQ; /* 0x04 */ U8 ASC; /* 0x05 */ U8 SenseKey; /* 0x06 */ U8 Reserved07; /* 0x07 */ U32 Reserved08[2]; /* 0x08 */ } MPI3_DRIVER2_TRIGGER_SCSI_SENSE, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_SCSI_SENSE, Mpi3Driver2TriggerScsiSense_t, MPI3_POINTER pMpi3Driver2TriggerScsiSense_t; /**** Defines for the ASCQ field ****/ #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL (0xFF) /**** Defines for the ASC field ****/ #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL (0xFF) /**** Defines for the SenseKey field ****/ #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL (0xFF) typedef struct _MPI3_DRIVER2_TRIGGER_REPLY { U8 Type; /* 0x00 */ U8 Flags; /* 0x01 */ U16 IOCStatus; /* 0x02 */ U32 IOCLogInfo; /* 0x04 */ U32 IOCLogInfoMask; /* 0x08 */ U32 Reserved0C; /* 0x0C */ } MPI3_DRIVER2_TRIGGER_REPLY, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_REPLY, Mpi3Driver2TriggerReply_t, MPI3_POINTER pMpi3Driver2TriggerReply_t; /**** Defines for the IOCStatus field ****/ #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL (0xFFFF) typedef union _MPI3_DRIVER2_TRIGGER_ELEMENT { MPI3_DRIVER2_TRIGGER_EVENT Event; MPI3_DRIVER2_TRIGGER_SCSI_SENSE ScsiSense; MPI3_DRIVER2_TRIGGER_REPLY Reply; } MPI3_DRIVER2_TRIGGER_ELEMENT, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_ELEMENT, Mpi3Driver2TriggerElement_t, MPI3_POINTER pMpi3Driver2TriggerElement_t; /**** Defines for the Type field ****/ #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT (0x00) #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE (0x01) #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY (0x02) /**** Defines for the Flags field ****/ #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE (0x02) #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE (0x01) typedef struct _MPI3_DRIVER_PAGE2 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U64 GlobalTrigger; /* 0x08 */ U32 Reserved10[3]; /* 0x10 */ U8 NumTriggers; /* 0x1C */ U8 Reserved1D[3]; /* 0x1D */ MPI3_DRIVER2_TRIGGER_ELEMENT Trigger[MPI3_DRIVER2_TRIGGER_MAX]; /* 0x20 */ /* variable length */ } MPI3_DRIVER_PAGE2, MPI3_POINTER PTR_MPI3_DRIVER_PAGE2, Mpi3DriverPage2_t, MPI3_POINTER pMpi3DriverPage2_t; /**** Defines for the PageVersion field ****/ #define MPI3_DRIVER2_PAGEVERSION (0x00) /**** Defines for the GlobalTrigger field ****/ #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL) #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL) #define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED (0x2000000000000000ULL) #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED (0x1000000000000000ULL) #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED (0x0800000000000000ULL) #define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL) #define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL) /***************************************************************************** * Driver Page 10 * ****************************************************************************/ typedef struct _MPI3_DRIVER_PAGE10 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U16 Flags; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U8 NumAllowedCommands; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ } MPI3_DRIVER_PAGE10, MPI3_POINTER PTR_MPI3_DRIVER_PAGE10, Mpi3DriverPage10_t, MPI3_POINTER pMpi3DriverPage10_t; /**** Defines for the PageVersion field ****/ #define MPI3_DRIVER10_PAGEVERSION (0x00) /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ /***************************************************************************** * Driver Page 20 * ****************************************************************************/ typedef struct _MPI3_DRIVER_PAGE20 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U16 Flags; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U8 NumAllowedCommands; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ } MPI3_DRIVER_PAGE20, MPI3_POINTER PTR_MPI3_DRIVER_PAGE20, Mpi3DriverPage20_t, MPI3_POINTER pMpi3DriverPage20_t; /**** Defines for the PageVersion field ****/ #define MPI3_DRIVER20_PAGEVERSION (0x00) /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ /***************************************************************************** * Driver Page 30 * ****************************************************************************/ typedef struct _MPI3_DRIVER_PAGE30 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U16 Flags; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U8 NumAllowedCommands; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ } MPI3_DRIVER_PAGE30, MPI3_POINTER PTR_MPI3_DRIVER_PAGE30, Mpi3DriverPage30_t, MPI3_POINTER pMpi3DriverPage30_t; /**** Defines for the PageVersion field ****/ #define MPI3_DRIVER30_PAGEVERSION (0x00) /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ /***************************************************************************** * Security Configuration Pages * ****************************************************************************/ typedef union _MPI3_SECURITY_MAC { U32 Dword[16]; U16 Word[32]; U8 Byte[64]; } MPI3_SECURITY_MAC, MPI3_POINTER PTR_MPI3_SECURITY_MAC, Mpi3SecurityMAC_t, MPI3_POINTER pMpi3SecurityMAC_t; typedef union _MPI3_SECURITY_NONCE { U32 Dword[16]; U16 Word[32]; U8 Byte[64]; } MPI3_SECURITY_NONCE, MPI3_POINTER PTR_MPI3_SECURITY_NONCE, Mpi3SecurityNonce_t, MPI3_POINTER pMpi3SecurityNonce_t; /***************************************************************************** * Security Page 0 * ****************************************************************************/ typedef union _MPI3_SECURITY0_CERT_CHAIN { U32 Dword[1024]; U16 Word[2048]; U8 Byte[4096]; } MPI3_SECURITY0_CERT_CHAIN, MPI3_POINTER PTR_MPI3_SECURITY0_CERT_CHAIN, Mpi3Security0CertChain_t, MPI3_POINTER pMpi3Security0CertChain_t; typedef struct _MPI3_SECURITY_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 SlotNumGroup; /* 0x08 */ U8 SlotNum; /* 0x09 */ U16 CertChainLength; /* 0x0A */ U8 CertChainFlags; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ U32 BaseAsymAlgo; /* 0x10 */ U32 BaseHashAlgo; /* 0x14 */ U32 Reserved18[4]; /* 0x18 */ MPI3_SECURITY_MAC Mac; /* 0x28 */ MPI3_SECURITY_NONCE Nonce; /* 0x68 */ MPI3_SECURITY0_CERT_CHAIN CertificateChain; /* 0xA8 */ } MPI3_SECURITY_PAGE0, MPI3_POINTER PTR_MPI3_SECURITY_PAGE0, Mpi3SecurityPage0_t, MPI3_POINTER pMpi3SecurityPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_SECURITY0_PAGEVERSION (0x00) /**** Defines for the CertChainFlags field ****/ #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0E) +#define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SHIFT (1) #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00) #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02) #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04) #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED (0x01) /***************************************************************************** * Security Page 1 * ****************************************************************************/ #ifndef MPI3_SECURITY1_KEY_RECORD_MAX #define MPI3_SECURITY1_KEY_RECORD_MAX 1 #endif /* MPI3_SECURITY1_KEY_RECORD_MAX */ #ifndef MPI3_SECURITY1_PAD_MAX #define MPI3_SECURITY1_PAD_MAX 4 #endif /* MPI3_SECURITY1_PAD_MAX */ typedef union _MPI3_SECURITY1_KEY_DATA { U32 Dword[128]; U16 Word[256]; U8 Byte[512]; } MPI3_SECURITY1_KEY_DATA, MPI3_POINTER PTR_MPI3_SECURITY1_KEY_DATA, Mpi3Security1KeyData_t, MPI3_POINTER pMpi3Security1KeyData_t; typedef struct _MPI3_SECURITY1_KEY_RECORD { U8 Flags; /* 0x00 */ U8 Consumer; /* 0x01 */ U16 KeyDataSize; /* 0x02 */ U32 AdditionalKeyData; /* 0x04 */ U32 Reserved08[2]; /* 0x08 */ MPI3_SECURITY1_KEY_DATA KeyData; /* 0x10 */ } MPI3_SECURITY1_KEY_RECORD, MPI3_POINTER PTR_MPI3_SECURITY1_KEY_RECORD, Mpi3Security1KeyRecord_t, MPI3_POINTER pMpi3Security1KeyRecord_t; /**** Defines for the Flags field ****/ #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1F) +#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_SHIFT (0) #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00) #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01) #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02) #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE (0x03) #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC (0x04) /**** Defines for the Consumer field ****/ #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID (0x00) #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE (0x01) #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN (0x02) #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY (0x03) #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD (0x04) typedef struct _MPI3_SECURITY_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08[2]; /* 0x08 */ MPI3_SECURITY_MAC Mac; /* 0x10 */ MPI3_SECURITY_NONCE Nonce; /* 0x50 */ U8 NumKeys; /* 0x90 */ U8 Reserved91[3]; /* 0x91 */ U32 Reserved94[3]; /* 0x94 */ MPI3_SECURITY1_KEY_RECORD KeyRecord[MPI3_SECURITY1_KEY_RECORD_MAX]; /* 0xA0 */ U8 Pad[MPI3_SECURITY1_PAD_MAX]; /* ?? */ } MPI3_SECURITY_PAGE1, MPI3_POINTER PTR_MPI3_SECURITY_PAGE1, Mpi3SecurityPage1_t, MPI3_POINTER pMpi3SecurityPage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_SECURITY1_PAGEVERSION (0x00) /***************************************************************************** * Security Page 2 * ****************************************************************************/ #ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX #define MPI3_SECURITY2_TRUSTED_ROOT_MAX 1 #endif /* MPI3_SECURITY2_TRUSTED_ROOT_MAX */ #ifndef MPI3_SECURITY2_ROOT_LEN #define MPI3_SECURITY2_ROOT_LEN 4 #endif /* MPI3_SECURITY2_ROOT_LEN */ typedef struct _MPI3_SECURITY2_TRUSTED_ROOT { U8 Level; /* 0x00 */ U8 HashAlgorithm; /* 0x01 */ U16 TrustedRootFlags; /* 0x02 */ U32 Reserved04[3]; /* 0x04 */ U8 Root[MPI3_SECURITY2_ROOT_LEN]; /* 0x10 */ /* variable length */ } MPI3_SECURITY2_TRUSTED_ROOT, MPI3_POINTER PTR_MPI3_SECURITY2_TRUSTED_ROOT, Mpi3Security2TrustedRoot_t, MPI3_POINTER pMpi3Security2TrustedRoot_t; /**** Defines for the TrustedRootFlags field ****/ #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_MASK (0xF000) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_SHIFT (12) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_DIGEST (0x0000) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_DERCERT (0x1000) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK (0x0006) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT (1) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD (0x0000) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI (0x0002) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES (0x0001) typedef struct _MPI3_SECURITY_PAGE2 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08[2]; /* 0x08 */ MPI3_SECURITY_MAC Mac; /* 0x10 */ MPI3_SECURITY_NONCE Nonce; /* 0x50 */ U32 Reserved90[3]; /* 0x90 */ U8 NumRoots; /* 0x9C */ U8 Reserved9D; /* 0x9D */ U16 RootElementSize; /* 0x9E */ MPI3_SECURITY2_TRUSTED_ROOT TrustedRoot[MPI3_SECURITY2_TRUSTED_ROOT_MAX]; /* 0xA0 */ /* variable length */ } MPI3_SECURITY_PAGE2, MPI3_POINTER PTR_MPI3_SECURITY_PAGE2, Mpi3SecurityPage2_t, MPI3_POINTER pMpi3SecurityPage2_t; /**** Defines for the PageVersion field ****/ #define MPI3_SECURITY2_PAGEVERSION (0x00) /***************************************************************************** * SAS IO Unit Configuration Pages * ****************************************************************************/ /***************************************************************************** * SAS IO Unit Page 0 * ****************************************************************************/ typedef struct _MPI3_SAS_IO_UNIT0_PHY_DATA { U8 IOUnitPort; /* 0x00 */ U8 PortFlags; /* 0x01 */ U8 PhyFlags; /* 0x02 */ U8 NegotiatedLinkRate; /* 0x03 */ U16 ControllerPhyDeviceInfo; /* 0x04 */ U16 Reserved06; /* 0x06 */ U16 AttachedDevHandle; /* 0x08 */ U16 ControllerDevHandle; /* 0x0A */ U32 DiscoveryStatus; /* 0x0C */ U32 Reserved10; /* 0x10 */ } MPI3_SAS_IO_UNIT0_PHY_DATA, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT0_PHY_DATA, Mpi3SasIOUnit0PhyData_t, MPI3_POINTER pMpi3SasIOUnit0PhyData_t; #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX #define MPI3_SAS_IO_UNIT0_PHY_MAX (1) #endif /* MPI3_SAS_IO_UNIT0_PHY_MAX */ typedef struct _MPI3_SAS_IO_UNIT_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumPhys; /* 0x0C */ U8 InitStatus; /* 0x0D */ U16 Reserved0E; /* 0x0E */ MPI3_SAS_IO_UNIT0_PHY_DATA PhyData[MPI3_SAS_IO_UNIT0_PHY_MAX]; /* 0x10 */ } MPI3_SAS_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE0, Mpi3SasIOUnitPage0_t, MPI3_POINTER pMpi3SasIOUnitPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASIOUNIT0_PAGEVERSION (0x00) /**** Defines for the InitStatus field ****/ #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS (0x00) #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED (0x06) #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN (0xF0) #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX (0xFF) /**** Defines for the PortFlags field ****/ #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08) #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK (0x03) +#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_SHIFT (0) #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 (0x00) #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC (0x01) #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02) /**** Defines for the PhyFlags field ****/ #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY (0x02) #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY (0x01) /**** Use MPI3_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field ****/ /**** Use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) for the ControllerPhyDeviceInfo field ****/ /**** Use MPI3_SAS_DISC_STATUS_ defines (see mpi30_ioc.h) for the DiscoveryStatus field ****/ /***************************************************************************** * SAS IO Unit Page 1 * ****************************************************************************/ typedef struct _MPI3_SAS_IO_UNIT1_PHY_DATA { U8 IOUnitPort; /* 0x00 */ U8 PortFlags; /* 0x01 */ U8 PhyFlags; /* 0x02 */ U8 MaxMinLinkRate; /* 0x03 */ U16 ControllerPhyDeviceInfo; /* 0x04 */ U16 MaxTargetPortConnectTime; /* 0x06 */ U32 Reserved08; /* 0x08 */ } MPI3_SAS_IO_UNIT1_PHY_DATA, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT1_PHY_DATA, Mpi3SasIOUnit1PhyData_t, MPI3_POINTER pMpi3SasIOUnit1PhyData_t; #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX #define MPI3_SAS_IO_UNIT1_PHY_MAX (1) #endif /* MPI3_SAS_IO_UNIT1_PHY_MAX */ typedef struct _MPI3_SAS_IO_UNIT_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U16 ControlFlags; /* 0x08 */ U16 SASNarrowMaxQueueDepth; /* 0x0A */ U16 AdditionalControlFlags; /* 0x0C */ U16 SASWideMaxQueueDepth; /* 0x0E */ U8 NumPhys; /* 0x10 */ U8 SATAMaxQDepth; /* 0x11 */ U16 Reserved12; /* 0x12 */ MPI3_SAS_IO_UNIT1_PHY_DATA PhyData[MPI3_SAS_IO_UNIT1_PHY_MAX]; /* 0x14 */ } MPI3_SAS_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE1, Mpi3SasIOUnitPage1_t, MPI3_POINTER pMpi3SasIOUnitPage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASIOUNIT1_PAGEVERSION (0x00) /**** Defines for the ControlFlags field ****/ #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST (0x8000) #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001) +#define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SHIFT (0) #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000) #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001) /**** Defines for the AdditionalControlFlags field ****/ #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) /**** Defines for the PortFlags field ****/ #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) /**** Defines for the PhyFlags field ****/ #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) /**** Defines for the MaxMinLinkRate field ****/ #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK (0xF0) #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT (4) #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 (0xA0) #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xB0) #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xC0) #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0F) +#define MPI3_SASIOUNIT1_MMLR_MIN_RATE_SHIFT (0) #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0A) #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0B) #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0C) /**** Use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) for the ControllerPhyDeviceInfo field ****/ /***************************************************************************** * SAS IO Unit Page 2 * ****************************************************************************/ typedef struct _MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS { U8 ControlFlags; /* 0x00 */ U8 Reserved01; /* 0x01 */ U16 InactivityTimerExponent; /* 0x02 */ U8 SATAPartialTimeout; /* 0x04 */ U8 Reserved05; /* 0x05 */ U8 SATASlumberTimeout; /* 0x06 */ U8 Reserved07; /* 0x07 */ U8 SASPartialTimeout; /* 0x08 */ U8 Reserved09; /* 0x09 */ U8 SASSlumberTimeout; /* 0x0A */ U8 Reserved0B; /* 0x0B */ } MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS, Mpi3SasIOUnit2PhyPmSettings_t, MPI3_POINTER pMpi3SasIOUnit2PhyPmSettings_t; #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX #define MPI3_SAS_IO_UNIT2_PHY_MAX (1) #endif /* MPI3_SAS_IO_UNIT2_PHY_MAX */ typedef struct _MPI3_SAS_IO_UNIT_PAGE2 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 NumPhys; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U32 Reserved0C; /* 0x0C */ MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI3_SAS_IO_UNIT2_PHY_MAX]; /* 0x10 */ } MPI3_SAS_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE2, Mpi3SasIOUnitPage2_t, MPI3_POINTER pMpi3SasIOUnitPage2_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASIOUNIT2_PAGEVERSION (0x00) /**** Defines for the ControlFlags field ****/ #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE (0x08) #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE (0x04) #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE (0x02) #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE (0x01) /**** Defines for the InactivityTimerExponent field ****/ #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK (0x7000) #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT (12) #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK (0x0700) #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT (8) #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK (0x0070) #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT (4) #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK (0x0007) #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT (0) #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS (7) #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND (6) #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS (5) #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS (4) #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND (3) #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS (2) #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS (1) #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND (0) /***************************************************************************** * SAS IO Unit Page 3 * ****************************************************************************/ typedef struct _MPI3_SAS_IO_UNIT_PAGE3 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U32 PowerManagementCapabilities; /* 0x0C */ } MPI3_SAS_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE3, Mpi3SasIOUnitPage3_t, MPI3_POINTER pMpi3SasIOUnitPage3_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASIOUNIT3_PAGEVERSION (0x00) /**** Defines for the PowerManagementCapabilities field ****/ #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE (0x00000800) #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE (0x00000400) #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE (0x00000200) #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE (0x00000100) #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) /***************************************************************************** * SAS Expander Configuration Pages * ****************************************************************************/ /***************************************************************************** * SAS Expander Page 0 * ****************************************************************************/ typedef struct _MPI3_SAS_EXPANDER_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 IOUnitPort; /* 0x08 */ U8 ReportGenLength; /* 0x09 */ U16 EnclosureHandle; /* 0x0A */ U32 Reserved0C; /* 0x0C */ U64 SASAddress; /* 0x10 */ U32 DiscoveryStatus; /* 0x18 */ U16 DevHandle; /* 0x1C */ U16 ParentDevHandle; /* 0x1E */ U16 ExpanderChangeCount; /* 0x20 */ U16 ExpanderRouteIndexes; /* 0x22 */ U8 NumPhys; /* 0x24 */ U8 SASLevel; /* 0x25 */ U16 Flags; /* 0x26 */ U16 STPBusInactivityTimeLimit; /* 0x28 */ U16 STPMaxConnectTimeLimit; /* 0x2A */ U16 STP_SMP_NexusLossTime; /* 0x2C */ U16 MaxNumRoutedSASAddresses; /* 0x2E */ U64 ActiveZoneManagerSASAddress; /* 0x30 */ U16 ZoneLockInactivityLimit; /* 0x38 */ U16 Reserved3A; /* 0x3A */ U8 TimeToReducedFunc; /* 0x3C */ U8 InitialTimeToReducedFunc; /* 0x3D */ U8 MaxReducedFuncTime; /* 0x3E */ U8 ExpStatus; /* 0x3F */ } MPI3_SAS_EXPANDER_PAGE0, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE0, Mpi3SasExpanderPage0_t, MPI3_POINTER pMpi3SasExpanderPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASEXPANDER0_PAGEVERSION (0x00) /**** Use MPI3_SAS_DISC_STATUS_ defines (see mpi30_ioc.h) for the DiscoveryStatus field ****/ /**** Defines for the Flags field ****/ #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED (0x1000) #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING (0x0100) #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) /**** Defines for the ExpStatus field ****/ #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING (0x02) #define MPI3_SASEXPANDER0_ES_RESPONDING (0x03) #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING (0x04) /***************************************************************************** * SAS Expander Page 1 * ****************************************************************************/ typedef struct _MPI3_SAS_EXPANDER_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 IOUnitPort; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U8 NumPhys; /* 0x0C */ U8 Phy; /* 0x0D */ U16 NumTableEntriesProgrammed; /* 0x0E */ U8 ProgrammedLinkRate; /* 0x10 */ U8 HwLinkRate; /* 0x11 */ U16 AttachedDevHandle; /* 0x12 */ U32 PhyInfo; /* 0x14 */ U16 AttachedDeviceInfo; /* 0x18 */ U16 Reserved1A; /* 0x1A */ U16 ExpanderDevHandle; /* 0x1C */ U8 ChangeCount; /* 0x1E */ U8 NegotiatedLinkRate; /* 0x1F */ U8 PhyIdentifier; /* 0x20 */ U8 AttachedPhyIdentifier; /* 0x21 */ U8 Reserved22; /* 0x22 */ U8 DiscoveryInfo; /* 0x23 */ U32 AttachedPhyInfo; /* 0x24 */ U8 ZoneGroup; /* 0x28 */ U8 SelfConfigStatus; /* 0x29 */ U16 Reserved2A; /* 0x2A */ U16 Slot; /* 0x2C */ U16 SlotIndex; /* 0x2E */ } MPI3_SAS_EXPANDER_PAGE1, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE1, Mpi3SasExpanderPage1_t, MPI3_POINTER pMpi3SasExpanderPage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASEXPANDER1_PAGEVERSION (0x00) /**** Defines for the ProgrammedLinkRate field - use MPI3_SAS_PRATE_ defines ****/ /**** Defines for the HwLinkRate field - use MPI3_SAS_HWRATE_ defines ****/ /**** Defines for the PhyInfo field - use MPI3_SAS_PHYINFO_ defines ****/ /**** Defines for the AttachedDeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines ****/ /**** Defines for the NegotiatedLinkRate field - use use MPI3_SAS_NEG_LINK_RATE_ defines ****/ /**** Defines for the DiscoveryInfo field ****/ #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) /**** Defines for the AttachedPhyInfo field - use MPI3_SAS_APHYINFO_ defines ****/ /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ /***************************************************************************** * SAS Expander Page 2 * ****************************************************************************/ #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS #define MPI3_SASEXPANDER2_MAX_NUM_PHYS (1) #endif /* MPI3_SASEXPANDER2_MAX_NUM_PHYS */ typedef struct _MPI3_SASEXPANDER2_PHY_ELEMENT { U8 LinkChangeCount; /* 0x00 */ U8 Reserved01; /* 0x01 */ U16 RateChangeCount; /* 0x02 */ U32 Reserved04; /* 0x04 */ } MPI3_SASEXPANDER2_PHY_ELEMENT, MPI3_POINTER PTR_MPI3_SASEXPANDER2_PHY_ELEMENT, Mpi3SasExpander2PhyElement_t, MPI3_POINTER pMpi3SasExpander2PhyElement_t; typedef struct _MPI3_SAS_EXPANDER_PAGE2 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 NumPhys; /* 0x08 */ U8 Reserved09; /* 0x09 */ U16 DevHandle; /* 0x0A */ U32 Reserved0C; /* 0x0C */ MPI3_SASEXPANDER2_PHY_ELEMENT Phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS]; /* 0x10 */ /* variable length */ } MPI3_SAS_EXPANDER_PAGE2, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE2, Mpi3SasExpanderPage2_t, MPI3_POINTER pMpi3SasExpanderPage2_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASEXPANDER2_PAGEVERSION (0x00) /***************************************************************************** * SAS Port Configuration Pages * ****************************************************************************/ /***************************************************************************** * SAS Port Page 0 * ****************************************************************************/ typedef struct _MPI3_SAS_PORT_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 PortNumber; /* 0x08 */ U8 Reserved09; /* 0x09 */ U8 PortWidth; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U8 ZoneGroup; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ U64 SASAddress; /* 0x10 */ U16 DeviceInfo; /* 0x18 */ U16 Reserved1A; /* 0x1A */ U32 Reserved1C; /* 0x1C */ } MPI3_SAS_PORT_PAGE0, MPI3_POINTER PTR_MPI3_SAS_PORT_PAGE0, Mpi3SasPortPage0_t, MPI3_POINTER pMpi3SasPortPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASPORT0_PAGEVERSION (0x00) /**** Defines for the DeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines ****/ /***************************************************************************** * SAS PHY Configuration Pages * ****************************************************************************/ /***************************************************************************** * SAS PHY Page 0 * ****************************************************************************/ typedef struct _MPI3_SAS_PHY_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U16 OwnerDevHandle; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U16 AttachedDevHandle; /* 0x0C */ U8 AttachedPhyIdentifier; /* 0x0E */ U8 Reserved0F; /* 0x0F */ U32 AttachedPhyInfo; /* 0x10 */ U8 ProgrammedLinkRate; /* 0x14 */ U8 HwLinkRate; /* 0x15 */ U8 ChangeCount; /* 0x16 */ U8 Flags; /* 0x17 */ U32 PhyInfo; /* 0x18 */ U8 NegotiatedLinkRate; /* 0x1C */ U8 Reserved1D[3]; /* 0x1D */ U16 Slot; /* 0x20 */ U16 SlotIndex; /* 0x22 */ } MPI3_SAS_PHY_PAGE0, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE0, Mpi3SasPhyPage0_t, MPI3_POINTER pMpi3SasPhyPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASPHY0_PAGEVERSION (0x00) /**** Defines for the AttachedPhyInfo field - use MPI3_SAS_APHYINFO_ defines ****/ /**** Defines for the ProgrammedLinkRate field - use MPI3_SAS_PRATE_ defines ****/ /**** Defines for the HwLinkRate field - use MPI3_SAS_HWRATE_ defines ****/ /**** Defines for the Flags field ****/ #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) /**** Defines for the PhyInfo field - use MPI3_SAS_PHYINFO_ defines ****/ /**** Defines for the NegotiatedLinkRate field - use MPI3_SAS_NEG_LINK_RATE_ defines ****/ /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ /***************************************************************************** * SAS PHY Page 1 * ****************************************************************************/ typedef struct _MPI3_SAS_PHY_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U32 InvalidDwordCount; /* 0x0C */ U32 RunningDisparityErrorCount; /* 0x10 */ U32 LossDwordSynchCount; /* 0x14 */ U32 PhyResetProblemCount; /* 0x18 */ } MPI3_SAS_PHY_PAGE1, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE1, Mpi3SasPhyPage1_t, MPI3_POINTER pMpi3SasPhyPage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASPHY1_PAGEVERSION (0x00) /***************************************************************************** * SAS PHY Page 2 * ****************************************************************************/ typedef struct _MPI3_SAS_PHY2_PHY_EVENT { U8 PhyEventCode; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U32 PhyEventInfo; /* 0x04 */ } MPI3_SAS_PHY2_PHY_EVENT, MPI3_POINTER PTR_MPI3_SAS_PHY2_PHY_EVENT, Mpi3SasPhy2PhyEvent_t, MPI3_POINTER pMpi3SasPhy2PhyEvent_t; /**** Defines for the PhyEventCode field - use MPI3_SASPHY3_EVENT_CODE_ defines */ #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX #define MPI3_SAS_PHY2_PHY_EVENT_MAX (1) #endif /* MPI3_SAS_PHY2_PHY_EVENT_MAX */ typedef struct _MPI3_SAS_PHY_PAGE2 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumPhyEvents; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_SAS_PHY2_PHY_EVENT PhyEvent[MPI3_SAS_PHY2_PHY_EVENT_MAX]; /* 0x10 */ } MPI3_SAS_PHY_PAGE2, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE2, Mpi3SasPhyPage2_t, MPI3_POINTER pMpi3SasPhyPage2_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASPHY2_PAGEVERSION (0x00) /***************************************************************************** * SAS PHY Page 3 * ****************************************************************************/ typedef struct _MPI3_SAS_PHY3_PHY_EVENT_CONFIG { U8 PhyEventCode; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U8 CounterType; /* 0x04 */ U8 ThresholdWindow; /* 0x05 */ U8 TimeUnits; /* 0x06 */ U8 Reserved07; /* 0x07 */ U32 EventThreshold; /* 0x08 */ U16 ThresholdFlags; /* 0x0C */ U16 Reserved0E; /* 0x0E */ } MPI3_SAS_PHY3_PHY_EVENT_CONFIG, MPI3_POINTER PTR_MPI3_SAS_PHY3_PHY_EVENT_CONFIG, Mpi3SasPhy3PhyEventConfig_t, MPI3_POINTER pMpi3SasPhy3PhyEventConfig_t; /**** Defines for the PhyEventCode field ****/ #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT (0x00) #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR (0x06) #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS (0x07) #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC (0x08) #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK (0x27) #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK (0x28) #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) #define MPI3_SASPHY3_EVENT_CODE_CONNECTION (0x2A) #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN (0x2F) #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) #define MPI3_SASPHY3_EVENT_CODE_RX_AIP (0xD2) #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) /**** Defines for the CounterType field ****/ #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING (0x01) #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) /**** Defines for the TimeUnits field ****/ #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) /**** Defines for the ThresholdFlags field ****/ #define MPI3_SASPHY3_TFLAGS_PHY_RESET (0x0002) #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX #define MPI3_SAS_PHY3_PHY_EVENT_MAX (1) #endif /* MPI3_SAS_PHY3_PHY_EVENT_MAX */ typedef struct _MPI3_SAS_PHY_PAGE3 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumPhyEvents; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_SAS_PHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI3_SAS_PHY3_PHY_EVENT_MAX]; /* 0x10 */ } MPI3_SAS_PHY_PAGE3, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE3, Mpi3SasPhyPage3_t, MPI3_POINTER pMpi3SasPhyPage3_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASPHY3_PAGEVERSION (0x00) /***************************************************************************** * SAS PHY Page 4 * ****************************************************************************/ typedef struct _MPI3_SAS_PHY_PAGE4 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 Reserved08[3]; /* 0x08 */ U8 Flags; /* 0x0B */ U8 InitialFrame[28]; /* 0x0C */ } MPI3_SAS_PHY_PAGE4, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE4, Mpi3SasPhyPage4_t, MPI3_POINTER pMpi3SasPhyPage4_t; /**** Defines for the PageVersion field ****/ #define MPI3_SASPHY4_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_SASPHY4_FLAGS_FRAME_VALID (0x02) #define MPI3_SASPHY4_FLAGS_SATA_FRAME (0x01) /***************************************************************************** * Common definitions used by PCIe Configuration Pages * ****************************************************************************/ /**** Defines for NegotiatedLinkRates ****/ #define MPI3_PCIE_LINK_RETIMERS_MASK (0x30) #define MPI3_PCIE_LINK_RETIMERS_SHIFT (4) #define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0F) +#define MPI3_PCIE_NEG_LINK_RATE_SHIFT (0) #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) #define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02) #define MPI3_PCIE_NEG_LINK_RATE_5_0 (0x03) #define MPI3_PCIE_NEG_LINK_RATE_8_0 (0x04) #define MPI3_PCIE_NEG_LINK_RATE_16_0 (0x05) #define MPI3_PCIE_NEG_LINK_RATE_32_0 (0x06) /**** Defines for Enabled ASPM States ****/ #define MPI3_PCIE_ASPM_ENABLE_NONE (0x0) #define MPI3_PCIE_ASPM_ENABLE_L0s (0x1) #define MPI3_PCIE_ASPM_ENABLE_L1 (0x2) #define MPI3_PCIE_ASPM_ENABLE_L0s_L1 (0x3) /**** Defines for Enabled ASPM States ****/ #define MPI3_PCIE_ASPM_SUPPORT_NONE (0x0) #define MPI3_PCIE_ASPM_SUPPORT_L0s (0x1) #define MPI3_PCIE_ASPM_SUPPORT_L1 (0x2) #define MPI3_PCIE_ASPM_SUPPORT_L0s_L1 (0x3) /***************************************************************************** * PCIe IO Unit Configuration Pages * ****************************************************************************/ /***************************************************************************** * PCIe IO Unit Page 0 * ****************************************************************************/ typedef struct _MPI3_PCIE_IO_UNIT0_PHY_DATA { U8 Link; /* 0x00 */ U8 LinkFlags; /* 0x01 */ U8 PhyFlags; /* 0x02 */ U8 NegotiatedLinkRate; /* 0x03 */ U16 AttachedDevHandle; /* 0x04 */ U16 ControllerDevHandle; /* 0x06 */ U32 EnumerationStatus; /* 0x08 */ U8 IOUnitPort; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ } MPI3_PCIE_IO_UNIT0_PHY_DATA, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT0_PHY_DATA, Mpi3PcieIOUnit0PhyData_t, MPI3_POINTER pMpi3PcieIOUnit0PhyData_t; /**** Defines for the LinkFlags field ****/ #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10) +#define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_SHIFT (4) #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00) #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10) #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08) /**** Defines for the PhyFlags field ****/ #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY (0x01) /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ /**** Defines for the EnumerationStatus field ****/ #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED (0x80000000) #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED (0x20000000) #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES (0x10000000) #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX #define MPI3_PCIE_IO_UNIT0_PHY_MAX (1) #endif /* MPI3_PCIE_IO_UNIT0_PHY_MAX */ typedef struct _MPI3_PCIE_IO_UNIT_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 NumPhys; /* 0x0C */ U8 InitStatus; /* 0x0D */ U8 ASPM; /* 0x0E */ U8 Reserved0F; /* 0x0F */ MPI3_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI3_PCIE_IO_UNIT0_PHY_MAX]; /* 0x10 */ } MPI3_PCIE_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE0, Mpi3PcieIOUnitPage0_t, MPI3_POINTER pMpi3PcieIOUnitPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_PCIEIOUNIT0_PAGEVERSION (0x00) /**** Defines for the InitStatus field ****/ #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS (0x00) #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED (0x03) #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH (0x06) #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE (0x07) #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE (0x08) #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START (0xF0) #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END (0xFF) /**** Defines for the ASPM field ****/ #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK (0xC0) #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT (6) #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK (0x30) #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT (4) /*** use MPI3_PCIE_ASPM_ENABLE_ defines for field values ***/ #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK (0x0C) #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT (2) #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK (0x03) #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT (0) /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for field values ***/ /***************************************************************************** * PCIe IO Unit Page 1 * ****************************************************************************/ typedef struct _MPI3_PCIE_IO_UNIT1_PHY_DATA { U8 Link; /* 0x00 */ U8 LinkFlags; /* 0x01 */ U8 PhyFlags; /* 0x02 */ U8 MaxMinLinkRate; /* 0x03 */ U32 Reserved04; /* 0x04 */ U32 Reserved08; /* 0x08 */ } MPI3_PCIE_IO_UNIT1_PHY_DATA, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT1_PHY_DATA, Mpi3PcieIOUnit1PhyData_t, MPI3_POINTER pMpi3PcieIOUnit1PhyData_t; /**** Defines for the LinkFlags field ****/ #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03) +#define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_SHIFT (0) #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00) #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01) #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02) /**** Defines for the PhyFlags field ****/ #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) /**** Defines for the MaxMinLinkRate ****/ #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK (0xF0) #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT (4) #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 (0x20) #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 (0x30) #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 (0x40) #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 (0x50) #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 (0x60) #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX #define MPI3_PCIE_IO_UNIT1_PHY_MAX (1) #endif /* MPI3_PCIE_IO_UNIT1_PHY_MAX */ typedef struct _MPI3_PCIE_IO_UNIT_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 ControlFlags; /* 0x08 */ U32 Reserved0C; /* 0x0C */ U8 NumPhys; /* 0x10 */ U8 Reserved11; /* 0x11 */ U8 ASPM; /* 0x12 */ U8 Reserved13; /* 0x13 */ MPI3_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI3_PCIE_IO_UNIT1_PHY_MAX]; /* 0x14 */ } MPI3_PCIE_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE1, Mpi3PcieIOUnitPage1_t, MPI3_POINTER pMpi3PcieIOUnitPage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00) /**** Defines for the ControlFlags field ****/ #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK (0xE0000000) +#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_SHIFT (29) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE (0x00000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT (0x20000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT (0x40000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR (0x60000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK (0x1C000000) +#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_SHIFT (26) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE (0x00000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ENABLE (0x04000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DISABLE (0x08000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR (0x0C000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PARTIAL_CAPACITY_ENABLE (0x00000100) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x00000080) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x00000040) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x00000030) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT (4) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x00000010) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x00000020) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0000000F) +#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_SHIFT (0) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE (0x00000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x00000002) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x00000003) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x00000004) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x00000005) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x00000006) /**** Defines for the ASPM field ****/ #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK (0x0C) #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT (2) #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK (0x03) #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT (0) /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPM field values ***/ /***************************************************************************** * PCIe IO Unit Page 2 * ****************************************************************************/ typedef struct _MPI3_PCIE_IO_UNIT_PAGE2 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U16 NVMeMaxQDx1; /* 0x08 */ U16 NVMeMaxQDx2; /* 0x0A */ U8 NVMeAbortTO; /* 0x0C */ U8 Reserved0D; /* 0x0D */ U16 NVMeMaxQDx4; /* 0x0E */ } MPI3_PCIE_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE2, Mpi3PcieIOUnitPage2_t, MPI3_POINTER pMpi3PcieIOUnitPage2_t; /**** Defines for the PageVersion field ****/ #define MPI3_PCIEIOUNIT2_PAGEVERSION (0x00) /***************************************************************************** * PCIe IO Unit Page 3 * ****************************************************************************/ /**** Defines for Error Indexes ****/ #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR (0) #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY (1) #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG (2) #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP (3) #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP (4) #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX (5) typedef struct _MPI3_PCIE_IO_UNIT3_ERROR { U16 ThresholdCount; /* 0x00 */ U16 Reserved02; /* 0x02 */ } MPI3_PCIE_IO_UNIT3_ERROR, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT3_ERROR, Mpi3PcieIOUnit3Error_t, MPI3_POINTER pMpi3PcieIOUnit3Error_t; typedef struct _MPI3_PCIE_IO_UNIT_PAGE3 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 ThresholdWindow; /* 0x08 */ U8 ThresholdAction; /* 0x09 */ U8 EscalationCount; /* 0x0A */ U8 EscalationAction; /* 0x0B */ U8 NumErrors; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ MPI3_PCIE_IO_UNIT3_ERROR Error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX]; /* 0x10 */ } MPI3_PCIE_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE3, Mpi3PcieIOUnitPage3_t, MPI3_POINTER pMpi3PcieIOUnitPage3_t; /**** Defines for the PageVersion field ****/ #define MPI3_PCIEIOUNIT3_PAGEVERSION (0x00) /**** Defines for the ThresholdAction and EscalationAction fields ****/ #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION (0x00) #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET (0x01) #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY (0x02) #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS (0x03) /**** Defines for Error Indexes - use MPI3_PCIEIOUNIT3_ERROR_ defines ****/ /***************************************************************************** * PCIe Switch Configuration Pages * ****************************************************************************/ /***************************************************************************** * PCIe Switch Page 0 * ****************************************************************************/ typedef struct _MPI3_PCIE_SWITCH_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 IOUnitPort; /* 0x08 */ U8 SwitchStatus; /* 0x09 */ U8 Reserved0A[2]; /* 0x0A */ U16 DevHandle; /* 0x0C */ U16 ParentDevHandle; /* 0x0E */ U8 NumPorts; /* 0x10 */ U8 PCIeLevel; /* 0x11 */ U16 Reserved12; /* 0x12 */ U32 Reserved14; /* 0x14 */ U32 Reserved18; /* 0x18 */ U32 Reserved1C; /* 0x1C */ } MPI3_PCIE_SWITCH_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE0, Mpi3PcieSwitchPage0_t, MPI3_POINTER pMpi3PcieSwitchPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_PCIESWITCH0_PAGEVERSION (0x00) /**** Defines for the SwitchStatus field ****/ #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING (0x02) #define MPI3_PCIESWITCH0_SS_RESPONDING (0x03) #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING (0x04) /***************************************************************************** * PCIe Switch Page 1 * ****************************************************************************/ typedef struct _MPI3_PCIE_SWITCH_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 IOUnitPort; /* 0x08 */ U8 Flags; /* 0x09 */ U16 Reserved0A; /* 0x0A */ U8 NumPorts; /* 0x0C */ U8 PortNum; /* 0x0D */ U16 AttachedDevHandle; /* 0x0E */ U16 SwitchDevHandle; /* 0x10 */ U8 NegotiatedPortWidth; /* 0x12 */ U8 NegotiatedLinkRate; /* 0x13 */ U16 Slot; /* 0x14 */ U16 SlotIndex; /* 0x16 */ U32 Reserved18; /* 0x18 */ } MPI3_PCIE_SWITCH_PAGE1, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE1, Mpi3PcieSwitchPage1_t, MPI3_POINTER pMpi3PcieSwitchPage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_PCIESWITCH1_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK (0x0C) #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT (2) /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPMState field values ***/ #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK (0x03) #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT (0) /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for ASPMSupport field values ***/ /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ /***************************************************************************** * PCIe Switch Page 2 * ****************************************************************************/ #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS #define MPI3_PCIESWITCH2_MAX_NUM_PORTS (1) #endif /* MPI3_PCIESWITCH2_MAX_NUM_PORTS */ typedef struct _MPI3_PCIESWITCH2_PORT_ELEMENT { U16 LinkChangeCount; /* 0x00 */ U16 RateChangeCount; /* 0x02 */ U32 Reserved04; /* 0x04 */ } MPI3_PCIESWITCH2_PORT_ELEMENT, MPI3_POINTER PTR_MPI3_PCIESWITCH2_PORT_ELEMENT, Mpi3PcieSwitch2PortElement_t, MPI3_POINTER pMpi3PcieSwitch2PortElement_t; typedef struct _MPI3_PCIE_SWITCH_PAGE2 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 NumPorts; /* 0x08 */ U8 Reserved09; /* 0x09 */ U16 DevHandle; /* 0x0A */ U32 Reserved0C; /* 0x0C */ MPI3_PCIESWITCH2_PORT_ELEMENT Port[MPI3_PCIESWITCH2_MAX_NUM_PORTS]; /* 0x10 */ /* variable length */ } MPI3_PCIE_SWITCH_PAGE2, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE2, Mpi3PcieSwitchPage2_t, MPI3_POINTER pMpi3PcieSwitchPage2_t; /**** Defines for the PageVersion field ****/ #define MPI3_PCIESWITCH2_PAGEVERSION (0x00) /***************************************************************************** * PCIe Link Configuration Pages * ****************************************************************************/ /***************************************************************************** * PCIe Link Page 0 * ****************************************************************************/ typedef struct _MPI3_PCIE_LINK_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 Link; /* 0x08 */ U8 Reserved09[3]; /* 0x09 */ U32 Reserved0C; /* 0x0C */ U32 ReceiverErrorCount; /* 0x10 */ U32 RecoveryCount; /* 0x14 */ U32 CorrErrorMsgCount; /* 0x18 */ U32 NonFatalErrorMsgCount; /* 0x1C */ U32 FatalErrorMsgCount; /* 0x20 */ U32 NonFatalErrorCount; /* 0x24 */ U32 FatalErrorCount; /* 0x28 */ U32 BadDLLPCount; /* 0x2C */ U32 BadTLPCount; /* 0x30 */ } MPI3_PCIE_LINK_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_LINK_PAGE0, Mpi3PcieLinkPage0_t, MPI3_POINTER pMpi3PcieLinkPage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_PCIELINK0_PAGEVERSION (0x00) /***************************************************************************** * Enclosure Configuration Pages * ****************************************************************************/ /***************************************************************************** * Enclosure Page 0 * ****************************************************************************/ typedef struct _MPI3_ENCLOSURE_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U64 EnclosureLogicalID; /* 0x08 */ U16 Flags; /* 0x10 */ U16 EnclosureHandle; /* 0x12 */ U16 NumSlots; /* 0x14 */ U16 Reserved16; /* 0x16 */ U8 IOUnitPort; /* 0x18 */ U8 EnclosureLevel; /* 0x19 */ U16 SEPDevHandle; /* 0x1A */ U8 ChassisSlot; /* 0x1C */ U8 Reserved1D[3]; /* 0x1D */ U32 ReceptacleIDs; /* 0x20 */ U32 Reserved24; /* 0x24 */ } MPI3_ENCLOSURE_PAGE0, MPI3_POINTER PTR_MPI3_ENCLOSURE_PAGE0, Mpi3EnclosurePage0_t, MPI3_POINTER pMpi3EnclosurePage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_ENCLOSURE0_PAGEVERSION (0x00) /**** Defines for the Flags field ****/ #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xC000) +#define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SHIFT (0xC000) #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000) #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000) #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000) #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010) +#define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_SHIFT (4) #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000) #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010) #define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000F) +#define MPI3_ENCLS0_FLAGS_MNG_SHIFT (0) #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002) /**** Defines for the ReceptacleIDs field ****/ #define MPI3_ENCLS0_RECEPTACLEIDS_NOT_REPORTED (0x00000000) /***************************************************************************** * Device Configuration Pages * ****************************************************************************/ /***************************************************************************** * Common definitions used by Device Configuration Pages * ****************************************************************************/ /**** Defines for the DeviceForm field ****/ #define MPI3_DEVICE_DEVFORM_SAS_SATA (0x00) #define MPI3_DEVICE_DEVFORM_PCIE (0x01) #define MPI3_DEVICE_DEVFORM_VD (0x02) /***************************************************************************** * Device Page 0 * ****************************************************************************/ typedef struct _MPI3_DEVICE0_SAS_SATA_FORMAT { U64 SASAddress; /* 0x00 */ U16 Flags; /* 0x08 */ U16 DeviceInfo; /* 0x0A */ U8 PhyNum; /* 0x0C */ U8 AttachedPhyIdentifier; /* 0x0D */ U8 MaxPortConnections; /* 0x0E */ U8 ZoneGroup; /* 0x0F */ } MPI3_DEVICE0_SAS_SATA_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_SAS_SATA_FORMAT, Mpi3Device0SasSataFormat_t, MPI3_POINTER pMpi3Device0SasSataFormat_t; /**** Defines for the Flags field ****/ #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400) #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP (0x0200) #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP (0x0100) #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY (0x0080) #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE (0x0040) #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV (0x0020) #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA (0x0010) #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP (0x0008) #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP (0x0004) #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP (0x0002) #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP (0x0001) /**** Defines for the DeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) ****/ typedef struct _MPI3_DEVICE0_PCIE_FORMAT { U8 SupportedLinkRates; /* 0x00 */ U8 MaxPortWidth; /* 0x01 */ U8 NegotiatedPortWidth; /* 0x02 */ U8 NegotiatedLinkRate; /* 0x03 */ U8 PortNum; /* 0x04 */ U8 ControllerResetTO; /* 0x05 */ U16 DeviceInfo; /* 0x06 */ U32 MaximumDataTransferSize; /* 0x08 */ U32 Capabilities; /* 0x0C */ U16 NOIOB; /* 0x10 */ U8 NVMeAbortTO; /* 0x12 */ U8 PageSize; /* 0x13 */ U16 ShutdownLatency; /* 0x14 */ U8 RecoveryInfo; /* 0x16 */ U8 Reserved17; /* 0x17 */ } MPI3_DEVICE0_PCIE_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_PCIE_FORMAT, Mpi3Device0PcieFormat_t, MPI3_POINTER pMpi3Device0PcieFormat_t; /**** Defines for the SupportedLinkRates field ****/ #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP (0x10) #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP (0x08) #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP (0x04) #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP (0x02) #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP (0x01) /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ /**** Defines for DeviceInfo bitfield ****/ #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0007) +#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SHIFT (0) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE (0x0003) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK (0x0030) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT (4) /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPM field values ***/ #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK (0x00C0) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT (6) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0 (0x0000) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1 (0x0040) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2 (0x0080) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3 (0x00C0) /**** Defines for the Capabilities field ****/ #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED (0x00000020) #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED (0x00000010) #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED (0x00000008) #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL (0x00000004) #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP (0x00000000) #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP (0x00000002) #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP (0x00000001) #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK (0x000000C0) #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT (6) /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for ASPM field values ***/ /**** Defines for the RecoveryInfo field ****/ #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK (0xE0) +#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_SHIFT (5) #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT (0x00) #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT (0x20) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK (0x1F) +#define MPI3_DEVICE0_PCIE_RECOVER_REASON_SHIFT (0) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS (0x00) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 (0x01) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS (0x02) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION (0x03) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ (0x04) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ (0x05) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PARTIAL_CAP (0x06) typedef struct _MPI3_DEVICE0_VD_FORMAT { U8 VdState; /* 0x00 */ U8 RAIDLevel; /* 0x01 */ U16 DeviceInfo; /* 0x02 */ U16 Flags; /* 0x04 */ U16 IOThrottleGroup; /* 0x06 */ U16 IOThrottleGroupLow; /* 0x08 */ U16 IOThrottleGroupHigh; /* 0x0A */ U32 Reserved0C; /* 0x0C */ } MPI3_DEVICE0_VD_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_VD_FORMAT, Mpi3Device0VdFormat_t, MPI3_POINTER pMpi3Device0VdFormat_t; /**** Defines for the VdState field ****/ #define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00) #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01) #define MPI3_DEVICE0_VD_STATE_DEGRADED (0x02) #define MPI3_DEVICE0_VD_STATE_OPTIMAL (0x03) /**** Defines for RAIDLevel field ****/ #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 (0) #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 (1) #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 (5) #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 (6) #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 (10) #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 (50) #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 (60) /**** Defines for DeviceInfo field ****/ #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD (0x0010) #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD (0x0008) #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME (0x0004) #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002) #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001) /**** Defines for the Flags field ****/ #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xF000) #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12) +#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_MASK (0x0003) +#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_SHIFT (0) +#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_HDD (0x0000) +#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_SSD (0x0001) +#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_NO_GUIDANCE (0x0002) typedef union _MPI3_DEVICE0_DEV_SPEC_FORMAT { MPI3_DEVICE0_SAS_SATA_FORMAT SasSataFormat; MPI3_DEVICE0_PCIE_FORMAT PcieFormat; MPI3_DEVICE0_VD_FORMAT VdFormat; } MPI3_DEVICE0_DEV_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_DEV_SPEC_FORMAT, Mpi3Device0DevSpecFormat_t, MPI3_POINTER pMpi3Device0DevSpecFormat_t; typedef struct _MPI3_DEVICE_PAGE0 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U16 DevHandle; /* 0x08 */ U16 ParentDevHandle; /* 0x0A */ U16 Slot; /* 0x0C */ U16 EnclosureHandle; /* 0x0E */ U64 WWID; /* 0x10 */ U16 PersistentID; /* 0x18 */ U8 IOUnitPort; /* 0x1A */ U8 AccessStatus; /* 0x1B */ U16 Flags; /* 0x1C */ U16 Reserved1E; /* 0x1E */ U16 SlotIndex; /* 0x20 */ U16 QueueDepth; /* 0x22 */ U8 Reserved24[3]; /* 0x24 */ U8 DeviceForm; /* 0x27 */ MPI3_DEVICE0_DEV_SPEC_FORMAT DeviceSpecific; /* 0x28 */ } MPI3_DEVICE_PAGE0, MPI3_POINTER PTR_MPI3_DEVICE_PAGE0, Mpi3DevicePage0_t, MPI3_POINTER pMpi3DevicePage0_t; /**** Defines for the PageVersion field ****/ #define MPI3_DEVICE0_PAGEVERSION (0x00) /**** Defines for the ParentDevHandle field ****/ #define MPI3_DEVICE0_PARENT_INVALID (0xFFFF) /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ /**** Defines for the EnclosureHandle field ****/ #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE (0x0000) /**** Defines for the WWID field ****/ #define MPI3_DEVICE0_WWID_INVALID (0xFFFFFFFFFFFFFFFF) /**** Defines for the PersistentID field ****/ #define MPI3_DEVICE0_PERSISTENTID_INVALID (0xFFFF) /**** Defines for the IOUnitPort field ****/ #define MPI3_DEVICE0_IOUNITPORT_INVALID (0xFF) /**** Defines for the AccessStatus field ****/ /* Generic Access Status Codes */ #define MPI3_DEVICE0_ASTATUS_NO_ERRORS (0x00) #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION (0x01) #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED (0x02) #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x03) #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED (0x04) #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY (0x05) #define MPI3_DEVICE0_ASTATUS_PREPARE (0x06) #define MPI3_DEVICE0_ASTATUS_SAFE_MODE (0x07) #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX (0x0F) /* SAS Access Status Codes */ #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN (0x10) #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x11) #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x12) #define MPI3_DEVICE0_ASTATUS_SAS_MAX (0x1F) /* SATA Access Status Codes */ #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN (0x20) #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x21) #define MPI3_DEVICE0_ASTATUS_SIF_DIAG (0x22) #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x23) #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x24) #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN (0x25) #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN (0x26) #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27) #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28) #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29) +#define MPI3_DEVICE0_ASTATUS_SIF_DEVICE_FAULT (0x2A) #define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2F) /* PCIe Access Status Codes */ #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30) #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS (0x31) #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED (0x32) #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED (0x33) #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED (0x34) #define MPI3_DEVICE0_ASTATUS_PCIE_MAX (0x3F) /* NVMe Access Status Codes */ #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN (0x40) #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT (0x41) #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x42) #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED (0x43) #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED (0x44) #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED (0x45) #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED (0x46) #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x47) #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT (0x48) #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS (0x49) #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER (0x4A) #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE (0x4B) #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE (0x4C) #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION (0x4D) #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME (0x4E) #define MPI3_DEVICE0_ASTATUS_NVME_BAR (0x4F) #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR (0x50) #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS (0x51) #define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS (0x52) #define MPI3_DEVICE0_ASTATUS_NVME_MAX (0x5F) /* Virtual Device Access Status Codes */ #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x80) #define MPI3_DEVICE0_ASTATUS_VD_MAX (0x8F) /**** Defines for the Flags field ****/ #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK (0xE000) +#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_SHIFT (13) #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT (0x0000) #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB (0x2000) #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB (0x4000) #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080) #define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED (0x0010) #define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008) #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL (0x0004) #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED (0x0002) #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ defines ****/ /**** Defines for the DeviceForm field - use MPI3_DEVICE_DEVFORM_ defines ****/ /**** Defines for the QueueDepth field ****/ #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE (0x0000) /***************************************************************************** * Device Page 1 * ****************************************************************************/ typedef struct _MPI3_DEVICE1_SAS_SATA_FORMAT { U32 Reserved00; /* 0x00 */ } MPI3_DEVICE1_SAS_SATA_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_SAS_SATA_FORMAT, Mpi3Device1SasSataFormat_t, MPI3_POINTER pMpi3Device1SasSataFormat_t; typedef struct _MPI3_DEVICE1_PCIE_FORMAT { U16 VendorID; /* 0x00 */ U16 DeviceID; /* 0x02 */ U16 SubsystemVendorID; /* 0x04 */ U16 SubsystemID; /* 0x06 */ - U32 Reserved08; /* 0x08 */ + U16 ReadyTimeout; /* 0x08 */ + U16 Reserved0A; /* 0x0A */ U8 RevisionID; /* 0x0C */ U8 Reserved0D; /* 0x0D */ U16 PCIParameters; /* 0x0E */ } MPI3_DEVICE1_PCIE_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_PCIE_FORMAT, Mpi3Device1PcieFormat_t, MPI3_POINTER pMpi3Device1PcieFormat_t; /**** Defines for the PCIParameters field ****/ #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B (0x0) #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B (0x1) #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B (0x2) #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B (0x3) #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B (0x4) #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B (0x5) /*** MaxReadRequestSize, CurrentMaxPayloadSize, and MaxPayloadSizeSupported ***/ /*** all use the size definitions above - shifted to the proper position ***/ #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK (0x01C0) #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT (6) #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK (0x0038) #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT (3) #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK (0x0007) #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT (0) typedef struct _MPI3_DEVICE1_VD_FORMAT { U32 Reserved00; /* 0x00 */ } MPI3_DEVICE1_VD_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_VD_FORMAT, Mpi3Device1VdFormat_t, MPI3_POINTER pMpi3Device1VdFormat_t; typedef union _MPI3_DEVICE1_DEV_SPEC_FORMAT { MPI3_DEVICE1_SAS_SATA_FORMAT SasSataFormat; MPI3_DEVICE1_PCIE_FORMAT PcieFormat; MPI3_DEVICE1_VD_FORMAT VdFormat; } MPI3_DEVICE1_DEV_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_DEV_SPEC_FORMAT, Mpi3Device1DevSpecFormat_t, MPI3_POINTER pMpi3Device1DevSpecFormat_t; typedef struct _MPI3_DEVICE_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U16 DevHandle; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U16 LinkChangeCount; /* 0x0C */ U16 RateChangeCount; /* 0x0E */ U16 TMCount; /* 0x10 */ U16 Reserved12; /* 0x12 */ U32 Reserved14[10]; /* 0x14 */ U8 Reserved3C[3]; /* 0x3C */ U8 DeviceForm; /* 0x3F */ MPI3_DEVICE1_DEV_SPEC_FORMAT DeviceSpecific; /* 0x40 */ } MPI3_DEVICE_PAGE1, MPI3_POINTER PTR_MPI3_DEVICE_PAGE1, Mpi3DevicePage1_t, MPI3_POINTER pMpi3DevicePage1_t; /**** Defines for the PageVersion field ****/ #define MPI3_DEVICE1_PAGEVERSION (0x00) /**** Defines for the LinkChangeCount, RateChangeCount, TMCount fields ****/ #define MPI3_DEVICE1_COUNTER_MAX (0xFFFE) #define MPI3_DEVICE1_COUNTER_INVALID (0xFFFF) /**** Defines for the DeviceForm field - use MPI3_DEVICE_DEVFORM_ defines ****/ #endif /* MPI30_CNFG_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_image.h b/sys/dev/mpi3mr/mpi/mpi30_image.h index 917763b3e921..73451d80fe58 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_image.h +++ b/sys/dev/mpi3mr/mpi/mpi30_image.h @@ -1,421 +1,435 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ + #ifndef MPI30_IMAGE_H #define MPI30_IMAGE_H 1 /* Component Image Version */ typedef struct _MPI3_COMP_IMAGE_VERSION { U16 BuildNum; /* 0x00 */ U16 CustomerID; /* 0x02 */ U8 PhaseMinor; /* 0x04 */ U8 PhaseMajor; /* 0x05 */ U8 GenMinor; /* 0x06 */ U8 GenMajor; /* 0x07 */ } MPI3_COMP_IMAGE_VERSION, MPI3_POINTER PTR_MPI3_COMP_IMAGE_VERSION, Mpi3CompImageVersion_t, MPI3_POINTER pMpi3CompImageVersion_t; /* Hash Exclusion Format */ typedef struct _MPI3_HASH_EXCLUSION_FORMAT { U32 Offset; /* 0x00 */ U32 Size; /* 0x04 */ } MPI3_HASH_EXCLUSION_FORMAT, MPI3_POINTER PTR_MPI3_HASH_EXCLUSION_FORMAT, Mpi3HashSxclusionFormat_t, MPI3_POINTER pMpi3HashExclusionFormat_t; #define MPI3_IMAGE_HASH_EXCUSION_NUM (4) /* FW Image Header */ typedef struct _MPI3_COMPONENT_IMAGE_HEADER { U32 Signature0; /* 0x00 */ U32 LoadAddress; /* 0x04 */ U32 DataSize; /* 0x08 */ U32 StartOffset; /* 0x0C */ U32 Signature1; /* 0x10 */ U32 FlashOffset; /* 0x14 */ U32 ImageSize; /* 0x18 */ U32 VersionStringOffset; /* 0x1C */ U32 BuildDateStringOffset; /* 0x20 */ U32 BuildTimeStringOffset; /* 0x24 */ U32 EnvironmentVariableOffset; /* 0x28 */ U32 ApplicationSpecific; /* 0x2C */ U32 Signature2; /* 0x30 */ U32 HeaderSize; /* 0x34 */ U32 Crc; /* 0x38 */ U32 Flags; /* 0x3C */ U32 SecondaryFlashOffset; /* 0x40 */ U32 ETPOffset; /* 0x44 */ U32 ETPSize; /* 0x48 */ MPI3_VERSION_UNION RMCInterfaceVersion; /* 0x4C */ MPI3_VERSION_UNION ETPInterfaceVersion; /* 0x50 */ MPI3_COMP_IMAGE_VERSION ComponentImageVersion; /* 0x54 */ MPI3_HASH_EXCLUSION_FORMAT HashExclusion[MPI3_IMAGE_HASH_EXCUSION_NUM]; /* 0x5C */ U32 NextImageHeaderOffset; /* 0x7C */ MPI3_VERSION_UNION SecurityVersion; /* 0x80 */ U32 Reserved84[31]; /* 0x84 -- 0xFC */ } MPI3_COMPONENT_IMAGE_HEADER, MPI3_POINTER PTR_MPI3_COMPONENT_IMAGE_HEADER, Mpi3ComponentImageHeader_t, MPI3_POINTER pMpi3ComponentImageHeader_t; /**** Definitions for Signature0 field ****/ #define MPI3_IMAGE_HEADER_SIGNATURE0_MPI3 (0xEB00003E) /**** Definitions for LoadAddress field ****/ #define MPI3_IMAGE_HEADER_LOAD_ADDRESS_INVALID (0x00000000) /**** Definitions for Signature1 field ****/ #define MPI3_IMAGE_HEADER_SIGNATURE1_APPLICATION (0x20505041) /* string "APP " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_FIRST_MUTABLE (0x20434D46) /* string "FMC " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_BSP (0x20505342) /* string "BSP " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_ROM_BIOS (0x534F4942) /* string "BIOS" */ #define MPI3_IMAGE_HEADER_SIGNATURE1_HII_X64 (0x4D494948) /* string "HIIM" */ #define MPI3_IMAGE_HEADER_SIGNATURE1_HII_ARM (0x41494948) /* string "HIIA" */ #define MPI3_IMAGE_HEADER_SIGNATURE1_CPLD (0x444C5043) /* string "CPLD" */ #define MPI3_IMAGE_HEADER_SIGNATURE1_SPD (0x20445053) /* string "SPD " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_GAS_GAUGE (0x20534147) /* string "GAS " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_PBLP (0x504C4250) /* string "PBLP" */ #define MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST (0x464E414D) /* string "MANF" */ #define MPI3_IMAGE_HEADER_SIGNATURE1_OEM (0x204D454F) /* string "OEM " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_RMC (0x20434D52) /* string "RMC " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_SMM (0x204D4D53) /* string "SMM " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_PSW (0x20575350) /* string "PSW " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_CSW (0x20575343) /* string "CSW " */ /**** Definitions for Signature2 field ****/ #define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546) /**** Definitions for Flags field ****/ #define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_MASK (0x00000300) +#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_SHIFT (8) #define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_UNSPECIFIED (0x00000000) #define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_NOT_SIGNED (0x00000100) #define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_MICROSOFT_SIGNED (0x00000200) #define MPI3_IMAGE_HEADER_FLAGS_CERT_CHAIN_FORMAT_MASK (0x000000C0) +#define MPI3_IMAGE_HEADER_FLAGS_CERT_CHAIN_FORMAT_SHIFT (6) #define MPI3_IMAGE_HEADER_FLAGS_CERT_CHAIN_FORMAT_DEVICE_CERT (0x00000000) #define MPI3_IMAGE_HEADER_FLAGS_CERT_CHAIN_FORMAT_ALIAS_CERT (0x00000040) #define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK (0x00000030) +#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_SHIFT (4) #define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI (0x00000000) #define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_DI (0x00000010) #define MPI3_IMAGE_HEADER_FLAGS_SIGNED_NVDATA (0x00000008) #define MPI3_IMAGE_HEADER_FLAGS_REQUIRES_ACTIVATION (0x00000004) #define MPI3_IMAGE_HEADER_FLAGS_COMPRESSED (0x00000002) #define MPI3_IMAGE_HEADER_FLAGS_FLASH (0x00000001) /**** Offsets for Image Header Fields ****/ #define MPI3_IMAGE_HEADER_SIGNATURE0_OFFSET (0x00) #define MPI3_IMAGE_HEADER_LOAD_ADDRESS_OFFSET (0x04) #define MPI3_IMAGE_HEADER_DATA_SIZE_OFFSET (0x08) #define MPI3_IMAGE_HEADER_START_OFFSET_OFFSET (0x0C) #define MPI3_IMAGE_HEADER_SIGNATURE1_OFFSET (0x10) #define MPI3_IMAGE_HEADER_FLASH_OFFSET_OFFSET (0x14) #define MPI3_IMAGE_HEADER_FLASH_SIZE_OFFSET (0x18) #define MPI3_IMAGE_HEADER_VERSION_STRING_OFFSET_OFFSET (0x1C) #define MPI3_IMAGE_HEADER_BUILD_DATE_STRING_OFFSET_OFFSET (0x20) #define MPI3_IMAGE_HEADER_BUILD_TIME_OFFSET_OFFSET (0x24) #define MPI3_IMAGE_HEADER_ENVIROMENT_VAR_OFFSET_OFFSET (0x28) #define MPI3_IMAGE_HEADER_APPLICATION_SPECIFIC_OFFSET (0x2C) #define MPI3_IMAGE_HEADER_SIGNATURE2_OFFSET (0x30) #define MPI3_IMAGE_HEADER_HEADER_SIZE_OFFSET (0x34) #define MPI3_IMAGE_HEADER_CRC_OFFSET (0x38) #define MPI3_IMAGE_HEADER_FLAGS_OFFSET (0x3C) #define MPI3_IMAGE_HEADER_SECONDARY_FLASH_OFFSET_OFFSET (0x40) #define MPI3_IMAGE_HEADER_ETP_OFFSET_OFFSET (0x44) #define MPI3_IMAGE_HEADER_ETP_SIZE_OFFSET (0x48) #define MPI3_IMAGE_HEADER_RMC_INTERFACE_VER_OFFSET (0x4C) #define MPI3_IMAGE_HEADER_ETP_INTERFACE_VER_OFFSET (0x50) #define MPI3_IMAGE_HEADER_COMPONENT_IMAGE_VER_OFFSET (0x54) #define MPI3_IMAGE_HEADER_HASH_EXCLUSION_OFFSET (0x5C) #define MPI3_IMAGE_HEADER_NEXT_IMAGE_HEADER_OFFSET_OFFSET (0x7C) #define MPI3_IMAGE_HEADER_SIZE (0x100) /***************************************************************************** * Component Image Data * *****************************************************************************/ /* Package Manifest Data */ #ifndef MPI3_CI_MANIFEST_MPI_MAX #define MPI3_CI_MANIFEST_MPI_MAX (1) #endif /* MPI3_CI_MANIFEST_MPI_MAX */ typedef struct _MPI3_CI_MANIFEST_MPI_COMP_IMAGE_REF { U32 Signature1; /* 0x00 */ U32 Reserved04[3]; /* 0x04 */ MPI3_COMP_IMAGE_VERSION ComponentImageVersion; /* 0x10 */ U32 ComponentImageVersionStringOffset; /* 0x18 */ U32 CRC; /* 0x1C */ } MPI3_CI_MANIFEST_MPI_COMP_IMAGE_REF, MPI3_POINTER PTR_MPI3_CI_MANIFEST_MPI_COMP_IMAGE_REF, Mpi3CIManifestMpiCompImageRef_t, MPI3_POINTER pMpi3CIManifestMpiCompImageRef_t; typedef struct _MPI3_CI_MANIFEST_MPI { U8 ManifestType; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U32 Reserved04[3]; /* 0x04 */ U8 NumImageReferences; /* 0x10 */ U8 ReleaseLevel; /* 0x11 */ U16 Reserved12; /* 0x12 */ U16 Reserved14; /* 0x14 */ U16 Flags; /* 0x16 */ U32 Reserved18[2]; /* 0x18 */ U16 VendorID; /* 0x20 */ U16 DeviceID; /* 0x22 */ U16 SubsystemVendorID; /* 0x24 */ U16 SubsystemID; /* 0x26 */ U32 Reserved28[2]; /* 0x28 */ MPI3_VERSION_UNION PackageSecurityVersion; /* 0x30 */ U32 Reserved34; /* 0x34 */ MPI3_COMP_IMAGE_VERSION PackageVersion; /* 0x38 */ U32 PackageVersionStringOffset; /* 0x40 */ U32 PackageBuildDateStringOffset; /* 0x44 */ U32 PackageBuildTimeStringOffset; /* 0x48 */ U32 Reserved4C; /* 0x4C */ U32 DiagAuthorizationIdentifier[16]; /* 0x50 */ MPI3_CI_MANIFEST_MPI_COMP_IMAGE_REF ComponentImageRef[MPI3_CI_MANIFEST_MPI_MAX]; /* 0x90 */ /* variable length */ /* StringData - offset of this field must be calculated */ /* variable length */ } MPI3_CI_MANIFEST_MPI, MPI3_POINTER PTR_MPI3_CI_MANIFEST_MPI, Mpi3CIManifestMpi_t, MPI3_POINTER pMpi3CIManifestMpi_t; /* defines for the ReleaseLevel field */ #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_DEV (0x00) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_PRE_PRODUCTION (0x08) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_PREALPHA (0x10) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_ALPHA (0x20) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_BETA (0x30) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_RC (0x40) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_GCA (0x50) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_POINT (0x60) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_DIAG (0xF0) /* defines for the Flags field */ #define MPI3_CI_MANIFEST_MPI_FLAGS_DIAG_AUTHORIZATION (0x01) /* defines for the SubsystemID field */ #define MPI3_CI_MANIFEST_MPI_SUBSYSTEMID_IGNORED (0xFFFF) /* defines for the PackageVersionStringOffset field */ #define MPI3_CI_MANIFEST_MPI_PKG_VER_STR_OFF_UNSPECIFIED (0x00000000) /* defines for the PackageBuildDateStringOffset field */ #define MPI3_CI_MANIFEST_MPI_PKG_BUILD_DATE_STR_OFF_UNSPECIFIED (0x00000000) /* defines for the PackageBuildTimeStringOffset field */ #define MPI3_CI_MANIFEST_MPI_PKG_BUILD_TIME_STR_OFF_UNSPECIFIED (0x00000000) typedef union _MPI3_CI_MANIFEST { MPI3_CI_MANIFEST_MPI Mpi; U32 Dword[1]; } MPI3_CI_MANIFEST, MPI3_POINTER PTR_MPI3_CI_MANIFEST, Mpi3CIManifest_t, MPI3_POINTER pMpi3CIManifest_t; /* defines for ManifestType field */ #define MPI3_CI_MANIFEST_TYPE_MPI (0x00) /***************************************************************************** * Extended Image Data * *****************************************************************************/ /* Extended Image Header */ typedef struct _MPI3_EXTENDED_IMAGE_HEADER { U8 ImageType; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ U32 Checksum; /* 0x04 */ U32 ImageSize; /* 0x08 */ U32 NextImageHeaderOffset; /* 0x0C */ U32 Reserved10[4]; /* 0x10 */ U32 IdentifyString[8]; /* 0x20 */ } MPI3_EXTENDED_IMAGE_HEADER, MPI3_POINTER PTR_MPI3_EXTENDED_IMAGE_HEADER, Mpi3ExtendedImageHeader_t, MPI3_POINTER pMpi3ExtendedImageHeader_t; /* useful offsets */ #define MPI3_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) #define MPI3_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) #define MPI3_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) #define MPI3_EXT_IMAGE_HEADER_SIZE (0x40) /* defines for the ImageType field */ #define MPI3_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) #define MPI3_EXT_IMAGE_TYPE_NVDATA (0x03) #define MPI3_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) #define MPI3_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09) #define MPI3_EXT_IMAGE_TYPE_RDE (0x0A) #define MPI3_EXT_IMAGE_TYPE_AUXILIARY_PROCESSOR (0x0B) #define MPI3_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80) #define MPI3_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF) /* Supported Device Data Format */ typedef struct _MPI3_SUPPORTED_DEVICE { U16 DeviceID; /* 0x00 */ U16 VendorID; /* 0x02 */ U16 DeviceIDMask; /* 0x04 */ U16 Reserved06; /* 0x06 */ U8 LowPCIRev; /* 0x08 */ U8 HighPCIRev; /* 0x09 */ U16 Reserved0A; /* 0x0A */ U32 Reserved0C; /* 0x0C */ } MPI3_SUPPORTED_DEVICE, MPI3_POINTER PTR_MPI3_SUPPORTED_DEVICE, Mpi3SupportedDevice_t, MPI3_POINTER pMpi3SupportedDevice_t; #ifndef MPI3_SUPPORTED_DEVICE_MAX #define MPI3_SUPPORTED_DEVICE_MAX (1) #endif /* MPI3_SUPPORTED_DEVICE_MAX */ /* Supported Devices Extended Image Data */ typedef struct _MPI3_SUPPORTED_DEVICES_DATA { U8 ImageVersion; /* 0x00 */ U8 Reserved01; /* 0x01 */ U8 NumDevices; /* 0x02 */ U8 Reserved03; /* 0x03 */ U32 Reserved04; /* 0x04 */ MPI3_SUPPORTED_DEVICE SupportedDevice[MPI3_SUPPORTED_DEVICE_MAX]; /* 0x08 */ /* variable length */ } MPI3_SUPPORTED_DEVICES_DATA, MPI3_POINTER PTR_MPI3_SUPPORTED_DEVICES_DATA, Mpi3SupportedDevicesData_t, MPI3_POINTER pMpi3SupportedDevicesData_t; #ifndef MPI3_PUBLIC_KEY_MAX #define MPI3_PUBLIC_KEY_MAX (1) #endif /* MPI3_PUBLIC_KEY_MAX */ /* Encrypted Hash Entry Format */ typedef struct _MPI3_ENCRYPTED_HASH_ENTRY { U8 HashImageType; /* 0x00 */ U8 HashAlgorithm; /* 0x01 */ U8 EncryptionAlgorithm; /* 0x02 */ - U8 Reserved03; /* 0x03 */ + U8 Flags; /* 0x03 */ U16 PublicKeySize; /* 0x04 */ U16 SignatureSize; /* 0x06 */ U32 PublicKey[MPI3_PUBLIC_KEY_MAX]; /* 0x08 */ /* variable length */ /* Signature - offset of this field must be calculated */ /* variable length */ } MPI3_ENCRYPTED_HASH_ENTRY, MPI3_POINTER PTR_MPI3_ENCRYPTED_HASH_ENTRY, Mpi3EncryptedHashEntry_t, MPI3_POINTER pMpi3EncryptedHashEntry_t; /* defines for the HashImageType field */ -#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_SIGNATURE (0x03) +#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH (0x03) +#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH_1_OF_2 (0x04) +#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH_2_OF_2 (0x05) /* defines for the HashAlgorithm field */ #define MPI3_HASH_ALGORITHM_VERSION_MASK (0xE0) +#define MPI3_HASH_ALGORITHM_VERSION_SHIFT (5) #define MPI3_HASH_ALGORITHM_VERSION_NONE (0x00) #define MPI3_HASH_ALGORITHM_VERSION_SHA1 (0x20) /* Obsolete */ #define MPI3_HASH_ALGORITHM_VERSION_SHA2 (0x40) #define MPI3_HASH_ALGORITHM_VERSION_SHA3 (0x60) #define MPI3_HASH_ALGORITHM_SIZE_MASK (0x1F) +#define MPI3_HASH_ALGORITHM_SIZE_SHIFT (0) #define MPI3_HASH_ALGORITHM_SIZE_UNUSED (0x00) #define MPI3_HASH_ALGORITHM_SIZE_SHA256 (0x01) #define MPI3_HASH_ALGORITHM_SIZE_SHA512 (0x02) #define MPI3_HASH_ALGORITHM_SIZE_SHA384 (0x03) /* defines for the EncryptionAlgorithm field */ #define MPI3_ENCRYPTION_ALGORITHM_UNUSED (0x00) #define MPI3_ENCRYPTION_ALGORITHM_RSA256 (0x01) /* Obsolete */ #define MPI3_ENCRYPTION_ALGORITHM_RSA512 (0x02) /* Obsolete */ #define MPI3_ENCRYPTION_ALGORITHM_RSA1024 (0x03) /* Obsolete */ #define MPI3_ENCRYPTION_ALGORITHM_RSA2048 (0x04) #define MPI3_ENCRYPTION_ALGORITHM_RSA4096 (0x05) #define MPI3_ENCRYPTION_ALGORITHM_RSA3072 (0x06) #define MPI3_ENCRYPTION_ALGORITHM_ECDSA_P256 (0x07) /* NIST secp256r1 curve */ #define MPI3_ENCRYPTION_ALGORITHM_ECDSA_P384 (0x08) /* NIST secp384r1 curve */ #define MPI3_ENCRYPTION_ALGORITHM_ECDSA_P521 (0x09) /* NIST secp521r1 curve */ -#define MPI3_ENCRYPTION_ALGORITHM_LMS_HSS (0x0A) /* Leighton-Micali Signature (LMS) - - * Hierarchical Signature System (HSS) - */ +#define MPI3_ENCRYPTION_ALGORITHM_LMS_HSS (0x0A) /* Leighton-Micali Signature (LMS) */ + /* Hierarchical Signature System (HSS) */ +#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_87 (0x0B) /* Module-Lattice-Based Sig Algo - Category 5 */ +#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_65 (0x0C) /* Module-Lattice-Based Sig Algo - Category 3 */ +#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_44 (0x0D) /* Module-Lattice-Based Sig Algo - Category 2 */ + +/* defines for the Flags field */ +#define MPI3_ENCRYPTED_HASH_ENTRY_FLAGS_PAIRED_KEY_MASK (0x0F) +#define MPI3_ENCRYPTED_HASH_ENTRY_FLAGS_PAIRED_KEY_SHIFT (0) #ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX #define MPI3_ENCRYPTED_HASH_ENTRY_MAX (1) #endif /* MPI3_ENCRYPTED_HASH_ENTRY_MAX */ /* Encrypted Hash Image Data */ typedef struct _MPI3_ENCRYPTED_HASH_DATA { U8 ImageVersion; /* 0x00 */ U8 NumHash; /* 0x01 */ U16 Reserved02; /* 0x02 */ U32 Reserved04; /* 0x04 */ MPI3_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[MPI3_ENCRYPTED_HASH_ENTRY_MAX]; /* 0x08 */ /* variable length */ } MPI3_ENCRYPTED_HASH_DATA, MPI3_POINTER PTR_MPI3_ENCRYPTED_HASH_DATA, Mpi3EncryptedHashData_t, MPI3_POINTER pMpi3EncryptedHashData_t; #ifndef MPI3_AUX_PROC_DATA_MAX #define MPI3_AUX_PROC_DATA_MAX (1) #endif /* MPI3_ENCRYPTED_HASH_ENTRY_MAX */ /* Auxiliary Processor Extended Image Data */ typedef struct _MPI3_AUX_PROCESSOR_DATA { U8 BootMethod; /* 0x00 */ U8 NumLoadAddr; /* 0x01 */ U8 Reserved02; /* 0x02 */ U8 Type; /* 0x03 */ U32 Version; /* 0x04 */ U32 LoadAddress[8]; /* 0x08 */ U32 Reserved28[22]; /* 0x28 */ U32 AuxProcessorData[MPI3_AUX_PROC_DATA_MAX]; /* 0x80 */ /* variable length */ } MPI3_AUX_PROCESSOR_DATA, MPI3_POINTER PTR_MPI3_AUX_PROCESSOR_DATA, Mpi3AuxProcessorData_t, MPI3_POINTER pMpi3AuxProcessorData_t; #define MPI3_AUX_PROC_DATA_OFFSET (0x80) /* defines for the BootMethod field */ #define MPI3_AUXPROCESSOR_BOOT_METHOD_MO_MSG (0x00) #define MPI3_AUXPROCESSOR_BOOT_METHOD_MO_DOORBELL (0x01) #define MPI3_AUXPROCESSOR_BOOT_METHOD_COMPONENT (0x02) /* defines for the Type field */ #define MPI3_AUXPROCESSOR_TYPE_ARM_A15 (0x00) #define MPI3_AUXPROCESSOR_TYPE_ARM_M0 (0x01) #define MPI3_AUXPROCESSOR_TYPE_ARM_R4 (0x02) #endif /* MPI30_IMAGE_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_init.h b/sys/dev/mpi3mr/mpi/mpi30_init.h index 361fb690fbe6..c24725972162 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_init.h +++ b/sys/dev/mpi3mr/mpi/mpi30_init.h @@ -1,266 +1,274 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ + #ifndef MPI30_INIT_H #define MPI30_INIT_H 1 /***************************************************************************** * SCSI Initiator Messages * ****************************************************************************/ /***************************************************************************** * SCSI IO Request Message * ****************************************************************************/ typedef struct _MPI3_SCSI_IO_CDB_EEDP32 { U8 CDB[20]; /* 0x00 */ U32 PrimaryReferenceTag; /* 0x14 */ U16 PrimaryApplicationTag; /* 0x18 */ U16 PrimaryApplicationTagMask; /* 0x1A */ U32 TransferLength; /* 0x1C */ } MPI3_SCSI_IO_CDB_EEDP32, MPI3_POINTER PTR_MPI3_SCSI_IO_CDB_EEDP32, Mpi3ScsiIoCdbEedp32_t, MPI3_POINTER pMpi3ScsiIoCdbEedp32_t; typedef union _MPI3_SCSI_IO_CDB_UNION { U8 CDB32[32]; MPI3_SCSI_IO_CDB_EEDP32 EEDP32; MPI3_SGE_SIMPLE SGE; } MPI3_SCSI_IO_CDB_UNION, MPI3_POINTER PTR_MPI3_SCSI_IO_CDB_UNION, Mpi3ScsiIoCdb_t, MPI3_POINTER pMpi3ScsiIoCdb_t; typedef struct _MPI3_SCSI_IO_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 DevHandle; /* 0x0A */ U32 Flags; /* 0x0C */ U32 IOCUseOnly10; /* 0x10 */ U32 DataLength; /* 0x14 */ U8 LUN[8]; /* 0x18 */ MPI3_SCSI_IO_CDB_UNION CDB; /* 0x20 */ MPI3_SGE_UNION SGL[4]; /* 0x40 */ } MPI3_SCSI_IO_REQUEST, MPI3_POINTER PTR_MPI3_SCSI_IO_REQUEST, Mpi3SCSIIORequest_t, MPI3_POINTER pMpi3SCSIIORequest_t; /**** Defines for the MsgFlags field ****/ #define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID (0x80) #define MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE (0x40) /**** Defines for the Flags field ****/ #define MPI3_SCSIIO_FLAGS_LARGE_CDB_MASK (0x60000000) +#define MPI3_SCSIIO_FLAGS_LARGE_CDB_SHIFT (29) #define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS (0x00000000) #define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16 (0x20000000) #define MPI3_SCSIIO_FLAGS_CDB_IN_SEPARATE_BUFFER (0x40000000) #define MPI3_SCSIIO_FLAGS_CDB_PRODUCT_SPECIFIC (0x60000000) #define MPI3_SCSIIO_FLAGS_IOC_USE_ONLY_27_MASK (0x18000000) +#define MPI3_SCSIIO_FLAGS_IOC_USE_ONLY_27_SHIFT (27) #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_MASK (0x07000000) +#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SHIFT (24) #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SIMPLEQ (0x00000000) #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_HEADOFQ (0x01000000) #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ORDEREDQ (0x02000000) #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ACAQ (0x04000000) #define MPI3_SCSIIO_FLAGS_CMDPRI_MASK (0x00F00000) #define MPI3_SCSIIO_FLAGS_CMDPRI_SHIFT (20) #define MPI3_SCSIIO_FLAGS_DATADIRECTION_MASK (0x000C0000) +#define MPI3_SCSIIO_FLAGS_DATADIRECTION_SHIFT (18) #define MPI3_SCSIIO_FLAGS_DATADIRECTION_NO_DATA_TRANSFER (0x00000000) #define MPI3_SCSIIO_FLAGS_DATADIRECTION_WRITE (0x00040000) #define MPI3_SCSIIO_FLAGS_DATADIRECTION_READ (0x00080000) #define MPI3_SCSIIO_FLAGS_DMAOPERATION_MASK (0x00030000) +#define MPI3_SCSIIO_FLAGS_DMAOPERATION_SHIFT (16) #define MPI3_SCSIIO_FLAGS_DMAOPERATION_HOST_PI (0x00010000) #define MPI3_SCSIIO_FLAGS_DIVERT_REASON_MASK (0x000000F0) +#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_SHIFT (4) #define MPI3_SCSIIO_FLAGS_DIVERT_REASON_IO_THROTTLING (0x00000010) #define MPI3_SCSIIO_FLAGS_DIVERT_REASON_WRITE_SAME_TOO_LARGE (0x00000020) #define MPI3_SCSIIO_FLAGS_DIVERT_REASON_PROD_SPECIFIC (0x00000080) /**** Defines for the SGL field ****/ #define MPI3_SCSIIO_METASGL_INDEX (3) /***************************************************************************** * SCSI IO Error Reply Message * ****************************************************************************/ typedef struct _MPI3_SCSI_IO_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U8 SCSIStatus; /* 0x10 */ U8 SCSIState; /* 0x11 */ U16 DevHandle; /* 0x12 */ U32 TransferCount; /* 0x14 */ U32 SenseCount; /* 0x18 */ U32 ResponseData; /* 0x1C */ U16 TaskTag; /* 0x20 */ U16 SCSIStatusQualifier; /* 0x22 */ U32 EEDPErrorOffset; /* 0x24 */ U16 EEDPObservedAppTag; /* 0x28 */ U16 EEDPObservedGuard; /* 0x2A */ U32 EEDPObservedRefTag; /* 0x2C */ U64 SenseDataBufferAddress; /* 0x30 */ } MPI3_SCSI_IO_REPLY, MPI3_POINTER PTR_MPI3_SCSI_IO_REPLY, Mpi3SCSIIOReply_t, MPI3_POINTER pMpi3SCSIIOReply_t; /**** Defines for the MsgFlags field ****/ #define MPI3_SCSIIO_REPLY_MSGFLAGS_REFTAG_OBSERVED_VALID (0x01) #define MPI3_SCSIIO_REPLY_MSGFLAGS_APPTAG_OBSERVED_VALID (0x02) #define MPI3_SCSIIO_REPLY_MSGFLAGS_GUARD_OBSERVED_VALID (0x04) /**** Defines for the SCSIStatus field ****/ #define MPI3_SCSI_STATUS_GOOD (0x00) #define MPI3_SCSI_STATUS_CHECK_CONDITION (0x02) #define MPI3_SCSI_STATUS_CONDITION_MET (0x04) #define MPI3_SCSI_STATUS_BUSY (0x08) #define MPI3_SCSI_STATUS_INTERMEDIATE (0x10) #define MPI3_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14) #define MPI3_SCSI_STATUS_RESERVATION_CONFLICT (0x18) #define MPI3_SCSI_STATUS_COMMAND_TERMINATED (0x22) #define MPI3_SCSI_STATUS_TASK_SET_FULL (0x28) #define MPI3_SCSI_STATUS_ACA_ACTIVE (0x30) #define MPI3_SCSI_STATUS_TASK_ABORTED (0x40) /**** Defines for the SCSIState field ****/ #define MPI3_SCSI_STATE_SENSE_MASK (0x03) +#define MPI3_SCSI_STATE_SENSE_SHIFT (0) #define MPI3_SCSI_STATE_SENSE_VALID (0x00) #define MPI3_SCSI_STATE_SENSE_FAILED (0x01) #define MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY (0x02) #define MPI3_SCSI_STATE_SENSE_NOT_AVAILABLE (0x03) #define MPI3_SCSI_STATE_NO_SCSI_STATUS (0x04) #define MPI3_SCSI_STATE_TERMINATED (0x08) #define MPI3_SCSI_STATE_RESPONSE_DATA_VALID (0x10) /**** Defines for the ResponseData field ****/ #define MPI3_SCSI_RSP_RESPONSECODE_MASK (0x000000FF) #define MPI3_SCSI_RSP_RESPONSECODE_SHIFT (0) #define MPI3_SCSI_RSP_ARI2_MASK (0x0000FF00) #define MPI3_SCSI_RSP_ARI2_SHIFT (8) #define MPI3_SCSI_RSP_ARI1_MASK (0x00FF0000) #define MPI3_SCSI_RSP_ARI1_SHIFT (16) #define MPI3_SCSI_RSP_ARI0_MASK (0xFF000000) #define MPI3_SCSI_RSP_ARI0_SHIFT (24) /**** Defines for the TaskTag field ****/ #define MPI3_SCSI_TASKTAG_UNKNOWN (0xFFFF) /***************************************************************************** * SCSI Task Management Request Message * ****************************************************************************/ typedef struct _MPI3_SCSI_TASK_MGMT_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 DevHandle; /* 0x0A */ U16 TaskHostTag; /* 0x0C */ U8 TaskType; /* 0x0E */ U8 Reserved0F; /* 0x0F */ U16 TaskRequestQueueID; /* 0x10 */ U8 IOCUseOnly12; /* 0x12 */ U8 Reserved13; /* 0x13 */ U32 Reserved14; /* 0x14 */ U8 LUN[8]; /* 0x18 */ } MPI3_SCSI_TASK_MGMT_REQUEST, MPI3_POINTER PTR_MPI3_SCSI_TASK_MGMT_REQUEST, Mpi3SCSITaskMgmtRequest_t, MPI3_POINTER pMpi3SCSITaskMgmtRequest_t; /**** Defines for the MsgFlags field ****/ #define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x08) /**** Defines for the TaskType field ****/ #define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) #define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK_SET (0x02) #define MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) #define MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) #define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) #define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) #define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_ACA (0x08) #define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK_SET (0x09) #define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT (0x0A) #define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET (0x0B) /***************************************************************************** * SCSI Task Management Reply Message * ****************************************************************************/ typedef struct _MPI3_SCSI_TASK_MGMT_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U32 TerminationCount; /* 0x10 */ U32 ResponseData; /* 0x14 */ U32 Reserved18; /* 0x18 */ } MPI3_SCSI_TASK_MGMT_REPLY, MPI3_POINTER PTR_MPI3_SCSI_TASK_MGMT_REPLY, Mpi3SCSITaskMgmtReply_t, MPI3_POINTER pMpi3SCSITaskMgmtReply_t; /**** Defines for the ResponseData field - use MPI3_SCSI_RSP_ defines ****/ /**** Defines for the ResponseCode field - Byte 0 of ResponseData ****/ #define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE (0x00) #define MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME (0x02) #define MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED (0x04) #define MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED (0x05) #define MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED (0x08) #define MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN (0x09) #define MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG (0x0A) #define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80) #define MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED (0x81) #endif /* MPI30_INIT_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_ioc.h b/sys/dev/mpi3mr/mpi/mpi30_ioc.h index 2d45a55b89e8..dc7b478536c3 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_ioc.h +++ b/sys/dev/mpi3mr/mpi/mpi30_ioc.h @@ -1,1625 +1,1655 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ + #ifndef MPI30_IOC_H #define MPI30_IOC_H 1 /***************************************************************************** * IOC Messages * ****************************************************************************/ /***************************************************************************** * IOCInit Request Message * ****************************************************************************/ typedef struct _MPI3_IOC_INIT_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ MPI3_VERSION_UNION MPIVersion; /* 0x0C */ U64 TimeStamp; /* 0x10 */ U8 Reserved18; /* 0x18 */ U8 WhoInit; /* 0x19 */ U16 Reserved1A; /* 0x1A */ U16 ReplyFreeQueueDepth; /* 0x1C */ U16 Reserved1E; /* 0x1E */ U64 ReplyFreeQueueAddress; /* 0x20 */ U32 Reserved28; /* 0x28 */ U16 SenseBufferFreeQueueDepth; /* 0x2C */ U16 SenseBufferLength; /* 0x2E */ U64 SenseBufferFreeQueueAddress; /* 0x30 */ U64 DriverInformationAddress; /* 0x38 */ } MPI3_IOC_INIT_REQUEST, MPI3_POINTER PTR_MPI3_IOC_INIT_REQUEST, Mpi3IOCInitRequest_t, MPI3_POINTER pMpi3IOCInitRequest_t; /**** Defines for the MsgFlags field ****/ #define MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED (0x08) #define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0x04) #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03) +#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SHIFT (0) #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00) #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01) #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02) #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03) /**** Defines for the WhoInit field ****/ #define MPI3_WHOINIT_NOT_INITIALIZED (0x00) #define MPI3_WHOINIT_ROM_BIOS (0x02) #define MPI3_WHOINIT_HOST_DRIVER (0x03) #define MPI3_WHOINIT_MANUFACTURER (0x04) /**** Defines for the DriverInformationAddress field */ typedef struct _MPI3_DRIVER_INFO_LAYOUT { U32 InformationLength; /* 0x00 */ U8 DriverSignature[12]; /* 0x04 */ U8 OsName[16]; /* 0x10 */ U8 OsVersion[12]; /* 0x20 */ U8 DriverName[20]; /* 0x2C */ U8 DriverVersion[32]; /* 0x40 */ U8 DriverReleaseDate[20]; /* 0x60 */ U32 DriverCapabilities; /* 0x74 */ } MPI3_DRIVER_INFO_LAYOUT, MPI3_POINTER PTR_MPI3_DRIVER_INFO_LAYOUT, Mpi3DriverInfoLayout_t, MPI3_POINTER pMpi3DriverInfoLayout_t; +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_MASK (0x00000003) +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_SHIFT (0) +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_GUIDANCE (0x00000000) +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_SPECIAL (0x00000001) +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_HDD (0x00000002) +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_SSD (0x00000003) + /***************************************************************************** * IOCFacts Request Message * ****************************************************************************/ typedef struct _MPI3_IOC_FACTS_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U32 Reserved0C; /* 0x0C */ MPI3_SGE_UNION SGL; /* 0x10 */ } MPI3_IOC_FACTS_REQUEST, MPI3_POINTER PTR_MPI3_IOC_FACTS_REQUEST, Mpi3IOCFactsRequest_t, MPI3_POINTER pMpi3IOCFactsRequest_t; /***************************************************************************** * IOCFacts Data * ****************************************************************************/ typedef struct _MPI3_IOC_FACTS_DATA { U16 IOCFactsDataLength; /* 0x00 */ U16 Reserved02; /* 0x02 */ MPI3_VERSION_UNION MPIVersion; /* 0x04 */ MPI3_COMP_IMAGE_VERSION FWVersion; /* 0x08 */ U32 IOCCapabilities; /* 0x10 */ U8 IOCNumber; /* 0x14 */ U8 WhoInit; /* 0x15 */ U16 MaxMSIxVectors; /* 0x16 */ U16 MaxOutstandingRequests; /* 0x18 */ U16 ProductID; /* 0x1A */ U16 IOCRequestFrameSize; /* 0x1C */ U16 ReplyFrameSize; /* 0x1E */ U16 IOCExceptions; /* 0x20 */ U16 MaxPersistentID; /* 0x22 */ U8 SGEModifierMask; /* 0x24 */ U8 SGEModifierValue; /* 0x25 */ U8 SGEModifierShift; /* 0x26 */ U8 ProtocolFlags; /* 0x27 */ U16 MaxSASInitiators; /* 0x28 */ U16 MaxDataLength; /* 0x2A */ U16 MaxSASExpanders; /* 0x2C */ U16 MaxEnclosures; /* 0x2E */ U16 MinDevHandle; /* 0x30 */ U16 MaxDevHandle; /* 0x32 */ U16 MaxPCIeSwitches; /* 0x34 */ U16 MaxNVMe; /* 0x36 */ U16 Reserved38; /* 0x38 */ U16 MaxVDs; /* 0x3A */ U16 MaxHostPDs; /* 0x3C */ U16 MaxAdvHostPDs; /* 0x3E */ U16 MaxRAIDPDs; /* 0x40 */ U16 MaxPostedCmdBuffers; /* 0x42 */ U32 Flags; /* 0x44 */ U16 MaxOperationalRequestQueues; /* 0x48 */ U16 MaxOperationalReplyQueues; /* 0x4A */ U16 ShutdownTimeout; /* 0x4C */ U16 Reserved4E; /* 0x4E */ U32 DiagTraceSize; /* 0x50 */ U32 DiagFwSize; /* 0x54 */ U32 DiagDriverSize; /* 0x58 */ U8 MaxHostPDNsCount; /* 0x5C */ U8 MaxAdvHostPDNsCount; /* 0x5D */ U8 MaxRAIDPDNsCount; /* 0x5E */ U8 MaxDevicesPerThrottleGroup; /* 0x5F */ U16 IOThrottleDataLength; /* 0x60 */ U16 MaxIOThrottleGroup; /* 0x62 */ U16 IOThrottleLow; /* 0x64 */ U16 IOThrottleHigh; /* 0x66 */ U32 DiagFdlSize; /* 0x68 */ U32 DiagTtySize; /* 0x6C */ } MPI3_IOC_FACTS_DATA, MPI3_POINTER PTR_MPI3_IOC_FACTS_DATA, Mpi3IOCFactsData_t, MPI3_POINTER pMpi3IOCFactsData_t; /**** Defines for the IOCCapabilities field ****/ #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000) +#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_SHIFT (31) #define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000) #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x80000000) #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600) +#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_SHIFT (9) #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000) #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200) #define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_SUPPORTED (0x00000100) #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED (0x00000080) #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_SUPPORTED (0x00000040) #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_SUPPORTED (0x00000020) #define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_SUPPORTED (0x00000010) #define MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED (0x00000008) #define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED (0x00000002) #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001) /**** WhoInit values are defined under IOCInit Request Message definition ****/ /**** Defines for the ProductID field ****/ #define MPI3_IOCFACTS_PID_TYPE_MASK (0xF000) #define MPI3_IOCFACTS_PID_TYPE_SHIFT (12) #define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0F00) #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8) #define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00FF) #define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0) /**** Defines for the IOCExceptions field ****/ #define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0x2000) #define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000) #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700) +#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_SHIFT (8) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0x0300) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0400) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0500) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0x0600) #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080) #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040) #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020) #define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010) #define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008) +#define MPI3_IOCFACTS_EXCEPT_BLOCKING_BOOT_EVENT (0x0004) +#define MPI3_IOCFACTS_EXCEPT_SECURITY_SELFTEST_FAILURE (0x0002) #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001) +#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SHIFT (0) #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000) #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001) /**** Defines for the ProtocolFlags field ****/ #define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010) #define MPI3_IOCFACTS_PROTOCOL_SATA (0x0008) #define MPI3_IOCFACTS_PROTOCOL_NVME (0x0004) #define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) #define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) /**** Defines for the MaxDataLength field ****/ #define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED (0x0000) /**** Defines for the Flags field ****/ #define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000) #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000FF00) #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8) #define MPI3_IOCFACTS_FLAGS_MAX_REQ_PER_REPLY_QUEUE_LIMIT (0x00000040) #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030) +#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_SHIFT (4) #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000) #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010) #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020) #define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000F) +#define MPI3_IOCFACTS_FLAGS_PERSONALITY_SHIFT (0) #define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000) #define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002) /**** Defines for the IOThrottleDataLength field ****/ #define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000) /**** Defines for the MaxIOThrottleGroup field ****/ #define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000) /**** Defines for the DiagFdlSize field ****/ #define MPI3_IOCFACTS_DIAGFDLSIZE_NOT_SUPPORTED (0x00000000) /**** Defines for the DiagTtySize field ****/ #define MPI3_IOCFACTS_DIAGTTYSIZE_NOT_SUPPORTED (0x00000000) /***************************************************************************** * Management Passthrough Request Message * ****************************************************************************/ typedef struct _MPI3_MGMT_PASSTHROUGH_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U32 Reserved0C[5]; /* 0x0C */ MPI3_SGE_UNION CommandSGL; /* 0x20 */ MPI3_SGE_UNION ResponseSGL; /* 0x30 */ } MPI3_MGMT_PASSTHROUGH_REQUEST, MPI3_POINTER PTR_MPI3_MGMT_PASSTHROUGH_REQUEST, Mpi3MgmtPassthroughRequest_t, MPI3_POINTER pMpi3MgmtPassthroughRequest_t; /***************************************************************************** * CreateRequestQueue Request Message * ****************************************************************************/ typedef struct _MPI3_CREATE_REQUEST_QUEUE_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Flags; /* 0x0A */ U8 Burst; /* 0x0B */ U16 Size; /* 0x0C */ U16 QueueID; /* 0x0E */ U16 ReplyQueueID; /* 0x10 */ U16 Reserved12; /* 0x12 */ U32 Reserved14; /* 0x14 */ U64 BaseAddress; /* 0x18 */ } MPI3_CREATE_REQUEST_QUEUE_REQUEST, MPI3_POINTER PTR_MPI3_CREATE_REQUEST_QUEUE_REQUEST, Mpi3CreateRequestQueueRequest_t, MPI3_POINTER pMpi3CreateRequestQueueRequest_t; /**** Defines for the Flags field ****/ #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80) +#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SHIFT (7) #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) /**** Defines for the Size field ****/ #define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2) /***************************************************************************** * DeleteRequestQueue Request Message * ****************************************************************************/ typedef struct _MPI3_DELETE_REQUEST_QUEUE_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 QueueID; /* 0x0A */ } MPI3_DELETE_REQUEST_QUEUE_REQUEST, MPI3_POINTER PTR_MPI3_DELETE_REQUEST_QUEUE_REQUEST, Mpi3DeleteRequestQueueRequest_t, MPI3_POINTER pMpi3DeleteRequestQueueRequest_t; /***************************************************************************** * CreateReplyQueue Request Message * ****************************************************************************/ typedef struct _MPI3_CREATE_REPLY_QUEUE_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Flags; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U16 Size; /* 0x0C */ U16 QueueID; /* 0x0E */ U16 MSIxIndex; /* 0x10 */ U16 Reserved12; /* 0x12 */ U32 Reserved14; /* 0x14 */ U64 BaseAddress; /* 0x18 */ } MPI3_CREATE_REPLY_QUEUE_REQUEST, MPI3_POINTER PTR_MPI3_CREATE_REPLY_QUEUE_REQUEST, Mpi3CreateReplyQueueRequest_t, MPI3_POINTER pMpi3CreateReplyQueueRequest_t; /**** Defines for the Flags field ****/ #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80) +#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SHIFT (7) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0x02) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01) +#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_SHIFT (0) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01) /**** Defines for the Size field ****/ #define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2) /***************************************************************************** * DeleteReplyQueue Request Message * ****************************************************************************/ typedef struct _MPI3_DELETE_REPLY_QUEUE_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 QueueID; /* 0x0A */ } MPI3_DELETE_REPLY_QUEUE_REQUEST, MPI3_POINTER PTR_MPI3_DELETE_REPLY_QUEUE_REQUEST, Mpi3DeleteReplyQueueRequest_t, MPI3_POINTER pMpi3DeleteReplyQueueRequest_t; /***************************************************************************** * PortEnable Request Message * ****************************************************************************/ typedef struct _MPI3_PORT_ENABLE_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ } MPI3_PORT_ENABLE_REQUEST, MPI3_POINTER PTR_MPI3_PORT_ENABLE_REQUEST, Mpi3PortEnableRequest_t, MPI3_POINTER pMpi3PortEnableRequest_t; /***************************************************************************** * IOC Events and Event Management * ****************************************************************************/ #define MPI3_EVENT_LOG_DATA (0x01) #define MPI3_EVENT_CHANGE (0x02) #define MPI3_EVENT_GPIO_INTERRUPT (0x04) #define MPI3_EVENT_CABLE_MGMT (0x06) #define MPI3_EVENT_DEVICE_ADDED (0x07) #define MPI3_EVENT_DEVICE_INFO_CHANGED (0x08) #define MPI3_EVENT_PREPARE_FOR_RESET (0x09) #define MPI3_EVENT_COMP_IMAGE_ACT_START (0x0A) #define MPI3_EVENT_ENCL_DEVICE_ADDED (0x0B) #define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x0C) #define MPI3_EVENT_DEVICE_STATUS_CHANGE (0x0D) #define MPI3_EVENT_ENERGY_PACK_CHANGE (0x0E) #define MPI3_EVENT_SAS_DISCOVERY (0x11) #define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0x12) #define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0x13) #define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x14) #define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0x15) #define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x16) #define MPI3_EVENT_SAS_PHY_COUNTER (0x18) #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19) #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20) #define MPI3_EVENT_PCIE_ENUMERATION (0x22) #define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0x23) #define MPI3_EVENT_HARD_RESET_RECEIVED (0x40) #define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0x50) #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60) #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7F) /***************************************************************************** * Event Notification Request Message * ****************************************************************************/ #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4) typedef struct _MPI3_EVENT_NOTIFICATION_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U16 SASBroadcastPrimitiveMasks; /* 0x0C */ U16 SASNotifyPrimitiveMasks; /* 0x0E */ U32 EventMasks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; /* 0x10 */ } MPI3_EVENT_NOTIFICATION_REQUEST, MPI3_POINTER PTR_MPI3_EVENT_NOTIFICATION_REQUEST, Mpi3EventNotificationRequest_t, MPI3_POINTER pMpi3EventNotificationRequest_t; /**** Defines for the SASBroadcastPrimitiveMasks field - use MPI3_EVENT_BROADCAST_PRIMITIVE_ values ****/ /**** Defines for the SASNotifyPrimitiveMasks field - use MPI3_EVENT_NOTIFY_PRIMITIVE_ values ****/ /**** Defines for the EventMasks field - use MPI3_EVENT_ values ****/ /***************************************************************************** * Event Notification Reply Message * ****************************************************************************/ typedef struct _MPI3_EVENT_NOTIFICATION_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U8 EventDataLength; /* 0x10 */ U8 Event; /* 0x11 */ U16 IOCChangeCount; /* 0x12 */ U32 EventContext; /* 0x14 */ U32 EventData[1]; /* 0x18 */ } MPI3_EVENT_NOTIFICATION_REPLY, MPI3_POINTER PTR_MPI3_EVENT_NOTIFICATION_REPLY, Mpi3EventNotificationReply_t, MPI3_POINTER pMpi3EventNotificationReply_t; /**** Defines for the MsgFlags field ****/ #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01) +#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_SHIFT (0) #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01) #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00) #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02) +#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_SHIFT (1) #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00) #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02) /**** Defines for the Event field - use MPI3_EVENT_ values ****/ /***************************************************************************** * GPIO Interrupt Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_GPIO_INTERRUPT { U8 GPIONum; /* 0x00 */ U8 Reserved01[3]; /* 0x01 */ } MPI3_EVENT_DATA_GPIO_INTERRUPT, MPI3_POINTER PTR_MPI3_EVENT_DATA_GPIO_INTERRUPT, Mpi3EventDataGpioInterrupt_t, MPI3_POINTER pMpi3EventDataGpioInterrupt_t; /***************************************************************************** * Cable Management Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_CABLE_MANAGEMENT { U32 ActiveCablePowerRequirement; /* 0x00 */ U8 Status; /* 0x04 */ U8 ReceptacleID; /* 0x05 */ U16 Reserved06; /* 0x06 */ } MPI3_EVENT_DATA_CABLE_MANAGEMENT, MPI3_POINTER PTR_MPI3_EVENT_DATA_CABLE_MANAGEMENT, Mpi3EventDataCableManagement_t, MPI3_POINTER pMpi3EventDataCableManagement_t; /**** Defines for the ActiveCablePowerRequirement field ****/ #define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0xFFFFFFFF) /**** Defines for the Status field ****/ #define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0x00) #define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0x01) #define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0x02) /***************************************************************************** * Event Ack Request Message * ****************************************************************************/ typedef struct _MPI3_EVENT_ACK_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U8 Event; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ U32 EventContext; /* 0x10 */ } MPI3_EVENT_ACK_REQUEST, MPI3_POINTER PTR_MPI3_EVENT_ACK_REQUEST, Mpi3EventAckRequest_t, MPI3_POINTER pMpi3EventAckRequest_t; /**** Defines for the Event field - use MPI3_EVENT_ values ****/ /***************************************************************************** * Prepare for Reset Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_PREPARE_FOR_RESET { U8 ReasonCode; /* 0x00 */ U8 Reserved01; /* 0x01 */ U16 Reserved02; /* 0x02 */ } MPI3_EVENT_DATA_PREPARE_FOR_RESET, MPI3_POINTER PTR_MPI3_EVENT_DATA_PREPARE_FOR_RESET, Mpi3EventDataPrepareForReset_t, MPI3_POINTER pMpi3EventDataPrepareForReset_t; /**** Defines for the ReasonCode field ****/ #define MPI3_EVENT_PREPARE_RESET_RC_START (0x01) #define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0x02) /***************************************************************************** * Component Image Activation Start Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_COMP_IMAGE_ACTIVATION { U32 Reserved00; /* 0x00 */ } MPI3_EVENT_DATA_COMP_IMAGE_ACTIVATION, MPI3_POINTER PTR_MPI3_EVENT_DATA_COMP_IMAGE_ACTIVATION, Mpi3EventDataCompImageActivation_t, MPI3_POINTER pMpi3EventDataCompImageActivation_t; /***************************************************************************** * Device Added Event * ****************************************************************************/ /* * The Device Added Event Data is exactly the same as Device Page 0 data * (including the Configuration Page header). So, please use/refer to * MPI3_DEVICE_PAGE0 structure for Device Added Event data. */ /**************************************************************************** * Device Info Changed Event * ****************************************************************************/ /* * The Device Info Changed Event Data is exactly the same as Device Page 0 data * (including the Configuration Page header). So, please use/refer to * MPI3_DEVICE_PAGE0 structure for Device Added Event data. */ /***************************************************************************** * Device Status Change Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_DEVICE_STATUS_CHANGE { U16 TaskTag; /* 0x00 */ U8 ReasonCode; /* 0x02 */ U8 IOUnitPort; /* 0x03 */ U16 ParentDevHandle; /* 0x04 */ U16 DevHandle; /* 0x06 */ U64 WWID; /* 0x08 */ U8 LUN[8]; /* 0x10 */ } MPI3_EVENT_DATA_DEVICE_STATUS_CHANGE, MPI3_POINTER PTR_MPI3_EVENT_DATA_DEVICE_STATUS_CHANGE, Mpi3EventDataDeviceStatusChange_t, MPI3_POINTER pMpi3EventDataDeviceStatusChange_t; /**** Defines for the ReasonCode field ****/ #define MPI3_EVENT_DEV_STAT_RC_MOVED (0x01) #define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0x02) #define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0x03) #define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0x04) #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0x20) #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0x21) #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0x22) #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0x23) #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0x24) #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0x25) #define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x30) #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0x40) #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0x41) #define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0x50) /***************************************************************************** * Energy Pack Change Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_ENERGY_PACK_CHANGE { U32 Reserved00; /* 0x00 */ U16 ShutdownTimeout; /* 0x04 */ U16 Reserved06; /* 0x06 */ } MPI3_EVENT_DATA_ENERGY_PACK_CHANGE, MPI3_POINTER PTR_MPI3_EVENT_DATA_ENERGY_PACK_CHANGE, Mpi3EventDataEnergyPackChange_t, MPI3_POINTER pMpi3EventDataEnergyPackChange_t; /***************************************************************************** * SAS Discovery Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_SAS_DISCOVERY { U8 Flags; /* 0x00 */ U8 ReasonCode; /* 0x01 */ U8 IOUnitPort; /* 0x02 */ U8 Reserved03; /* 0x03 */ U32 DiscoveryStatus; /* 0x04 */ } MPI3_EVENT_DATA_SAS_DISCOVERY, MPI3_POINTER PTR_MPI3_EVENT_DATA_SAS_DISCOVERY, Mpi3EventDataSasDiscovery_t, MPI3_POINTER pMpi3EventDataSasDiscovery_t; /**** Defines for the Flags field ****/ #define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0x02) #define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0x01) /**** Defines for the ReasonCode field ****/ #define MPI3_EVENT_SAS_DISC_RC_STARTED (0x01) #define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0x02) /**** Defines for the DiscoveryStatus field ****/ #define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0x80000000) #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000) #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000) #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000) #define MPI3_SAS_DISC_STATUS_INVALID_CEI (0x00010000) #define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0x00008000) #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000) #define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0x00002000) #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000) #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800) #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400) #define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0x00000200) #define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0x00000100) #define MPI3_SAS_DISC_STATUS_TABLE_LINK (0x00000080) #define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0x00000040) #define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0x00000020) #define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0x00000010) #define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0x00000008) #define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0x00000004) #define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0x00000002) #define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0x00000001) /***************************************************************************** * SAS Broadcast Primitive Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_SAS_BROADCAST_PRIMITIVE { U8 PhyNum; /* 0x00 */ U8 IOUnitPort; /* 0x01 */ U8 PortWidth; /* 0x02 */ U8 Primitive; /* 0x03 */ } MPI3_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, MPI3_POINTER PTR_MPI3_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, Mpi3EventDataSasBroadcastPrimitive_t, MPI3_POINTER pMpi3EventDataSasBroadcastPrimitive_t; /**** Defines for the Primitive field ****/ #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0x01) #define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0x02) #define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0x03) #define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0x05) #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0x06) #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0x07) #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0x08) /***************************************************************************** * SAS Notify Primitive Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_SAS_NOTIFY_PRIMITIVE { U8 PhyNum; /* 0x00 */ U8 IOUnitPort; /* 0x01 */ U8 Reserved02; /* 0x02 */ U8 Primitive; /* 0x03 */ } MPI3_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, MPI3_POINTER PTR_MPI3_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, Mpi3EventDataSasNotifyPrimitive_t, MPI3_POINTER pMpi3EventDataSasNotifyPrimitive_t; /**** Defines for the Primitive field ****/ #define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0x01) #define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0x02) #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0x03) #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0x04) /***************************************************************************** * SAS Topology Change List Event * ****************************************************************************/ #ifndef MPI3_EVENT_SAS_TOPO_PHY_COUNT #define MPI3_EVENT_SAS_TOPO_PHY_COUNT (1) #endif /* MPI3_EVENT_SAS_TOPO_PHY_COUNT */ typedef struct _MPI3_EVENT_SAS_TOPO_PHY_ENTRY { U16 AttachedDevHandle; /* 0x00 */ U8 LinkRate; /* 0x02 */ U8 PhyStatus; /* 0x03 */ } MPI3_EVENT_SAS_TOPO_PHY_ENTRY, MPI3_POINTER PTR_MPI3_EVENT_SAS_TOPO_PHY_ENTRY, Mpi3EventSasTopoPhyEntry_t, MPI3_POINTER pMpi3EventSasTopoPhyEntry_t; /**** Defines for the LinkRate field ****/ #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) #define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) #define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) #define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) #define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) #define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) #define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) #define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) #define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) #define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) #define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) #define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) #define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C) /**** Defines for the PhyStatus field ****/ #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0xC0) #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6) #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0x00) #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40) #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80) #define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0F) +#define MPI3_EVENT_SAS_TOPO_PHY_RC_SHIFT (0) #define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02) #define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03) #define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04) #define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0x05) #define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0x06) typedef struct _MPI3_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST { U16 EnclosureHandle; /* 0x00 */ U16 ExpanderDevHandle; /* 0x02 */ U8 NumPhys; /* 0x04 */ U8 Reserved05[3]; /* 0x05 */ U8 NumEntries; /* 0x08 */ U8 StartPhyNum; /* 0x09 */ U8 ExpStatus; /* 0x0A */ U8 IOUnitPort; /* 0x0B */ MPI3_EVENT_SAS_TOPO_PHY_ENTRY PhyEntry[MPI3_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C */ } MPI3_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, MPI3_POINTER PTR_MPI3_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, Mpi3EventDataSasTopologyChangeList_t, MPI3_POINTER pMpi3EventDataSasTopologyChangeList_t; /**** Defines for the ExpStatus field ****/ #define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) #define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) #define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0x03) #define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) /***************************************************************************** * SAS PHY Counter Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_SAS_PHY_COUNTER { U64 TimeStamp; /* 0x00 */ U32 Reserved08; /* 0x08 */ U8 PhyEventCode; /* 0x0C */ U8 PhyNum; /* 0x0D */ U16 Reserved0E; /* 0x0E */ U32 PhyEventInfo; /* 0x10 */ U8 CounterType; /* 0x14 */ U8 ThresholdWindow; /* 0x15 */ U8 TimeUnits; /* 0x16 */ U8 Reserved17; /* 0x17 */ U32 EventThreshold; /* 0x18 */ U16 ThresholdFlags; /* 0x1C */ U16 Reserved1E; /* 0x1E */ } MPI3_EVENT_DATA_SAS_PHY_COUNTER, MPI3_POINTER PTR_MPI3_EVENT_DATA_SAS_PHY_COUNTER, Mpi3EventDataSasPhyCounter_t, MPI3_POINTER pMpi3EventDataSasPhyCounter_t; /**** Defines for the PhyEventCode field - use MPI3_SASPHY3_EVENT_CODE_ defines ****/ /**** Defines for the CounterType field - use MPI3_SASPHY3_COUNTER_TYPE_ defines ****/ /**** Defines for the TimeUnits field - use MPI3_SASPHY3_TIME_UNITS_ defines ****/ /**** Defines for the ThresholdFlags field - use MPI3_SASPHY3_TFLAGS_ defines ****/ /***************************************************************************** * SAS Device Discovery Error Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_SAS_DEVICE_DISC_ERR { U16 DevHandle; /* 0x00 */ U8 ReasonCode; /* 0x02 */ U8 IOUnitPort; /* 0x03 */ U32 Reserved04; /* 0x04 */ U64 SASAddress; /* 0x08 */ } MPI3_EVENT_DATA_SAS_DEVICE_DISC_ERR, MPI3_POINTER PTR_MPI3_EVENT_DATA_SAS_DEVICE_DISC_ERR, Mpi3EventDataSasDeviceDiscErr_t, MPI3_POINTER pMpi3EventDataSasDeviceDiscErr_t; /**** Defines for the ReasonCode field ****/ #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0x01) #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0x02) /***************************************************************************** * PCIe Enumeration Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_PCIE_ENUMERATION { U8 Flags; /* 0x00 */ U8 ReasonCode; /* 0x01 */ U8 IOUnitPort; /* 0x02 */ U8 Reserved03; /* 0x03 */ U32 EnumerationStatus; /* 0x04 */ } MPI3_EVENT_DATA_PCIE_ENUMERATION, MPI3_POINTER PTR_MPI3_EVENT_DATA_PCIE_ENUMERATION, Mpi3EventDataPcieEnumeration_t, MPI3_POINTER pMpi3EventDataPcieEnumeration_t; /**** Defines for the Flags field ****/ #define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0x02) #define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0x01) /**** Defines for the ReasonCode field ****/ #define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0x01) #define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) /**** Defines for the EnumerationStatus field ****/ #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0x80000000) #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) #define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) #define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) /***************************************************************************** * PCIe Topology Change List Event * ****************************************************************************/ #ifndef MPI3_EVENT_PCIE_TOPO_PORT_COUNT #define MPI3_EVENT_PCIE_TOPO_PORT_COUNT (1) #endif /* MPI3_EVENT_PCIE_TOPO_PORT_COUNT */ typedef struct _MPI3_EVENT_PCIE_TOPO_PORT_ENTRY { U16 AttachedDevHandle; /* 0x00 */ U8 PortStatus; /* 0x02 */ U8 Reserved03; /* 0x03 */ U8 CurrentPortInfo; /* 0x04 */ U8 Reserved05; /* 0x05 */ U8 PreviousPortInfo; /* 0x06 */ U8 Reserved07; /* 0x07 */ } MPI3_EVENT_PCIE_TOPO_PORT_ENTRY, MPI3_POINTER PTR_MPI3_EVENT_PCIE_TOPO_PORT_ENTRY, Mpi3EventPcieTopoPortEntry_t, MPI3_POINTER pMpi3EventPcieTopoPortEntry_t; /**** Defines for the PortStatus field ****/ #define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) #define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) #define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) #define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) #define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06) /**** Defines for the CurrentPortInfo and PreviousPortInfo field ****/ #define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xF0) +#define MPI3_EVENT_PCIE_TOPO_PI_LANES_SHIFT (4) #define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) #define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10) #define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20) #define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30) #define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40) #define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F) +#define MPI3_EVENT_PCIE_TOPO_PI_RATE_SHIFT (0) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0x06) typedef struct _MPI3_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST { U16 EnclosureHandle; /* 0x00 */ U16 SwitchDevHandle; /* 0x02 */ U8 NumPorts; /* 0x04 */ U8 Reserved05[3]; /* 0x05 */ U8 NumEntries; /* 0x08 */ U8 StartPortNum; /* 0x09 */ U8 SwitchStatus; /* 0x0A */ U8 IOUnitPort; /* 0x0B */ U32 Reserved0C; /* 0x0C */ MPI3_EVENT_PCIE_TOPO_PORT_ENTRY PortEntry[MPI3_EVENT_PCIE_TOPO_PORT_COUNT]; /* 0x10 */ } MPI3_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, MPI3_POINTER PTR_MPI3_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, Mpi3EventDataPcieTopologyChangeList_t, MPI3_POINTER pMpi3EventDataPcieTopologyChangeList_t; /**** Defines for the SwitchStatus field ****/ #define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) /***************************************************************************** * PCIe Error Threshold Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_PCIE_ERROR_THRESHOLD { U64 Timestamp; /* 0x00 */ U8 ReasonCode; /* 0x08 */ U8 Port; /* 0x09 */ U16 SwitchDevHandle; /* 0x0A */ U8 Error; /* 0x0C */ U8 Action; /* 0x0D */ U16 ThresholdCount; /* 0x0E */ U16 AttachedDevHandle; /* 0x10 */ U16 Reserved12; /* 0x12 */ U32 Reserved14; /* 0x14 */ } MPI3_EVENT_DATA_PCIE_ERROR_THRESHOLD, MPI3_POINTER PTR_MPI3_EVENT_DATA_PCIE_ERROR_THRESHOLD, Mpi3EventDataPcieErrorThreshold_t, MPI3_POINTER pMpi3EventDataPcieErrorThreshold_t; /**** Defines for the ReasonCode field ****/ #define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0x00) #define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0x01) /**** Defines for the Error field - use MPI3_PCIEIOUNIT3_ERROR_ values ****/ /**** Defines for the Action field - use MPI3_PCIEIOUNIT3_ACTION_ values ****/ /**************************************************************************** * Enclosure Device Added Event * ****************************************************************************/ /* * The Enclosure Device Added Event Data is exactly the same as Enclosure * Page 0 data (including the Configuration Page header). So, please * use/refer to MPI3_ENCLOSURE_PAGE0 structure for Enclosure Device Added * Event data. */ /**************************************************************************** * Enclosure Device Changed Event * ****************************************************************************/ /* * The Enclosure Device Change Event Data is exactly the same as Enclosure * Page 0 data (including the Configuration Page header). So, please * use/refer to MPI3_ENCLOSURE_PAGE0 structure for Enclosure Device Change * Event data. */ /***************************************************************************** * SAS Initiator Device Status Change Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE { U8 ReasonCode; /* 0x00 */ U8 IOUnitPort; /* 0x01 */ U16 DevHandle; /* 0x02 */ U32 Reserved04; /* 0x04 */ U64 SASAddress; /* 0x08 */ } MPI3_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, MPI3_POINTER PTR_MPI3_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, Mpi3EventDataSasInitDevStatusChange_t, MPI3_POINTER pMpi3EventDataSasInitDevStatusChange_t; /**** Defines for the ReasonCode field ****/ #define MPI3_EVENT_SAS_INIT_RC_ADDED (0x01) #define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) /***************************************************************************** * SAS Initiator Device Table Overflow Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW { U16 MaxInit; /* 0x00 */ U16 CurrentInit; /* 0x02 */ U32 Reserved04; /* 0x04 */ U64 SASAddress; /* 0x08 */ } MPI3_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, MPI3_POINTER PTR_MPI3_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, Mpi3EventDataSasInitTableOverflow_t, MPI3_POINTER pMpi3EventDataSasInitTableOverflow_t; /***************************************************************************** * Hard Reset Received Event * ****************************************************************************/ typedef struct _MPI3_EVENT_DATA_HARD_RESET_RECEIVED { U8 Reserved00; /* 0x00 */ U8 IOUnitPort; /* 0x01 */ U16 Reserved02; /* 0x02 */ } MPI3_EVENT_DATA_HARD_RESET_RECEIVED, MPI3_POINTER PTR_MPI3_EVENT_DATA_HARD_RESET_RECEIVED, Mpi3EventDataHardResetReceived_t, MPI3_POINTER pMpi3EventDataHardResetReceived_t; /***************************************************************************** * Diagnostic Tool Events * *****************************************************************************/ /***************************************************************************** * Diagnostic Buffer Status Change Event * *****************************************************************************/ typedef struct _MPI3_EVENT_DATA_DIAG_BUFFER_STATUS_CHANGE { U8 Type; /* 0x00 */ U8 ReasonCode; /* 0x01 */ U16 Reserved02; /* 0x02 */ U32 Reserved04; /* 0x04 */ } MPI3_EVENT_DATA_DIAG_BUFFER_STATUS_CHANGE, MPI3_POINTER PTR_MPI3_EVENT_DATA_DIAG_BUFFER_STATUS_CHANGE, Mpi3EventDataDiagBufferStatusChange_t, MPI3_POINTER pMpi3EventDataDiagBufferStatusChange_t; /**** Defines for the Type field - use MPI3_DIAG_BUFFER_TYPE_ values ****/ /**** Defines for the ReasonCode field ****/ #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01) #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02) #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03) /***************************************************************************** * Persistent Event Logs * ****************************************************************************/ /**** Definitions for the Locale field ****/ #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) #define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) #define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040) #define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020) #define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010) #define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008) #define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004) #define MPI3_PEL_LOCALE_FLAGS_PD (0x0002) #define MPI3_PEL_LOCALE_FLAGS_VD (0x0001) /**** Definitions for the Class field ****/ #define MPI3_PEL_CLASS_DEBUG (0x00) #define MPI3_PEL_CLASS_PROGRESS (0x01) #define MPI3_PEL_CLASS_INFORMATIONAL (0x02) #define MPI3_PEL_CLASS_WARNING (0x03) #define MPI3_PEL_CLASS_CRITICAL (0x04) #define MPI3_PEL_CLASS_FATAL (0x05) #define MPI3_PEL_CLASS_FAULT (0x06) /**** Definitions for the ClearType field ****/ #define MPI3_PEL_CLEARTYPE_CLEAR (0x00) /**** Definitions for the WaitTime field ****/ #define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00) /**** Definitions for the Action field ****/ #define MPI3_PEL_ACTION_GET_SEQNUM (0x01) #define MPI3_PEL_ACTION_MARK_CLEAR (0x02) #define MPI3_PEL_ACTION_GET_LOG (0x03) #define MPI3_PEL_ACTION_GET_COUNT (0x04) #define MPI3_PEL_ACTION_WAIT (0x05) #define MPI3_PEL_ACTION_ABORT (0x06) #define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0x07) #define MPI3_PEL_ACTION_ACKNOWLEDGE (0x08) /**** Definitions for the LogStatus field ****/ #define MPI3_PEL_STATUS_SUCCESS (0x00) #define MPI3_PEL_STATUS_NOT_FOUND (0x01) #define MPI3_PEL_STATUS_ABORTED (0x02) #define MPI3_PEL_STATUS_NOT_READY (0x03) /**************************************************************************** * PEL Sequence Numbers * ****************************************************************************/ typedef struct _MPI3_PEL_SEQ { U32 Newest; /* 0x00 */ U32 Oldest; /* 0x04 */ U32 Clear; /* 0x08 */ U32 Shutdown; /* 0x0C */ U32 Boot; /* 0x10 */ U32 LastAcknowledged; /* 0x14 */ } MPI3_PEL_SEQ, MPI3_POINTER PTR_MPI3_PEL_SEQ, Mpi3PELSeq_t, MPI3_POINTER pMpi3PELSeq_t; /**************************************************************************** * PEL Entry * ****************************************************************************/ typedef struct _MPI3_PEL_ENTRY { U64 TimeStamp; /* 0x00 */ U32 SequenceNumber; /* 0x08 */ U16 LogCode; /* 0x0C */ U16 ArgType; /* 0x0E */ U16 Locale; /* 0x10 */ U8 Class; /* 0x12 */ U8 Flags; /* 0x13 */ U8 ExtNum; /* 0x14 */ U8 NumExts; /* 0x15 */ U8 ArgDataSize; /* 0x16 */ U8 FixedFormatStringsSize; /* 0x17 */ U32 Reserved18[2]; /* 0x18 */ U32 PELInfo[24]; /* 0x20 - 0x7F */ } MPI3_PEL_ENTRY, MPI3_POINTER PTR_MPI3_PEL_ENTRY, Mpi3PELEntry_t, MPI3_POINTER pMpi3PELEntry_t; /**** Definitions for the Flags field ****/ #define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0x02) #define MPI3_PEL_FLAGS_ACK_NEEDED (0x01) /**************************************************************************** * PEL Event List * ****************************************************************************/ typedef struct _MPI3_PEL_LIST { U32 LogCount; /* 0x00 */ U32 Reserved04; /* 0x04 */ MPI3_PEL_ENTRY Entry[1]; /* 0x08 */ /* variable length */ } MPI3_PEL_LIST, MPI3_POINTER PTR_MPI3_PEL_LIST, Mpi3PELList_t, MPI3_POINTER pMpi3PELList_t; /**************************************************************************** * PEL Count Data * ****************************************************************************/ typedef U32 MPI3_PEL_LOG_COUNT, MPI3_POINTER PTR_MPI3_PEL_LOG_COUNT, Mpi3PELLogCount_t, MPI3_POINTER pMpi3PELLogCount_t; /**************************************************************************** * PEL Arg Map * ****************************************************************************/ typedef struct _MPI3_PEL_ARG_MAP { U8 ArgType; /* 0x00 */ U8 Length; /* 0x01 */ U16 StartLocation; /* 0x02 */ } MPI3_PEL_ARG_MAP, MPI3_POINTER PTR_MPI3_PEL_ARG_MAP, Mpi3PELArgMap_t, MPI3_POINTER pMpi3PELArgMap_t; /**** Definitions for the ArgType field ****/ #define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0x00) #define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0x01) #define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0x02) #define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0x03) /**************************************************************************** * PEL Print String * ****************************************************************************/ typedef struct _MPI3_PEL_PRINT_STRING { U16 LogCode; /* 0x00 */ U16 StringLength; /* 0x02 */ U8 NumArgMap; /* 0x04 */ U8 Reserved05[3]; /* 0x05 */ MPI3_PEL_ARG_MAP ArgMap[1]; /* 0x08 */ /* variable length */ /* FormatString - offset must be calculated */ /* variable length */ } MPI3_PEL_PRINT_STRING, MPI3_POINTER PTR_MPI3_PEL_PRINT_STRING, Mpi3PELPrintString_t, MPI3_POINTER pMpi3PELPrintString_t; /**************************************************************************** * PEL Print String List * ****************************************************************************/ typedef struct _MPI3_PEL_PRINT_STRING_LIST { U32 NumPrintStrings; /* 0x00 */ U32 ResidualBytesRemain; /* 0x04 */ U32 Reserved08[2]; /* 0x08 */ MPI3_PEL_PRINT_STRING PrintString[1]; /* 0x10 */ /* variable length */ } MPI3_PEL_PRINT_STRING_LIST, MPI3_POINTER PTR_MPI3_PEL_PRINT_STRING_LIST, Mpi3PELPrintStringList_t, MPI3_POINTER pMpi3PELPrintStringList_t; /**************************************************************************** * PEL Request Msg - generic to allow header decoding * ****************************************************************************/ #ifndef MPI3_PEL_ACTION_SPECIFIC_MAX #define MPI3_PEL_ACTION_SPECIFIC_MAX (1) #endif /* MPI3_PEL_ACTION_SPECIFIC_MAX */ typedef struct _MPI3_PEL_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Action; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 ActionSpecific[MPI3_PEL_ACTION_SPECIFIC_MAX]; /* 0x0C */ /* variable length */ } MPI3_PEL_REQUEST, MPI3_POINTER PTR_MPI3_PEL_REQUEST, Mpi3PELRequest_t, MPI3_POINTER pMpi3PELRequest_t; /**************************************************************************** * PEL ACTION Get Sequence Nembers * ****************************************************************************/ typedef struct _MPI3_PEL_REQ_ACTION_GET_SEQUENCE_NUMBERS { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Action; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 Reserved0C[5]; /* 0x0C */ MPI3_SGE_UNION SGL; /* 0x20 */ } MPI3_PEL_REQ_ACTION_GET_SEQUENCE_NUMBERS, MPI3_POINTER PTR_MPI3_PEL_REQ_ACTION_GET_SEQUENCE_NUMBERS, Mpi3PELReqActionGetSequenceNumbers_t, MPI3_POINTER pMpi3PELReqActionGetSequenceNumbers_t; /**************************************************************************** * PEL ACTION Clear Log * ****************************************************************************/ typedef struct _MPI3_PEL_REQ_ACTION_CLEAR_LOG_MARKER { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Action; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U8 ClearType; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ } MPI3_PEL_REQ_ACTION_CLEAR_LOG_MARKER, MPI3_POINTER PTR_MPI3_PEL_REQ_ACTION_CLEAR_LOG_MARKER, Mpi3PELReqActionClearLogMMarker_t, MPI3_POINTER pMpi3PELReqActionClearLogMMarker_t; /**************************************************************************** * PEL ACTION Get Log * ****************************************************************************/ typedef struct _MPI3_PEL_REQ_ACTION_GET_LOG { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Action; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 StartingSequenceNumber; /* 0x0C */ U16 Locale; /* 0x10 */ U8 Class; /* 0x12 */ U8 Reserved13; /* 0x13 */ U32 Reserved14[3]; /* 0x14 */ MPI3_SGE_UNION SGL; /* 0x20 */ } MPI3_PEL_REQ_ACTION_GET_LOG, MPI3_POINTER PTR_MPI3_PEL_REQ_ACTION_GET_LOG, Mpi3PELReqActionGetLog_t, MPI3_POINTER pMpi3PELReqActionGetLog_t; /**************************************************************************** * PEL ACTION Get Count * ****************************************************************************/ typedef struct _MPI3_PEL_REQ_ACTION_GET_COUNT { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Action; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 StartingSequenceNumber; /* 0x0C */ U16 Locale; /* 0x10 */ U8 Class; /* 0x12 */ U8 Reserved13; /* 0x13 */ U32 Reserved14[3]; /* 0x14 */ MPI3_SGE_UNION SGL; /* 0x20 */ } MPI3_PEL_REQ_ACTION_GET_COUNT, MPI3_POINTER PTR_MPI3_PEL_REQ_ACTION_GET_COUNT, Mpi3PELReqActionGetCount_t, MPI3_POINTER pMpi3PELReqActionGetCount_t; /**************************************************************************** * PEL ACTION Wait * ****************************************************************************/ typedef struct _MPI3_PEL_REQ_ACTION_WAIT { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Action; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 StartingSequenceNumber; /* 0x0C */ U16 Locale; /* 0x10 */ U8 Class; /* 0x12 */ U8 Reserved13; /* 0x13 */ U16 WaitTime; /* 0x14 */ U16 Reserved16; /* 0x16 */ U32 Reserved18[2]; /* 0x18 */ } MPI3_PEL_REQ_ACTION_WAIT, MPI3_POINTER PTR_MPI3_PEL_REQ_ACTION_WAIT, Mpi3PELReqActionWait_t, MPI3_POINTER pMpi3PELReqActionWait_t; /**************************************************************************** * PEL ACTION Abort * ****************************************************************************/ typedef struct _MPI3_PEL_REQ_ACTION_ABORT { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Action; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 Reserved0C; /* 0x0C */ U16 AbortHostTag; /* 0x10 */ U16 Reserved12; /* 0x12 */ U32 Reserved14; /* 0x14 */ } MPI3_PEL_REQ_ACTION_ABORT, MPI3_POINTER PTR_MPI3_PEL_REQ_ACTION_ABORT, Mpi3PELReqActionAbort_t, MPI3_POINTER pMpi3PELReqActionAbort_t; /**************************************************************************** * PEL ACTION Get Print Strings * ****************************************************************************/ typedef struct _MPI3_PEL_REQ_ACTION_GET_PRINT_STRINGS { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Action; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 Reserved0C; /* 0x0C */ U16 StartLogCode; /* 0x10 */ U16 Reserved12; /* 0x12 */ U32 Reserved14[3]; /* 0x14 */ MPI3_SGE_UNION SGL; /* 0x20 */ } MPI3_PEL_REQ_ACTION_GET_PRINT_STRINGS, MPI3_POINTER PTR_MPI3_PEL_REQ_ACTION_GET_PRINT_STRINGS, Mpi3PELReqActionGetPrintStrings_t, MPI3_POINTER pMpi3PELReqActionGetPrintStrings_t; /**************************************************************************** * PEL ACTION Acknowledge * ****************************************************************************/ typedef struct _MPI3_PEL_REQ_ACTION_ACKNOWLEDGE { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Action; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 SequenceNumber; /* 0x0C */ U32 Reserved10; /* 0x10 */ } MPI3_PEL_REQ_ACTION_ACKNOWLEDGE, MPI3_POINTER PTR_MPI3_PEL_REQ_ACTION_ACKNOWLEDGE, Mpi3PELReqActionAcknowledge_t, MPI3_POINTER pMpi3PELReqActionAcknowledge_t; /**** Definitions for the MsgFlags field ****/ #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03) +#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_SHIFT (0) #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00) #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01) #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02) /**************************************************************************** * PEL Reply * ****************************************************************************/ typedef struct _MPI3_PEL_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U8 Action; /* 0x10 */ U8 Reserved11; /* 0x11 */ U16 Reserved12; /* 0x12 */ U16 PELogStatus; /* 0x14 */ U16 Reserved16; /* 0x16 */ U32 TransferLength; /* 0x18 */ } MPI3_PEL_REPLY, MPI3_POINTER PTR_MPI3_PEL_REPLY, Mpi3PELReply_t, MPI3_POINTER pMpi3PELReply_t; /***************************************************************************** * Component Image Download * ****************************************************************************/ typedef struct _MPI3_CI_DOWNLOAD_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Action; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 Signature1; /* 0x0C */ U32 TotalImageSize; /* 0x10 */ U32 ImageOffset; /* 0x14 */ U32 SegmentSize; /* 0x18 */ U32 Reserved1C; /* 0x1C */ MPI3_SGE_UNION SGL; /* 0x20 */ } MPI3_CI_DOWNLOAD_REQUEST, MPI3_POINTER PTR_MPI3_CI_DOWNLOAD_REQUEST, Mpi3CIDownloadRequest_t, MPI3_POINTER pMpi3CIDownloadRequest_t; /**** Definitions for the MsgFlags field ****/ #define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0x80) #define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40) #define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20) #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03) +#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SHIFT (0) #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00) #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01) #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02) /**** Definitions for the Action field ****/ #define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0x01) #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02) #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03) #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04) #define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0x05) typedef struct _MPI3_CI_DOWNLOAD_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U8 Flags; /* 0x10 */ U8 CacheDirty; /* 0x11 */ U8 PendingCount; /* 0x12 */ U8 Reserved13; /* 0x13 */ } MPI3_CI_DOWNLOAD_REPLY, MPI3_POINTER PTR_MPI3_CI_DOWNLOAD_REPLY, Mpi3CIDownloadReply_t, MPI3_POINTER pMpi3CIDownloadReply_t; /**** Definitions for the Flags field ****/ #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_FAILURE (0x40) #define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20) #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0E) +#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_SHIFT (1) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0x06) #define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0x01) /***************************************************************************** * Component Image Upload * ****************************************************************************/ typedef struct _MPI3_CI_UPLOAD_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U32 Signature1; /* 0x0C */ U32 Reserved10; /* 0x10 */ U32 ImageOffset; /* 0x14 */ U32 SegmentSize; /* 0x18 */ U32 Reserved1C; /* 0x1C */ MPI3_SGE_UNION SGL; /* 0x20 */ } MPI3_CI_UPLOAD_REQUEST, MPI3_POINTER PTR_MPI3_CI_UPLOAD_REQUEST, Mpi3CIUploadRequest_t, MPI3_POINTER pMpi3CIUploadRequest_t; /**** Defines for the MsgFlags field ****/ #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01) +#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SHIFT (0) #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00) #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01) #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02) +#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_SHIFT (1) #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00) #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02) /**** Defines for Signature1 field - use MPI3_IMAGE_HEADER_SIGNATURE1_ defines */ /***************************************************************************** * IO Unit Control * ****************************************************************************/ /**** Definitions for the Operation field ****/ #define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01) #define MPI3_CTRL_OP_LOOKUP_MAPPING (0x02) #define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0x04) #define MPI3_CTRL_OP_GET_TIMESTAMP (0x05) #define MPI3_CTRL_OP_GET_IOC_CHANGE_COUNT (0x06) #define MPI3_CTRL_OP_CHANGE_PROFILE (0x07) #define MPI3_CTRL_OP_REMOVE_DEVICE (0x10) #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11) #define MPI3_CTRL_OP_HIDDEN_ACK (0x12) #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0x13) #define MPI3_CTRL_OP_SEND_SAS_PRIMITIVE (0x20) #define MPI3_CTRL_OP_SAS_PHY_CONTROL (0x21) #define MPI3_CTRL_OP_READ_INTERNAL_BUS (0x23) #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0x24) #define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0x30) /**** Depending on the Operation selected, the various ParamX fields *****/ /**** contain defined data values. These indexes help identify those values *****/ #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00) #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00) #define MPI3_CTRL_OP_CHANGE_PROFILE_PARAM8_PROFILE_ID_INDEX (0x00) #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00) #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00) #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00) #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0x00) #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PHY_INDEX (0x00) #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PRIMSEQ_INDEX (0x01) #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM32_PRIMITIVE_INDEX (0x00) #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0x00) #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0x01) #define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0x00) #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0x00) #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0x01) /**** Definitions for the LookupMethod field in LOOKUP_MAPPING reqs ****/ #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) #define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0x04) /**** Definitions for IoUnitControl Lookup Mapping Method Parameters ****/ #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0) #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0) #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0) #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0) #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0) #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0) #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0) #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1) /*** Definitions for IoUnitControl Reply fields ****/ #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0) #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0) #define MPI3_CTRL_GET_IOC_CHANGE_COUNT_VALUE16_CHANGECOUNT_INDEX (0) #define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0) /**** Definitions for the PrimSeq field in SEND_SAS_PRIMITIVE reqs ****/ #define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01) #define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03) #define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06) /**** Definitions for the Action field in PCIE_LINK_CONTROL and SAS_PHY_CONTROL reqs ****/ #define MPI3_CTRL_ACTION_NOP (0x00) #define MPI3_CTRL_ACTION_LINK_RESET (0x01) #define MPI3_CTRL_ACTION_HARD_RESET (0x02) #define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0x05) typedef struct _MPI3_IOUNIT_CONTROL_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Reserved0A; /* 0x0A */ U8 Operation; /* 0x0B */ U32 Reserved0C; /* 0x0C */ U64 Param64[2]; /* 0x10 */ U32 Param32[4]; /* 0x20 */ U16 Param16[4]; /* 0x30 */ U8 Param8[8]; /* 0x38 */ } MPI3_IOUNIT_CONTROL_REQUEST, MPI3_POINTER PTR_MPI3_IOUNIT_CONTROL_REQUEST, Mpi3IoUnitControlRequest_t, MPI3_POINTER pMpi3IoUnitControlRequest_t; typedef struct _MPI3_IOUNIT_CONTROL_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U64 Value64[2]; /* 0x10 */ U32 Value32[4]; /* 0x20 */ U16 Value16[4]; /* 0x30 */ U8 Value8[8]; /* 0x38 */ } MPI3_IOUNIT_CONTROL_REPLY, MPI3_POINTER PTR_MPI3_IOUNIT_CONTROL_REPLY, Mpi3IoUnitControlReply_t, MPI3_POINTER pMpi3IoUnitControlReply_t; #endif /* MPI30_IOC_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_pci.h b/sys/dev/mpi3mr/mpi/mpi30_pci.h index 008ec7059b76..12d7000882cb 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_pci.h +++ b/sys/dev/mpi3mr/mpi/mpi30_pci.h @@ -1,96 +1,99 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ + #ifndef MPI30_PCI_H #define MPI30_PCI_H 1 /***************************************************************************** * NVMe Encapsulated Request Message * ****************************************************************************/ #ifndef MPI3_NVME_ENCAP_CMD_MAX #define MPI3_NVME_ENCAP_CMD_MAX (1) #endif /* MPI3_NVME_ENCAP_CMD_MAX */ typedef struct _MPI3_NVME_ENCAPSULATED_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 DevHandle; /* 0x0A */ U16 EncapsulatedCommandLength; /* 0x0C */ U16 Flags; /* 0x0E */ U32 DataLength; /* 0x10 */ U32 Reserved14[3]; /* 0x14 */ U32 Command[MPI3_NVME_ENCAP_CMD_MAX]; /* 0x20 */ /* variable length */ } MPI3_NVME_ENCAPSULATED_REQUEST, MPI3_POINTER PTR_MPI3_NVME_ENCAPSULATED_REQUEST, Mpi3NVMeEncapsulatedRequest_t, MPI3_POINTER pMpi3NVMeEncapsulatedRequest_t; /**** Defines for the Flags field ****/ #define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_MASK (0x0002) +#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_SHIFT (1) #define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_FAIL_ONLY (0x0000) #define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_ALL (0x0002) #define MPI3_NVME_FLAGS_SUBMISSIONQ_MASK (0x0001) +#define MPI3_NVME_FLAGS_SUBMISSIONQ_SHIFT (0) #define MPI3_NVME_FLAGS_SUBMISSIONQ_IO (0x0000) #define MPI3_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0001) /***************************************************************************** * NVMe Encapsulated Error Reply Message * ****************************************************************************/ typedef struct _MPI3_NVME_ENCAPSULATED_ERROR_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U32 NVMeCompletionEntry[4]; /* 0x10 */ } MPI3_NVME_ENCAPSULATED_ERROR_REPLY, MPI3_POINTER PTR_MPI3_NVME_ENCAPSULATED_ERROR_REPLY, Mpi3NVMeEncapsulatedErrorReply_t, MPI3_POINTER pMpi3NVMeEncapsulatedErrorReply_t; #endif /* MPI30_PCI_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_raid.h b/sys/dev/mpi3mr/mpi/mpi30_raid.h index 85941544e8fe..6fe557f843f3 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_raid.h +++ b/sys/dev/mpi3mr/mpi/mpi30_raid.h @@ -1,45 +1,46 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ + #ifndef MPI30_RAID_H #define MPI30_RAID_H 1 #endif /* MPI30_RAID_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_sas.h b/sys/dev/mpi3mr/mpi/mpi30_sas.h index fc55fba4747f..e50bcde0ade4 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_sas.h +++ b/sys/dev/mpi3mr/mpi/mpi30_sas.h @@ -1,98 +1,100 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ + #ifndef MPI30_SAS_H #define MPI30_SAS_H 1 /***************************************************************************** * SAS Device Info Definitions * ****************************************************************************/ #define MPI3_SAS_DEVICE_INFO_SSP_TARGET (0x00000100) #define MPI3_SAS_DEVICE_INFO_STP_SATA_TARGET (0x00000080) #define MPI3_SAS_DEVICE_INFO_SMP_TARGET (0x00000040) #define MPI3_SAS_DEVICE_INFO_SSP_INITIATOR (0x00000020) #define MPI3_SAS_DEVICE_INFO_STP_INITIATOR (0x00000010) #define MPI3_SAS_DEVICE_INFO_SMP_INITIATOR (0x00000008) #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK (0x00000007) +#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_SHIFT (0) #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_NO_DEVICE (0x00000000) #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE (0x00000001) #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_EXPANDER (0x00000002) /***************************************************************************** * SMP Passthrough Request Message * ****************************************************************************/ typedef struct _MPI3_SMP_PASSTHROUGH_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Reserved0A; /* 0x0A */ U8 IOUnitPort; /* 0x0B */ U32 Reserved0C[3]; /* 0x0C */ U64 SASAddress; /* 0x18 */ MPI3_SGE_SIMPLE RequestSGE; /* 0x20 */ MPI3_SGE_SIMPLE ResponseSGE; /* 0x30 */ } MPI3_SMP_PASSTHROUGH_REQUEST, MPI3_POINTER PTR_MPI3_SMP_PASSTHROUGH_REQUEST, Mpi3SmpPassthroughRequest_t, MPI3_POINTER pMpi3SmpPassthroughRequest_t; /***************************************************************************** * SMP Passthrough Reply Message * ****************************************************************************/ typedef struct _MPI3_SMP_PASSTHROUGH_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U16 ResponseDataLength; /* 0x10 */ U16 Reserved12; /* 0x12 */ } MPI3_SMP_PASSTHROUGH_REPLY, MPI3_POINTER PTR_MPI3_SMP_PASSTHROUGH_REPLY, Mpi3SmpPassthroughReply_t, MPI3_POINTER pMpi3SmpPassthroughReply_t; #endif /* MPI30_SAS_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_targ.h b/sys/dev/mpi3mr/mpi/mpi30_targ.h index 646b5287d502..8ae654410165 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_targ.h +++ b/sys/dev/mpi3mr/mpi/mpi30_targ.h @@ -1,318 +1,325 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ + #ifndef MPI30_TARG_H #define MPI30_TARG_H 1 /***************************************************************************** * Command Buffer Formats * ****************************************************************************/ typedef struct _MPI3_TARGET_SSP_CMD_BUFFER { U8 FrameType; /* 0x00 */ U8 Reserved01; /* 0x01 */ U16 InitiatorConnectionTag; /* 0x02 */ U32 HashedSourceSASAddress; /* 0x04 */ U16 Reserved08; /* 0x08 */ U16 Flags; /* 0x0A */ U32 Reserved0C; /* 0x0C */ U16 Tag; /* 0x10 */ U16 TargetPortTransferTag; /* 0x12 */ U32 DataOffset; /* 0x14 */ U8 LogicalUnitNumber[8]; /* 0x18 */ U8 Reserved20; /* 0x20 */ U8 TaskAttribute; /* 0x21 */ U8 Reserved22; /* 0x22 */ U8 AdditionalCDBLength; /* 0x23 */ U8 CDB[16]; /* 0x24 */ /* AdditionalCDBBytes field starts here */ /* 0x34 */ } MPI3_TARGET_SSP_CMD_BUFFER, MPI3_POINTER PTR_MPI3_TARGET_SSP_CMD_BUFFER, Mpi3TargetSspCmdBuffer_t, MPI3_POINTER pMpi3TargetSspCmdBuffer_t; typedef struct _MPI3_TARGET_SSP_TASK_BUFFER { U8 FrameType; /* 0x00 */ U8 Reserved01; /* 0x01 */ U16 InitiatorConnectionTag; /* 0x02 */ U32 HashedSourceSASAddress; /* 0x04 */ U16 Reserved08; /* 0x08 */ U16 Flags; /* 0x0A */ U32 Reserved0C; /* 0x0C */ U16 Tag; /* 0x10 */ U16 TargetPortTransferTag; /* 0x12 */ U32 DataOffset; /* 0x14 */ U8 LogicalUnitNumber[8]; /* 0x18 */ U16 Reserved20; /* 0x20 */ U8 TaskManagementFunction; /* 0x22 */ U8 Reserved23; /* 0x23 */ U16 ManagedTaskTag; /* 0x24 */ U16 Reserved26; /* 0x26 */ U32 Reserved28[3]; /* 0x28 */ } MPI3_TARGET_SSP_TASK_BUFFER, MPI3_POINTER PTR_MPI3_TARGET_SSP_TASK_BUFFER, Mpi3TargetSspTaskBuffer_t, MPI3_POINTER pMpi3TargetSspTaskBuffer_t; /**** Defines for the FrameType field ****/ #define MPI3_TARGET_FRAME_TYPE_COMMAND (0x06) #define MPI3_TARGET_FRAME_TYPE_TASK (0x16) /**** Defines for the HashedSourceSASAddress field ****/ #define MPI3_TARGET_HASHED_SAS_ADDRESS_MASK (0xFFFFFF00) #define MPI3_TARGET_HASHED_SAS_ADDRESS_SHIFT (8) /***************************************************************************** * Target Command Buffer Post Base Request Message * ****************************************************************************/ typedef struct _MPI3_TARGET_CMD_BUF_POST_BASE_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 BufferPostFlags; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U16 MinReplyQueueID; /* 0x0C */ U16 MaxReplyQueueID; /* 0x0E */ U64 BaseAddress; /* 0x10 */ U16 CmdBufferLength; /* 0x18 */ U16 TotalCmdBuffers; /* 0x1A */ U32 Reserved1C; /* 0x1C */ } MPI3_TARGET_CMD_BUF_POST_BASE_REQUEST, MPI3_POINTER PTR_MPI3_TARGET_CMD_BUF_POST_BASE_REQUEST, Mpi3TargetCmdBufPostBaseRequest_t, MPI3_POINTER pMpi3TargetCmdBufPostBaseRequest_t; /**** Defines for the BufferPostFlags field ****/ #define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_MASK (0x0C) +#define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_SHIFT (2) #define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_SYSTEM (0x00) #define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_IOCUDP (0x04) #define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_IOCCTL (0x08) #define MPI3_CMD_BUF_POST_BASE_FLAGS_AUTO_POST_ALL (0x01) /**** Defines for the CmdBufferLength field ****/ #define MPI3_CMD_BUF_POST_BASE_MIN_BUF_LENGTH (0x34) #define MPI3_CMD_BUF_POST_BASE_MAX_BUF_LENGTH (0x3FC) /***************************************************************************** * Target Command Buffer Post List Request Message * ****************************************************************************/ typedef struct _MPI3_TARGET_CMD_BUF_POST_LIST_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U8 CmdBufferCount; /* 0x0C */ U8 Reserved0D[3]; /* 0x0D */ U16 IoIndex[2]; /* 0x10 */ } MPI3_TARGET_CMD_BUF_POST_LIST_REQUEST, MPI3_POINTER PTR_MPI3_TARGET_CMD_BUF_POST_LIST_REQUEST, Mpi3TargetCmdBufPostListRequest_t, MPI3_POINTER pMpi3TargetCmdBufPostListRequest_t; /***************************************************************************** * Target Command Buffer Post Base List Reply Message * ****************************************************************************/ typedef struct _MPI3_TARGET_CMD_BUF_POST_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U8 CmdBufferCount; /* 0x10 */ U8 Reserved11[3]; /* 0x11 */ U16 IoIndex[2]; /* 0x14 */ } MPI3_TARGET_CMD_BUF_POST_REPLY, MPI3_POINTER PTR_MPI3_TARGET_CMD_BUF_POST_REPLY, Mpi3TargetCmdBufPostReply_t, MPI3_POINTER pMpi3TargetCmdBufPostReply_t; /***************************************************************************** * Target Assist Request Message * ****************************************************************************/ typedef struct _MPI3_TARGET_ASSIST_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 DevHandle; /* 0x0A */ U32 Flags; /* 0x0C */ U16 Reserved10; /* 0x10 */ U16 QueueTag; /* 0x12 */ U16 IoIndex; /* 0x14 */ U16 InitiatorConnectionTag; /* 0x16 */ U32 IOCUseOnly18; /* 0x18 */ U32 DataLength; /* 0x1C */ U32 PortTransferLength; /* 0x20 */ U32 PrimaryReferenceTag; /* 0x24 */ U16 PrimaryApplicationTag; /* 0x28 */ U16 PrimaryApplicationTagMask; /* 0x2A */ U32 RelativeOffset; /* 0x2C */ MPI3_SGE_UNION SGL[5]; /* 0x30 */ } MPI3_TARGET_ASSIST_REQUEST, MPI3_POINTER PTR_MPI3_TARGET_ASSIST_REQUEST, Mpi3TargetAssistRequest_t, MPI3_POINTER pMpi3TargetAssistRequest_t; /**** Defines for the MsgFlags field ****/ #define MPI3_TARGET_ASSIST_MSGFLAGS_METASGL_VALID (0x80) /**** Defines for the Flags field ****/ #define MPI3_TARGET_ASSIST_FLAGS_IOC_USE_ONLY_23_MASK (0x00800000) +#define MPI3_TARGET_ASSIST_FLAGS_IOC_USE_ONLY_23_SHIFT (23) #define MPI3_TARGET_ASSIST_FLAGS_IOC_USE_ONLY_22_MASK (0x00400000) +#define MPI3_TARGET_ASSIST_FLAGS_IOC_USE_ONLY_22_SHIFT (22) #define MPI3_TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x00200000) #define MPI3_TARGET_ASSIST_FLAGS_AUTO_STATUS (0x00100000) #define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_MASK (0x000C0000) +#define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_SHIFT (18) #define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_WRITE (0x00040000) #define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_READ (0x00080000) #define MPI3_TARGET_ASSIST_FLAGS_DMAOPERATION_MASK (0x00030000) +#define MPI3_TARGET_ASSIST_FLAGS_DMAOPERATION_SHIFT (16) #define MPI3_TARGET_ASSIST_FLAGS_DMAOPERATION_HOST_PI (0x00010000) /**** Defines for the SGL field ****/ #define MPI3_TARGET_ASSIST_METASGL_INDEX (4) /***************************************************************************** * Target Status Send Request Message * ****************************************************************************/ typedef struct _MPI3_TARGET_STATUS_SEND_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 DevHandle; /* 0x0A */ U16 ResponseIULength; /* 0x0C */ U16 Flags; /* 0x0E */ U16 Reserved10; /* 0x10 */ U16 QueueTag; /* 0x12 */ U16 IoIndex; /* 0x14 */ U16 InitiatorConnectionTag; /* 0x16 */ U32 IOCUseOnly18[6]; /* 0x18 */ U32 IOCUseOnly30[4]; /* 0x30 */ MPI3_SGE_UNION SGL; /* 0x40 */ } MPI3_TARGET_STATUS_SEND_REQUEST, MPI3_POINTER PTR_MPI3_TARGET_STATUS_SEND_REQUEST, Mpi3TargetStatusSendRequest_t, MPI3_POINTER pMpi3TargetStatusSendRequest_t; /**** Defines for the Flags field ****/ #define MPI3_TSS_FLAGS_IOC_USE_ONLY_6_MASK (0x0040) +#define MPI3_TSS_FLAGS_IOC_USE_ONLY_6_SHIFT (6) #define MPI3_TSS_FLAGS_REPOST_CMD_BUFFER (0x0020) #define MPI3_TSS_FLAGS_AUTO_SEND_GOOD_STATUS (0x0010) /***************************************************************************** * Standard Target Mode Reply Message * ****************************************************************************/ typedef struct _MPI3_TARGET_STANDARD_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U32 TransferCount; /* 0x10 */ } MPI3_TARGET_STANDARD_REPLY, MPI3_POINTER PTR_MPI3_TARGET_STANDARD_REPLY, Mpi3TargetStandardReply_t, MPI3_POINTER pMpi3TargetStandardReply_t; /***************************************************************************** * Target Mode Abort Request Message * ****************************************************************************/ typedef struct _MPI3_TARGET_MODE_ABORT_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 AbortType; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U16 RequestQueueIDToAbort; /* 0x0C */ U16 HostTagToAbort; /* 0x0E */ U16 DevHandle; /* 0x10 */ U8 IOCUseOnly12; /* 0x12 */ U8 Reserved13; /* 0x13 */ } MPI3_TARGET_MODE_ABORT_REQUEST, MPI3_POINTER PTR_MPI3_TARGET_MODE_ABORT_REQUEST, Mpi3TargetModeAbortRequest_t, MPI3_POINTER pMpi3TargetModeAbortRequest_t; /**** Defines for the AbortType field ****/ #define MPI3_TARGET_MODE_ABORT_ALL_CMD_BUFFERS (0x00) #define MPI3_TARGET_MODE_ABORT_EXACT_IO_REQUEST (0x01) #define MPI3_TARGET_MODE_ABORT_ALL_COMMANDS (0x02) - +#define MPI3_TARGET_MODE_ABORT_ALL_COMMANDS_DEVHANDLE (0x03) /***************************************************************************** * Target Mode Abort Reply Message * ****************************************************************************/ typedef struct _MPI3_TARGET_MODE_ABORT_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U32 AbortCount; /* 0x10 */ } MPI3_TARGET_MODE_ABORT_REPLY, MPI3_POINTER PTR_MPI3_TARGET_MODE_ABORT_REPLY, Mpi3TargetModeAbortReply_t, MPI3_POINTER pMpi3TargetModeAbortReply_t; #endif /* MPI30_TARG_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_tool.h b/sys/dev/mpi3mr/mpi/mpi30_tool.h index e11ddf068555..7f43d5d45465 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_tool.h +++ b/sys/dev/mpi3mr/mpi/mpi30_tool.h @@ -1,476 +1,481 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ + #ifndef MPI30_TOOL_H #define MPI30_TOOL_H 1 /***************************************************************************** * Toolbox Messages * *****************************************************************************/ /***************************************************************************** * Clean Tool Request Message * *****************************************************************************/ typedef struct _MPI3_TOOL_CLEAN_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Tool; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 Area; /* 0x0C */ } MPI3_TOOL_CLEAN_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_CLEAN_REQUEST, Mpi3ToolCleanRequest_t, MPI3_POINTER pMpi3ToolCleanRequest_t; /**** Defines for the Tool field ****/ #define MPI3_TOOLBOX_TOOL_CLEAN (0x01) #define MPI3_TOOLBOX_TOOL_ISTWI_READ_WRITE (0x02) #define MPI3_TOOLBOX_TOOL_DIAGNOSTIC_CLI (0x03) #define MPI3_TOOLBOX_TOOL_LANE_MARGINING (0x04) #define MPI3_TOOLBOX_TOOL_RECOVER_DEVICE (0x05) #define MPI3_TOOLBOX_TOOL_LOOPBACK (0x06) /**** Bitfield definitions for Area field ****/ #define MPI3_TOOLBOX_CLEAN_AREA_BIOS_BOOT_SERVICES (0x00000008) #define MPI3_TOOLBOX_CLEAN_AREA_ALL_BUT_MFG (0x00000002) #define MPI3_TOOLBOX_CLEAN_AREA_NVSTORE (0x00000001) /***************************************************************************** * ISTWI Read Write Tool Request Message * *****************************************************************************/ typedef struct _MPI3_TOOL_ISTWI_READ_WRITE_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Tool; /* 0x0A */ U8 Flags; /* 0x0B */ U8 DevIndex; /* 0x0C */ U8 Action; /* 0x0D */ U16 Reserved0E; /* 0x0E */ U16 TxDataLength; /* 0x10 */ U16 RxDataLength; /* 0x12 */ U32 Reserved14[3]; /* 0x14 */ MPI3_MAN11_ISTWI_DEVICE_FORMAT IstwiDevice; /* 0x20 */ MPI3_SGE_UNION SGL; /* 0x30 */ } MPI3_TOOL_ISTWI_READ_WRITE_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_ISTWI_READ_WRITE_REQUEST, Mpi3ToolIstwiReadWriteRequest_t, MPI3_POINTER pMpi3ToolIstwiReadWRiteRequest_t; /**** Bitfield definitions for Flags field ****/ #define MPI3_TOOLBOX_ISTWI_FLAGS_AUTO_RESERVE_RELEASE (0x80) #define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_MASK (0x04) +#define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_SHIFT (2) #define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_DEVINDEX (0x00) #define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_DEVICE_FIELD (0x04) #define MPI3_TOOLBOX_ISTWI_FLAGS_PAGE_ADDRESS_MASK (0x03) +#define MPI3_TOOLBOX_ISTWI_FLAGS_PAGE_ADDRESS_SHIFT (0) /**** Definitions for the Action field ****/ #define MPI3_TOOLBOX_ISTWI_ACTION_RESERVE_BUS (0x00) #define MPI3_TOOLBOX_ISTWI_ACTION_RELEASE_BUS (0x01) #define MPI3_TOOLBOX_ISTWI_ACTION_RESET (0x02) #define MPI3_TOOLBOX_ISTWI_ACTION_READ_DATA (0x03) #define MPI3_TOOLBOX_ISTWI_ACTION_WRITE_DATA (0x04) #define MPI3_TOOLBOX_ISTWI_ACTION_SEQUENCE (0x05) /**** Defines for the IstwiDevice field - refer to struct definition in mpi30_cnfg.h ****/ /***************************************************************************** * ISTWI Read Write Tool Reply Message * *****************************************************************************/ typedef struct _MPI3_TOOL_ISTWI_READ_WRITE_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U16 IstwiStatus; /* 0x10 */ U16 Reserved12; /* 0x12 */ U16 TxDataCount; /* 0x14 */ U16 RxDataCount; /* 0x16 */ } MPI3_TOOL_ISTWI_READ_WRITE_REPLY, MPI3_POINTER PTR_MPI3_TOOL_ISTWI_READ_WRITE_REPLY, Mpi3ToolIstwiReadWriteReply_t, MPI3_POINTER pMpi3ToolIstwiReadWRiteReply_t; /***************************************************************************** * Diagnostic CLI Tool Request Message * *****************************************************************************/ typedef struct _MPI3_TOOL_DIAGNOSTIC_CLI_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Tool; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 CommandDataLength; /* 0x0C */ U32 ResponseDataLength; /* 0x10 */ U32 Reserved14[3]; /* 0x14 */ MPI3_SGE_UNION SGL; /* 0x20 */ } MPI3_TOOL_DIAGNOSTIC_CLI_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_DIAGNOSTIC_CLI_REQUEST, Mpi3ToolDiagnosticCliRequest_t, MPI3_POINTER pMpi3ToolDiagnosticCliRequest_t; /***************************************************************************** * Diagnostic CLI Tool Reply Message * *****************************************************************************/ typedef struct _MPI3_TOOL_DIAGNOSTIC_CLI_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U32 ReturnedDataLength; /* 0x10 */ } MPI3_TOOL_DIAGNOSTIC_CLI_REPLY, MPI3_POINTER PTR_MPI3_TOOL_DIAGNOSTIC_CLI_REPLY, Mpi3ToolDiagnosticCliReply_t, MPI3_POINTER pMpi3ToolDiagnosticCliReply_t; /***************************************************************************** * Lane Margining Tool Request Message * *****************************************************************************/ typedef struct _MPI3_TOOL_LANE_MARGIN_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Tool; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U8 Action; /* 0x0C */ U8 SwitchPort; /* 0x0D */ U16 DevHandle; /* 0x0E */ U8 StartLane; /* 0x10 */ U8 NumLanes; /* 0x11 */ U16 Reserved12; /* 0x12 */ U32 Reserved14[3]; /* 0x14 */ MPI3_SGE_UNION SGL; /* 0x20 */ } MPI3_TOOL_LANE_MARGIN_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_LANE_MARGIN_REQUEST, Mpi3ToolIstwiLaneMarginRequest_t, MPI3_POINTER pMpi3ToolLaneMarginRequest_t; /**** Definitions for the Action field ****/ #define MPI3_TOOLBOX_LM_ACTION_ENTER (0x00) #define MPI3_TOOLBOX_LM_ACTION_EXIT (0x01) #define MPI3_TOOLBOX_LM_ACTION_READ (0x02) #define MPI3_TOOLBOX_LM_ACTION_WRITE (0x03) typedef struct _MPI3_LANE_MARGIN_ELEMENT { U16 Control; /* 0x00 */ U16 Status; /* 0x02 */ } MPI3_LANE_MARGIN_ELEMENT, MPI3_POINTER PTR_MPI3_LANE_MARGIN_ELEMENT, Mpi3LaneMarginElement_t, MPI3_POINTER pMpi3LaneMarginElement_t; /***************************************************************************** * Lane Margining Tool Reply Message * *****************************************************************************/ typedef struct _MPI3_TOOL_LANE_MARGIN_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U32 ReturnedDataLength; /* 0x10 */ } MPI3_TOOL_LANE_MARGIN_REPLY, MPI3_POINTER PTR_MPI3_TOOL_LANE_MARGIN_REPLY, Mpi3ToolLaneMarginReply_t, MPI3_POINTER pMpi3ToolLaneMarginReply_t; /***************************************************************************** * Recover Device Request Message * *****************************************************************************/ typedef struct _MPI3_TOOL_RECOVER_DEVICE_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Tool; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U8 Action; /* 0x0C */ U8 Reserved0D; /* 0x0D */ U16 DevHandle; /* 0x0E */ } MPI3_TOOL_RECOVER_DEVICE_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_RECOVER_DEVICE_REQUEST, Mpi3ToolRecoverDeviceRequest_t, MPI3_POINTER pMpi3ToolRecoverDeviceRequest_t; /**** Bitfield definitions for the Action field ****/ #define MPI3_TOOLBOX_RD_ACTION_START (0x01) #define MPI3_TOOLBOX_RD_ACTION_GET_STATUS (0x02) #define MPI3_TOOLBOX_RD_ACTION_ABORT (0x03) /***************************************************************************** * Recover Device Reply Message * *****************************************************************************/ typedef struct _MPI3_TOOL_RECOVER_DEVICE_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U8 Status; /* 0x10 */ U8 Reserved11; /* 0x11 */ U16 Reserved1C; /* 0x12 */ } MPI3_TOOL_RECOVER_DEVICE_REPLY, MPI3_POINTER PTR_MPI3_TOOL_RECOVER_DEVICE_REPLY, Mpi3ToolRecoverDeviceReply_t, MPI3_POINTER pMpi3ToolRecoverDeviceReply_t; /**** Bitfield definitions for the Status field ****/ #define MPI3_TOOLBOX_RD_STATUS_NOT_NEEDED (0x01) #define MPI3_TOOLBOX_RD_STATUS_NEEDED (0x02) #define MPI3_TOOLBOX_RD_STATUS_IN_PROGRESS (0x03) #define MPI3_TOOLBOX_RD_STATUS_ABORTING (0x04) /***************************************************************************** * Loopback Tool Request Message * *****************************************************************************/ typedef struct _MPI3_TOOL_LOOPBACK_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U8 Tool; /* 0x0A */ U8 Reserved0B; /* 0x0B */ U32 Reserved0C; /* 0x0C */ U64 Phys; /* 0x10 */ } MPI3_TOOL_LOOPBACK_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_LOOPBACK_REQUEST, Mpi3ToolLoopbackRequest_t, MPI3_POINTER pMpi3ToolLoopbackRequest_t; /***************************************************************************** * Loopback Tool Reply Message * *****************************************************************************/ typedef struct _MPI3_TOOL_LOOPBACK_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U64 TestedPhys; /* 0x10 */ U64 FailedPhys; /* 0x18 */ } MPI3_TOOL_LOOPBACK_REPLY, MPI3_POINTER PTR_MPI3_TOOL_LOOPBACK_REPLY, Mpi3ToolLoopbackReply_t, MPI3_POINTER pMpi3ToolLoopbackReply_t; /***************************************************************************** * Diagnostic Buffer Messages * *****************************************************************************/ /***************************************************************************** * Diagnostic Buffer Post Request Message * *****************************************************************************/ typedef struct _MPI3_DIAG_BUFFER_POST_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U8 Type; /* 0x0C */ U8 Reserved0D; /* 0x0D */ U16 Reserved0E; /* 0x0E */ U64 Address; /* 0x10 */ U32 Length; /* 0x18 */ U32 Reserved1C; /* 0x1C */ } MPI3_DIAG_BUFFER_POST_REQUEST, MPI3_POINTER PTR_MPI3_DIAG_BUFFER_POST_REQUEST, Mpi3DiagBufferPostRequest_t, MPI3_POINTER pMpi3DiagBufferPostRequest_t; /**** Defines for the MsgFlags field ****/ #define MPI3_DIAG_BUFFER_POST_MSGFLAGS_SEGMENTED (0x01) /**** Defines for the Type field ****/ #define MPI3_DIAG_BUFFER_TYPE_TRACE (0x01) #define MPI3_DIAG_BUFFER_TYPE_FW (0x02) #define MPI3_DIAG_BUFFER_TYPE_DRIVER (0x10) #define MPI3_DIAG_BUFFER_TYPE_FDL (0x20) #define MPI3_DIAG_BUFFER_TYPE_TTY (0x30) #define MPI3_DIAG_BUFFER_MIN_PRODUCT_SPECIFIC (0xF0) #define MPI3_DIAG_BUFFER_MAX_PRODUCT_SPECIFIC (0xFF) /***************************************************************************** * DRIVER DIAGNOSTIC Buffer * *****************************************************************************/ typedef struct _MPI3_DRIVER_BUFFER_HEADER { U32 Signature; /* 0x00 */ U16 HeaderSize; /* 0x04 */ U16 RTTFileHeaderOffset; /* 0x06 */ U32 Flags; /* 0x08 */ U32 CircularBufferSize; /* 0x0C */ U32 LogicalBufferEnd; /* 0x10 */ U32 LogicalBufferStart; /* 0x14 */ U32 IOCUseOnly18[2]; /* 0x18 */ U32 Reserved20[760]; /* 0x20 - 0xBFC */ U32 ReservedRTTRACE[256]; /* 0xC00 - 0xFFC */ } MPI3_DRIVER_BUFFER_HEADER, MPI3_POINTER PTR_MPI3_DRIVER_BUFFER_HEADER, Mpi3DriverBufferHeader_t, MPI3_POINTER pMpi3DriverBufferHeader_t; /**** Defines for the Signature field ****/ #define MPI3_DRIVER_DIAG_BUFFER_HEADER_SIGNATURE_CIRCULAR (0x43495243) /**** Defines for the Flags field ****/ #define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_MASK (0x00000003) +#define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_SHIFT (0) #define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_ASCII (0x00000000) #define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_RTTRACE (0x00000001) /***************************************************************************** * Diagnostic Buffer Manage Request Message * *****************************************************************************/ typedef struct _MPI3_DIAG_BUFFER_MANAGE_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U8 Type; /* 0x0C */ U8 Action; /* 0x0D */ U16 Reserved0E; /* 0x0E */ } MPI3_DIAG_BUFFER_MANAGE_REQUEST, MPI3_POINTER PTR_MPI3_DIAG_BUFFER_MANAGE_REQUEST, Mpi3DiagBufferManageRequest_t, MPI3_POINTER pMpi3DiagBufferManageRequest_t; /**** Defines for the Type field - use MPI3_DIAG_BUFFER_TYPE_ values ****/ /**** Defined for the Action field ****/ #define MPI3_DIAG_BUFFER_ACTION_RELEASE (0x01) #define MPI3_DIAG_BUFFER_ACTION_PAUSE (0x02) #define MPI3_DIAG_BUFFER_ACTION_RESUME (0x03) /***************************************************************************** * Diagnostic Buffer Upload Request Message * *****************************************************************************/ typedef struct _MPI3_DIAG_BUFFER_UPLOAD_REQUEST { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 Reserved0A; /* 0x0A */ U8 Type; /* 0x0C */ U8 Flags; /* 0x0D */ U16 Reserved0E; /* 0x0E */ U64 Context; /* 0x10 */ U32 Reserved18; /* 0x18 */ U32 Reserved1C; /* 0x1C */ MPI3_SGE_UNION SGL; /* 0x20 */ } MPI3_DIAG_BUFFER_UPLOAD_REQUEST, MPI3_POINTER PTR_MPI3_DIAG_BUFFER_UPLOAD_REQUEST, Mpi3DiagBufferUploadRequest_t, MPI3_POINTER pMpi3DiagBufferUploadRequest_t; /**** Defines for the Type field - use MPI3_DIAG_BUFFER_TYPE_ values ****/ /**** Defined for the Flags field ****/ #define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_MASK (0x01) +#define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_SHIFT (0) #define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_DECODED (0x00) #define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_ENCODED (0x01) /***************************************************************************** * Diagnostic Buffer Upload Reply Message * *****************************************************************************/ typedef struct _MPI3_DIAG_BUFFER_UPLOAD_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ U64 Context; /* 0x10 */ U32 ReturnedDataLength; /* 0x18 */ U32 Reserved1C; /* 0x1C */ } MPI3_DIAG_BUFFER_UPLOAD_REPLY, MPI3_POINTER PTR_MPI3_DIAG_BUFFER_UPLOAD_REPLY, Mpi3DiagBufferUploadReply_t, MPI3_POINTER pMpi3DiagBufferUploadReply_t; #endif /* MPI30_TOOL_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_transport.h b/sys/dev/mpi3mr/mpi/mpi30_transport.h index 860c27a2dd42..d9ebbfa0b5d8 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_transport.h +++ b/sys/dev/mpi3mr/mpi/mpi30_transport.h @@ -1,743 +1,772 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * * + * * Version History * --------------- * * Date Version Description * -------- ----------- ------------------------------------------------------ * 11-30-18 03.00.00.08 Corresponds to Fusion-MPT MPI 3.0 Specification Rev H. * 02-08-19 03.00.00.09 Corresponds to Fusion-MPT MPI 3.0 Specification Rev I. * 05-03-19 03.00.00.10 Corresponds to Fusion-MPT MPI 3.0 Specification Rev J. * 08-30-19 03.00.00.12 Corresponds to Fusion-MPT MPI 3.0 Specification Rev L. * 11-01-19 03.00.00.13 Corresponds to Fusion-MPT MPI 3.0 Specification Rev M. * 12-16-19 03.00.00.14 Corresponds to Fusion-MPT MPI 3.0 Specification Rev N. * 02-28-20 03.00.00.15 Corresponds to Fusion-MPT MPI 3.0 Specification Rev O. * 05-01-20 03.00.00.16 Corresponds to Fusion-MPT MPI 3.0 Specification Rev P. * 06-26-20 03.00.00.17 Corresponds to Fusion-MPT MPI 3.0 Specification Rev Q. * 08-28-20 03.00.00.18 Corresponds to Fusion-MPT MPI 3.0 Specification Rev R. * 10-30-20 03.00.00.19 Corresponds to Fusion-MPT MPI 3.0 Specification Rev S. * 12-18-20 03.00.00.20 Corresponds to Fusion-MPT MPI 3.0 Specification Rev T. * 02-09-21 03.00.20.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev T - Interim Release 1. * 02-26-21 03.00.21.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U. * 04-16-21 03.00.21.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U - Interim Release 1. * 04-28-21 03.00.21.02 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U - Interim Release 2. * 05-28-21 03.00.22.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev V. * 07-23-21 03.00.22.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev V - Interim Release 1. * 09-03-21 03.00.23.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 23. * 10-23-21 03.00.23.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 23 - Interim Release 1. * 12-03-21 03.00.24.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 24. * 02-25-22 03.00.25.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 25. * 06-03-22 03.00.26.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 26. * 08-09-22 03.00.26.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 26 - Interim Release 1. * 09-02-22 03.00.27.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27. * 10-20-22 03.00.27.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27 - Interim Release 1. * 12-02-22 03.00.28.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 28. * 02-24-23 03.00.29.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 29. * 05-19-23 03.00.30.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 30. * 08-18-23 03.00.30.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 30 - Interim Release 1. * 11-17-23 03.00.31.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 31 * 02-16-24 03.00.32.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 32 + * 02-23-24 03.00.32.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 32 - Interim Release 1. + * 04-19-24 03.00.32.02 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 32 - Interim Release 2. + * 05-10-24 03.00.33.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 33 + * 06-14-24 03.00.33.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 33 - Interim Release 1. + * 07-26-24 03.00.34.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 34 + * 11-08-24 03.00.35.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 35 + * 02-14-25 03.00.36.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 36 */ + #ifndef MPI30_TRANSPORT_H #define MPI30_TRANSPORT_H 1 /***************************************************************************** * Common version structure/union used in * * messages and configuration pages * ****************************************************************************/ typedef struct _MPI3_VERSION_STRUCT { U8 Dev; /* 0x00 */ U8 Unit; /* 0x01 */ U8 Minor; /* 0x02 */ U8 Major; /* 0x03 */ } MPI3_VERSION_STRUCT, MPI3_POINTER PTR_MPI3_VERSION_STRUCT, Mpi3VersionStruct_t, MPI3_POINTER pMpi3VersionStruct_t; typedef union _MPI3_VERSION_UNION { MPI3_VERSION_STRUCT Struct; U32 Word; } MPI3_VERSION_UNION, MPI3_POINTER PTR_MPI3_VERSION_UNION, Mpi3VersionUnion_t, MPI3_POINTER pMpi3VersionUnion_t; /****** Version constants for this revision ****/ #define MPI3_VERSION_MAJOR (3) #define MPI3_VERSION_MINOR (0) -#define MPI3_VERSION_UNIT (32) +#define MPI3_VERSION_UNIT (36) #define MPI3_VERSION_DEV (0) /****** DevHandle definitions *****/ #define MPI3_DEVHANDLE_INVALID (0xFFFF) /***************************************************************************** * System Interface Register Definitions * ****************************************************************************/ typedef struct _MPI3_SYSIF_OPER_QUEUE_INDEXES { U16 ProducerIndex; /* 0x00 */ U16 Reserved02; /* 0x02 */ U16 ConsumerIndex; /* 0x04 */ U16 Reserved06; /* 0x06 */ } MPI3_SYSIF_OPER_QUEUE_INDEXES, MPI3_POINTER PTR_MPI3_SYSIF_OPER_QUEUE_INDEXES; typedef volatile struct _MPI3_SYSIF_REGISTERS { U64 IOCInformation; /* 0x00 */ MPI3_VERSION_UNION Version; /* 0x08 */ U32 Reserved0C[2]; /* 0x0C */ U32 IOCConfiguration; /* 0x14 */ U32 Reserved18; /* 0x18 */ U32 IOCStatus; /* 0x1C */ U32 Reserved20; /* 0x20 */ U32 AdminQueueNumEntries; /* 0x24 */ U64 AdminRequestQueueAddress; /* 0x28 */ U64 AdminReplyQueueAddress; /* 0x30 */ U32 Reserved38[2]; /* 0x38 */ U32 CoalesceControl; /* 0x40 */ U32 Reserved44[1007]; /* 0x44 */ U16 AdminRequestQueuePI; /* 0x1000 */ U16 Reserved1002; /* 0x1002 */ U16 AdminReplyQueueCI; /* 0x1004 */ U16 Reserved1006; /* 0x1006 */ MPI3_SYSIF_OPER_QUEUE_INDEXES OperQueueIndexes[383]; /* 0x1008 */ U32 Reserved1C00; /* 0x1C00 */ U32 WriteSequence; /* 0x1C04 */ U32 HostDiagnostic; /* 0x1C08 */ U32 Reserved1C0C; /* 0x1C0C */ U32 Fault; /* 0x1C10 */ U32 FaultInfo[3]; /* 0x1C14 */ U32 Reserved1C20[4]; /* 0x1C20 */ U64 HCBAddress; /* 0x1C30 */ U32 HCBSize; /* 0x1C38 */ U32 Reserved1C3C; /* 0x1C3C */ U32 ReplyFreeHostIndex; /* 0x1C40 */ U32 SenseBufferFreeHostIndex; /* 0x1C44 */ U32 Reserved1C48[2]; /* 0x1C48 */ U64 DiagRWData; /* 0x1C50 */ U64 DiagRWAddress; /* 0x1C58 */ U16 DiagRWControl; /* 0x1C60 */ U16 DiagRWStatus; /* 0x1C62 */ U32 Reserved1C64[35]; /* 0x1C64 */ U32 Scratchpad[4]; /* 0x1CF0 */ U32 Reserved1D00[192]; /* 0x1D00 */ U32 DeviceAssignedRegisters[2048]; /* 0x2000 */ } MPI3_SYSIF_REGS, MPI3_POINTER PTR_MPI3_SYSIF_REGS, Mpi3SysIfRegs_t, MPI3_POINTER pMpi3SysIfRegs_t; /**** Defines for the IOCInformation register ****/ #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000) #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004) #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xFF000000) #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24) #define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001) /**** Defines for the IOCConfiguration register ****/ #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014) #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00F00000) #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20) #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000F0000) #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT (16) #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000C000) +#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_SHIFT (14) #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000) #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000) #define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ (0x00002000) #define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010) #define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001) /**** Defines for the IOCStatus register ****/ #define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001C) #define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010) #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000C) #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_SHIFT (0x00000002) #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000) #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004) #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008) #define MPI3_SYSIF_IOC_STATUS_FAULT (0x00000002) #define MPI3_SYSIF_IOC_STATUS_READY (0x00000001) /**** Defines for the AdminQueueNumEntries register ****/ #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET (0x00000024) #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK (0x0FFF) +#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_SHIFT (0) #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET (0x00000026) #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK (0x0FFF0000) #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT (16) /**** Defines for the AdminRequestQueueAddress register ****/ #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET (0x00000028) #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_HIGH_OFFSET (0x0000002C) /**** Defines for the AdminReplyQueueAddress register ****/ #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET (0x00000030) #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_HIGH_OFFSET (0x00000034) /**** Defines for the CoalesceControl register ****/ #define MPI3_SYSIF_COALESCE_CONTROL_OFFSET (0x00000040) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK (0xC0000000) +#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_SHIFT (30) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xC0000000) #define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x20000000) #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_MASK (0x01FF0000) #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_SHIFT (16) #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000FF00) #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8) #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000FF) #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_SHIFT (0) /**** Defines for the AdminRequestQueuePI register ****/ #define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000) /**** Defines for the AdminReplyQueueCI register ****/ #define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004) /**** Defines for the OperationalRequestQueuePI register */ #define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008) #define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(N) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((N)-1)*8)) /* N = 1, 2, 3, ..., 255 */ /**** Defines for the OperationalReplyQueueCI register */ #define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100C) #define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(N) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((N)-1)*8)) /* N = 1, 2, 3, ..., 255 */ /**** Defines for the WriteSequence register *****/ #define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001C04) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000F) +#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_SHIFT (0) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST (0xF) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND (0x4) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD (0xB) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH (0x2) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH (0x7) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH (0xD) /**** Defines for the HostDiagnostic register *****/ #define MPI3_SYSIF_HOST_DIAG_OFFSET (0x00001C08) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700) +#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SHIFT (8) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET (0x00000200) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700) #define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080) #define MPI3_SYSIF_HOST_DIAG_SECURE_BOOT (0x00000040) #define MPI3_SYSIF_HOST_DIAG_CLEAR_INVALID_FW_IMAGE (0x00000020) #define MPI3_SYSIF_HOST_DIAG_INVALID_FW_IMAGE (0x00000010) #define MPI3_SYSIF_HOST_DIAG_HCBENABLE (0x00000008) #define MPI3_SYSIF_HOST_DIAG_HCBMODE (0x00000004) #define MPI3_SYSIF_HOST_DIAG_DIAG_RW_ENABLE (0x00000002) #define MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE (0x00000001) /**** Defines for the Fault register ****/ #define MPI3_SYSIF_FAULT_OFFSET (0x00001C10) #define MPI3_SYSIF_FAULT_CODE_MASK (0x0000FFFF) +#define MPI3_SYSIF_FAULT_CODE_SHIFT (0) #define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET (0x0000F000) #define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000F001) #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000F002) #define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000F003) #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED (0x0000F004) #define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED (0x0000F005) #define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED (0x0000F006) +#define MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER (0x0000F007) /**** Defines for FaultCodeAdditionalInfo registers ****/ #define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001C14) #define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001C18) #define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001C1C) /**** Defines for HCBAddress register ****/ #define MPI3_SYSIF_HCB_ADDRESS_LOW_OFFSET (0x00001C30) #define MPI3_SYSIF_HCB_ADDRESS_HIGH_OFFSET (0x00001C34) /**** Defines for HCBSize register ****/ #define MPI3_SYSIF_HCB_SIZE_OFFSET (0x00001C38) #define MPI3_SYSIF_HCB_SIZE_SIZE_MASK (0xFFFFF000) #define MPI3_SYSIF_HCB_SIZE_SIZE_SHIFT (12) #define MPI3_SYSIF_HCB_SIZE_HCDW_ENABLE (0x00000001) /**** Defines for ReplyFreeHostIndex register ****/ #define MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET (0x00001C40) /**** Defines for SenseBufferFreeHostIndex register ****/ #define MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET (0x00001C44) /**** Defines for DiagRWData register ****/ #define MPI3_SYSIF_DIAG_RW_DATA_LOW_OFFSET (0x00001C50) #define MPI3_SYSIF_DIAG_RW_DATA_HIGH_OFFSET (0x00001C54) /**** Defines for DiagRWAddress ****/ #define MPI3_SYSIF_DIAG_RW_ADDRESS_LOW_OFFSET (0x00001C58) #define MPI3_SYSIF_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00001C5C) /**** Defines for DiagRWControl register ****/ #define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET (0x00001C60) #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK (0x00000030) +#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_SHIFT (4) #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE (0x00000000) #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES (0x00000010) #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES (0x00000020) #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES (0x00000030) #define MPI3_SYSIF_DIAG_RW_CONTROL_RESET (0x00000004) #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK (0x00000002) +#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_SHIFT (1) #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ (0x00000000) #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE (0x00000002) #define MPI3_SYSIF_DIAG_RW_CONTROL_START (0x00000001) /**** Defines for DiagRWStatus register ****/ #define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET (0x00001C62) #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK (0x0000000E) +#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SHIFT (1) #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS (0x00000000) #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR (0x00000002) #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR (0x00000004) #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_PAR_ERR (0x00000006) #define MPI3_SYSIF_DIAG_RW_STATUS_BUSY (0x00000001) /**** Defines for Scratchpad registers ****/ #define MPI3_SYSIF_SCRATCHPAD0_OFFSET (0x00001CF0) #define MPI3_SYSIF_SCRATCHPAD1_OFFSET (0x00001CF4) #define MPI3_SYSIF_SCRATCHPAD2_OFFSET (0x00001CF8) #define MPI3_SYSIF_SCRATCHPAD3_OFFSET (0x00001CFC) /**** Defines for Device Assigned registers ****/ #define MPI3_SYSIF_DEVICE_ASSIGNED_REGS_OFFSET (0x00002000) /**** Default Defines for Diag Save Timeout ****/ #define MPI3_SYSIF_DIAG_SAVE_TIMEOUT (60) /* seconds */ /***************************************************************************** * Reply Descriptors * ****************************************************************************/ /***************************************************************************** * Default Reply Descriptor * ****************************************************************************/ typedef struct _MPI3_DEFAULT_REPLY_DESCRIPTOR { U32 DescriptorTypeDependent1[2]; /* 0x00 */ U16 RequestQueueCI; /* 0x08 */ U16 RequestQueueID; /* 0x0A */ U16 DescriptorTypeDependent2; /* 0x0C */ U16 ReplyFlags; /* 0x0E */ } MPI3_DEFAULT_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_DEFAULT_REPLY_DESCRIPTOR, Mpi3DefaultReplyDescriptor_t, MPI3_POINTER pMpi3DefaultReplyDescriptor_t; /**** Defines for the ReplyFlags field ****/ #define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK (0x0001) +#define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_SHIFT (0) #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK (0xF000) +#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SHIFT (12) #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY (0x0000) #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000) #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000) #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS (0x3000) /**** Defines for the RequestQueueID field ****/ #define MPI3_REPLY_DESCRIPT_REQUEST_QUEUE_ID_INVALID (0xFFFF) /***************************************************************************** * Address Reply Descriptor * ****************************************************************************/ typedef struct _MPI3_ADDRESS_REPLY_DESCRIPTOR { U64 ReplyFrameAddress; /* 0x00 */ U16 RequestQueueCI; /* 0x08 */ U16 RequestQueueID; /* 0x0A */ U16 Reserved0C; /* 0x0C */ U16 ReplyFlags; /* 0x0E */ } MPI3_ADDRESS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_ADDRESS_REPLY_DESCRIPTOR, Mpi3AddressReplyDescriptor_t, MPI3_POINTER pMpi3AddressReplyDescriptor_t; /***************************************************************************** * Success Reply Descriptor * ****************************************************************************/ typedef struct _MPI3_SUCCESS_REPLY_DESCRIPTOR { U32 Reserved00[2]; /* 0x00 */ U16 RequestQueueCI; /* 0x08 */ U16 RequestQueueID; /* 0x0A */ U16 HostTag; /* 0x0C */ U16 ReplyFlags; /* 0x0E */ } MPI3_SUCCESS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_SUCCESS_REPLY_DESCRIPTOR, Mpi3SuccessReplyDescriptor_t, MPI3_POINTER pMpi3SuccessReplyDescriptor_t; /***************************************************************************** * Target Command Buffer Reply Descriptor * ****************************************************************************/ typedef struct _MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { U32 Reserved00; /* 0x00 */ U16 InitiatorDevHandle; /* 0x04 */ U8 PhyNum; /* 0x06 */ U8 Reserved07; /* 0x07 */ U16 RequestQueueCI; /* 0x08 */ U16 RequestQueueID; /* 0x0A */ U16 IOIndex; /* 0x0C */ U16 ReplyFlags; /* 0x0E */ } MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, Mpi3TargetCommandBufferReplyDescriptor_t, MPI3_POINTER pMpi3TargetCommandBufferReplyDescriptor_t; /**** See Default Reply Descriptor Defines above for definitions in the ReplyFlags field ****/ /***************************************************************************** * Status Reply Descriptor * ****************************************************************************/ typedef struct _MPI3_STATUS_REPLY_DESCRIPTOR { U16 IOCStatus; /* 0x00 */ U16 Reserved02; /* 0x02 */ U32 IOCLogInfo; /* 0x04 */ U16 RequestQueueCI; /* 0x08 */ U16 RequestQueueID; /* 0x0A */ U16 HostTag; /* 0x0C */ U16 ReplyFlags; /* 0x0E */ } MPI3_STATUS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_STATUS_REPLY_DESCRIPTOR, Mpi3StatusReplyDescriptor_t, MPI3_POINTER pMpi3StatusReplyDescriptor_t; /**** Use MPI3_IOCSTATUS_ defines for the IOCStatus field ****/ /**** Use MPI3_IOCLOGINFO_ defines for the IOCLogInfo field ****/ /***************************************************************************** * Union of Reply Descriptors * ****************************************************************************/ typedef union _MPI3_REPLY_DESCRIPTORS_UNION { MPI3_DEFAULT_REPLY_DESCRIPTOR Default; MPI3_ADDRESS_REPLY_DESCRIPTOR AddressReply; MPI3_SUCCESS_REPLY_DESCRIPTOR Success; MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; MPI3_STATUS_REPLY_DESCRIPTOR Status; U32 Words[4]; } MPI3_REPLY_DESCRIPTORS_UNION, MPI3_POINTER PTR_MPI3_REPLY_DESCRIPTORS_UNION, Mpi3ReplyDescriptorsUnion_t, MPI3_POINTER pMpi3ReplyDescriptorsUnion_t; /***************************************************************************** * Scatter Gather Elements * ****************************************************************************/ /***************************************************************************** * Common structure for Simple, Chain, and Last Chain * * scatter gather elements * ****************************************************************************/ typedef struct _MPI3_SGE_COMMON { U64 Address; /* 0x00 */ U32 Length; /* 0x08 */ U8 Reserved0C[3]; /* 0x0C */ U8 Flags; /* 0x0F */ } MPI3_SGE_SIMPLE, MPI3_POINTER PTR_MPI3_SGE_SIMPLE, Mpi3SGESimple_t, MPI3_POINTER pMpi3SGESimple_t, MPI3_SGE_CHAIN, MPI3_POINTER PTR_MPI3_SGE_CHAIN, Mpi3SGEChain_t, MPI3_POINTER pMpi3SGEChain_t, MPI3_SGE_LAST_CHAIN, MPI3_POINTER PTR_MPI3_SGE_LAST_CHAIN, Mpi3SGELastChain_t, MPI3_POINTER pMpi3SGELastChain_t; /***************************************************************************** * Bit Bucket scatter gather element * ****************************************************************************/ typedef struct _MPI3_SGE_BIT_BUCKET { U64 Reserved00; /* 0x00 */ U32 Length; /* 0x08 */ U8 Reserved0C[3]; /* 0x0C */ U8 Flags; /* 0x0F */ } MPI3_SGE_BIT_BUCKET, MPI3_POINTER PTR_MPI3_SGE_BIT_BUCKET, Mpi3SGEBitBucket_t, MPI3_POINTER pMpi3SGEBitBucket_t; /***************************************************************************** * Extended EEDP scatter gather element * ****************************************************************************/ typedef struct _MPI3_SGE_EXTENDED_EEDP { U8 UserDataSize; /* 0x00 */ U8 Reserved01; /* 0x01 */ U16 EEDPFlags; /* 0x02 */ U32 SecondaryReferenceTag; /* 0x04 */ U16 SecondaryApplicationTag; /* 0x08 */ U16 ApplicationTagTranslationMask; /* 0x0A */ U16 Reserved0C; /* 0x0C */ U8 ExtendedOperation; /* 0x0E */ U8 Flags; /* 0x0F */ } MPI3_SGE_EXTENDED_EEDP, MPI3_POINTER PTR_MPI3_SGE_EXTENDED_EEDP, Mpi3SGEExtendedEEDP_t, MPI3_POINTER pMpi3SGEExtendedEEDP_t; /***************************************************************************** * Union of scatter gather elements * ****************************************************************************/ typedef union _MPI3_SGE_UNION { MPI3_SGE_SIMPLE Simple; MPI3_SGE_CHAIN Chain; MPI3_SGE_LAST_CHAIN LastChain; MPI3_SGE_BIT_BUCKET BitBucket; MPI3_SGE_EXTENDED_EEDP Eedp; U32 Words[4]; } MPI3_SGE_UNION, MPI3_POINTER PTR_MPI3_SGE_UNION, Mpi3SGEUnion_t, MPI3_POINTER pMpi3SGEUnion_t; /**** Definitions for the Flags field ****/ #define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK (0xF0) +#define MPI3_SGE_FLAGS_ELEMENT_TYPE_SHIFT (4) #define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE (0x00) #define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET (0x10) #define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN (0x20) #define MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN (0x30) #define MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED (0xF0) #define MPI3_SGE_FLAGS_END_OF_LIST (0x08) #define MPI3_SGE_FLAGS_END_OF_BUFFER (0x04) #define MPI3_SGE_FLAGS_DLAS_MASK (0x03) +#define MPI3_SGE_FLAGS_DLAS_SHIFT (0) #define MPI3_SGE_FLAGS_DLAS_SYSTEM (0x00) #define MPI3_SGE_FLAGS_DLAS_IOC_UDP (0x01) #define MPI3_SGE_FLAGS_DLAS_IOC_CTL (0x02) /**** Definitions for the ExtendedOperation field of Extended element ****/ #define MPI3_SGE_EXT_OPER_EEDP (0x00) /**** Definitions for the EEDPFlags field of Extended EEDP element ****/ -#define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000) -#define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000) -#define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000) -#define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000) -#define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800) -#define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400) -#define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200) -#define MPI3_EEDPFLAGS_CHK_GUARD (0x0100) -#define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00C0) -#define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040) -#define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080) +#define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000) +#define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000) +#define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000) +#define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000) +#define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800) +#define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400) +#define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200) +#define MPI3_EEDPFLAGS_CHK_GUARD (0x0100) +#define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00C0) +#define MPI3_EEDPFLAGS_ESC_MODE_SHIFT (6) +#define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040) +#define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080) #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE (0x00C0) -#define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030) -#define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000) -#define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010) -#define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020) -#define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008) -#define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007) -#define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001) -#define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002) -#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003) -#define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004) -#define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006) -#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007) +#define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030) +#define MPI3_EEDPFLAGS_HOST_GUARD_SHIFT (4) +#define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000) +#define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010) +#define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020) +#define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008) +#define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007) +#define MPI3_EEDPFLAGS_EEDP_OP_SHIFT (0) +#define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001) +#define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002) +#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003) +#define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004) +#define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006) +#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007) /**** Definitions for the UserDataSize field of Extended EEDP element ****/ #define MPI3_EEDP_UDS_512 (0x01) #define MPI3_EEDP_UDS_520 (0x02) #define MPI3_EEDP_UDS_4080 (0x03) #define MPI3_EEDP_UDS_4088 (0x04) #define MPI3_EEDP_UDS_4096 (0x05) #define MPI3_EEDP_UDS_4104 (0x06) #define MPI3_EEDP_UDS_4160 (0x07) /***************************************************************************** * Standard Message Structures * ****************************************************************************/ /***************************************************************************** * Request Message Header for all request messages * ****************************************************************************/ typedef struct _MPI3_REQUEST_HEADER { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ U16 FunctionDependent; /* 0x0A */ } MPI3_REQUEST_HEADER, MPI3_POINTER PTR_MPI3_REQUEST_HEADER, Mpi3RequestHeader_t, MPI3_POINTER pMpi3RequestHeader_t; /***************************************************************************** * Default Reply * ****************************************************************************/ typedef struct _MPI3_DEFAULT_REPLY { U16 HostTag; /* 0x00 */ U8 IOCUseOnly02; /* 0x02 */ U8 Function; /* 0x03 */ U16 IOCUseOnly04; /* 0x04 */ U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 IOCUseOnly08; /* 0x08 */ U16 IOCStatus; /* 0x0A */ U32 IOCLogInfo; /* 0x0C */ } MPI3_DEFAULT_REPLY, MPI3_POINTER PTR_MPI3_DEFAULT_REPLY, Mpi3DefaultReply_t, MPI3_POINTER pMpi3DefaultReply_t; /**** Defines for the HostTag field ****/ #define MPI3_HOST_TAG_INVALID (0xFFFF) /**** Defines for message Function ****/ /* I/O Controller functions */ #define MPI3_FUNCTION_IOC_FACTS (0x01) /* IOC Facts */ #define MPI3_FUNCTION_IOC_INIT (0x02) /* IOC Init */ #define MPI3_FUNCTION_PORT_ENABLE (0x03) /* Port Enable */ #define MPI3_FUNCTION_EVENT_NOTIFICATION (0x04) /* Event Notification */ #define MPI3_FUNCTION_EVENT_ACK (0x05) /* Event Acknowledge */ #define MPI3_FUNCTION_CI_DOWNLOAD (0x06) /* Component Image Download */ #define MPI3_FUNCTION_CI_UPLOAD (0x07) /* Component Image Upload */ #define MPI3_FUNCTION_IO_UNIT_CONTROL (0x08) /* IO Unit Control */ #define MPI3_FUNCTION_PERSISTENT_EVENT_LOG (0x09) /* Persistent Event Log */ #define MPI3_FUNCTION_MGMT_PASSTHROUGH (0x0A) /* Management Passthrough */ #define MPI3_FUNCTION_CONFIG (0x10) /* Configuration */ /* SCSI Initiator I/O functions */ #define MPI3_FUNCTION_SCSI_IO (0x20) /* SCSI IO */ #define MPI3_FUNCTION_SCSI_TASK_MGMT (0x21) /* SCSI Task Management */ #define MPI3_FUNCTION_SMP_PASSTHROUGH (0x22) /* SMP Passthrough */ #define MPI3_FUNCTION_NVME_ENCAPSULATED (0x24) /* NVMe Encapsulated */ /* SCSI Target I/O functions */ #define MPI3_FUNCTION_TARGET_ASSIST (0x30) /* Target Assist */ #define MPI3_FUNCTION_TARGET_STATUS_SEND (0x31) /* Target Status Send */ #define MPI3_FUNCTION_TARGET_MODE_ABORT (0x32) /* Target Mode Abort */ #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_BASE (0x33) /* Target Command Buffer Post Base */ #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_LIST (0x34) /* Target Command Buffer Post List */ /* Queue Management functions */ #define MPI3_FUNCTION_CREATE_REQUEST_QUEUE (0x70) /* Create an operational request queue */ #define MPI3_FUNCTION_DELETE_REQUEST_QUEUE (0x71) /* Delete an operational request queue */ #define MPI3_FUNCTION_CREATE_REPLY_QUEUE (0x72) /* Create an operational reply queue */ #define MPI3_FUNCTION_DELETE_REPLY_QUEUE (0x73) /* Delete an operational reply queue */ /* Diagnostic Tools */ #define MPI3_FUNCTION_TOOLBOX (0x80) /* Toolbox */ #define MPI3_FUNCTION_DIAG_BUFFER_POST (0x81) /* Post a Diagnostic Buffer to the I/O Unit */ #define MPI3_FUNCTION_DIAG_BUFFER_MANAGE (0x82) /* Manage a Diagnostic Buffer */ #define MPI3_FUNCTION_DIAG_BUFFER_UPLOAD (0x83) /* Upload a Diagnostic Buffer */ /* Miscellaneous functions */ #define MPI3_FUNCTION_MIN_IOC_USE_ONLY (0xC0) /* Beginning of IOC Use Only range of function codes */ #define MPI3_FUNCTION_MAX_IOC_USE_ONLY (0xEF) /* End of IOC Use Only range of function codes */ #define MPI3_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* Beginning of the product-specific range of function codes */ #define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* End of the product-specific range of function codes */ /**** Defines for IOCStatus ****/ #define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE (0x8000) #define MPI3_IOCSTATUS_STATUS_MASK (0x7FFF) +#define MPI3_IOCSTATUS_STATUS_SHIFT (0) /* Common IOCStatus values for all replies */ #define MPI3_IOCSTATUS_SUCCESS (0x0000) #define MPI3_IOCSTATUS_INVALID_FUNCTION (0x0001) #define MPI3_IOCSTATUS_BUSY (0x0002) #define MPI3_IOCSTATUS_INVALID_SGL (0x0003) #define MPI3_IOCSTATUS_INTERNAL_ERROR (0x0004) #define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) #define MPI3_IOCSTATUS_INVALID_FIELD (0x0007) #define MPI3_IOCSTATUS_INVALID_STATE (0x0008) +#define MPI3_IOCSTATUS_SHUTDOWN_ACTIVE (0x0009) #define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000A) #define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000B) #define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK (0x000C) #define MPI3_IOCSTATUS_SUPERVISOR_ONLY (0x000D) #define MPI3_IOCSTATUS_FAILURE (0x001F) /* Config IOCStatus values */ #define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) #define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) #define MPI3_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) #define MPI3_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) #define MPI3_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) #define MPI3_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) /* SCSI IO IOCStatus values */ #define MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) #define MPI3_IOCSTATUS_SCSI_TM_NOT_SUPPORTED (0x0041) #define MPI3_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) #define MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) #define MPI3_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) #define MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) #define MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) #define MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) #define MPI3_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) #define MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) #define MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) #define MPI3_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) #define MPI3_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) /* SCSI Initiator and SCSI Target end-to-end data protection values */ #define MPI3_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) #define MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) #define MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) /* SCSI Target IOCStatus values */ #define MPI3_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) #define MPI3_IOCSTATUS_TARGET_ABORTED (0x0063) #define MPI3_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) #define MPI3_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) #define MPI3_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) #define MPI3_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) #define MPI3_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) #define MPI3_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) #define MPI3_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) #define MPI3_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) /* Serial Attached SCSI IOCStatus values */ #define MPI3_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) #define MPI3_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) /* Diagnostic Buffer Post/Release IOCStatus values */ #define MPI3_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) /* Component Image Upload/Download */ #define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00B0) #define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00B1) #define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00B2) #define MPI3_IOCSTATUS_CI_KEY_UPDATE_PENDING (0x00B3) #define MPI3_IOCSTATUS_CI_KEY_UPDATE_NOT_POSSIBLE (0x00B4) /* Security values */ #define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00C0) #define MPI3_IOCSTATUS_SECURITY_VIOLATION (0x00C1) /* Request and Reply Queues related IOCStatus values */ #define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0F00) #define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0F01) #define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0F02) #define MPI3_IOCSTATUS_INVALID_REPLY_QUEUE_ID (0x0F03) #define MPI3_IOCSTATUS_INVALID_QUEUE_DELETION (0x0F04) /**** Defines for IOCLogInfo ****/ #define MPI3_IOCLOGINFO_TYPE_MASK (0xF0000000) #define MPI3_IOCLOGINFO_TYPE_SHIFT (28) #define MPI3_IOCLOGINFO_TYPE_NONE (0x0) #define MPI3_IOCLOGINFO_TYPE_SAS (0x3) #define MPI3_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) +#define MPI3_IOCLOGINFO_LOG_DATA_SHIFT (0) #endif /* MPI30_TRANSPORT_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_type.h b/sys/dev/mpi3mr/mpi/mpi30_type.h index 815becadcf25..a6ec8c395c35 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_type.h +++ b/sys/dev/mpi3mr/mpi/mpi30_type.h @@ -1,98 +1,99 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. Neither the name of the Broadcom Inc. nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * The views and conclusions contained in the software and documentation are * those of the authors and should not be interpreted as representing * official policies,either expressed or implied, of the FreeBSD Project. * * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * */ + #ifndef MPI30_TYPE_H #define MPI30_TYPE_H 1 /***************************************************************************** * Define MPI3_POINTER if it has not already been defined. By default * * MPI3_POINTER is defined to be a near pointer. MPI3_POINTER can be defined * * as a far pointer by defining MPI3_POINTER as "far *" before this header * * file is included. * ****************************************************************************/ #ifndef MPI3_POINTER #define MPI3_POINTER * #endif /* MPI3_POINTER */ /* The basic types may have already been included by mpi_type.h or mpi2_type.h */ #if !defined(MPI_TYPE_H) && !defined(MPI2_TYPE_H) /***************************************************************************** * Basic Types * ****************************************************************************/ typedef int8_t S8; typedef uint8_t U8; typedef int16_t S16; typedef uint16_t U16; typedef int32_t S32; typedef uint32_t U32; typedef int64_t S64; typedef uint64_t U64; /***************************************************************************** * Structure Types * ****************************************************************************/ typedef struct _S64struct { U32 Low; S32 High; } S64struct; typedef struct _U64struct { U32 Low; U32 High; } U64struct; /***************************************************************************** * Pointer Types * ****************************************************************************/ typedef S8 *PS8; typedef U8 *PU8; typedef S16 *PS16; typedef U16 *PU16; typedef S32 *PS32; typedef U32 *PU32; typedef S64 *PS64; typedef U64 *PU64; typedef S64struct *PS64struct; typedef U64struct *PU64struct; #endif /* MPI_TYPE_H && MPI2_TYPE_H */ #endif /* MPI30_TYPE_H */