diff --git a/sys/mips/ingenic/jz4780_clock.c b/sys/mips/ingenic/jz4780_clock.c index 7a6a989d5e93..f743e193c7a9 100644 --- a/sys/mips/ingenic/jz4780_clock.c +++ b/sys/mips/ingenic/jz4780_clock.c @@ -1,830 +1,830 @@ /*- * Copyright 2015 Alexander Kabaev * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Ingenic JZ4780 CGU driver. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "clkdev_if.h" -#include +#include /********************************************************************** * JZ4780 CGU clock domain **********************************************************************/ struct jz4780_clock_softc { device_t dev; struct resource *res[1]; struct mtx mtx; struct clkdom *clkdom; }; static struct resource_spec jz4780_clock_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; struct jz4780_clk_pll_def { uint16_t clk_id; uint16_t clk_reg; const char *clk_name; const char *clk_pname[1]; }; #define PLL(_id, cname, pname, reg) { \ .clk_id = _id, \ .clk_reg = reg, \ .clk_name = cname, \ .clk_pname[0] = pname, \ } struct jz4780_clk_gate_def { uint16_t clk_id; uint16_t clk_bit; const char *clk_name; const char *clk_pname[1]; }; #define GATE(_id, cname, pname, bit) { \ .clk_id = _id, \ .clk_bit = bit, \ .clk_name = cname, \ .clk_pname[0] = pname, \ } #define MUX(reg, shift, bits, map) \ .clk_mux.mux_reg = (reg), \ .clk_mux.mux_shift = (shift), \ .clk_mux.mux_bits = (bits), \ .clk_mux.mux_map = (map), #define NO_MUX #define DIV(reg, shift, lg, bits, ce, st, bb) \ .clk_div.div_reg = (reg), \ .clk_div.div_shift = (shift), \ .clk_div.div_bits = (bits), \ .clk_div.div_lg = (lg), \ .clk_div.div_ce_bit = (ce), \ .clk_div.div_st_bit = (st), \ .clk_div.div_busy_bit = (bb), #define NO_DIV \ #define GATEBIT(bit) \ .clk_gate_bit = (bit), #define NO_GATE \ .clk_gate_bit = (-1), #define PLIST(pnames...) \ .clk_pnames = { pnames }, #define GENCLK(id, name, type, parents, mux, div, gt) { \ .clk_id = id, \ .clk_type = type, \ .clk_name = name, \ parents \ mux \ div \ gt \ } /* PLL definitions */ static struct jz4780_clk_pll_def pll_clks[] = { PLL(JZ4780_CLK_APLL, "apll", "ext", JZ_CPAPCR), PLL(JZ4780_CLK_MPLL, "mpll", "ext", JZ_CPMPCR), PLL(JZ4780_CLK_EPLL, "epll", "ext", JZ_CPEPCR), PLL(JZ4780_CLK_VPLL, "vpll", "ext", JZ_CPVPCR), }; /* OTG PHY clock (reuse gate def structure */ static struct jz4780_clk_gate_def otg_clks[] = { GATE(JZ4780_CLK_OTGPHY, "otg_phy", "ext", 0), }; static const struct jz4780_clk_descr gen_clks[] = { GENCLK(JZ4780_CLK_SCLKA, "sclk_a", CLK_MASK_MUX, PLIST("apll", "ext", "rtc"), MUX(JZ_CPCCR, 30, 2, 0x7), NO_DIV, NO_GATE ), GENCLK(JZ4780_CLK_CPUMUX, "cpumux", CLK_MASK_MUX, PLIST("sclk_a", "mpll", "epll"), MUX(JZ_CPCCR, 28, 2, 0x7), NO_DIV, NO_GATE ), GENCLK(JZ4780_CLK_CPU, "cpu", CLK_MASK_DIV, PLIST("cpumux"), NO_MUX, DIV(JZ_CPCCR, 0, 0, 4, 22, -1, -1), NO_GATE ), GENCLK(JZ4780_CLK_L2CACHE, "l2cache", CLK_MASK_DIV, PLIST("cpumux"), NO_MUX, DIV(JZ_CPCCR, 4, 0, 4, -1, -1, -1), NO_GATE ), GENCLK(JZ4780_CLK_AHB0, "ahb0", CLK_MASK_MUX | CLK_MASK_DIV, PLIST("sclk_a", "mpll", "epll"), MUX(JZ_CPCCR, 26, 2, 0x7), DIV(JZ_CPCCR, 8, 0, 4, 21, -1, -1), NO_GATE ), GENCLK(JZ4780_CLK_AHB2PMUX, "ahb2_apb_mux", CLK_MASK_MUX, PLIST("sclk_a", "mpll", "rtc"), MUX(JZ_CPCCR, 24, 2, 0x7), NO_DIV, NO_GATE ), GENCLK(JZ4780_CLK_AHB2, "ahb2", CLK_MASK_DIV, PLIST("ahb2_apb_mux"), NO_MUX, DIV(JZ_CPCCR, 12, 0, 4, 20, -1, -1), NO_GATE ), GENCLK(JZ4780_CLK_PCLK, "pclk", CLK_MASK_DIV, PLIST("ahb2_apb_mux"), NO_MUX, DIV(JZ_CPCCR, 16, 0, 4, 20, -1, -1), NO_GATE ), GENCLK(JZ4780_CLK_DDR, "ddr", CLK_MASK_MUX | CLK_MASK_DIV, PLIST("sclk_a", "mpll"), MUX(JZ_DDCDR, 30, 2, 0x6), DIV(JZ_DDCDR, 0, 0, 4, 29, 28, 27), NO_GATE ), GENCLK(JZ4780_CLK_VPU, "vpu", CLK_MASK_MUX | CLK_MASK_DIV | CLK_MASK_GATE, PLIST("sclk_a", "mpll", "epll"), MUX(JZ_VPUCDR, 30, 2, 0xe), DIV(JZ_VPUCDR, 0, 0, 4, 29, 28, 27), GATEBIT(32 + 2) ), GENCLK(JZ4780_CLK_I2SPLL, "i2s_pll", CLK_MASK_MUX | CLK_MASK_DIV, PLIST("sclk_a", "epll"), MUX(JZ_I2SCDR, 30, 1, 0xc), DIV(JZ_I2SCDR, 0, 0, 8, 29, 28, 27), NO_GATE ), GENCLK(JZ4780_CLK_I2S, "i2s", CLK_MASK_MUX, PLIST("ext", "i2s_pll"), MUX(JZ_I2SCDR, 31, 1, 0xc), NO_DIV, NO_GATE ), GENCLK(JZ4780_CLK_LCD0PIXCLK, "lcd0pixclk", CLK_MASK_MUX | CLK_MASK_DIV, PLIST("sclk_a", "mpll", "vpll"), MUX(JZ_LP0CDR, 30, 2, 0xe), DIV(JZ_LP0CDR, 0, 0, 8, 28, 27, 26), NO_GATE ), GENCLK(JZ4780_CLK_LCD1PIXCLK, "lcd1pixclk", CLK_MASK_MUX | CLK_MASK_DIV, PLIST("sclk_a", "mpll", "vpll"), MUX(JZ_LP1CDR, 30, 2, 0xe), DIV(JZ_LP1CDR, 0, 0, 8, 28, 27, 26), NO_GATE ), GENCLK(JZ4780_CLK_MSCMUX, "msc_mux", CLK_MASK_MUX, PLIST("sclk_a", "mpll"), MUX(JZ_MSC0CDR, 30, 2, 0x6), NO_DIV, NO_GATE ), GENCLK(JZ4780_CLK_MSC0, "msc0", CLK_MASK_DIV | CLK_MASK_GATE, PLIST("msc_mux"), NO_MUX, DIV(JZ_MSC0CDR, 0, 1, 8, 29, 28, 27), GATEBIT(3) ), GENCLK(JZ4780_CLK_MSC1, "msc1", CLK_MASK_DIV | CLK_MASK_GATE, PLIST("msc_mux"), NO_MUX, DIV(JZ_MSC1CDR, 0, 1, 8, 29, 28, 27), GATEBIT(11) ), GENCLK(JZ4780_CLK_MSC2, "msc2", CLK_MASK_DIV | CLK_MASK_GATE, PLIST("msc_mux"), NO_MUX, DIV(JZ_MSC2CDR, 0, 1, 8, 29, 28, 27), GATEBIT(12) ), GENCLK(JZ4780_CLK_UHC, "uhc", CLK_MASK_MUX | CLK_MASK_DIV | CLK_MASK_GATE, PLIST("sclk_a", "mpll", "epll", "otg_phy"), MUX(JZ_UHCCDR, 30, 2, 0xf), DIV(JZ_UHCCDR, 0, 0, 8, 29, 28, 27), GATEBIT(24) ), GENCLK(JZ4780_CLK_SSIPLL, "ssi_pll", CLK_MASK_MUX | CLK_MASK_DIV, PLIST("sclk_a", "mpll"), MUX(JZ_SSICDR, 30, 1, 0xc), DIV(JZ_SSICDR, 0, 0, 8, 29, 28, 27), NO_GATE ), GENCLK(JZ4780_CLK_SSI, "ssi", CLK_MASK_MUX, PLIST("ext", "ssi_pll"), MUX(JZ_SSICDR, 31, 1, 0xc), NO_DIV, NO_GATE ), GENCLK(JZ4780_CLK_CIMMCLK, "cim_mclk", CLK_MASK_MUX | CLK_MASK_DIV, PLIST("sclk_a", "mpll"), MUX(JZ_CIMCDR, 31, 1, 0xc), DIV(JZ_CIMCDR, 0, 0, 8, 30, 29, 28), NO_GATE ), GENCLK(JZ4780_CLK_PCMPLL, "pcm_pll", CLK_MASK_MUX | CLK_MASK_DIV, PLIST("sclk_a", "mpll", "epll", "vpll"), MUX(JZ_PCMCDR, 29, 2, 0xf), DIV(JZ_PCMCDR, 0, 0, 8, 28, 27, 26), NO_GATE ), GENCLK(JZ4780_CLK_PCM, "pcm", CLK_MASK_MUX | CLK_MASK_GATE, PLIST("ext", "pcm_pll"), MUX(JZ_PCMCDR, 31, 1, 0xc), NO_DIV, GATEBIT(32 + 3) ), GENCLK(JZ4780_CLK_GPU, "gpu", CLK_MASK_MUX | CLK_MASK_DIV | CLK_MASK_GATE, PLIST("sclk_a", "mpll", "epll"), MUX(JZ_GPUCDR, 30, 2, 0x7), DIV(JZ_GPUCDR, 0, 0, 4, 29, 28, 27), GATEBIT(32 + 4) ), GENCLK(JZ4780_CLK_HDMI, "hdmi", CLK_MASK_MUX | CLK_MASK_DIV | CLK_MASK_GATE, PLIST("sclk_a", "mpll", "vpll"), MUX(JZ_HDMICDR, 30, 2, 0xe), DIV(JZ_HDMICDR, 0, 0, 8, 29, 28, 26), GATEBIT(32 + 9) ), GENCLK(JZ4780_CLK_BCH, "bch", CLK_MASK_MUX | CLK_MASK_DIV | CLK_MASK_GATE, PLIST("sclk_a", "mpll", "epll"), MUX(JZ_BCHCDR, 30, 2, 0x7), DIV(JZ_BCHCDR, 0, 0, 4, 29, 28, 27), GATEBIT(1) ), }; static struct jz4780_clk_gate_def gate_clks[] = { GATE(JZ4780_CLK_NEMC, "nemc", "ahb2", 0), GATE(JZ4780_CLK_OTG0, "otg0", "ext", 2), GATE(JZ4780_CLK_SSI0, "ssi0", "ssi", 4), GATE(JZ4780_CLK_SMB0, "smb0", "pclk", 5), GATE(JZ4780_CLK_SMB1, "smb1", "pclk", 6), GATE(JZ4780_CLK_SCC, "scc", "ext", 7), GATE(JZ4780_CLK_AIC, "aic", "ext", 8), GATE(JZ4780_CLK_TSSI0, "tssi0", "ext", 9), GATE(JZ4780_CLK_OWI, "owi", "ext", 10), GATE(JZ4780_CLK_KBC, "kbc", "ext", 13), GATE(JZ4780_CLK_SADC, "sadc", "ext", 14), GATE(JZ4780_CLK_UART0, "uart0", "ext", 15), GATE(JZ4780_CLK_UART1, "uart1", "ext", 16), GATE(JZ4780_CLK_UART2, "uart2", "ext", 17), GATE(JZ4780_CLK_UART3, "uart3", "ext", 18), GATE(JZ4780_CLK_SSI1, "ssi1", "ssi", 19), GATE(JZ4780_CLK_SSI2, "ssi2", "ssi", 20), GATE(JZ4780_CLK_PDMA, "pdma", "ext", 21), GATE(JZ4780_CLK_GPS, "gps", "ext", 22), GATE(JZ4780_CLK_MAC, "mac", "ext", 23), GATE(JZ4780_CLK_SMB2, "smb2", "pclk", 25), GATE(JZ4780_CLK_CIM, "cim", "ext", 26), GATE(JZ4780_CLK_LCD, "lcd", "ext", 28), GATE(JZ4780_CLK_TVE, "tve", "lcd", 27), GATE(JZ4780_CLK_IPU, "ipu", "ext", 29), GATE(JZ4780_CLK_DDR0, "ddr0", "ddr", 30), GATE(JZ4780_CLK_DDR1, "ddr1", "ddr", 31), GATE(JZ4780_CLK_SMB3, "smb3", "pclk", 32 + 0), GATE(JZ4780_CLK_TSSI1, "tssi1", "ext", 32 + 1), GATE(JZ4780_CLK_COMPRESS, "compress", "ext", 32 + 5), GATE(JZ4780_CLK_AIC1, "aic1", "ext", 32 + 6), GATE(JZ4780_CLK_GPVLC, "gpvlc", "ext", 32 + 7), GATE(JZ4780_CLK_OTG1, "otg1", "ext", 32 + 8), GATE(JZ4780_CLK_UART4, "uart4", "ext", 32 + 10), GATE(JZ4780_CLK_AHBMON, "ahb_mon", "ext", 32 + 11), GATE(JZ4780_CLK_SMB4, "smb4", "pclk", 32 + 12), GATE(JZ4780_CLK_DES, "des", "ext", 32 + 13), GATE(JZ4780_CLK_X2D, "x2d", "ext", 32 + 14), GATE(JZ4780_CLK_CORE1, "core1", "cpu", 32 + 15), }; static int jz4780_clock_register(struct jz4780_clock_softc *sc) { int i, ret; /* Register PLLs */ for (i = 0; i < nitems(pll_clks); i++) { struct clknode_init_def clkdef; clkdef.id = pll_clks[i].clk_id; clkdef.name = __DECONST(char *, pll_clks[i].clk_name); clkdef.parent_names = pll_clks[i].clk_pname; clkdef.parent_cnt = 1; clkdef.flags = CLK_NODE_STATIC_STRINGS; ret = jz4780_clk_pll_register(sc->clkdom, &clkdef, &sc->mtx, sc->res[0], pll_clks[i].clk_reg); if (ret != 0) return (ret); } /* Register OTG clock */ for (i = 0; i < nitems(otg_clks); i++) { struct clknode_init_def clkdef; clkdef.id = otg_clks[i].clk_id; clkdef.name = __DECONST(char *, otg_clks[i].clk_name); clkdef.parent_names = otg_clks[i].clk_pname; clkdef.parent_cnt = 1; clkdef.flags = CLK_NODE_STATIC_STRINGS; ret = jz4780_clk_otg_register(sc->clkdom, &clkdef, &sc->mtx, sc->res[0]); if (ret != 0) return (ret); } /* Register muxes and divisors */ for (i = 0; i < nitems(gen_clks); i++) { ret = jz4780_clk_gen_register(sc->clkdom, &gen_clks[i], &sc->mtx, sc->res[0]); if (ret != 0) return (ret); } /* Register simple gates */ for (i = 0; i < nitems(gate_clks); i++) { struct clk_gate_def gatedef; gatedef.clkdef.id = gate_clks[i].clk_id; gatedef.clkdef.name = __DECONST(char *, gate_clks[i].clk_name); gatedef.clkdef.parent_names = gate_clks[i].clk_pname; gatedef.clkdef.parent_cnt = 1; gatedef.clkdef.flags = CLK_NODE_STATIC_STRINGS; if (gate_clks[i].clk_bit < 32) { gatedef.offset = JZ_CLKGR0; gatedef.shift = gate_clks[i].clk_bit; } else { gatedef.offset = JZ_CLKGR1; gatedef.shift = gate_clks[i].clk_bit - 32; } gatedef.mask = 1; gatedef.on_value = 0; gatedef.off_value = 1; gatedef.gate_flags = 0; ret = clknode_gate_register(sc->clkdom, &gatedef); if (ret != 0) return (ret); } return (0); } static int jz4780_clock_fixup(struct jz4780_clock_softc *sc) { struct clknode *clk_uhc; int ret; /* * Make UHC mux use MPLL as the source. It defaults to OTG_PHY * and that somehow just does not work. */ clkdom_xlock(sc->clkdom); /* Assume the worst */ ret = ENXIO; clk_uhc = clknode_find_by_id(sc->clkdom, JZ4780_CLK_UHC); if (clk_uhc != NULL) { ret = clknode_set_parent_by_name(clk_uhc, "mpll"); if (ret != 0) device_printf(sc->dev, "unable to reparent uhc clock\n"); else ret = clknode_set_freq(clk_uhc, 48000000, 0, 0); if (ret != 0) device_printf(sc->dev, "unable to init uhc clock\n"); } else device_printf(sc->dev, "unable to lookup uhc clock\n"); clkdom_unlock(sc->clkdom); return (ret); } #define CGU_LOCK(sc) mtx_lock(&(sc)->mtx) #define CGU_UNLOCK(sc) mtx_unlock(&(sc)->mtx) #define CGU_LOCK_INIT(sc) \ mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ "jz4780-cgu", MTX_DEF) #define CGU_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) static int jz4780_clock_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-cgu")) return (ENXIO); device_set_desc(dev, "Ingenic jz4780 CGU"); return (BUS_PROBE_DEFAULT); } static int jz4780_clock_attach(device_t dev) { struct jz4780_clock_softc *sc; sc = device_get_softc(dev); if (bus_alloc_resources(dev, jz4780_clock_spec, sc->res)) { device_printf(dev, "could not allocate resources for device\n"); return (ENXIO); } sc->dev = dev; CGU_LOCK_INIT(sc); sc->clkdom = clkdom_create(dev); if (sc->clkdom == NULL) goto fail; if (jz4780_clock_register(sc) != 0) goto fail; if (clkdom_finit(sc->clkdom) != 0) goto fail; if (jz4780_clock_fixup(sc) != 0) goto fail; if (bootverbose) clkdom_dump(sc->clkdom); return (0); fail: bus_release_resources(dev, jz4780_clock_spec, sc->res); CGU_LOCK_DESTROY(sc); return (ENXIO); } static int jz4780_clock_detach(device_t dev) { struct jz4780_clock_softc *sc; sc = device_get_softc(dev); bus_release_resources(dev, jz4780_clock_spec, sc->res); CGU_LOCK_DESTROY(sc); return (0); } static int jz4780_clock_write_4(device_t dev, bus_addr_t addr, uint32_t val) { struct jz4780_clock_softc *sc; sc = device_get_softc(dev); CSR_WRITE_4(sc, addr, val); return (0); } static int jz4780_clock_read_4(device_t dev, bus_addr_t addr, uint32_t *val) { struct jz4780_clock_softc *sc; sc = device_get_softc(dev); *val = CSR_READ_4(sc, addr); return (0); } static int jz4780_clock_modify_4(device_t dev, bus_addr_t addr, uint32_t clear_mask, uint32_t set_mask) { struct jz4780_clock_softc *sc; uint32_t val; sc = device_get_softc(dev); val = CSR_READ_4(sc, addr); val &= ~clear_mask; val |= set_mask; CSR_WRITE_4(sc, addr, val); return (0); } static void jz4780_clock_device_lock(device_t dev) { struct jz4780_clock_softc *sc; sc = device_get_softc(dev); CGU_LOCK(sc); } static void jz4780_clock_device_unlock(device_t dev) { struct jz4780_clock_softc *sc; sc = device_get_softc(dev); CGU_UNLOCK(sc); } static device_method_t jz4780_clock_methods[] = { /* Device interface */ DEVMETHOD(device_probe, jz4780_clock_probe), DEVMETHOD(device_attach, jz4780_clock_attach), DEVMETHOD(device_detach, jz4780_clock_detach), /* Clock device interface */ DEVMETHOD(clkdev_write_4, jz4780_clock_write_4), DEVMETHOD(clkdev_read_4, jz4780_clock_read_4), DEVMETHOD(clkdev_modify_4, jz4780_clock_modify_4), DEVMETHOD(clkdev_device_lock, jz4780_clock_device_lock), DEVMETHOD(clkdev_device_unlock, jz4780_clock_device_unlock), DEVMETHOD_END }; static driver_t jz4780_clock_driver = { "cgu", jz4780_clock_methods, sizeof(struct jz4780_clock_softc), }; static devclass_t jz4780_clock_devclass; EARLY_DRIVER_MODULE(jz4780_clock, simplebus, jz4780_clock_driver, jz4780_clock_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_LATE); static int jz4780_ehci_clk_config(struct jz4780_clock_softc *sc) { clk_t phy_clk, ext_clk; uint64_t phy_freq; int err; phy_clk = NULL; ext_clk = NULL; err = -1; /* Set phy timing by copying it from ext */ if (clk_get_by_id(sc->dev, sc->clkdom, JZ4780_CLK_OTGPHY, &phy_clk) != 0) goto done; if (clk_get_parent(phy_clk, &ext_clk) != 0) goto done; if (clk_get_freq(ext_clk, &phy_freq) != 0) goto done; if (clk_set_freq(phy_clk, phy_freq, 0) != 0) goto done; err = 0; done: clk_release(ext_clk); clk_release(phy_clk); return (err); } int jz4780_ohci_enable(void) { device_t dev; struct jz4780_clock_softc *sc; uint32_t reg; dev = devclass_get_device(jz4780_clock_devclass, 0); if (dev == NULL) return (-1); sc = device_get_softc(dev); CGU_LOCK(sc); /* Do not force port1 to suspend mode */ reg = CSR_READ_4(sc, JZ_OPCR); reg |= OPCR_SPENDN1; CSR_WRITE_4(sc, JZ_OPCR, reg); CGU_UNLOCK(sc); return (0); } int jz4780_ehci_enable(void) { device_t dev; struct jz4780_clock_softc *sc; uint32_t reg; dev = devclass_get_device(jz4780_clock_devclass, 0); if (dev == NULL) return (-1); sc = device_get_softc(dev); /* * EHCI should use MPPL as a parent, but Linux configures OTG * clock anyway. Follow their lead blindly. */ if (jz4780_ehci_clk_config(sc) != 0) return (-1); CGU_LOCK(sc); /* Enable OTG, should not be necessary since we use PLL clock */ reg = CSR_READ_4(sc, JZ_USBPCR); reg &= ~(PCR_OTG_DISABLE); CSR_WRITE_4(sc, JZ_USBPCR, reg); /* Do not force port1 to suspend mode */ reg = CSR_READ_4(sc, JZ_OPCR); reg |= OPCR_SPENDN1; CSR_WRITE_4(sc, JZ_OPCR, reg); /* D- pulldown */ reg = CSR_READ_4(sc, JZ_USBPCR1); reg |= PCR_DMPD1; CSR_WRITE_4(sc, JZ_USBPCR1, reg); /* D+ pulldown */ reg = CSR_READ_4(sc, JZ_USBPCR1); reg |= PCR_DPPD1; CSR_WRITE_4(sc, JZ_USBPCR1, reg); /* 16 bit bus witdth for port 1*/ reg = CSR_READ_4(sc, JZ_USBPCR1); reg |= PCR_WORD_I_F1 | PCR_WORD_I_F0; CSR_WRITE_4(sc, JZ_USBPCR1, reg); /* Reset USB */ reg = CSR_READ_4(sc, JZ_USBPCR); reg |= PCR_POR; CSR_WRITE_4(sc, JZ_USBPCR, reg); DELAY(1); reg = CSR_READ_4(sc, JZ_USBPCR); reg &= ~(PCR_POR); CSR_WRITE_4(sc, JZ_USBPCR, reg); /* Soft-reset USB */ reg = CSR_READ_4(sc, JZ_SRBC); reg |= SRBC_UHC_SR; CSR_WRITE_4(sc, JZ_SRBC, reg); /* 300ms */ DELAY(300*hz/1000); reg = CSR_READ_4(sc, JZ_SRBC); reg &= ~(SRBC_UHC_SR); CSR_WRITE_4(sc, JZ_SRBC, reg); /* 300ms */ DELAY(300*hz/1000); CGU_UNLOCK(sc); return (0); } #define USBRESET_DETECT_TIME 0x96 int jz4780_otg_enable(void) { device_t dev; struct jz4780_clock_softc *sc; uint32_t reg; dev = devclass_get_device(jz4780_clock_devclass, 0); if (dev == NULL) return (-1); sc = device_get_softc(dev); CGU_LOCK(sc); /* Select Synopsys OTG mode */ reg = CSR_READ_4(sc, JZ_USBPCR1); reg |= PCR_SYNOPSYS; /* Set UTMI bus width to 16 bit */ reg |= PCR_WORD_I_F0 | PCR_WORD_I_F1; CSR_WRITE_4(sc, JZ_USBPCR1, reg); /* Blah */ reg = CSR_READ_4(sc, JZ_USBVBFIL); reg = REG_SET(reg, USBVBFIL_IDDIGFIL, 0); reg = REG_SET(reg, USBVBFIL_USBVBFIL, 0); CSR_WRITE_4(sc, JZ_USBVBFIL, reg); /* Setup reset detect time */ reg = CSR_READ_4(sc, JZ_USBRDT); reg = REG_SET(reg, USBRDT_USBRDT, USBRESET_DETECT_TIME); reg |= USBRDT_VBFIL_LD_EN; CSR_WRITE_4(sc, JZ_USBRDT, reg); /* Setup USBPCR bits */ reg = CSR_READ_4(sc, JZ_USBPCR); reg |= PCR_USB_MODE; reg |= PCR_COMMONONN; reg |= PCR_VBUSVLDEXT; reg |= PCR_VBUSVLDEXTSEL; reg &= ~(PCR_OTG_DISABLE); CSR_WRITE_4(sc, JZ_USBPCR, reg); /* Reset USB */ reg = CSR_READ_4(sc, JZ_USBPCR); reg |= PCR_POR; CSR_WRITE_4(sc, JZ_USBPCR, reg); DELAY(1000); reg = CSR_READ_4(sc, JZ_USBPCR); reg &= ~(PCR_POR); CSR_WRITE_4(sc, JZ_USBPCR, reg); /* Unsuspend OTG port */ reg = CSR_READ_4(sc, JZ_OPCR); reg |= OPCR_SPENDN0; CSR_WRITE_4(sc, JZ_OPCR, reg); CGU_UNLOCK(sc); return (0); } diff --git a/sys/mips/ingenic/jz4780_gpio.c b/sys/mips/ingenic/jz4780_gpio.c index fe1de7ccb915..77d1f5baaa3a 100644 --- a/sys/mips/ingenic/jz4780_gpio.c +++ b/sys/mips/ingenic/jz4780_gpio.c @@ -1,840 +1,840 @@ /*- * Copyright 2015 Alexander Kabaev * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include +#include #include "jz4780_gpio_if.h" #include "gpio_if.h" #include "pic_if.h" #define JZ4780_GPIO_PINS 32 enum pin_function { JZ_FUNC_DEV_0, JZ_FUNC_DEV_1, JZ_FUNC_DEV_2, JZ_FUNC_DEV_3, JZ_FUNC_GPIO, JZ_FUNC_INTR, }; struct jz4780_gpio_pin { struct intr_irqsrc pin_irqsrc; enum intr_trigger intr_trigger; enum intr_polarity intr_polarity; enum pin_function pin_func; uint32_t pin_caps; uint32_t pin_flags; uint32_t pin_num; char pin_name[GPIOMAXNAME]; }; struct jz4780_gpio_softc { device_t dev; device_t busdev; struct resource *res[2]; struct mtx mtx; struct jz4780_gpio_pin pins[JZ4780_GPIO_PINS]; void *intrhand; }; static struct resource_spec jz4780_gpio_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static int jz4780_gpio_probe(device_t dev); static int jz4780_gpio_attach(device_t dev); static int jz4780_gpio_detach(device_t dev); static int jz4780_gpio_intr(void *arg); #define JZ4780_GPIO_LOCK(sc) mtx_lock_spin(&(sc)->mtx) #define JZ4780_GPIO_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx) #define JZ4780_GPIO_LOCK_INIT(sc) \ mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ "jz4780_gpio", MTX_SPIN) #define JZ4780_GPIO_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) static int jz4780_gpio_probe(device_t dev) { phandle_t node; if (!ofw_bus_status_okay(dev)) return (ENXIO); /* We only like particular parent */ if (!ofw_bus_is_compatible(device_get_parent(dev), "ingenic,jz4780-pinctrl")) return (ENXIO); /* ... and only specific children os that parent */ node = ofw_bus_get_node(dev); if (!OF_hasprop(node, "gpio-controller")) return (ENXIO); device_set_desc(dev, "Ingenic JZ4780 GPIO Controller"); return (BUS_PROBE_DEFAULT); } static int jz4780_gpio_pin_set_func(struct jz4780_gpio_softc *sc, uint32_t pin, uint32_t func) { uint32_t mask = (1u << pin); if (func > (uint32_t)JZ_FUNC_DEV_3) return (EINVAL); CSR_WRITE_4(sc, JZ_GPIO_INTC, mask); CSR_WRITE_4(sc, JZ_GPIO_MASKC, mask); if (func & 2) CSR_WRITE_4(sc, JZ_GPIO_PAT1S, mask); else CSR_WRITE_4(sc, JZ_GPIO_PAT1C, mask); if (func & 1) CSR_WRITE_4(sc, JZ_GPIO_PAT0S, mask); else CSR_WRITE_4(sc, JZ_GPIO_PAT0C, mask); sc->pins[pin].pin_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); sc->pins[pin].pin_func = (enum pin_function)func; return (0); } static int jz4780_gpio_pin_set_direction(struct jz4780_gpio_softc *sc, uint32_t pin, uint32_t dir) { uint32_t mask = (1u << pin); switch (dir) { case GPIO_PIN_OUTPUT: if (sc->pins[pin].pin_caps & dir) CSR_WRITE_4(sc, JZ_GPIO_PAT1C, mask); else return (EINVAL); break; case GPIO_PIN_INPUT: if (sc->pins[pin].pin_caps & dir) CSR_WRITE_4(sc, JZ_GPIO_PAT1S, mask); else return (EINVAL); break; } sc->pins[pin].pin_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); sc->pins[pin].pin_flags |= dir; return (0); } static int jz4780_gpio_pin_set_bias(struct jz4780_gpio_softc *sc, uint32_t pin, uint32_t bias) { uint32_t mask = (1u << pin); switch (bias) { case GPIO_PIN_PULLUP: case GPIO_PIN_PULLDOWN: if (sc->pins[pin].pin_caps & bias) CSR_WRITE_4(sc, JZ_GPIO_DPULLC, mask); else return (EINVAL); break; case 0: CSR_WRITE_4(sc, JZ_GPIO_DPULLS, mask); break; default: return (ENOTSUP); } sc->pins[pin].pin_flags &= ~(GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN); sc->pins[pin].pin_flags |= bias; return (0); } /* * Decode pin configuration using this map */ #if 0 INT MASK PAT1 PAT0 1 x 0 0 /* intr, level, low */ 1 x 0 1 /* intr, level, high */ 1 x 1 0 /* intr, edge, falling */ 1 x 1 1 /* intr, edge, rising */ 0 0 0 0 /* function, func 0 */ 0 0 0 1 /* function, func 1 */ 0 0 1 0 /* function, func 2 */ 0 0 1 0 /* function, func 3 */ 0 1 0 0 /* gpio, output 0 */ 0 1 0 1 /* gpio, output 1 */ 0 1 1 x /* gpio, input */ #endif static void jz4780_gpio_pin_probe(struct jz4780_gpio_softc *sc, uint32_t pin) { uint32_t mask = (1u << pin); uint32_t val; /* Clear cached gpio config */ sc->pins[pin].pin_flags = 0; /* First check if pin is in interrupt mode */ val = CSR_READ_4(sc, JZ_GPIO_INT); if (val & mask) { /* Pin is in interrupt mode, decode interrupt triggering mode */ val = CSR_READ_4(sc, JZ_GPIO_PAT1); if (val & mask) sc->pins[pin].intr_trigger = INTR_TRIGGER_EDGE; else sc->pins[pin].intr_trigger = INTR_TRIGGER_LEVEL; /* Decode interrupt polarity */ val = CSR_READ_4(sc, JZ_GPIO_PAT0); if (val & mask) sc->pins[pin].intr_polarity = INTR_POLARITY_HIGH; else sc->pins[pin].intr_polarity = INTR_POLARITY_LOW; sc->pins[pin].pin_func = JZ_FUNC_INTR; sc->pins[pin].pin_flags = 0; return; } /* Next check if pin is in gpio mode */ val = CSR_READ_4(sc, JZ_GPIO_MASK); if (val & mask) { /* Pin is in gpio mode, decode direction and bias */ val = CSR_READ_4(sc, JZ_GPIO_PAT1); if (val & mask) sc->pins[pin].pin_flags |= GPIO_PIN_INPUT; else sc->pins[pin].pin_flags |= GPIO_PIN_OUTPUT; /* Check for bias */ val = CSR_READ_4(sc, JZ_GPIO_DPULL); if ((val & mask) == 0) sc->pins[pin].pin_flags |= sc->pins[pin].pin_caps & (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN); sc->pins[pin].pin_func = JZ_FUNC_GPIO; return; } /* By exclusion, pin is in alternate function mode */ val = CSR_READ_4(sc, JZ_GPIO_DPULL); if ((val & mask) == 0) sc->pins[pin].pin_flags = sc->pins[pin].pin_caps & (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN); val = ((CSR_READ_4(sc, JZ_GPIO_PAT1) & mask) >> pin) << 1; val = val | ((CSR_READ_4(sc, JZ_GPIO_PAT1) & mask) >> pin); sc->pins[pin].pin_func = (enum pin_function)val; } static int jz4780_gpio_register_isrcs(struct jz4780_gpio_softc *sc) { int error; uint32_t irq, i; struct intr_irqsrc *isrc; const char *name; name = device_get_nameunit(sc->dev); for (irq = 0; irq < JZ4780_GPIO_PINS; irq++) { isrc = &sc->pins[irq].pin_irqsrc; error = intr_isrc_register(isrc, sc->dev, 0, "%s,%d", name, irq); if (error != 0) { for (i = 0; i < irq; i++) intr_isrc_deregister(&sc->pins[i].pin_irqsrc); device_printf(sc->dev, "%s failed", __func__); return (error); } } return (0); } static int jz4780_gpio_attach(device_t dev) { struct jz4780_gpio_softc *sc = device_get_softc(dev); phandle_t node; uint32_t i, pd_pins, pu_pins; sc->dev = dev; if (bus_alloc_resources(dev, jz4780_gpio_spec, sc->res)) { device_printf(dev, "could not allocate resources for device\n"); return (ENXIO); } JZ4780_GPIO_LOCK_INIT(sc); node = ofw_bus_get_node(dev); OF_getencprop(node, "ingenic,pull-ups", &pu_pins, sizeof(pu_pins)); OF_getencprop(node, "ingenic,pull-downs", &pd_pins, sizeof(pd_pins)); for (i = 0; i < JZ4780_GPIO_PINS; i++) { sc->pins[i].pin_num = i; sc->pins[i].pin_caps |= GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; if (pu_pins & (1 << i)) sc->pins[i].pin_caps |= GPIO_PIN_PULLUP; if (pd_pins & (1 << i)) sc->pins[i].pin_caps |= GPIO_PIN_PULLDOWN; sc->pins[i].intr_polarity = INTR_POLARITY_CONFORM; sc->pins[i].intr_trigger = INTR_TRIGGER_CONFORM; snprintf(sc->pins[i].pin_name, GPIOMAXNAME - 1, "gpio%c%d", device_get_unit(dev) + 'a', i); sc->pins[i].pin_name[GPIOMAXNAME - 1] = '\0'; jz4780_gpio_pin_probe(sc, i); } if (jz4780_gpio_register_isrcs(sc) != 0) goto fail; if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { device_printf(dev, "could not register PIC\n"); goto fail; } if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, jz4780_gpio_intr, NULL, sc, &sc->intrhand) != 0) goto fail_pic; sc->busdev = gpiobus_attach_bus(dev); if (sc->busdev == NULL) goto fail_pic; return (0); fail_pic: intr_pic_deregister(dev, OF_xref_from_node(node)); fail: if (sc->intrhand != NULL) bus_teardown_intr(dev, sc->res[1], sc->intrhand); bus_release_resources(dev, jz4780_gpio_spec, sc->res); JZ4780_GPIO_LOCK_DESTROY(sc); return (ENXIO); } static int jz4780_gpio_detach(device_t dev) { struct jz4780_gpio_softc *sc = device_get_softc(dev); bus_release_resources(dev, jz4780_gpio_spec, sc->res); JZ4780_GPIO_LOCK_DESTROY(sc); return (0); } static int jz4780_gpio_configure_pin(device_t dev, uint32_t pin, uint32_t func, uint32_t flags) { struct jz4780_gpio_softc *sc; int retval; if (pin >= JZ4780_GPIO_PINS) return (EINVAL); sc = device_get_softc(dev); JZ4780_GPIO_LOCK(sc); retval = jz4780_gpio_pin_set_func(sc, pin, func); if (retval == 0) retval = jz4780_gpio_pin_set_bias(sc, pin, flags); JZ4780_GPIO_UNLOCK(sc); return (retval); } static device_t jz4780_gpio_get_bus(device_t dev) { struct jz4780_gpio_softc *sc; sc = device_get_softc(dev); return (sc->busdev); } static int jz4780_gpio_pin_max(device_t dev, int *maxpin) { *maxpin = JZ4780_GPIO_PINS - 1; return (0); } static int jz4780_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { struct jz4780_gpio_softc *sc; if (pin >= JZ4780_GPIO_PINS) return (EINVAL); sc = device_get_softc(dev); JZ4780_GPIO_LOCK(sc); *caps = sc->pins[pin].pin_caps; JZ4780_GPIO_UNLOCK(sc); return (0); } static int jz4780_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { struct jz4780_gpio_softc *sc; if (pin >= JZ4780_GPIO_PINS) return (EINVAL); sc = device_get_softc(dev); JZ4780_GPIO_LOCK(sc); *flags = sc->pins[pin].pin_flags; JZ4780_GPIO_UNLOCK(sc); return (0); } static int jz4780_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { struct jz4780_gpio_softc *sc; if (pin >= JZ4780_GPIO_PINS) return (EINVAL); sc = device_get_softc(dev); strncpy(name, sc->pins[pin].pin_name, GPIOMAXNAME - 1); name[GPIOMAXNAME - 1] = '\0'; return (0); } static int jz4780_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct jz4780_gpio_softc *sc; int retval; if (pin >= JZ4780_GPIO_PINS) return (EINVAL); sc = device_get_softc(dev); JZ4780_GPIO_LOCK(sc); retval = jz4780_gpio_pin_set_direction(sc, pin, flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)); if (retval == 0) retval = jz4780_gpio_pin_set_bias(sc, pin, flags & (GPIO_PIN_PULLDOWN | GPIO_PIN_PULLUP)); JZ4780_GPIO_UNLOCK(sc); return (retval); } static int jz4780_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct jz4780_gpio_softc *sc; uint32_t mask; int retval; if (pin >= JZ4780_GPIO_PINS) return (EINVAL); retval = EINVAL; mask = (1u << pin); sc = device_get_softc(dev); JZ4780_GPIO_LOCK(sc); if (sc->pins[pin].pin_func == JZ_FUNC_GPIO) { CSR_WRITE_4(sc, value ? JZ_GPIO_PAT0S : JZ_GPIO_PAT0C, mask); retval = 0; } JZ4780_GPIO_UNLOCK(sc); return (retval); } static int jz4780_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { struct jz4780_gpio_softc *sc; uint32_t data, mask; if (pin >= JZ4780_GPIO_PINS) return (EINVAL); mask = (1u << pin); sc = device_get_softc(dev); JZ4780_GPIO_LOCK(sc); data = CSR_READ_4(sc, JZ_GPIO_PIN); JZ4780_GPIO_UNLOCK(sc); *val = (data & mask) ? 1 : 0; return (0); } static int jz4780_gpio_pin_toggle(device_t dev, uint32_t pin) { struct jz4780_gpio_softc *sc; uint32_t data, mask; int retval; if (pin >= JZ4780_GPIO_PINS) return (EINVAL); retval = EINVAL; mask = (1u << pin); sc = device_get_softc(dev); JZ4780_GPIO_LOCK(sc); if (sc->pins[pin].pin_func == JZ_FUNC_GPIO && sc->pins[pin].pin_flags & GPIO_PIN_OUTPUT) { data = CSR_READ_4(sc, JZ_GPIO_PIN); CSR_WRITE_4(sc, (data & mask) ? JZ_GPIO_PAT0C : JZ_GPIO_PAT0S, mask); retval = 0; } JZ4780_GPIO_UNLOCK(sc); return (retval); } #ifdef FDT static int jz_gpio_map_intr_fdt(device_t dev, struct intr_map_data *data, u_int *irqp, enum intr_polarity *polp, enum intr_trigger *trigp) { struct jz4780_gpio_softc *sc; struct intr_map_data_fdt *daf; sc = device_get_softc(dev); daf = (struct intr_map_data_fdt *)data; if (data == NULL || data->type != INTR_MAP_DATA_FDT || daf->ncells == 0 || daf->ncells > 2) return (EINVAL); *irqp = daf->cells[0]; if (daf->ncells == 1) { *trigp = INTR_TRIGGER_CONFORM; *polp = INTR_POLARITY_CONFORM; return (0); } switch (daf->cells[1]) { case IRQ_TYPE_EDGE_RISING: *trigp = INTR_TRIGGER_EDGE; *polp = INTR_POLARITY_HIGH; break; case IRQ_TYPE_EDGE_FALLING: *trigp = INTR_TRIGGER_EDGE; *polp = INTR_POLARITY_LOW; break; case IRQ_TYPE_LEVEL_HIGH: *trigp = INTR_TRIGGER_LEVEL; *polp = INTR_POLARITY_HIGH; break; case IRQ_TYPE_LEVEL_LOW: *trigp = INTR_TRIGGER_LEVEL; *polp = INTR_POLARITY_LOW; break; default: device_printf(sc->dev, "unsupported trigger/polarity 0x%2x\n", daf->cells[1]); return (ENOTSUP); } return (0); } #endif static int jz_gpio_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp, enum intr_polarity *polp, enum intr_trigger *trigp) { struct jz4780_gpio_softc *sc; enum intr_polarity pol; enum intr_trigger trig; u_int irq; sc = device_get_softc(dev); switch (data->type) { #ifdef FDT case INTR_MAP_DATA_FDT: if (jz_gpio_map_intr_fdt(dev, data, &irq, &pol, &trig) != 0) return (EINVAL); break; #endif default: return (EINVAL); } if (irq >= nitems(sc->pins)) return (EINVAL); *irqp = irq; if (polp != NULL) *polp = pol; if (trigp != NULL) *trigp = trig; return (0); } static int jz4780_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, struct intr_irqsrc **isrcp) { struct jz4780_gpio_softc *sc; int retval; u_int irq; retval = jz_gpio_map_intr(dev, data, &irq, NULL, NULL); if (retval == 0) { sc = device_get_softc(dev); *isrcp = &sc->pins[irq].pin_irqsrc; } return (retval); } static int jz4780_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res, struct intr_map_data *data) { struct jz4780_gpio_softc *sc; struct jz4780_gpio_pin *pin; enum intr_polarity pol; enum intr_trigger trig; uint32_t mask, irq; if (data == NULL) return (ENOTSUP); /* Get config for resource. */ if (jz_gpio_map_intr(dev, data, &irq, &pol, &trig)) return (EINVAL); pin = __containerof(isrc, struct jz4780_gpio_pin, pin_irqsrc); if (isrc != &pin->pin_irqsrc) return (EINVAL); /* Compare config if this is not first setup. */ if (isrc->isrc_handlers != 0) { if ((pol != INTR_POLARITY_CONFORM && pol != pin->intr_polarity) || (trig != INTR_TRIGGER_CONFORM && trig != pin->intr_trigger)) return (EINVAL); else return (0); } if (pol == INTR_POLARITY_CONFORM) pol = INTR_POLARITY_LOW; /* just pick some */ if (trig == INTR_TRIGGER_CONFORM) trig = INTR_TRIGGER_EDGE; /* just pick some */ sc = device_get_softc(dev); mask = 1u << pin->pin_num; JZ4780_GPIO_LOCK(sc); CSR_WRITE_4(sc, JZ_GPIO_MASKS, mask); CSR_WRITE_4(sc, JZ_GPIO_INTS, mask); if (trig == INTR_TRIGGER_LEVEL) CSR_WRITE_4(sc, JZ_GPIO_PAT1C, mask); else CSR_WRITE_4(sc, JZ_GPIO_PAT1S, mask); if (pol == INTR_POLARITY_LOW) CSR_WRITE_4(sc, JZ_GPIO_PAT0C, mask); else CSR_WRITE_4(sc, JZ_GPIO_PAT0S, mask); pin->pin_func = JZ_FUNC_INTR; pin->intr_trigger = trig; pin->intr_polarity = pol; CSR_WRITE_4(sc, JZ_GPIO_FLAGC, mask); CSR_WRITE_4(sc, JZ_GPIO_MASKC, mask); JZ4780_GPIO_UNLOCK(sc); return (0); } static void jz4780_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) { struct jz4780_gpio_softc *sc; struct jz4780_gpio_pin *pin; sc = device_get_softc(dev); pin = __containerof(isrc, struct jz4780_gpio_pin, pin_irqsrc); CSR_WRITE_4(sc, JZ_GPIO_MASKC, 1u << pin->pin_num); } static void jz4780_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) { struct jz4780_gpio_softc *sc; struct jz4780_gpio_pin *pin; sc = device_get_softc(dev); pin = __containerof(isrc, struct jz4780_gpio_pin, pin_irqsrc); CSR_WRITE_4(sc, JZ_GPIO_MASKS, 1u << pin->pin_num); } static void jz4780_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) { jz4780_gpio_pic_disable_intr(dev, isrc); } static void jz4780_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) { jz4780_gpio_pic_enable_intr(dev, isrc); } static void jz4780_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) { struct jz4780_gpio_softc *sc; struct jz4780_gpio_pin *pin; sc = device_get_softc(dev); pin = __containerof(isrc, struct jz4780_gpio_pin, pin_irqsrc); CSR_WRITE_4(sc, JZ_GPIO_FLAGC, 1u << pin->pin_num); } static int jz4780_gpio_intr(void *arg) { struct jz4780_gpio_softc *sc; uint32_t i, interrupts; sc = arg; interrupts = CSR_READ_4(sc, JZ_GPIO_FLAG); for (i = 0; interrupts != 0; i++, interrupts >>= 1) { if ((interrupts & 0x1) == 0) continue; if (intr_isrc_dispatch(&sc->pins[i].pin_irqsrc, curthread->td_intr_frame) != 0) { device_printf(sc->dev, "spurious interrupt %d\n", i); PIC_DISABLE_INTR(sc->dev, &sc->pins[i].pin_irqsrc); } } return (FILTER_HANDLED); } static phandle_t jz4780_gpio_bus_get_node(device_t bus, device_t dev) { return (ofw_bus_get_node(bus)); } static device_method_t jz4780_gpio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, jz4780_gpio_probe), DEVMETHOD(device_attach, jz4780_gpio_attach), DEVMETHOD(device_detach, jz4780_gpio_detach), /* GPIO protocol */ DEVMETHOD(gpio_get_bus, jz4780_gpio_get_bus), DEVMETHOD(gpio_pin_max, jz4780_gpio_pin_max), DEVMETHOD(gpio_pin_getname, jz4780_gpio_pin_getname), DEVMETHOD(gpio_pin_getflags, jz4780_gpio_pin_getflags), DEVMETHOD(gpio_pin_getcaps, jz4780_gpio_pin_getcaps), DEVMETHOD(gpio_pin_setflags, jz4780_gpio_pin_setflags), DEVMETHOD(gpio_pin_get, jz4780_gpio_pin_get), DEVMETHOD(gpio_pin_set, jz4780_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, jz4780_gpio_pin_toggle), /* Custom interface to set pin function */ DEVMETHOD(jz4780_gpio_configure_pin, jz4780_gpio_configure_pin), /* Interrupt controller interface */ DEVMETHOD(pic_setup_intr, jz4780_gpio_pic_setup_intr), DEVMETHOD(pic_enable_intr, jz4780_gpio_pic_enable_intr), DEVMETHOD(pic_disable_intr, jz4780_gpio_pic_disable_intr), DEVMETHOD(pic_map_intr, jz4780_gpio_pic_map_intr), DEVMETHOD(pic_post_filter, jz4780_gpio_pic_post_filter), DEVMETHOD(pic_post_ithread, jz4780_gpio_pic_post_ithread), DEVMETHOD(pic_pre_ithread, jz4780_gpio_pic_pre_ithread), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, jz4780_gpio_bus_get_node), DEVMETHOD_END }; static driver_t jz4780_gpio_driver = { "gpio", jz4780_gpio_methods, sizeof(struct jz4780_gpio_softc), }; static devclass_t jz4780_gpio_devclass; EARLY_DRIVER_MODULE(jz4780_gpio, simplebus, jz4780_gpio_driver, jz4780_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); diff --git a/sys/mips/mediatek/mtk_gpio_v1.c b/sys/mips/mediatek/mtk_gpio_v1.c index 2771c6610d35..8c7df30f81e3 100644 --- a/sys/mips/mediatek/mtk_gpio_v1.c +++ b/sys/mips/mediatek/mtk_gpio_v1.c @@ -1,775 +1,775 @@ /*- * Copyright 2016 Stanislav Galabov * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include +#include #include "gpio_if.h" #include "pic_if.h" #define MTK_GPIO_PINS 32 enum mtk_gpio_regs { GPIO_PIOINT = 0, GPIO_PIOEDGE, GPIO_PIORENA, GPIO_PIOFENA, GPIO_PIODATA, GPIO_PIODIR, GPIO_PIOPOL, GPIO_PIOSET, GPIO_PIORESET, GPIO_PIOTOG, GPIO_PIOMAX }; struct mtk_gpio_pin_irqsrc { struct intr_irqsrc isrc; u_int irq; }; struct mtk_gpio_pin { uint32_t pin_caps; uint32_t pin_flags; enum intr_trigger intr_trigger; enum intr_polarity intr_polarity; char pin_name[GPIOMAXNAME]; struct mtk_gpio_pin_irqsrc pin_irqsrc; }; struct mtk_gpio_softc { device_t dev; device_t busdev; struct resource *res[2]; struct mtx mtx; struct mtk_gpio_pin pins[MTK_GPIO_PINS]; void *intrhand; uint8_t regs[GPIO_PIOMAX]; uint32_t num_pins; uint8_t do_remap; }; #define PIC_INTR_ISRC(sc, irq) (&(sc)->pins[(irq)].pin_irqsrc.isrc) static struct resource_spec mtk_gpio_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0 } }; static int mtk_gpio_probe(device_t dev); static int mtk_gpio_attach(device_t dev); static int mtk_gpio_detach(device_t dev); static int mtk_gpio_intr(void *arg); #define MTK_GPIO_LOCK(sc) mtx_lock_spin(&(sc)->mtx) #define MTK_GPIO_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx) #define MTK_GPIO_LOCK_INIT(sc) \ mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ "mtk_gpio", MTX_SPIN) #define MTK_GPIO_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) #define MTK_WRITE_4(sc, reg, val) \ bus_write_4((sc)->res[0], (sc)->regs[(reg)], (val)) #define MTK_READ_4(sc, reg) \ bus_read_4((sc)->res[0], (sc)->regs[(reg)]) static struct ofw_compat_data compat_data[] = { { "ralink,rt2880-gpio", 1 }, { "ralink,rt3050-gpio", 1 }, { "ralink,rt3352-gpio", 1 }, { "ralink,rt3883-gpio", 1 }, { "ralink,rt5350-gpio", 1 }, { "ralink,mt7620a-gpio", 1 }, { NULL, 0 } }; static int mtk_gpio_probe(device_t dev) { phandle_t node; if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); node = ofw_bus_get_node(dev); if (!OF_hasprop(node, "gpio-controller")) return (ENXIO); device_set_desc(dev, "MTK GPIO Controller (v1)"); return (BUS_PROBE_DEFAULT); } static int mtk_pic_register_isrcs(struct mtk_gpio_softc *sc) { int error; uint32_t irq; struct intr_irqsrc *isrc; const char *name; name = device_get_nameunit(sc->dev); for (irq = 0; irq < sc->num_pins; irq++) { sc->pins[irq].pin_irqsrc.irq = irq; isrc = PIC_INTR_ISRC(sc, irq); error = intr_isrc_register(isrc, sc->dev, 0, "%s", name); if (error != 0) { /* XXX call intr_isrc_deregister */ device_printf(sc->dev, "%s failed", __func__); return (error); } } return (0); } static int mtk_gpio_pin_set_direction(struct mtk_gpio_softc *sc, uint32_t pin, uint32_t dir) { uint32_t regval, mask = (1u << pin); if (!(sc->pins[pin].pin_caps & dir)) return (EINVAL); regval = MTK_READ_4(sc, GPIO_PIODIR); if (dir == GPIO_PIN_INPUT) regval &= ~mask; else regval |= mask; MTK_WRITE_4(sc, GPIO_PIODIR, regval); sc->pins[pin].pin_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); sc->pins[pin].pin_flags |= dir; return (0); } static int mtk_gpio_pin_set_invert(struct mtk_gpio_softc *sc, uint32_t pin, uint32_t val) { uint32_t regval, mask = (1u << pin); regval = MTK_READ_4(sc, GPIO_PIOPOL); if (val) regval |= mask; else regval &= ~mask; MTK_WRITE_4(sc, GPIO_PIOPOL, regval); sc->pins[pin].pin_flags &= ~(GPIO_PIN_INVIN | GPIO_PIN_INVOUT); sc->pins[pin].pin_flags |= val; return (0); } static void mtk_gpio_pin_probe(struct mtk_gpio_softc *sc, uint32_t pin) { uint32_t mask = (1u << pin); uint32_t val; /* Clear cached gpio config */ sc->pins[pin].pin_flags = 0; val = MTK_READ_4(sc, GPIO_PIORENA) | MTK_READ_4(sc, GPIO_PIOFENA); if (val & mask) { /* Pin is in interrupt mode */ sc->pins[pin].intr_trigger = INTR_TRIGGER_EDGE; val = MTK_READ_4(sc, GPIO_PIORENA); if (val & mask) sc->pins[pin].intr_polarity = INTR_POLARITY_HIGH; else sc->pins[pin].intr_polarity = INTR_POLARITY_LOW; } val = MTK_READ_4(sc, GPIO_PIODIR); if (val & mask) sc->pins[pin].pin_flags |= GPIO_PIN_OUTPUT; else sc->pins[pin].pin_flags |= GPIO_PIN_INPUT; val = MTK_READ_4(sc, GPIO_PIOPOL); if (val & mask) { if (sc->pins[pin].pin_flags & GPIO_PIN_INPUT) { sc->pins[pin].pin_flags |= GPIO_PIN_INVIN; } else { sc->pins[pin].pin_flags |= GPIO_PIN_INVOUT; } } } static int mtk_gpio_attach(device_t dev) { struct mtk_gpio_softc *sc; phandle_t node; uint32_t i, num_pins; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, mtk_gpio_spec, sc->res)) { device_printf(dev, "could not allocate resources for device\n"); return (ENXIO); } MTK_GPIO_LOCK_INIT(sc); node = ofw_bus_get_node(dev); if (OF_hasprop(node, "clocks")) mtk_soc_start_clock(dev); if (OF_hasprop(node, "resets")) mtk_soc_reset_device(dev); if (OF_getprop(node, "ralink,register-map", sc->regs, GPIO_PIOMAX) <= 0) { device_printf(dev, "Failed to read register map\n"); return (ENXIO); } if (OF_hasprop(node, "ralink,num-gpios") && (OF_getencprop(node, "ralink,num-gpios", &num_pins, sizeof(num_pins)) >= 0)) sc->num_pins = num_pins; else sc->num_pins = MTK_GPIO_PINS; for (i = 0; i < sc->num_pins; i++) { sc->pins[i].pin_caps |= GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_INVIN | GPIO_PIN_INVOUT | GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING; sc->pins[i].intr_polarity = INTR_POLARITY_HIGH; sc->pins[i].intr_trigger = INTR_TRIGGER_EDGE; snprintf(sc->pins[i].pin_name, GPIOMAXNAME - 1, "gpio%c%d", device_get_unit(dev) + 'a', i); sc->pins[i].pin_name[GPIOMAXNAME - 1] = '\0'; mtk_gpio_pin_probe(sc, i); } if (mtk_pic_register_isrcs(sc) != 0) { device_printf(dev, "could not register PIC ISRCs\n"); goto fail; } if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { device_printf(dev, "could not register PIC\n"); goto fail; } if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, mtk_gpio_intr, NULL, sc, &sc->intrhand) != 0) goto fail_pic; sc->busdev = gpiobus_attach_bus(dev); if (sc->busdev == NULL) goto fail_pic; return (0); fail_pic: intr_pic_deregister(dev, OF_xref_from_node(node)); fail: if(sc->intrhand != NULL) bus_teardown_intr(dev, sc->res[1], sc->intrhand); bus_release_resources(dev, mtk_gpio_spec, sc->res); MTK_GPIO_LOCK_DESTROY(sc); return (ENXIO); } static int mtk_gpio_detach(device_t dev) { struct mtk_gpio_softc *sc = device_get_softc(dev); phandle_t node; node = ofw_bus_get_node(dev); intr_pic_deregister(dev, OF_xref_from_node(node)); if (sc->intrhand != NULL) bus_teardown_intr(dev, sc->res[1], sc->intrhand); bus_release_resources(dev, mtk_gpio_spec, sc->res); MTK_GPIO_LOCK_DESTROY(sc); return (0); } static device_t mtk_gpio_get_bus(device_t dev) { struct mtk_gpio_softc *sc = device_get_softc(dev); return (sc->busdev); } static int mtk_gpio_pin_max(device_t dev, int *maxpin) { struct mtk_gpio_softc *sc = device_get_softc(dev); *maxpin = sc->num_pins - 1; return (0); } static int mtk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); *caps = sc->pins[pin].pin_caps; MTK_GPIO_UNLOCK(sc); return (0); } static int mtk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); *flags = sc->pins[pin].pin_flags; MTK_GPIO_UNLOCK(sc); return (0); } static int mtk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); strncpy(name, sc->pins[pin].pin_name, GPIOMAXNAME - 1); name[GPIOMAXNAME - 1] = '\0'; return (0); } static int mtk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct mtk_gpio_softc *sc; int retval; sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); retval = mtk_gpio_pin_set_direction(sc, pin, flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)); if (retval == 0) retval = mtk_gpio_pin_set_invert(sc, pin, flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)); MTK_GPIO_UNLOCK(sc); return (retval); } static int mtk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct mtk_gpio_softc *sc; int ret; sc = device_get_softc(dev); ret = 0; if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); if (value) MTK_WRITE_4(sc, GPIO_PIOSET, (1u << pin)); else MTK_WRITE_4(sc, GPIO_PIORESET, (1u << pin)); MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { struct mtk_gpio_softc *sc; uint32_t data; int ret; sc = device_get_softc(dev); ret = 0; if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); data = MTK_READ_4(sc, GPIO_PIODATA); *val = (data & (1u << pin)) ? 1 : 0; MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pin_toggle(device_t dev, uint32_t pin) { struct mtk_gpio_softc *sc; int ret; sc = device_get_softc(dev); ret = 0; if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); if (!(sc->pins[pin].pin_flags & GPIO_PIN_OUTPUT)) { ret = EINVAL; goto out; } MTK_WRITE_4(sc, GPIO_PIOTOG, (1u << pin)); out: MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pic_map_fdt(struct mtk_gpio_softc *sc, struct intr_map_data_fdt *daf, u_int *irqp, uint32_t *modep) { u_int irq; if (daf->ncells != 1) { device_printf(sc->dev, "Invalid #interrupt-cells\n"); return (EINVAL); } irq = daf->cells[0]; if (irq >= sc->num_pins) { device_printf(sc->dev, "Invalid interrupt number %u\n", irq); return (EINVAL); } *irqp = irq; if (modep != NULL) *modep = GPIO_INTR_EDGE_BOTH; return (0); } static int mtk_gpio_pic_map_gpio(struct mtk_gpio_softc *sc, struct intr_map_data_gpio *dag, u_int *irqp, uint32_t *modep) { u_int irq; irq = dag->gpio_pin_num; if (irq >= sc->num_pins) { device_printf(sc->dev, "Invalid interrupt number %u\n", irq); return (EINVAL); } *irqp = irq; if (modep != NULL) *modep = dag->gpio_intr_mode; return (0); } static int mtk_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, struct intr_irqsrc **isrcp) { int error; u_int irq; struct mtk_gpio_softc *sc; sc = device_get_softc(dev); switch (data->type) { case INTR_MAP_DATA_FDT: error = (mtk_gpio_pic_map_fdt(sc, (struct intr_map_data_fdt *)data, &irq, NULL)); break; case INTR_MAP_DATA_GPIO: error = (mtk_gpio_pic_map_gpio(sc, (struct intr_map_data_gpio *)data, &irq, NULL)); break; default: error = EINVAL; break; } if (error != 0) { device_printf(dev, "Invalid map type\n"); return (error); } *isrcp = PIC_INTR_ISRC(sc, irq); return (0); } static void mtk_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; uint32_t pin, mask, val; sc = device_get_softc(dev); pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; pin = pisrc->irq; mask = 1u << pin; MTK_GPIO_LOCK(sc); if (sc->pins[pin].intr_polarity == INTR_POLARITY_LOW) { val = MTK_READ_4(sc, GPIO_PIORENA) & ~mask; MTK_WRITE_4(sc, GPIO_PIORENA, val); val = MTK_READ_4(sc, GPIO_PIOFENA) | mask; MTK_WRITE_4(sc, GPIO_PIOFENA, val); } else { val = MTK_READ_4(sc, GPIO_PIOFENA) & ~mask; MTK_WRITE_4(sc, GPIO_PIOFENA, val); val = MTK_READ_4(sc, GPIO_PIORENA) | mask; MTK_WRITE_4(sc, GPIO_PIORENA, val); } MTK_GPIO_UNLOCK(sc); } static void mtk_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; uint32_t pin, mask, val; sc = device_get_softc(dev); pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; pin = pisrc->irq; mask = 1u << pin; MTK_GPIO_LOCK(sc); val = MTK_READ_4(sc, GPIO_PIORENA) & ~mask; MTK_WRITE_4(sc, GPIO_PIORENA, val); val = MTK_READ_4(sc, GPIO_PIOFENA) & ~mask; MTK_WRITE_4(sc, GPIO_PIOFENA, val); MTK_GPIO_UNLOCK(sc); } static void mtk_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) { mtk_gpio_pic_disable_intr(dev, isrc); } static void mtk_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) { mtk_gpio_pic_enable_intr(dev, isrc); } static void mtk_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; sc = device_get_softc(dev); MTK_GPIO_LOCK(sc); MTK_WRITE_4(sc, GPIO_PIOINT, 1u << pisrc->irq); MTK_GPIO_UNLOCK(sc); } static int mtk_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res, struct intr_map_data *data) { struct mtk_gpio_softc *sc; uint32_t val; int error; uint32_t mode; u_int irq; if (data == NULL) return (ENOTSUP); sc = device_get_softc(dev); switch (data->type) { case INTR_MAP_DATA_FDT: error = mtk_gpio_pic_map_fdt(sc, (struct intr_map_data_fdt *)data, &irq, &mode); break; case INTR_MAP_DATA_GPIO: error = mtk_gpio_pic_map_gpio(sc, (struct intr_map_data_gpio *)data, &irq, &mode); break; default: error = ENOTSUP; break; } if (error != 0) return (error); MTK_GPIO_LOCK(sc); if (mode == GPIO_INTR_EDGE_BOTH || mode == GPIO_INTR_EDGE_RISING) { val = MTK_READ_4(sc, GPIO_PIORENA) | (1u << irq); MTK_WRITE_4(sc, GPIO_PIORENA, val); } if (mode == GPIO_INTR_EDGE_BOTH || mode == GPIO_INTR_EDGE_FALLING) { val = MTK_READ_4(sc, GPIO_PIOFENA) | (1u << irq); MTK_WRITE_4(sc, GPIO_PIOFENA, val); } MTK_GPIO_UNLOCK(sc); return (0); } static int mtk_gpio_intr(void *arg) { struct mtk_gpio_softc *sc; uint32_t i, interrupts; sc = arg; interrupts = MTK_READ_4(sc, GPIO_PIOINT); MTK_WRITE_4(sc, GPIO_PIOINT, interrupts); for (i = 0; interrupts != 0; i++, interrupts >>= 1) { if ((interrupts & 0x1) == 0) continue; if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i), curthread->td_intr_frame) != 0) { device_printf(sc->dev, "spurious interrupt %d\n", i); } } return (FILTER_HANDLED); } static phandle_t mtk_gpio_get_node(device_t bus, device_t dev) { /* We only have one child, the GPIO bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t mtk_gpio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_gpio_probe), DEVMETHOD(device_attach, mtk_gpio_attach), DEVMETHOD(device_detach, mtk_gpio_detach), /* GPIO protocol */ DEVMETHOD(gpio_get_bus, mtk_gpio_get_bus), DEVMETHOD(gpio_pin_max, mtk_gpio_pin_max), DEVMETHOD(gpio_pin_getname, mtk_gpio_pin_getname), DEVMETHOD(gpio_pin_getflags, mtk_gpio_pin_getflags), DEVMETHOD(gpio_pin_getcaps, mtk_gpio_pin_getcaps), DEVMETHOD(gpio_pin_setflags, mtk_gpio_pin_setflags), DEVMETHOD(gpio_pin_get, mtk_gpio_pin_get), DEVMETHOD(gpio_pin_set, mtk_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, mtk_gpio_pin_toggle), /* Interrupt controller interface */ DEVMETHOD(pic_disable_intr, mtk_gpio_pic_disable_intr), DEVMETHOD(pic_enable_intr, mtk_gpio_pic_enable_intr), DEVMETHOD(pic_map_intr, mtk_gpio_pic_map_intr), DEVMETHOD(pic_setup_intr, mtk_gpio_pic_setup_intr), DEVMETHOD(pic_post_filter, mtk_gpio_pic_post_filter), DEVMETHOD(pic_post_ithread, mtk_gpio_pic_post_ithread), DEVMETHOD(pic_pre_ithread, mtk_gpio_pic_pre_ithread), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, mtk_gpio_get_node), DEVMETHOD_END }; static driver_t mtk_gpio_driver = { "gpio", mtk_gpio_methods, sizeof(struct mtk_gpio_softc), }; static devclass_t mtk_gpio_devclass; EARLY_DRIVER_MODULE(mtk_gpio_v1, simplebus, mtk_gpio_driver, mtk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); diff --git a/sys/mips/mediatek/mtk_gpio_v2.c b/sys/mips/mediatek/mtk_gpio_v2.c index cd1708261fd4..677c42c64c0b 100644 --- a/sys/mips/mediatek/mtk_gpio_v2.c +++ b/sys/mips/mediatek/mtk_gpio_v2.c @@ -1,668 +1,668 @@ /*- * Copyright 2016 Stanislav Galabov * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include +#include #include "gpio_if.h" #include "pic_if.h" #define MTK_GPIO_PINS 32 struct mtk_gpio_pin_irqsrc { struct intr_irqsrc isrc; u_int irq; }; struct mtk_gpio_pin { uint32_t pin_caps; uint32_t pin_flags; enum intr_trigger intr_trigger; enum intr_polarity intr_polarity; char pin_name[GPIOMAXNAME]; struct mtk_gpio_pin_irqsrc pin_irqsrc; }; struct mtk_gpio_softc { device_t dev; device_t busdev; struct resource *res[2]; struct mtx mtx; struct mtk_gpio_pin pins[MTK_GPIO_PINS]; void *intrhand; uint32_t num_pins; uint32_t bank_id; }; #define PIC_INTR_ISRC(sc, irq) (&(sc)->pins[(irq)].pin_irqsrc.isrc) static struct resource_spec mtk_gpio_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE }, { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0 } }; static int mtk_gpio_probe(device_t dev); static int mtk_gpio_attach(device_t dev); static int mtk_gpio_detach(device_t dev); static int mtk_gpio_intr(void *arg); #define MTK_GPIO_LOCK(sc) mtx_lock_spin(&(sc)->mtx) #define MTK_GPIO_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx) #define MTK_GPIO_LOCK_INIT(sc) \ mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ "mtk_gpio", MTX_SPIN) #define MTK_GPIO_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) #define MTK_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) #define MTK_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) /* Register definitions */ #define GPIO_REG(_sc, _reg) ((_reg) + (_sc)->bank_id * 0x4) #define GPIO_PIOINT(_sc) GPIO_REG((_sc), 0x0090) #define GPIO_PIOEDGE(_sc) GPIO_REG((_sc), 0x00A0) #define GPIO_PIORENA(_sc) GPIO_REG((_sc), 0x0050) #define GPIO_PIOFENA(_sc) GPIO_REG((_sc), 0x0060) #define GPIO_PIODATA(_sc) GPIO_REG((_sc), 0x0020) #define GPIO_PIODIR(_sc) GPIO_REG((_sc), 0x0000) #define GPIO_PIOPOL(_sc) GPIO_REG((_sc), 0x0010) #define GPIO_PIOSET(_sc) GPIO_REG((_sc), 0x0030) #define GPIO_PIORESET(_sc) GPIO_REG((_sc), 0x0040) static struct ofw_compat_data compat_data[] = { { "mtk,mt7621-gpio-bank", 1 }, { "mtk,mt7628-gpio-bank", 1 }, { NULL, 0 } }; static int mtk_gpio_probe(device_t dev) { phandle_t node; if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); node = ofw_bus_get_node(dev); if (!OF_hasprop(node, "gpio-controller")) return (ENXIO); device_set_desc(dev, "MTK GPIO Controller (v2)"); return (BUS_PROBE_DEFAULT); } static int mtk_pic_register_isrcs(struct mtk_gpio_softc *sc) { int error; uint32_t irq; struct intr_irqsrc *isrc; const char *name; name = device_get_nameunit(sc->dev); for (irq = 0; irq < sc->num_pins; irq++) { sc->pins[irq].pin_irqsrc.irq = irq; isrc = PIC_INTR_ISRC(sc, irq); error = intr_isrc_register(isrc, sc->dev, 0, "%s", name); if (error != 0) { /* XXX call intr_isrc_deregister */ device_printf(sc->dev, "%s failed", __func__); return (error); } } return (0); } static int mtk_gpio_pin_set_direction(struct mtk_gpio_softc *sc, uint32_t pin, uint32_t dir) { uint32_t regval, mask = (1u << pin); if (!(sc->pins[pin].pin_caps & dir)) return (EINVAL); regval = MTK_READ_4(sc, GPIO_PIODIR(sc)); if (dir == GPIO_PIN_INPUT) regval &= ~mask; else regval |= mask; MTK_WRITE_4(sc, GPIO_PIODIR(sc), regval); sc->pins[pin].pin_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); sc->pins[pin].pin_flags |= dir; return (0); } static int mtk_gpio_pin_set_invert(struct mtk_gpio_softc *sc, uint32_t pin, uint32_t val) { uint32_t regval, mask = (1u << pin); regval = MTK_READ_4(sc, GPIO_PIOPOL(sc)); if (val) regval |= mask; else regval &= ~mask; MTK_WRITE_4(sc, GPIO_PIOPOL(sc), regval); sc->pins[pin].pin_flags &= ~(GPIO_PIN_INVIN | GPIO_PIN_INVOUT); sc->pins[pin].pin_flags |= val; return (0); } static void mtk_gpio_pin_probe(struct mtk_gpio_softc *sc, uint32_t pin) { uint32_t mask = (1u << pin); uint32_t val; /* Clear cached gpio config */ sc->pins[pin].pin_flags = 0; val = MTK_READ_4(sc, GPIO_PIORENA(sc)) | MTK_READ_4(sc, GPIO_PIOFENA(sc)); if (val & mask) { /* Pin is in interrupt mode */ sc->pins[pin].intr_trigger = INTR_TRIGGER_EDGE; val = MTK_READ_4(sc, GPIO_PIORENA(sc)); if (val & mask) sc->pins[pin].intr_polarity = INTR_POLARITY_HIGH; else sc->pins[pin].intr_polarity = INTR_POLARITY_LOW; } val = MTK_READ_4(sc, GPIO_PIODIR(sc)); if (val & mask) sc->pins[pin].pin_flags |= GPIO_PIN_OUTPUT; else sc->pins[pin].pin_flags |= GPIO_PIN_INPUT; val = MTK_READ_4(sc, GPIO_PIOPOL(sc)); if (val & mask) { if (sc->pins[pin].pin_flags & GPIO_PIN_INPUT) { sc->pins[pin].pin_flags |= GPIO_PIN_INVIN; } else { sc->pins[pin].pin_flags |= GPIO_PIN_INVOUT; } } } static int mtk_gpio_attach(device_t dev) { struct mtk_gpio_softc *sc; phandle_t node; uint32_t i, num_pins, bank_id; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, mtk_gpio_spec, sc->res)) { device_printf(dev, "could not allocate resources for device\n"); return (ENXIO); } MTK_GPIO_LOCK_INIT(sc); node = ofw_bus_get_node(dev); if (OF_hasprop(node, "clocks")) mtk_soc_start_clock(dev); if (OF_hasprop(node, "resets")) mtk_soc_reset_device(dev); if (OF_hasprop(node, "mtk,bank-id") && (OF_getencprop(node, "mtk,bank-id", &bank_id, sizeof(bank_id)) >= 0)) sc->bank_id = bank_id; else sc->bank_id = device_get_unit(dev); if (OF_hasprop(node, "mtk,num-pins") && (OF_getencprop(node, "mtk,num-pins", &num_pins, sizeof(num_pins)) >= 0)) sc->num_pins = num_pins; else sc->num_pins = MTK_GPIO_PINS; for (i = 0; i < sc->num_pins; i++) { sc->pins[i].pin_caps |= GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_INVIN | GPIO_PIN_INVOUT; sc->pins[i].intr_polarity = INTR_POLARITY_HIGH; sc->pins[i].intr_trigger = INTR_TRIGGER_EDGE; snprintf(sc->pins[i].pin_name, GPIOMAXNAME - 1, "gpio%c%d", device_get_unit(dev) + 'a', i); sc->pins[i].pin_name[GPIOMAXNAME - 1] = '\0'; mtk_gpio_pin_probe(sc, i); } if (mtk_pic_register_isrcs(sc) != 0) { device_printf(dev, "could not register PIC ISRCs\n"); goto fail; } if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { device_printf(dev, "could not register PIC\n"); goto fail; } if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, mtk_gpio_intr, NULL, sc, &sc->intrhand) != 0) goto fail_pic; sc->busdev = gpiobus_attach_bus(dev); if (sc->busdev == NULL) goto fail_pic; return (0); fail_pic: intr_pic_deregister(dev, OF_xref_from_node(node)); fail: if(sc->intrhand != NULL) bus_teardown_intr(dev, sc->res[1], sc->intrhand); bus_release_resources(dev, mtk_gpio_spec, sc->res); MTK_GPIO_LOCK_DESTROY(sc); return (ENXIO); } static int mtk_gpio_detach(device_t dev) { struct mtk_gpio_softc *sc = device_get_softc(dev); phandle_t node; node = ofw_bus_get_node(dev); intr_pic_deregister(dev, OF_xref_from_node(node)); if (sc->intrhand != NULL) bus_teardown_intr(dev, sc->res[1], sc->intrhand); bus_release_resources(dev, mtk_gpio_spec, sc->res); MTK_GPIO_LOCK_DESTROY(sc); return (0); } static device_t mtk_gpio_get_bus(device_t dev) { struct mtk_gpio_softc *sc = device_get_softc(dev); return (sc->busdev); } static int mtk_gpio_pin_max(device_t dev, int *maxpin) { struct mtk_gpio_softc *sc = device_get_softc(dev); *maxpin = sc->num_pins - 1; return (0); } static int mtk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); *caps = sc->pins[pin].pin_caps; MTK_GPIO_UNLOCK(sc); return (0); } static int mtk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); *flags = sc->pins[pin].pin_flags; MTK_GPIO_UNLOCK(sc); return (0); } static int mtk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { struct mtk_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); strncpy(name, sc->pins[pin].pin_name, GPIOMAXNAME - 1); name[GPIOMAXNAME - 1] = '\0'; return (0); } static int mtk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct mtk_gpio_softc *sc; int retval; sc = device_get_softc(dev); if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); retval = mtk_gpio_pin_set_direction(sc, pin, flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)); if (retval == 0) retval = mtk_gpio_pin_set_invert(sc, pin, flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)); MTK_GPIO_UNLOCK(sc); return (retval); } static int mtk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct mtk_gpio_softc *sc; int ret; sc = device_get_softc(dev); ret = 0; if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); if (value) MTK_WRITE_4(sc, GPIO_PIOSET(sc), (1u << pin)); else MTK_WRITE_4(sc, GPIO_PIORESET(sc), (1u << pin)); MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { struct mtk_gpio_softc *sc; uint32_t data; int ret; sc = device_get_softc(dev); ret = 0; if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); data = MTK_READ_4(sc, GPIO_PIODATA(sc)); *val = (data & (1u << pin)) ? 1 : 0; MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pin_toggle(device_t dev, uint32_t pin) { struct mtk_gpio_softc *sc; uint32_t val; int ret; sc = device_get_softc(dev); ret = 0; if (pin >= sc->num_pins) return (EINVAL); MTK_GPIO_LOCK(sc); if(!(sc->pins[pin].pin_flags & GPIO_PIN_OUTPUT)) { ret = EINVAL; goto out; } val = MTK_READ_4(sc, GPIO_PIODATA(sc)); val &= (1u << pin); if (val) MTK_WRITE_4(sc, GPIO_PIORESET(sc), (1u << pin)); else MTK_WRITE_4(sc, GPIO_PIOSET(sc), (1u << pin)); out: MTK_GPIO_UNLOCK(sc); return (ret); } static int mtk_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, struct intr_irqsrc **isrcp) { struct intr_map_data_fdt *daf; struct mtk_gpio_softc *sc; if (data->type != INTR_MAP_DATA_FDT) return (ENOTSUP); sc = device_get_softc(dev); daf = (struct intr_map_data_fdt *)data; if (daf->ncells != 1 || daf->cells[0] >= sc->num_pins) return (EINVAL); *isrcp = PIC_INTR_ISRC(sc, daf->cells[0]); return (0); } static void mtk_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; uint32_t pin, mask, val; sc = device_get_softc(dev); pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; pin = pisrc->irq; mask = 1u << pin; MTK_GPIO_LOCK(sc); if (sc->pins[pin].intr_polarity == INTR_POLARITY_LOW) { val = MTK_READ_4(sc, GPIO_PIORENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIORENA(sc), val); val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) | mask; MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val); } else { val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val); val = MTK_READ_4(sc, GPIO_PIORENA(sc)) | mask; MTK_WRITE_4(sc, GPIO_PIORENA(sc), val); } MTK_GPIO_UNLOCK(sc); } static void mtk_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; uint32_t pin, mask, val; sc = device_get_softc(dev); pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; pin = pisrc->irq; mask = 1u << pin; MTK_GPIO_LOCK(sc); val = MTK_READ_4(sc, GPIO_PIORENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIORENA(sc), val); val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) & ~mask; MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val); MTK_GPIO_UNLOCK(sc); } static void mtk_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) { mtk_gpio_pic_disable_intr(dev, isrc); } static void mtk_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) { mtk_gpio_pic_enable_intr(dev, isrc); } static void mtk_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) { struct mtk_gpio_softc *sc; struct mtk_gpio_pin_irqsrc *pisrc; pisrc = (struct mtk_gpio_pin_irqsrc *)isrc; sc = device_get_softc(dev); MTK_GPIO_LOCK(sc); MTK_WRITE_4(sc, GPIO_PIOINT(sc), 1u << pisrc->irq); MTK_GPIO_UNLOCK(sc); } static int mtk_gpio_intr(void *arg) { struct mtk_gpio_softc *sc; uint32_t i, interrupts; sc = arg; interrupts = MTK_READ_4(sc, GPIO_PIOINT(sc)); for (i = 0; interrupts != 0; i++, interrupts >>= 1) { if ((interrupts & 0x1) == 0) continue; if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i), curthread->td_intr_frame) != 0) { device_printf(sc->dev, "spurious interrupt %d\n", i); } } return (FILTER_HANDLED); } static phandle_t mtk_gpio_get_node(device_t bus, device_t dev) { /* We only have one child, the GPIO bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t mtk_gpio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_gpio_probe), DEVMETHOD(device_attach, mtk_gpio_attach), DEVMETHOD(device_detach, mtk_gpio_detach), /* GPIO protocol */ DEVMETHOD(gpio_get_bus, mtk_gpio_get_bus), DEVMETHOD(gpio_pin_max, mtk_gpio_pin_max), DEVMETHOD(gpio_pin_getname, mtk_gpio_pin_getname), DEVMETHOD(gpio_pin_getflags, mtk_gpio_pin_getflags), DEVMETHOD(gpio_pin_getcaps, mtk_gpio_pin_getcaps), DEVMETHOD(gpio_pin_setflags, mtk_gpio_pin_setflags), DEVMETHOD(gpio_pin_get, mtk_gpio_pin_get), DEVMETHOD(gpio_pin_set, mtk_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, mtk_gpio_pin_toggle), /* Interrupt controller interface */ DEVMETHOD(pic_disable_intr, mtk_gpio_pic_disable_intr), DEVMETHOD(pic_enable_intr, mtk_gpio_pic_enable_intr), DEVMETHOD(pic_map_intr, mtk_gpio_pic_map_intr), DEVMETHOD(pic_post_filter, mtk_gpio_pic_post_filter), DEVMETHOD(pic_post_ithread, mtk_gpio_pic_post_ithread), DEVMETHOD(pic_pre_ithread, mtk_gpio_pic_pre_ithread), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, mtk_gpio_get_node), DEVMETHOD_END }; static driver_t mtk_gpio_driver = { "gpio", mtk_gpio_methods, sizeof(struct mtk_gpio_softc), }; static devclass_t mtk_gpio_devclass; EARLY_DRIVER_MODULE(mtk_gpio_v2, simplebus, mtk_gpio_driver, mtk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);