diff --git a/sys/contrib/dev/iwlwifi/iwl-dbg-tlv.c b/sys/contrib/dev/iwlwifi/iwl-dbg-tlv.c index 866a33f49915..3237d4b528b5 100644 --- a/sys/contrib/dev/iwlwifi/iwl-dbg-tlv.c +++ b/sys/contrib/dev/iwlwifi/iwl-dbg-tlv.c @@ -1,1383 +1,1383 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* * Copyright (C) 2018-2022 Intel Corporation */ #include #include "iwl-drv.h" #include "iwl-trans.h" #include "iwl-dbg-tlv.h" #include "fw/dbg.h" #include "fw/runtime.h" /** * enum iwl_dbg_tlv_type - debug TLV types * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV * @IWL_DBG_TLV_TYPE_HCMD: host command TLV * @IWL_DBG_TLV_TYPE_REGION: region TLV * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs */ enum iwl_dbg_tlv_type { IWL_DBG_TLV_TYPE_DEBUG_INFO = IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, IWL_DBG_TLV_TYPE_BUF_ALLOC, IWL_DBG_TLV_TYPE_HCMD, IWL_DBG_TLV_TYPE_REGION, IWL_DBG_TLV_TYPE_TRIGGER, IWL_DBG_TLV_TYPE_CONF_SET, IWL_DBG_TLV_TYPE_NUM, }; /** * struct iwl_dbg_tlv_ver_data - debug TLV version struct * @min_ver: min version supported * @max_ver: max version supported */ struct iwl_dbg_tlv_ver_data { int min_ver; int max_ver; }; /** * struct iwl_dbg_tlv_timer_node - timer node struct * @list: list of &struct iwl_dbg_tlv_timer_node * @timer: timer * @fwrt: &struct iwl_fw_runtime * @tlv: TLV attach to the timer node */ struct iwl_dbg_tlv_timer_node { struct list_head list; struct timer_list timer; struct iwl_fw_runtime *fwrt; struct iwl_ucode_tlv *tlv; }; static const struct iwl_dbg_tlv_ver_data dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 3,}, [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,}, }; static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv, struct list_head *list) { u32 len = le32_to_cpu(tlv->length); struct iwl_dbg_tlv_node *node; node = kzalloc(sizeof(*node) + len, GFP_KERNEL); if (!node) return -ENOMEM; memcpy(&node->tlv, tlv, sizeof(node->tlv)); memcpy(node->tlv.data, tlv->data, len); list_add_tail(&node->list, list); return 0; } static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv) { const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; u32 type = le32_to_cpu(tlv->type); u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; u32 ver = le32_to_cpu(hdr->version); if (ver < dbg_ver_table[tlv_idx].min_ver || ver > dbg_ver_table[tlv_idx].max_ver) return false; return true; } static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv) { const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data; if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) return -EINVAL; IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", debug_info->debug_cfg_name); return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); } static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv) { const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data; u32 buf_location; u32 alloc_id; if (le32_to_cpu(tlv->length) != sizeof(*alloc)) return -EINVAL; buf_location = le32_to_cpu(alloc->buf_location); alloc_id = le32_to_cpu(alloc->alloc_id); if (buf_location == IWL_FW_INI_LOCATION_INVALID || buf_location >= IWL_FW_INI_LOCATION_NUM) goto err; if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || alloc_id >= IWL_FW_INI_ALLOCATION_NUM) goto err; if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH && alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) goto err; if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) goto err; trans->dbg.fw_mon_cfg[alloc_id] = *alloc; return 0; err: IWL_ERR(trans, "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", alloc_id, buf_location); return -EINVAL; } static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv) { const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data; u32 tp = le32_to_cpu(hcmd->time_point); if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) return -EINVAL; /* Host commands can not be sent in early time point since the FW * is not ready */ if (tp == IWL_FW_INI_TIME_POINT_INVALID || tp >= IWL_FW_INI_TIME_POINT_NUM || tp == IWL_FW_INI_TIME_POINT_EARLY) { IWL_ERR(trans, "WRT: Invalid time point %u for host command TLV\n", tp); return -EINVAL; } return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); } static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv) { const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data; struct iwl_ucode_tlv **active_reg; u32 id = le32_to_cpu(reg->id); u8 type = reg->type; u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); /* * The higher part of the ID from version 2 is debug policy. * The id will be only lsb 16 bits, so mask it out. */ if (le32_to_cpu(reg->hdr.version) >= 2) id &= IWL_FW_INI_REGION_ID_MASK; if (le32_to_cpu(tlv->length) < sizeof(*reg)) return -EINVAL; /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */ IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n", IWL_FW_INI_MAX_NAME, reg->name); if (id >= IWL_FW_INI_MAX_REGION_ID) { IWL_ERR(trans, "WRT: Invalid region id %u\n", id); return -EINVAL; } if (type <= IWL_FW_INI_REGION_INVALID || type >= IWL_FW_INI_REGION_NUM) { IWL_ERR(trans, "WRT: Invalid region type %u\n", type); return -EINVAL; } if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG && !trans->ops->read_config32) { IWL_ERR(trans, "WRT: Unsupported region type %u\n", type); return -EOPNOTSUPP; } if (type == IWL_FW_INI_REGION_INTERNAL_BUFFER) { trans->dbg.imr_data.sram_addr = le32_to_cpu(reg->internal_buffer.base_addr); trans->dbg.imr_data.sram_size = le32_to_cpu(reg->internal_buffer.size); } active_reg = &trans->dbg.active_regions[id]; if (*active_reg) { IWL_WARN(trans, "WRT: Overriding region id %u\n", id); kfree(*active_reg); } *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); if (!*active_reg) return -ENOMEM; IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); return 0; } static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv) { const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data; struct iwl_fw_ini_trigger_tlv *dup_trig; u32 tp = le32_to_cpu(trig->time_point); u32 rf = le32_to_cpu(trig->reset_fw); struct iwl_ucode_tlv *dup = NULL; int ret; if (le32_to_cpu(tlv->length) < sizeof(*trig)) return -EINVAL; if (tp <= IWL_FW_INI_TIME_POINT_INVALID || tp >= IWL_FW_INI_TIME_POINT_NUM) { IWL_ERR(trans, "WRT: Invalid time point %u for trigger TLV\n", tp); return -EINVAL; } IWL_DEBUG_FW(trans, "WRT: time point %u for trigger TLV with reset_fw %u\n", tp, rf); trans->dbg.last_tp_resetfw = 0xFF; if (!le32_to_cpu(trig->occurrences)) { dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length), GFP_KERNEL); if (!dup) return -ENOMEM; dup_trig = (void *)dup->data; dup_trig->occurrences = cpu_to_le32(-1); tlv = dup; } ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); kfree(dup); return ret; } static int iwl_dbg_tlv_config_set(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv) { const struct iwl_fw_ini_conf_set_tlv *conf_set = (const void *)tlv->data; u32 tp = le32_to_cpu(conf_set->time_point); u32 type = le32_to_cpu(conf_set->set_type); if (tp <= IWL_FW_INI_TIME_POINT_INVALID || tp >= IWL_FW_INI_TIME_POINT_NUM) { IWL_DEBUG_FW(trans, "WRT: Invalid time point %u for config set TLV\n", tp); return -EINVAL; } if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID || type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) { IWL_DEBUG_FW(trans, "WRT: Invalid config set type %u for config set TLV\n", type); return -EINVAL; } return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list); } static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv) = { [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set, }; void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv, bool ext) { enum iwl_ini_cfg_state *cfg_state = ext ? &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; u32 type; u32 tlv_idx; u32 domain; int ret; if (le32_to_cpu(tlv->length) < sizeof(*hdr)) return; type = le32_to_cpu(tlv->type); tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; domain = le32_to_cpu(hdr->domain); if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && !(domain & trans->dbg.domains_bitmap)) { IWL_DEBUG_FW(trans, "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", domain, trans->dbg.domains_bitmap); return; } if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); goto out_err; } if (!iwl_dbg_tlv_ver_support(tlv)) { IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, le32_to_cpu(hdr->version)); goto out_err; } ret = dbg_tlv_alloc[tlv_idx](trans, tlv); if (ret) { IWL_ERR(trans, "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", type, ret, ext); goto out_err; } if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) *cfg_state = IWL_INI_CFG_STATE_LOADED; return; out_err: *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; } void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) { struct list_head *timer_list = &trans->dbg.periodic_trig_list; struct iwl_dbg_tlv_timer_node *node, *tmp; list_for_each_entry_safe(node, tmp, timer_list, list) { - del_timer(&node->timer); + del_timer_sync(&node->timer); list_del(&node->list); kfree(node); } } IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, enum iwl_fw_ini_allocation_id alloc_id) { struct iwl_fw_mon *fw_mon; int i; if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || alloc_id >= IWL_FW_INI_ALLOCATION_NUM) return; fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; for (i = 0; i < fw_mon->num_frags; i++) { struct iwl_dram_data *frag = &fw_mon->frags[i]; dma_free_coherent(trans->dev, frag->size, frag->block, frag->physical); frag->physical = 0; frag->block = NULL; frag->size = 0; } kfree(fw_mon->frags); fw_mon->frags = NULL; fw_mon->num_frags = 0; } void iwl_dbg_tlv_free(struct iwl_trans *trans) { struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; int i; iwl_dbg_tlv_del_timers(trans); for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { struct iwl_ucode_tlv **active_reg = &trans->dbg.active_regions[i]; kfree(*active_reg); *active_reg = NULL; } list_for_each_entry_safe(tlv_node, tlv_node_tmp, &trans->dbg.debug_info_tlv_list, list) { list_del(&tlv_node->list); kfree(tlv_node); } for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { struct iwl_dbg_tlv_time_point_data *tp = &trans->dbg.time_point[i]; list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, list) { list_del(&tlv_node->list); kfree(tlv_node); } list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, list) { list_del(&tlv_node->list); kfree(tlv_node); } list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->active_trig_list, list) { list_del(&tlv_node->list); kfree(tlv_node); } list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->config_list, list) { list_del(&tlv_node->list); kfree(tlv_node); } } for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) iwl_dbg_tlv_fragments_free(trans, i); } static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, size_t len) { const struct iwl_ucode_tlv *tlv; u32 tlv_len; while (len >= sizeof(*tlv)) { len -= sizeof(*tlv); tlv = (const void *)data; tlv_len = le32_to_cpu(tlv->length); if (len < tlv_len) { IWL_ERR(trans, "invalid TLV len: %zd/%u\n", len, tlv_len); return -EINVAL; } len -= ALIGN(tlv_len, 4); data += sizeof(*tlv) + ALIGN(tlv_len, 4); iwl_dbg_tlv_alloc(trans, tlv, true); } return 0; } void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) { const struct firmware *fw; const char *yoyo_bin = "iwl-debug-yoyo.bin"; int res; if (!iwlwifi_mod_params.enable_ini || trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_8000) return; res = firmware_request_nowarn(&fw, yoyo_bin, dev); IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin); if (res) return; iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); release_firmware(fw); } void iwl_dbg_tlv_init(struct iwl_trans *trans) { int i; INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { struct iwl_dbg_tlv_time_point_data *tp = &trans->dbg.time_point[i]; INIT_LIST_HEAD(&tp->trig_list); INIT_LIST_HEAD(&tp->hcmd_list); INIT_LIST_HEAD(&tp->active_trig_list); INIT_LIST_HEAD(&tp->config_list); } } static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, struct iwl_dram_data *frag, u32 pages) { void *block = NULL; dma_addr_t physical; if (!frag || frag->size || !pages) return -EIO; /* * We try to allocate as many pages as we can, starting with * the requested amount and going down until we can allocate * something. Because of DIV_ROUND_UP(), pages will never go * down to 0 and stop the loop, so stop when pages reaches 1, * which is too small anyway. */ while (pages > 1) { block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, &physical, GFP_KERNEL | __GFP_NOWARN); if (block) break; IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", pages * PAGE_SIZE); pages = DIV_ROUND_UP(pages, 2); } if (!block) return -ENOMEM; frag->physical = physical; frag->block = block; frag->size = pages * PAGE_SIZE; return pages; } static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, enum iwl_fw_ini_allocation_id alloc_id) { struct iwl_fw_mon *fw_mon; struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; u32 num_frags, remain_pages, frag_pages; int i; if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || alloc_id >= IWL_FW_INI_ALLOCATION_NUM) return -EIO; fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; if (fw_mon->num_frags || fw_mon_cfg->buf_location != cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) return 0; num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) return -EIO; num_frags = 1; } remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), PAGE_SIZE); num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); num_frags = min_t(u32, num_frags, remain_pages); frag_pages = DIV_ROUND_UP(remain_pages, num_frags); fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); if (!fw_mon->frags) return -ENOMEM; for (i = 0; i < num_frags; i++) { int pages = min_t(u32, frag_pages, remain_pages); IWL_DEBUG_FW(fwrt, "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", alloc_id, i, pages * PAGE_SIZE); pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], pages); if (pages < 0) { u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - (remain_pages * PAGE_SIZE); if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { iwl_dbg_tlv_fragments_free(fwrt->trans, alloc_id); return pages; } break; } remain_pages -= pages; fw_mon->num_frags++; } return 0; } static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, enum iwl_fw_ini_allocation_id alloc_id) { struct iwl_fw_mon *fw_mon; u32 remain_frags, num_commands; int i, fw_mon_idx = 0; if (!fw_has_capa(&fwrt->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) return 0; if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || alloc_id >= IWL_FW_INI_ALLOCATION_NUM) return -EIO; if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != IWL_FW_INI_LOCATION_DRAM_PATH) return 0; fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; /* the first fragment of DBGC1 is given to the FW via register * or context info */ if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) fw_mon_idx++; remain_frags = fw_mon->num_frags - fw_mon_idx; if (!remain_frags) return 0; num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", alloc_id); for (i = 0; i < num_commands; i++) { u32 num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); struct iwl_buf_alloc_cmd data = { .alloc_id = cpu_to_le32(alloc_id), .num_frags = cpu_to_le32(num_frags), .buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), }; struct iwl_host_cmd hcmd = { .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), .data[0] = &data, .len[0] = sizeof(data), .flags = CMD_SEND_IN_RFKILL, }; int ret, j; for (j = 0; j < num_frags; j++) { struct iwl_buf_alloc_frag *frag = &data.frags[j]; struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++]; frag->addr = cpu_to_le64(fw_mon_frag->physical); frag->size = cpu_to_le32(fw_mon_frag->size); } ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); if (ret) return ret; remain_frags -= num_frags; } return 0; } static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) { int ret, i; if (fw_has_capa(&fwrt->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) return; for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { ret = iwl_dbg_tlv_apply_buffer(fwrt, i); if (ret) IWL_WARN(fwrt, "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", i, ret); } } static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt, enum iwl_fw_ini_allocation_id alloc_id, struct iwl_dram_info *dram_info) { struct iwl_fw_mon *fw_mon; u32 remain_frags, num_frags; int j, fw_mon_idx = 0; struct iwl_buf_alloc_cmd *data; if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != IWL_FW_INI_LOCATION_DRAM_PATH) { IWL_DEBUG_FW(fwrt, "DRAM_PATH is not supported alloc_id %u\n", alloc_id); return -1; } fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; /* the first fragment of DBGC1 is given to the FW via register * or context info */ if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) fw_mon_idx++; remain_frags = fw_mon->num_frags - fw_mon_idx; if (!remain_frags) return -1; num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); data = &dram_info->dram_frags[alloc_id - 1]; data->alloc_id = cpu_to_le32(alloc_id); data->num_frags = cpu_to_le32(num_frags); data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH); IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n", cpu_to_le32(alloc_id), cpu_to_le32(num_frags)); for (j = 0; j < num_frags; j++) { struct iwl_buf_alloc_frag *frag = &data->frags[j]; struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++]; frag->addr = cpu_to_le64(fw_mon_frag->physical); frag->size = cpu_to_le32(fw_mon_frag->size); IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n"); IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n", j, cpu_to_le64(fw_mon_frag->physical), cpu_to_le32(fw_mon_frag->size)); } return 0; } static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt) { int ret, i; bool dram_alloc = false; struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0]; struct iwl_dram_info *dram_info; if (!frags || !frags->block) return; dram_info = frags->block; if (!fw_has_capa(&fwrt->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) return; dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD); dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD); for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1; i <= IWL_FW_INI_ALLOCATION_ID_DBGC3; i++) { ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info); if (!ret) dram_alloc = true; else IWL_WARN(fwrt, "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n", i, ret); } if (dram_alloc) IWL_DEBUG_FW(fwrt, "block data after %08x\n", dram_info->first_word); else memset(frags->block, 0, sizeof(*dram_info)); } static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, struct list_head *hcmd_list) { struct iwl_dbg_tlv_node *node; list_for_each_entry(node, hcmd_list, list) { struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); struct iwl_host_cmd cmd = { .id = WIDE_ID(hcmd_data->group, hcmd_data->id), .len = { hcmd_len, }, .data = { hcmd_data->data, }, }; iwl_trans_send_cmd(fwrt->trans, &cmd); } } static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt, struct list_head *conf_list) { struct iwl_dbg_tlv_node *node; list_for_each_entry(node, conf_list, list) { struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data; u32 count, address, value; u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8; u32 type = le32_to_cpu(config_list->set_type); u32 offset = le32_to_cpu(config_list->addr_offset); switch (type) { case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: { if (!iwl_trans_grab_nic_access(fwrt->trans)) { IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n"); IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n"); continue; } IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len); for (count = 0; count < len; count++) { address = le32_to_cpu(config_list->addr_val[count].address); value = le32_to_cpu(config_list->addr_val[count].value); iwl_trans_write_prph(fwrt->trans, address + offset, value); } iwl_trans_release_nic_access(fwrt->trans); break; } case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: { for (count = 0; count < len; count++) { address = le32_to_cpu(config_list->addr_val[count].address); value = le32_to_cpu(config_list->addr_val[count].value); iwl_trans_write_mem32(fwrt->trans, address + offset, value); IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n", count, address, value); } break; } case IWL_FW_INI_CONFIG_SET_TYPE_CSR: { for (count = 0; count < len; count++) { address = le32_to_cpu(config_list->addr_val[count].address); value = le32_to_cpu(config_list->addr_val[count].value); iwl_write32(fwrt->trans, address + offset, value); IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n", count, address, value); } break; } case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: { struct iwl_dbgc1_info dram_info = {}; struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0]; __le64 dram_base_addr; __le32 dram_size; u64 dram_addr; u32 ret; if (!frags) break; dram_base_addr = cpu_to_le64(frags->physical); dram_size = cpu_to_le32(frags->size); dram_addr = le64_to_cpu(dram_base_addr); IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n", dram_base_addr, dram_size); IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n", le32_to_cpu(config_list->addr_offset)); for (count = 0; count < len; count++) { address = le32_to_cpu(config_list->addr_val[count].address); dram_info.dbgc1_add_lsb = cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400); dram_info.dbgc1_add_msb = cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32); dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400); ret = iwl_trans_write_mem(fwrt->trans, address + offset, &dram_info, 4); if (ret) { IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n"); break; } } break; } case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: { u32 debug_token_config = le32_to_cpu(config_list->addr_val[0].value); IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n", debug_token_config); fwrt->trans->dbg.ucode_preset = debug_token_config; break; } default: break; } } } static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) { struct iwl_dbg_tlv_timer_node *timer_node = from_timer(timer_node, t, timer); struct iwl_fwrt_dump_data dump_data = { .trig = (void *)timer_node->tlv->data, }; int ret; ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false); if (!ret || ret == -EBUSY) { u32 occur = le32_to_cpu(dump_data.trig->occurrences); u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); if (!occur) return; mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); } } static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) { struct iwl_dbg_tlv_node *node; struct list_head *trig_list = &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; list_for_each_entry(node, trig_list, list) { struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; struct iwl_dbg_tlv_timer_node *timer_node; u32 occur = le32_to_cpu(trig->occurrences), collect_interval; u32 min_interval = 100; if (!occur) continue; /* make sure there is at least one dword of data for the * interval value */ if (le32_to_cpu(node->tlv.length) < sizeof(*trig) + sizeof(__le32)) { IWL_ERR(fwrt, "WRT: Invalid periodic trigger data was not given\n"); continue; } if (le32_to_cpu(trig->data[0]) < min_interval) { IWL_WARN(fwrt, "WRT: Override min interval from %u to %u msec\n", le32_to_cpu(trig->data[0]), min_interval); trig->data[0] = cpu_to_le32(min_interval); } collect_interval = le32_to_cpu(trig->data[0]); timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); if (!timer_node) { IWL_ERR(fwrt, "WRT: Failed to allocate periodic trigger\n"); continue; } timer_node->fwrt = fwrt; timer_node->tlv = &node->tlv; timer_setup(&timer_node->timer, iwl_dbg_tlv_periodic_trig_handler, 0); list_add_tail(&timer_node->list, &fwrt->trans->dbg.periodic_trig_list); IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); mod_timer(&timer_node->timer, jiffies + msecs_to_jiffies(collect_interval)); } } static bool is_trig_data_contained(const struct iwl_ucode_tlv *new, const struct iwl_ucode_tlv *old) { const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data; const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data; const __le32 *new_data = new_trig->data, *old_data = old_trig->data; u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data); int i, j; for (i = 0; i < new_dwords_num; i++) { bool match = false; for (j = 0; j < old_dwords_num; j++) { if (new_data[i] == old_data[j]) { match = true; break; } } if (!match) return false; } return true; } static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, struct iwl_ucode_tlv *trig_tlv, struct iwl_dbg_tlv_node *node) { struct iwl_ucode_tlv *node_tlv = &node->tlv; struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; u32 policy = le32_to_cpu(trig->apply_policy); u32 size = le32_to_cpu(trig_tlv->length); u32 trig_data_len = size - sizeof(*trig); u32 offset = 0; if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { u32 data_len = le32_to_cpu(node_tlv->length) - sizeof(*node_trig); IWL_DEBUG_FW(fwrt, "WRT: Appending trigger data (time point %u)\n", le32_to_cpu(trig->time_point)); offset += data_len; size += data_len; } else { IWL_DEBUG_FW(fwrt, "WRT: Overriding trigger data (time point %u)\n", le32_to_cpu(trig->time_point)); } if (size != le32_to_cpu(node_tlv->length)) { struct list_head *prev = node->list.prev; struct iwl_dbg_tlv_node *tmp; list_del(&node->list); tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); if (!tmp) { IWL_WARN(fwrt, "WRT: No memory to override trigger (time point %u)\n", le32_to_cpu(trig->time_point)); list_add(&node->list, prev); return -ENOMEM; } list_add(&tmp->list, prev); node_tlv = &tmp->tlv; node_trig = (void *)node_tlv->data; } memcpy(node_trig->data + offset, trig->data, trig_data_len); node_tlv->length = cpu_to_le32(size); if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { IWL_DEBUG_FW(fwrt, "WRT: Overriding trigger configuration (time point %u)\n", le32_to_cpu(trig->time_point)); /* the first 11 dwords are configuration related */ memcpy(node_trig, trig, sizeof(__le32) * 11); } if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { IWL_DEBUG_FW(fwrt, "WRT: Overriding trigger regions (time point %u)\n", le32_to_cpu(trig->time_point)); node_trig->regions_mask = trig->regions_mask; } else { IWL_DEBUG_FW(fwrt, "WRT: Appending trigger regions (time point %u)\n", le32_to_cpu(trig->time_point)); node_trig->regions_mask |= trig->regions_mask; } return 0; } static int iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, struct list_head *trig_list, struct iwl_ucode_tlv *trig_tlv) { struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; struct iwl_dbg_tlv_node *node, *match = NULL; u32 policy = le32_to_cpu(trig->apply_policy); list_for_each_entry(node, trig_list, list) { if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) break; if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || is_trig_data_contained(trig_tlv, &node->tlv)) { match = node; break; } } if (!match) { IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", le32_to_cpu(trig->time_point)); return iwl_dbg_tlv_add(trig_tlv, trig_list); } return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); } static void iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, struct iwl_dbg_tlv_time_point_data *tp) { struct iwl_dbg_tlv_node *node; struct list_head *trig_list = &tp->trig_list; struct list_head *active_trig_list = &tp->active_trig_list; list_for_each_entry(node, trig_list, list) { struct iwl_ucode_tlv *tlv = &node->tlv; iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); } } static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, struct iwl_fwrt_dump_data *dump_data, union iwl_dbg_tlv_tp_data *tp_data, u32 trig_data) { struct iwl_rx_packet *pkt = tp_data->fw_pkt; struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd && pkt->hdr.group_id == wanted_hdr->group_id)) { struct iwl_rx_packet *fw_pkt = kmemdup(pkt, sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), GFP_ATOMIC); if (!fw_pkt) return false; dump_data->fw_pkt = fw_pkt; return true; } return false; } static int iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync, struct list_head *active_trig_list, union iwl_dbg_tlv_tp_data *tp_data, bool (*data_check)(struct iwl_fw_runtime *fwrt, struct iwl_fwrt_dump_data *dump_data, union iwl_dbg_tlv_tp_data *tp_data, u32 trig_data)) { struct iwl_dbg_tlv_node *node; list_for_each_entry(node, active_trig_list, list) { struct iwl_fwrt_dump_data dump_data = { .trig = (void *)node->tlv.data, }; u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, data); int ret, i; u32 tp = le32_to_cpu(dump_data.trig->time_point); if (!num_data) { ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); if (ret) return ret; } for (i = 0; i < num_data; i++) { if (!data_check || data_check(fwrt, &dump_data, tp_data, le32_to_cpu(dump_data.trig->data[i]))) { ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); if (ret) return ret; break; } } fwrt->trans->dbg.restart_required = FALSE; IWL_DEBUG_INFO(fwrt, "WRT: tp %d, reset_fw %d\n", tp, dump_data.trig->reset_fw); IWL_DEBUG_INFO(fwrt, "WRT: restart_required %d, last_tp_resetfw %d\n", fwrt->trans->dbg.restart_required, fwrt->trans->dbg.last_tp_resetfw); if (fwrt->trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_9000) { fwrt->trans->dbg.restart_required = TRUE; } else if (tp == IWL_FW_INI_TIME_POINT_FW_ASSERT && fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { fwrt->trans->dbg.restart_required = FALSE; fwrt->trans->dbg.last_tp_resetfw = 0xFF; IWL_DEBUG_FW(fwrt, "WRT: FW_ASSERT due to reset_fw_mode-no restart\n"); } else if (le32_to_cpu(dump_data.trig->reset_fw) == IWL_FW_INI_RESET_FW_MODE_STOP_AND_RELOAD_FW) { IWL_DEBUG_INFO(fwrt, "WRT: stop and reload firmware\n"); fwrt->trans->dbg.restart_required = TRUE; } else if (le32_to_cpu(dump_data.trig->reset_fw) == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { IWL_DEBUG_INFO(fwrt, "WRT: stop only and no reload firmware\n"); fwrt->trans->dbg.restart_required = FALSE; fwrt->trans->dbg.last_tp_resetfw = le32_to_cpu(dump_data.trig->reset_fw); } else if (le32_to_cpu(dump_data.trig->reset_fw) == IWL_FW_INI_RESET_FW_MODE_NOTHING) { IWL_DEBUG_INFO(fwrt, "WRT: nothing need to be done after debug collection\n"); } else { IWL_ERR(fwrt, "WRT: wrong resetfw %d\n", le32_to_cpu(dump_data.trig->reset_fw)); } } return 0; } static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) { enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; int ret, i; u32 failed_alloc = 0; if (*ini_dest != IWL_FW_INI_LOCATION_INVALID) return; IWL_DEBUG_FW(fwrt, "WRT: Generating active triggers list, domain 0x%x\n", fwrt->trans->dbg.domains_bitmap); for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { struct iwl_dbg_tlv_time_point_data *tp = &fwrt->trans->dbg.time_point[i]; iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); } *ini_dest = IWL_FW_INI_LOCATION_INVALID; for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[i]; u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); if (dest == IWL_FW_INI_LOCATION_INVALID) { failed_alloc |= BIT(i); continue; } if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) *ini_dest = dest; if (dest != *ini_dest) continue; ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); if (ret) { IWL_WARN(fwrt, "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", i, ret); failed_alloc |= BIT(i); } } if (!failed_alloc) return; for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) { struct iwl_fw_ini_region_tlv *reg; struct iwl_ucode_tlv **active_reg = &fwrt->trans->dbg.active_regions[i]; u32 reg_type; if (!*active_reg) { fwrt->trans->dbg.unsupported_region_msk |= BIT(i); continue; } reg = (void *)(*active_reg)->data; reg_type = reg->type; if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER || !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc)) continue; IWL_DEBUG_FW(fwrt, "WRT: removing allocation id %d from region id %d\n", le32_to_cpu(reg->dram_alloc_id), i); failed_alloc &= ~le32_to_cpu(reg->dram_alloc_id); fwrt->trans->dbg.unsupported_region_msk |= BIT(i); kfree(*active_reg); *active_reg = NULL; } } void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, enum iwl_fw_ini_time_point tp_id, union iwl_dbg_tlv_tp_data *tp_data, bool sync) { struct list_head *hcmd_list, *trig_list, *conf_list; if (!iwl_trans_dbg_ini_valid(fwrt->trans) || tp_id == IWL_FW_INI_TIME_POINT_INVALID || tp_id >= IWL_FW_INI_TIME_POINT_NUM) return; hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list; switch (tp_id) { case IWL_FW_INI_TIME_POINT_EARLY: iwl_dbg_tlv_init_cfg(fwrt); iwl_dbg_tlv_apply_config(fwrt, conf_list); iwl_dbg_tlv_update_drams(fwrt); iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); break; case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: iwl_dbg_tlv_apply_buffers(fwrt); iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); iwl_dbg_tlv_apply_config(fwrt, conf_list); iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); break; case IWL_FW_INI_TIME_POINT_PERIODIC: iwl_dbg_tlv_set_periodic_trigs(fwrt); iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); break; case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION: iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); iwl_dbg_tlv_apply_config(fwrt, conf_list); iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, iwl_dbg_tlv_check_fw_pkt); break; default: iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); iwl_dbg_tlv_apply_config(fwrt, conf_list); iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); break; } } IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point); diff --git a/sys/contrib/dev/iwlwifi/mvm/fw.c b/sys/contrib/dev/iwlwifi/mvm/fw.c index 747d03471f0d..766bd7c7f9cf 100644 --- a/sys/contrib/dev/iwlwifi/mvm/fw.c +++ b/sys/contrib/dev/iwlwifi/mvm/fw.c @@ -1,1742 +1,1743 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* * Copyright (C) 2012-2014, 2018-2022 Intel Corporation * Copyright (C) 2013-2015 Intel Mobile Communications GmbH * Copyright (C) 2016-2017 Intel Deutschland GmbH */ #include #include #include #include "iwl-trans.h" #include "iwl-op-mode.h" #include "fw/img.h" #include "iwl-debug.h" #include "iwl-prph.h" #include "fw/acpi.h" #include "fw/pnvm.h" #include "mvm.h" #include "fw/dbg.h" #include "iwl-phy-db.h" #include "iwl-modparams.h" #include "iwl-nvm-parse.h" #define MVM_UCODE_ALIVE_TIMEOUT (HZ) #define MVM_UCODE_CALIB_TIMEOUT (2 * HZ) #define IWL_TAS_US_MCC 0x5553 #define IWL_TAS_CANADA_MCC 0x4341 struct iwl_mvm_alive_data { bool valid; u32 scd_base_addr; }; static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) { struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { .valid = cpu_to_le32(valid_tx_ant), }; IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, sizeof(tx_ant_cmd), &tx_ant_cmd); } static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) { int i; struct iwl_rss_config_cmd cmd = { .flags = cpu_to_le32(IWL_RSS_ENABLE), .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) | BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) | BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) | BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) | BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) | BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD), }; if (mvm->trans->num_rx_queues == 1) return 0; /* Do not direct RSS traffic to Q 0 which is our fallback queue */ for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) cmd.indirection_table[i] = 1 + (i % (mvm->trans->num_rx_queues - 1)); netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key)); return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); } static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm) { struct iwl_dqa_enable_cmd dqa_cmd = { .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE), }; u32 cmd_id = WIDE_ID(DATA_PATH_GROUP, DQA_ENABLE_CMD); int ret; ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); if (ret) IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret); else IWL_DEBUG_FW(mvm, "Working in DQA mode\n"); return ret; } void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm, struct iwl_rx_cmd_buffer *rxb) { struct iwl_rx_packet *pkt = rxb_addr(rxb); struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data; __le32 *dump_data = mfu_dump_notif->data; int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32); int i; if (mfu_dump_notif->index_num == 0) IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n", le32_to_cpu(mfu_dump_notif->assert_id)); for (i = 0; i < n_words; i++) IWL_DEBUG_INFO(mvm, "MFUART assert dump, dword %u: 0x%08x\n", le16_to_cpu(mfu_dump_notif->index_num) * n_words + i, le32_to_cpu(dump_data[i])); } static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, struct iwl_rx_packet *pkt, void *data) { unsigned int pkt_len = iwl_rx_packet_payload_len(pkt); struct iwl_mvm *mvm = container_of(notif_wait, struct iwl_mvm, notif_wait); struct iwl_mvm_alive_data *alive_data = data; struct iwl_umac_alive *umac; struct iwl_lmac_alive *lmac1; struct iwl_lmac_alive *lmac2 = NULL; u16 status; u32 lmac_error_event_table, umac_error_table; u32 version = iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP, UCODE_ALIVE_NTFY, 0); u32 i; if (version == 6) { struct iwl_alive_ntf_v6 *palive; if (pkt_len < sizeof(*palive)) return false; palive = (void *)pkt->data; mvm->trans->dbg.imr_data.imr_enable = le32_to_cpu(palive->imr.enabled); mvm->trans->dbg.imr_data.imr_size = le32_to_cpu(palive->imr.size); mvm->trans->dbg.imr_data.imr2sram_remainbyte = mvm->trans->dbg.imr_data.imr_size; mvm->trans->dbg.imr_data.imr_base_addr = palive->imr.base_addr; mvm->trans->dbg.imr_data.imr_curr_addr = le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr); IWL_DEBUG_FW(mvm, "IMR Enabled: 0x0%x size 0x0%x Address 0x%016llx\n", mvm->trans->dbg.imr_data.imr_enable, mvm->trans->dbg.imr_data.imr_size, le64_to_cpu(mvm->trans->dbg.imr_data.imr_base_addr)); if (!mvm->trans->dbg.imr_data.imr_enable) { for (i = 0; i < ARRAY_SIZE(mvm->trans->dbg.active_regions); i++) { struct iwl_ucode_tlv *reg_tlv; struct iwl_fw_ini_region_tlv *reg; reg_tlv = mvm->trans->dbg.active_regions[i]; if (!reg_tlv) continue; reg = (void *)reg_tlv->data; /* * We have only one DRAM IMR region, so we * can break as soon as we find the first * one. */ if (reg->type == IWL_FW_INI_REGION_DRAM_IMR) { mvm->trans->dbg.unsupported_region_msk |= BIT(i); break; } } } } if (version >= 5) { struct iwl_alive_ntf_v5 *palive; if (pkt_len < sizeof(*palive)) return false; palive = (void *)pkt->data; umac = &palive->umac_data; lmac1 = &palive->lmac_data[0]; lmac2 = &palive->lmac_data[1]; status = le16_to_cpu(palive->status); mvm->trans->sku_id[0] = le32_to_cpu(palive->sku_id.data[0]); mvm->trans->sku_id[1] = le32_to_cpu(palive->sku_id.data[1]); mvm->trans->sku_id[2] = le32_to_cpu(palive->sku_id.data[2]); IWL_DEBUG_FW(mvm, "Got sku_id: 0x0%x 0x0%x 0x0%x\n", mvm->trans->sku_id[0], mvm->trans->sku_id[1], mvm->trans->sku_id[2]); } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v4)) { struct iwl_alive_ntf_v4 *palive; if (pkt_len < sizeof(*palive)) return false; palive = (void *)pkt->data; umac = &palive->umac_data; lmac1 = &palive->lmac_data[0]; lmac2 = &palive->lmac_data[1]; status = le16_to_cpu(palive->status); } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v3)) { struct iwl_alive_ntf_v3 *palive3; if (pkt_len < sizeof(*palive3)) return false; palive3 = (void *)pkt->data; umac = &palive3->umac_data; lmac1 = &palive3->lmac_data; status = le16_to_cpu(palive3->status); } else { WARN(1, "unsupported alive notification (size %d)\n", iwl_rx_packet_payload_len(pkt)); /* get timeout later */ return false; } lmac_error_event_table = le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr); iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table); if (lmac2) mvm->trans->dbg.lmac_error_event_table[1] = le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr); umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr) & ~FW_ADDR_CACHE_CONTROL; if (umac_error_table) { if (umac_error_table >= mvm->trans->cfg->min_umac_error_event_table) { iwl_fw_umac_set_alive_err_table(mvm->trans, umac_error_table); } else { IWL_ERR(mvm, "Not valid error log pointer 0x%08X for %s uCode\n", umac_error_table, (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ? "Init" : "RT"); } } alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr); alive_data->valid = status == IWL_ALIVE_STATUS_OK; IWL_DEBUG_FW(mvm, "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n", status, lmac1->ver_type, lmac1->ver_subtype); if (lmac2) IWL_DEBUG_FW(mvm, "Alive ucode CDB\n"); IWL_DEBUG_FW(mvm, "UMAC version: Major - 0x%x, Minor - 0x%x\n", le32_to_cpu(umac->umac_major), le32_to_cpu(umac->umac_minor)); iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac); return true; } static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait, struct iwl_rx_packet *pkt, void *data) { WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); return true; } static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, struct iwl_rx_packet *pkt, void *data) { struct iwl_phy_db *phy_db = data; if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); return true; } WARN_ON(iwl_phy_db_set_section(phy_db, pkt)); return false; } static void iwl_mvm_print_pd_notification(struct iwl_mvm *mvm) { struct iwl_trans *trans = mvm->trans; enum iwl_device_family device_family = trans->trans_cfg->device_family; if (device_family < IWL_DEVICE_FAMILY_8000) return; if (device_family <= IWL_DEVICE_FAMILY_9000) IWL_ERR(mvm, "WFPM_ARC1_PD_NOTIFICATION: 0x%x\n", iwl_read_umac_prph(trans, WFPM_ARC1_PD_NOTIFICATION)); else IWL_ERR(mvm, "WFPM_LMAC1_PD_NOTIFICATION: 0x%x\n", iwl_read_umac_prph(trans, WFPM_LMAC1_PD_NOTIFICATION)); IWL_ERR(mvm, "HPM_SECONDARY_DEVICE_STATE: 0x%x\n", iwl_read_umac_prph(trans, HPM_SECONDARY_DEVICE_STATE)); } static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type) { struct iwl_notification_wait alive_wait; struct iwl_mvm_alive_data alive_data = {}; const struct fw_img *fw; int ret; enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img; static const u16 alive_cmd[] = { UCODE_ALIVE_NTFY }; bool run_in_rfkill = ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm); if (ucode_type == IWL_UCODE_REGULAR && iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && !(fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER); else fw = iwl_get_ucode_image(mvm->fw, ucode_type); if (WARN_ON(!fw)) return -EINVAL; iwl_fw_set_current_image(&mvm->fwrt, ucode_type); clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, alive_cmd, ARRAY_SIZE(alive_cmd), iwl_alive_fn, &alive_data); /* * We want to load the INIT firmware even in RFKILL * For the unified firmware case, the ucode_type is not * INIT, but we still need to run it. */ ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill); if (ret) { iwl_fw_set_current_image(&mvm->fwrt, old_type); iwl_remove_notification(&mvm->notif_wait, &alive_wait); return ret; } /* * Some things may run in the background now, but we * just wait for the ALIVE notification here. */ ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, MVM_UCODE_ALIVE_TIMEOUT); if (ret) { struct iwl_trans *trans = mvm->trans; /* SecBoot info */ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) { IWL_ERR(mvm, "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS), iwl_read_umac_prph(trans, UMAG_SB_CPU_2_STATUS)); } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) { IWL_ERR(mvm, "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", iwl_read_prph(trans, SB_CPU_1_STATUS), iwl_read_prph(trans, SB_CPU_2_STATUS)); } iwl_mvm_print_pd_notification(mvm); /* LMAC/UMAC PC info */ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) { IWL_ERR(mvm, "UMAC PC: 0x%x\n", iwl_read_umac_prph(trans, UREG_UMAC_CURRENT_PC)); IWL_ERR(mvm, "LMAC PC: 0x%x\n", iwl_read_umac_prph(trans, UREG_LMAC1_CURRENT_PC)); if (iwl_mvm_is_cdb_supported(mvm)) IWL_ERR(mvm, "LMAC2 PC: 0x%x\n", iwl_read_umac_prph(trans, UREG_LMAC2_CURRENT_PC)); } if (ret == -ETIMEDOUT) iwl_fw_dbg_error_collect(&mvm->fwrt, FW_DBG_TRIGGER_ALIVE_TIMEOUT); iwl_fw_set_current_image(&mvm->fwrt, old_type); return ret; } if (!alive_data.valid) { IWL_ERR(mvm, "Loaded ucode is not valid!\n"); iwl_fw_set_current_image(&mvm->fwrt, old_type); return -EIO; } ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait); if (ret) { IWL_ERR(mvm, "Timeout waiting for PNVM load!\n"); iwl_fw_set_current_image(&mvm->fwrt, old_type); return ret; } iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); /* * Note: all the queues are enabled as part of the interface * initialization, but in firmware restart scenarios they * could be stopped, so wake them up. In firmware restart, * mac80211 will have the queues stopped as well until the * reconfiguration completes. During normal startup, they * will be empty. */ memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); /* * Set a 'fake' TID for the command queue, since we use the * hweight() of the tid_bitmap as a refcount now. Not that * we ever even consider the command queue as one we might * want to reuse, but be safe nevertheless. */ mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap = BIT(IWL_MAX_TID_COUNT + 2); set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); #ifdef CONFIG_IWLWIFI_DEBUGFS iwl_fw_set_dbg_rec_on(&mvm->fwrt); #endif /* * All the BSSes in the BSS table include the GP2 in the system * at the beacon Rx time, this is of course no longer relevant * since we are resetting the firmware. * Purge all the BSS table. */ cfg80211_bss_flush(mvm->hw->wiphy); return 0; } static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm) { struct iwl_notification_wait init_wait; struct iwl_nvm_access_complete_cmd nvm_complete = {}; struct iwl_init_extended_cfg_cmd init_cfg = { .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)), }; static const u16 init_complete[] = { INIT_COMPLETE_NOTIF, }; int ret; if (mvm->trans->cfg->tx_with_siso_diversity) init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY)); lockdep_assert_held(&mvm->mutex); mvm->rfkill_safe_init_done = false; iwl_init_notification_wait(&mvm->notif_wait, &init_wait, init_complete, ARRAY_SIZE(init_complete), iwl_wait_init_complete, NULL); iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); /* Will also start the device */ ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); if (ret) { IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); goto error; } iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, NULL); /* Send init config command to mark that we are sending NVM access * commands */ ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP, INIT_EXTENDED_CFG_CMD), CMD_SEND_IN_RFKILL, sizeof(init_cfg), &init_cfg); if (ret) { IWL_ERR(mvm, "Failed to run init config command: %d\n", ret); goto error; } /* Load NVM to NIC if needed */ if (mvm->nvm_file_name) { ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name, mvm->nvm_sections); if (ret) goto error; ret = iwl_mvm_load_nvm_to_nic(mvm); if (ret) goto error; } if (IWL_MVM_PARSE_NVM && !mvm->nvm_data) { ret = iwl_nvm_init(mvm); if (ret) { IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); goto error; } } ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_ACCESS_COMPLETE), CMD_SEND_IN_RFKILL, sizeof(nvm_complete), &nvm_complete); if (ret) { IWL_ERR(mvm, "Failed to run complete NVM access: %d\n", ret); goto error; } /* We wait for the INIT complete notification */ ret = iwl_wait_notification(&mvm->notif_wait, &init_wait, MVM_UCODE_ALIVE_TIMEOUT); if (ret) return ret; /* Read the NVM only at driver load time, no need to do this twice */ if (!IWL_MVM_PARSE_NVM && !mvm->nvm_data) { mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw); if (IS_ERR(mvm->nvm_data)) { ret = PTR_ERR(mvm->nvm_data); mvm->nvm_data = NULL; IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); return ret; } } mvm->rfkill_safe_init_done = true; return 0; error: iwl_remove_notification(&mvm->notif_wait, &init_wait); return ret; } #ifdef CONFIG_ACPI static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm, struct iwl_phy_specific_cfg *phy_filters) { /* * TODO: read specific phy config from BIOS * ACPI table for this feature has not been defined yet, * so for now we use hardcoded values. */ if (IWL_MVM_PHY_FILTER_CHAIN_A) { phy_filters->filter_cfg_chain_a = cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A); } if (IWL_MVM_PHY_FILTER_CHAIN_B) { phy_filters->filter_cfg_chain_b = cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B); } if (IWL_MVM_PHY_FILTER_CHAIN_C) { phy_filters->filter_cfg_chain_c = cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C); } if (IWL_MVM_PHY_FILTER_CHAIN_D) { phy_filters->filter_cfg_chain_d = cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D); } } #else /* CONFIG_ACPI */ static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm, struct iwl_phy_specific_cfg *phy_filters) { } #endif /* CONFIG_ACPI */ #if defined(CONFIG_ACPI) && defined(CONFIG_EFI) static int iwl_mvm_sgom_init(struct iwl_mvm *mvm) { u8 cmd_ver; int ret; struct iwl_host_cmd cmd = { .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, SAR_OFFSET_MAPPING_TABLE_CMD), .flags = 0, .data[0] = &mvm->fwrt.sgom_table, .len[0] = sizeof(mvm->fwrt.sgom_table), .dataflags[0] = IWL_HCMD_DFL_NOCOPY, }; if (!mvm->fwrt.sgom_enabled) { IWL_DEBUG_RADIO(mvm, "SGOM table is disabled\n"); return 0; } cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id, IWL_FW_CMD_VER_UNKNOWN); if (cmd_ver != 2) { IWL_DEBUG_RADIO(mvm, "command version is unsupported. version = %d\n", cmd_ver); return 0; } ret = iwl_mvm_send_cmd(mvm, &cmd); if (ret < 0) IWL_ERR(mvm, "failed to send SAR_OFFSET_MAPPING_CMD (%d)\n", ret); return ret; } #else static int iwl_mvm_sgom_init(struct iwl_mvm *mvm) { return 0; } #endif static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) { u32 cmd_id = PHY_CONFIGURATION_CMD; struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd; enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img; struct iwl_phy_specific_cfg phy_filters = {}; u8 cmd_ver; size_t cmd_size; if (iwl_mvm_has_unified_ucode(mvm) && !mvm->trans->cfg->tx_with_siso_diversity) return 0; if (mvm->trans->cfg->tx_with_siso_diversity) { /* * TODO: currently we don't set the antenna but letting the NIC * to decide which antenna to use. This should come from BIOS. */ phy_cfg_cmd.phy_cfg = cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED); } /* Set parameters */ phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); /* set flags extra PHY configuration flags from the device's cfg */ phy_cfg_cmd.phy_cfg |= cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags); phy_cfg_cmd.calib_control.event_trigger = mvm->fw->default_calib[ucode_type].event_trigger; phy_cfg_cmd.calib_control.flow_trigger = mvm->fw->default_calib[ucode_type].flow_trigger; cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id, IWL_FW_CMD_VER_UNKNOWN); if (cmd_ver == 3) { iwl_mvm_phy_filter_init(mvm, &phy_filters); memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters, sizeof(struct iwl_phy_specific_cfg)); } IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", phy_cfg_cmd.phy_cfg); cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) : sizeof(struct iwl_phy_cfg_cmd_v1); return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &phy_cfg_cmd); } int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm) { struct iwl_notification_wait calib_wait; static const u16 init_complete[] = { INIT_COMPLETE_NOTIF, CALIB_RES_NOTIF_PHY_DB }; int ret; if (iwl_mvm_has_unified_ucode(mvm)) return iwl_run_unified_mvm_ucode(mvm); lockdep_assert_held(&mvm->mutex); mvm->rfkill_safe_init_done = false; iwl_init_notification_wait(&mvm->notif_wait, &calib_wait, init_complete, ARRAY_SIZE(init_complete), iwl_wait_phy_db_entry, mvm->phy_db); iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); /* Will also start the device */ ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); if (ret) { IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); goto remove_notif; } if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) { ret = iwl_mvm_send_bt_init_conf(mvm); if (ret) goto remove_notif; } /* Read the NVM only at driver load time, no need to do this twice */ if (!mvm->nvm_data) { ret = iwl_nvm_init(mvm); if (ret) { IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); goto remove_notif; } } /* In case we read the NVM from external file, load it to the NIC */ if (mvm->nvm_file_name) { ret = iwl_mvm_load_nvm_to_nic(mvm); if (ret) goto remove_notif; } WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver, "Too old NVM version (0x%0x, required = 0x%0x)", mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver); /* * abort after reading the nvm in case RF Kill is on, we will complete * the init seq later when RF kill will switch to off */ if (iwl_mvm_is_radio_hw_killed(mvm)) { IWL_DEBUG_RF_KILL(mvm, "jump over all phy activities due to RF kill\n"); goto remove_notif; } mvm->rfkill_safe_init_done = true; /* Send TX valid antennas before triggering calibrations */ ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); if (ret) goto remove_notif; ret = iwl_send_phy_cfg_cmd(mvm); if (ret) { IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", ret); goto remove_notif; } /* * Some things may run in the background now, but we * just wait for the calibration complete notification. */ ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, MVM_UCODE_CALIB_TIMEOUT); if (!ret) goto out; if (iwl_mvm_is_radio_hw_killed(mvm)) { IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); ret = 0; } else { IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", ret); } goto out; remove_notif: iwl_remove_notification(&mvm->notif_wait, &calib_wait); out: mvm->rfkill_safe_init_done = false; if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { /* we want to debug INIT and we have no NVM - fake */ mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + sizeof(struct ieee80211_channel) + sizeof(struct ieee80211_rate), GFP_KERNEL); if (!mvm->nvm_data) return -ENOMEM; mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; mvm->nvm_data->bands[0].n_channels = 1; mvm->nvm_data->bands[0].n_bitrates = 1; mvm->nvm_data->bands[0].bitrates = (void *)(mvm->nvm_data->channels + 1); mvm->nvm_data->bands[0].bitrates->hw_value = 10; } return ret; } static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) { struct iwl_ltr_config_cmd cmd = { .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), }; if (!mvm->trans->ltr_enabled) return 0; return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, sizeof(cmd), &cmd); } #ifdef CONFIG_ACPI int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b) { u32 cmd_id = REDUCE_TX_POWER_CMD; struct iwl_dev_tx_power_cmd cmd = { .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS), }; __le16 *per_chain; int ret; u16 len = 0; u32 n_subbands; u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id, IWL_FW_CMD_VER_UNKNOWN); if (cmd_ver == 7) { len = sizeof(cmd.v7); n_subbands = IWL_NUM_SUB_BANDS_V2; per_chain = cmd.v7.per_chain[0][0]; cmd.v7.flags = cpu_to_le32(mvm->fwrt.reduced_power_flags); } else if (cmd_ver == 6) { len = sizeof(cmd.v6); n_subbands = IWL_NUM_SUB_BANDS_V2; per_chain = cmd.v6.per_chain[0][0]; } else if (fw_has_api(&mvm->fw->ucode_capa, IWL_UCODE_TLV_API_REDUCE_TX_POWER)) { len = sizeof(cmd.v5); n_subbands = IWL_NUM_SUB_BANDS_V1; per_chain = cmd.v5.per_chain[0][0]; } else if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) { len = sizeof(cmd.v4); n_subbands = IWL_NUM_SUB_BANDS_V1; per_chain = cmd.v4.per_chain[0][0]; } else { len = sizeof(cmd.v3); n_subbands = IWL_NUM_SUB_BANDS_V1; per_chain = cmd.v3.per_chain[0][0]; } /* all structs have the same common part, add it */ len += sizeof(cmd.common); ret = iwl_sar_select_profile(&mvm->fwrt, per_chain, IWL_NUM_CHAIN_TABLES, n_subbands, prof_a, prof_b); /* return on error or if the profile is disabled (positive number) */ if (ret) return ret; iwl_mei_set_power_limit(per_chain); IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n"); return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd); } int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) { union iwl_geo_tx_power_profiles_cmd geo_tx_cmd; struct iwl_geo_tx_power_profiles_resp *resp; u16 len; int ret; struct iwl_host_cmd cmd = { .id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD), .flags = CMD_WANT_SKB, .data = { &geo_tx_cmd }, }; u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd.id, IWL_FW_CMD_VER_UNKNOWN); /* the ops field is at the same spot for all versions, so set in v1 */ geo_tx_cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE); if (cmd_ver == 5) len = sizeof(geo_tx_cmd.v5); else if (cmd_ver == 4) len = sizeof(geo_tx_cmd.v4); else if (cmd_ver == 3) len = sizeof(geo_tx_cmd.v3); else if (fw_has_api(&mvm->fwrt.fw->ucode_capa, IWL_UCODE_TLV_API_SAR_TABLE_VER)) len = sizeof(geo_tx_cmd.v2); else len = sizeof(geo_tx_cmd.v1); if (!iwl_sar_geo_support(&mvm->fwrt)) return -EOPNOTSUPP; cmd.len[0] = len; ret = iwl_mvm_send_cmd(mvm, &cmd); if (ret) { IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret); return ret; } resp = (void *)cmd.resp_pkt->data; ret = le32_to_cpu(resp->profile_idx); if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES_REV3)) ret = -EIO; iwl_free_resp(&cmd); return ret; } static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) { u32 cmd_id = WIDE_ID(PHY_OPS_GROUP, PER_CHAIN_LIMIT_OFFSET_CMD); union iwl_geo_tx_power_profiles_cmd cmd; u16 len; u32 n_bands; u32 n_profiles; u32 sk = 0; int ret; u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id, IWL_FW_CMD_VER_UNKNOWN); BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, ops) != offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) || offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, ops) != offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) || offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, ops) != offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) || offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, ops) != offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, ops)); /* the ops field is at the same spot for all versions, so set in v1 */ cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES); if (cmd_ver == 5) { len = sizeof(cmd.v5); n_bands = ARRAY_SIZE(cmd.v5.table[0]); n_profiles = ACPI_NUM_GEO_PROFILES_REV3; } else if (cmd_ver == 4) { len = sizeof(cmd.v4); n_bands = ARRAY_SIZE(cmd.v4.table[0]); n_profiles = ACPI_NUM_GEO_PROFILES_REV3; } else if (cmd_ver == 3) { len = sizeof(cmd.v3); n_bands = ARRAY_SIZE(cmd.v3.table[0]); n_profiles = ACPI_NUM_GEO_PROFILES; } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa, IWL_UCODE_TLV_API_SAR_TABLE_VER)) { len = sizeof(cmd.v2); n_bands = ARRAY_SIZE(cmd.v2.table[0]); n_profiles = ACPI_NUM_GEO_PROFILES; } else { len = sizeof(cmd.v1); n_bands = ARRAY_SIZE(cmd.v1.table[0]); n_profiles = ACPI_NUM_GEO_PROFILES; } BUILD_BUG_ON(offsetof(struct iwl_geo_tx_power_profiles_cmd_v1, table) != offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) || offsetof(struct iwl_geo_tx_power_profiles_cmd_v2, table) != offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) || offsetof(struct iwl_geo_tx_power_profiles_cmd_v3, table) != offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) || offsetof(struct iwl_geo_tx_power_profiles_cmd_v4, table) != offsetof(struct iwl_geo_tx_power_profiles_cmd_v5, table)); /* the table is at the same position for all versions, so set use v1 */ ret = iwl_sar_geo_init(&mvm->fwrt, &cmd.v1.table[0][0], n_bands, n_profiles); /* * It is a valid scenario to not support SAR, or miss wgds table, * but in that case there is no need to send the command. */ if (ret) return 0; /* Only set to South Korea if the table revision is 1 */ if (mvm->fwrt.geo_rev == 1) sk = 1; /* * Set the table_revision to South Korea (1) or not (0). The * element name is misleading, as it doesn't contain the table * revision number, but whether the South Korea variation * should be used. * This must be done after calling iwl_sar_geo_init(). */ if (cmd_ver == 5) cmd.v5.table_revision = cpu_to_le32(sk); else if (cmd_ver == 4) cmd.v4.table_revision = cpu_to_le32(sk); else if (cmd_ver == 3) cmd.v3.table_revision = cpu_to_le32(sk); else if (fw_has_api(&mvm->fwrt.fw->ucode_capa, IWL_UCODE_TLV_API_SAR_TABLE_VER)) cmd.v2.table_revision = cpu_to_le32(sk); return iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, len, &cmd); } int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) { union iwl_ppag_table_cmd cmd; int ret, cmd_size; ret = iwl_read_ppag_table(&mvm->fwrt, &cmd, &cmd_size); + /* Not supporting PPAG table is a valid scenario */ if(ret < 0) - return ret; + return 0; IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n"); ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP, PER_PLATFORM_ANT_GAIN_CMD), 0, cmd_size, &cmd); if (ret < 0) IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n", ret); return ret; } static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) { /* no need to read the table, done in INIT stage */ if (!(iwl_acpi_is_ppag_approved(&mvm->fwrt))) return 0; return iwl_mvm_ppag_send_cmd(mvm); } static const struct dmi_system_id dmi_tas_approved_list[] = { { .ident = "HP", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "HP"), }, }, { .ident = "SAMSUNG", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD"), }, }, { .ident = "LENOVO", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Lenovo"), }, }, { .ident = "DELL", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), }, }, /* keep last */ {} }; static bool iwl_mvm_add_to_tas_block_list(__le32 *list, __le32 *le_size, unsigned int mcc) { int i; u32 size = le32_to_cpu(*le_size); /* Verify that there is room for another country */ if (size >= IWL_TAS_BLOCK_LIST_MAX) return false; for (i = 0; i < size; i++) { if (list[i] == cpu_to_le32(mcc)) return true; } list[size++] = cpu_to_le32(mcc); *le_size = cpu_to_le32(size); return true; } static void iwl_mvm_tas_init(struct iwl_mvm *mvm) { u32 cmd_id = WIDE_ID(REGULATORY_AND_NVM_GROUP, TAS_CONFIG); int ret; union iwl_tas_config_cmd cmd = {}; int cmd_size, fw_ver; BUILD_BUG_ON(ARRAY_SIZE(cmd.v3.block_list_array) < APCI_WTAS_BLACK_LIST_MAX); if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) { IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n"); return; } fw_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id, IWL_FW_CMD_VER_UNKNOWN); ret = iwl_acpi_get_tas(&mvm->fwrt, &cmd, fw_ver); if (ret < 0) { IWL_DEBUG_RADIO(mvm, "TAS table invalid or unavailable. (%d)\n", ret); return; } if (ret == 0) return; if (!dmi_check_system(dmi_tas_approved_list)) { IWL_DEBUG_RADIO(mvm, "System vendor '%s' is not in the approved list, disabling TAS in US and Canada.\n", dmi_get_system_info(DMI_SYS_VENDOR)); if ((!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array, &cmd.v4.block_list_size, IWL_TAS_US_MCC)) || (!iwl_mvm_add_to_tas_block_list(cmd.v4.block_list_array, &cmd.v4.block_list_size, IWL_TAS_CANADA_MCC))) { IWL_DEBUG_RADIO(mvm, "Unable to add US/Canada to TAS block list, disabling TAS\n"); return; } } /* v4 is the same size as v3, so no need to differentiate here */ cmd_size = fw_ver < 3 ? sizeof(struct iwl_tas_config_cmd_v2) : sizeof(struct iwl_tas_config_cmd_v3); ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, cmd_size, &cmd); if (ret < 0) IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret); } static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm) { u8 value; int ret = iwl_acpi_get_dsm_u8(mvm->fwrt.dev, 0, DSM_RFI_FUNC_ENABLE, &iwl_rfi_guid, &value); if (ret < 0) { IWL_DEBUG_RADIO(mvm, "Failed to get DSM RFI, ret=%d\n", ret); } else if (value >= DSM_VALUE_RFI_MAX) { IWL_DEBUG_RADIO(mvm, "DSM RFI got invalid value, ret=%d\n", value); } else if (value == DSM_VALUE_RFI_ENABLE) { IWL_DEBUG_RADIO(mvm, "DSM RFI is evaluated to enable\n"); return DSM_VALUE_RFI_ENABLE; } IWL_DEBUG_RADIO(mvm, "DSM RFI is disabled\n"); /* default behaviour is disabled */ return DSM_VALUE_RFI_DISABLE; } static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm) { int ret; u32 value; struct iwl_lari_config_change_cmd_v6 cmd = {}; cmd.config_bitmap = iwl_acpi_get_lari_config_bitmap(&mvm->fwrt); ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0, DSM_FUNC_11AX_ENABLEMENT, &iwl_guid, &value); if (!ret) cmd.oem_11ax_allow_bitmap = cpu_to_le32(value); ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0, DSM_FUNC_ENABLE_UNII4_CHAN, &iwl_guid, &value); if (!ret) cmd.oem_unii4_allow_bitmap = cpu_to_le32(value); ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0, DSM_FUNC_ACTIVATE_CHANNEL, &iwl_guid, &value); if (!ret) cmd.chan_state_active_bitmap = cpu_to_le32(value); ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0, DSM_FUNC_ENABLE_6E, &iwl_guid, &value); if (!ret) cmd.oem_uhb_allow_bitmap = cpu_to_le32(value); ret = iwl_acpi_get_dsm_u32(mvm->fwrt.dev, 0, DSM_FUNC_FORCE_DISABLE_CHANNELS, &iwl_guid, &value); if (!ret) cmd.force_disable_channels_bitmap = cpu_to_le32(value); if (cmd.config_bitmap || cmd.oem_uhb_allow_bitmap || cmd.oem_11ax_allow_bitmap || cmd.oem_unii4_allow_bitmap || cmd.chan_state_active_bitmap || cmd.force_disable_channels_bitmap) { size_t cmd_size; u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, WIDE_ID(REGULATORY_AND_NVM_GROUP, LARI_CONFIG_CHANGE), 1); switch (cmd_ver) { case 6: cmd_size = sizeof(struct iwl_lari_config_change_cmd_v6); break; case 5: cmd_size = sizeof(struct iwl_lari_config_change_cmd_v5); break; case 4: cmd_size = sizeof(struct iwl_lari_config_change_cmd_v4); break; case 3: cmd_size = sizeof(struct iwl_lari_config_change_cmd_v3); break; case 2: cmd_size = sizeof(struct iwl_lari_config_change_cmd_v2); break; default: cmd_size = sizeof(struct iwl_lari_config_change_cmd_v1); break; } IWL_DEBUG_RADIO(mvm, "sending LARI_CONFIG_CHANGE, config_bitmap=0x%x, oem_11ax_allow_bitmap=0x%x\n", le32_to_cpu(cmd.config_bitmap), le32_to_cpu(cmd.oem_11ax_allow_bitmap)); IWL_DEBUG_RADIO(mvm, "sending LARI_CONFIG_CHANGE, oem_unii4_allow_bitmap=0x%x, chan_state_active_bitmap=0x%x, cmd_ver=%d\n", le32_to_cpu(cmd.oem_unii4_allow_bitmap), le32_to_cpu(cmd.chan_state_active_bitmap), cmd_ver); IWL_DEBUG_RADIO(mvm, "sending LARI_CONFIG_CHANGE, oem_uhb_allow_bitmap=0x%x, force_disable_channels_bitmap=0x%x\n", le32_to_cpu(cmd.oem_uhb_allow_bitmap), le32_to_cpu(cmd.force_disable_channels_bitmap)); ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, LARI_CONFIG_CHANGE), 0, cmd_size, &cmd); if (ret < 0) IWL_DEBUG_RADIO(mvm, "Failed to send LARI_CONFIG_CHANGE (%d)\n", ret); } } void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm) { int ret; /* read PPAG table */ ret = iwl_acpi_get_ppag_table(&mvm->fwrt); if (ret < 0) { IWL_DEBUG_RADIO(mvm, "PPAG BIOS table invalid or unavailable. (%d)\n", ret); } /* read SAR tables */ ret = iwl_sar_get_wrds_table(&mvm->fwrt); if (ret < 0) { IWL_DEBUG_RADIO(mvm, "WRDS SAR BIOS table invalid or unavailable. (%d)\n", ret); /* * If not available, don't fail and don't bother with EWRD and * WGDS */ if (!iwl_sar_get_wgds_table(&mvm->fwrt)) { /* * If basic SAR is not available, we check for WGDS, * which should *not* be available either. If it is * available, issue an error, because we can't use SAR * Geo without basic SAR. */ IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n"); } } else { ret = iwl_sar_get_ewrd_table(&mvm->fwrt); /* if EWRD is not available, we can still use * WRDS, so don't fail */ if (ret < 0) IWL_DEBUG_RADIO(mvm, "EWRD SAR BIOS table invalid or unavailable. (%d)\n", ret); /* read geo SAR table */ if (iwl_sar_geo_support(&mvm->fwrt)) { ret = iwl_sar_get_wgds_table(&mvm->fwrt); if (ret < 0) IWL_DEBUG_RADIO(mvm, "Geo SAR BIOS table invalid or unavailable. (%d)\n", ret); /* we don't fail if the table is not available */ } } } #else /* CONFIG_ACPI */ inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b) { return 1; } inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) { return -ENOENT; } static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) { return 0; } int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) { return -ENOENT; } static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) { return 0; } static void iwl_mvm_tas_init(struct iwl_mvm *mvm) { } static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm) { } static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm) { return DSM_VALUE_RFI_DISABLE; } void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm) { } #endif /* CONFIG_ACPI */ void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags) { u32 error_log_size = mvm->fw->ucode_capa.error_log_size; int ret; u32 resp; struct iwl_fw_error_recovery_cmd recovery_cmd = { .flags = cpu_to_le32(flags), .buf_size = 0, }; struct iwl_host_cmd host_cmd = { .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD), .flags = CMD_WANT_SKB, .data = {&recovery_cmd, }, .len = {sizeof(recovery_cmd), }, }; /* no error log was defined in TLV */ if (!error_log_size) return; if (flags & ERROR_RECOVERY_UPDATE_DB) { /* no buf was allocated while HW reset */ if (!mvm->error_recovery_buf) return; host_cmd.data[1] = mvm->error_recovery_buf; host_cmd.len[1] = error_log_size; host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY; recovery_cmd.buf_size = cpu_to_le32(error_log_size); } ret = iwl_mvm_send_cmd(mvm, &host_cmd); kfree(mvm->error_recovery_buf); mvm->error_recovery_buf = NULL; if (ret) { IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret); return; } /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */ if (flags & ERROR_RECOVERY_UPDATE_DB) { resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data); if (resp) IWL_ERR(mvm, "Failed to send recovery cmd blob was invalid %d\n", resp); } } static int iwl_mvm_sar_init(struct iwl_mvm *mvm) { return iwl_mvm_sar_select_profile(mvm, 1, 1); } static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm) { int ret; if (iwl_mvm_has_unified_ucode(mvm)) return iwl_run_unified_mvm_ucode(mvm); ret = iwl_run_init_mvm_ucode(mvm); if (ret) { IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); if (iwlmvm_mod_params.init_dbg) return 0; return ret; } iwl_fw_dbg_stop_sync(&mvm->fwrt); iwl_trans_stop_device(mvm->trans); ret = iwl_trans_start_hw(mvm->trans); if (ret) return ret; mvm->rfkill_safe_init_done = false; ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); if (ret) return ret; mvm->rfkill_safe_init_done = true; iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, NULL); return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img); } int iwl_mvm_up(struct iwl_mvm *mvm) { int ret, i; struct ieee80211_channel *chan; struct cfg80211_chan_def chandef; struct ieee80211_supported_band *sband = NULL; lockdep_assert_held(&mvm->mutex); ret = iwl_trans_start_hw(mvm->trans); if (ret) return ret; ret = iwl_mvm_load_rt_fw(mvm); if (ret) { IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); if (ret != -ERFKILL) iwl_fw_dbg_error_collect(&mvm->fwrt, FW_DBG_TRIGGER_DRIVER); goto error; } iwl_get_shared_mem_conf(&mvm->fwrt); ret = iwl_mvm_sf_update(mvm, NULL, false); if (ret) IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); if (!iwl_trans_dbg_ini_valid(mvm->trans)) { mvm->fwrt.dump.conf = FW_DBG_INVALID; /* if we have a destination, assume EARLY START */ if (mvm->fw->dbg.dest_tlv) mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE; iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE); } ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); if (ret) goto error; if (!iwl_mvm_has_unified_ucode(mvm)) { /* Send phy db control command and then phy db calibration */ ret = iwl_send_phy_db_data(mvm->phy_db); if (ret) goto error; } ret = iwl_send_phy_cfg_cmd(mvm); if (ret) goto error; ret = iwl_mvm_send_bt_init_conf(mvm); if (ret) goto error; if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) { ret = iwl_set_soc_latency(&mvm->fwrt); if (ret) goto error; } /* Init RSS configuration */ ret = iwl_configure_rxq(&mvm->fwrt); if (ret) goto error; if (iwl_mvm_has_new_rx_api(mvm)) { ret = iwl_send_rss_cfg_cmd(mvm); if (ret) { IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", ret); goto error; } } /* init the fw <-> mac80211 STA mapping */ for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA; /* reset quota debouncing buffer - 0xff will yield invalid data */ memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) { ret = iwl_mvm_send_dqa_cmd(mvm); if (ret) goto error; } /* * Add auxiliary station for scanning. * Newer versions of this command implies that the fw uses * internal aux station for all aux activities that don't * requires a dedicated data queue. */ if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) { /* * In old version the aux station uses mac id like other * station and not lmac id */ ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX); if (ret) goto error; } /* Add all the PHY contexts */ i = 0; while (!sband && i < NUM_NL80211_BANDS) sband = mvm->hw->wiphy->bands[i++]; if (WARN_ON_ONCE(!sband)) { ret = -ENODEV; goto error; } chan = &sband->channels[0]; cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); for (i = 0; i < NUM_PHY_CTX; i++) { /* * The channel used here isn't relevant as it's * going to be overwritten in the other flows. * For now use the first channel we have. */ ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], &chandef, 1, 1); if (ret) goto error; } if (iwl_mvm_is_tt_in_fw(mvm)) { /* in order to give the responsibility of ct-kill and * TX backoff to FW we need to send empty temperature reporting * cmd during init time */ iwl_mvm_send_temp_report_ths_cmd(mvm); } else { /* Initialize tx backoffs to the minimal possible */ iwl_mvm_tt_tx_backoff(mvm, 0); } #ifdef CONFIG_THERMAL /* TODO: read the budget from BIOS / Platform NVM */ /* * In case there is no budget from BIOS / Platform NVM the default * budget should be 2000mW (cooling state 0). */ if (iwl_mvm_is_ctdp_supported(mvm)) { ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, mvm->cooling_dev.cur_state); if (ret) goto error; } #endif if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2)) WARN_ON(iwl_mvm_config_ltr(mvm)); ret = iwl_mvm_power_update_device(mvm); if (ret) goto error; iwl_mvm_lari_cfg(mvm); /* * RTNL is not taken during Ct-kill, but we don't need to scan/Tx * anyway, so don't init MCC. */ if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { ret = iwl_mvm_init_mcc(mvm); if (ret) goto error; } if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET; ret = iwl_mvm_config_scan(mvm); if (ret) goto error; } if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB); if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid)) IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n"); ret = iwl_mvm_ppag_init(mvm); if (ret) goto error; ret = iwl_mvm_sar_init(mvm); if (ret == 0) ret = iwl_mvm_sar_geo_init(mvm); if (ret < 0) goto error; ret = iwl_mvm_sgom_init(mvm); if (ret) goto error; iwl_mvm_tas_init(mvm); iwl_mvm_leds_sync(mvm); iwl_mvm_ftm_initiator_smooth_config(mvm); if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_RFIM_SUPPORT)) { if (iwl_mvm_eval_dsm_rfi(mvm) == DSM_VALUE_RFI_ENABLE) iwl_rfi_send_config_cmd(mvm, NULL); } IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); return 0; error: if (!iwlmvm_mod_params.init_dbg || !ret) iwl_mvm_stop_device(mvm); return ret; } int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) { int ret, i; lockdep_assert_held(&mvm->mutex); ret = iwl_trans_start_hw(mvm->trans); if (ret) return ret; ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); if (ret) { IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); goto error; } ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); if (ret) goto error; /* Send phy db control command and then phy db calibration*/ ret = iwl_send_phy_db_data(mvm->phy_db); if (ret) goto error; ret = iwl_send_phy_cfg_cmd(mvm); if (ret) goto error; /* init the fw <-> mac80211 STA mapping */ for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) { /* * Add auxiliary station for scanning. * Newer versions of this command implies that the fw uses * internal aux station for all aux activities that don't * requires a dedicated data queue. * In old version the aux station uses mac id like other * station and not lmac id */ ret = iwl_mvm_add_aux_sta(mvm, MAC_INDEX_AUX); if (ret) goto error; } return 0; error: iwl_mvm_stop_device(mvm); return ret; } void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, struct iwl_rx_cmd_buffer *rxb) { struct iwl_rx_packet *pkt = rxb_addr(rxb); struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; IWL_DEBUG_INFO(mvm, "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", le32_to_cpu(mfuart_notif->installed_ver), le32_to_cpu(mfuart_notif->external_ver), le32_to_cpu(mfuart_notif->status), le32_to_cpu(mfuart_notif->duration)); if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif)) IWL_DEBUG_INFO(mvm, "MFUART: image size: 0x%08x\n", le32_to_cpu(mfuart_notif->image_size)); }