diff --git a/sys/contrib/dev/athk/ath10k/pci.c b/sys/contrib/dev/athk/ath10k/pci.c index 2b0b594b5466..23ff786fe45c 100644 --- a/sys/contrib/dev/athk/ath10k/pci.c +++ b/sys/contrib/dev/athk/ath10k/pci.c @@ -1,3967 +1,3968 @@ // SPDX-License-Identifier: ISC /* * Copyright (c) 2005-2011 Atheros Communications Inc. * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. */ #if defined(__FreeBSD__) #define LINUXKPI_PARAM_PREFIX ath10k_pci_ #endif #include #include #include #include #include #if defined(__FreeBSD__) #include +#include #endif #include "core.h" #include "debug.h" #include "coredump.h" #include "targaddrs.h" #include "bmi.h" #include "hif.h" #include "htc.h" #include "ce.h" #include "pci.h" enum ath10k_pci_reset_mode { ATH10K_PCI_RESET_AUTO = 0, ATH10K_PCI_RESET_WARM_ONLY = 1, }; static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); /* how long wait to wait for target to initialise, in ms */ #define ATH10K_PCI_TARGET_WAIT 3000 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 /* Maximum number of bytes that can be handled atomically by * diag read and write. */ #define ATH10K_DIAG_TRANSFER_LIMIT 0x5000 #define QCA99X0_PCIE_BAR0_START_REG 0x81030 #define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c #define QCA99X0_CPU_MEM_DATA_REG 0x4d010 static const struct pci_device_id ath10k_pci_id_table[] = { /* PCI-E QCA988X V2 (Ubiquiti branded) */ { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) }, { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */ { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */ { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */ { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */ {0} }; static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { /* QCA988X pre 2.0 chips are not supported because they need some nasty * hacks. ath10k doesn't have them and these devices crash horribly * because of that. */ { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV }, { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV }, { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV }, { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV }, { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV }, }; static void ath10k_pci_buffer_cleanup(struct ath10k *ar); static int ath10k_pci_cold_reset(struct ath10k *ar); static int ath10k_pci_safe_chip_reset(struct ath10k *ar); static int ath10k_pci_init_irq(struct ath10k *ar); static int ath10k_pci_deinit_irq(struct ath10k *ar); static int ath10k_pci_request_irq(struct ath10k *ar); static void ath10k_pci_free_irq(struct ath10k *ar); static int ath10k_pci_bmi_wait(struct ath10k *ar, struct ath10k_ce_pipe *tx_pipe, struct ath10k_ce_pipe *rx_pipe, struct bmi_xfer *xfer); static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); static const struct ce_attr pci_host_ce_config_wlan[] = { /* CE0: host->target HTC control and raw streams */ { .flags = CE_ATTR_FLAGS, .src_nentries = 16, .src_sz_max = 256, .dest_nentries = 0, .send_cb = ath10k_pci_htc_tx_cb, }, /* CE1: target->host HTT + HTC control */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 512, .recv_cb = ath10k_pci_htt_htc_rx_cb, }, /* CE2: target->host WMI */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 128, .recv_cb = ath10k_pci_htc_rx_cb, }, /* CE3: host->target WMI */ { .flags = CE_ATTR_FLAGS, .src_nentries = 32, .src_sz_max = 2048, .dest_nentries = 0, .send_cb = ath10k_pci_htc_tx_cb, }, /* CE4: host->target HTT */ { .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, .src_sz_max = 256, .dest_nentries = 0, .send_cb = ath10k_pci_htt_tx_cb, }, /* CE5: target->host HTT (HIF->HTT) */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 512, .dest_nentries = 512, .recv_cb = ath10k_pci_htt_rx_cb, }, /* CE6: target autonomous hif_memcpy */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 0, .dest_nentries = 0, }, /* CE7: ce_diag, the Diagnostic Window */ { .flags = CE_ATTR_FLAGS | CE_ATTR_POLL, .src_nentries = 2, .src_sz_max = DIAG_TRANSFER_LIMIT, .dest_nentries = 2, }, /* CE8: target->host pktlog */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 128, .recv_cb = ath10k_pci_pktlog_rx_cb, }, /* CE9 target autonomous qcache memcpy */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 0, .dest_nentries = 0, }, /* CE10: target autonomous hif memcpy */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 0, .dest_nentries = 0, }, /* CE11: target autonomous hif memcpy */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 0, .dest_nentries = 0, }, }; /* Target firmware's Copy Engine configuration. */ static const struct ce_pipe_config pci_target_ce_config_wlan[] = { /* CE0: host->target HTC control and raw streams */ { .pipenum = __cpu_to_le32(0), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(256), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE1: target->host HTT + HTC control */ { .pipenum = __cpu_to_le32(1), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE2: target->host WMI */ { .pipenum = __cpu_to_le32(2), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(64), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE3: host->target WMI */ { .pipenum = __cpu_to_le32(3), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE4: host->target HTT */ { .pipenum = __cpu_to_le32(4), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(256), .nbytes_max = __cpu_to_le32(256), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* NB: 50% of src nentries, since tx has 2 frags */ /* CE5: target->host HTT (HIF->HTT) */ { .pipenum = __cpu_to_le32(5), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(512), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE6: Reserved for target autonomous hif_memcpy */ { .pipenum = __cpu_to_le32(6), .pipedir = __cpu_to_le32(PIPEDIR_INOUT), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(4096), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE7 used only by Host */ { .pipenum = __cpu_to_le32(7), .pipedir = __cpu_to_le32(PIPEDIR_INOUT), .nentries = __cpu_to_le32(0), .nbytes_max = __cpu_to_le32(0), .flags = __cpu_to_le32(0), .reserved = __cpu_to_le32(0), }, /* CE8 target->host packtlog */ { .pipenum = __cpu_to_le32(8), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(64), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), .reserved = __cpu_to_le32(0), }, /* CE9 target autonomous qcache memcpy */ { .pipenum = __cpu_to_le32(9), .pipedir = __cpu_to_le32(PIPEDIR_INOUT), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), .reserved = __cpu_to_le32(0), }, /* It not necessary to send target wlan configuration for CE10 & CE11 * as these CEs are not actively used in target. */ }; /* * Map from service/endpoint to Copy Engine. * This table is derived from the CE_PCI TABLE, above. * It is passed to the Target at startup for use by firmware. */ static const struct ce_service_to_pipe pci_target_service_to_ce_map_wlan[] = { { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(0), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(1), }, { /* not used */ __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(0), }, { /* not used */ __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(1), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(4), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(5), }, /* (Additions here) */ { /* must be last */ __cpu_to_le32(0), __cpu_to_le32(0), __cpu_to_le32(0), }, }; static bool ath10k_pci_is_awake(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); #if defined(__linux__) u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + RTC_STATE_ADDRESS); #elif defined(__FreeBSD__) u32 val = bus_read_4((struct resource *)ar_pci->mem, PCIE_LOCAL_BASE_ADDRESS + RTC_STATE_ADDRESS); #endif return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; } static void __ath10k_pci_wake(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); lockdep_assert_held(&ar_pci->ps_lock); ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", ar_pci->ps_wake_refcount, ar_pci->ps_awake); #if defined(__linux__) iowrite32(PCIE_SOC_WAKE_V_MASK, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS); #elif defined(__FreeBSD__) bus_write_4((struct resource *)ar_pci->mem, PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK); #endif } static void __ath10k_pci_sleep(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); lockdep_assert_held(&ar_pci->ps_lock); ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", ar_pci->ps_wake_refcount, ar_pci->ps_awake); #if defined(__linux__) iowrite32(PCIE_SOC_WAKE_RESET, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS); #elif defined(__FreeBSD__) bus_write_4((struct resource *)ar_pci->mem, PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET); #endif ar_pci->ps_awake = false; } static int ath10k_pci_wake_wait(struct ath10k *ar) { int tot_delay = 0; int curr_delay = 5; while (tot_delay < PCIE_WAKE_TIMEOUT) { if (ath10k_pci_is_awake(ar)) { if (tot_delay > PCIE_WAKE_LATE_US) ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n", tot_delay / 1000); return 0; } udelay(curr_delay); tot_delay += curr_delay; if (curr_delay < 50) curr_delay += 5; } return -ETIMEDOUT; } static int ath10k_pci_force_wake(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); unsigned long flags; int ret = 0; if (ar_pci->pci_ps) return ret; spin_lock_irqsave(&ar_pci->ps_lock, flags); if (!ar_pci->ps_awake) { #if defined(__linux__) iowrite32(PCIE_SOC_WAKE_V_MASK, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS); #elif defined(__FreeBSD__) bus_write_4((struct resource *)ar_pci->mem, PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK); #endif ret = ath10k_pci_wake_wait(ar); if (ret == 0) ar_pci->ps_awake = true; } spin_unlock_irqrestore(&ar_pci->ps_lock, flags); return ret; } static void ath10k_pci_force_sleep(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); unsigned long flags; spin_lock_irqsave(&ar_pci->ps_lock, flags); #if defined(__linux__) iowrite32(PCIE_SOC_WAKE_RESET, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS); #elif defined(__FreeBSD__) bus_write_4((struct resource *)ar_pci->mem, PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET); #endif ar_pci->ps_awake = false; spin_unlock_irqrestore(&ar_pci->ps_lock, flags); } static int ath10k_pci_wake(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); unsigned long flags; int ret = 0; if (ar_pci->pci_ps == 0) return ret; spin_lock_irqsave(&ar_pci->ps_lock, flags); ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", ar_pci->ps_wake_refcount, ar_pci->ps_awake); /* This function can be called very frequently. To avoid excessive * CPU stalls for MMIO reads use a cache var to hold the device state. */ if (!ar_pci->ps_awake) { __ath10k_pci_wake(ar); ret = ath10k_pci_wake_wait(ar); if (ret == 0) ar_pci->ps_awake = true; } if (ret == 0) { ar_pci->ps_wake_refcount++; WARN_ON(ar_pci->ps_wake_refcount == 0); } spin_unlock_irqrestore(&ar_pci->ps_lock, flags); return ret; } static void ath10k_pci_sleep(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); unsigned long flags; if (ar_pci->pci_ps == 0) return; spin_lock_irqsave(&ar_pci->ps_lock, flags); ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", ar_pci->ps_wake_refcount, ar_pci->ps_awake); if (WARN_ON(ar_pci->ps_wake_refcount == 0)) goto skip; ar_pci->ps_wake_refcount--; mod_timer(&ar_pci->ps_timer, jiffies + msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC)); skip: spin_unlock_irqrestore(&ar_pci->ps_lock, flags); } static void ath10k_pci_ps_timer(struct timer_list *t) { struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer); struct ath10k *ar = ar_pci->ar; unsigned long flags; spin_lock_irqsave(&ar_pci->ps_lock, flags); ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", ar_pci->ps_wake_refcount, ar_pci->ps_awake); if (ar_pci->ps_wake_refcount > 0) goto skip; __ath10k_pci_sleep(ar); skip: spin_unlock_irqrestore(&ar_pci->ps_lock, flags); } static void ath10k_pci_sleep_sync(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); unsigned long flags; if (ar_pci->pci_ps == 0) { ath10k_pci_force_sleep(ar); return; } del_timer_sync(&ar_pci->ps_timer); spin_lock_irqsave(&ar_pci->ps_lock, flags); WARN_ON(ar_pci->ps_wake_refcount > 0); __ath10k_pci_sleep(ar); spin_unlock_irqrestore(&ar_pci->ps_lock, flags); } static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int ret; if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", offset, offset + sizeof(value), ar_pci->mem_len); return; } ret = ath10k_pci_wake(ar); if (ret) { ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", value, offset, ret); return; } #if defined(__linux__) iowrite32(value, ar_pci->mem + offset); #elif defined(__FreeBSD__) bus_write_4((struct resource *)ar_pci->mem, offset, value); #endif ath10k_pci_sleep(ar); } static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); u32 val; int ret; if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", offset, offset + sizeof(val), ar_pci->mem_len); return 0; } ret = ath10k_pci_wake(ar); if (ret) { ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", offset, ret); return 0xffffffff; } #if defined(__linux__) val = ioread32(ar_pci->mem + offset); #elif defined(__FreeBSD__) val = bus_read_4((struct resource *)ar_pci->mem, offset); #endif ath10k_pci_sleep(ar); return val; } inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) { struct ath10k_ce *ce = ath10k_ce_priv(ar); ce->bus_ops->write32(ar, offset, value); } inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) { struct ath10k_ce *ce = ath10k_ce_priv(ar); return ce->bus_ops->read32(ar, offset); } u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) { return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); } void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) { ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); } u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) { return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); } void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) { ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); } bool ath10k_pci_irq_pending(struct ath10k *ar) { u32 cause; /* Check if the shared legacy irq is for us */ cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CAUSE_ADDRESS); if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) return true; return false; } void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) { /* IMPORTANT: INTR_CLR register has to be set after * INTR_ENABLE is set to 0, otherwise interrupt can not be * really cleared. */ ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 0); ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); /* IMPORTANT: this extra read transaction is required to * flush the posted write buffer. */ (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS); } void ath10k_pci_enable_legacy_irq(struct ath10k *ar) { ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); /* IMPORTANT: this extra read transaction is required to * flush the posted write buffer. */ (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS); } static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) return "msi"; return "legacy"; } static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) { struct ath10k *ar = pipe->hif_ce_state; struct ath10k_ce *ce = ath10k_ce_priv(ar); struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; struct sk_buff *skb; dma_addr_t paddr; int ret; skb = dev_alloc_skb(pipe->buf_sz); if (!skb) return -ENOMEM; WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); paddr = dma_map_single(ar->dev, skb->data, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); if (unlikely(dma_mapping_error(ar->dev, paddr))) { ath10k_warn(ar, "failed to dma map pci rx buf\n"); dev_kfree_skb_any(skb); return -EIO; } ATH10K_SKB_RXCB(skb)->paddr = paddr; spin_lock_bh(&ce->ce_lock); ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); spin_unlock_bh(&ce->ce_lock); if (ret) { dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); dev_kfree_skb_any(skb); return ret; } return 0; } static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) { struct ath10k *ar = pipe->hif_ce_state; struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar); struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; int ret, num; if (pipe->buf_sz == 0) return; if (!ce_pipe->dest_ring) return; spin_lock_bh(&ce->ce_lock); num = __ath10k_ce_rx_num_free_bufs(ce_pipe); spin_unlock_bh(&ce->ce_lock); while (num >= 0) { ret = __ath10k_pci_rx_post_buf(pipe); if (ret) { if (ret == -ENOSPC) break; ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); mod_timer(&ar_pci->rx_post_retry, jiffies + ATH10K_PCI_RX_POST_RETRY_MS); break; } num--; } } void ath10k_pci_rx_post(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int i; for (i = 0; i < CE_COUNT; i++) ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); } void ath10k_pci_rx_replenish_retry(struct timer_list *t) { struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry); struct ath10k *ar = ar_pci->ar; ath10k_pci_rx_post(ar); } static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) { u32 val = 0, region = addr & 0xfffff; val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) & 0x7ff) << 21; val |= 0x100000 | region; return val; } /* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr. * Support to access target space below 1M for qca6174 and qca9377. * If target space is below 1M, the bit[20] of converted CE addr is 0. * Otherwise bit[20] of converted CE addr is 1. */ static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) { u32 val = 0, region = addr & 0xfffff; val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) & 0x7ff) << 21; val |= ((addr >= 0x100000) ? 0x100000 : 0) | region; return val; } static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) { u32 val = 0, region = addr & 0xfffff; val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); val |= 0x100000 | region; return val; } static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) return -ENOTSUPP; return ar_pci->targ_cpu_to_ce_addr(ar, addr); } /* * Diagnostic read/write access is provided for startup/config/debug usage. * Caller must guarantee proper alignment, when applicable, and single user * at any moment. */ #if defined(__linux__) static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, #elif defined(__FreeBSD__) static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, u8 *data, #endif int nbytes) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int ret = 0; u32 *buf; unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; struct ath10k_ce_pipe *ce_diag; /* Host buffer address in CE space */ u32 ce_data; dma_addr_t ce_data_base = 0; void *data_buf; int i; mutex_lock(&ar_pci->ce_diag_mutex); ce_diag = ar_pci->ce_diag; /* * Allocate a temporary bounce buffer to hold caller's data * to be DMA'ed from Target. This guarantees * 1) 4-byte alignment * 2) Buffer in DMA-able space */ alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, GFP_ATOMIC); if (!data_buf) { ret = -ENOMEM; goto done; } /* The address supplied by the caller is in the * Target CPU virtual address space. * * In order to use this address with the diagnostic CE, * convert it from Target CPU virtual address space * to CE address space */ address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); remaining_bytes = nbytes; ce_data = ce_data_base; while (remaining_bytes) { nbytes = min_t(unsigned int, remaining_bytes, DIAG_TRANSFER_LIMIT); ret = ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data); if (ret != 0) goto done; /* Request CE to send from Target(!) address to Host buffer */ ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0, 0); if (ret) goto done; i = 0; while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) { udelay(DIAG_ACCESS_CE_WAIT_US); i += DIAG_ACCESS_CE_WAIT_US; if (i > DIAG_ACCESS_CE_TIMEOUT_US) { ret = -EBUSY; goto done; } } i = 0; while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf, &completed_nbytes) != 0) { udelay(DIAG_ACCESS_CE_WAIT_US); i += DIAG_ACCESS_CE_WAIT_US; if (i > DIAG_ACCESS_CE_TIMEOUT_US) { ret = -EBUSY; goto done; } } if (nbytes != completed_nbytes) { ret = -EIO; goto done; } if (*buf != ce_data) { ret = -EIO; goto done; } remaining_bytes -= nbytes; memcpy(data, data_buf, nbytes); address += nbytes; data += nbytes; } done: if (data_buf) dma_free_coherent(ar->dev, alloc_nbytes, data_buf, ce_data_base); mutex_unlock(&ar_pci->ce_diag_mutex); return ret; } static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) { __le32 val = 0; int ret; #if defined(__linux__) ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); #elif defined(__FreeBSD__) ret = ath10k_pci_diag_read_mem(ar, address, (u8 *)&val, sizeof(val)); #endif *value = __le32_to_cpu(val); return ret; } static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, u32 src, u32 len) { u32 host_addr, addr; int ret; host_addr = host_interest_item_address(src); ret = ath10k_pci_diag_read32(ar, host_addr, &addr); if (ret != 0) { ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", src, ret); return ret; } ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); if (ret != 0) { ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", addr, len, ret); return ret; } return 0; } #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, #if defined(__linux__) const void *data, int nbytes) #elif defined(__FreeBSD__) const void *_d, int nbytes) #endif { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int ret = 0; u32 *buf; unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; struct ath10k_ce_pipe *ce_diag; void *data_buf; dma_addr_t ce_data_base = 0; int i; #if defined(__FreeBSD__) const u8 *data = _d; #endif mutex_lock(&ar_pci->ce_diag_mutex); ce_diag = ar_pci->ce_diag; /* * Allocate a temporary bounce buffer to hold caller's data * to be DMA'ed to Target. This guarantees * 1) 4-byte alignment * 2) Buffer in DMA-able space */ alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, GFP_ATOMIC); if (!data_buf) { ret = -ENOMEM; goto done; } /* * The address supplied by the caller is in the * Target CPU virtual address space. * * In order to use this address with the diagnostic CE, * convert it from * Target CPU virtual address space * to * CE address space */ address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); remaining_bytes = nbytes; while (remaining_bytes) { /* FIXME: check cast */ nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); /* Copy caller's data to allocated DMA buf */ memcpy(data_buf, data, nbytes); /* Set up to receive directly into Target(!) address */ ret = ath10k_ce_rx_post_buf(ce_diag, &address, address); if (ret != 0) goto done; /* * Request CE to send caller-supplied data that * was copied to bounce buffer to Target(!) address. */ ret = ath10k_ce_send(ce_diag, NULL, ce_data_base, nbytes, 0, 0); if (ret != 0) goto done; i = 0; while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) { udelay(DIAG_ACCESS_CE_WAIT_US); i += DIAG_ACCESS_CE_WAIT_US; if (i > DIAG_ACCESS_CE_TIMEOUT_US) { ret = -EBUSY; goto done; } } i = 0; while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf, &completed_nbytes) != 0) { udelay(DIAG_ACCESS_CE_WAIT_US); i += DIAG_ACCESS_CE_WAIT_US; if (i > DIAG_ACCESS_CE_TIMEOUT_US) { ret = -EBUSY; goto done; } } if (nbytes != completed_nbytes) { ret = -EIO; goto done; } if (*buf != address) { ret = -EIO; goto done; } remaining_bytes -= nbytes; address += nbytes; data += nbytes; } done: if (data_buf) { dma_free_coherent(ar->dev, alloc_nbytes, data_buf, ce_data_base); } if (ret != 0) ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", address, ret); mutex_unlock(&ar_pci->ce_diag_mutex); return ret; } static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) { __le32 val = __cpu_to_le32(value); return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); } /* Called by lower (CE) layer when a send to Target completes. */ static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) { struct ath10k *ar = ce_state->ar; struct sk_buff_head list; struct sk_buff *skb; __skb_queue_head_init(&list); while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { /* no need to call tx completion for NULL pointers */ if (skb == NULL) continue; __skb_queue_tail(&list, skb); } while ((skb = __skb_dequeue(&list))) ath10k_htc_tx_completion_handler(ar, skb); } static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, void (*callback)(struct ath10k *ar, struct sk_buff *skb)) { struct ath10k *ar = ce_state->ar; struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; struct sk_buff *skb; struct sk_buff_head list; void *transfer_context; unsigned int nbytes, max_nbytes; __skb_queue_head_init(&list); while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, &nbytes) == 0) { skb = transfer_context; max_nbytes = skb->len + skb_tailroom(skb); dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, max_nbytes, DMA_FROM_DEVICE); if (unlikely(max_nbytes < nbytes)) { ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", nbytes, max_nbytes); dev_kfree_skb_any(skb); continue; } skb_put(skb, nbytes); __skb_queue_tail(&list, skb); } while ((skb = __skb_dequeue(&list))) { ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", ce_state->id, skb->len); ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", skb->data, skb->len); callback(ar, skb); } ath10k_pci_rx_post_pipe(pipe_info); } static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state, void (*callback)(struct ath10k *ar, struct sk_buff *skb)) { struct ath10k *ar = ce_state->ar; struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; struct sk_buff *skb; struct sk_buff_head list; void *transfer_context; unsigned int nbytes, max_nbytes, nentries; int orig_len; /* No need to acquire ce_lock for CE5, since this is the only place CE5 * is processed other than init and deinit. Before releasing CE5 * buffers, interrupts are disabled. Thus CE5 access is serialized. */ __skb_queue_head_init(&list); while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context, &nbytes) == 0) { skb = transfer_context; max_nbytes = skb->len + skb_tailroom(skb); if (unlikely(max_nbytes < nbytes)) { ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", nbytes, max_nbytes); continue; } dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, max_nbytes, DMA_FROM_DEVICE); skb_put(skb, nbytes); __skb_queue_tail(&list, skb); } nentries = skb_queue_len(&list); while ((skb = __skb_dequeue(&list))) { ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", ce_state->id, skb->len); ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", skb->data, skb->len); orig_len = skb->len; callback(ar, skb); skb_push(skb, orig_len - skb->len); skb_reset_tail_pointer(skb); skb_trim(skb, 0); /*let device gain the buffer again*/ dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); } ath10k_ce_rx_update_write_idx(ce_pipe, nentries); } /* Called by lower (CE) layer when data is received from the Target. */ static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) { ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); } static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) { /* CE4 polling needs to be done whenever CE pipe which transports * HTT Rx (target->host) is processed. */ ath10k_ce_per_engine_service(ce_state->ar, 4); ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); } /* Called by lower (CE) layer when data is received from the Target. * Only 10.4 firmware uses separate CE to transfer pktlog data. */ static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) { ath10k_pci_process_rx_cb(ce_state, ath10k_htt_rx_pktlog_completion_handler); } /* Called by lower (CE) layer when a send to HTT Target completes. */ static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) { struct ath10k *ar = ce_state->ar; struct sk_buff *skb; while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { /* no need to call tx completion for NULL pointers */ if (!skb) continue; dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, skb->len, DMA_TO_DEVICE); ath10k_htt_hif_tx_complete(ar, skb); } } static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) { skb_pull(skb, sizeof(struct ath10k_htc_hdr)); ath10k_htt_t2h_msg_handler(ar, skb); } /* Called by lower (CE) layer when HTT data is received from the Target. */ static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) { /* CE4 polling needs to be done whenever CE pipe which transports * HTT Rx (target->host) is processed. */ ath10k_ce_per_engine_service(ce_state->ar, 4); ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver); } int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, struct ath10k_hif_sg_item *items, int n_items) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar); struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; unsigned int nentries_mask; unsigned int sw_index; unsigned int write_index; int err, i = 0; spin_lock_bh(&ce->ce_lock); nentries_mask = src_ring->nentries_mask; sw_index = src_ring->sw_index; write_index = src_ring->write_index; if (unlikely(CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) < n_items)) { err = -ENOBUFS; goto err; } for (i = 0; i < n_items - 1; i++) { ath10k_dbg(ar, ATH10K_DBG_PCI, "pci tx item %d paddr %pad len %d n_items %d\n", i, &items[i].paddr, items[i].len, n_items); ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", items[i].vaddr, items[i].len); err = ath10k_ce_send_nolock(ce_pipe, items[i].transfer_context, items[i].paddr, items[i].len, items[i].transfer_id, CE_SEND_FLAG_GATHER); if (err) goto err; } /* `i` is equal to `n_items -1` after for() */ ath10k_dbg(ar, ATH10K_DBG_PCI, #if defined(__linux__) "pci tx item %d paddr %pad len %d n_items %d\n", i, &items[i].paddr, items[i].len, n_items); #elif defined(__FreeBSD__) "pci tx item %d paddr %pad len %d n_items %d pipe_id %u\n", i, &items[i].paddr, items[i].len, n_items, pipe_id); /* * XXX-BZ specific debug; the DELAY makes things work for one chipset. * There's likely a race somewhere (here or LinuxKPI). */ if (n_items == 1 && items[i].len == 140) { ath10k_dbg_dump(ar, ATH10K_DBG_PCI, NULL, "pci tx data: ", items[i].vaddr, items[i].len); dump_stack(); DELAY(500); } #endif ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", items[i].vaddr, items[i].len); err = ath10k_ce_send_nolock(ce_pipe, items[i].transfer_context, items[i].paddr, items[i].len, items[i].transfer_id, 0); if (err) goto err; spin_unlock_bh(&ce->ce_lock); return 0; err: for (; i > 0; i--) __ath10k_ce_send_revert(ce_pipe); spin_unlock_bh(&ce->ce_lock); return err; } int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, size_t buf_len) { return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); } u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); } static void ath10k_pci_dump_registers(struct ath10k *ar, struct ath10k_fw_crash_data *crash_data) { __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; int i, ret; lockdep_assert_held(&ar->dump_mutex); ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], hi_failure_state, REG_DUMP_COUNT_QCA988X * sizeof(__le32)); if (ret) { ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); return; } BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); ath10k_err(ar, "firmware register dump:\n"); for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, __le32_to_cpu(reg_dump_values[i]), __le32_to_cpu(reg_dump_values[i + 1]), __le32_to_cpu(reg_dump_values[i + 2]), __le32_to_cpu(reg_dump_values[i + 3])); if (!crash_data) return; for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) crash_data->registers[i] = reg_dump_values[i]; } static int ath10k_pci_dump_memory_section(struct ath10k *ar, const struct ath10k_mem_region *mem_region, u8 *buf, size_t buf_len) { const struct ath10k_mem_section *cur_section, *next_section; unsigned int count, section_size, skip_size; int ret, i, j; if (!mem_region || !buf) return 0; cur_section = &mem_region->section_table.sections[0]; if (mem_region->start > cur_section->start) { ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n", mem_region->start, cur_section->start); return 0; } skip_size = cur_section->start - mem_region->start; /* fill the gap between the first register section and register * start address */ for (i = 0; i < skip_size; i++) { *buf = ATH10K_MAGIC_NOT_COPIED; buf++; } count = 0; for (i = 0; cur_section != NULL; i++) { section_size = cur_section->end - cur_section->start; if (section_size <= 0) { ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n", cur_section->start, cur_section->end); break; } if ((i + 1) == mem_region->section_table.size) { /* last section */ next_section = NULL; skip_size = 0; } else { next_section = cur_section + 1; if (cur_section->end > next_section->start) { ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n", next_section->start, cur_section->end); break; } skip_size = next_section->start - cur_section->end; } if (buf_len < (skip_size + section_size)) { ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len); break; } buf_len -= skip_size + section_size; /* read section to dest memory */ ret = ath10k_pci_diag_read_mem(ar, cur_section->start, buf, section_size); if (ret) { ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n", cur_section->start, ret); break; } buf += section_size; count += section_size; /* fill in the gap between this section and the next */ for (j = 0; j < skip_size; j++) { *buf = ATH10K_MAGIC_NOT_COPIED; buf++; } count += skip_size; if (!next_section) /* this was the last section */ break; cur_section = next_section; } return count; } static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config) { u32 val; ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + FW_RAM_CONFIG_ADDRESS, config); val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + FW_RAM_CONFIG_ADDRESS); if (val != config) { ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n", val, config); return -EIO; } return 0; } /* Always returns the length */ static int ath10k_pci_dump_memory_sram(struct ath10k *ar, const struct ath10k_mem_region *region, u8 *buf) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); u32 base_addr, i; #if defined(__linux__) base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG); #elif defined(__FreeBSD__) base_addr = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_PCIE_BAR0_START_REG); #endif base_addr += region->start; for (i = 0; i < region->len; i += 4) { #if defined(__linux__) iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG); *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG); #elif defined(__FreeBSD__) bus_write_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_ADDR_REG, base_addr + i); *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_DATA_REG); #endif } return region->len; } /* if an error happened returns < 0, otherwise the length */ static int ath10k_pci_dump_memory_reg(struct ath10k *ar, const struct ath10k_mem_region *region, u8 *buf) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); u32 i; int ret; mutex_lock(&ar->conf_mutex); if (ar->state != ATH10K_STATE_ON) { ath10k_warn(ar, "Skipping pci_dump_memory_reg invalid state\n"); ret = -EIO; goto done; } for (i = 0; i < region->len; i += 4) #if defined(__linux__) *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i); #elif defined(__FreeBSD__) *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, region->start + i); #endif ret = region->len; done: mutex_unlock(&ar->conf_mutex); return ret; } /* if an error happened returns < 0, otherwise the length */ static int ath10k_pci_dump_memory_generic(struct ath10k *ar, const struct ath10k_mem_region *current_region, u8 *buf) { int ret; if (current_region->section_table.size > 0) /* Copy each section individually. */ return ath10k_pci_dump_memory_section(ar, current_region, buf, current_region->len); /* No individiual memory sections defined so we can * copy the entire memory region. */ ret = ath10k_pci_diag_read_mem(ar, current_region->start, buf, current_region->len); if (ret) { ath10k_warn(ar, "failed to copy ramdump region %s: %d\n", current_region->name, ret); return ret; } return current_region->len; } static void ath10k_pci_dump_memory(struct ath10k *ar, struct ath10k_fw_crash_data *crash_data) { const struct ath10k_hw_mem_layout *mem_layout; const struct ath10k_mem_region *current_region; struct ath10k_dump_ram_data_hdr *hdr; u32 count, shift; size_t buf_len; int ret, i; u8 *buf; lockdep_assert_held(&ar->dump_mutex); if (!crash_data) return; mem_layout = ath10k_coredump_get_mem_layout(ar); if (!mem_layout) return; current_region = &mem_layout->region_table.regions[0]; buf = crash_data->ramdump_buf; buf_len = crash_data->ramdump_buf_len; memset(buf, 0, buf_len); for (i = 0; i < mem_layout->region_table.size; i++) { count = 0; if (current_region->len > buf_len) { ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n", current_region->name, current_region->len, buf_len); break; } /* To get IRAM dump, the host driver needs to switch target * ram config from DRAM to IRAM. */ if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 || current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) { shift = current_region->start >> 20; ret = ath10k_pci_set_ram_config(ar, shift); if (ret) { ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n", current_region->name, ret); break; } } /* Reserve space for the header. */ hdr = (void *)buf; buf += sizeof(*hdr); buf_len -= sizeof(*hdr); switch (current_region->type) { case ATH10K_MEM_REGION_TYPE_IOSRAM: count = ath10k_pci_dump_memory_sram(ar, current_region, buf); break; case ATH10K_MEM_REGION_TYPE_IOREG: ret = ath10k_pci_dump_memory_reg(ar, current_region, buf); if (ret < 0) break; count = ret; break; default: ret = ath10k_pci_dump_memory_generic(ar, current_region, buf); if (ret < 0) break; count = ret; break; } hdr->region_type = cpu_to_le32(current_region->type); hdr->start = cpu_to_le32(current_region->start); hdr->length = cpu_to_le32(count); if (count == 0) /* Note: the header remains, just with zero length. */ break; buf += count; buf_len -= count; current_region++; } } static void ath10k_pci_fw_dump_work(struct work_struct *work) { struct ath10k_pci *ar_pci = container_of(work, struct ath10k_pci, dump_work); struct ath10k_fw_crash_data *crash_data; struct ath10k *ar = ar_pci->ar; char guid[UUID_STRING_LEN + 1]; mutex_lock(&ar->dump_mutex); spin_lock_bh(&ar->data_lock); ar->stats.fw_crash_counter++; spin_unlock_bh(&ar->data_lock); crash_data = ath10k_coredump_new(ar); if (crash_data) scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); else scnprintf(guid, sizeof(guid), "n/a"); ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); ath10k_print_driver_info(ar); ath10k_pci_dump_registers(ar, crash_data); ath10k_ce_dump_registers(ar, crash_data); ath10k_pci_dump_memory(ar, crash_data); mutex_unlock(&ar->dump_mutex); ath10k_core_start_recovery(ar); } static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); queue_work(ar->workqueue, &ar_pci->dump_work); } void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, int force) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); if (!force) { int resources; /* * Decide whether to actually poll for completions, or just * wait for a later chance. * If there seem to be plenty of resources left, then just wait * since checking involves reading a CE register, which is a * relatively expensive operation. */ resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); /* * If at least 50% of the total resources are still available, * don't bother checking again yet. */ if (resources > (ar_pci->attr[pipe].src_nentries >> 1)) return; } ath10k_ce_per_engine_service(ar, pipe); } static void ath10k_pci_rx_retry_sync(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); del_timer_sync(&ar_pci->rx_post_retry); } int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, u8 *ul_pipe, u8 *dl_pipe) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); const struct ce_service_to_pipe *entry; bool ul_set = false, dl_set = false; int i; ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); for (i = 0; i < ARRAY_SIZE(pci_target_service_to_ce_map_wlan); i++) { entry = &ar_pci->serv_to_pipe[i]; if (__le32_to_cpu(entry->service_id) != service_id) continue; switch (__le32_to_cpu(entry->pipedir)) { case PIPEDIR_NONE: break; case PIPEDIR_IN: WARN_ON(dl_set); *dl_pipe = __le32_to_cpu(entry->pipenum); dl_set = true; break; case PIPEDIR_OUT: WARN_ON(ul_set); *ul_pipe = __le32_to_cpu(entry->pipenum); ul_set = true; break; case PIPEDIR_INOUT: WARN_ON(dl_set); WARN_ON(ul_set); *dl_pipe = __le32_to_cpu(entry->pipenum); *ul_pipe = __le32_to_cpu(entry->pipenum); dl_set = true; ul_set = true; break; } } if (!ul_set || !dl_set) return -ENOENT; return 0; } void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe, u8 *dl_pipe) { ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); (void)ath10k_pci_hif_map_service_to_pipe(ar, ATH10K_HTC_SVC_ID_RSVD_CTRL, ul_pipe, dl_pipe); } void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) { u32 val; switch (ar->hw_rev) { case ATH10K_HW_QCA988X: case ATH10K_HW_QCA9887: case ATH10K_HW_QCA6174: case ATH10K_HW_QCA9377: val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS); val &= ~CORE_CTRL_PCIE_REG_31_MASK; ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS, val); break; case ATH10K_HW_QCA99X0: case ATH10K_HW_QCA9984: case ATH10K_HW_QCA9888: case ATH10K_HW_QCA4019: /* TODO: Find appropriate register configuration for QCA99X0 * to mask irq/MSI. */ break; case ATH10K_HW_WCN3990: break; } } static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) { u32 val; switch (ar->hw_rev) { case ATH10K_HW_QCA988X: case ATH10K_HW_QCA9887: case ATH10K_HW_QCA6174: case ATH10K_HW_QCA9377: val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS); val |= CORE_CTRL_PCIE_REG_31_MASK; ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS, val); break; case ATH10K_HW_QCA99X0: case ATH10K_HW_QCA9984: case ATH10K_HW_QCA9888: case ATH10K_HW_QCA4019: /* TODO: Find appropriate register configuration for QCA99X0 * to unmask irq/MSI. */ break; case ATH10K_HW_WCN3990: break; } } static void ath10k_pci_irq_disable(struct ath10k *ar) { ath10k_ce_disable_interrupts(ar); ath10k_pci_disable_and_clear_legacy_irq(ar); ath10k_pci_irq_msi_fw_mask(ar); } static void ath10k_pci_irq_sync(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); synchronize_irq(ar_pci->pdev->irq); } static void ath10k_pci_irq_enable(struct ath10k *ar) { ath10k_ce_enable_interrupts(ar); ath10k_pci_enable_legacy_irq(ar); ath10k_pci_irq_msi_fw_unmask(ar); } static int ath10k_pci_hif_start(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); ath10k_core_napi_enable(ar); ath10k_pci_irq_enable(ar); ath10k_pci_rx_post(ar); pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, ar_pci->link_ctl); return 0; } static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) { struct ath10k *ar; struct ath10k_ce_pipe *ce_pipe; struct ath10k_ce_ring *ce_ring; struct sk_buff *skb; int i; ar = pci_pipe->hif_ce_state; ce_pipe = pci_pipe->ce_hdl; ce_ring = ce_pipe->dest_ring; if (!ce_ring) return; if (!pci_pipe->buf_sz) return; for (i = 0; i < ce_ring->nentries; i++) { skb = ce_ring->per_transfer_context[i]; if (!skb) continue; ce_ring->per_transfer_context[i] = NULL; dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); dev_kfree_skb_any(skb); } } static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) { struct ath10k *ar; struct ath10k_ce_pipe *ce_pipe; struct ath10k_ce_ring *ce_ring; struct sk_buff *skb; int i; ar = pci_pipe->hif_ce_state; ce_pipe = pci_pipe->ce_hdl; ce_ring = ce_pipe->src_ring; if (!ce_ring) return; if (!pci_pipe->buf_sz) return; for (i = 0; i < ce_ring->nentries; i++) { skb = ce_ring->per_transfer_context[i]; if (!skb) continue; ce_ring->per_transfer_context[i] = NULL; ath10k_htc_tx_completion_handler(ar, skb); } } /* * Cleanup residual buffers for device shutdown: * buffers that were enqueued for receive * buffers that were to be sent * Note: Buffers that had completed but which were * not yet processed are on a completion queue. They * are handled when the completion thread shuts down. */ static void ath10k_pci_buffer_cleanup(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int pipe_num; for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { struct ath10k_pci_pipe *pipe_info; pipe_info = &ar_pci->pipe_info[pipe_num]; ath10k_pci_rx_pipe_cleanup(pipe_info); ath10k_pci_tx_pipe_cleanup(pipe_info); } } void ath10k_pci_ce_deinit(struct ath10k *ar) { int i; for (i = 0; i < CE_COUNT; i++) ath10k_ce_deinit_pipe(ar, i); } void ath10k_pci_flush(struct ath10k *ar) { ath10k_pci_rx_retry_sync(ar); ath10k_pci_buffer_cleanup(ar); } static void ath10k_pci_hif_stop(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); unsigned long flags; ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); ath10k_pci_irq_disable(ar); ath10k_pci_irq_sync(ar); ath10k_core_napi_sync_disable(ar); cancel_work_sync(&ar_pci->dump_work); /* Most likely the device has HTT Rx ring configured. The only way to * prevent the device from accessing (and possible corrupting) host * memory is to reset the chip now. * * There's also no known way of masking MSI interrupts on the device. * For ranged MSI the CE-related interrupts can be masked. However * regardless how many MSI interrupts are assigned the first one * is always used for firmware indications (crashes) and cannot be * masked. To prevent the device from asserting the interrupt reset it * before proceeding with cleanup. */ ath10k_pci_safe_chip_reset(ar); ath10k_pci_flush(ar); spin_lock_irqsave(&ar_pci->ps_lock, flags); WARN_ON(ar_pci->ps_wake_refcount > 0); spin_unlock_irqrestore(&ar_pci->ps_lock, flags); } int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len, void *resp, u32 *resp_len) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; dma_addr_t req_paddr = 0; dma_addr_t resp_paddr = 0; struct bmi_xfer xfer = {}; void *treq, *tresp = NULL; int ret = 0; might_sleep(); if (resp && !resp_len) return -EINVAL; if (resp && resp_len && *resp_len == 0) return -EINVAL; treq = kmemdup(req, req_len, GFP_KERNEL); if (!treq) return -ENOMEM; req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); ret = dma_mapping_error(ar->dev, req_paddr); if (ret) { ret = -EIO; goto err_dma; } if (resp && resp_len) { tresp = kzalloc(*resp_len, GFP_KERNEL); if (!tresp) { ret = -ENOMEM; goto err_req; } resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, DMA_FROM_DEVICE); ret = dma_mapping_error(ar->dev, resp_paddr); if (ret) { ret = -EIO; goto err_req; } xfer.wait_for_resp = true; xfer.resp_len = 0; ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); } ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); if (ret) goto err_resp; ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer); if (ret) { dma_addr_t unused_buffer; unsigned int unused_nbytes; unsigned int unused_id; ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, &unused_nbytes, &unused_id); } else { /* non-zero means we did not time out */ ret = 0; } err_resp: if (resp) { dma_addr_t unused_buffer; ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); dma_unmap_single(ar->dev, resp_paddr, *resp_len, DMA_FROM_DEVICE); } err_req: dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); if (ret == 0 && resp_len) { *resp_len = min(*resp_len, xfer.resp_len); memcpy(resp, tresp, *resp_len); } err_dma: kfree(treq); kfree(tresp); return ret; } static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) { struct bmi_xfer *xfer; if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer)) return; xfer->tx_done = true; } static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) { struct ath10k *ar = ce_state->ar; struct bmi_xfer *xfer; unsigned int nbytes; if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &nbytes)) return; if (WARN_ON_ONCE(!xfer)) return; if (!xfer->wait_for_resp) { ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); return; } xfer->resp_len = nbytes; xfer->rx_done = true; } static int ath10k_pci_bmi_wait(struct ath10k *ar, struct ath10k_ce_pipe *tx_pipe, struct ath10k_ce_pipe *rx_pipe, struct bmi_xfer *xfer) { unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; unsigned long started = jiffies; unsigned long dur; int ret; while (time_before_eq(jiffies, timeout)) { ath10k_pci_bmi_send_done(tx_pipe); ath10k_pci_bmi_recv_data(rx_pipe); if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) { ret = 0; goto out; } #if defined(__linux__) schedule(); #elif defined(__FreeBSD__) /* Using LinuxKPI we'll hang for-ever as there's no wake_up */ kern_yield(PRI_USER); #endif } ret = -ETIMEDOUT; out: dur = jiffies - started; if (dur > HZ) ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi cmd took %lu jiffies hz %d ret %d\n", dur, HZ, ret); return ret; } /* * Send an interrupt to the device to wake up the Target CPU * so it has an opportunity to notice any changed state. */ static int ath10k_pci_wake_target_cpu(struct ath10k *ar) { u32 addr, val; addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS; val = ath10k_pci_read32(ar, addr); val |= CORE_CTRL_CPU_INTR_MASK; ath10k_pci_write32(ar, addr, val); return 0; } static int ath10k_pci_get_num_banks(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); switch (ar_pci->pdev->device) { case QCA988X_2_0_DEVICE_ID_UBNT: case QCA988X_2_0_DEVICE_ID: case QCA99X0_2_0_DEVICE_ID: case QCA9888_2_0_DEVICE_ID: case QCA9984_1_0_DEVICE_ID: case QCA9887_1_0_DEVICE_ID: return 1; case QCA6164_2_1_DEVICE_ID: case QCA6174_2_1_DEVICE_ID: switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) { case QCA6174_HW_1_0_CHIP_ID_REV: case QCA6174_HW_1_1_CHIP_ID_REV: case QCA6174_HW_2_1_CHIP_ID_REV: case QCA6174_HW_2_2_CHIP_ID_REV: return 3; case QCA6174_HW_1_3_CHIP_ID_REV: return 2; case QCA6174_HW_3_0_CHIP_ID_REV: case QCA6174_HW_3_1_CHIP_ID_REV: case QCA6174_HW_3_2_CHIP_ID_REV: return 9; } break; case QCA9377_1_0_DEVICE_ID: return 9; } ath10k_warn(ar, "unknown number of banks, assuming 1\n"); return 1; } static int ath10k_bus_get_num_banks(struct ath10k *ar) { struct ath10k_ce *ce = ath10k_ce_priv(ar); return ce->bus_ops->get_num_banks(ar); } int ath10k_pci_init_config(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); u32 interconnect_targ_addr; u32 pcie_state_targ_addr = 0; u32 pipe_cfg_targ_addr = 0; u32 svc_to_pipe_map = 0; u32 pcie_config_flags = 0; u32 ealloc_value; u32 ealloc_targ_addr; u32 flag2_value; u32 flag2_targ_addr; int ret = 0; /* Download to Target the CE Config and the service-to-CE map */ interconnect_targ_addr = host_interest_item_address(HI_ITEM(hi_interconnect_state)); /* Supply Target-side CE configuration */ ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, &pcie_state_targ_addr); if (ret != 0) { ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); return ret; } if (pcie_state_targ_addr == 0) { ret = -EIO; ath10k_err(ar, "Invalid pcie state addr\n"); return ret; } ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + offsetof(struct pcie_state, pipe_cfg_addr)), &pipe_cfg_targ_addr); if (ret != 0) { ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); return ret; } if (pipe_cfg_targ_addr == 0) { ret = -EIO; ath10k_err(ar, "Invalid pipe cfg addr\n"); return ret; } ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, ar_pci->pipe_config, sizeof(struct ce_pipe_config) * NUM_TARGET_CE_CONFIG_WLAN); if (ret != 0) { ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); return ret; } ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + offsetof(struct pcie_state, svc_to_pipe_map)), &svc_to_pipe_map); if (ret != 0) { ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); return ret; } if (svc_to_pipe_map == 0) { ret = -EIO; ath10k_err(ar, "Invalid svc_to_pipe map\n"); return ret; } ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, ar_pci->serv_to_pipe, sizeof(pci_target_service_to_ce_map_wlan)); if (ret != 0) { ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); return ret; } ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + offsetof(struct pcie_state, config_flags)), &pcie_config_flags); if (ret != 0) { ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); return ret; } pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + offsetof(struct pcie_state, config_flags)), pcie_config_flags); if (ret != 0) { ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); return ret; } /* configure early allocation */ ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); if (ret != 0) { ath10k_err(ar, "Failed to get early alloc val: %d\n", ret); return ret; } /* first bank is switched to IRAM */ ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & HI_EARLY_ALLOC_MAGIC_MASK); ealloc_value |= ((ath10k_bus_get_num_banks(ar) << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & HI_EARLY_ALLOC_IRAM_BANKS_MASK); ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); if (ret != 0) { ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); return ret; } /* Tell Target to proceed with initialization */ flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); if (ret != 0) { ath10k_err(ar, "Failed to get option val: %d\n", ret); return ret; } flag2_value |= HI_OPTION_EARLY_CFG_DONE; ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); if (ret != 0) { ath10k_err(ar, "Failed to set option val: %d\n", ret); return ret; } return 0; } static void ath10k_pci_override_ce_config(struct ath10k *ar) { struct ce_attr *attr; struct ce_pipe_config *config; struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); /* For QCA6174 we're overriding the Copy Engine 5 configuration, * since it is currently used for other feature. */ /* Override Host's Copy Engine 5 configuration */ attr = &ar_pci->attr[5]; attr->src_sz_max = 0; attr->dest_nentries = 0; /* Override Target firmware's Copy Engine configuration */ config = &ar_pci->pipe_config[5]; config->pipedir = __cpu_to_le32(PIPEDIR_OUT); config->nbytes_max = __cpu_to_le32(2048); /* Map from service/endpoint to Copy Engine */ ar_pci->serv_to_pipe[15].pipenum = __cpu_to_le32(1); } int ath10k_pci_alloc_pipes(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci_pipe *pipe; struct ath10k_ce *ce = ath10k_ce_priv(ar); int i, ret; for (i = 0; i < CE_COUNT; i++) { pipe = &ar_pci->pipe_info[i]; pipe->ce_hdl = &ce->ce_states[i]; pipe->pipe_num = i; pipe->hif_ce_state = ar; ret = ath10k_ce_alloc_pipe(ar, i, &ar_pci->attr[i]); if (ret) { ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", i, ret); return ret; } /* Last CE is Diagnostic Window */ if (i == CE_DIAG_PIPE) { ar_pci->ce_diag = pipe->ce_hdl; continue; } pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max); } return 0; } void ath10k_pci_free_pipes(struct ath10k *ar) { int i; for (i = 0; i < CE_COUNT; i++) ath10k_ce_free_pipe(ar, i); } int ath10k_pci_init_pipes(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int i, ret; for (i = 0; i < CE_COUNT; i++) { ret = ath10k_ce_init_pipe(ar, i, &ar_pci->attr[i]); if (ret) { ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", i, ret); return ret; } } return 0; } static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) { return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & FW_IND_EVENT_PENDING; } static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) { u32 val; val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); val &= ~FW_IND_EVENT_PENDING; ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); } static bool ath10k_pci_has_device_gone(struct ath10k *ar) { u32 val; val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); return (val == 0xffffffff); } /* this function effectively clears target memory controller assert line */ static void ath10k_pci_warm_reset_si0(struct ath10k *ar) { u32 val; val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, val | SOC_RESET_CONTROL_SI0_RST_MASK); val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); msleep(10); val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, val & ~SOC_RESET_CONTROL_SI0_RST_MASK); val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); msleep(10); } static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) { u32 val; ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); } static void ath10k_pci_warm_reset_ce(struct ath10k *ar) { u32 val; val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, val | SOC_RESET_CONTROL_CE_RST_MASK); msleep(10); ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, val & ~SOC_RESET_CONTROL_CE_RST_MASK); } static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) { u32 val; val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS); ath10k_pci_soc_write32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS, val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); } static int ath10k_pci_warm_reset(struct ath10k *ar) { int ret; ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); spin_lock_bh(&ar->data_lock); ar->stats.fw_warm_reset_counter++; spin_unlock_bh(&ar->data_lock); ath10k_pci_irq_disable(ar); /* Make sure the target CPU is not doing anything dangerous, e.g. if it * were to access copy engine while host performs copy engine reset * then it is possible for the device to confuse pci-e controller to * the point of bringing host system to a complete stop (i.e. hang). */ ath10k_pci_warm_reset_si0(ar); ath10k_pci_warm_reset_cpu(ar); ath10k_pci_init_pipes(ar); ath10k_pci_wait_for_target_init(ar); ath10k_pci_warm_reset_clear_lf(ar); ath10k_pci_warm_reset_ce(ar); ath10k_pci_warm_reset_cpu(ar); ath10k_pci_init_pipes(ar); ret = ath10k_pci_wait_for_target_init(ar); if (ret) { ath10k_warn(ar, "failed to wait for target init: %d\n", ret); return ret; } ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); return 0; } static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) { ath10k_pci_irq_disable(ar); return ath10k_pci_qca99x0_chip_reset(ar); } static int ath10k_pci_safe_chip_reset(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); if (!ar_pci->pci_soft_reset) return -ENOTSUPP; return ar_pci->pci_soft_reset(ar); } static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) { int i, ret; u32 val; ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. * It is thus preferred to use warm reset which is safer but may not be * able to recover the device from all possible fail scenarios. * * Warm reset doesn't always work on first try so attempt it a few * times before giving up. */ for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { ret = ath10k_pci_warm_reset(ar); if (ret) { ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, ret); continue; } /* FIXME: Sometimes copy engine doesn't recover after warm * reset. In most cases this needs cold reset. In some of these * cases the device is in such a state that a cold reset may * lock up the host. * * Reading any host interest register via copy engine is * sufficient to verify if device is capable of booting * firmware blob. */ ret = ath10k_pci_init_pipes(ar); if (ret) { ath10k_warn(ar, "failed to init copy engine: %d\n", ret); continue; } ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, &val); if (ret) { ath10k_warn(ar, "failed to poke copy engine: %d\n", ret); continue; } ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); return 0; } if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { ath10k_warn(ar, "refusing cold reset as requested\n"); return -EPERM; } ret = ath10k_pci_cold_reset(ar); if (ret) { ath10k_warn(ar, "failed to cold reset: %d\n", ret); return ret; } ret = ath10k_pci_wait_for_target_init(ar); if (ret) { ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", ret); return ret; } ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); return 0; } static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) { int ret; ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); /* FIXME: QCA6174 requires cold + warm reset to work. */ ret = ath10k_pci_cold_reset(ar); if (ret) { ath10k_warn(ar, "failed to cold reset: %d\n", ret); return ret; } ret = ath10k_pci_wait_for_target_init(ar); if (ret) { ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", ret); return ret; } ret = ath10k_pci_warm_reset(ar); if (ret) { ath10k_warn(ar, "failed to warm reset: %d\n", ret); return ret; } ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); return 0; } static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) { int ret; ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); ret = ath10k_pci_cold_reset(ar); if (ret) { ath10k_warn(ar, "failed to cold reset: %d\n", ret); return ret; } ret = ath10k_pci_wait_for_target_init(ar); if (ret) { ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", ret); return ret; } ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); return 0; } static int ath10k_pci_chip_reset(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); if (WARN_ON(!ar_pci->pci_hard_reset)) return -ENOTSUPP; return ar_pci->pci_hard_reset(ar); } static int ath10k_pci_hif_power_up(struct ath10k *ar, enum ath10k_firmware_mode fw_mode) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int ret; ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, &ar_pci->link_ctl); pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); /* * Bring the target up cleanly. * * The target may be in an undefined state with an AUX-powered Target * and a Host in WoW mode. If the Host crashes, loses power, or is * restarted (without unloading the driver) then the Target is left * (aux) powered and running. On a subsequent driver load, the Target * is in an unexpected state. We try to catch that here in order to * reset the Target and retry the probe. */ ret = ath10k_pci_chip_reset(ar); if (ret) { if (ath10k_pci_has_fw_crashed(ar)) { ath10k_warn(ar, "firmware crashed during chip reset\n"); ath10k_pci_fw_crashed_clear(ar); ath10k_pci_fw_crashed_dump(ar); } ath10k_err(ar, "failed to reset chip: %d\n", ret); goto err_sleep; } ret = ath10k_pci_init_pipes(ar); if (ret) { ath10k_err(ar, "failed to initialize CE: %d\n", ret); goto err_sleep; } ret = ath10k_pci_init_config(ar); if (ret) { ath10k_err(ar, "failed to setup init config: %d\n", ret); goto err_ce; } ret = ath10k_pci_wake_target_cpu(ar); if (ret) { ath10k_err(ar, "could not wake up target CPU: %d\n", ret); goto err_ce; } return 0; err_ce: ath10k_pci_ce_deinit(ar); err_sleep: return ret; } void ath10k_pci_hif_power_down(struct ath10k *ar) { ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); /* Currently hif_power_up performs effectively a reset and hif_stop * resets the chip as well so there's no point in resetting here. */ } static int ath10k_pci_hif_suspend(struct ath10k *ar) { /* Nothing to do; the important stuff is in the driver suspend. */ return 0; } #ifdef CONFIG_PM static int ath10k_pci_suspend(struct ath10k *ar) { /* The grace timer can still be counting down and ar->ps_awake be true. * It is known that the device may be asleep after resuming regardless * of the SoC powersave state before suspending. Hence make sure the * device is asleep before proceeding. */ ath10k_pci_sleep_sync(ar); return 0; } #endif static int ath10k_pci_hif_resume(struct ath10k *ar) { /* Nothing to do; the important stuff is in the driver resume. */ return 0; } #ifdef CONFIG_PM static int ath10k_pci_resume(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct pci_dev *pdev = ar_pci->pdev; u32 val; int ret = 0; ret = ath10k_pci_force_wake(ar); if (ret) { ath10k_err(ar, "failed to wake up target: %d\n", ret); return ret; } /* Suspend/Resume resets the PCI configuration space, so we have to * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries * from interfering with C3 CPU state. pci_restore_state won't help * here since it only restores the first 64 bytes pci config header. */ pci_read_config_dword(pdev, 0x40, &val); if ((val & 0x0000ff00) != 0) pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); return ret; } #endif static bool ath10k_pci_validate_cal(void *data, size_t size) { __le16 *cal_words = data; u16 checksum = 0; size_t i; if (size % 2 != 0) return false; for (i = 0; i < size / 2; i++) checksum ^= le16_to_cpu(cal_words[i]); return checksum == 0xffff; } static void ath10k_pci_enable_eeprom(struct ath10k *ar) { /* Enable SI clock */ ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0); /* Configure GPIOs for I2C operation */ ath10k_pci_write32(ar, GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN, SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, GPIO_PIN0_CONFIG) | SM(1, GPIO_PIN0_PAD_PULL)); ath10k_pci_write32(ar, GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 4 * QCA9887_1_0_SI_CLK_GPIO_PIN, SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | SM(1, GPIO_PIN0_PAD_PULL)); ath10k_pci_write32(ar, GPIO_BASE_ADDRESS + QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS, 1u << QCA9887_1_0_SI_CLK_GPIO_PIN); /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CONFIG_OFFSET, SM(1, SI_CONFIG_ERR_INT) | SM(1, SI_CONFIG_BIDIR_OD_DATA) | SM(1, SI_CONFIG_I2C) | SM(1, SI_CONFIG_POS_SAMPLE) | SM(1, SI_CONFIG_INACTIVE_DATA) | SM(1, SI_CONFIG_INACTIVE_CLK) | SM(8, SI_CONFIG_DIVIDER)); } static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) { u32 reg; int wait_limit; /* set device select byte and for the read operation */ reg = QCA9887_EEPROM_SELECT_READ | SM(addr, QCA9887_EEPROM_ADDR_LO) | SM(addr >> 8, QCA9887_EEPROM_ADDR_HI); ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); /* write transmit data, transfer length, and START bit */ ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) | SM(4, SI_CS_TX_CNT)); /* wait max 1 sec */ wait_limit = 100000; /* wait for SI_CS_DONE_INT */ do { reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); if (MS(reg, SI_CS_DONE_INT)) break; wait_limit--; udelay(10); } while (wait_limit > 0); if (!MS(reg, SI_CS_DONE_INT)) { ath10k_err(ar, "timeout while reading device EEPROM at %04x\n", addr); return -ETIMEDOUT; } /* clear SI_CS_DONE_INT */ ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); if (MS(reg, SI_CS_DONE_ERR)) { ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr); return -EIO; } /* extract receive data */ reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); *out = reg; return 0; } static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, size_t *data_len) { u8 *caldata = NULL; size_t calsize, i; int ret; if (!QCA_REV_9887(ar)) return -EOPNOTSUPP; calsize = ar->hw_params.cal_data_len; caldata = kmalloc(calsize, GFP_KERNEL); if (!caldata) return -ENOMEM; ath10k_pci_enable_eeprom(ar); for (i = 0; i < calsize; i++) { ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]); if (ret) goto err_free; } if (!ath10k_pci_validate_cal(caldata, calsize)) goto err_free; *data = caldata; *data_len = calsize; return 0; err_free: kfree(caldata); return -EINVAL; } static const struct ath10k_hif_ops ath10k_pci_hif_ops = { .tx_sg = ath10k_pci_hif_tx_sg, .diag_read = ath10k_pci_hif_diag_read, .diag_write = ath10k_pci_diag_write_mem, .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, .start = ath10k_pci_hif_start, .stop = ath10k_pci_hif_stop, .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, .get_default_pipe = ath10k_pci_hif_get_default_pipe, .send_complete_check = ath10k_pci_hif_send_complete_check, .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, .power_up = ath10k_pci_hif_power_up, .power_down = ath10k_pci_hif_power_down, .read32 = ath10k_pci_read32, .write32 = ath10k_pci_write32, .suspend = ath10k_pci_hif_suspend, .resume = ath10k_pci_hif_resume, .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom, }; /* * Top-level interrupt handler for all PCI interrupts from a Target. * When a block of MSI interrupts is allocated, this top-level handler * is not used; instead, we directly call the correct sub-handler. */ static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) { struct ath10k *ar = arg; struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int ret; if (ath10k_pci_has_device_gone(ar)) return IRQ_NONE; ret = ath10k_pci_force_wake(ar); if (ret) { ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret); return IRQ_NONE; } if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) && !ath10k_pci_irq_pending(ar)) return IRQ_NONE; ath10k_pci_disable_and_clear_legacy_irq(ar); ath10k_pci_irq_msi_fw_mask(ar); napi_schedule(&ar->napi); return IRQ_HANDLED; } static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) { struct ath10k *ar = container_of(ctx, struct ath10k, napi); int done = 0; if (ath10k_pci_has_fw_crashed(ar)) { ath10k_pci_fw_crashed_clear(ar); ath10k_pci_fw_crashed_dump(ar); napi_complete(ctx); return done; } ath10k_ce_per_engine_service_any(ar); done = ath10k_htt_txrx_compl_task(ar, budget); if (done < budget) { napi_complete_done(ctx, done); /* In case of MSI, it is possible that interrupts are received * while NAPI poll is inprogress. So pending interrupts that are * received after processing all copy engine pipes by NAPI poll * will not be handled again. This is causing failure to * complete boot sequence in x86 platform. So before enabling * interrupts safer to check for pending interrupts for * immediate servicing. */ if (ath10k_ce_interrupt_summary(ar)) { napi_reschedule(ctx); goto out; } ath10k_pci_enable_legacy_irq(ar); ath10k_pci_irq_msi_fw_unmask(ar); } out: return done; } static int ath10k_pci_request_irq_msi(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int ret; ret = request_irq(ar_pci->pdev->irq, ath10k_pci_interrupt_handler, IRQF_SHARED, "ath10k_pci", ar); if (ret) { ath10k_warn(ar, "failed to request MSI irq %d: %d\n", ar_pci->pdev->irq, ret); return ret; } return 0; } static int ath10k_pci_request_irq_legacy(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int ret; ret = request_irq(ar_pci->pdev->irq, ath10k_pci_interrupt_handler, IRQF_SHARED, "ath10k_pci", ar); if (ret) { ath10k_warn(ar, "failed to request legacy irq %d: %d\n", ar_pci->pdev->irq, ret); return ret; } return 0; } static int ath10k_pci_request_irq(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); switch (ar_pci->oper_irq_mode) { case ATH10K_PCI_IRQ_LEGACY: return ath10k_pci_request_irq_legacy(ar); case ATH10K_PCI_IRQ_MSI: return ath10k_pci_request_irq_msi(ar); default: return -EINVAL; } } static void ath10k_pci_free_irq(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); free_irq(ar_pci->pdev->irq, ar); } void ath10k_pci_init_napi(struct ath10k *ar) { netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll); } static int ath10k_pci_init_irq(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); int ret; ath10k_pci_init_napi(ar); if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) ath10k_info(ar, "limiting irq mode to: %d\n", ath10k_pci_irq_mode); /* Try MSI */ if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; ret = pci_enable_msi(ar_pci->pdev); if (ret == 0) return 0; /* MHI failed, try legacy irq next */ } /* Try legacy irq * * A potential race occurs here: The CORE_BASE write * depends on target correctly decoding AXI address but * host won't know when target writes BAR to CORE_CTRL. * This write might get lost if target has NOT written BAR. * For now, fix the race by repeating the write in below * synchronization checking. */ ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); return 0; } static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) { ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 0); } static int ath10k_pci_deinit_irq(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); switch (ar_pci->oper_irq_mode) { case ATH10K_PCI_IRQ_LEGACY: ath10k_pci_deinit_irq_legacy(ar); break; default: pci_disable_msi(ar_pci->pdev); break; } return 0; } int ath10k_pci_wait_for_target_init(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); unsigned long timeout; u32 val; ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); do { val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", val); /* target should never return this */ if (val == 0xffffffff) continue; /* the device has crashed so don't bother trying anymore */ if (val & FW_IND_EVENT_PENDING) break; if (val & FW_IND_INITIALIZED) break; if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) /* Fix potential race by repeating CORE_BASE writes */ ath10k_pci_enable_legacy_irq(ar); mdelay(10); } while (time_before(jiffies, timeout)); ath10k_pci_disable_and_clear_legacy_irq(ar); ath10k_pci_irq_msi_fw_mask(ar); if (val == 0xffffffff) { ath10k_err(ar, "failed to read device register, device is gone\n"); return -EIO; } if (val & FW_IND_EVENT_PENDING) { ath10k_warn(ar, "device has crashed during init\n"); return -ECOMM; } if (!(val & FW_IND_INITIALIZED)) { ath10k_err(ar, "failed to receive initialized event from target: %08x\n", val); return -ETIMEDOUT; } ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); return 0; } static int ath10k_pci_cold_reset(struct ath10k *ar) { u32 val; ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); spin_lock_bh(&ar->data_lock); ar->stats.fw_cold_reset_counter++; spin_unlock_bh(&ar->data_lock); /* Put Target, including PCIe, into RESET. */ val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); val |= 1; ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); /* After writing into SOC_GLOBAL_RESET to put device into * reset and pulling out of reset pcie may not be stable * for any immediate pcie register access and cause bus error, * add delay before any pcie access request to fix this issue. */ msleep(20); /* Pull Target, including PCIe, out of RESET. */ val &= ~1; ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); msleep(20); ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); return 0; } static int ath10k_pci_claim(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct pci_dev *pdev = ar_pci->pdev; int ret; pci_set_drvdata(pdev, ar); ret = pci_enable_device(pdev); if (ret) { ath10k_err(ar, "failed to enable pci device: %d\n", ret); return ret; } ret = pci_request_region(pdev, BAR_NUM, "ath"); if (ret) { ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, ret); goto err_device; } /* Target expects 32 bit DMA. Enforce it. */ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); if (ret) { ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); goto err_region; } pci_set_master(pdev); #if defined(__FreeBSD__) linuxkpi_pcim_want_to_use_bus_functions(pdev); #endif /* Arrange for access to Target SoC registers. */ ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); if (!ar_pci->mem) { ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); ret = -EIO; goto err_region; } ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem); return 0; err_region: pci_release_region(pdev, BAR_NUM); err_device: pci_disable_device(pdev); return ret; } static void ath10k_pci_release(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct pci_dev *pdev = ar_pci->pdev; pci_iounmap(pdev, ar_pci->mem); pci_release_region(pdev, BAR_NUM); pci_disable_device(pdev); } static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) { const struct ath10k_pci_supp_chip *supp_chip; int i; u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { supp_chip = &ath10k_pci_supp_chips[i]; if (supp_chip->dev_id == dev_id && supp_chip->rev_id == rev_id) return true; } return false; } int ath10k_pci_setup_resource(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar); int ret; spin_lock_init(&ce->ce_lock); spin_lock_init(&ar_pci->ps_lock); mutex_init(&ar_pci->ce_diag_mutex); INIT_WORK(&ar_pci->dump_work, ath10k_pci_fw_dump_work); timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0); ar_pci->attr = kmemdup(pci_host_ce_config_wlan, sizeof(pci_host_ce_config_wlan), GFP_KERNEL); if (!ar_pci->attr) return -ENOMEM; ar_pci->pipe_config = kmemdup(pci_target_ce_config_wlan, sizeof(pci_target_ce_config_wlan), GFP_KERNEL); if (!ar_pci->pipe_config) { ret = -ENOMEM; goto err_free_attr; } ar_pci->serv_to_pipe = kmemdup(pci_target_service_to_ce_map_wlan, sizeof(pci_target_service_to_ce_map_wlan), GFP_KERNEL); if (!ar_pci->serv_to_pipe) { ret = -ENOMEM; goto err_free_pipe_config; } if (QCA_REV_6174(ar) || QCA_REV_9377(ar)) ath10k_pci_override_ce_config(ar); ret = ath10k_pci_alloc_pipes(ar); if (ret) { ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", ret); goto err_free_serv_to_pipe; } return 0; err_free_serv_to_pipe: kfree(ar_pci->serv_to_pipe); err_free_pipe_config: kfree(ar_pci->pipe_config); err_free_attr: kfree(ar_pci->attr); return ret; } void ath10k_pci_release_resource(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); ath10k_pci_rx_retry_sync(ar); netif_napi_del(&ar->napi); ath10k_pci_ce_deinit(ar); ath10k_pci_free_pipes(ar); kfree(ar_pci->attr); kfree(ar_pci->pipe_config); kfree(ar_pci->serv_to_pipe); } static const struct ath10k_bus_ops ath10k_pci_bus_ops = { .read32 = ath10k_bus_pci_read32, .write32 = ath10k_bus_pci_write32, .get_num_banks = ath10k_pci_get_num_banks, }; static int ath10k_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pci_dev) { int ret = 0; struct ath10k *ar; struct ath10k_pci *ar_pci; enum ath10k_hw_rev hw_rev; struct ath10k_bus_params bus_params = {}; bool pci_ps, is_qca988x = false; int (*pci_soft_reset)(struct ath10k *ar); int (*pci_hard_reset)(struct ath10k *ar); u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); switch (pci_dev->device) { case QCA988X_2_0_DEVICE_ID_UBNT: case QCA988X_2_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA988X; pci_ps = false; is_qca988x = true; pci_soft_reset = ath10k_pci_warm_reset; pci_hard_reset = ath10k_pci_qca988x_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; break; case QCA9887_1_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA9887; pci_ps = false; pci_soft_reset = ath10k_pci_warm_reset; pci_hard_reset = ath10k_pci_qca988x_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; break; case QCA6164_2_1_DEVICE_ID: case QCA6174_2_1_DEVICE_ID: hw_rev = ATH10K_HW_QCA6174; pci_ps = true; pci_soft_reset = ath10k_pci_warm_reset; pci_hard_reset = ath10k_pci_qca6174_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; break; case QCA99X0_2_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA99X0; pci_ps = false; pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; case QCA9984_1_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA9984; pci_ps = false; pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; case QCA9888_2_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA9888; pci_ps = false; pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; case QCA9377_1_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA9377; pci_ps = true; pci_soft_reset = ath10k_pci_warm_reset; pci_hard_reset = ath10k_pci_qca6174_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; break; default: WARN_ON(1); return -ENOTSUPP; } ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, hw_rev, &ath10k_pci_hif_ops); if (!ar) { dev_err(&pdev->dev, "failed to allocate core\n"); return -ENOMEM; } ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, pdev->subsystem_device); ar_pci = ath10k_pci_priv(ar); ar_pci->pdev = pdev; ar_pci->dev = &pdev->dev; ar_pci->ar = ar; ar->dev_id = pci_dev->device; ar_pci->pci_ps = pci_ps; ar_pci->ce.bus_ops = &ath10k_pci_bus_ops; ar_pci->pci_soft_reset = pci_soft_reset; ar_pci->pci_hard_reset = pci_hard_reset; ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; ar->ce_priv = &ar_pci->ce; ar->id.vendor = pdev->vendor; ar->id.device = pdev->device; ar->id.subsystem_vendor = pdev->subsystem_vendor; ar->id.subsystem_device = pdev->subsystem_device; timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0); ret = ath10k_pci_setup_resource(ar); if (ret) { ath10k_err(ar, "failed to setup resource: %d\n", ret); goto err_core_destroy; } ret = ath10k_pci_claim(ar); if (ret) { ath10k_err(ar, "failed to claim device: %d\n", ret); goto err_free_pipes; } ret = ath10k_pci_force_wake(ar); if (ret) { ath10k_warn(ar, "failed to wake up device : %d\n", ret); goto err_sleep; } ath10k_pci_ce_deinit(ar); ath10k_pci_irq_disable(ar); ret = ath10k_pci_init_irq(ar); if (ret) { ath10k_err(ar, "failed to init irqs: %d\n", ret); goto err_sleep; } ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n", ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, ath10k_pci_irq_mode, ath10k_pci_reset_mode); ret = ath10k_pci_request_irq(ar); if (ret) { ath10k_warn(ar, "failed to request irqs: %d\n", ret); goto err_deinit_irq; } bus_params.dev_type = ATH10K_DEV_TYPE_LL; bus_params.link_can_suspend = true; /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that * fall off the bus during chip_reset. These chips have the same pci * device id as the QCA9880 BR4A or 2R4E. So that's why the check. */ if (is_qca988x) { bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); if (bus_params.chip_id != 0xffffffff) { if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { ret = -ENODEV; goto err_unsupported; } } } ret = ath10k_pci_chip_reset(ar); if (ret) { ath10k_err(ar, "failed to reset chip: %d\n", ret); goto err_free_irq; } bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); if (bus_params.chip_id == 0xffffffff) { ret = -ENODEV; goto err_unsupported; } if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { ret = -ENODEV; goto err_unsupported; } ret = ath10k_core_register(ar, &bus_params); if (ret) { ath10k_err(ar, "failed to register driver core: %d\n", ret); goto err_free_irq; } return 0; err_unsupported: ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", pdev->device, bus_params.chip_id); err_free_irq: ath10k_pci_free_irq(ar); err_deinit_irq: ath10k_pci_release_resource(ar); err_sleep: ath10k_pci_sleep_sync(ar); ath10k_pci_release(ar); err_free_pipes: ath10k_pci_free_pipes(ar); err_core_destroy: ath10k_core_destroy(ar); return ret; } static void ath10k_pci_remove(struct pci_dev *pdev) { struct ath10k *ar = pci_get_drvdata(pdev); ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); if (!ar) return; ath10k_core_unregister(ar); ath10k_pci_free_irq(ar); ath10k_pci_deinit_irq(ar); ath10k_pci_release_resource(ar); ath10k_pci_sleep_sync(ar); ath10k_pci_release(ar); ath10k_core_destroy(ar); } MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); #ifdef CONFIG_PM static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev) { struct ath10k *ar = dev_get_drvdata(dev); int ret; ret = ath10k_pci_suspend(ar); if (ret) ath10k_warn(ar, "failed to suspend hif: %d\n", ret); return ret; } static __maybe_unused int ath10k_pci_pm_resume(struct device *dev) { struct ath10k *ar = dev_get_drvdata(dev); int ret; ret = ath10k_pci_resume(ar); if (ret) ath10k_warn(ar, "failed to resume hif: %d\n", ret); return ret; } static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops, ath10k_pci_pm_suspend, ath10k_pci_pm_resume); #endif static struct pci_driver ath10k_pci_driver = { .name = "ath10k_pci", .id_table = ath10k_pci_id_table, .probe = ath10k_pci_probe, .remove = ath10k_pci_remove, #ifdef CONFIG_PM .driver.pm = &ath10k_pci_pm_ops, #endif #if defined(__FreeBSD__) .bsddriver.name = KBUILD_MODNAME, /* Allow a possible native driver to attach. */ .bsd_probe_return = (BUS_PROBE_DEFAULT - 1), #endif }; static int __init ath10k_pci_init(void) { int ret1, ret2; ret1 = pci_register_driver(&ath10k_pci_driver); if (ret1) printk(KERN_ERR "failed to register ath10k pci driver: %d\n", ret1); ret2 = ath10k_ahb_init(); if (ret2) printk(KERN_ERR "ahb init failed: %d\n", ret2); if (ret1 && ret2) return ret1; /* registered to at least one bus */ return 0; } module_init(ath10k_pci_init); static void __exit ath10k_pci_exit(void) { pci_unregister_driver(&ath10k_pci_driver); ath10k_ahb_exit(); } module_exit(ath10k_pci_exit); MODULE_AUTHOR("Qualcomm Atheros"); MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices"); MODULE_LICENSE("Dual BSD/GPL"); #if defined(__FreeBSD__) MODULE_VERSION(ath10k_pci, 1); MODULE_DEPEND(ath10k_pci, linuxkpi, 1, 1, 1); MODULE_DEPEND(ath10k_pci, linuxkpi_wlan, 1, 1, 1); MODULE_DEPEND(ath10k_pci, athk_common, 1, 1, 1); #ifdef CONFIG_ATH10K_DEBUGFS MODULE_DEPEND(ath10k_pci, debugfs, 1, 1, 1); #endif #endif /* QCA988x 2.0 firmware files */ MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE); MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE); MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); /* QCA9887 1.0 firmware files */ MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE); MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); /* QCA6174 2.1 firmware files */ MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE); MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE); MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE); MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE); /* QCA6174 3.1 firmware files */ MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE); MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE); MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE); MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE); MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); /* QCA9377 1.0 firmware files */ MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE); MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE); diff --git a/sys/contrib/dev/rtw89/pci.c b/sys/contrib/dev/rtw89/pci.c index 9220f5b40d29..5639a52c2ddc 100644 --- a/sys/contrib/dev/rtw89/pci.c +++ b/sys/contrib/dev/rtw89/pci.c @@ -1,4031 +1,4034 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* Copyright(c) 2020 Realtek Corporation */ #if defined(__FreeBSD__) #define LINUXKPI_PARAM_PREFIX rtw89_pci_ #endif #include +#if defined(__FreeBSD__) +#include +#endif #include "mac.h" #include "pci.h" #include "reg.h" #include "ser.h" static bool rtw89_pci_disable_clkreq; static bool rtw89_pci_disable_aspm_l1; static bool rtw89_pci_disable_l1ss; module_param_named(disable_clkreq, rtw89_pci_disable_clkreq, bool, 0644); module_param_named(disable_aspm_l1, rtw89_pci_disable_aspm_l1, bool, 0644); module_param_named(disable_aspm_l1ss, rtw89_pci_disable_l1ss, bool, 0644); MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support"); MODULE_PARM_DESC(disable_aspm_l1, "Set Y to disable PCI ASPM L1 support"); MODULE_PARM_DESC(disable_aspm_l1ss, "Set Y to disable PCI L1SS support"); static int rtw89_pci_rst_bdram_pcie(struct rtw89_dev *rtwdev) { u32 val; int ret; rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) | B_AX_RST_BDRAM); ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_RST_BDRAM), 1, RTW89_PCI_POLL_BDRAM_RST_CNT, false, rtwdev, R_AX_PCIE_INIT_CFG1); if (ret) return -EBUSY; return 0; } static u32 rtw89_pci_dma_recalc(struct rtw89_dev *rtwdev, struct rtw89_pci_dma_ring *bd_ring, u32 cur_idx, bool tx) { u32 cnt, cur_rp, wp, rp, len; rp = bd_ring->rp; wp = bd_ring->wp; len = bd_ring->len; cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); if (tx) cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp); else cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp); bd_ring->rp = cur_rp; return cnt; } static u32 rtw89_pci_txbd_recalc(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) { struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; u32 addr_idx = bd_ring->addr.idx; u32 cnt, idx; idx = rtw89_read32(rtwdev, addr_idx); cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, true); return cnt; } static void rtw89_pci_release_fwcmd(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci, u32 cnt, bool release_all) { struct rtw89_pci_tx_data *tx_data; struct sk_buff *skb; u32 qlen; while (cnt--) { skb = skb_dequeue(&rtwpci->h2c_queue); if (!skb) { rtw89_err(rtwdev, "failed to pre-release fwcmd\n"); return; } skb_queue_tail(&rtwpci->h2c_release_queue, skb); } qlen = skb_queue_len(&rtwpci->h2c_release_queue); if (!release_all) qlen = qlen > RTW89_PCI_MULTITAG ? qlen - RTW89_PCI_MULTITAG : 0; while (qlen--) { skb = skb_dequeue(&rtwpci->h2c_release_queue); if (!skb) { rtw89_err(rtwdev, "failed to release fwcmd\n"); return; } tx_data = RTW89_PCI_TX_SKB_CB(skb); dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, DMA_TO_DEVICE); dev_kfree_skb_any(skb); } } static void rtw89_pci_reclaim_tx_fwcmd(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) { struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; u32 cnt; cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); if (!cnt) return; rtw89_pci_release_fwcmd(rtwdev, rtwpci, cnt, false); } static u32 rtw89_pci_rxbd_recalc(struct rtw89_dev *rtwdev, struct rtw89_pci_rx_ring *rx_ring) { struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; u32 addr_idx = bd_ring->addr.idx; u32 cnt, idx; idx = rtw89_read32(rtwdev, addr_idx); cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, false); return cnt; } static void rtw89_pci_sync_skb_for_cpu(struct rtw89_dev *rtwdev, struct sk_buff *skb) { struct rtw89_pci_rx_info *rx_info; dma_addr_t dma; rx_info = RTW89_PCI_RX_SKB_CB(skb); dma = rx_info->dma; dma_sync_single_for_cpu(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, DMA_FROM_DEVICE); } static void rtw89_pci_sync_skb_for_device(struct rtw89_dev *rtwdev, struct sk_buff *skb) { struct rtw89_pci_rx_info *rx_info; dma_addr_t dma; rx_info = RTW89_PCI_RX_SKB_CB(skb); dma = rx_info->dma; dma_sync_single_for_device(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, DMA_FROM_DEVICE); } static int rtw89_pci_rxbd_info_update(struct rtw89_dev *rtwdev, struct sk_buff *skb) { struct rtw89_pci_rxbd_info *rxbd_info; struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb); rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data; rx_info->fs = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_FS); rx_info->ls = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_LS); rx_info->len = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_WRITE_SIZE); rx_info->tag = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_TAG); return 0; } static void rtw89_pci_ctrl_txdma_ch_pcie(struct rtw89_dev *rtwdev, bool enable) { const struct rtw89_pci_info *info = rtwdev->pci_info; const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1; const struct rtw89_reg_def *dma_stop2 = &info->dma_stop2; if (enable) { rtw89_write32_clr(rtwdev, dma_stop1->addr, dma_stop1->mask); if (dma_stop2->addr) rtw89_write32_clr(rtwdev, dma_stop2->addr, dma_stop2->mask); } else { rtw89_write32_set(rtwdev, dma_stop1->addr, dma_stop1->mask); if (dma_stop2->addr) rtw89_write32_set(rtwdev, dma_stop2->addr, dma_stop2->mask); } } static void rtw89_pci_ctrl_txdma_fw_ch_pcie(struct rtw89_dev *rtwdev, bool enable) { const struct rtw89_pci_info *info = rtwdev->pci_info; const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1; if (enable) rtw89_write32_clr(rtwdev, dma_stop1->addr, B_AX_STOP_CH12); else rtw89_write32_set(rtwdev, dma_stop1->addr, B_AX_STOP_CH12); } static bool rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls, struct sk_buff *new, const struct sk_buff *skb, u32 offset, const struct rtw89_pci_rx_info *rx_info, const struct rtw89_rx_desc_info *desc_info) { u32 copy_len = rx_info->len - offset; if (unlikely(skb_tailroom(new) < copy_len)) { rtw89_debug(rtwdev, RTW89_DBG_TXRX, "invalid rx data length bd_len=%d desc_len=%d offset=%d (fs=%d ls=%d)\n", rx_info->len, desc_info->pkt_size, offset, fs, ls); rtw89_hex_dump(rtwdev, RTW89_DBG_TXRX, "rx_data: ", skb->data, rx_info->len); /* length of a single segment skb is desc_info->pkt_size */ if (fs && ls) { copy_len = desc_info->pkt_size; } else { rtw89_info(rtwdev, "drop rx data due to invalid length\n"); return false; } } skb_put_data(new, skb->data + offset, copy_len); return true; } static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev, struct rtw89_pci_rx_ring *rx_ring) { struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; struct rtw89_pci_rx_info *rx_info; struct rtw89_rx_desc_info *desc_info = &rx_ring->diliver_desc; struct sk_buff *new = rx_ring->diliver_skb; struct sk_buff *skb; u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); u32 offset; u32 cnt = 1; bool fs, ls; int ret; skb = rx_ring->buf[bd_ring->wp]; rtw89_pci_sync_skb_for_cpu(rtwdev, skb); ret = rtw89_pci_rxbd_info_update(rtwdev, skb); if (ret) { rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", bd_ring->wp, ret); goto err_sync_device; } rx_info = RTW89_PCI_RX_SKB_CB(skb); fs = rx_info->fs; ls = rx_info->ls; if (fs) { if (new) { rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "skb should not be ready before first segment start\n"); goto err_sync_device; } if (desc_info->ready) { rtw89_warn(rtwdev, "desc info should not be ready before first segment start\n"); goto err_sync_device; } rtw89_chip_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size); new = rtw89_alloc_skb_for_rx(rtwdev, desc_info->pkt_size); if (!new) goto err_sync_device; rx_ring->diliver_skb = new; /* first segment has RX desc */ offset = desc_info->offset + desc_info->rxd_len; } else { offset = sizeof(struct rtw89_pci_rxbd_info); if (!new) { rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "no last skb\n"); goto err_sync_device; } } if (!rtw89_skb_put_rx_data(rtwdev, fs, ls, new, skb, offset, rx_info, desc_info)) goto err_sync_device; rtw89_pci_sync_skb_for_device(rtwdev, skb); rtw89_pci_rxbd_increase(rx_ring, 1); if (!desc_info->ready) { rtw89_warn(rtwdev, "no rx desc information\n"); goto err_free_resource; } if (ls) { rtw89_core_rx(rtwdev, desc_info, new); rx_ring->diliver_skb = NULL; desc_info->ready = false; } return cnt; err_sync_device: rtw89_pci_sync_skb_for_device(rtwdev, skb); rtw89_pci_rxbd_increase(rx_ring, 1); err_free_resource: if (new) dev_kfree_skb_any(new); rx_ring->diliver_skb = NULL; desc_info->ready = false; return cnt; } static void rtw89_pci_rxbd_deliver(struct rtw89_dev *rtwdev, struct rtw89_pci_rx_ring *rx_ring, u32 cnt) { struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; u32 rx_cnt; while (cnt && rtwdev->napi_budget_countdown > 0) { rx_cnt = rtw89_pci_rxbd_deliver_skbs(rtwdev, rx_ring); if (!rx_cnt) { rtw89_err(rtwdev, "failed to deliver RXBD skb\n"); /* skip the rest RXBD bufs */ rtw89_pci_rxbd_increase(rx_ring, cnt); break; } cnt -= rx_cnt; } rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp); } static int rtw89_pci_poll_rxq_dma(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci, int budget) { struct rtw89_pci_rx_ring *rx_ring; int countdown = rtwdev->napi_budget_countdown; u32 cnt; rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ]; cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); if (!cnt) return 0; cnt = min_t(u32, budget, cnt); rtw89_pci_rxbd_deliver(rtwdev, rx_ring, cnt); /* In case of flushing pending SKBs, the countdown may exceed. */ if (rtwdev->napi_budget_countdown <= 0) return budget; return budget - countdown; } static void rtw89_pci_tx_status(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, struct sk_buff *skb, u8 tx_status) { struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); struct ieee80211_tx_info *info; rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status == RTW89_TX_DONE); info = IEEE80211_SKB_CB(skb); ieee80211_tx_info_clear_status(info); if (info->flags & IEEE80211_TX_CTL_NO_ACK) info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; if (tx_status == RTW89_TX_DONE) { info->flags |= IEEE80211_TX_STAT_ACK; tx_ring->tx_acked++; } else { if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) rtw89_debug(rtwdev, RTW89_DBG_FW, "failed to TX of status %x\n", tx_status); switch (tx_status) { case RTW89_TX_RETRY_LIMIT: tx_ring->tx_retry_lmt++; break; case RTW89_TX_LIFE_TIME: tx_ring->tx_life_time++; break; case RTW89_TX_MACID_DROP: tx_ring->tx_mac_id_drop++; break; default: rtw89_warn(rtwdev, "invalid TX status %x\n", tx_status); break; } } ieee80211_tx_status_ni(rtwdev->hw, skb); } static void rtw89_pci_reclaim_txbd(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) { struct rtw89_pci_tx_wd *txwd; u32 cnt; cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); while (cnt--) { txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); if (!txwd) { rtw89_warn(rtwdev, "No busy txwd pages available\n"); break; } list_del_init(&txwd->list); /* this skb has been freed by RPP */ if (skb_queue_len(&txwd->queue) == 0) rtw89_pci_enqueue_txwd(tx_ring, txwd); } } static void rtw89_pci_release_busy_txwd(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) { struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; struct rtw89_pci_tx_wd *txwd; int i; for (i = 0; i < wd_ring->page_num; i++) { txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); if (!txwd) break; list_del_init(&txwd->list); } } static void rtw89_pci_release_txwd_skb(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, struct rtw89_pci_tx_wd *txwd, u16 seq, u8 tx_status) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_tx_data *tx_data; struct sk_buff *skb, *tmp; u8 txch = tx_ring->txch; if (!list_empty(&txwd->list)) { rtw89_pci_reclaim_txbd(rtwdev, tx_ring); /* In low power mode, RPP can receive before updating of TX BD. * In normal mode, it should not happen so give it a warning. */ if (!rtwpci->low_power && !list_empty(&txwd->list)) rtw89_warn(rtwdev, "queue %d txwd %d is not idle\n", txch, seq); } skb_queue_walk_safe(&txwd->queue, skb, tmp) { skb_unlink(skb, &txwd->queue); tx_data = RTW89_PCI_TX_SKB_CB(skb); dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, DMA_TO_DEVICE); rtw89_pci_tx_status(rtwdev, tx_ring, skb, tx_status); } if (list_empty(&txwd->list)) rtw89_pci_enqueue_txwd(tx_ring, txwd); } static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, struct rtw89_pci_rpp_fmt *rpp) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_tx_ring *tx_ring; struct rtw89_pci_tx_wd_ring *wd_ring; struct rtw89_pci_tx_wd *txwd; u16 seq; u8 qsel, tx_status, txch; seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ); qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL); tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS); txch = rtw89_core_get_ch_dma(rtwdev, qsel); if (txch == RTW89_TXCH_CH12) { rtw89_warn(rtwdev, "should no fwcmd release report\n"); return; } tx_ring = &rtwpci->tx_rings[txch]; wd_ring = &tx_ring->wd_ring; txwd = &wd_ring->pages[seq]; rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, seq, tx_status); } static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) { struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; struct rtw89_pci_tx_wd *txwd; int i; for (i = 0; i < wd_ring->page_num; i++) { txwd = &wd_ring->pages[i]; if (!list_empty(&txwd->list)) continue; rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, i, RTW89_TX_MACID_DROP); } } static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev, struct rtw89_pci_rx_ring *rx_ring, u32 max_cnt) { struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; struct rtw89_pci_rx_info *rx_info; struct rtw89_pci_rpp_fmt *rpp; struct rtw89_rx_desc_info desc_info = {}; struct sk_buff *skb; u32 cnt = 0; u32 rpp_size = sizeof(struct rtw89_pci_rpp_fmt); u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); u32 offset; int ret; skb = rx_ring->buf[bd_ring->wp]; rtw89_pci_sync_skb_for_cpu(rtwdev, skb); ret = rtw89_pci_rxbd_info_update(rtwdev, skb); if (ret) { rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", bd_ring->wp, ret); goto err_sync_device; } rx_info = RTW89_PCI_RX_SKB_CB(skb); if (!rx_info->fs || !rx_info->ls) { rtw89_err(rtwdev, "cannot process RP frame not set FS/LS\n"); return cnt; } rtw89_chip_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size); /* first segment has RX desc */ offset = desc_info.offset + desc_info.rxd_len; for (; offset + rpp_size <= rx_info->len; offset += rpp_size) { rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset); rtw89_pci_release_rpp(rtwdev, rpp); } rtw89_pci_sync_skb_for_device(rtwdev, skb); rtw89_pci_rxbd_increase(rx_ring, 1); cnt++; return cnt; err_sync_device: rtw89_pci_sync_skb_for_device(rtwdev, skb); return 0; } static void rtw89_pci_release_tx(struct rtw89_dev *rtwdev, struct rtw89_pci_rx_ring *rx_ring, u32 cnt) { struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; u32 release_cnt; while (cnt) { release_cnt = rtw89_pci_release_tx_skbs(rtwdev, rx_ring, cnt); if (!release_cnt) { rtw89_err(rtwdev, "failed to release TX skbs\n"); /* skip the rest RXBD bufs */ rtw89_pci_rxbd_increase(rx_ring, cnt); break; } cnt -= release_cnt; } rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp); } static int rtw89_pci_poll_rpq_dma(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci, int budget) { struct rtw89_pci_rx_ring *rx_ring; u32 cnt; int work_done; rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; spin_lock_bh(&rtwpci->trx_lock); cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); if (cnt == 0) goto out_unlock; rtw89_pci_release_tx(rtwdev, rx_ring, cnt); out_unlock: spin_unlock_bh(&rtwpci->trx_lock); /* always release all RPQ */ work_done = min_t(int, cnt, budget); rtwdev->napi_budget_countdown -= work_done; return work_done; } static void rtw89_pci_isr_rxd_unavail(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) { struct rtw89_pci_rx_ring *rx_ring; struct rtw89_pci_dma_ring *bd_ring; u32 reg_idx; u16 hw_idx, hw_idx_next, host_idx; int i; for (i = 0; i < RTW89_RXCH_NUM; i++) { rx_ring = &rtwpci->rx_rings[i]; bd_ring = &rx_ring->bd_ring; reg_idx = rtw89_read32(rtwdev, bd_ring->addr.idx); hw_idx = FIELD_GET(TXBD_HW_IDX_MASK, reg_idx); host_idx = FIELD_GET(TXBD_HOST_IDX_MASK, reg_idx); hw_idx_next = (hw_idx + 1) % bd_ring->len; if (hw_idx_next == host_idx) rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "%d RXD unavailable\n", i); rtw89_debug(rtwdev, RTW89_DBG_TXRX, "%d RXD unavailable, idx=0x%08x, len=%d\n", i, reg_idx, bd_ring->len); } } void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci, struct rtw89_pci_isrs *isrs) { isrs->halt_c2h_isrs = rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs; isrs->isrs[0] = rtw89_read32(rtwdev, R_AX_PCIE_HISR00) & rtwpci->intrs[0]; isrs->isrs[1] = rtw89_read32(rtwdev, R_AX_PCIE_HISR10) & rtwpci->intrs[1]; rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs); rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isrs->isrs[0]); rtw89_write32(rtwdev, R_AX_PCIE_HISR10, isrs->isrs[1]); } EXPORT_SYMBOL(rtw89_pci_recognize_intrs); void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci, struct rtw89_pci_isrs *isrs) { isrs->ind_isrs = rtw89_read32(rtwdev, R_AX_PCIE_HISR00_V1) & rtwpci->ind_intrs; isrs->halt_c2h_isrs = isrs->ind_isrs & B_AX_HS0ISR_IND_INT_EN ? rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs : 0; isrs->isrs[0] = isrs->ind_isrs & B_AX_HCI_AXIDMA_INT_EN ? rtw89_read32(rtwdev, R_AX_HAXI_HISR00) & rtwpci->intrs[0] : 0; isrs->isrs[1] = isrs->ind_isrs & B_AX_HS1ISR_IND_INT_EN ? rtw89_read32(rtwdev, R_AX_HISR1) & rtwpci->intrs[1] : 0; if (isrs->halt_c2h_isrs) rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs); if (isrs->isrs[0]) rtw89_write32(rtwdev, R_AX_HAXI_HISR00, isrs->isrs[0]); if (isrs->isrs[1]) rtw89_write32(rtwdev, R_AX_HISR1, isrs->isrs[1]); } EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v1); static void rtw89_pci_clear_isr0(struct rtw89_dev *rtwdev, u32 isr00) { /* write 1 clear */ rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isr00); } void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) { rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs); rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, rtwpci->intrs[0]); rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, rtwpci->intrs[1]); } EXPORT_SYMBOL(rtw89_pci_enable_intr); void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) { rtw89_write32(rtwdev, R_AX_HIMR0, 0); rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, 0); rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, 0); } EXPORT_SYMBOL(rtw89_pci_disable_intr); void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) { rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, rtwpci->ind_intrs); rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs); rtw89_write32(rtwdev, R_AX_HAXI_HIMR00, rtwpci->intrs[0]); rtw89_write32(rtwdev, R_AX_HIMR1, rtwpci->intrs[1]); } EXPORT_SYMBOL(rtw89_pci_enable_intr_v1); void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) { rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, 0); } EXPORT_SYMBOL(rtw89_pci_disable_intr_v1); static void rtw89_pci_ops_recovery_start(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; unsigned long flags; spin_lock_irqsave(&rtwpci->irq_lock, flags); rtw89_chip_disable_intr(rtwdev, rtwpci); rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RECOVERY_START); rtw89_chip_enable_intr(rtwdev, rtwpci); spin_unlock_irqrestore(&rtwpci->irq_lock, flags); } static void rtw89_pci_ops_recovery_complete(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; unsigned long flags; spin_lock_irqsave(&rtwpci->irq_lock, flags); rtw89_chip_disable_intr(rtwdev, rtwpci); rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE); rtw89_chip_enable_intr(rtwdev, rtwpci); spin_unlock_irqrestore(&rtwpci->irq_lock, flags); } static void rtw89_pci_low_power_interrupt_handler(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; int budget = NAPI_POLL_WEIGHT; /* To prevent RXQ get stuck due to run out of budget. */ rtwdev->napi_budget_countdown = budget; rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, budget); rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, budget); } static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev) { struct rtw89_dev *rtwdev = dev; struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_isrs isrs; unsigned long flags; spin_lock_irqsave(&rtwpci->irq_lock, flags); rtw89_chip_recognize_intrs(rtwdev, rtwpci, &isrs); spin_unlock_irqrestore(&rtwpci->irq_lock, flags); if (unlikely(isrs.isrs[0] & B_AX_RDU_INT)) rtw89_pci_isr_rxd_unavail(rtwdev, rtwpci); if (unlikely(isrs.halt_c2h_isrs & B_AX_HALT_C2H_INT_EN)) rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev)); if (unlikely(isrs.halt_c2h_isrs & B_AX_WDT_TIMEOUT_INT_EN)) rtw89_ser_notify(rtwdev, MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT); if (unlikely(rtwpci->under_recovery)) goto enable_intr; if (unlikely(rtwpci->low_power)) { rtw89_pci_low_power_interrupt_handler(rtwdev); goto enable_intr; } if (likely(rtwpci->running)) { local_bh_disable(); napi_schedule(&rtwdev->napi); local_bh_enable(); } return IRQ_HANDLED; enable_intr: spin_lock_irqsave(&rtwpci->irq_lock, flags); if (likely(rtwpci->running)) rtw89_chip_enable_intr(rtwdev, rtwpci); spin_unlock_irqrestore(&rtwpci->irq_lock, flags); return IRQ_HANDLED; } static irqreturn_t rtw89_pci_interrupt_handler(int irq, void *dev) { struct rtw89_dev *rtwdev = dev; struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; unsigned long flags; irqreturn_t irqret = IRQ_WAKE_THREAD; spin_lock_irqsave(&rtwpci->irq_lock, flags); /* If interrupt event is on the road, it is still trigger interrupt * even we have done pci_stop() to turn off IMR. */ if (unlikely(!rtwpci->running)) { irqret = IRQ_HANDLED; goto exit; } rtw89_chip_disable_intr(rtwdev, rtwpci); exit: spin_unlock_irqrestore(&rtwpci->irq_lock, flags); return irqret; } #define DEF_TXCHADDRS_TYPE1(info, txch, v...) \ [RTW89_TXCH_##txch] = { \ .num = R_AX_##txch##_TXBD_NUM ##v, \ .idx = R_AX_##txch##_TXBD_IDX ##v, \ .bdram = R_AX_##txch##_BDRAM_CTRL ##v, \ .desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \ .desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \ } #define DEF_TXCHADDRS(info, txch, v...) \ [RTW89_TXCH_##txch] = { \ .num = R_AX_##txch##_TXBD_NUM, \ .idx = R_AX_##txch##_TXBD_IDX, \ .bdram = R_AX_##txch##_BDRAM_CTRL ##v, \ .desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \ .desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \ } #define DEF_RXCHADDRS(info, rxch, v...) \ [RTW89_RXCH_##rxch] = { \ .num = R_AX_##rxch##_RXBD_NUM ##v, \ .idx = R_AX_##rxch##_RXBD_IDX ##v, \ .desa_l = R_AX_##rxch##_RXBD_DESA_L ##v, \ .desa_h = R_AX_##rxch##_RXBD_DESA_H ##v, \ } const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set = { .tx = { DEF_TXCHADDRS(info, ACH0), DEF_TXCHADDRS(info, ACH1), DEF_TXCHADDRS(info, ACH2), DEF_TXCHADDRS(info, ACH3), DEF_TXCHADDRS(info, ACH4), DEF_TXCHADDRS(info, ACH5), DEF_TXCHADDRS(info, ACH6), DEF_TXCHADDRS(info, ACH7), DEF_TXCHADDRS(info, CH8), DEF_TXCHADDRS(info, CH9), DEF_TXCHADDRS_TYPE1(info, CH10), DEF_TXCHADDRS_TYPE1(info, CH11), DEF_TXCHADDRS(info, CH12), }, .rx = { DEF_RXCHADDRS(info, RXQ), DEF_RXCHADDRS(info, RPQ), }, }; EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set); const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1 = { .tx = { DEF_TXCHADDRS(info, ACH0, _V1), DEF_TXCHADDRS(info, ACH1, _V1), DEF_TXCHADDRS(info, ACH2, _V1), DEF_TXCHADDRS(info, ACH3, _V1), DEF_TXCHADDRS(info, ACH4, _V1), DEF_TXCHADDRS(info, ACH5, _V1), DEF_TXCHADDRS(info, ACH6, _V1), DEF_TXCHADDRS(info, ACH7, _V1), DEF_TXCHADDRS(info, CH8, _V1), DEF_TXCHADDRS(info, CH9, _V1), DEF_TXCHADDRS_TYPE1(info, CH10, _V1), DEF_TXCHADDRS_TYPE1(info, CH11, _V1), DEF_TXCHADDRS(info, CH12, _V1), }, .rx = { DEF_RXCHADDRS(info, RXQ, _V1), DEF_RXCHADDRS(info, RPQ, _V1), }, }; EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set_v1); #undef DEF_TXCHADDRS_TYPE1 #undef DEF_TXCHADDRS #undef DEF_RXCHADDRS static int rtw89_pci_get_txch_addrs(struct rtw89_dev *rtwdev, enum rtw89_tx_channel txch, const struct rtw89_pci_ch_dma_addr **addr) { const struct rtw89_pci_info *info = rtwdev->pci_info; if (txch >= RTW89_TXCH_NUM) return -EINVAL; *addr = &info->dma_addr_set->tx[txch]; return 0; } static int rtw89_pci_get_rxch_addrs(struct rtw89_dev *rtwdev, enum rtw89_rx_channel rxch, const struct rtw89_pci_ch_dma_addr **addr) { const struct rtw89_pci_info *info = rtwdev->pci_info; if (rxch >= RTW89_RXCH_NUM) return -EINVAL; *addr = &info->dma_addr_set->rx[rxch]; return 0; } static u32 rtw89_pci_get_avail_txbd_num(struct rtw89_pci_tx_ring *ring) { struct rtw89_pci_dma_ring *bd_ring = &ring->bd_ring; /* reserved 1 desc check ring is full or not */ if (bd_ring->rp > bd_ring->wp) return bd_ring->rp - bd_ring->wp - 1; return bd_ring->len - (bd_ring->wp - bd_ring->rp) - 1; } static u32 __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; u32 cnt; spin_lock_bh(&rtwpci->trx_lock); rtw89_pci_reclaim_tx_fwcmd(rtwdev, rtwpci); cnt = rtw89_pci_get_avail_txbd_num(tx_ring); spin_unlock_bh(&rtwpci->trx_lock); return cnt; } static u32 __rtw89_pci_check_and_reclaim_tx_resource_noio(struct rtw89_dev *rtwdev, u8 txch) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; u32 cnt; spin_lock_bh(&rtwpci->trx_lock); cnt = rtw89_pci_get_avail_txbd_num(tx_ring); cnt = min(cnt, wd_ring->curr_num); spin_unlock_bh(&rtwpci->trx_lock); return cnt; } static u32 __rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; const struct rtw89_chip_info *chip = rtwdev->chip; u32 bd_cnt, wd_cnt, min_cnt = 0; struct rtw89_pci_rx_ring *rx_ring; enum rtw89_debug_mask debug_mask; u32 cnt; rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; spin_lock_bh(&rtwpci->trx_lock); bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); wd_cnt = wd_ring->curr_num; if (wd_cnt == 0 || bd_cnt == 0) { cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); if (cnt) rtw89_pci_release_tx(rtwdev, rx_ring, cnt); else if (wd_cnt == 0) goto out_unlock; bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); if (bd_cnt == 0) rtw89_pci_reclaim_txbd(rtwdev, tx_ring); } bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); wd_cnt = wd_ring->curr_num; min_cnt = min(bd_cnt, wd_cnt); if (min_cnt == 0) { /* This message can be frequently shown in low power mode or * high traffic with small FIFO chips, and we have recognized it as normal * behavior, so print with mask RTW89_DBG_TXRX in these situations. */ if (rtwpci->low_power || chip->small_fifo_size) debug_mask = RTW89_DBG_TXRX; else debug_mask = RTW89_DBG_UNEXP; rtw89_debug(rtwdev, debug_mask, "still no tx resource after reclaim: wd_cnt=%d bd_cnt=%d\n", wd_cnt, bd_cnt); } out_unlock: spin_unlock_bh(&rtwpci->trx_lock); return min_cnt; } static u32 rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) { if (rtwdev->hci.paused) return __rtw89_pci_check_and_reclaim_tx_resource_noio(rtwdev, txch); if (txch == RTW89_TXCH_CH12) return __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(rtwdev); return __rtw89_pci_check_and_reclaim_tx_resource(rtwdev, txch); } static void __rtw89_pci_tx_kick_off(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; u32 host_idx, addr; spin_lock_bh(&rtwpci->trx_lock); addr = bd_ring->addr.idx; host_idx = bd_ring->wp; rtw89_write16(rtwdev, addr, host_idx); spin_unlock_bh(&rtwpci->trx_lock); } static void rtw89_pci_tx_bd_ring_update(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, int n_txbd) { struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; u32 host_idx, len; len = bd_ring->len; host_idx = bd_ring->wp + n_txbd; host_idx = host_idx < len ? host_idx : host_idx - len; bd_ring->wp = host_idx; } static void rtw89_pci_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; if (rtwdev->hci.paused) { set_bit(txch, rtwpci->kick_map); return; } __rtw89_pci_tx_kick_off(rtwdev, tx_ring); } static void rtw89_pci_tx_kick_off_pending(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_tx_ring *tx_ring; int txch; for (txch = 0; txch < RTW89_TXCH_NUM; txch++) { if (!test_and_clear_bit(txch, rtwpci->kick_map)) continue; tx_ring = &rtwpci->tx_rings[txch]; __rtw89_pci_tx_kick_off(rtwdev, tx_ring); } } static void __pci_flush_txch(struct rtw89_dev *rtwdev, u8 txch, bool drop) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; u32 cur_idx, cur_rp; u8 i; /* Because the time taked by the I/O is a bit dynamic, it's hard to * define a reasonable fixed total timeout to use read_poll_timeout* * helper. Instead, we can ensure a reasonable polling times, so we * just use for loop with udelay here. */ for (i = 0; i < 60; i++) { cur_idx = rtw89_read32(rtwdev, bd_ring->addr.idx); cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); if (cur_rp == bd_ring->wp) return; udelay(1); } if (!drop) rtw89_info(rtwdev, "timed out to flush pci txch: %d\n", txch); } static void __rtw89_pci_ops_flush_txchs(struct rtw89_dev *rtwdev, u32 txchs, bool drop) { const struct rtw89_pci_info *info = rtwdev->pci_info; u8 i; for (i = 0; i < RTW89_TXCH_NUM; i++) { /* It may be unnecessary to flush FWCMD queue. */ if (i == RTW89_TXCH_CH12) continue; if (info->tx_dma_ch_mask & BIT(i)) continue; if (txchs & BIT(i)) __pci_flush_txch(rtwdev, i, drop); } } static void rtw89_pci_ops_flush_queues(struct rtw89_dev *rtwdev, u32 queues, bool drop) { __rtw89_pci_ops_flush_txchs(rtwdev, BIT(RTW89_TXCH_NUM) - 1, drop); } u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev, void *txaddr_info_addr, u32 total_len, dma_addr_t dma, u8 *add_info_nr) { struct rtw89_pci_tx_addr_info_32 *txaddr_info = txaddr_info_addr; txaddr_info->length = cpu_to_le16(total_len); txaddr_info->option = cpu_to_le16(RTW89_PCI_ADDR_MSDU_LS | RTW89_PCI_ADDR_NUM(1)); txaddr_info->dma = cpu_to_le32(dma); *add_info_nr = 1; return sizeof(*txaddr_info); } EXPORT_SYMBOL(rtw89_pci_fill_txaddr_info); u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev, void *txaddr_info_addr, u32 total_len, dma_addr_t dma, u8 *add_info_nr) { struct rtw89_pci_tx_addr_info_32_v1 *txaddr_info = txaddr_info_addr; u32 remain = total_len; u32 len; u16 length_option; int n; for (n = 0; n < RTW89_TXADDR_INFO_NR_V1 && remain; n++) { len = remain >= TXADDR_INFO_LENTHG_V1_MAX ? TXADDR_INFO_LENTHG_V1_MAX : remain; remain -= len; length_option = FIELD_PREP(B_PCIADDR_LEN_V1_MASK, len) | FIELD_PREP(B_PCIADDR_HIGH_SEL_V1_MASK, 0) | FIELD_PREP(B_PCIADDR_LS_V1_MASK, remain == 0); txaddr_info->length_opt = cpu_to_le16(length_option); txaddr_info->dma_low_lsb = cpu_to_le16(FIELD_GET(GENMASK(15, 0), dma)); txaddr_info->dma_low_msb = cpu_to_le16(FIELD_GET(GENMASK(31, 16), dma)); dma += len; txaddr_info++; } WARN_ONCE(remain, "length overflow remain=%u total_len=%u", remain, total_len); *add_info_nr = n; return n * sizeof(*txaddr_info); } EXPORT_SYMBOL(rtw89_pci_fill_txaddr_info_v1); static int rtw89_pci_txwd_submit(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, struct rtw89_pci_tx_wd *txwd, struct rtw89_core_tx_request *tx_req) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; const struct rtw89_chip_info *chip = rtwdev->chip; struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; struct rtw89_txwd_info *txwd_info; struct rtw89_pci_tx_wp_info *txwp_info; void *txaddr_info_addr; struct pci_dev *pdev = rtwpci->pdev; struct sk_buff *skb = tx_req->skb; struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); bool en_wd_info = desc_info->en_wd_info; u32 txwd_len; u32 txwp_len; u32 txaddr_info_len; dma_addr_t dma; int ret; dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); if (dma_mapping_error(&pdev->dev, dma)) { rtw89_err(rtwdev, "failed to map skb dma data\n"); ret = -EBUSY; goto err; } tx_data->dma = dma; rcu_assign_pointer(skb_data->wait, NULL); txwp_len = sizeof(*txwp_info); txwd_len = chip->txwd_body_size; txwd_len += en_wd_info ? sizeof(*txwd_info) : 0; #if defined(__linux__) txwp_info = txwd->vaddr + txwd_len; #elif defined(__FreeBSD__) txwp_info = (struct rtw89_pci_tx_wp_info *)((u8 *)txwd->vaddr + txwd_len); #endif txwp_info->seq0 = cpu_to_le16(txwd->seq | RTW89_PCI_TXWP_VALID); txwp_info->seq1 = 0; txwp_info->seq2 = 0; txwp_info->seq3 = 0; tx_ring->tx_cnt++; #if defined(__linux__) txaddr_info_addr = txwd->vaddr + txwd_len + txwp_len; #elif defined(__FreeBSD__) txaddr_info_addr = (u8 *)txwd->vaddr + txwd_len + txwp_len; #endif txaddr_info_len = rtw89_chip_fill_txaddr_info(rtwdev, txaddr_info_addr, skb->len, dma, &desc_info->addr_info_nr); txwd->len = txwd_len + txwp_len + txaddr_info_len; rtw89_chip_fill_txdesc(rtwdev, desc_info, txwd->vaddr); skb_queue_tail(&txwd->queue, skb); return 0; err: return ret; } static int rtw89_pci_fwcmd_submit(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, struct rtw89_pci_tx_bd_32 *txbd, struct rtw89_core_tx_request *tx_req) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; const struct rtw89_chip_info *chip = rtwdev->chip; struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; void *txdesc; int txdesc_size = chip->h2c_desc_size; struct pci_dev *pdev = rtwpci->pdev; struct sk_buff *skb = tx_req->skb; struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); dma_addr_t dma; txdesc = skb_push(skb, txdesc_size); memset(txdesc, 0, txdesc_size); rtw89_chip_fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); if (dma_mapping_error(&pdev->dev, dma)) { rtw89_err(rtwdev, "failed to map fwcmd dma data\n"); return -EBUSY; } tx_data->dma = dma; txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS); txbd->length = cpu_to_le16(skb->len); txbd->dma = cpu_to_le32(tx_data->dma); skb_queue_tail(&rtwpci->h2c_queue, skb); rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); return 0; } static int rtw89_pci_txbd_submit(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, struct rtw89_pci_tx_bd_32 *txbd, struct rtw89_core_tx_request *tx_req) { struct rtw89_pci_tx_wd *txwd; int ret; /* FWCMD queue doesn't have wd pages. Instead, it submits the CMD * buffer with WD BODY only. So here we don't need to check the free * pages of the wd ring. */ if (tx_ring->txch == RTW89_TXCH_CH12) return rtw89_pci_fwcmd_submit(rtwdev, tx_ring, txbd, tx_req); txwd = rtw89_pci_dequeue_txwd(tx_ring); if (!txwd) { rtw89_err(rtwdev, "no available TXWD\n"); ret = -ENOSPC; goto err; } ret = rtw89_pci_txwd_submit(rtwdev, tx_ring, txwd, tx_req); if (ret) { rtw89_err(rtwdev, "failed to submit TXWD %d\n", txwd->seq); goto err_enqueue_wd; } list_add_tail(&txwd->list, &tx_ring->busy_pages); txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS); txbd->length = cpu_to_le16(txwd->len); txbd->dma = cpu_to_le32(txwd->paddr); rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); return 0; err_enqueue_wd: rtw89_pci_enqueue_txwd(tx_ring, txwd); err: return ret; } static int rtw89_pci_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req, u8 txch) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_tx_ring *tx_ring; struct rtw89_pci_tx_bd_32 *txbd; u32 n_avail_txbd; int ret = 0; /* check the tx type and dma channel for fw cmd queue */ if ((txch == RTW89_TXCH_CH12 || tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD) && (txch != RTW89_TXCH_CH12 || tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD)) { rtw89_err(rtwdev, "only fw cmd uses dma channel 12\n"); return -EINVAL; } tx_ring = &rtwpci->tx_rings[txch]; spin_lock_bh(&rtwpci->trx_lock); n_avail_txbd = rtw89_pci_get_avail_txbd_num(tx_ring); if (n_avail_txbd == 0) { rtw89_err(rtwdev, "no available TXBD\n"); ret = -ENOSPC; goto err_unlock; } txbd = rtw89_pci_get_next_txbd(tx_ring); ret = rtw89_pci_txbd_submit(rtwdev, tx_ring, txbd, tx_req); if (ret) { rtw89_err(rtwdev, "failed to submit TXBD\n"); goto err_unlock; } spin_unlock_bh(&rtwpci->trx_lock); return 0; err_unlock: spin_unlock_bh(&rtwpci->trx_lock); return ret; } static int rtw89_pci_ops_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req) { struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; int ret; ret = rtw89_pci_tx_write(rtwdev, tx_req, desc_info->ch_dma); if (ret) { rtw89_err(rtwdev, "failed to TX Queue %d\n", desc_info->ch_dma); return ret; } return 0; } const struct rtw89_pci_bd_ram rtw89_bd_ram_table_dual[RTW89_TXCH_NUM] = { [RTW89_TXCH_ACH0] = {.start_idx = 0, .max_num = 5, .min_num = 2}, [RTW89_TXCH_ACH1] = {.start_idx = 5, .max_num = 5, .min_num = 2}, [RTW89_TXCH_ACH2] = {.start_idx = 10, .max_num = 5, .min_num = 2}, [RTW89_TXCH_ACH3] = {.start_idx = 15, .max_num = 5, .min_num = 2}, [RTW89_TXCH_ACH4] = {.start_idx = 20, .max_num = 5, .min_num = 2}, [RTW89_TXCH_ACH5] = {.start_idx = 25, .max_num = 5, .min_num = 2}, [RTW89_TXCH_ACH6] = {.start_idx = 30, .max_num = 5, .min_num = 2}, [RTW89_TXCH_ACH7] = {.start_idx = 35, .max_num = 5, .min_num = 2}, [RTW89_TXCH_CH8] = {.start_idx = 40, .max_num = 5, .min_num = 1}, [RTW89_TXCH_CH9] = {.start_idx = 45, .max_num = 5, .min_num = 1}, [RTW89_TXCH_CH10] = {.start_idx = 50, .max_num = 5, .min_num = 1}, [RTW89_TXCH_CH11] = {.start_idx = 55, .max_num = 5, .min_num = 1}, [RTW89_TXCH_CH12] = {.start_idx = 60, .max_num = 4, .min_num = 1}, }; EXPORT_SYMBOL(rtw89_bd_ram_table_dual); const struct rtw89_pci_bd_ram rtw89_bd_ram_table_single[RTW89_TXCH_NUM] = { [RTW89_TXCH_ACH0] = {.start_idx = 0, .max_num = 5, .min_num = 2}, [RTW89_TXCH_ACH1] = {.start_idx = 5, .max_num = 5, .min_num = 2}, [RTW89_TXCH_ACH2] = {.start_idx = 10, .max_num = 5, .min_num = 2}, [RTW89_TXCH_ACH3] = {.start_idx = 15, .max_num = 5, .min_num = 2}, [RTW89_TXCH_CH8] = {.start_idx = 20, .max_num = 4, .min_num = 1}, [RTW89_TXCH_CH9] = {.start_idx = 24, .max_num = 4, .min_num = 1}, [RTW89_TXCH_CH12] = {.start_idx = 28, .max_num = 4, .min_num = 1}, }; EXPORT_SYMBOL(rtw89_bd_ram_table_single); static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; const struct rtw89_pci_info *info = rtwdev->pci_info; const struct rtw89_pci_bd_ram *bd_ram_table = *info->bd_ram_table; struct rtw89_pci_tx_ring *tx_ring; struct rtw89_pci_rx_ring *rx_ring; struct rtw89_pci_dma_ring *bd_ring; const struct rtw89_pci_bd_ram *bd_ram; u32 addr_num; u32 addr_bdram; u32 addr_desa_l; u32 val32; int i; for (i = 0; i < RTW89_TXCH_NUM; i++) { if (info->tx_dma_ch_mask & BIT(i)) continue; tx_ring = &rtwpci->tx_rings[i]; bd_ring = &tx_ring->bd_ring; bd_ram = &bd_ram_table[i]; addr_num = bd_ring->addr.num; addr_bdram = bd_ring->addr.bdram; addr_desa_l = bd_ring->addr.desa_l; bd_ring->wp = 0; bd_ring->rp = 0; val32 = FIELD_PREP(BDRAM_SIDX_MASK, bd_ram->start_idx) | FIELD_PREP(BDRAM_MAX_MASK, bd_ram->max_num) | FIELD_PREP(BDRAM_MIN_MASK, bd_ram->min_num); rtw89_write16(rtwdev, addr_num, bd_ring->len); rtw89_write32(rtwdev, addr_bdram, val32); rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); } for (i = 0; i < RTW89_RXCH_NUM; i++) { rx_ring = &rtwpci->rx_rings[i]; bd_ring = &rx_ring->bd_ring; addr_num = bd_ring->addr.num; addr_desa_l = bd_ring->addr.desa_l; bd_ring->wp = 0; bd_ring->rp = 0; rx_ring->diliver_skb = NULL; rx_ring->diliver_desc.ready = false; rtw89_write16(rtwdev, addr_num, bd_ring->len); rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); } } static void rtw89_pci_release_tx_ring(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) { rtw89_pci_release_busy_txwd(rtwdev, tx_ring); rtw89_pci_release_pending_txwd_skb(rtwdev, tx_ring); } static void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; const struct rtw89_pci_info *info = rtwdev->pci_info; int txch; rtw89_pci_reset_trx_rings(rtwdev); spin_lock_bh(&rtwpci->trx_lock); for (txch = 0; txch < RTW89_TXCH_NUM; txch++) { if (info->tx_dma_ch_mask & BIT(txch)) continue; if (txch == RTW89_TXCH_CH12) { rtw89_pci_release_fwcmd(rtwdev, rtwpci, skb_queue_len(&rtwpci->h2c_queue), true); continue; } rtw89_pci_release_tx_ring(rtwdev, &rtwpci->tx_rings[txch]); } spin_unlock_bh(&rtwpci->trx_lock); } static void rtw89_pci_enable_intr_lock(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; unsigned long flags; spin_lock_irqsave(&rtwpci->irq_lock, flags); rtwpci->running = true; rtw89_chip_enable_intr(rtwdev, rtwpci); spin_unlock_irqrestore(&rtwpci->irq_lock, flags); } static void rtw89_pci_disable_intr_lock(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; unsigned long flags; spin_lock_irqsave(&rtwpci->irq_lock, flags); rtwpci->running = false; rtw89_chip_disable_intr(rtwdev, rtwpci); spin_unlock_irqrestore(&rtwpci->irq_lock, flags); } static int rtw89_pci_ops_start(struct rtw89_dev *rtwdev) { rtw89_core_napi_start(rtwdev); rtw89_pci_enable_intr_lock(rtwdev); return 0; } static void rtw89_pci_ops_stop(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct pci_dev *pdev = rtwpci->pdev; rtw89_pci_disable_intr_lock(rtwdev); synchronize_irq(pdev->irq); rtw89_core_napi_stop(rtwdev); } static void rtw89_pci_ops_pause(struct rtw89_dev *rtwdev, bool pause) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct pci_dev *pdev = rtwpci->pdev; if (pause) { rtw89_pci_disable_intr_lock(rtwdev); synchronize_irq(pdev->irq); if (test_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) napi_synchronize(&rtwdev->napi); } else { rtw89_pci_enable_intr_lock(rtwdev); rtw89_pci_tx_kick_off_pending(rtwdev); } } static void rtw89_pci_switch_bd_idx_addr(struct rtw89_dev *rtwdev, bool low_power) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; const struct rtw89_pci_info *info = rtwdev->pci_info; const struct rtw89_pci_bd_idx_addr *bd_idx_addr = info->bd_idx_addr_low_power; const struct rtw89_pci_ch_dma_addr_set *dma_addr_set = info->dma_addr_set; struct rtw89_pci_tx_ring *tx_ring; struct rtw89_pci_rx_ring *rx_ring; int i; if (WARN(!bd_idx_addr, "only HCI with low power mode needs this\n")) return; for (i = 0; i < RTW89_TXCH_NUM; i++) { tx_ring = &rtwpci->tx_rings[i]; tx_ring->bd_ring.addr.idx = low_power ? bd_idx_addr->tx_bd_addrs[i] : dma_addr_set->tx[i].idx; } for (i = 0; i < RTW89_RXCH_NUM; i++) { rx_ring = &rtwpci->rx_rings[i]; rx_ring->bd_ring.addr.idx = low_power ? bd_idx_addr->rx_bd_addrs[i] : dma_addr_set->rx[i].idx; } } static void rtw89_pci_ops_switch_mode(struct rtw89_dev *rtwdev, bool low_power) { enum rtw89_pci_intr_mask_cfg cfg; WARN(!rtwdev->hci.paused, "HCI isn't paused\n"); cfg = low_power ? RTW89_PCI_INTR_MASK_LOW_POWER : RTW89_PCI_INTR_MASK_NORMAL; rtw89_chip_config_intr_mask(rtwdev, cfg); rtw89_pci_switch_bd_idx_addr(rtwdev, low_power); } static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data); static u32 rtw89_pci_ops_read32_cmac(struct rtw89_dev *rtwdev, u32 addr) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; #if defined(__linux__) u32 val = readl(rtwpci->mmap + addr); #elif defined(__FreeBSD__) u32 val; val = bus_read_4((struct resource *)rtwpci->mmap, addr); rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val); #endif int count; for (count = 0; ; count++) { if (val != RTW89_R32_DEAD) return val; if (count >= MAC_REG_POOL_COUNT) { rtw89_warn(rtwdev, "addr %#x = %#x\n", addr, val); return RTW89_R32_DEAD; } rtw89_pci_ops_write32(rtwdev, R_AX_CK_EN, B_AX_CMAC_ALLCKEN); #if defined(__linux__) val = readl(rtwpci->mmap + addr); #elif defined(__FreeBSD__) val = bus_read_4((struct resource *)rtwpci->mmap, addr); rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val); #endif } return val; } static u8 rtw89_pci_ops_read8(struct rtw89_dev *rtwdev, u32 addr) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; u32 addr32, val32, shift; if (!ACCESS_CMAC(addr)) #if defined(__linux__) return readb(rtwpci->mmap + addr); #elif defined(__FreeBSD__) { u8 val; val = bus_read_1((struct resource *)rtwpci->mmap, addr); rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R08 (%#010x) -> %#04x\n", addr, val); return (val); } #endif addr32 = addr & ~0x3; shift = (addr & 0x3) * 8; val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); return val32 >> shift; } static u16 rtw89_pci_ops_read16(struct rtw89_dev *rtwdev, u32 addr) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; u32 addr32, val32, shift; if (!ACCESS_CMAC(addr)) #if defined(__linux__) return readw(rtwpci->mmap + addr); #elif defined(__FreeBSD__) { u16 val; val = bus_read_2((struct resource *)rtwpci->mmap, addr); rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R16 (%#010x) -> %#06x\n", addr, val); return (val); } #endif addr32 = addr & ~0x3; shift = (addr & 0x3) * 8; val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); return val32 >> shift; } static u32 rtw89_pci_ops_read32(struct rtw89_dev *rtwdev, u32 addr) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; if (!ACCESS_CMAC(addr)) #if defined(__linux__) return readl(rtwpci->mmap + addr); #elif defined(__FreeBSD__) { u32 val; val = bus_read_4((struct resource *)rtwpci->mmap, addr); rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val); return (val); } #endif return rtw89_pci_ops_read32_cmac(rtwdev, addr); } static void rtw89_pci_ops_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; #if defined(__linux__) writeb(data, rtwpci->mmap + addr); #elif defined(__FreeBSD__) rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "W08 (%#010x) <- %#04x\n", addr, data); return (bus_write_1((struct resource *)rtwpci->mmap, addr, data)); #endif } static void rtw89_pci_ops_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; #if defined(__linux__) writew(data, rtwpci->mmap + addr); #elif defined(__FreeBSD__) rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "W16 (%#010x) <- %#06x\n", addr, data); return (bus_write_2((struct resource *)rtwpci->mmap, addr, data)); #endif } static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; #if defined(__linux__) writel(data, rtwpci->mmap + addr); #elif defined(__FreeBSD__) rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "W32 (%#010x) <- %#010x\n", addr, data); return (bus_write_4((struct resource *)rtwpci->mmap, addr, data)); #endif } static void rtw89_pci_ctrl_dma_trx(struct rtw89_dev *rtwdev, bool enable) { const struct rtw89_pci_info *info = rtwdev->pci_info; if (enable) rtw89_write32_set(rtwdev, info->init_cfg_reg, info->rxhci_en_bit | info->txhci_en_bit); else rtw89_write32_clr(rtwdev, info->init_cfg_reg, info->rxhci_en_bit | info->txhci_en_bit); } static void rtw89_pci_ctrl_dma_io(struct rtw89_dev *rtwdev, bool enable) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; u32 reg, mask; if (chip_id == RTL8852C) { reg = R_AX_HAXI_INIT_CFG1; mask = B_AX_STOP_AXI_MST; } else { reg = R_AX_PCIE_DMA_STOP1; mask = B_AX_STOP_PCIEIO; } if (enable) rtw89_write32_clr(rtwdev, reg, mask); else rtw89_write32_set(rtwdev, reg, mask); } static void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable) { rtw89_pci_ctrl_dma_io(rtwdev, enable); rtw89_pci_ctrl_dma_trx(rtwdev, enable); } static int rtw89_pci_check_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 rw_bit) { u16 val; rtw89_write8(rtwdev, R_AX_MDIO_CFG, addr & 0x1F); val = rtw89_read16(rtwdev, R_AX_MDIO_CFG); switch (speed) { case PCIE_PHY_GEN1: if (addr < 0x20) val = u16_replace_bits(val, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR_MASK); else val = u16_replace_bits(val, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR_MASK); break; case PCIE_PHY_GEN2: if (addr < 0x20) val = u16_replace_bits(val, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR_MASK); else val = u16_replace_bits(val, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR_MASK); break; default: rtw89_err(rtwdev, "[ERR]Error Speed %d!\n", speed); return -EINVAL; } rtw89_write16(rtwdev, R_AX_MDIO_CFG, val); rtw89_write16_set(rtwdev, R_AX_MDIO_CFG, rw_bit); return read_poll_timeout(rtw89_read16, val, !(val & rw_bit), 10, 2000, false, rtwdev, R_AX_MDIO_CFG); } static int rtw89_read16_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 *val) { int ret; ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_RFLAG); if (ret) { rtw89_err(rtwdev, "[ERR]MDIO R16 0x%X fail ret=%d!\n", addr, ret); return ret; } *val = rtw89_read16(rtwdev, R_AX_MDIO_RDATA); return 0; } static int rtw89_write16_mdio(struct rtw89_dev *rtwdev, u8 addr, u16 data, u8 speed) { int ret; rtw89_write16(rtwdev, R_AX_MDIO_WDATA, data); ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_WFLAG); if (ret) { rtw89_err(rtwdev, "[ERR]MDIO W16 0x%X = %x fail ret=%d!\n", addr, data, ret); return ret; } return 0; } static int rtw89_write16_mdio_mask(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u16 data, u8 speed) { u32 shift; int ret; u16 val; ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); if (ret) return ret; shift = __ffs(mask); val &= ~mask; val |= ((data << shift) & mask); ret = rtw89_write16_mdio(rtwdev, addr, val, speed); if (ret) return ret; return 0; } static int rtw89_write16_mdio_set(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) { int ret; u16 val; ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); if (ret) return ret; ret = rtw89_write16_mdio(rtwdev, addr, val | mask, speed); if (ret) return ret; return 0; } static int rtw89_write16_mdio_clr(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) { int ret; u16 val; ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); if (ret) return ret; ret = rtw89_write16_mdio(rtwdev, addr, val & ~mask, speed); if (ret) return ret; return 0; } static int rtw89_pci_write_config_byte(struct rtw89_dev *rtwdev, u16 addr, u8 data) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct pci_dev *pdev = rtwpci->pdev; return pci_write_config_byte(pdev, addr, data); } static int rtw89_pci_read_config_byte(struct rtw89_dev *rtwdev, u16 addr, u8 *value) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct pci_dev *pdev = rtwpci->pdev; return pci_read_config_byte(pdev, addr, value); } static int rtw89_pci_config_byte_set(struct rtw89_dev *rtwdev, u16 addr, u8 bit) { u8 value; int ret; ret = rtw89_pci_read_config_byte(rtwdev, addr, &value); if (ret) return ret; value |= bit; ret = rtw89_pci_write_config_byte(rtwdev, addr, value); return ret; } static int rtw89_pci_config_byte_clr(struct rtw89_dev *rtwdev, u16 addr, u8 bit) { u8 value; int ret; ret = rtw89_pci_read_config_byte(rtwdev, addr, &value); if (ret) return ret; value &= ~bit; ret = rtw89_pci_write_config_byte(rtwdev, addr, value); return ret; } static int __get_target(struct rtw89_dev *rtwdev, u16 *target, enum rtw89_pcie_phy phy_rate) { u16 val, tar; int ret; /* Enable counter */ ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val); if (ret) return ret; ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, phy_rate); if (ret) return ret; ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val | B_AX_CLK_CALIB_EN, phy_rate); if (ret) return ret; fsleep(300); ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &tar); if (ret) return ret; ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, phy_rate); if (ret) return ret; tar = tar & 0x0FFF; if (tar == 0 || tar == 0x0FFF) { rtw89_err(rtwdev, "[ERR]Get target failed.\n"); return -EINVAL; } *target = tar; return 0; } static int rtw89_pci_autok_x(struct rtw89_dev *rtwdev) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; int ret; if (chip_id != RTL8852B && chip_id != RTL8851B) return 0; ret = rtw89_write16_mdio_mask(rtwdev, RAC_REG_FLD_0, BAC_AUTOK_N_MASK, PCIE_AUTOK_4, PCIE_PHY_GEN1); return ret; } static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; enum rtw89_pcie_phy phy_rate; u16 val16, mgn_set, div_set, tar; u8 val8, bdr_ori; bool l1_flag = false; int ret = 0; if (chip_id != RTL8852B && chip_id != RTL8851B) return 0; ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_PHY_RATE, &val8); if (ret) { rtw89_err(rtwdev, "[ERR]pci config read %X\n", RTW89_PCIE_PHY_RATE); return ret; } if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x1) { phy_rate = PCIE_PHY_GEN1; } else if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x2) { phy_rate = PCIE_PHY_GEN2; } else { rtw89_err(rtwdev, "[ERR]PCIe PHY rate %#x not support\n", val8); return -EOPNOTSUPP; } /* Disable L1BD */ ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, &bdr_ori); if (ret) { rtw89_err(rtwdev, "[ERR]pci config read %X\n", RTW89_PCIE_L1_CTRL); return ret; } if (bdr_ori & RTW89_PCIE_BIT_L1) { ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, bdr_ori & ~RTW89_PCIE_BIT_L1); if (ret) { rtw89_err(rtwdev, "[ERR]pci config write %X\n", RTW89_PCIE_L1_CTRL); return ret; } l1_flag = true; } ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); if (ret) { rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); goto end; } if (val16 & B_AX_CALIB_EN) { ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val16 & ~B_AX_CALIB_EN, phy_rate); if (ret) { rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); goto end; } } if (!autook_en) goto end; /* Set div */ ret = rtw89_write16_mdio_clr(rtwdev, RAC_CTRL_PPR_V1, B_AX_DIV, phy_rate); if (ret) { rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); goto end; } /* Obtain div and margin */ ret = __get_target(rtwdev, &tar, phy_rate); if (ret) { rtw89_err(rtwdev, "[ERR]1st get target fail %d\n", ret); goto end; } mgn_set = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar; if (mgn_set >= 128) { div_set = 0x0003; mgn_set = 0x000F; } else if (mgn_set >= 64) { div_set = 0x0003; mgn_set >>= 3; } else if (mgn_set >= 32) { div_set = 0x0002; mgn_set >>= 2; } else if (mgn_set >= 16) { div_set = 0x0001; mgn_set >>= 1; } else if (mgn_set == 0) { rtw89_err(rtwdev, "[ERR]cal mgn is 0,tar = %d\n", tar); goto end; } else { div_set = 0x0000; } ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); if (ret) { rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); goto end; } val16 |= u16_encode_bits(div_set, B_AX_DIV); ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val16, phy_rate); if (ret) { rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); goto end; } ret = __get_target(rtwdev, &tar, phy_rate); if (ret) { rtw89_err(rtwdev, "[ERR]2nd get target fail %d\n", ret); goto end; } rtw89_debug(rtwdev, RTW89_DBG_HCI, "[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\n", tar, div_set, mgn_set); ret = rtw89_write16_mdio(rtwdev, RAC_SET_PPR_V1, (tar & 0x0FFF) | (mgn_set << 12), phy_rate); if (ret) { rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_SET_PPR_V1); goto end; } /* Enable function */ ret = rtw89_write16_mdio_set(rtwdev, RAC_CTRL_PPR_V1, B_AX_CALIB_EN, phy_rate); if (ret) { rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); goto end; } /* CLK delay = 0 */ ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL, PCIE_CLKDLY_HW_0); end: /* Set L1BD to ori */ if (l1_flag) { ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, bdr_ori); if (ret) { rtw89_err(rtwdev, "[ERR]pci config write %X\n", RTW89_PCIE_L1_CTRL); return ret; } } return ret; } static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; int ret; if (chip_id == RTL8852A) { ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, PCIE_PHY_GEN1); if (ret) return ret; ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, PCIE_PHY_GEN2); if (ret) return ret; } else if (chip_id == RTL8852C) { rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA24 * 2, B_AX_DEGLITCH); rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA24 * 2, B_AX_DEGLITCH); } return 0; } static void rtw89_pci_rxdma_prefth(struct rtw89_dev *rtwdev) { if (rtwdev->chip->chip_id != RTL8852A) return; rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_DIS_RXDMA_PRE); } static void rtw89_pci_l1off_pwroff(struct rtw89_dev *rtwdev) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; if (chip_id != RTL8852A && chip_id != RTL8852B && chip_id != RTL8851B) return; rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL, B_AX_L1OFF_PWR_OFF_EN); } static u32 rtw89_pci_l2_rxen_lat(struct rtw89_dev *rtwdev) { int ret; if (rtwdev->chip->chip_id != RTL8852A) return 0; ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, PCIE_PHY_GEN1); if (ret) return ret; ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, PCIE_PHY_GEN2); if (ret) return ret; return 0; } static void rtw89_pci_aphy_pwrcut(struct rtw89_dev *rtwdev) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; if (chip_id != RTL8852A && chip_id != RTL8852B && chip_id != RTL8851B) return; rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_PSUS_OFF_CAPC_EN); } static void rtw89_pci_hci_ldo(struct rtw89_dev *rtwdev) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) { rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_DIS_WLSUS_AFT_PDN); } else if (rtwdev->chip->chip_id == RTL8852C) { rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); } } static int rtw89_pci_dphy_delay(struct rtw89_dev *rtwdev) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; if (chip_id != RTL8852B && chip_id != RTL8851B) return 0; return rtw89_write16_mdio_mask(rtwdev, RAC_REG_REV2, BAC_CMU_EN_DLY_MASK, PCIE_DPHY_DLY_25US, PCIE_PHY_GEN1); } static void rtw89_pci_power_wake(struct rtw89_dev *rtwdev, bool pwr_up) { if (pwr_up) rtw89_write32_set(rtwdev, R_AX_HCI_OPT_CTRL, BIT_WAKE_CTRL); else rtw89_write32_clr(rtwdev, R_AX_HCI_OPT_CTRL, BIT_WAKE_CTRL); } static void rtw89_pci_autoload_hang(struct rtw89_dev *rtwdev) { if (rtwdev->chip->chip_id != RTL8852C) return; rtw89_write32_set(rtwdev, R_AX_PCIE_BG_CLR, B_AX_BG_CLR_ASYNC_M3); rtw89_write32_clr(rtwdev, R_AX_PCIE_BG_CLR, B_AX_BG_CLR_ASYNC_M3); } static void rtw89_pci_l12_vmain(struct rtw89_dev *rtwdev) { if (!(rtwdev->chip->chip_id == RTL8852C && rtwdev->hal.cv == CHIP_CAV)) return; rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_FORCE_PWR_NGAT); } static void rtw89_pci_gen2_force_ib(struct rtw89_dev *rtwdev) { if (!(rtwdev->chip->chip_id == RTL8852C && rtwdev->hal.cv == CHIP_CAV)) return; rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); rtw89_write32_set(rtwdev, R_AX_HCI_BG_CTRL, B_AX_BG_CLR_ASYNC_M3); rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); } static void rtw89_pci_l1_ent_lat(struct rtw89_dev *rtwdev) { if (rtwdev->chip->chip_id != RTL8852C) return; rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_SEL_REQ_ENTR_L1); } static void rtw89_pci_wd_exit_l1(struct rtw89_dev *rtwdev) { if (rtwdev->chip->chip_id != RTL8852C) return; rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_DMAC0_EXIT_L1_EN); } static void rtw89_pci_set_sic(struct rtw89_dev *rtwdev) { if (rtwdev->chip->chip_id == RTL8852C) return; rtw89_write32_clr(rtwdev, R_AX_PCIE_EXP_CTRL, B_AX_SIC_EN_FORCE_CLKREQ); } static void rtw89_pci_set_lbc(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; u32 lbc; if (rtwdev->chip->chip_id == RTL8852C) return; lbc = rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG); if (info->lbc_en == MAC_AX_PCIE_ENABLE) { lbc = u32_replace_bits(lbc, info->lbc_tmr, B_AX_LBC_TIMER); lbc |= B_AX_LBC_FLAG | B_AX_LBC_EN; rtw89_write32(rtwdev, R_AX_LBC_WATCHDOG, lbc); } else { lbc &= ~B_AX_LBC_EN; } rtw89_write32_set(rtwdev, R_AX_LBC_WATCHDOG, lbc); } static void rtw89_pci_set_io_rcy(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; u32 val32; if (rtwdev->chip->chip_id != RTL8852C) return; if (info->io_rcy_en == MAC_AX_PCIE_ENABLE) { val32 = FIELD_PREP(B_AX_PCIE_WDT_TIMER_M1_MASK, info->io_rcy_tmr); rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_M1, val32); rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_M2, val32); rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_E0, val32); rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1); rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2); rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0); } else { rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1); rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2); rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0); } rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_S1, B_AX_PCIE_IO_RCY_WDT_MODE_S1); } static void rtw89_pci_set_dbg(struct rtw89_dev *rtwdev) { if (rtwdev->chip->chip_id == RTL8852C) return; rtw89_write32_set(rtwdev, R_AX_PCIE_DBG_CTRL, B_AX_ASFF_FULL_NO_STK | B_AX_EN_STUCK_DBG); if (rtwdev->chip->chip_id == RTL8852A) rtw89_write32_set(rtwdev, R_AX_PCIE_EXP_CTRL, B_AX_EN_CHKDSC_NO_RX_STUCK); } static void rtw89_pci_set_keep_reg(struct rtw89_dev *rtwdev) { if (rtwdev->chip->chip_id == RTL8852C) return; rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_TXRST_KEEP_REG | B_AX_PCIE_RXRST_KEEP_REG); } static void rtw89_pci_clr_idx_all(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; u32 val = B_AX_CLR_ACH0_IDX | B_AX_CLR_ACH1_IDX | B_AX_CLR_ACH2_IDX | B_AX_CLR_ACH3_IDX | B_AX_CLR_CH8_IDX | B_AX_CLR_CH9_IDX | B_AX_CLR_CH12_IDX; u32 rxbd_rwptr_clr = info->rxbd_rwptr_clr_reg; u32 txbd_rwptr_clr2 = info->txbd_rwptr_clr2_reg; if (chip_id == RTL8852A || chip_id == RTL8852C) val |= B_AX_CLR_ACH4_IDX | B_AX_CLR_ACH5_IDX | B_AX_CLR_ACH6_IDX | B_AX_CLR_ACH7_IDX; /* clear DMA indexes */ rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR1, val); if (chip_id == RTL8852A || chip_id == RTL8852C) rtw89_write32_set(rtwdev, txbd_rwptr_clr2, B_AX_CLR_CH10_IDX | B_AX_CLR_CH11_IDX); rtw89_write32_set(rtwdev, rxbd_rwptr_clr, B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX); } static int rtw89_poll_txdma_ch_idle_pcie(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; u32 ret, check, dma_busy; u32 dma_busy1 = info->dma_busy1.addr; u32 dma_busy2 = info->dma_busy2_reg; check = info->dma_busy1.mask; ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, 10, 100, false, rtwdev, dma_busy1); if (ret) return ret; if (!dma_busy2) return 0; check = B_AX_CH10_BUSY | B_AX_CH11_BUSY; ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, 10, 100, false, rtwdev, dma_busy2); if (ret) return ret; return 0; } static int rtw89_poll_rxdma_ch_idle_pcie(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; u32 ret, check, dma_busy; u32 dma_busy3 = info->dma_busy3_reg; check = B_AX_RXQ_BUSY | B_AX_RPQ_BUSY; ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, 10, 100, false, rtwdev, dma_busy3); if (ret) return ret; return 0; } static int rtw89_pci_poll_dma_all_idle(struct rtw89_dev *rtwdev) { u32 ret; ret = rtw89_poll_txdma_ch_idle_pcie(rtwdev); if (ret) { rtw89_err(rtwdev, "txdma ch busy\n"); return ret; } ret = rtw89_poll_rxdma_ch_idle_pcie(rtwdev); if (ret) { rtw89_err(rtwdev, "rxdma ch busy\n"); return ret; } return 0; } static int rtw89_pci_mode_op(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; enum mac_ax_bd_trunc_mode txbd_trunc_mode = info->txbd_trunc_mode; enum mac_ax_bd_trunc_mode rxbd_trunc_mode = info->rxbd_trunc_mode; enum mac_ax_rxbd_mode rxbd_mode = info->rxbd_mode; enum mac_ax_tag_mode tag_mode = info->tag_mode; enum mac_ax_wd_dma_intvl wd_dma_idle_intvl = info->wd_dma_idle_intvl; enum mac_ax_wd_dma_intvl wd_dma_act_intvl = info->wd_dma_act_intvl; enum mac_ax_tx_burst tx_burst = info->tx_burst; enum mac_ax_rx_burst rx_burst = info->rx_burst; enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; u8 cv = rtwdev->hal.cv; u32 val32; if (txbd_trunc_mode == MAC_AX_BD_TRUNC) { if (chip_id == RTL8852A && cv == CHIP_CBV) rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE); } else if (txbd_trunc_mode == MAC_AX_BD_NORM) { if (chip_id == RTL8852A || chip_id == RTL8852B) rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE); } if (rxbd_trunc_mode == MAC_AX_BD_TRUNC) { if (chip_id == RTL8852A && cv == CHIP_CBV) rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE); } else if (rxbd_trunc_mode == MAC_AX_BD_NORM) { if (chip_id == RTL8852A || chip_id == RTL8852B) rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE); } if (rxbd_mode == MAC_AX_RXBD_PKT) { rtw89_write32_clr(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit); } else if (rxbd_mode == MAC_AX_RXBD_SEP) { rtw89_write32_set(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit); if (chip_id == RTL8852A || chip_id == RTL8852B) rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_PCIE_RX_APPLEN_MASK, 0); } if (chip_id == RTL8852A || chip_id == RTL8852B) { rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, tx_burst); rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, rx_burst); } else if (chip_id == RTL8852C) { rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_TXDMA_MASK, tx_burst); rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_RXDMA_MASK, rx_burst); } if (chip_id == RTL8852A || chip_id == RTL8852B) { if (tag_mode == MAC_AX_TAG_SGL) { val32 = rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) & ~B_AX_LATENCY_CONTROL; rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, val32); } else if (tag_mode == MAC_AX_TAG_MULTI) { val32 = rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) | B_AX_LATENCY_CONTROL; rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, val32); } } rtw89_write32_mask(rtwdev, info->exp_ctrl_reg, info->max_tag_num_mask, info->multi_tag_num); if (chip_id == RTL8852A || chip_id == RTL8852B) { rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE, wd_dma_idle_intvl); rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT, wd_dma_act_intvl); } else if (chip_id == RTL8852C) { rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_IDLE_V1_MASK, wd_dma_idle_intvl); rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_ACT_V1_MASK, wd_dma_act_intvl); } if (txbd_trunc_mode == MAC_AX_BD_TRUNC) { rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, B_AX_HOST_ADDR_INFO_8B_SEL); rtw89_write32_clr(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); } else if (txbd_trunc_mode == MAC_AX_BD_NORM) { rtw89_write32_clr(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, B_AX_HOST_ADDR_INFO_8B_SEL); rtw89_write32_set(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); } return 0; } static int rtw89_pci_ops_deinit(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; if (rtwdev->chip->chip_id == RTL8852A) { /* ltr sw trigger */ rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_IDLE); } info->ltr_set(rtwdev, false); rtw89_pci_ctrl_dma_all(rtwdev, false); rtw89_pci_clr_idx_all(rtwdev); return 0; } static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; int ret; rtw89_pci_rxdma_prefth(rtwdev); rtw89_pci_l1off_pwroff(rtwdev); rtw89_pci_deglitch_setting(rtwdev); ret = rtw89_pci_l2_rxen_lat(rtwdev); if (ret) { rtw89_err(rtwdev, "[ERR] pcie l2 rxen lat %d\n", ret); return ret; } rtw89_pci_aphy_pwrcut(rtwdev); rtw89_pci_hci_ldo(rtwdev); rtw89_pci_dphy_delay(rtwdev); ret = rtw89_pci_autok_x(rtwdev); if (ret) { rtw89_err(rtwdev, "[ERR] pcie autok_x fail %d\n", ret); return ret; } ret = rtw89_pci_auto_refclk_cal(rtwdev, false); if (ret) { rtw89_err(rtwdev, "[ERR] pcie autok fail %d\n", ret); return ret; } rtw89_pci_power_wake(rtwdev, true); rtw89_pci_autoload_hang(rtwdev); rtw89_pci_l12_vmain(rtwdev); rtw89_pci_gen2_force_ib(rtwdev); rtw89_pci_l1_ent_lat(rtwdev); rtw89_pci_wd_exit_l1(rtwdev); rtw89_pci_set_sic(rtwdev); rtw89_pci_set_lbc(rtwdev); rtw89_pci_set_io_rcy(rtwdev); rtw89_pci_set_dbg(rtwdev); rtw89_pci_set_keep_reg(rtwdev); rtw89_write32_set(rtwdev, info->dma_stop1.addr, B_AX_STOP_WPDMA); /* stop DMA activities */ rtw89_pci_ctrl_dma_all(rtwdev, false); ret = rtw89_pci_poll_dma_all_idle(rtwdev); if (ret) { rtw89_err(rtwdev, "[ERR] poll pcie dma all idle\n"); return ret; } rtw89_pci_clr_idx_all(rtwdev); rtw89_pci_mode_op(rtwdev); /* fill TRX BD indexes */ rtw89_pci_ops_reset(rtwdev); ret = rtw89_pci_rst_bdram_pcie(rtwdev); if (ret) { rtw89_warn(rtwdev, "reset bdram busy\n"); return ret; } /* disable all channels except to FW CMD channel to download firmware */ rtw89_pci_ctrl_txdma_ch_pcie(rtwdev, false); rtw89_pci_ctrl_txdma_fw_ch_pcie(rtwdev, true); /* start DMA activities */ rtw89_pci_ctrl_dma_all(rtwdev, true); return 0; } int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en) { u32 val; if (!en) return 0; val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0); if (rtw89_pci_ltr_is_err_reg_val(val)) return -EINVAL; val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1); if (rtw89_pci_ltr_is_err_reg_val(val)) return -EINVAL; val = rtw89_read32(rtwdev, R_AX_LTR_IDLE_LATENCY); if (rtw89_pci_ltr_is_err_reg_val(val)) return -EINVAL; val = rtw89_read32(rtwdev, R_AX_LTR_ACTIVE_LATENCY); if (rtw89_pci_ltr_is_err_reg_val(val)) return -EINVAL; rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_HW_EN | B_AX_LTR_EN | B_AX_LTR_WD_NOEMP_CHK); rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_SPACE_IDX_MASK, PCI_LTR_SPC_500US); rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, PCI_LTR_IDLE_TIMER_3_2MS); rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28); rtw89_write32(rtwdev, R_AX_LTR_IDLE_LATENCY, 0x90039003); rtw89_write32(rtwdev, R_AX_LTR_ACTIVE_LATENCY, 0x880b880b); return 0; } EXPORT_SYMBOL(rtw89_pci_ltr_set); int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en) { u32 dec_ctrl; u32 val32; val32 = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0); if (rtw89_pci_ltr_is_err_reg_val(val32)) return -EINVAL; val32 = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1); if (rtw89_pci_ltr_is_err_reg_val(val32)) return -EINVAL; dec_ctrl = rtw89_read32(rtwdev, R_AX_LTR_DEC_CTRL); if (rtw89_pci_ltr_is_err_reg_val(dec_ctrl)) return -EINVAL; val32 = rtw89_read32(rtwdev, R_AX_LTR_LATENCY_IDX3); if (rtw89_pci_ltr_is_err_reg_val(val32)) return -EINVAL; val32 = rtw89_read32(rtwdev, R_AX_LTR_LATENCY_IDX0); if (rtw89_pci_ltr_is_err_reg_val(val32)) return -EINVAL; if (!en) { dec_ctrl &= ~(LTR_EN_BITS | B_AX_LTR_IDX_DRV_MASK | B_AX_LTR_HW_DEC_EN); dec_ctrl |= FIELD_PREP(B_AX_LTR_IDX_DRV_MASK, PCIE_LTR_IDX_IDLE) | B_AX_LTR_REQ_DRV; } else { dec_ctrl |= B_AX_LTR_HW_DEC_EN; } dec_ctrl &= ~B_AX_LTR_SPACE_IDX_V1_MASK; dec_ctrl |= FIELD_PREP(B_AX_LTR_SPACE_IDX_V1_MASK, PCI_LTR_SPC_500US); if (en) rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_WD_NOEMP_CHK_V1 | B_AX_LTR_HW_EN); rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, PCI_LTR_IDLE_TIMER_3_2MS); rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28); rtw89_write32(rtwdev, R_AX_LTR_DEC_CTRL, dec_ctrl); rtw89_write32(rtwdev, R_AX_LTR_LATENCY_IDX3, 0x90039003); rtw89_write32(rtwdev, R_AX_LTR_LATENCY_IDX0, 0x880b880b); return 0; } EXPORT_SYMBOL(rtw89_pci_ltr_set_v1); static int rtw89_pci_ops_mac_post_init(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; int ret; ret = info->ltr_set(rtwdev, true); if (ret) { rtw89_err(rtwdev, "pci ltr set fail\n"); return ret; } if (chip_id == RTL8852A) { /* ltr sw trigger */ rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_ACT); } if (chip_id == RTL8852A || chip_id == RTL8852B) { /* ADDR info 8-byte mode */ rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, B_AX_HOST_ADDR_INFO_8B_SEL); rtw89_write32_clr(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); } /* enable DMA for all queues */ rtw89_pci_ctrl_txdma_ch_pcie(rtwdev, true); /* Release PCI IO */ rtw89_write32_clr(rtwdev, info->dma_stop1.addr, B_AX_STOP_WPDMA | B_AX_STOP_PCIEIO); return 0; } static int rtw89_pci_claim_device(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; int ret; ret = pci_enable_device(pdev); if (ret) { rtw89_err(rtwdev, "failed to enable pci device\n"); return ret; } pci_set_master(pdev); pci_set_drvdata(pdev, rtwdev->hw); rtwpci->pdev = pdev; return 0; } static void rtw89_pci_declaim_device(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { pci_disable_device(pdev); } static int rtw89_pci_setup_mapping(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; unsigned long resource_len; u8 bar_id = 2; int ret; ret = pci_request_regions(pdev, KBUILD_MODNAME); if (ret) { rtw89_err(rtwdev, "failed to request pci regions\n"); goto err; } ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); if (ret) { rtw89_err(rtwdev, "failed to set dma mask to 32-bit\n"); goto err_release_regions; } ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); if (ret) { rtw89_err(rtwdev, "failed to set consistent dma mask to 32-bit\n"); goto err_release_regions; } #if defined(__FreeBSD__) linuxkpi_pcim_want_to_use_bus_functions(pdev); #endif resource_len = pci_resource_len(pdev, bar_id); rtwpci->mmap = pci_iomap(pdev, bar_id, resource_len); if (!rtwpci->mmap) { rtw89_err(rtwdev, "failed to map pci io\n"); ret = -EIO; goto err_release_regions; } return 0; err_release_regions: pci_release_regions(pdev); err: return ret; } static void rtw89_pci_clear_mapping(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; if (rtwpci->mmap) { pci_iounmap(pdev, rtwpci->mmap); pci_release_regions(pdev); } } static void rtw89_pci_free_tx_wd_ring(struct rtw89_dev *rtwdev, struct pci_dev *pdev, struct rtw89_pci_tx_ring *tx_ring) { struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; u8 *head = wd_ring->head; dma_addr_t dma = wd_ring->dma; u32 page_size = wd_ring->page_size; u32 page_num = wd_ring->page_num; u32 ring_sz = page_size * page_num; dma_free_coherent(&pdev->dev, ring_sz, head, dma); wd_ring->head = NULL; } static void rtw89_pci_free_tx_ring(struct rtw89_dev *rtwdev, struct pci_dev *pdev, struct rtw89_pci_tx_ring *tx_ring) { int ring_sz; u8 *head; dma_addr_t dma; head = tx_ring->bd_ring.head; dma = tx_ring->bd_ring.dma; ring_sz = tx_ring->bd_ring.desc_size * tx_ring->bd_ring.len; dma_free_coherent(&pdev->dev, ring_sz, head, dma); tx_ring->bd_ring.head = NULL; } static void rtw89_pci_free_tx_rings(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; const struct rtw89_pci_info *info = rtwdev->pci_info; struct rtw89_pci_tx_ring *tx_ring; int i; for (i = 0; i < RTW89_TXCH_NUM; i++) { if (info->tx_dma_ch_mask & BIT(i)) continue; tx_ring = &rtwpci->tx_rings[i]; rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); } } static void rtw89_pci_free_rx_ring(struct rtw89_dev *rtwdev, struct pci_dev *pdev, struct rtw89_pci_rx_ring *rx_ring) { struct rtw89_pci_rx_info *rx_info; struct sk_buff *skb; dma_addr_t dma; u32 buf_sz; u8 *head; int ring_sz = rx_ring->bd_ring.desc_size * rx_ring->bd_ring.len; int i; buf_sz = rx_ring->buf_sz; for (i = 0; i < rx_ring->bd_ring.len; i++) { skb = rx_ring->buf[i]; if (!skb) continue; rx_info = RTW89_PCI_RX_SKB_CB(skb); dma = rx_info->dma; dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); dev_kfree_skb(skb); rx_ring->buf[i] = NULL; } head = rx_ring->bd_ring.head; dma = rx_ring->bd_ring.dma; dma_free_coherent(&pdev->dev, ring_sz, head, dma); rx_ring->bd_ring.head = NULL; } static void rtw89_pci_free_rx_rings(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_rx_ring *rx_ring; int i; for (i = 0; i < RTW89_RXCH_NUM; i++) { rx_ring = &rtwpci->rx_rings[i]; rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); } } static void rtw89_pci_free_trx_rings(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { rtw89_pci_free_rx_rings(rtwdev, pdev); rtw89_pci_free_tx_rings(rtwdev, pdev); } static int rtw89_pci_init_rx_bd(struct rtw89_dev *rtwdev, struct pci_dev *pdev, struct rtw89_pci_rx_ring *rx_ring, struct sk_buff *skb, int buf_sz, u32 idx) { struct rtw89_pci_rx_info *rx_info; struct rtw89_pci_rx_bd_32 *rx_bd; dma_addr_t dma; if (!skb) return -EINVAL; dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE); if (dma_mapping_error(&pdev->dev, dma)) return -EBUSY; rx_info = RTW89_PCI_RX_SKB_CB(skb); rx_bd = RTW89_PCI_RX_BD(rx_ring, idx); memset(rx_bd, 0, sizeof(*rx_bd)); rx_bd->buf_size = cpu_to_le16(buf_sz); rx_bd->dma = cpu_to_le32(dma); rx_info->dma = dma; return 0; } static int rtw89_pci_alloc_tx_wd_ring(struct rtw89_dev *rtwdev, struct pci_dev *pdev, struct rtw89_pci_tx_ring *tx_ring, enum rtw89_tx_channel txch) { struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; struct rtw89_pci_tx_wd *txwd; dma_addr_t dma; dma_addr_t cur_paddr; u8 *head; u8 *cur_vaddr; u32 page_size = RTW89_PCI_TXWD_PAGE_SIZE; u32 page_num = RTW89_PCI_TXWD_NUM_MAX; u32 ring_sz = page_size * page_num; u32 page_offset; int i; /* FWCMD queue doesn't use txwd as pages */ if (txch == RTW89_TXCH_CH12) return 0; head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); if (!head) return -ENOMEM; INIT_LIST_HEAD(&wd_ring->free_pages); wd_ring->head = head; wd_ring->dma = dma; wd_ring->page_size = page_size; wd_ring->page_num = page_num; page_offset = 0; for (i = 0; i < page_num; i++) { txwd = &wd_ring->pages[i]; cur_paddr = dma + page_offset; cur_vaddr = head + page_offset; skb_queue_head_init(&txwd->queue); INIT_LIST_HEAD(&txwd->list); txwd->paddr = cur_paddr; txwd->vaddr = cur_vaddr; txwd->len = page_size; txwd->seq = i; rtw89_pci_enqueue_txwd(tx_ring, txwd); page_offset += page_size; } return 0; } static int rtw89_pci_alloc_tx_ring(struct rtw89_dev *rtwdev, struct pci_dev *pdev, struct rtw89_pci_tx_ring *tx_ring, u32 desc_size, u32 len, enum rtw89_tx_channel txch) { const struct rtw89_pci_ch_dma_addr *txch_addr; int ring_sz = desc_size * len; u8 *head; dma_addr_t dma; int ret; ret = rtw89_pci_alloc_tx_wd_ring(rtwdev, pdev, tx_ring, txch); if (ret) { rtw89_err(rtwdev, "failed to alloc txwd ring of txch %d\n", txch); goto err; } ret = rtw89_pci_get_txch_addrs(rtwdev, txch, &txch_addr); if (ret) { rtw89_err(rtwdev, "failed to get address of txch %d", txch); goto err_free_wd_ring; } head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); if (!head) { ret = -ENOMEM; goto err_free_wd_ring; } INIT_LIST_HEAD(&tx_ring->busy_pages); tx_ring->bd_ring.head = head; tx_ring->bd_ring.dma = dma; tx_ring->bd_ring.len = len; tx_ring->bd_ring.desc_size = desc_size; tx_ring->bd_ring.addr = *txch_addr; tx_ring->bd_ring.wp = 0; tx_ring->bd_ring.rp = 0; tx_ring->txch = txch; return 0; err_free_wd_ring: rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); err: return ret; } static int rtw89_pci_alloc_tx_rings(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; const struct rtw89_pci_info *info = rtwdev->pci_info; struct rtw89_pci_tx_ring *tx_ring; u32 desc_size; u32 len; u32 i, tx_allocated; int ret; for (i = 0; i < RTW89_TXCH_NUM; i++) { if (info->tx_dma_ch_mask & BIT(i)) continue; tx_ring = &rtwpci->tx_rings[i]; desc_size = sizeof(struct rtw89_pci_tx_bd_32); len = RTW89_PCI_TXBD_NUM_MAX; ret = rtw89_pci_alloc_tx_ring(rtwdev, pdev, tx_ring, desc_size, len, i); if (ret) { #if defined(__linux__) rtw89_err(rtwdev, "failed to alloc tx ring %d\n", i); #elif defined(__FreeBSD__) rtw89_err(rtwdev, "failed to alloc tx ring %d: ret=%d\n", i, ret); #endif goto err_free; } } return 0; err_free: tx_allocated = i; for (i = 0; i < tx_allocated; i++) { tx_ring = &rtwpci->tx_rings[i]; rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); } return ret; } static int rtw89_pci_alloc_rx_ring(struct rtw89_dev *rtwdev, struct pci_dev *pdev, struct rtw89_pci_rx_ring *rx_ring, u32 desc_size, u32 len, u32 rxch) { const struct rtw89_pci_ch_dma_addr *rxch_addr; struct sk_buff *skb; u8 *head; dma_addr_t dma; int ring_sz = desc_size * len; int buf_sz = RTW89_PCI_RX_BUF_SIZE; int i, allocated; int ret; ret = rtw89_pci_get_rxch_addrs(rtwdev, rxch, &rxch_addr); if (ret) { rtw89_err(rtwdev, "failed to get address of rxch %d", rxch); return ret; } head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); if (!head) { ret = -ENOMEM; goto err; } rx_ring->bd_ring.head = head; rx_ring->bd_ring.dma = dma; rx_ring->bd_ring.len = len; rx_ring->bd_ring.desc_size = desc_size; rx_ring->bd_ring.addr = *rxch_addr; rx_ring->bd_ring.wp = 0; rx_ring->bd_ring.rp = 0; rx_ring->buf_sz = buf_sz; rx_ring->diliver_skb = NULL; rx_ring->diliver_desc.ready = false; for (i = 0; i < len; i++) { skb = dev_alloc_skb(buf_sz); if (!skb) { ret = -ENOMEM; goto err_free; } memset(skb->data, 0, buf_sz); rx_ring->buf[i] = skb; ret = rtw89_pci_init_rx_bd(rtwdev, pdev, rx_ring, skb, buf_sz, i); if (ret) { #if defined(__linux__) rtw89_err(rtwdev, "failed to init rx buf %d\n", i); #elif defined(__FreeBSD__) rtw89_err(rtwdev, "failed to init rx buf %d ret=%d\n", i, ret); #endif dev_kfree_skb_any(skb); rx_ring->buf[i] = NULL; goto err_free; } } return 0; err_free: allocated = i; for (i = 0; i < allocated; i++) { skb = rx_ring->buf[i]; if (!skb) continue; dma = *((dma_addr_t *)skb->cb); dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); dev_kfree_skb(skb); rx_ring->buf[i] = NULL; } head = rx_ring->bd_ring.head; dma = rx_ring->bd_ring.dma; dma_free_coherent(&pdev->dev, ring_sz, head, dma); rx_ring->bd_ring.head = NULL; err: return ret; } static int rtw89_pci_alloc_rx_rings(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct rtw89_pci_rx_ring *rx_ring; u32 desc_size; u32 len; int i, rx_allocated; int ret; for (i = 0; i < RTW89_RXCH_NUM; i++) { rx_ring = &rtwpci->rx_rings[i]; desc_size = sizeof(struct rtw89_pci_rx_bd_32); len = RTW89_PCI_RXBD_NUM_MAX; ret = rtw89_pci_alloc_rx_ring(rtwdev, pdev, rx_ring, desc_size, len, i); if (ret) { rtw89_err(rtwdev, "failed to alloc rx ring %d\n", i); goto err_free; } } return 0; err_free: rx_allocated = i; for (i = 0; i < rx_allocated; i++) { rx_ring = &rtwpci->rx_rings[i]; rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); } return ret; } static int rtw89_pci_alloc_trx_rings(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { int ret; ret = rtw89_pci_alloc_tx_rings(rtwdev, pdev); if (ret) { rtw89_err(rtwdev, "failed to alloc dma tx rings\n"); goto err; } ret = rtw89_pci_alloc_rx_rings(rtwdev, pdev); if (ret) { rtw89_err(rtwdev, "failed to alloc dma rx rings\n"); goto err_free_tx_rings; } return 0; err_free_tx_rings: rtw89_pci_free_tx_rings(rtwdev, pdev); err: return ret; } static void rtw89_pci_h2c_init(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) { skb_queue_head_init(&rtwpci->h2c_queue); skb_queue_head_init(&rtwpci->h2c_release_queue); } static int rtw89_pci_setup_resource(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; int ret; ret = rtw89_pci_setup_mapping(rtwdev, pdev); if (ret) { rtw89_err(rtwdev, "failed to setup pci mapping\n"); goto err; } ret = rtw89_pci_alloc_trx_rings(rtwdev, pdev); if (ret) { rtw89_err(rtwdev, "failed to alloc pci trx rings\n"); goto err_pci_unmap; } rtw89_pci_h2c_init(rtwdev, rtwpci); spin_lock_init(&rtwpci->irq_lock); spin_lock_init(&rtwpci->trx_lock); return 0; err_pci_unmap: rtw89_pci_clear_mapping(rtwdev, pdev); err: return ret; } static void rtw89_pci_clear_resource(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; rtw89_pci_free_trx_rings(rtwdev, pdev); rtw89_pci_clear_mapping(rtwdev, pdev); rtw89_pci_release_fwcmd(rtwdev, rtwpci, skb_queue_len(&rtwpci->h2c_queue), true); } void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; const struct rtw89_chip_info *chip = rtwdev->chip; u32 hs0isr_ind_int_en = B_AX_HS0ISR_IND_INT_EN; if (chip->chip_id == RTL8851B) hs0isr_ind_int_en = B_AX_HS0ISR_IND_INT_EN_WKARND; rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | 0; if (rtwpci->under_recovery) { rtwpci->intrs[0] = hs0isr_ind_int_en; rtwpci->intrs[1] = 0; } else { rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN | B_AX_RXDMA_INT_EN | B_AX_RXP1DMA_INT_EN | B_AX_RPQDMA_INT_EN | B_AX_RXDMA_STUCK_INT_EN | B_AX_RDU_INT_EN | B_AX_RPQBD_FULL_INT_EN | hs0isr_ind_int_en; rtwpci->intrs[1] = B_AX_HC10ISR_IND_INT_EN; } } EXPORT_SYMBOL(rtw89_pci_config_intr_mask); static void rtw89_pci_recovery_intr_mask_v1(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; rtwpci->ind_intrs = B_AX_HS0ISR_IND_INT_EN; rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN; rtwpci->intrs[0] = 0; rtwpci->intrs[1] = 0; } static void rtw89_pci_default_intr_mask_v1(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; rtwpci->ind_intrs = B_AX_HCI_AXIDMA_INT_EN | B_AX_HS1ISR_IND_INT_EN | B_AX_HS0ISR_IND_INT_EN; rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN; rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN | B_AX_RXDMA_INT_EN | B_AX_RXP1DMA_INT_EN | B_AX_RPQDMA_INT_EN | B_AX_RXDMA_STUCK_INT_EN | B_AX_RDU_INT_EN | B_AX_RPQBD_FULL_INT_EN; rtwpci->intrs[1] = B_AX_GPIO18_INT_EN; } static void rtw89_pci_low_power_intr_mask_v1(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; rtwpci->ind_intrs = B_AX_HS1ISR_IND_INT_EN | B_AX_HS0ISR_IND_INT_EN; rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN; rtwpci->intrs[0] = 0; rtwpci->intrs[1] = B_AX_GPIO18_INT_EN; } void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; if (rtwpci->under_recovery) rtw89_pci_recovery_intr_mask_v1(rtwdev); else if (rtwpci->low_power) rtw89_pci_low_power_intr_mask_v1(rtwdev); else rtw89_pci_default_intr_mask_v1(rtwdev); } EXPORT_SYMBOL(rtw89_pci_config_intr_mask_v1); static int rtw89_pci_request_irq(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { unsigned long flags = 0; int ret; flags |= PCI_IRQ_LEGACY | PCI_IRQ_MSI; ret = pci_alloc_irq_vectors(pdev, 1, 1, flags); if (ret < 0) { rtw89_err(rtwdev, "failed to alloc irq vectors, ret %d\n", ret); goto err; } ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq, rtw89_pci_interrupt_handler, rtw89_pci_interrupt_threadfn, IRQF_SHARED, KBUILD_MODNAME, rtwdev); if (ret) { rtw89_err(rtwdev, "failed to request threaded irq\n"); goto err_free_vector; } rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RESET); return 0; err_free_vector: pci_free_irq_vectors(pdev); err: return ret; } static void rtw89_pci_free_irq(struct rtw89_dev *rtwdev, struct pci_dev *pdev) { devm_free_irq(rtwdev->dev, pdev->irq, rtwdev); pci_free_irq_vectors(pdev); } static u16 gray_code_to_bin(u16 gray_code, u32 bit_num) { u16 bin = 0, gray_bit; u32 bit_idx; for (bit_idx = 0; bit_idx < bit_num; bit_idx++) { gray_bit = (gray_code >> bit_idx) & 0x1; if (bit_num - bit_idx > 1) gray_bit ^= (gray_code >> (bit_idx + 1)) & 0x1; bin |= (gray_bit << bit_idx); } return bin; } static int rtw89_pci_filter_out(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct pci_dev *pdev = rtwpci->pdev; u16 val16, filter_out_val; u32 val, phy_offset; int ret; if (rtwdev->chip->chip_id != RTL8852C) return 0; val = rtw89_read32_mask(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_ASPM_CTRL_MASK); if (val == B_AX_ASPM_CTRL_L1) return 0; ret = pci_read_config_dword(pdev, RTW89_PCIE_L1_STS_V1, &val); if (ret) return ret; val = FIELD_GET(RTW89_BCFG_LINK_SPEED_MASK, val); if (val == RTW89_PCIE_GEN1_SPEED) { phy_offset = R_RAC_DIRECT_OFFSET_G1; } else if (val == RTW89_PCIE_GEN2_SPEED) { phy_offset = R_RAC_DIRECT_OFFSET_G2; val16 = rtw89_read16(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT); rtw89_write16_set(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT, val16 | B_PCIE_BIT_PINOUT_DIS); rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, val16 & ~B_PCIE_BIT_RD_SEL); val16 = rtw89_read16_mask(rtwdev, phy_offset + RAC_ANA1F * RAC_MULT, FILTER_OUT_EQ_MASK); val16 = gray_code_to_bin(val16, hweight16(val16)); filter_out_val = rtw89_read16(rtwdev, phy_offset + RAC_ANA24 * RAC_MULT); filter_out_val &= ~REG_FILTER_OUT_MASK; filter_out_val |= FIELD_PREP(REG_FILTER_OUT_MASK, val16); rtw89_write16(rtwdev, phy_offset + RAC_ANA24 * RAC_MULT, filter_out_val); rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0A * RAC_MULT, B_BAC_EQ_SEL); rtw89_write16_set(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA0C * RAC_MULT, B_PCIE_BIT_PSAVE); } else { return -EOPNOTSUPP; } rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0C * RAC_MULT, B_PCIE_BIT_PSAVE); return 0; } static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; int ret; if (rtw89_pci_disable_clkreq) return; ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL, PCIE_CLKDLY_HW_30US); if (ret) rtw89_err(rtwdev, "failed to set CLKREQ Delay\n"); if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) { if (enable) ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL, RTW89_PCIE_BIT_CLK); else ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1_CTRL, RTW89_PCIE_BIT_CLK); if (ret) rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d", enable ? "set" : "unset", ret); } else if (chip_id == RTL8852C) { rtw89_write32_set(rtwdev, R_AX_PCIE_LAT_CTRL, B_AX_CLK_REQ_SEL_OPT | B_AX_CLK_REQ_SEL); if (enable) rtw89_write32_set(rtwdev, R_AX_L1_CLK_CTRL, B_AX_CLK_REQ_N); else rtw89_write32_clr(rtwdev, R_AX_L1_CLK_CTRL, B_AX_CLK_REQ_N); } } static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; u8 value = 0; int ret; if (rtw89_pci_disable_aspm_l1) return; ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, &value); if (ret) rtw89_err(rtwdev, "failed to read ASPM Delay\n"); value &= ~(RTW89_L1DLY_MASK | RTW89_L0DLY_MASK); value |= FIELD_PREP(RTW89_L1DLY_MASK, PCIE_L1DLY_16US) | FIELD_PREP(RTW89_L0DLY_MASK, PCIE_L0SDLY_4US); ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, value); if (ret) rtw89_err(rtwdev, "failed to read ASPM Delay\n"); if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) { if (enable) ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL, RTW89_PCIE_BIT_L1); else ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1_CTRL, RTW89_PCIE_BIT_L1); } else if (chip_id == RTL8852C) { if (enable) rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_ASPM_CTRL_L1); else rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_ASPM_CTRL_L1); } if (ret) rtw89_err(rtwdev, "failed to %s ASPM L1, ret=%d", enable ? "set" : "unset", ret); } static void rtw89_pci_recalc_int_mit(struct rtw89_dev *rtwdev) { struct rtw89_traffic_stats *stats = &rtwdev->stats; enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; u32 val = 0; if (!rtwdev->scanning && (tx_tfc_lv >= RTW89_TFC_HIGH || rx_tfc_lv >= RTW89_TFC_HIGH)) val = B_AX_RXMIT_RXP2_SEL | B_AX_RXMIT_RXP1_SEL | FIELD_PREP(B_AX_RXCOUNTER_MATCH_MASK, RTW89_PCI_RXBD_NUM_MAX / 2) | FIELD_PREP(B_AX_RXTIMER_UNIT_MASK, AX_RXTIMER_UNIT_64US) | FIELD_PREP(B_AX_RXTIMER_MATCH_MASK, 2048 / 64); rtw89_write32(rtwdev, R_AX_INT_MIT_RX, val); } static void rtw89_pci_link_cfg(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct pci_dev *pdev = rtwpci->pdev; u16 link_ctrl; int ret; /* Though there is standard PCIE configuration space to set the * link control register, but by Realtek's design, driver should * check if host supports CLKREQ/ASPM to enable the HW module. * * These functions are implemented by two HW modules associated, * one is responsible to access PCIE configuration space to * follow the host settings, and another is in charge of doing * CLKREQ/ASPM mechanisms, it is default disabled. Because sometimes * the host does not support it, and due to some reasons or wrong * settings (ex. CLKREQ# not Bi-Direction), it could lead to device * loss if HW misbehaves on the link. * * Hence it's designed that driver should first check the PCIE * configuration space is sync'ed and enabled, then driver can turn * on the other module that is actually working on the mechanism. */ ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl); if (ret) { rtw89_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret); return; } if (link_ctrl & PCI_EXP_LNKCTL_CLKREQ_EN) rtw89_pci_clkreq_set(rtwdev, true); if (link_ctrl & PCI_EXP_LNKCTL_ASPM_L1) rtw89_pci_aspm_set(rtwdev, true); } static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; int ret; if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) { if (enable) ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_TIMER_CTRL, RTW89_PCIE_BIT_L1SUB); else ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_TIMER_CTRL, RTW89_PCIE_BIT_L1SUB); if (ret) rtw89_err(rtwdev, "failed to %s L1SS, ret=%d", enable ? "set" : "unset", ret); } else if (chip_id == RTL8852C) { ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1SS_STS_V1, RTW89_PCIE_BIT_ASPM_L11 | RTW89_PCIE_BIT_PCI_L11); if (ret) rtw89_warn(rtwdev, "failed to unset ASPM L1.1, ret=%d", ret); if (enable) rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_L1SUB_DISABLE); else rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_L1SUB_DISABLE); } } static void rtw89_pci_l1ss_cfg(struct rtw89_dev *rtwdev) { struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; struct pci_dev *pdev = rtwpci->pdev; u32 l1ss_cap_ptr, l1ss_ctrl; if (rtw89_pci_disable_l1ss) return; l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); if (!l1ss_cap_ptr) return; pci_read_config_dword(pdev, l1ss_cap_ptr + PCI_L1SS_CTL1, &l1ss_ctrl); if (l1ss_ctrl & PCI_L1SS_CTL1_L1SS_MASK) rtw89_pci_l1ss_set(rtwdev, true); } static int rtw89_pci_poll_io_idle(struct rtw89_dev *rtwdev) { int ret = 0; u32 sts; u32 busy = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY; ret = read_poll_timeout_atomic(rtw89_read32, sts, (sts & busy) == 0x0, 10, 1000, false, rtwdev, R_AX_PCIE_DMA_BUSY1); if (ret) { rtw89_err(rtwdev, "pci dmach busy1 0x%X\n", rtw89_read32(rtwdev, R_AX_PCIE_DMA_BUSY1)); return -EINVAL; } return ret; } static int rtw89_pci_lv1rst_stop_dma(struct rtw89_dev *rtwdev) { u32 val; int ret; if (rtwdev->chip->chip_id == RTL8852C) return 0; rtw89_pci_ctrl_dma_all(rtwdev, false); ret = rtw89_pci_poll_io_idle(rtwdev); if (ret) { val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); rtw89_debug(rtwdev, RTW89_DBG_HCI, "[PCIe] poll_io_idle fail, before 0x%08x: 0x%08x\n", R_AX_DBG_ERR_FLAG, val); if (val & B_AX_TX_STUCK || val & B_AX_PCIE_TXBD_LEN0) rtw89_mac_ctrl_hci_dma_tx(rtwdev, false); if (val & B_AX_RX_STUCK) rtw89_mac_ctrl_hci_dma_rx(rtwdev, false); rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); ret = rtw89_pci_poll_io_idle(rtwdev); val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); rtw89_debug(rtwdev, RTW89_DBG_HCI, "[PCIe] poll_io_idle fail, after 0x%08x: 0x%08x\n", R_AX_DBG_ERR_FLAG, val); } return ret; } static int rtw89_pci_rst_bdram(struct rtw89_dev *rtwdev) { int ret = 0; u32 val32, sts; val32 = B_AX_RST_BDRAM; rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, val32); ret = read_poll_timeout_atomic(rtw89_read32, sts, (sts & B_AX_RST_BDRAM) == 0x0, 1, 100, true, rtwdev, R_AX_PCIE_INIT_CFG1); return ret; } static int rtw89_pci_lv1rst_start_dma(struct rtw89_dev *rtwdev) { u32 ret; if (rtwdev->chip->chip_id == RTL8852C) return 0; rtw89_mac_ctrl_hci_dma_trx(rtwdev, false); rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); rtw89_pci_clr_idx_all(rtwdev); ret = rtw89_pci_rst_bdram(rtwdev); if (ret) return ret; rtw89_pci_ctrl_dma_all(rtwdev, true); return ret; } static int rtw89_pci_ops_mac_lv1_recovery(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step) { int ret; switch (step) { case RTW89_LV1_RCVY_STEP_1: ret = rtw89_pci_lv1rst_stop_dma(rtwdev); if (ret) rtw89_err(rtwdev, "lv1 rcvy pci stop dma fail\n"); break; case RTW89_LV1_RCVY_STEP_2: ret = rtw89_pci_lv1rst_start_dma(rtwdev); if (ret) rtw89_err(rtwdev, "lv1 rcvy pci start dma fail\n"); break; default: return -EINVAL; } return ret; } static void rtw89_pci_ops_dump_err_status(struct rtw89_dev *rtwdev) { rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX =0x%08x\n", rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); rtw89_info(rtwdev, "R_AX_DBG_ERR_FLAG=0x%08x\n", rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG)); rtw89_info(rtwdev, "R_AX_LBC_WATCHDOG=0x%08x\n", rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG)); } static int rtw89_pci_napi_poll(struct napi_struct *napi, int budget) { struct rtw89_dev *rtwdev = container_of(napi, struct rtw89_dev, napi); struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; unsigned long flags; int work_done; rtwdev->napi_budget_countdown = budget; rtw89_pci_clear_isr0(rtwdev, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT); work_done = rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); if (work_done == budget) return budget; rtw89_pci_clear_isr0(rtwdev, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT | B_AX_RDU_INT); work_done += rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); if (work_done < budget && napi_complete_done(napi, work_done)) { spin_lock_irqsave(&rtwpci->irq_lock, flags); if (likely(rtwpci->running)) rtw89_chip_enable_intr(rtwdev, rtwpci); spin_unlock_irqrestore(&rtwpci->irq_lock, flags); } return work_done; } static int __maybe_unused rtw89_pci_suspend(struct device *dev) { struct ieee80211_hw *hw = dev_get_drvdata(dev); struct rtw89_dev *rtwdev = hw->priv; enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) { rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); } else { rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_CMAC_EXIT_L1_EN | B_AX_DMAC0_EXIT_L1_EN); } return 0; } static void rtw89_pci_l2_hci_ldo(struct rtw89_dev *rtwdev) { if (rtwdev->chip->chip_id == RTL8852C) return; /* Hardware need write the reg twice to ensure the setting work */ rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_RST_MSTATE, RTW89_PCIE_BIT_CFG_RST_MSTATE); rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_RST_MSTATE, RTW89_PCIE_BIT_CFG_RST_MSTATE); } static int __maybe_unused rtw89_pci_resume(struct device *dev) { struct ieee80211_hw *hw = dev_get_drvdata(dev); struct rtw89_dev *rtwdev = hw->priv; enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) { rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); } else { rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_CMAC_EXIT_L1_EN | B_AX_DMAC0_EXIT_L1_EN); rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_SEL_REQ_ENTR_L1); } rtw89_pci_l2_hci_ldo(rtwdev); rtw89_pci_filter_out(rtwdev); rtw89_pci_link_cfg(rtwdev); rtw89_pci_l1ss_cfg(rtwdev); return 0; } SIMPLE_DEV_PM_OPS(rtw89_pm_ops, rtw89_pci_suspend, rtw89_pci_resume); EXPORT_SYMBOL(rtw89_pm_ops); static const struct rtw89_hci_ops rtw89_pci_ops = { .tx_write = rtw89_pci_ops_tx_write, .tx_kick_off = rtw89_pci_ops_tx_kick_off, .flush_queues = rtw89_pci_ops_flush_queues, .reset = rtw89_pci_ops_reset, .start = rtw89_pci_ops_start, .stop = rtw89_pci_ops_stop, .pause = rtw89_pci_ops_pause, .switch_mode = rtw89_pci_ops_switch_mode, .recalc_int_mit = rtw89_pci_recalc_int_mit, .read8 = rtw89_pci_ops_read8, .read16 = rtw89_pci_ops_read16, .read32 = rtw89_pci_ops_read32, .write8 = rtw89_pci_ops_write8, .write16 = rtw89_pci_ops_write16, .write32 = rtw89_pci_ops_write32, .mac_pre_init = rtw89_pci_ops_mac_pre_init, .mac_post_init = rtw89_pci_ops_mac_post_init, .deinit = rtw89_pci_ops_deinit, .check_and_reclaim_tx_resource = rtw89_pci_check_and_reclaim_tx_resource, .mac_lv1_rcvy = rtw89_pci_ops_mac_lv1_recovery, .dump_err_status = rtw89_pci_ops_dump_err_status, .napi_poll = rtw89_pci_napi_poll, .recovery_start = rtw89_pci_ops_recovery_start, .recovery_complete = rtw89_pci_ops_recovery_complete, .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch_pcie, .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch_pcie, .ctrl_trxhci = rtw89_pci_ctrl_dma_trx, .poll_txdma_ch = rtw89_poll_txdma_ch_idle_pcie, .clr_idx_all = rtw89_pci_clr_idx_all, .clear = rtw89_pci_clear_resource, .disable_intr = rtw89_pci_disable_intr_lock, .enable_intr = rtw89_pci_enable_intr_lock, .rst_bdram = rtw89_pci_rst_bdram_pcie, }; int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct rtw89_dev *rtwdev; const struct rtw89_driver_info *info; const struct rtw89_pci_info *pci_info; int ret; info = (const struct rtw89_driver_info *)id->driver_data; rtwdev = rtw89_alloc_ieee80211_hw(&pdev->dev, sizeof(struct rtw89_pci), info->chip); if (!rtwdev) { dev_err(&pdev->dev, "failed to allocate hw\n"); return -ENOMEM; } pci_info = info->bus.pci; rtwdev->pci_info = info->bus.pci; rtwdev->hci.ops = &rtw89_pci_ops; rtwdev->hci.type = RTW89_HCI_TYPE_PCIE; rtwdev->hci.rpwm_addr = pci_info->rpwm_addr; rtwdev->hci.cpwm_addr = pci_info->cpwm_addr; SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev); ret = rtw89_core_init(rtwdev); if (ret) { rtw89_err(rtwdev, "failed to initialise core\n"); goto err_release_hw; } ret = rtw89_pci_claim_device(rtwdev, pdev); if (ret) { rtw89_err(rtwdev, "failed to claim pci device\n"); goto err_core_deinit; } ret = rtw89_pci_setup_resource(rtwdev, pdev); if (ret) { rtw89_err(rtwdev, "failed to setup pci resource\n"); goto err_declaim_pci; } ret = rtw89_chip_info_setup(rtwdev); if (ret) { rtw89_err(rtwdev, "failed to setup chip information\n"); goto err_clear_resource; } rtw89_pci_filter_out(rtwdev); rtw89_pci_link_cfg(rtwdev); rtw89_pci_l1ss_cfg(rtwdev); rtw89_core_napi_init(rtwdev); ret = rtw89_pci_request_irq(rtwdev, pdev); if (ret) { rtw89_err(rtwdev, "failed to request pci irq\n"); goto err_deinit_napi; } ret = rtw89_core_register(rtwdev); if (ret) { rtw89_err(rtwdev, "failed to register core\n"); goto err_free_irq; } return 0; err_free_irq: rtw89_pci_free_irq(rtwdev, pdev); err_deinit_napi: rtw89_core_napi_deinit(rtwdev); err_clear_resource: rtw89_pci_clear_resource(rtwdev, pdev); err_declaim_pci: rtw89_pci_declaim_device(rtwdev, pdev); err_core_deinit: rtw89_core_deinit(rtwdev); err_release_hw: rtw89_free_ieee80211_hw(rtwdev); return ret; } EXPORT_SYMBOL(rtw89_pci_probe); void rtw89_pci_remove(struct pci_dev *pdev) { struct ieee80211_hw *hw = pci_get_drvdata(pdev); struct rtw89_dev *rtwdev; rtwdev = hw->priv; rtw89_pci_free_irq(rtwdev, pdev); rtw89_core_napi_deinit(rtwdev); rtw89_core_unregister(rtwdev); rtw89_pci_clear_resource(rtwdev, pdev); rtw89_pci_declaim_device(rtwdev, pdev); rtw89_core_deinit(rtwdev); rtw89_free_ieee80211_hw(rtwdev); } EXPORT_SYMBOL(rtw89_pci_remove); MODULE_AUTHOR("Realtek Corporation"); MODULE_DESCRIPTION("Realtek 802.11ax wireless PCI driver"); MODULE_LICENSE("Dual BSD/GPL"); #if defined(__FreeBSD__) MODULE_VERSION(rtw89_pci, 1); MODULE_DEPEND(rtw89_pci, linuxkpi, 1, 1, 1); MODULE_DEPEND(rtw89_pci, linuxkpi_wlan, 1, 1, 1); #ifdef CONFIG_RTW89_DEBUGFS MODULE_DEPEND(rtw89_pci, lindebugfs, 1, 1, 1); #endif #endif