diff --git a/share/man/man4/pci.4 b/share/man/man4/pci.4 index 28a456d18179..3c2c08afe466 100644 --- a/share/man/man4/pci.4 +++ b/share/man/man4/pci.4 @@ -1,675 +1,709 @@ .\" .\" Copyright (c) 1999 Kenneth D. Merry. .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. The name of the author may not be used to endorse or promote products .\" derived from this software without specific prior written permission. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" -.Dd July 27, 2021 +.Dd August 13, 2021 .Dt PCI 4 .Os .Sh NAME .Nm pci .Nd generic PCI/PCIe bus driver .Sh SYNOPSIS To compile the PCI bus driver into the kernel, place the following line in your kernel configuration file: .Bd -ragged -offset indent .Cd device pci .Ed .Pp To compile in support for Single Root I/O Virtualization .Pq SR-IOV : .Bd -ragged -offset indent .Cd options PCI_IOV .Ed .Pp To compile in support for native PCI-express HotPlug: .Bd -ragged -offset indent .Cd options PCI_HP .Ed .Sh DESCRIPTION The .Nm driver provides support for .Tn PCI and .Tn PCIe devices in the kernel and limited access to .Tn PCI devices for userland. .Pp The .Nm driver provides a .Pa /dev/pci character device that can be used by userland programs to read and write .Tn PCI configuration registers. Programs can also use this device to get a list of all .Tn PCI devices, or all .Tn PCI devices that match various patterns. .Pp Since the .Nm driver provides a write interface for .Tn PCI configuration registers, system administrators should exercise caution when granting access to the .Nm device. If used improperly, this driver can allow userland applications to crash a machine or cause data loss. In particular, driver only allows operations on the opened .Pa /dev/pci to modify system state if the file descriptor was opened for writing. For instance, the .Dv PCIOCREAD and .Dv PCIOCBARMMAP operations require a writeable descriptor, because reading a config register or a BAR read access could have function-specific side-effects. .Pp The .Nm driver implements the .Tn PCI bus in the kernel. It enumerates any devices on the .Tn PCI bus and gives .Tn PCI client drivers the chance to attach to them. It assigns resources to children, when the BIOS does not. It takes care of routing interrupts when necessary. It reprobes the unattached .Tn PCI children when .Tn PCI client drivers are dynamically loaded at runtime. The .Nm driver also includes support for PCI-PCI bridges, various platform-specific Host-PCI bridges, and basic support for .Tn PCI VGA adapters. .Sh IOCTLS The following .Xr ioctl 2 calls are supported by the .Nm driver. They are defined in the header file .In sys/pciio.h . .Bl -tag -width 012345678901234 .It PCIOCGETCONF This .Xr ioctl 2 takes a .Va pci_conf_io structure. It allows the user to retrieve information on all .Tn PCI devices in the system, or on .Tn PCI devices matching patterns supplied by the user. The call may set .Va errno to any value specified in either .Xr copyin 9 or .Xr copyout 9 . The .Va pci_conf_io structure consists of a number of fields: .Bl -tag -width match_buf_len .It pat_buf_len The length, in bytes, of the buffer filled with user-supplied patterns. .It num_patterns The number of user-supplied patterns. .It patterns Pointer to a buffer filled with user-supplied patterns. .Va patterns is a pointer to .Va num_patterns .Va pci_match_conf structures. The .Va pci_match_conf structure consists of the following elements: .Bl -tag -width pd_vendor .It pc_sel .Tn PCI domain, bus, slot and function. .It pd_name .Tn PCI device driver name. .It pd_unit .Tn PCI device driver unit number. .It pc_vendor .Tn PCI vendor ID. .It pc_device .Tn PCI device ID. .It pc_class .Tn PCI device class. .It flags The flags describe which of the fields the kernel should match against. A device must match all specified fields in order to be returned. The match flags are enumerated in the .Va pci_getconf_flags structure. Hopefully the flag values are obvious enough that they do not need to described in detail. .El .It match_buf_len Length of the .Va matches buffer allocated by the user to hold the results of the .Dv PCIOCGETCONF query. .It num_matches Number of matches returned by the kernel. .It matches Buffer containing matching devices returned by the kernel. The items in this buffer are of type .Va pci_conf , which consists of the following items: .Bl -tag -width pc_subvendor .It pc_sel .Tn PCI domain, bus, slot and function. .It pc_hdr .Tn PCI header type. .It pc_subvendor .Tn PCI subvendor ID. .It pc_subdevice .Tn PCI subdevice ID. .It pc_vendor .Tn PCI vendor ID. .It pc_device .Tn PCI device ID. .It pc_class .Tn PCI device class. .It pc_subclass .Tn PCI device subclass. .It pc_progif .Tn PCI device programming interface. .It pc_revid .Tn PCI revision ID. .It pd_name Driver name. .It pd_unit Driver unit number. .El .It offset The offset is passed in by the user to tell the kernel where it should start traversing the device list. The value passed out by the kernel points to the record immediately after the last one returned. The user may pass the value returned by the kernel in subsequent calls to the .Dv PCIOCGETCONF ioctl. If the user does not intend to use the offset, it must be set to zero. .It generation .Tn PCI configuration generation. This value only needs to be set if the offset is set. The kernel will compare the current generation number of its internal device list to the generation passed in by the user to determine whether its device list has changed since the user last called the .Dv PCIOCGETCONF ioctl. If the device list has changed, a status of .Va PCI_GETCONF_LIST_CHANGED will be passed back. .It status The status tells the user the disposition of his request for a device list. The possible status values are: .Bl -ohang .It PCI_GETCONF_LAST_DEVICE This means that there are no more devices in the PCI device list matching the specified criteria after the ones returned in the .Va matches buffer. .It PCI_GETCONF_LIST_CHANGED This status tells the user that the .Tn PCI device list has changed since his last call to the .Dv PCIOCGETCONF ioctl and he must reset the .Va offset and .Va generation to zero to start over at the beginning of the list. .It PCI_GETCONF_MORE_DEVS This tells the user that his buffer was not large enough to hold all of the remaining devices in the device list that match his criteria. .It PCI_GETCONF_ERROR This indicates a general error while servicing the user's request. If the .Va pat_buf_len is not equal to .Va num_patterns times .Fn sizeof "struct pci_match_conf" , .Va errno will be set to .Er EINVAL . .El .El .It PCIOCREAD This .Xr ioctl 2 reads the .Tn PCI configuration registers specified by the passed-in .Va pci_io structure. The .Va pci_io structure consists of the following fields: .Bl -tag -width pi_width .It pi_sel A .Va pcisel structure which specifies the domain, bus, slot and function the user would like to query. If the specific bus is not found, errno will be set to ENODEV and -1 returned from the ioctl. .It pi_reg The .Tn PCI configuration registers the user would like to access. .It pi_width The width, in bytes, of the data the user would like to read. This value may be either 1, 2, or 4. 3-byte reads and reads larger than 4 bytes are not supported. If an invalid width is passed, errno will be set to EINVAL. .It pi_data The data returned by the kernel. .El .It PCIOCWRITE This .Xr ioctl 2 allows users to write to the .Tn PCI configuration registers specified in the passed-in .Va pci_io structure. The .Va pci_io structure is described above. The limitations on data width described for reading registers, above, also apply to writing .Tn PCI configuration registers. .It PCIOCATTACHED This .Xr ioctl 2 allows users to query if a driver is attached to the .Tn PCI device specified in the passed-in .Va pci_io structure. The .Va pci_io structure is described above, however, the .Va pi_reg and .Va pi_width fields are not used. The status of the device is stored in the .Va pi_data field. A value of 0 indicates no driver is attached, while a value larger than 0 indicates that a driver is attached. .It PCIOCBARMMAP This .Xr ioctl 2 command allows userspace processes to .Xr mmap 2 the memory-mapped PCI BAR into its address space. The input parameters and results are passed in the .Va pci_bar_mmap structure, which has the following fields: .Bl -tag -width Vt struct pcise pbm_sel .It Vt uint64_t pbm_map_base Reports the established mapping base to the caller. If .Va PCIIO_BAR_MMAP_FIXED flag was specified, then this field must be filled before the call with the desired address for the mapping. .It Vt uint64_t pbm_map_length Reports the mapped length of the BAR, in bytes. Its .Vt uint64_t value is always multiple of machine pages. .It Vt int64_t pbm_bar_length Reports length of the bar as exposed by the device. .It Vt int pbm_bar_off Reports offset from the mapped base to the start of the first register in the bar. .It Vt struct pcisel pbm_sel Should be filled before the call. Describes the device to operate on. .It Vt int pbm_reg The BAR index to mmap. .It Vt int pbm_flags Flags which augments the operation. See below. .It Vt int pbm_memattr The caching attribute for the mapping. Typical values are .Dv VM_MEMATTR_UNCACHEABLE for control registers BARs, and .Dv VM_MEMATTR_WRITE_COMBINING for frame buffers. Regular memory-like BAR should be mapped with .Dv VM_MEMATTR_DEFAULT attribute. .El .Pp Currently defined flags are: .Bl -tag -width PCIIO_BAR_MMAP_ACTIVATE .It PCIIO_BAR_MMAP_FIXED The resulted mappings should be established at the address specified by the .Va pbm_map_base member, otherwise fail. .It PCIIO_BAR_MMAP_EXCL Must be used together with .Dv PCIIO_BAR_MMAP_FIXED If the specified base contains already established mappings, the operation fails instead of implicitly unmapping them. .It PCIIO_BAR_MMAP_RW The requested mapping allows both reading and writing. Without the flag, read-only mapping is established. Note that it is common for the device registers to have side-effects even on reads. .It PCIIO_BAR_MMAP_ACTIVATE (Unimplemented) If the BAR is not activated, activate it in the course of mapping. Currently attempt to mmap an inactive BAR results in error. .El +.It PCIOCBARIO +This +.Xr ioctl 2 +command allows users to read from and write to BARs. +The I/O request parameters are passed in a +.Va struct pci_bar_ioreq +structure, which has the following fields: +.Bl -tag +.It Vt struct pcisel pbi_sel +Describes the device to operate on. +.It Vt int pbi_op +The operation to perform. +Currently supported values are +.Dv PCIBARIO_READ +and +.Dv PCIBARIO_WRITE . +.It Vt uint32_t pbi_bar +The index of the BAR on which to operate. +.It Vt uint32_t pbi_offset +The offset into the BAR at which to operate. +.It Vt uint32_t pbi_width +The size, in bytes, of the I/O operation. +1-byte, 2-byte, 4-byte and 8-byte perations are supported. +.It Vt uint32_t pbi_value +For reads, the value is returned in this field. +For writes, the caller specifies the value to be written in this field. +.Pp +Note that this operation maps and unmaps the corresponding resource and +so is relatively expensive for memory BARs. +The +.Va PCIOCBARMMAP +.Xr ioctl 2 +can be used to create a persistent userspace mapping for such BARs instead. +.El .El .Sh LOADER TUNABLES Tunables can be set at the .Xr loader 8 prompt before booting the kernel, or stored in .Xr loader.conf 5 . The current value of these tunables can be examined at runtime via .Xr sysctl 8 nodes of the same name. Unless otherwise specified, each of these tunables is a boolean that can be enabled by setting the tunable to a non-zero value. .Bl -tag -width indent .It Va hw.pci.clear_bars Pq Defaults to 0 Ignore any firmware-assigned memory and I/O port resources. This forces the .Tn PCI bus driver to allocate resource ranges for memory and I/O port resources from scratch. .It Va hw.pci.clear_buses Pq Defaults to 0 Ignore any firmware-assigned bus number registers in PCI-PCI bridges. This forces the .Tn PCI bus driver and PCI-PCI bridge driver to allocate bus numbers for secondary buses behind PCI-PCI bridges. .It Va hw.pci.clear_pcib Pq Defaults to 0 Ignore any firmware-assigned memory and I/O port resource windows in PCI-PCI bridges. This forces the PCI-PCI bridge driver to allocate memory and I/O port resources for resource windows from scratch. .Pp By default the PCI-PCI bridge driver will allocate windows that contain the firmware-assigned resources devices behind the bridge. In addition, the PCI-PCI bridge driver will suballocate from existing window regions when possible to satisfy a resource request. As a result, both .Va hw.pci.clear_bars and .Va hw.pci.clear_pcib must be enabled to fully ignore firmware-supplied resource assignments. .It Va hw.pci.default_vgapci_unit Pq Defaults to -1 By default, the first .Tn PCI VGA adapter encountered by the system is assumed to be the boot display device. This tunable can be set to choose a specific VGA adapter by specifying the unit number of the associated .Va vgapci Ns Ar X device. .It Va hw.pci.do_power_nodriver Pq Defaults to 0 Place devices into a low power state .Pq D3 when a suitable device driver is not found. Can be set to one of the following values: .Bl -tag -width indent .It 3 Powers down all .Tn PCI devices without a device driver. .It 2 Powers down most devices without a device driver. PCI devices with the display, memory, and base peripheral device classes are not powered down. .It 1 Similar to a setting of 2 except that storage controllers are also not powered down. .It 0 All devices are left fully powered. .El .Pp A .Tn PCI device must support power management to be powered down. Placing a device into a low power state may not reduce power consumption. .It Va hw.pci.do_power_resume Pq Defaults to 1 Place .Tn PCI devices into the fully powered state when resuming either the system or an individual device. Setting this to zero is discouraged as the system will not attempt to power up non-powered PCI devices after a suspend. .It Va hw.pci.do_power_suspend Pq Defaults to 1 Place .Tn PCI devices into a low power state when suspending either the system or individual devices. Normally the D3 state is used as the low power state, but firmware may override the desired power state during a system suspend. .It Va hw.pci.enable_ari Pq Defaults to 1 Enable support for PCI-express Alternative RID Interpretation. This is often used in conjunction with SR-IOV. .It Va hw.pci.enable_io_modes Pq Defaults to 1 Enable memory or I/O port decoding in a PCI device's command register if it has firmware-assigned memory or I/O port resources. The firmware .Pq BIOS in some systems does not enable memory or I/O port decoding for some devices even when it has assigned resources to the device. This enables decoding for such resources during bus probe. .It Va hw.pci.enable_msi Pq Defaults to 1 Enable support for Message Signalled Interrupts .Pq MSI . MSI interrupts can be disabled by setting this tunable to 0. .It Va hw.pci.enable_msix Pq Defaults to 1 Enable support for extended Message Signalled Interrupts .Pq MSI-X . MSI-X interrupts can be disabled by setting this tunable to 0. .It Va hw.pci.enable_pcie_hp Pq Defaults to 1 Enable support for native PCI-express HotPlug. .It Va hw.pci.honor_msi_blacklist Pq Defaults to 1 MSI and MSI-X interrupts are disabled for certain chipsets known to have broken MSI and MSI-X implementations when this tunable is set. It can be set to zero to permit use of MSI and MSI-X interrupts if the chipset match is a false positive. .It Va hw.pci.iov_max_config Pq Defaults to 1MB The maximum amount of memory permitted for the configuration parameters used when creating Virtual Functions via SR-IOV. This tunable can also be changed at runtime via .Xr sysctl 8 . .It Va hw.pci.realloc_bars Pq Defaults to 0 Attempt to allocate a new resource range during the initial device scan for any memory or I/O port resources with firmware-assigned ranges that conflict with another active resource. .It Va hw.pci.usb_early_takeover Pq Defaults to 1 on Tn amd64 and Tn i386 Disable legacy device emulation of USB devices during the initial device scan. Set this tunable to zero to use USB devices via legacy emulation when using a custom kernel without USB controller drivers. .It Va hw.pci...INT

.irq These tunables can be used to override the interrupt routing for legacy PCI INTx interrupts. Unlike other tunables in this list, these do not have corresponding sysctl nodes. The tunable name includes the address of the PCI device as well as the pin of the desired INTx IRQ to override: .Bl -tag -width indent .It The domain .Pq or segment of the PCI device in decimal. .It The bus address of the PCI device in decimal. .It The slot of the PCI device in decimal. .It

The interrupt pin of the PCI slot to override. One of .Ql A , .Ql B , .Ql C , or .Ql D . .El .Pp The value of the tunable is the raw IRQ value to use for the INTx interrupt pin identified by the tunable name. Mapping of IRQ values to platform interrupt sources is machine dependent. .El .Sh DEVICE WIRING You can wire the device unit at a given location with device.hints. Entries of the form .Va hints...at="pci::" or .Va hints...at="pci:::" will force the driver .Va name to probe and attach at unit .Va unit for any PCI device found to match the specification, where: .Bl -tag -width -indent .It The domain .Pq or segment of the PCI device in decimal. Defaults to 0 if unspecified .It The bus address of the PCI device in decimal. .It The slot of the PCI device in decimal. .It The function of the PCI device in decimal. .El .Pp The code to do the matching requires an exact string match. Do not specify the angle brackets .Pq < > in the hints file. Wiring multiple devices to the same .Va name and .Va unit produces undefined results. .Ss Examples Given the following lines in .Pa /boot/device.hints : .Cd hint.nvme.3.at="pci6:0:0" .Cd hint.igb.8.at="pci14:0:0" If there is a device that supports .Xr igb 4 at PCI bus 14 slot 0 function 0, then it will be assigned igb8 for probe and attach. Likewise, if there is an .Xr nvme 4 card at PCI bus 6 slot 0 function 0, then it will be assigned nvme3 for probe and attach. If another type of card is in either of these locations, the name and unit of that card will be the default names and will be unaffected by these hints. If other igb or nvme cards are located elsewhere, they will be assigned their unit numbers sequentially, skipping the unit numbers that have 'at' hints. .Sh FILES .Bl -tag -width /dev/pci -compact .It Pa /dev/pci Character device for the .Nm driver. .El .Sh SEE ALSO .Xr pciconf 8 .Sh HISTORY The .Nm driver (not the kernel's .Tn PCI support code) first appeared in .Fx 2.2 , and was written by Stefan Esser and Garrett Wollman. Support for device listing and matching was re-implemented by Kenneth Merry, and first appeared in .Fx 3.0 . .Sh AUTHORS .An Kenneth Merry Aq Mt ken@FreeBSD.org .Sh BUGS It is not possible for users to specify an accurate offset into the device list without calling the .Dv PCIOCGETCONF at least once, since they have no way of knowing the current generation number otherwise. This probably is not a serious problem, though, since users can easily narrow their search by specifying a pattern or patterns for the kernel to match against. diff --git a/sys/dev/pci/pci_user.c b/sys/dev/pci/pci_user.c index e1813b67c05c..7ebd9b66138c 100644 --- a/sys/dev/pci/pci_user.c +++ b/sys/dev/pci/pci_user.c @@ -1,1318 +1,1418 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright 1997, Stefan Esser * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_bus.h" /* XXX trim includes */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" #include "pci_if.h" #ifdef COMPAT_FREEBSD32 struct pci_conf32 { struct pcisel pc_sel; /* domain+bus+slot+function */ u_int8_t pc_hdr; /* PCI header type */ u_int16_t pc_subvendor; /* card vendor ID */ u_int16_t pc_subdevice; /* card device ID, assigned by card vendor */ u_int16_t pc_vendor; /* chip vendor ID */ u_int16_t pc_device; /* chip device ID, assigned by chip vendor */ u_int8_t pc_class; /* chip PCI class */ u_int8_t pc_subclass; /* chip PCI subclass */ u_int8_t pc_progif; /* chip PCI programming interface */ u_int8_t pc_revid; /* chip revision ID */ char pd_name[PCI_MAXNAMELEN + 1]; /* device name */ u_int32_t pd_unit; /* device unit number */ }; struct pci_match_conf32 { struct pcisel pc_sel; /* domain+bus+slot+function */ char pd_name[PCI_MAXNAMELEN + 1]; /* device name */ u_int32_t pd_unit; /* Unit number */ u_int16_t pc_vendor; /* PCI Vendor ID */ u_int16_t pc_device; /* PCI Device ID */ u_int8_t pc_class; /* PCI class */ u_int32_t flags; /* Matching expression */ }; struct pci_conf_io32 { u_int32_t pat_buf_len; /* pattern buffer length */ u_int32_t num_patterns; /* number of patterns */ u_int32_t patterns; /* struct pci_match_conf ptr */ u_int32_t match_buf_len; /* match buffer length */ u_int32_t num_matches; /* number of matches returned */ u_int32_t matches; /* struct pci_conf ptr */ u_int32_t offset; /* offset into device list */ u_int32_t generation; /* device list generation */ u_int32_t status; /* request status */ }; #define PCIOCGETCONF32 _IOC_NEWTYPE(PCIOCGETCONF, struct pci_conf_io32) #endif /* * This is the user interface to PCI configuration space. */ static d_open_t pci_open; static d_close_t pci_close; static d_ioctl_t pci_ioctl; struct cdevsw pcicdev = { .d_version = D_VERSION, .d_flags = 0, .d_open = pci_open, .d_close = pci_close, .d_ioctl = pci_ioctl, .d_name = "pci", }; static int pci_open(struct cdev *dev, int oflags, int devtype, struct thread *td) { int error; if (oflags & FWRITE) { error = securelevel_gt(td->td_ucred, 0); if (error) return (error); } return (0); } static int pci_close(struct cdev *dev, int flag, int devtype, struct thread *td) { return 0; } /* * Match a single pci_conf structure against an array of pci_match_conf * structures. The first argument, 'matches', is an array of num_matches * pci_match_conf structures. match_buf is a pointer to the pci_conf * structure that will be compared to every entry in the matches array. * This function returns 1 on failure, 0 on success. */ static int pci_conf_match_native(struct pci_match_conf *matches, int num_matches, struct pci_conf *match_buf) { int i; if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) return(1); for (i = 0; i < num_matches; i++) { /* * I'm not sure why someone would do this...but... */ if (matches[i].flags == PCI_GETCONF_NO_MATCH) continue; /* * Look at each of the match flags. If it's set, do the * comparison. If the comparison fails, we don't have a * match, go on to the next item if there is one. */ if (((matches[i].flags & PCI_GETCONF_MATCH_DOMAIN) != 0) && (match_buf->pc_sel.pc_domain != matches[i].pc_sel.pc_domain)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) && (match_buf->pc_vendor != matches[i].pc_vendor)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) && (match_buf->pc_device != matches[i].pc_device)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) && (match_buf->pc_class != matches[i].pc_class)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) && (match_buf->pd_unit != matches[i].pd_unit)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) && (strncmp(matches[i].pd_name, match_buf->pd_name, sizeof(match_buf->pd_name)) != 0)) continue; return(0); } return(1); } #ifdef COMPAT_FREEBSD32 static int pci_conf_match32(struct pci_match_conf32 *matches, int num_matches, struct pci_conf *match_buf) { int i; if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) return(1); for (i = 0; i < num_matches; i++) { /* * I'm not sure why someone would do this...but... */ if (matches[i].flags == PCI_GETCONF_NO_MATCH) continue; /* * Look at each of the match flags. If it's set, do the * comparison. If the comparison fails, we don't have a * match, go on to the next item if there is one. */ if (((matches[i].flags & PCI_GETCONF_MATCH_DOMAIN) != 0) && (match_buf->pc_sel.pc_domain != matches[i].pc_sel.pc_domain)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) && (match_buf->pc_vendor != matches[i].pc_vendor)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) && (match_buf->pc_device != matches[i].pc_device)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) && (match_buf->pc_class != matches[i].pc_class)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) && (match_buf->pd_unit != matches[i].pd_unit)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) && (strncmp(matches[i].pd_name, match_buf->pd_name, sizeof(match_buf->pd_name)) != 0)) continue; return(0); } return(1); } #endif /* COMPAT_FREEBSD32 */ #if defined(COMPAT_FREEBSD4) || defined(COMPAT_FREEBSD5) || \ defined(COMPAT_FREEBSD6) #define PRE7_COMPAT typedef enum { PCI_GETCONF_NO_MATCH_OLD = 0x00, PCI_GETCONF_MATCH_BUS_OLD = 0x01, PCI_GETCONF_MATCH_DEV_OLD = 0x02, PCI_GETCONF_MATCH_FUNC_OLD = 0x04, PCI_GETCONF_MATCH_NAME_OLD = 0x08, PCI_GETCONF_MATCH_UNIT_OLD = 0x10, PCI_GETCONF_MATCH_VENDOR_OLD = 0x20, PCI_GETCONF_MATCH_DEVICE_OLD = 0x40, PCI_GETCONF_MATCH_CLASS_OLD = 0x80 } pci_getconf_flags_old; struct pcisel_old { u_int8_t pc_bus; /* bus number */ u_int8_t pc_dev; /* device on this bus */ u_int8_t pc_func; /* function on this device */ }; struct pci_conf_old { struct pcisel_old pc_sel; /* bus+slot+function */ u_int8_t pc_hdr; /* PCI header type */ u_int16_t pc_subvendor; /* card vendor ID */ u_int16_t pc_subdevice; /* card device ID, assigned by card vendor */ u_int16_t pc_vendor; /* chip vendor ID */ u_int16_t pc_device; /* chip device ID, assigned by chip vendor */ u_int8_t pc_class; /* chip PCI class */ u_int8_t pc_subclass; /* chip PCI subclass */ u_int8_t pc_progif; /* chip PCI programming interface */ u_int8_t pc_revid; /* chip revision ID */ char pd_name[PCI_MAXNAMELEN + 1]; /* device name */ u_long pd_unit; /* device unit number */ }; struct pci_match_conf_old { struct pcisel_old pc_sel; /* bus+slot+function */ char pd_name[PCI_MAXNAMELEN + 1]; /* device name */ u_long pd_unit; /* Unit number */ u_int16_t pc_vendor; /* PCI Vendor ID */ u_int16_t pc_device; /* PCI Device ID */ u_int8_t pc_class; /* PCI class */ pci_getconf_flags_old flags; /* Matching expression */ }; struct pci_io_old { struct pcisel_old pi_sel; /* device to operate on */ int pi_reg; /* configuration register to examine */ int pi_width; /* width (in bytes) of read or write */ u_int32_t pi_data; /* data to write or result of read */ }; #ifdef COMPAT_FREEBSD32 struct pci_conf_old32 { struct pcisel_old pc_sel; /* bus+slot+function */ uint8_t pc_hdr; /* PCI header type */ uint16_t pc_subvendor; /* card vendor ID */ uint16_t pc_subdevice; /* card device ID, assigned by card vendor */ uint16_t pc_vendor; /* chip vendor ID */ uint16_t pc_device; /* chip device ID, assigned by chip vendor */ uint8_t pc_class; /* chip PCI class */ uint8_t pc_subclass; /* chip PCI subclass */ uint8_t pc_progif; /* chip PCI programming interface */ uint8_t pc_revid; /* chip revision ID */ char pd_name[PCI_MAXNAMELEN + 1]; /* device name */ uint32_t pd_unit; /* device unit number (u_long) */ }; struct pci_match_conf_old32 { struct pcisel_old pc_sel; /* bus+slot+function */ char pd_name[PCI_MAXNAMELEN + 1]; /* device name */ uint32_t pd_unit; /* Unit number (u_long) */ uint16_t pc_vendor; /* PCI Vendor ID */ uint16_t pc_device; /* PCI Device ID */ uint8_t pc_class; /* PCI class */ pci_getconf_flags_old flags; /* Matching expression */ }; #define PCIOCGETCONF_OLD32 _IOWR('p', 1, struct pci_conf_io32) #endif /* COMPAT_FREEBSD32 */ #define PCIOCGETCONF_OLD _IOWR('p', 1, struct pci_conf_io) #define PCIOCREAD_OLD _IOWR('p', 2, struct pci_io_old) #define PCIOCWRITE_OLD _IOWR('p', 3, struct pci_io_old) static int pci_conf_match_old(struct pci_match_conf_old *matches, int num_matches, struct pci_conf *match_buf) { int i; if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) return(1); for (i = 0; i < num_matches; i++) { if (match_buf->pc_sel.pc_domain != 0) continue; /* * I'm not sure why someone would do this...but... */ if (matches[i].flags == PCI_GETCONF_NO_MATCH_OLD) continue; /* * Look at each of the match flags. If it's set, do the * comparison. If the comparison fails, we don't have a * match, go on to the next item if there is one. */ if (((matches[i].flags & PCI_GETCONF_MATCH_BUS_OLD) != 0) && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_DEV_OLD) != 0) && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC_OLD) != 0) && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR_OLD) != 0) && (match_buf->pc_vendor != matches[i].pc_vendor)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE_OLD) != 0) && (match_buf->pc_device != matches[i].pc_device)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS_OLD) != 0) && (match_buf->pc_class != matches[i].pc_class)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT_OLD) != 0) && (match_buf->pd_unit != matches[i].pd_unit)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_NAME_OLD) != 0) && (strncmp(matches[i].pd_name, match_buf->pd_name, sizeof(match_buf->pd_name)) != 0)) continue; return(0); } return(1); } #ifdef COMPAT_FREEBSD32 static int pci_conf_match_old32(struct pci_match_conf_old32 *matches, int num_matches, struct pci_conf *match_buf) { int i; if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) return(1); for (i = 0; i < num_matches; i++) { if (match_buf->pc_sel.pc_domain != 0) continue; /* * I'm not sure why someone would do this...but... */ if (matches[i].flags == PCI_GETCONF_NO_MATCH_OLD) continue; /* * Look at each of the match flags. If it's set, do the * comparison. If the comparison fails, we don't have a * match, go on to the next item if there is one. */ if (((matches[i].flags & PCI_GETCONF_MATCH_BUS_OLD) != 0) && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_DEV_OLD) != 0) && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC_OLD) != 0) && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR_OLD) != 0) && (match_buf->pc_vendor != matches[i].pc_vendor)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE_OLD) != 0) && (match_buf->pc_device != matches[i].pc_device)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS_OLD) != 0) && (match_buf->pc_class != matches[i].pc_class)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT_OLD) != 0) && ((u_int32_t)match_buf->pd_unit != matches[i].pd_unit)) continue; if (((matches[i].flags & PCI_GETCONF_MATCH_NAME_OLD) != 0) && (strncmp(matches[i].pd_name, match_buf->pd_name, sizeof(match_buf->pd_name)) != 0)) continue; return (0); } return (1); } #endif /* COMPAT_FREEBSD32 */ #endif /* !PRE7_COMPAT */ union pci_conf_union { struct pci_conf pc; #ifdef COMPAT_FREEBSD32 struct pci_conf32 pc32; #endif #ifdef PRE7_COMPAT struct pci_conf_old pco; #ifdef COMPAT_FREEBSD32 struct pci_conf_old32 pco32; #endif #endif }; static int pci_conf_match(u_long cmd, struct pci_match_conf *matches, int num_matches, struct pci_conf *match_buf) { switch (cmd) { case PCIOCGETCONF: return (pci_conf_match_native( (struct pci_match_conf *)matches, num_matches, match_buf)); #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF32: return (pci_conf_match32((struct pci_match_conf32 *)matches, num_matches, match_buf)); #endif #ifdef PRE7_COMPAT case PCIOCGETCONF_OLD: return (pci_conf_match_old( (struct pci_match_conf_old *)matches, num_matches, match_buf)); #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF_OLD32: return (pci_conf_match_old32( (struct pci_match_conf_old32 *)matches, num_matches, match_buf)); #endif #endif default: /* programmer error */ return (0); } } /* * Like PVE_NEXT but takes an explicit length since 'pve' is a user * pointer that cannot be dereferenced. */ #define PVE_NEXT_LEN(pve, datalen) \ ((struct pci_vpd_element *)((char *)(pve) + \ sizeof(struct pci_vpd_element) + (datalen))) static int pci_list_vpd(device_t dev, struct pci_list_vpd_io *lvio) { struct pci_vpd_element vpd_element, *vpd_user; struct pcicfg_vpd *vpd; size_t len; int error, i; vpd = pci_fetch_vpd_list(dev); if (vpd->vpd_reg == 0 || vpd->vpd_ident == NULL) return (ENXIO); /* * Calculate the amount of space needed in the data buffer. An * identifier element is always present followed by the read-only * and read-write keywords. */ len = sizeof(struct pci_vpd_element) + strlen(vpd->vpd_ident); for (i = 0; i < vpd->vpd_rocnt; i++) len += sizeof(struct pci_vpd_element) + vpd->vpd_ros[i].len; for (i = 0; i < vpd->vpd_wcnt; i++) len += sizeof(struct pci_vpd_element) + vpd->vpd_w[i].len; if (lvio->plvi_len == 0) { lvio->plvi_len = len; return (0); } if (lvio->plvi_len < len) { lvio->plvi_len = len; return (ENOMEM); } /* * Copyout the identifier string followed by each keyword and * value. */ vpd_user = lvio->plvi_data; vpd_element.pve_keyword[0] = '\0'; vpd_element.pve_keyword[1] = '\0'; vpd_element.pve_flags = PVE_FLAG_IDENT; vpd_element.pve_datalen = strlen(vpd->vpd_ident); error = copyout(&vpd_element, vpd_user, sizeof(vpd_element)); if (error) return (error); error = copyout(vpd->vpd_ident, vpd_user->pve_data, strlen(vpd->vpd_ident)); if (error) return (error); vpd_user = PVE_NEXT_LEN(vpd_user, vpd_element.pve_datalen); vpd_element.pve_flags = 0; for (i = 0; i < vpd->vpd_rocnt; i++) { vpd_element.pve_keyword[0] = vpd->vpd_ros[i].keyword[0]; vpd_element.pve_keyword[1] = vpd->vpd_ros[i].keyword[1]; vpd_element.pve_datalen = vpd->vpd_ros[i].len; error = copyout(&vpd_element, vpd_user, sizeof(vpd_element)); if (error) return (error); error = copyout(vpd->vpd_ros[i].value, vpd_user->pve_data, vpd->vpd_ros[i].len); if (error) return (error); vpd_user = PVE_NEXT_LEN(vpd_user, vpd_element.pve_datalen); } vpd_element.pve_flags = PVE_FLAG_RW; for (i = 0; i < vpd->vpd_wcnt; i++) { vpd_element.pve_keyword[0] = vpd->vpd_w[i].keyword[0]; vpd_element.pve_keyword[1] = vpd->vpd_w[i].keyword[1]; vpd_element.pve_datalen = vpd->vpd_w[i].len; error = copyout(&vpd_element, vpd_user, sizeof(vpd_element)); if (error) return (error); error = copyout(vpd->vpd_w[i].value, vpd_user->pve_data, vpd->vpd_w[i].len); if (error) return (error); vpd_user = PVE_NEXT_LEN(vpd_user, vpd_element.pve_datalen); } KASSERT((char *)vpd_user - (char *)lvio->plvi_data == len, ("length mismatch")); lvio->plvi_len = len; return (0); } static size_t pci_match_conf_size(u_long cmd) { switch (cmd) { case PCIOCGETCONF: return (sizeof(struct pci_match_conf)); #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF32: return (sizeof(struct pci_match_conf32)); #endif #ifdef PRE7_COMPAT case PCIOCGETCONF_OLD: return (sizeof(struct pci_match_conf_old)); #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF_OLD32: return (sizeof(struct pci_match_conf_old32)); #endif #endif default: /* programmer error */ return (0); } } static size_t pci_conf_size(u_long cmd) { switch (cmd) { case PCIOCGETCONF: return (sizeof(struct pci_conf)); #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF32: return (sizeof(struct pci_conf32)); #endif #ifdef PRE7_COMPAT case PCIOCGETCONF_OLD: return (sizeof(struct pci_conf_old)); #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF_OLD32: return (sizeof(struct pci_conf_old32)); #endif #endif default: /* programmer error */ return (0); } } static void pci_conf_io_init(struct pci_conf_io *cio, caddr_t data, u_long cmd) { #if defined(COMPAT_FREEBSD32) struct pci_conf_io32 *cio32; #endif switch (cmd) { case PCIOCGETCONF: #ifdef PRE7_COMPAT case PCIOCGETCONF_OLD: #endif *cio = *(struct pci_conf_io *)data; return; #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF32: #ifdef PRE7_COMPAT case PCIOCGETCONF_OLD32: #endif cio32 = (struct pci_conf_io32 *)data; cio->pat_buf_len = cio32->pat_buf_len; cio->num_patterns = cio32->num_patterns; cio->patterns = (void *)(uintptr_t)cio32->patterns; cio->match_buf_len = cio32->match_buf_len; cio->num_matches = cio32->num_matches; cio->matches = (void *)(uintptr_t)cio32->matches; cio->offset = cio32->offset; cio->generation = cio32->generation; cio->status = cio32->status; return; #endif default: /* programmer error */ return; } } static void pci_conf_io_update_data(const struct pci_conf_io *cio, caddr_t data, u_long cmd) { struct pci_conf_io *d_cio; #if defined(COMPAT_FREEBSD32) struct pci_conf_io32 *cio32; #endif switch (cmd) { case PCIOCGETCONF: #ifdef PRE7_COMPAT case PCIOCGETCONF_OLD: #endif d_cio = (struct pci_conf_io *)data; d_cio->status = cio->status; d_cio->generation = cio->generation; d_cio->offset = cio->offset; d_cio->num_matches = cio->num_matches; return; #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF32: #ifdef PRE7_COMPAT case PCIOCGETCONF_OLD32: #endif cio32 = (struct pci_conf_io32 *)data; cio32->status = cio->status; cio32->generation = cio->generation; cio32->offset = cio->offset; cio32->num_matches = cio->num_matches; return; #endif default: /* programmer error */ return; } } static void pci_conf_for_copyout(const struct pci_conf *pcp, union pci_conf_union *pcup, u_long cmd) { memset(pcup, 0, sizeof(*pcup)); switch (cmd) { case PCIOCGETCONF: pcup->pc = *pcp; return; #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF32: pcup->pc32.pc_sel = pcp->pc_sel; pcup->pc32.pc_hdr = pcp->pc_hdr; pcup->pc32.pc_subvendor = pcp->pc_subvendor; pcup->pc32.pc_subdevice = pcp->pc_subdevice; pcup->pc32.pc_vendor = pcp->pc_vendor; pcup->pc32.pc_device = pcp->pc_device; pcup->pc32.pc_class = pcp->pc_class; pcup->pc32.pc_subclass = pcp->pc_subclass; pcup->pc32.pc_progif = pcp->pc_progif; pcup->pc32.pc_revid = pcp->pc_revid; strlcpy(pcup->pc32.pd_name, pcp->pd_name, sizeof(pcup->pc32.pd_name)); pcup->pc32.pd_unit = (uint32_t)pcp->pd_unit; return; #endif #ifdef PRE7_COMPAT #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF_OLD32: pcup->pco32.pc_sel.pc_bus = pcp->pc_sel.pc_bus; pcup->pco32.pc_sel.pc_dev = pcp->pc_sel.pc_dev; pcup->pco32.pc_sel.pc_func = pcp->pc_sel.pc_func; pcup->pco32.pc_hdr = pcp->pc_hdr; pcup->pco32.pc_subvendor = pcp->pc_subvendor; pcup->pco32.pc_subdevice = pcp->pc_subdevice; pcup->pco32.pc_vendor = pcp->pc_vendor; pcup->pco32.pc_device = pcp->pc_device; pcup->pco32.pc_class = pcp->pc_class; pcup->pco32.pc_subclass = pcp->pc_subclass; pcup->pco32.pc_progif = pcp->pc_progif; pcup->pco32.pc_revid = pcp->pc_revid; strlcpy(pcup->pco32.pd_name, pcp->pd_name, sizeof(pcup->pco32.pd_name)); pcup->pco32.pd_unit = (uint32_t)pcp->pd_unit; return; #endif /* COMPAT_FREEBSD32 */ case PCIOCGETCONF_OLD: pcup->pco.pc_sel.pc_bus = pcp->pc_sel.pc_bus; pcup->pco.pc_sel.pc_dev = pcp->pc_sel.pc_dev; pcup->pco.pc_sel.pc_func = pcp->pc_sel.pc_func; pcup->pco.pc_hdr = pcp->pc_hdr; pcup->pco.pc_subvendor = pcp->pc_subvendor; pcup->pco.pc_subdevice = pcp->pc_subdevice; pcup->pco.pc_vendor = pcp->pc_vendor; pcup->pco.pc_device = pcp->pc_device; pcup->pco.pc_class = pcp->pc_class; pcup->pco.pc_subclass = pcp->pc_subclass; pcup->pco.pc_progif = pcp->pc_progif; pcup->pco.pc_revid = pcp->pc_revid; strlcpy(pcup->pco.pd_name, pcp->pd_name, sizeof(pcup->pco.pd_name)); pcup->pco.pd_unit = pcp->pd_unit; return; #endif /* PRE7_COMPAT */ default: /* programmer error */ return; } } static int pci_bar_mmap(device_t pcidev, struct pci_bar_mmap *pbm) { vm_map_t map; vm_object_t obj; struct thread *td; struct sglist *sg; struct pci_map *pm; rman_res_t membase; vm_paddr_t pbase; vm_size_t plen; vm_offset_t addr; vm_prot_t prot; int error, flags; td = curthread; map = &td->td_proc->p_vmspace->vm_map; if ((pbm->pbm_flags & ~(PCIIO_BAR_MMAP_FIXED | PCIIO_BAR_MMAP_EXCL | PCIIO_BAR_MMAP_RW | PCIIO_BAR_MMAP_ACTIVATE)) != 0 || pbm->pbm_memattr != (vm_memattr_t)pbm->pbm_memattr || !pmap_is_valid_memattr(map->pmap, pbm->pbm_memattr)) return (EINVAL); /* Fetch the BAR physical base and length. */ pm = pci_find_bar(pcidev, pbm->pbm_reg); if (pm == NULL) return (EINVAL); if (!pci_bar_enabled(pcidev, pm)) return (EBUSY); /* XXXKIB enable if _ACTIVATE */ if (!PCI_BAR_MEM(pm->pm_value)) return (EIO); error = BUS_TRANSLATE_RESOURCE(pcidev, SYS_RES_MEMORY, pm->pm_value & PCIM_BAR_MEM_BASE, &membase); if (error != 0) return (error); pbase = trunc_page(membase); plen = round_page(membase + ((pci_addr_t)1 << pm->pm_size)) - pbase; prot = VM_PROT_READ | (((pbm->pbm_flags & PCIIO_BAR_MMAP_RW) != 0) ? VM_PROT_WRITE : 0); /* Create vm structures and mmap. */ sg = sglist_alloc(1, M_WAITOK); error = sglist_append_phys(sg, pbase, plen); if (error != 0) goto out; obj = vm_pager_allocate(OBJT_SG, sg, plen, prot, 0, td->td_ucred); if (obj == NULL) { error = EIO; goto out; } obj->memattr = pbm->pbm_memattr; flags = MAP_SHARED; addr = 0; if ((pbm->pbm_flags & PCIIO_BAR_MMAP_FIXED) != 0) { addr = (uintptr_t)pbm->pbm_map_base; flags |= MAP_FIXED; } if ((pbm->pbm_flags & PCIIO_BAR_MMAP_EXCL) != 0) flags |= MAP_CHECK_EXCL; error = vm_mmap_object(map, &addr, plen, prot, prot, flags, obj, 0, FALSE, td); if (error != 0) { vm_object_deallocate(obj); goto out; } pbm->pbm_map_base = (void *)addr; pbm->pbm_map_length = plen; pbm->pbm_bar_off = membase - pbase; pbm->pbm_bar_length = (pci_addr_t)1 << pm->pm_size; out: sglist_free(sg); return (error); } +static int +pci_bar_io(device_t pcidev, struct pci_bar_ioreq *pbi) +{ + struct pci_map *pm; + struct resource *res; + uint32_t offset, width; + int bar, error, type; + + if (pbi->pbi_op != PCIBARIO_READ && + pbi->pbi_op != PCIBARIO_WRITE) + return (EINVAL); + + bar = PCIR_BAR(pbi->pbi_bar); + pm = pci_find_bar(pcidev, bar); + if (pm == NULL) + return (EINVAL); + + offset = pbi->pbi_offset; + width = pbi->pbi_width; + + if (offset + width < offset || + ((pci_addr_t)1 << pm->pm_size) < offset + width) + return (EINVAL); + + type = PCI_BAR_MEM(pm->pm_value) ? SYS_RES_MEMORY : SYS_RES_IOPORT; + + /* + * This will fail if a driver has allocated the resource. This could be + * worked around by detecting that case and using bus_map_resource() to + * populate the handle, but so far this is not needed. + */ + res = bus_alloc_resource_any(pcidev, type, &bar, RF_ACTIVE); + if (res == NULL) + return (ENOENT); + + error = 0; + switch (pbi->pbi_op) { + case PCIBARIO_READ: + switch (pbi->pbi_width) { + case 1: + pbi->pbi_value = bus_read_1(res, offset); + break; + case 2: + pbi->pbi_value = bus_read_2(res, offset); + break; + case 4: + pbi->pbi_value = bus_read_4(res, offset); + break; +#ifndef __i386__ + case 8: + pbi->pbi_value = bus_read_8(res, offset); + break; +#endif + default: + error = EINVAL; + break; + } + break; + case PCIBARIO_WRITE: + switch (pbi->pbi_width) { + case 1: + bus_write_1(res, offset, pbi->pbi_value); + break; + case 2: + bus_write_2(res, offset, pbi->pbi_value); + break; + case 4: + bus_write_4(res, offset, pbi->pbi_value); + break; +#ifndef __i386__ + case 8: + bus_write_8(res, offset, pbi->pbi_value); + break; +#endif + default: + error = EINVAL; + break; + } + break; + } + + bus_release_resource(pcidev, type, bar, res); + + return (error); +} + static int pci_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag, struct thread *td) { device_t pcidev; const char *name; struct devlist *devlist_head; struct pci_conf_io *cio = NULL; struct pci_devinfo *dinfo; struct pci_io *io; + struct pci_bar_ioreq *pbi; struct pci_bar_io *bio; struct pci_list_vpd_io *lvio; struct pci_match_conf *pattern_buf; struct pci_map *pm; struct pci_bar_mmap *pbm; size_t confsz, iolen; int error, ionum, i, num_patterns; union pci_conf_union pcu; #ifdef PRE7_COMPAT struct pci_io iodata; struct pci_io_old *io_old; io_old = NULL; #endif /* * Interpret read-only opened /dev/pci as a promise that no * operation of the file descriptor could modify system state, * including side-effects due to reading devices registers. */ if ((flag & FWRITE) == 0) { switch (cmd) { case PCIOCGETCONF: #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF32: #endif #ifdef PRE7_COMPAT case PCIOCGETCONF_OLD: #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF_OLD32: #endif #endif case PCIOCGETBAR: case PCIOCLISTVPD: break; default: return (EPERM); } } /* Giant because newbus is Giant locked revisit with newbus locking */ mtx_lock(&Giant); switch (cmd) { case PCIOCGETCONF: #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF32: #endif #ifdef PRE7_COMPAT case PCIOCGETCONF_OLD: #ifdef COMPAT_FREEBSD32 case PCIOCGETCONF_OLD32: #endif #endif cio = malloc(sizeof(struct pci_conf_io), M_TEMP, M_WAITOK | M_ZERO); pci_conf_io_init(cio, data, cmd); pattern_buf = NULL; num_patterns = 0; dinfo = NULL; cio->num_matches = 0; /* * If the user specified an offset into the device list, * but the list has changed since they last called this * ioctl, tell them that the list has changed. They will * have to get the list from the beginning. */ if ((cio->offset != 0) && (cio->generation != pci_generation)){ cio->status = PCI_GETCONF_LIST_CHANGED; error = 0; goto getconfexit; } /* * Check to see whether the user has asked for an offset * past the end of our list. */ if (cio->offset >= pci_numdevs) { cio->status = PCI_GETCONF_LAST_DEVICE; error = 0; goto getconfexit; } /* get the head of the device queue */ devlist_head = &pci_devq; /* * Determine how much room we have for pci_conf structures. * Round the user's buffer size down to the nearest * multiple of sizeof(struct pci_conf) in case the user * didn't specify a multiple of that size. */ confsz = pci_conf_size(cmd); iolen = min(cio->match_buf_len - (cio->match_buf_len % confsz), pci_numdevs * confsz); /* * Since we know that iolen is a multiple of the size of * the pciconf union, it's okay to do this. */ ionum = iolen / confsz; /* * If this test is true, the user wants the pci_conf * structures returned to match the supplied entries. */ if ((cio->num_patterns > 0) && (cio->num_patterns < pci_numdevs) && (cio->pat_buf_len > 0)) { /* * pat_buf_len needs to be: * num_patterns * sizeof(struct pci_match_conf) * While it is certainly possible the user just * allocated a large buffer, but set the number of * matches correctly, it is far more likely that * their kernel doesn't match the userland utility * they're using. It's also possible that the user * forgot to initialize some variables. Yes, this * may be overly picky, but I hazard to guess that * it's far more likely to just catch folks that * updated their kernel but not their userland. */ if (cio->num_patterns * pci_match_conf_size(cmd) != cio->pat_buf_len) { /* The user made a mistake, return an error. */ cio->status = PCI_GETCONF_ERROR; error = EINVAL; goto getconfexit; } /* * Allocate a buffer to hold the patterns. */ pattern_buf = malloc(cio->pat_buf_len, M_TEMP, M_WAITOK); error = copyin(cio->patterns, pattern_buf, cio->pat_buf_len); if (error != 0) { error = EINVAL; goto getconfexit; } num_patterns = cio->num_patterns; } else if ((cio->num_patterns > 0) || (cio->pat_buf_len > 0)) { /* * The user made a mistake, spit out an error. */ cio->status = PCI_GETCONF_ERROR; error = EINVAL; goto getconfexit; } /* * Go through the list of devices and copy out the devices * that match the user's criteria. */ for (cio->num_matches = 0, i = 0, dinfo = STAILQ_FIRST(devlist_head); dinfo != NULL; dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { if (i < cio->offset) continue; /* Populate pd_name and pd_unit */ name = NULL; if (dinfo->cfg.dev) name = device_get_name(dinfo->cfg.dev); if (name) { strncpy(dinfo->conf.pd_name, name, sizeof(dinfo->conf.pd_name)); dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; dinfo->conf.pd_unit = device_get_unit(dinfo->cfg.dev); } else { dinfo->conf.pd_name[0] = '\0'; dinfo->conf.pd_unit = 0; } if (pattern_buf == NULL || pci_conf_match(cmd, pattern_buf, num_patterns, &dinfo->conf) == 0) { /* * If we've filled up the user's buffer, * break out at this point. Since we've * got a match here, we'll pick right back * up at the matching entry. We can also * tell the user that there are more matches * left. */ if (cio->num_matches >= ionum) { error = 0; break; } pci_conf_for_copyout(&dinfo->conf, &pcu, cmd); error = copyout(&pcu, (caddr_t)cio->matches + confsz * cio->num_matches, confsz); if (error) break; cio->num_matches++; } } /* * Set the pointer into the list, so if the user is getting * n records at a time, where n < pci_numdevs, */ cio->offset = i; /* * Set the generation, the user will need this if they make * another ioctl call with offset != 0. */ cio->generation = pci_generation; /* * If this is the last device, inform the user so he won't * bother asking for more devices. If dinfo isn't NULL, we * know that there are more matches in the list because of * the way the traversal is done. */ if (dinfo == NULL) cio->status = PCI_GETCONF_LAST_DEVICE; else cio->status = PCI_GETCONF_MORE_DEVS; getconfexit: pci_conf_io_update_data(cio, data, cmd); free(cio, M_TEMP); free(pattern_buf, M_TEMP); break; #ifdef PRE7_COMPAT case PCIOCREAD_OLD: case PCIOCWRITE_OLD: io_old = (struct pci_io_old *)data; iodata.pi_sel.pc_domain = 0; iodata.pi_sel.pc_bus = io_old->pi_sel.pc_bus; iodata.pi_sel.pc_dev = io_old->pi_sel.pc_dev; iodata.pi_sel.pc_func = io_old->pi_sel.pc_func; iodata.pi_reg = io_old->pi_reg; iodata.pi_width = io_old->pi_width; iodata.pi_data = io_old->pi_data; data = (caddr_t)&iodata; /* FALLTHROUGH */ #endif case PCIOCREAD: case PCIOCWRITE: io = (struct pci_io *)data; switch(io->pi_width) { case 4: case 2: case 1: /* Make sure register is not negative and aligned. */ if (io->pi_reg < 0 || io->pi_reg & (io->pi_width - 1)) { error = EINVAL; break; } /* * Assume that the user-level bus number is * in fact the physical PCI bus number. * Look up the grandparent, i.e. the bridge device, * so that we can issue configuration space cycles. */ pcidev = pci_find_dbsf(io->pi_sel.pc_domain, io->pi_sel.pc_bus, io->pi_sel.pc_dev, io->pi_sel.pc_func); if (pcidev) { #ifdef PRE7_COMPAT if (cmd == PCIOCWRITE || cmd == PCIOCWRITE_OLD) #else if (cmd == PCIOCWRITE) #endif pci_write_config(pcidev, io->pi_reg, io->pi_data, io->pi_width); #ifdef PRE7_COMPAT else if (cmd == PCIOCREAD_OLD) io_old->pi_data = pci_read_config(pcidev, io->pi_reg, io->pi_width); #endif else io->pi_data = pci_read_config(pcidev, io->pi_reg, io->pi_width); error = 0; } else { #ifdef COMPAT_FREEBSD4 if (cmd == PCIOCREAD_OLD) { io_old->pi_data = -1; error = 0; } else #endif error = ENODEV; } break; default: error = EINVAL; break; } break; case PCIOCGETBAR: bio = (struct pci_bar_io *)data; /* * Assume that the user-level bus number is * in fact the physical PCI bus number. */ pcidev = pci_find_dbsf(bio->pbi_sel.pc_domain, bio->pbi_sel.pc_bus, bio->pbi_sel.pc_dev, bio->pbi_sel.pc_func); if (pcidev == NULL) { error = ENODEV; break; } pm = pci_find_bar(pcidev, bio->pbi_reg); if (pm == NULL) { error = EINVAL; break; } bio->pbi_base = pm->pm_value; bio->pbi_length = (pci_addr_t)1 << pm->pm_size; bio->pbi_enabled = pci_bar_enabled(pcidev, pm); error = 0; break; case PCIOCATTACHED: error = 0; io = (struct pci_io *)data; pcidev = pci_find_dbsf(io->pi_sel.pc_domain, io->pi_sel.pc_bus, io->pi_sel.pc_dev, io->pi_sel.pc_func); if (pcidev != NULL) io->pi_data = device_is_attached(pcidev); else error = ENODEV; break; case PCIOCLISTVPD: lvio = (struct pci_list_vpd_io *)data; /* * Assume that the user-level bus number is * in fact the physical PCI bus number. */ pcidev = pci_find_dbsf(lvio->plvi_sel.pc_domain, lvio->plvi_sel.pc_bus, lvio->plvi_sel.pc_dev, lvio->plvi_sel.pc_func); if (pcidev == NULL) { error = ENODEV; break; } error = pci_list_vpd(pcidev, lvio); break; case PCIOCBARMMAP: pbm = (struct pci_bar_mmap *)data; if ((flag & FWRITE) == 0 && (pbm->pbm_flags & PCIIO_BAR_MMAP_RW) != 0) { error = EPERM; break; } pcidev = pci_find_dbsf(pbm->pbm_sel.pc_domain, pbm->pbm_sel.pc_bus, pbm->pbm_sel.pc_dev, pbm->pbm_sel.pc_func); error = pcidev == NULL ? ENODEV : pci_bar_mmap(pcidev, pbm); break; + case PCIOCBARIO: + pbi = (struct pci_bar_ioreq *)data; + + pcidev = pci_find_dbsf(pbi->pbi_sel.pc_domain, + pbi->pbi_sel.pc_bus, pbi->pbi_sel.pc_dev, + pbi->pbi_sel.pc_func); + if (pcidev == NULL) { + error = ENODEV; + break; + } + error = pci_bar_io(pcidev, pbi); + break; + default: error = ENOTTY; break; } mtx_unlock(&Giant); return (error); } diff --git a/sys/sys/pciio.h b/sys/sys/pciio.h index 50e9116d63d4..16635a884ca3 100644 --- a/sys/sys/pciio.h +++ b/sys/sys/pciio.h @@ -1,167 +1,179 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 1997, Stefan Esser * Copyright (c) 1997, 1998, 1999, Kenneth D. Merry * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef _SYS_PCIIO_H_ #define _SYS_PCIIO_H_ #include #define PCI_MAXNAMELEN 16 typedef enum { PCI_GETCONF_LAST_DEVICE, PCI_GETCONF_LIST_CHANGED, PCI_GETCONF_MORE_DEVS, PCI_GETCONF_ERROR } pci_getconf_status; typedef enum { PCI_GETCONF_NO_MATCH = 0x0000, PCI_GETCONF_MATCH_DOMAIN = 0x0001, PCI_GETCONF_MATCH_BUS = 0x0002, PCI_GETCONF_MATCH_DEV = 0x0004, PCI_GETCONF_MATCH_FUNC = 0x0008, PCI_GETCONF_MATCH_NAME = 0x0010, PCI_GETCONF_MATCH_UNIT = 0x0020, PCI_GETCONF_MATCH_VENDOR = 0x0040, PCI_GETCONF_MATCH_DEVICE = 0x0080, PCI_GETCONF_MATCH_CLASS = 0x0100 } pci_getconf_flags; struct pcisel { u_int32_t pc_domain; /* domain number */ u_int8_t pc_bus; /* bus number */ u_int8_t pc_dev; /* device on this bus */ u_int8_t pc_func; /* function on this device */ }; struct pci_conf { struct pcisel pc_sel; /* domain+bus+slot+function */ u_int8_t pc_hdr; /* PCI header type */ u_int16_t pc_subvendor; /* card vendor ID */ u_int16_t pc_subdevice; /* card device ID, assigned by card vendor */ u_int16_t pc_vendor; /* chip vendor ID */ u_int16_t pc_device; /* chip device ID, assigned by chip vendor */ u_int8_t pc_class; /* chip PCI class */ u_int8_t pc_subclass; /* chip PCI subclass */ u_int8_t pc_progif; /* chip PCI programming interface */ u_int8_t pc_revid; /* chip revision ID */ char pd_name[PCI_MAXNAMELEN + 1]; /* device name */ u_long pd_unit; /* device unit number */ }; struct pci_match_conf { struct pcisel pc_sel; /* domain+bus+slot+function */ char pd_name[PCI_MAXNAMELEN + 1]; /* device name */ u_long pd_unit; /* Unit number */ u_int16_t pc_vendor; /* PCI Vendor ID */ u_int16_t pc_device; /* PCI Device ID */ u_int8_t pc_class; /* PCI class */ pci_getconf_flags flags; /* Matching expression */ }; struct pci_conf_io { u_int32_t pat_buf_len; /* pattern buffer length */ u_int32_t num_patterns; /* number of patterns */ struct pci_match_conf *patterns; /* pattern buffer */ u_int32_t match_buf_len; /* match buffer length */ u_int32_t num_matches; /* number of matches returned */ struct pci_conf *matches; /* match buffer */ u_int32_t offset; /* offset into device list */ u_int32_t generation; /* device list generation */ pci_getconf_status status; /* request status */ }; struct pci_io { struct pcisel pi_sel; /* device to operate on */ int pi_reg; /* configuration register to examine */ int pi_width; /* width (in bytes) of read or write */ u_int32_t pi_data; /* data to write or result of read */ }; struct pci_bar_io { struct pcisel pbi_sel; /* device to operate on */ int pbi_reg; /* starting address of BAR */ int pbi_enabled; /* decoding enabled */ uint64_t pbi_base; /* current value of BAR */ uint64_t pbi_length; /* length of BAR */ }; struct pci_vpd_element { char pve_keyword[2]; uint8_t pve_flags; uint8_t pve_datalen; uint8_t pve_data[0]; }; #define PVE_FLAG_IDENT 0x01 /* Element is the string identifier */ #define PVE_FLAG_RW 0x02 /* Element is read/write */ #define PVE_NEXT(pve) \ ((struct pci_vpd_element *)((char *)(pve) + \ sizeof(struct pci_vpd_element) + (pve)->pve_datalen)) struct pci_list_vpd_io { struct pcisel plvi_sel; /* device to operate on */ size_t plvi_len; /* size of the data area */ struct pci_vpd_element *plvi_data; }; struct pci_bar_mmap { void *pbm_map_base; /* (sometimes IN)/OUT mmaped base */ size_t pbm_map_length; /* mapped length of the BAR, multiple of pages */ uint64_t pbm_bar_length; /* actual length of the BAR */ int pbm_bar_off; /* offset from the mapped base to the start of BAR */ struct pcisel pbm_sel; /* device to operate on */ int pbm_reg; /* starting address of BAR */ int pbm_flags; int pbm_memattr; }; +struct pci_bar_ioreq { + struct pcisel pbi_sel; /* device to operate on */ +#define PCIBARIO_READ 0x1 +#define PCIBARIO_WRITE 0x2 + int pbi_op; + uint32_t pbi_bar; + uint32_t pbi_offset; + uint32_t pbi_width; + uint32_t pbi_value; +}; + #define PCIIO_BAR_MMAP_FIXED 0x01 #define PCIIO_BAR_MMAP_EXCL 0x02 #define PCIIO_BAR_MMAP_RW 0x04 #define PCIIO_BAR_MMAP_ACTIVATE 0x08 #define PCIOCGETCONF _IOWR('p', 5, struct pci_conf_io) #define PCIOCREAD _IOWR('p', 2, struct pci_io) #define PCIOCWRITE _IOWR('p', 3, struct pci_io) #define PCIOCATTACHED _IOWR('p', 4, struct pci_io) #define PCIOCGETBAR _IOWR('p', 6, struct pci_bar_io) #define PCIOCLISTVPD _IOWR('p', 7, struct pci_list_vpd_io) #define PCIOCBARMMAP _IOWR('p', 8, struct pci_bar_mmap) +#define PCIOCBARIO _IOWR('p', 9, struct pci_bar_ioreq) #endif /* !_SYS_PCIIO_H_ */