diff --git a/sys/dev/em/if_em.c b/sys/dev/em/if_em.c index cf2a2ac9ae8b..bc049cfdeec9 100644 --- a/sys/dev/em/if_em.c +++ b/sys/dev/em/if_em.c @@ -1,3461 +1,3515 @@ /************************************************************************** Copyright (c) 2001-2005, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ***************************************************************************/ /*$FreeBSD$*/ #ifdef HAVE_KERNEL_OPTION_HEADERS #include "opt_device_polling.h" #endif #include /********************************************************************* * Set this to one to display debug statistics *********************************************************************/ int em_display_debug_stats = 0; /********************************************************************* * Driver version *********************************************************************/ -char em_driver_version[] = "2.1.7"; +char em_driver_version[] = "Version - 3.2.18"; /********************************************************************* * PCI Device ID Table * * Used by probe to select devices to load on * Last field stores an index into em_strings * Last entry must be all 0s * * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } *********************************************************************/ static em_vendor_info_t em_vendor_info_array[] = { /* Intel(R) PRO/1000 Network Connection */ { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, + + { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, /* required last entry */ { 0, 0, 0, 0, 0} }; /********************************************************************* * Table of branding strings for all supported NICs. *********************************************************************/ static char *em_strings[] = { "Intel(R) PRO/1000 Network Connection" }; /********************************************************************* * Function prototypes *********************************************************************/ static int em_probe(device_t); static int em_attach(device_t); static int em_detach(device_t); static int em_shutdown(device_t); static void em_intr(void *); static void em_start(struct ifnet *); static int em_ioctl(struct ifnet *, u_long, caddr_t); static void em_watchdog(struct ifnet *); static void em_init(void *); static void em_init_locked(struct adapter *); static void em_stop(void *); static void em_media_status(struct ifnet *, struct ifmediareq *); static int em_media_change(struct ifnet *); static void em_identify_hardware(struct adapter *); static int em_allocate_pci_resources(struct adapter *); static void em_free_pci_resources(struct adapter *); static void em_local_timer(void *); static int em_hardware_init(struct adapter *); static void em_setup_interface(device_t, struct adapter *); static int em_setup_transmit_structures(struct adapter *); static void em_initialize_transmit_unit(struct adapter *); static int em_setup_receive_structures(struct adapter *); static void em_initialize_receive_unit(struct adapter *); static void em_enable_intr(struct adapter *); static void em_disable_intr(struct adapter *); static void em_free_transmit_structures(struct adapter *); static void em_free_receive_structures(struct adapter *); static void em_update_stats_counters(struct adapter *); static void em_clean_transmit_interrupts(struct adapter *); static int em_allocate_receive_structures(struct adapter *); static int em_allocate_transmit_structures(struct adapter *); static void em_process_receive_interrupts(struct adapter *, int); static void em_receive_checksum(struct adapter *, struct em_rx_desc *, struct mbuf *); static void em_transmit_checksum_setup(struct adapter *, struct mbuf *, u_int32_t *, u_int32_t *); static void em_set_promisc(struct adapter *); static void em_disable_promisc(struct adapter *); static void em_set_multi(struct adapter *); static void em_print_hw_stats(struct adapter *); static void em_print_link_status(struct adapter *); static int em_get_buf(int i, struct adapter *, struct mbuf *); static void em_enable_vlans(struct adapter *); static void em_disable_vlans(struct adapter *); static int em_encap(struct adapter *, struct mbuf **); static void em_smartspeed(struct adapter *); static int em_82547_fifo_workaround(struct adapter *, int); static void em_82547_update_fifo_head(struct adapter *, int); static int em_82547_tx_fifo_reset(struct adapter *); static void em_82547_move_tail(void *arg); static void em_82547_move_tail_locked(struct adapter *); static int em_dma_malloc(struct adapter *, bus_size_t, struct em_dma_alloc *, int); static void em_dma_free(struct adapter *, struct em_dma_alloc *); static void em_print_debug_info(struct adapter *); static int em_is_valid_ether_addr(u_int8_t *); static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); static u_int32_t em_fill_descriptors (bus_addr_t address, u_int32_t length, PDESC_ARRAY desc_array); static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); static void em_add_int_delay_sysctl(struct adapter *, const char *, const char *, struct em_int_delay_info *, int, int); #ifdef DEVICE_POLLING static poll_handler_t em_poll; #endif /********************************************************************* * FreeBSD Device Interface Entry Points *********************************************************************/ static device_method_t em_methods[] = { /* Device interface */ DEVMETHOD(device_probe, em_probe), DEVMETHOD(device_attach, em_attach), DEVMETHOD(device_detach, em_detach), DEVMETHOD(device_shutdown, em_shutdown), {0, 0} }; static driver_t em_driver = { "em", em_methods, sizeof(struct adapter ), }; static devclass_t em_devclass; DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); MODULE_DEPEND(em, pci, 1, 1, 1); MODULE_DEPEND(em, ether, 1, 1, 1); /********************************************************************* * Tunable default values. *********************************************************************/ #define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) #define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); static int em_rxd = EM_DEFAULT_RXD; static int em_txd = EM_DEFAULT_TXD; TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); TUNABLE_INT("hw.em.rxd", &em_rxd); TUNABLE_INT("hw.em.txd", &em_txd); /********************************************************************* * Device identification routine * * em_probe determines if the driver should be loaded on * adapter based on PCI vendor/device id of the adapter. * * return BUS_PROBE_DEFAULT on success, positive on failure *********************************************************************/ static int em_probe(device_t dev) { em_vendor_info_t *ent; u_int16_t pci_vendor_id = 0; u_int16_t pci_device_id = 0; u_int16_t pci_subvendor_id = 0; u_int16_t pci_subdevice_id = 0; char adapter_name[60]; INIT_DEBUGOUT("em_probe: begin"); pci_vendor_id = pci_get_vendor(dev); if (pci_vendor_id != EM_VENDOR_ID) return(ENXIO); pci_device_id = pci_get_device(dev); pci_subvendor_id = pci_get_subvendor(dev); pci_subdevice_id = pci_get_subdevice(dev); ent = em_vendor_info_array; while (ent->vendor_id != 0) { if ((pci_vendor_id == ent->vendor_id) && (pci_device_id == ent->device_id) && ((pci_subvendor_id == ent->subvendor_id) || (ent->subvendor_id == PCI_ANY_ID)) && ((pci_subdevice_id == ent->subdevice_id) || (ent->subdevice_id == PCI_ANY_ID))) { - sprintf(adapter_name, "%s, Version - %s", + sprintf(adapter_name, "%s %s", em_strings[ent->index], em_driver_version); device_set_desc_copy(dev, adapter_name); return(BUS_PROBE_DEFAULT); } ent++; } return(ENXIO); } /********************************************************************* * Device initialization routine * * The attach entry point is called when the driver is being loaded. * This routine identifies the type of hardware, allocates all resources * and initializes the hardware. * * return 0 on success, positive on failure *********************************************************************/ static int em_attach(device_t dev) { struct adapter * adapter; int tsize, rsize; int error = 0; INIT_DEBUGOUT("em_attach: begin"); /* Allocate, clear, and link in our adapter structure */ if (!(adapter = device_get_softc(dev))) { printf("em: adapter structure allocation failed\n"); return(ENOMEM); } bzero(adapter, sizeof(struct adapter )); adapter->dev = dev; adapter->osdep.dev = dev; adapter->unit = device_get_unit(dev); EM_LOCK_INIT(adapter, device_get_nameunit(dev)); /* SYSCTL stuff */ SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, (void *)adapter, 0, em_sysctl_debug_info, "I", "Debug Information"); SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, (void *)adapter, 0, em_sysctl_stats, "I", "Statistics"); callout_init(&adapter->timer, CALLOUT_MPSAFE); callout_init(&adapter->tx_fifo_timer, CALLOUT_MPSAFE); /* Determine hardware revision */ em_identify_hardware(adapter); /* Set up some sysctls for the tunable interrupt delays */ em_add_int_delay_sysctl(adapter, "rx_int_delay", "receive interrupt delay in usecs", &adapter->rx_int_delay, E1000_REG_OFFSET(&adapter->hw, RDTR), em_rx_int_delay_dflt); em_add_int_delay_sysctl(adapter, "tx_int_delay", "transmit interrupt delay in usecs", &adapter->tx_int_delay, E1000_REG_OFFSET(&adapter->hw, TIDV), em_tx_int_delay_dflt); if (adapter->hw.mac_type >= em_82540) { em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", "receive interrupt delay limit in usecs", &adapter->rx_abs_int_delay, E1000_REG_OFFSET(&adapter->hw, RADV), em_rx_abs_int_delay_dflt); em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", "transmit interrupt delay limit in usecs", &adapter->tx_abs_int_delay, E1000_REG_OFFSET(&adapter->hw, TADV), em_tx_abs_int_delay_dflt); } /* * Validate number of transmit and receive descriptors. It * must not exceed hardware maximum, and must be multiple * of E1000_DBA_ALIGN. */ if (((em_txd * sizeof(struct em_tx_desc)) % E1000_DBA_ALIGN) != 0 || (adapter->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || (adapter->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || (em_txd < EM_MIN_TXD)) { printf("em%d: Using %d TX descriptors instead of %d!\n", adapter->unit, EM_DEFAULT_TXD, em_txd); adapter->num_tx_desc = EM_DEFAULT_TXD; } else adapter->num_tx_desc = em_txd; if (((em_rxd * sizeof(struct em_rx_desc)) % E1000_DBA_ALIGN) != 0 || (adapter->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || (adapter->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || (em_rxd < EM_MIN_RXD)) { printf("em%d: Using %d RX descriptors instead of %d!\n", adapter->unit, EM_DEFAULT_RXD, em_rxd); adapter->num_rx_desc = EM_DEFAULT_RXD; } else adapter->num_rx_desc = em_rxd; adapter->hw.autoneg = DO_AUTO_NEG; adapter->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; adapter->hw.tbi_compatibility_en = TRUE; adapter->rx_buffer_len = EM_RXBUFFER_2048; - /* - * These parameters control the automatic generation(Tx) and - * response(Rx) to Ethernet PAUSE frames. - */ - adapter->hw.fc_high_water = FC_DEFAULT_HI_THRESH; - adapter->hw.fc_low_water = FC_DEFAULT_LO_THRESH; - adapter->hw.fc_pause_time = FC_DEFAULT_TX_TIMER; - adapter->hw.fc_send_xon = TRUE; - adapter->hw.fc = em_fc_full; - adapter->hw.phy_init_script = 1; adapter->hw.phy_reset_disable = FALSE; #ifndef EM_MASTER_SLAVE adapter->hw.master_slave = em_ms_hw_default; #else adapter->hw.master_slave = EM_MASTER_SLAVE; #endif /* * Set the max frame size assuming standard ethernet * sized frames */ adapter->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; adapter->hw.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; /* * This controls when hardware reports transmit completion * status. */ adapter->hw.report_tx_early = 1; if (em_allocate_pci_resources(adapter)) { printf("em%d: Allocation of PCI resources failed\n", adapter->unit); error = ENXIO; goto err_pci; } /* Initialize eeprom parameters */ em_init_eeprom_params(&adapter->hw); tsize = roundup2(adapter->num_tx_desc * sizeof(struct em_tx_desc), E1000_DBA_ALIGN); /* Allocate Transmit Descriptor ring */ if (em_dma_malloc(adapter, tsize, &adapter->txdma, BUS_DMA_NOWAIT)) { printf("em%d: Unable to allocate tx_desc memory\n", adapter->unit); error = ENOMEM; goto err_tx_desc; } adapter->tx_desc_base = (struct em_tx_desc *) adapter->txdma.dma_vaddr; rsize = roundup2(adapter->num_rx_desc * sizeof(struct em_rx_desc), E1000_DBA_ALIGN); /* Allocate Receive Descriptor ring */ if (em_dma_malloc(adapter, rsize, &adapter->rxdma, BUS_DMA_NOWAIT)) { printf("em%d: Unable to allocate rx_desc memory\n", adapter->unit); error = ENOMEM; goto err_rx_desc; } adapter->rx_desc_base = (struct em_rx_desc *) adapter->rxdma.dma_vaddr; /* Initialize the hardware */ if (em_hardware_init(adapter)) { printf("em%d: Unable to initialize the hardware\n", adapter->unit); error = EIO; goto err_hw_init; } /* Copy the permanent MAC address out of the EEPROM */ if (em_read_mac_addr(&adapter->hw) < 0) { printf("em%d: EEPROM read error while reading mac address\n", adapter->unit); error = EIO; goto err_mac_addr; } if (!em_is_valid_ether_addr(adapter->hw.mac_addr)) { printf("em%d: Invalid mac address\n", adapter->unit); error = EIO; goto err_mac_addr; } /* Setup OS specific network interface */ em_setup_interface(dev, adapter); /* Initialize statistics */ em_clear_hw_cntrs(&adapter->hw); em_update_stats_counters(adapter); adapter->hw.get_link_status = 1; em_check_for_link(&adapter->hw); if (bootverbose) { /* Print the link status */ if (adapter->link_active == 1) { em_get_speed_and_duplex(&adapter->hw, &adapter->link_speed, &adapter->link_duplex); printf("em%d: Speed:%d Mbps Duplex:%s\n", adapter->unit, adapter->link_speed, adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half"); } else printf("em%d: Speed:N/A Duplex:N/A\n", adapter->unit); } /* Identify 82544 on PCIX */ em_get_bus_info(&adapter->hw); if(adapter->hw.bus_type == em_bus_type_pcix && adapter->hw.mac_type == em_82544) { adapter->pcix_82544 = TRUE; } else { adapter->pcix_82544 = FALSE; } INIT_DEBUGOUT("em_attach: end"); return(0); err_mac_addr: err_hw_init: em_dma_free(adapter, &adapter->rxdma); err_rx_desc: em_dma_free(adapter, &adapter->txdma); err_tx_desc: err_pci: em_free_pci_resources(adapter); EM_LOCK_DESTROY(adapter); return(error); } /********************************************************************* * Device removal routine * * The detach entry point is called when the driver is being removed. * This routine stops the adapter and deallocates all the resources * that were allocated for driver operation. * * return 0 on success, positive on failure *********************************************************************/ static int em_detach(device_t dev) { struct adapter * adapter = device_get_softc(dev); struct ifnet *ifp = adapter->ifp; INIT_DEBUGOUT("em_detach: begin"); #ifdef DEVICE_POLLING if (ifp->if_capenable & IFCAP_POLLING) ether_poll_deregister(ifp); #endif EM_LOCK(adapter); adapter->in_detach = 1; em_stop(adapter); em_phy_hw_reset(&adapter->hw); EM_UNLOCK(adapter); ether_ifdetach(adapter->ifp); em_free_pci_resources(adapter); bus_generic_detach(dev); if_free(ifp); /* Free Transmit Descriptor ring */ if (adapter->tx_desc_base) { em_dma_free(adapter, &adapter->txdma); adapter->tx_desc_base = NULL; } /* Free Receive Descriptor ring */ if (adapter->rx_desc_base) { em_dma_free(adapter, &adapter->rxdma); adapter->rx_desc_base = NULL; } EM_LOCK_DESTROY(adapter); return(0); } /********************************************************************* * * Shutdown entry point * **********************************************************************/ static int em_shutdown(device_t dev) { struct adapter *adapter = device_get_softc(dev); EM_LOCK(adapter); em_stop(adapter); EM_UNLOCK(adapter); return(0); } /********************************************************************* * Transmit entry point * * em_start is called by the stack to initiate a transmit. * The driver will remain in this routine as long as there are * packets to transmit and transmit resources are available. * In case resources are not available stack is notified and * the packet is requeued. **********************************************************************/ static void em_start_locked(struct ifnet *ifp) { struct mbuf *m_head; struct adapter *adapter = ifp->if_softc; mtx_assert(&adapter->mtx, MA_OWNED); if (!adapter->link_active) return; while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); if (m_head == NULL) break; /* * em_encap() can modify our pointer, and or make it NULL on * failure. In that event, we can't requeue. */ if (em_encap(adapter, &m_head)) { if (m_head == NULL) break; ifp->if_drv_flags |= IFF_DRV_OACTIVE; IFQ_DRV_PREPEND(&ifp->if_snd, m_head); break; } /* Send a copy of the frame to the BPF listener */ BPF_MTAP(ifp, m_head); /* Set timeout in case hardware has problems transmitting */ ifp->if_timer = EM_TX_TIMEOUT; } return; } static void em_start(struct ifnet *ifp) { struct adapter *adapter = ifp->if_softc; EM_LOCK(adapter); if (ifp->if_drv_flags & IFF_DRV_RUNNING) em_start_locked(ifp); EM_UNLOCK(adapter); return; } /********************************************************************* * Ioctl entry point * * em_ioctl is called when the user wants to configure the * interface. * * return 0 on success, positive on failure **********************************************************************/ static int em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) { - int mask, reinit, error = 0; struct ifreq *ifr = (struct ifreq *) data; struct adapter * adapter = ifp->if_softc; + int error = 0; if (adapter->in_detach) return(error); switch (command) { case SIOCSIFADDR: case SIOCGIFADDR: IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)"); ether_ioctl(ifp, command, data); break; case SIOCSIFMTU: - IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); + { #ifndef __NO_STRICT_ALIGNMENT - if (ifr->ifr_mtu > ETHERMTU) { + if (ifr->ifr_mtu > ETHERMTU) /* * XXX * Due to the limitation of DMA engine, it needs fix-up * code for strict alignment architectures. Disable * jumbo frame until we have better solutions. */ error = EINVAL; - } else -#endif - if (ifr->ifr_mtu > MAX_JUMBO_FRAME_SIZE - ETHER_HDR_LEN || \ - /* 82573 does not support jumbo frames */ - (adapter->hw.mac_type == em_82573 && ifr->ifr_mtu > ETHERMTU) ) { +#else + int max_frame_size; + + IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); + + switch (adapter->hw.mac_type) { + case em_82571: + case em_82572: + max_frame_size = 10500; + break; + case em_82573: + /* 82573 does not support jumbo frames. */ + max_frame_size = ETHER_MAX_LEN; + break; + default: + max_frame_size = MAX_JUMBO_FRAME_SIZE; + } + if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - + ETHER_CRC_LEN) { error = EINVAL; - } else { - EM_LOCK(adapter); - ifp->if_mtu = ifr->ifr_mtu; - adapter->hw.max_frame_size = - ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; - em_init_locked(adapter); - EM_UNLOCK(adapter); + break; } + + EM_LOCK(adapter); + ifp->if_mtu = ifr->ifr_mtu; + adapter->hw.max_frame_size = + ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; + em_init_locked(adapter); + EM_UNLOCK(adapter); +#endif break; + } case SIOCSIFFLAGS: IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); EM_LOCK(adapter); if (ifp->if_flags & IFF_UP) { if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { em_init_locked(adapter); } em_disable_promisc(adapter); em_set_promisc(adapter); } else { if (ifp->if_drv_flags & IFF_DRV_RUNNING) { em_stop(adapter); } } EM_UNLOCK(adapter); break; case SIOCADDMULTI: case SIOCDELMULTI: IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); if (ifp->if_drv_flags & IFF_DRV_RUNNING) { EM_LOCK(adapter); em_disable_intr(adapter); em_set_multi(adapter); if (adapter->hw.mac_type == em_82542_rev2_0) { em_initialize_receive_unit(adapter); } #ifdef DEVICE_POLLING if (!(ifp->if_capenable & IFCAP_POLLING)) #endif em_enable_intr(adapter); EM_UNLOCK(adapter); } break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); break; case SIOCSIFCAP: + { + int mask, reinit; + IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); reinit = 0; mask = ifr->ifr_reqcap ^ ifp->if_capenable; #ifdef DEVICE_POLLING if (mask & IFCAP_POLLING) { if (ifr->ifr_reqcap & IFCAP_POLLING) { error = ether_poll_register(em_poll, ifp); if (error) return(error); EM_LOCK(adapter); em_disable_intr(adapter); ifp->if_capenable |= IFCAP_POLLING; EM_UNLOCK(adapter); } else { error = ether_poll_deregister(ifp); /* Enable interrupt even in error case */ EM_LOCK(adapter); em_enable_intr(adapter); ifp->if_capenable &= ~IFCAP_POLLING; EM_UNLOCK(adapter); } } #endif if (mask & IFCAP_HWCSUM) { ifp->if_capenable ^= IFCAP_HWCSUM; reinit = 1; } if (mask & IFCAP_VLAN_HWTAGGING) { ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; reinit = 1; } if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) em_init(adapter); break; + } default: IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)", (int)command); error = EINVAL; } return(error); } /********************************************************************* * Watchdog entry point * * This routine is called whenever hardware quits transmitting. * **********************************************************************/ static void em_watchdog(struct ifnet *ifp) { struct adapter * adapter; adapter = ifp->if_softc; EM_LOCK(adapter); /* If we are in this routine because of pause frames, then * don't reset the hardware. */ if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF) { ifp->if_timer = EM_TX_TIMEOUT; EM_UNLOCK(adapter); return; } if (em_check_for_link(&adapter->hw)) printf("em%d: watchdog timeout -- resetting\n", adapter->unit); ifp->if_drv_flags &= ~IFF_DRV_RUNNING; adapter->watchdog_events++; em_init_locked(adapter); EM_UNLOCK(adapter); } /********************************************************************* * Init entry point * * This routine is used in two ways. It is used by the stack as * init entry point in network interface structure. It is also used * by the driver as a hw/sw initialization routine to get to a * consistent state. * * return 0 on success, positive on failure **********************************************************************/ static void em_init_locked(struct adapter * adapter) { struct ifnet *ifp; uint32_t pba; ifp = adapter->ifp; INIT_DEBUGOUT("em_init: begin"); mtx_assert(&adapter->mtx, MA_OWNED); em_stop(adapter); - /* Packet Buffer Allocation (PBA) + /* + * Packet Buffer Allocation (PBA) * Writing PBA sets the receive portion of the buffer * the remainder is used for the transmit buffer. - * - * Devices before the 82547 had a Packet Buffer of 64K. - * Default allocation: PBA=48K for Rx, leaving 16K for Tx. - * After the 82547 the buffer was reduced to 40K. - * Default allocation: PBA=30K for Rx, leaving 10K for Tx. - * Note: default does not leave enough room for Jumbo Frame >10k. */ - if(adapter->hw.mac_type < em_82547) { - /* Total FIFO is 64K */ - if(adapter->rx_buffer_len > EM_RXBUFFER_8192) - pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ - else - pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ - } else { - /* Total FIFO is 40K */ - if(adapter->hw.max_frame_size > EM_RXBUFFER_8192) { + switch (adapter->hw.mac_type) { + case em_82547: + case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ + if (adapter->hw.max_frame_size > EM_RXBUFFER_8192) pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ - } else { - pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ - } + else + pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ adapter->tx_fifo_head = 0; adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; adapter->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; + break; + case em_82571: /* 82571: Total Packet Buffer is 48K */ + case em_82572: /* 82572: Total Packet Buffer is 48K */ + pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ + break; + case em_82573: /* 82573: Total Packet Buffer is 32K */ + /* Jumbo frames not supported */ + pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ + break; + default: + /* Devices before 82547 had a Packet Buffer of 64K. */ + if(adapter->hw.max_frame_size > EM_RXBUFFER_8192) + pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ + else + pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ } + INIT_DEBUGOUT1("em_init: pba=%dK",pba); E1000_WRITE_REG(&adapter->hw, PBA, pba); /* Get the latest mac address, User can use a LAA */ bcopy(IF_LLADDR(adapter->ifp), adapter->hw.mac_addr, ETHER_ADDR_LEN); /* Initialize the hardware */ if (em_hardware_init(adapter)) { printf("em%d: Unable to initialize the hardware\n", adapter->unit); return; } if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) em_enable_vlans(adapter); /* Prepare transmit descriptors and buffers */ if (em_setup_transmit_structures(adapter)) { printf("em%d: Could not setup transmit structures\n", adapter->unit); em_stop(adapter); return; } em_initialize_transmit_unit(adapter); /* Setup Multicast table */ em_set_multi(adapter); /* Prepare receive descriptors and buffers */ if (em_setup_receive_structures(adapter)) { printf("em%d: Could not setup receive structures\n", adapter->unit); em_stop(adapter); return; } em_initialize_receive_unit(adapter); /* Don't loose promiscuous settings */ em_set_promisc(adapter); ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if (adapter->hw.mac_type >= em_82543) { if (ifp->if_capenable & IFCAP_TXCSUM) ifp->if_hwassist = EM_CHECKSUM_FEATURES; else ifp->if_hwassist = 0; } callout_reset(&adapter->timer, hz, em_local_timer, adapter); em_clear_hw_cntrs(&adapter->hw); #ifdef DEVICE_POLLING /* * Only enable interrupts if we are not polling, make sure * they are off otherwise. */ if (ifp->if_capenable & IFCAP_POLLING) em_disable_intr(adapter); else #endif /* DEVICE_POLLING */ em_enable_intr(adapter); /* Don't reset the phy next time init gets called */ adapter->hw.phy_reset_disable = TRUE; return; } static void em_init(void *arg) { struct adapter * adapter = arg; EM_LOCK(adapter); em_init_locked(adapter); EM_UNLOCK(adapter); return; } #ifdef DEVICE_POLLING static void em_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct adapter *adapter = ifp->if_softc; u_int32_t reg_icr; mtx_assert(&adapter->mtx, MA_OWNED); if (cmd == POLL_AND_CHECK_STATUS) { reg_icr = E1000_READ_REG(&adapter->hw, ICR); if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { callout_stop(&adapter->timer); adapter->hw.get_link_status = 1; em_check_for_link(&adapter->hw); em_print_link_status(adapter); callout_reset(&adapter->timer, hz, em_local_timer, adapter); } } em_process_receive_interrupts(adapter, count); em_clean_transmit_interrupts(adapter); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) em_start_locked(ifp); } static void em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct adapter *adapter = ifp->if_softc; EM_LOCK(adapter); if (ifp->if_drv_flags & IFF_DRV_RUNNING) em_poll_locked(ifp, cmd, count); EM_UNLOCK(adapter); } #endif /* DEVICE_POLLING */ /********************************************************************* * * Interrupt Service routine * **********************************************************************/ static void em_intr(void *arg) { struct adapter *adapter = arg; struct ifnet *ifp; uint32_t reg_icr; int wantinit = 0; EM_LOCK(adapter); ifp = adapter->ifp; #ifdef DEVICE_POLLING if (ifp->if_capenable & IFCAP_POLLING) { EM_UNLOCK(adapter); return; } #endif /* DEVICE_POLLING */ for (;;) { reg_icr = E1000_READ_REG(&adapter->hw, ICR); if (reg_icr == 0) break; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { em_process_receive_interrupts(adapter, -1); em_clean_transmit_interrupts(adapter); } /* Link status change */ if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { callout_stop(&adapter->timer); adapter->hw.get_link_status = 1; em_check_for_link(&adapter->hw); em_print_link_status(adapter); callout_reset(&adapter->timer, hz, em_local_timer, adapter); } if (reg_icr & E1000_ICR_RXO) { adapter->rx_overruns++; wantinit = 1; } } #if 0 if (wantinit) em_init_locked(adapter); #endif if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) em_start_locked(ifp); EM_UNLOCK(adapter); return; } /********************************************************************* * * Media Ioctl callback * * This routine is called whenever the user queries the status of * the interface using ifconfig. * **********************************************************************/ static void em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) { struct adapter * adapter = ifp->if_softc; INIT_DEBUGOUT("em_media_status: begin"); em_check_for_link(&adapter->hw); if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) { if (adapter->link_active == 0) { em_get_speed_and_duplex(&adapter->hw, &adapter->link_speed, &adapter->link_duplex); adapter->link_active = 1; } } else { if (adapter->link_active == 1) { adapter->link_speed = 0; adapter->link_duplex = 0; adapter->link_active = 0; } } ifmr->ifm_status = IFM_AVALID; ifmr->ifm_active = IFM_ETHER; if (!adapter->link_active) return; ifmr->ifm_status |= IFM_ACTIVE; if (adapter->hw.media_type == em_media_type_fiber) { ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; } else { switch (adapter->link_speed) { case 10: ifmr->ifm_active |= IFM_10_T; break; case 100: ifmr->ifm_active |= IFM_100_TX; break; case 1000: ifmr->ifm_active |= IFM_1000_T; break; } if (adapter->link_duplex == FULL_DUPLEX) ifmr->ifm_active |= IFM_FDX; else ifmr->ifm_active |= IFM_HDX; } return; } /********************************************************************* * * Media Ioctl callback * * This routine is called when the user changes speed/duplex using * media/mediopt option with ifconfig. * **********************************************************************/ static int em_media_change(struct ifnet *ifp) { struct adapter * adapter = ifp->if_softc; struct ifmedia *ifm = &adapter->media; INIT_DEBUGOUT("em_media_change: begin"); if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) return(EINVAL); switch (IFM_SUBTYPE(ifm->ifm_media)) { case IFM_AUTO: adapter->hw.autoneg = DO_AUTO_NEG; adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; break; case IFM_1000_SX: case IFM_1000_T: adapter->hw.autoneg = DO_AUTO_NEG; adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL; break; case IFM_100_TX: adapter->hw.autoneg = FALSE; adapter->hw.autoneg_advertised = 0; if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) adapter->hw.forced_speed_duplex = em_100_full; else adapter->hw.forced_speed_duplex = em_100_half; break; case IFM_10_T: adapter->hw.autoneg = FALSE; adapter->hw.autoneg_advertised = 0; if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) adapter->hw.forced_speed_duplex = em_10_full; else adapter->hw.forced_speed_duplex = em_10_half; break; default: printf("em%d: Unsupported media type\n", adapter->unit); } /* As the speed/duplex settings my have changed we need to * reset the PHY. */ adapter->hw.phy_reset_disable = FALSE; em_init(adapter); return(0); } /********************************************************************* * * This routine maps the mbufs to tx descriptors. * * return 0 on success, positive on failure **********************************************************************/ static int em_encap(struct adapter *adapter, struct mbuf **m_headp) { u_int32_t txd_upper; u_int32_t txd_lower, txd_used = 0, txd_saved = 0; int i, j, error = 0; struct mbuf *m_head; /* For 82544 Workaround */ DESC_ARRAY desc_array; u_int32_t array_elements; u_int32_t counter; struct m_tag *mtag; bus_dma_segment_t segs[EM_MAX_SCATTER]; int nsegs; struct em_buffer *tx_buffer; struct em_tx_desc *current_tx_desc = NULL; struct ifnet *ifp = adapter->ifp; m_head = *m_headp; /* * Force a cleanup if number of TX descriptors * available hits the threshold */ if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { em_clean_transmit_interrupts(adapter); if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { adapter->no_tx_desc_avail1++; return(ENOBUFS); } } /* * Map the packet for DMA. */ tx_buffer = &adapter->tx_buffer_area[adapter->next_avail_tx_desc]; error = bus_dmamap_load_mbuf_sg(adapter->txtag, tx_buffer->map, m_head, segs, &nsegs, BUS_DMA_NOWAIT); if (error != 0) { adapter->no_tx_dma_setup++; return (error); } KASSERT(nsegs != 0, ("em_encap: empty packet")); if (nsegs > adapter->num_tx_desc_avail) { adapter->no_tx_desc_avail2++; error = ENOBUFS; goto encap_fail; } if (ifp->if_hwassist > 0) { em_transmit_checksum_setup(adapter, m_head, &txd_upper, &txd_lower); } else txd_upper = txd_lower = 0; /* Find out if we are in vlan mode */ mtag = VLAN_OUTPUT_TAG(ifp, m_head); /* * When operating in promiscuous mode, hardware encapsulation for * packets is disabled. This means we have to add the vlan * encapsulation in the driver, since it will have come down from the * VLAN layer with a tag instead of a VLAN header. */ if (mtag != NULL && adapter->em_insert_vlan_header) { struct ether_vlan_header *evl; struct ether_header eh; m_head = m_pullup(m_head, sizeof(eh)); if (m_head == NULL) { *m_headp = NULL; error = ENOBUFS; goto encap_fail; } eh = *mtod(m_head, struct ether_header *); M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT); if (m_head == NULL) { *m_headp = NULL; error = ENOBUFS; goto encap_fail; } m_head = m_pullup(m_head, sizeof(*evl)); if (m_head == NULL) { *m_headp = NULL; error = ENOBUFS; goto encap_fail; } evl = mtod(m_head, struct ether_vlan_header *); bcopy(&eh, evl, sizeof(*evl)); evl->evl_proto = evl->evl_encap_proto; evl->evl_encap_proto = htons(ETHERTYPE_VLAN); evl->evl_tag = htons(VLAN_TAG_VALUE(mtag)); m_tag_delete(m_head, mtag); mtag = NULL; *m_headp = m_head; } i = adapter->next_avail_tx_desc; if (adapter->pcix_82544) { txd_saved = i; txd_used = 0; } for (j = 0; j < nsegs; j++) { /* If adapter is 82544 and on PCIX bus */ if(adapter->pcix_82544) { /* * Check the Address and Length combination and * split the data accordingly */ array_elements = em_fill_descriptors(segs[j].ds_addr, segs[j].ds_len, &desc_array); for (counter = 0; counter < array_elements; counter++) { if (txd_used == adapter->num_tx_desc_avail) { adapter->next_avail_tx_desc = txd_saved; adapter->no_tx_desc_avail2++; error = ENOBUFS; goto encap_fail; } tx_buffer = &adapter->tx_buffer_area[i]; current_tx_desc = &adapter->tx_desc_base[i]; current_tx_desc->buffer_addr = htole64( desc_array.descriptor[counter].address); current_tx_desc->lower.data = htole32( (adapter->txd_cmd | txd_lower | (u_int16_t)desc_array.descriptor[counter].length)); current_tx_desc->upper.data = htole32((txd_upper)); if (++i == adapter->num_tx_desc) i = 0; tx_buffer->m_head = NULL; txd_used++; } } else { tx_buffer = &adapter->tx_buffer_area[i]; current_tx_desc = &adapter->tx_desc_base[i]; current_tx_desc->buffer_addr = htole64(segs[j].ds_addr); current_tx_desc->lower.data = htole32( adapter->txd_cmd | txd_lower | segs[j].ds_len); current_tx_desc->upper.data = htole32(txd_upper); if (++i == adapter->num_tx_desc) i = 0; tx_buffer->m_head = NULL; } } adapter->next_avail_tx_desc = i; if (adapter->pcix_82544) { adapter->num_tx_desc_avail -= txd_used; } else { adapter->num_tx_desc_avail -= nsegs; } if (mtag != NULL) { /* Set the vlan id */ current_tx_desc->upper.fields.special = htole16(VLAN_TAG_VALUE(mtag)); /* Tell hardware to add tag */ current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); } tx_buffer->m_head = m_head; bus_dmamap_sync(adapter->txtag, tx_buffer->map, BUS_DMASYNC_PREWRITE); /* * Last Descriptor of Packet needs End Of Packet (EOP) */ current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP); /* * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 * that this frame is available to transmit. */ bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); if (adapter->hw.mac_type == em_82547 && adapter->link_duplex == HALF_DUPLEX) { em_82547_move_tail_locked(adapter); } else { E1000_WRITE_REG(&adapter->hw, TDT, i); if (adapter->hw.mac_type == em_82547) { em_82547_update_fifo_head(adapter, m_head->m_pkthdr.len); } } return(0); encap_fail: bus_dmamap_unload(adapter->txtag, tx_buffer->map); return (error); } /********************************************************************* * * 82547 workaround to avoid controller hang in half-duplex environment. * The workaround is to avoid queuing a large packet that would span * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers * in this case. We do that only when FIFO is quiescent. * **********************************************************************/ static void em_82547_move_tail_locked(struct adapter *adapter) { uint16_t hw_tdt; uint16_t sw_tdt; struct em_tx_desc *tx_desc; uint16_t length = 0; boolean_t eop = 0; EM_LOCK_ASSERT(adapter); hw_tdt = E1000_READ_REG(&adapter->hw, TDT); sw_tdt = adapter->next_avail_tx_desc; while (hw_tdt != sw_tdt) { tx_desc = &adapter->tx_desc_base[hw_tdt]; length += tx_desc->lower.flags.length; eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; if(++hw_tdt == adapter->num_tx_desc) hw_tdt = 0; if(eop) { if (em_82547_fifo_workaround(adapter, length)) { adapter->tx_fifo_wrk_cnt++; callout_reset(&adapter->tx_fifo_timer, 1, em_82547_move_tail, adapter); break; } E1000_WRITE_REG(&adapter->hw, TDT, hw_tdt); em_82547_update_fifo_head(adapter, length); length = 0; } } return; } static void em_82547_move_tail(void *arg) { struct adapter *adapter = arg; EM_LOCK(adapter); em_82547_move_tail_locked(adapter); EM_UNLOCK(adapter); } static int em_82547_fifo_workaround(struct adapter *adapter, int len) { int fifo_space, fifo_pkt_len; fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); if (adapter->link_duplex == HALF_DUPLEX) { fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { if (em_82547_tx_fifo_reset(adapter)) { return(0); } else { return(1); } } } return(0); } static void em_82547_update_fifo_head(struct adapter *adapter, int len) { int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); /* tx_fifo_head is always 16 byte aligned */ adapter->tx_fifo_head += fifo_pkt_len; if (adapter->tx_fifo_head >= adapter->tx_fifo_size) { adapter->tx_fifo_head -= adapter->tx_fifo_size; } return; } static int em_82547_tx_fifo_reset(struct adapter *adapter) { uint32_t tctl; if ( (E1000_READ_REG(&adapter->hw, TDT) == E1000_READ_REG(&adapter->hw, TDH)) && (E1000_READ_REG(&adapter->hw, TDFT) == E1000_READ_REG(&adapter->hw, TDFH)) && (E1000_READ_REG(&adapter->hw, TDFTS) == E1000_READ_REG(&adapter->hw, TDFHS)) && (E1000_READ_REG(&adapter->hw, TDFPC) == 0)) { /* Disable TX unit */ tctl = E1000_READ_REG(&adapter->hw, TCTL); E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN); /* Reset FIFO pointers */ E1000_WRITE_REG(&adapter->hw, TDFT, adapter->tx_head_addr); E1000_WRITE_REG(&adapter->hw, TDFH, adapter->tx_head_addr); E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr); E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr); /* Re-enable TX unit */ E1000_WRITE_REG(&adapter->hw, TCTL, tctl); E1000_WRITE_FLUSH(&adapter->hw); adapter->tx_fifo_head = 0; adapter->tx_fifo_reset_cnt++; return(TRUE); } else { return(FALSE); } } static void em_set_promisc(struct adapter * adapter) { u_int32_t reg_rctl; struct ifnet *ifp = adapter->ifp; reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); if (ifp->if_flags & IFF_PROMISC) { reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); /* Disable VLAN stripping in promiscous mode * This enables bridging of vlan tagged frames to occur * and also allows vlan tags to be seen in tcpdump */ if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) em_disable_vlans(adapter); adapter->em_insert_vlan_header = 1; } else if (ifp->if_flags & IFF_ALLMULTI) { reg_rctl |= E1000_RCTL_MPE; reg_rctl &= ~E1000_RCTL_UPE; E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); adapter->em_insert_vlan_header = 0; } else adapter->em_insert_vlan_header = 0; return; } static void em_disable_promisc(struct adapter * adapter) { u_int32_t reg_rctl; struct ifnet *ifp = adapter->ifp; reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); reg_rctl &= (~E1000_RCTL_UPE); reg_rctl &= (~E1000_RCTL_MPE); E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) em_enable_vlans(adapter); adapter->em_insert_vlan_header = 0; return; } /********************************************************************* * Multicast Update * * This routine is called whenever multicast address list is updated. * **********************************************************************/ static void em_set_multi(struct adapter * adapter) { u_int32_t reg_rctl = 0; u_int8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; struct ifmultiaddr *ifma; int mcnt = 0; struct ifnet *ifp = adapter->ifp; IOCTL_DEBUGOUT("em_set_multi: begin"); if (adapter->hw.mac_type == em_82542_rev2_0) { reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) { em_pci_clear_mwi(&adapter->hw); } reg_rctl |= E1000_RCTL_RST; E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); msec_delay(5); } IF_ADDR_LOCK(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) break; bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); mcnt++; } IF_ADDR_UNLOCK(ifp); if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); reg_rctl |= E1000_RCTL_MPE; E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); } else em_mc_addr_list_update(&adapter->hw, mta, mcnt, 0, 1); if (adapter->hw.mac_type == em_82542_rev2_0) { reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); reg_rctl &= ~E1000_RCTL_RST; E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); msec_delay(5); if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) { em_pci_set_mwi(&adapter->hw); } } return; } /********************************************************************* * Timer routine * * This routine checks for link status and updates statistics. * **********************************************************************/ static void em_local_timer(void *arg) { struct ifnet *ifp; struct adapter * adapter = arg; ifp = adapter->ifp; EM_LOCK(adapter); em_check_for_link(&adapter->hw); em_print_link_status(adapter); em_update_stats_counters(adapter); if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) { em_print_hw_stats(adapter); } em_smartspeed(adapter); callout_reset(&adapter->timer, hz, em_local_timer, adapter); EM_UNLOCK(adapter); return; } static void em_print_link_status(struct adapter * adapter) { struct ifnet *ifp = adapter->ifp; if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) { if (adapter->link_active == 0) { em_get_speed_and_duplex(&adapter->hw, &adapter->link_speed, &adapter->link_duplex); if (bootverbose) printf("em%d: Link is up %d Mbps %s\n", adapter->unit, adapter->link_speed, ((adapter->link_duplex == FULL_DUPLEX) ? "Full Duplex" : "Half Duplex")); adapter->link_active = 1; adapter->smartspeed = 0; if_link_state_change(ifp, LINK_STATE_UP); } } else { if (adapter->link_active == 1) { adapter->link_speed = 0; adapter->link_duplex = 0; if (bootverbose) printf("em%d: Link is Down\n", adapter->unit); adapter->link_active = 0; if_link_state_change(ifp, LINK_STATE_DOWN); } } return; } /********************************************************************* * * This routine disables all traffic on the adapter by issuing a * global reset on the MAC and deallocates TX/RX buffers. * **********************************************************************/ static void em_stop(void *arg) { struct ifnet *ifp; struct adapter * adapter = arg; ifp = adapter->ifp; mtx_assert(&adapter->mtx, MA_OWNED); INIT_DEBUGOUT("em_stop: begin"); em_disable_intr(adapter); em_reset_hw(&adapter->hw); callout_stop(&adapter->timer); callout_stop(&adapter->tx_fifo_timer); em_free_transmit_structures(adapter); em_free_receive_structures(adapter); /* Tell the stack that the interface is no longer active */ ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); return; } /********************************************************************* * * Determine hardware revision. * **********************************************************************/ static void em_identify_hardware(struct adapter * adapter) { device_t dev = adapter->dev; /* Make sure our PCI config space has the necessary stuff set */ adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); if (!((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) && (adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN))) { printf("em%d: Memory Access and/or Bus Master bits were not set!\n", adapter->unit); adapter->hw.pci_cmd_word |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); pci_write_config(dev, PCIR_COMMAND, adapter->hw.pci_cmd_word, 2); } /* Save off the information about this board */ adapter->hw.vendor_id = pci_get_vendor(dev); adapter->hw.device_id = pci_get_device(dev); adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); adapter->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); adapter->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); /* Identify the MAC */ if (em_set_mac_type(&adapter->hw)) printf("em%d: Unknown MAC Type\n", adapter->unit); if(adapter->hw.mac_type == em_82541 || adapter->hw.mac_type == em_82541_rev_2 || adapter->hw.mac_type == em_82547 || adapter->hw.mac_type == em_82547_rev_2) adapter->hw.phy_init_script = TRUE; return; } static int em_allocate_pci_resources(struct adapter * adapter) { int val, rid; device_t dev = adapter->dev; rid = PCIR_BAR(0); adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!(adapter->res_memory)) { printf("em%d: Unable to allocate bus resource: memory\n", adapter->unit); return(ENXIO); } adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->res_memory); adapter->osdep.mem_bus_space_handle = rman_get_bushandle(adapter->res_memory); adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; if (adapter->hw.mac_type > em_82543) { /* Figure our where our IO BAR is ? */ for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { val = pci_read_config(dev, rid, 4); if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) { adapter->io_rid = rid; break; } rid += 4; /* check for 64bit BAR */ if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT) rid += 4; } if (rid >= PCIR_CIS) { printf("em%d: Unable to locate IO BAR\n", adapter->unit); return (ENXIO); } adapter->res_ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); if (!(adapter->res_ioport)) { printf("em%d: Unable to allocate bus resource: ioport\n", adapter->unit); return(ENXIO); } adapter->hw.io_base = 0; adapter->osdep.io_bus_space_tag = rman_get_bustag(adapter->res_ioport); adapter->osdep.io_bus_space_handle = rman_get_bushandle(adapter->res_ioport); } rid = 0x0; adapter->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (!(adapter->res_interrupt)) { printf("em%d: Unable to allocate bus resource: interrupt\n", adapter->unit); return(ENXIO); } if (bus_setup_intr(dev, adapter->res_interrupt, INTR_TYPE_NET | INTR_MPSAFE, (void (*)(void *)) em_intr, adapter, &adapter->int_handler_tag)) { printf("em%d: Error registering interrupt handler!\n", adapter->unit); return(ENXIO); } adapter->hw.back = &adapter->osdep; return(0); } static void em_free_pci_resources(struct adapter * adapter) { device_t dev = adapter->dev; if (adapter->res_interrupt != NULL) { bus_teardown_intr(dev, adapter->res_interrupt, adapter->int_handler_tag); bus_release_resource(dev, SYS_RES_IRQ, 0, adapter->res_interrupt); } if (adapter->res_memory != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), adapter->res_memory); } if (adapter->res_ioport != NULL) { bus_release_resource(dev, SYS_RES_IOPORT, adapter->io_rid, adapter->res_ioport); } return; } /********************************************************************* * * Initialize the hardware to a configuration as specified by the * adapter structure. The controller is reset, the EEPROM is * verified, the MAC address is set, then the shared initialization * routines are called. * **********************************************************************/ static int em_hardware_init(struct adapter * adapter) { + uint16_t rx_buffer_size; + INIT_DEBUGOUT("em_hardware_init: begin"); /* Issue a global reset */ em_reset_hw(&adapter->hw); /* When hardware is reset, fifo_head is also reset */ adapter->tx_fifo_head = 0; /* Make sure we have a good EEPROM before we read from it */ if (em_validate_eeprom_checksum(&adapter->hw) < 0) { printf("em%d: The EEPROM Checksum Is Not Valid\n", adapter->unit); return(EIO); } if (em_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) { printf("em%d: EEPROM read error while reading part number\n", adapter->unit); return(EIO); } + /* + * These parameters control the automatic generation (Tx) and + * response (Rx) to Ethernet PAUSE frames. + * - High water mark should allow for at least two frames to be + * received after sending an XOFF. + * - Low water mark works best when it is very near the high water mark. + * This allows the receiver to restart by sending XON when it has drained + * a bit. Here we use an arbitary value of 1500 which will restart after + * one full frame is pulled from the buffer. There could be several smaller + * frames in the buffer and if so they will not trigger the XON until their + * total number reduces the buffer by 1500. + * - The pause time is fairly large at 1000 x 512ns = 512 usec. + */ + rx_buffer_size = ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff) << 10 ); + + adapter->hw.fc_high_water = rx_buffer_size - + roundup2(adapter->hw.max_frame_size, 1024); + adapter->hw.fc_low_water = adapter->hw.fc_high_water - 1500; + adapter->hw.fc_pause_time = 0x1000; + adapter->hw.fc_send_xon = TRUE; + adapter->hw.fc = em_fc_full; + if (em_init_hw(&adapter->hw) < 0) { printf("em%d: Hardware Initialization Failed", adapter->unit); return(EIO); } em_check_for_link(&adapter->hw); if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) adapter->link_active = 1; else adapter->link_active = 0; if (adapter->link_active) { em_get_speed_and_duplex(&adapter->hw, &adapter->link_speed, &adapter->link_duplex); } else { adapter->link_speed = 0; adapter->link_duplex = 0; } return(0); } /********************************************************************* * * Setup networking device structure and register an interface. * **********************************************************************/ static void em_setup_interface(device_t dev, struct adapter * adapter) { struct ifnet *ifp; INIT_DEBUGOUT("em_setup_interface: begin"); ifp = adapter->ifp = if_alloc(IFT_ETHER); if (ifp == NULL) panic("%s: can not if_alloc()", device_get_nameunit(dev)); if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_mtu = ETHERMTU; ifp->if_baudrate = 1000000000; ifp->if_init = em_init; ifp->if_softc = adapter; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = em_ioctl; ifp->if_start = em_start; ifp->if_watchdog = em_watchdog; IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1); ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1; IFQ_SET_READY(&ifp->if_snd); ether_ifattach(ifp, adapter->hw.mac_addr); ifp->if_capabilities = ifp->if_capenable = 0; if (adapter->hw.mac_type >= em_82543) { ifp->if_capabilities |= IFCAP_HWCSUM; ifp->if_capenable |= IFCAP_HWCSUM; } /* * Tell the upper layer(s) we support long frames. */ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; ifp->if_capenable |= IFCAP_VLAN_MTU; #ifdef DEVICE_POLLING ifp->if_capabilities |= IFCAP_POLLING; #endif /* * Specify the media types supported by this adapter and register * callbacks to update media and link information */ ifmedia_init(&adapter->media, IFM_IMASK, em_media_change, em_media_status); if (adapter->hw.media_type == em_media_type_fiber) { ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_SX, 0, NULL); } else { ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); } ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); return; } /********************************************************************* * * Workaround for SmartSpeed on 82541 and 82547 controllers * **********************************************************************/ static void em_smartspeed(struct adapter *adapter) { uint16_t phy_tmp; if(adapter->link_active || (adapter->hw.phy_type != em_phy_igp) || !adapter->hw.autoneg || !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL)) return; if(adapter->smartspeed == 0) { /* If Master/Slave config fault is asserted twice, * we assume back-to-back */ em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); if(!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) return; em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); if(phy_tmp & SR_1000T_MS_CONFIG_FAULT) { em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); if(phy_tmp & CR_1000T_MS_ENABLE) { phy_tmp &= ~CR_1000T_MS_ENABLE; em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); adapter->smartspeed++; if(adapter->hw.autoneg && !em_phy_setup_autoneg(&adapter->hw) && !em_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_tmp)) { phy_tmp |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); em_write_phy_reg(&adapter->hw, PHY_CTRL, phy_tmp); } } } return; } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { /* If still no link, perhaps using 2/3 pair cable */ em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); phy_tmp |= CR_1000T_MS_ENABLE; em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); if(adapter->hw.autoneg && !em_phy_setup_autoneg(&adapter->hw) && !em_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_tmp)) { phy_tmp |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); em_write_phy_reg(&adapter->hw, PHY_CTRL, phy_tmp); } } /* Restart process after EM_SMARTSPEED_MAX iterations */ if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) adapter->smartspeed = 0; return; } /* * Manage DMA'able memory. */ static void em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) { if (error) return; *(bus_addr_t *) arg = segs[0].ds_addr; } static int em_dma_malloc(struct adapter *adapter, bus_size_t size, struct em_dma_alloc *dma, int mapflags) { int r; r = bus_dma_tag_create(NULL, /* parent */ E1000_DBA_ALIGN, 0, /* alignment, bounds */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ size, /* maxsize */ 1, /* nsegments */ size, /* maxsegsize */ BUS_DMA_ALLOCNOW, /* flags */ NULL, /* lockfunc */ NULL, /* lockarg */ &dma->dma_tag); if (r != 0) { printf("em%d: em_dma_malloc: bus_dma_tag_create failed; " "error %u\n", adapter->unit, r); goto fail_0; } r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, BUS_DMA_NOWAIT, &dma->dma_map); if (r != 0) { printf("em%d: em_dma_malloc: bus_dmammem_alloc failed; " "size %ju, error %d\n", adapter->unit, (uintmax_t)size, r); goto fail_2; } dma->dma_paddr = 0; r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); if (r != 0 || dma->dma_paddr == 0) { printf("em%d: em_dma_malloc: bus_dmamap_load failed; " "error %u\n", adapter->unit, r); goto fail_3; } return (0); fail_3: bus_dmamap_unload(dma->dma_tag, dma->dma_map); fail_2: bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); bus_dma_tag_destroy(dma->dma_tag); fail_0: dma->dma_map = NULL; dma->dma_tag = NULL; return (r); } static void em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) { if (dma->dma_tag == NULL) return; if (dma->dma_map != NULL) { bus_dmamap_sync(dma->dma_tag, dma->dma_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(dma->dma_tag, dma->dma_map); bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); dma->dma_map = NULL; } bus_dma_tag_destroy(dma->dma_tag); dma->dma_tag = NULL; } /********************************************************************* * * Allocate memory for tx_buffer structures. The tx_buffer stores all * the information needed to transmit a packet on the wire. * **********************************************************************/ static int em_allocate_transmit_structures(struct adapter * adapter) { if (!(adapter->tx_buffer_area = (struct em_buffer *) malloc(sizeof(struct em_buffer) * adapter->num_tx_desc, M_DEVBUF, M_NOWAIT))) { printf("em%d: Unable to allocate tx_buffer memory\n", adapter->unit); return ENOMEM; } bzero(adapter->tx_buffer_area, sizeof(struct em_buffer) * adapter->num_tx_desc); return 0; } /********************************************************************* * * Allocate and initialize transmit structures. * **********************************************************************/ static int em_setup_transmit_structures(struct adapter * adapter) { struct em_buffer *tx_buffer; bus_size_t size; int error, i; /* * Setup DMA descriptor areas. */ size = roundup2(adapter->hw.max_frame_size, MCLBYTES); if ((error = bus_dma_tag_create(NULL, /* parent */ 1, 0, /* alignment, bounds */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ size, /* maxsize */ EM_MAX_SCATTER, /* nsegments */ size, /* maxsegsize */ 0, /* flags */ NULL, /* lockfunc */ NULL, /* lockarg */ &adapter->txtag)) != 0) { printf("em%d: Unable to allocate TX DMA tag\n", adapter->unit); goto fail; } if ((error = em_allocate_transmit_structures(adapter)) != 0) goto fail; bzero((void *) adapter->tx_desc_base, (sizeof(struct em_tx_desc)) * adapter->num_tx_desc); tx_buffer = adapter->tx_buffer_area; for (i = 0; i < adapter->num_tx_desc; i++) { error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map); if (error != 0) { printf("em%d: Unable to create TX DMA map\n", adapter->unit); goto fail; } tx_buffer++; } adapter->next_avail_tx_desc = 0; adapter->oldest_used_tx_desc = 0; /* Set number of descriptors available */ adapter->num_tx_desc_avail = adapter->num_tx_desc; /* Set checksum context */ adapter->active_checksum_context = OFFLOAD_NONE; bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); return (0); fail: em_free_transmit_structures(adapter); return (error); } /********************************************************************* * * Enable transmit unit. * **********************************************************************/ static void em_initialize_transmit_unit(struct adapter * adapter) { u_int32_t reg_tctl; u_int32_t reg_tipg = 0; u_int64_t bus_addr; INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); /* Setup the Base and Length of the Tx Descriptor Ring */ bus_addr = adapter->txdma.dma_paddr; E1000_WRITE_REG(&adapter->hw, TDBAL, (u_int32_t)bus_addr); E1000_WRITE_REG(&adapter->hw, TDBAH, (u_int32_t)(bus_addr >> 32)); E1000_WRITE_REG(&adapter->hw, TDLEN, adapter->num_tx_desc * sizeof(struct em_tx_desc)); /* Setup the HW Tx Head and Tail descriptor pointers */ E1000_WRITE_REG(&adapter->hw, TDH, 0); E1000_WRITE_REG(&adapter->hw, TDT, 0); HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&adapter->hw, TDBAL), E1000_READ_REG(&adapter->hw, TDLEN)); /* Set the default values for the Tx Inter Packet Gap timer */ switch (adapter->hw.mac_type) { case em_82542_rev2_0: case em_82542_rev2_1: reg_tipg = DEFAULT_82542_TIPG_IPGT; reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; break; default: if (adapter->hw.media_type == em_media_type_fiber) reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; else reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; } E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg); E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay.value); if(adapter->hw.mac_type >= em_82540) E1000_WRITE_REG(&adapter->hw, TADV, adapter->tx_abs_int_delay.value); /* Program the Transmit Control Register */ reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); - if (adapter->hw.mac_type >= em_82573) + if (adapter->hw.mac_type >= em_82571) reg_tctl |= E1000_TCTL_MULR; if (adapter->link_duplex == 1) { reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; } else { reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; } E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl); /* Setup Transmit Descriptor Settings for this adapter */ adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS; if (adapter->tx_int_delay.value > 0) adapter->txd_cmd |= E1000_TXD_CMD_IDE; return; } /********************************************************************* * * Free all transmit related data structures. * **********************************************************************/ static void em_free_transmit_structures(struct adapter * adapter) { struct em_buffer *tx_buffer; int i; INIT_DEBUGOUT("free_transmit_structures: begin"); if (adapter->tx_buffer_area != NULL) { tx_buffer = adapter->tx_buffer_area; for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { if (tx_buffer->m_head != NULL) { bus_dmamap_sync(adapter->txtag, tx_buffer->map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(adapter->txtag, tx_buffer->map); m_freem(tx_buffer->m_head); tx_buffer->m_head = NULL; } else if (tx_buffer->map != NULL) bus_dmamap_unload(adapter->txtag, tx_buffer->map); if (tx_buffer->map != NULL) { bus_dmamap_destroy(adapter->txtag, tx_buffer->map); tx_buffer->map = NULL; } } } if (adapter->tx_buffer_area != NULL) { free(adapter->tx_buffer_area, M_DEVBUF); adapter->tx_buffer_area = NULL; } if (adapter->txtag != NULL) { bus_dma_tag_destroy(adapter->txtag); adapter->txtag = NULL; } return; } /********************************************************************* * * The offload context needs to be set when we transfer the first * packet of a particular protocol (TCP/UDP). We change the * context only if the protocol type changes. * **********************************************************************/ static void em_transmit_checksum_setup(struct adapter * adapter, struct mbuf *mp, u_int32_t *txd_upper, u_int32_t *txd_lower) { struct em_context_desc *TXD; struct em_buffer *tx_buffer; int curr_txd; if (mp->m_pkthdr.csum_flags) { if (mp->m_pkthdr.csum_flags & CSUM_TCP) { *txd_upper = E1000_TXD_POPTS_TXSM << 8; *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; if (adapter->active_checksum_context == OFFLOAD_TCP_IP) return; else adapter->active_checksum_context = OFFLOAD_TCP_IP; } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { *txd_upper = E1000_TXD_POPTS_TXSM << 8; *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; if (adapter->active_checksum_context == OFFLOAD_UDP_IP) return; else adapter->active_checksum_context = OFFLOAD_UDP_IP; } else { *txd_upper = 0; *txd_lower = 0; return; } } else { *txd_upper = 0; *txd_lower = 0; return; } /* If we reach this point, the checksum offload context * needs to be reset. */ curr_txd = adapter->next_avail_tx_desc; tx_buffer = &adapter->tx_buffer_area[curr_txd]; TXD = (struct em_context_desc *) &adapter->tx_desc_base[curr_txd]; TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; TXD->lower_setup.ip_fields.ipcso = ETHER_HDR_LEN + offsetof(struct ip, ip_sum); TXD->lower_setup.ip_fields.ipcse = htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); TXD->upper_setup.tcp_fields.tucss = ETHER_HDR_LEN + sizeof(struct ip); TXD->upper_setup.tcp_fields.tucse = htole16(0); if (adapter->active_checksum_context == OFFLOAD_TCP_IP) { TXD->upper_setup.tcp_fields.tucso = ETHER_HDR_LEN + sizeof(struct ip) + offsetof(struct tcphdr, th_sum); } else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) { TXD->upper_setup.tcp_fields.tucso = ETHER_HDR_LEN + sizeof(struct ip) + offsetof(struct udphdr, uh_sum); } TXD->tcp_seg_setup.data = htole32(0); TXD->cmd_and_length = htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT); tx_buffer->m_head = NULL; if (++curr_txd == adapter->num_tx_desc) curr_txd = 0; adapter->num_tx_desc_avail--; adapter->next_avail_tx_desc = curr_txd; return; } /********************************************************************** * * Examine each tx_buffer in the used queue. If the hardware is done * processing the packet then free associated resources. The * tx_buffer is put back on the free queue. * **********************************************************************/ static void em_clean_transmit_interrupts(struct adapter * adapter) { int i, num_avail; struct em_buffer *tx_buffer; struct em_tx_desc *tx_desc; struct ifnet *ifp = adapter->ifp; mtx_assert(&adapter->mtx, MA_OWNED); if (adapter->num_tx_desc_avail == adapter->num_tx_desc) return; num_avail = adapter->num_tx_desc_avail; i = adapter->oldest_used_tx_desc; tx_buffer = &adapter->tx_buffer_area[i]; tx_desc = &adapter->tx_desc_base[i]; bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, BUS_DMASYNC_POSTREAD); while (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { tx_desc->upper.data = 0; num_avail++; if (tx_buffer->m_head) { ifp->if_opackets++; bus_dmamap_sync(adapter->txtag, tx_buffer->map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(adapter->txtag, tx_buffer->map); m_freem(tx_buffer->m_head); tx_buffer->m_head = NULL; } if (++i == adapter->num_tx_desc) i = 0; tx_buffer = &adapter->tx_buffer_area[i]; tx_desc = &adapter->tx_desc_base[i]; } bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); adapter->oldest_used_tx_desc = i; /* * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack * that it is OK to send packets. * If there are no pending descriptors, clear the timeout. Otherwise, * if some descriptors have been freed, restart the timeout. */ if (num_avail > EM_TX_CLEANUP_THRESHOLD) { ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if (num_avail == adapter->num_tx_desc) ifp->if_timer = 0; else if (num_avail == adapter->num_tx_desc_avail) ifp->if_timer = EM_TX_TIMEOUT; } adapter->num_tx_desc_avail = num_avail; return; } /********************************************************************* * * Get a buffer from system mbuf buffer pool. * **********************************************************************/ static int em_get_buf(int i, struct adapter *adapter, struct mbuf *nmp) { struct mbuf *mp = nmp; struct em_buffer *rx_buffer; struct ifnet *ifp; bus_dma_segment_t segs[1]; int error, nsegs; ifp = adapter->ifp; if (mp == NULL) { mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); if (mp == NULL) { adapter->mbuf_cluster_failed++; return(ENOBUFS); } mp->m_len = mp->m_pkthdr.len = MCLBYTES; } else { mp->m_len = mp->m_pkthdr.len = MCLBYTES; mp->m_data = mp->m_ext.ext_buf; mp->m_next = NULL; } if (ifp->if_mtu <= ETHERMTU) { m_adj(mp, ETHER_ALIGN); } rx_buffer = &adapter->rx_buffer_area[i]; /* * Using memory from the mbuf cluster pool, invoke the * bus_dma machinery to arrange the memory mapping. */ error = bus_dmamap_load_mbuf_sg(adapter->rxtag, rx_buffer->map, mp, segs, &nsegs, 0); if (error != 0) { m_free(mp); return(error); } /* If nsegs is wrong then the stack is corrupt */ KASSERT(nsegs == 1, ("Too many segments returned!")); rx_buffer->m_head = mp; adapter->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); return(0); } /********************************************************************* * * Allocate memory for rx_buffer structures. Since we use one * rx_buffer per received packet, the maximum number of rx_buffer's * that we'll need is equal to the number of receive descriptors * that we've allocated. * **********************************************************************/ static int em_allocate_receive_structures(struct adapter * adapter) { int i, error; struct em_buffer *rx_buffer; if (!(adapter->rx_buffer_area = (struct em_buffer *) malloc(sizeof(struct em_buffer) * adapter->num_rx_desc, M_DEVBUF, M_NOWAIT))) { printf("em%d: Unable to allocate rx_buffer memory\n", adapter->unit); return(ENOMEM); } bzero(adapter->rx_buffer_area, sizeof(struct em_buffer) * adapter->num_rx_desc); error = bus_dma_tag_create(NULL, /* parent */ 1, 0, /* alignment, bounds */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES, /* maxsize */ 1, /* nsegments */ MCLBYTES, /* maxsegsize */ BUS_DMA_ALLOCNOW, /* flags */ NULL, /* lockfunc */ NULL, /* lockarg */ &adapter->rxtag); if (error != 0) { printf("em%d: em_allocate_receive_structures: " "bus_dma_tag_create failed; error %u\n", adapter->unit, error); goto fail; } rx_buffer = adapter->rx_buffer_area; for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, &rx_buffer->map); if (error != 0) { printf("em%d: em_allocate_receive_structures: " "bus_dmamap_create failed; error %u\n", adapter->unit, error); goto fail; } } for (i = 0; i < adapter->num_rx_desc; i++) { error = em_get_buf(i, adapter, NULL); if (error != 0) goto fail; } bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); return(0); fail: em_free_receive_structures(adapter); return (error); } /********************************************************************* * * Allocate and initialize receive structures. * **********************************************************************/ static int em_setup_receive_structures(struct adapter * adapter) { bzero((void *) adapter->rx_desc_base, (sizeof(struct em_rx_desc)) * adapter->num_rx_desc); if (em_allocate_receive_structures(adapter)) return ENOMEM; /* Setup our descriptor pointers */ adapter->next_rx_desc_to_check = 0; return(0); } /********************************************************************* * * Enable receive unit. * **********************************************************************/ static void em_initialize_receive_unit(struct adapter * adapter) { u_int32_t reg_rctl; u_int32_t reg_rxcsum; struct ifnet *ifp; u_int64_t bus_addr; INIT_DEBUGOUT("em_initialize_receive_unit: begin"); ifp = adapter->ifp; /* Make sure receives are disabled while setting up the descriptor ring */ E1000_WRITE_REG(&adapter->hw, RCTL, 0); /* Set the Receive Delay Timer Register */ E1000_WRITE_REG(&adapter->hw, RDTR, adapter->rx_int_delay.value | E1000_RDT_FPDB); if(adapter->hw.mac_type >= em_82540) { E1000_WRITE_REG(&adapter->hw, RADV, adapter->rx_abs_int_delay.value); /* Set the interrupt throttling rate. Value is calculated * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ #define MAX_INTS_PER_SEC 8000 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) E1000_WRITE_REG(&adapter->hw, ITR, DEFAULT_ITR); } /* Setup the Base and Length of the Rx Descriptor Ring */ bus_addr = adapter->rxdma.dma_paddr; E1000_WRITE_REG(&adapter->hw, RDBAL, (u_int32_t)bus_addr); E1000_WRITE_REG(&adapter->hw, RDBAH, (u_int32_t)(bus_addr >> 32)); E1000_WRITE_REG(&adapter->hw, RDLEN, adapter->num_rx_desc * sizeof(struct em_rx_desc)); /* Setup the HW Rx Head and Tail Descriptor Pointers */ E1000_WRITE_REG(&adapter->hw, RDH, 0); E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1); /* Setup the Receive Control Register */ reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); if (adapter->hw.tbi_compatibility_on == TRUE) reg_rctl |= E1000_RCTL_SBP; switch (adapter->rx_buffer_len) { default: case EM_RXBUFFER_2048: reg_rctl |= E1000_RCTL_SZ_2048; break; case EM_RXBUFFER_4096: reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; break; case EM_RXBUFFER_8192: reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; break; case EM_RXBUFFER_16384: reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; break; } if (ifp->if_mtu > ETHERMTU) reg_rctl |= E1000_RCTL_LPE; /* Enable 82543 Receive Checksum Offload for TCP and UDP */ if ((adapter->hw.mac_type >= em_82543) && (ifp->if_capenable & IFCAP_RXCSUM)) { reg_rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM); reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); E1000_WRITE_REG(&adapter->hw, RXCSUM, reg_rxcsum); } /* Enable Receives */ E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); return; } /********************************************************************* * * Free receive related data structures. * **********************************************************************/ static void em_free_receive_structures(struct adapter *adapter) { struct em_buffer *rx_buffer; int i; INIT_DEBUGOUT("free_receive_structures: begin"); if (adapter->rx_buffer_area != NULL) { rx_buffer = adapter->rx_buffer_area; for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { if (rx_buffer->m_head != NULL) { bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(adapter->rxtag, rx_buffer->map); m_freem(rx_buffer->m_head); rx_buffer->m_head = NULL; } else if (rx_buffer->map != NULL) bus_dmamap_unload(adapter->rxtag, rx_buffer->map); if (rx_buffer->map != NULL) { bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); rx_buffer->map = NULL; } } } if (adapter->rx_buffer_area != NULL) { free(adapter->rx_buffer_area, M_DEVBUF); adapter->rx_buffer_area = NULL; } if (adapter->rxtag != NULL) { bus_dma_tag_destroy(adapter->rxtag); adapter->rxtag = NULL; } return; } /********************************************************************* * * This routine executes in interrupt context. It replenishes * the mbufs in the descriptor and sends data which has been * dma'ed into host memory to upper layer. * * We loop at most count times if count is > 0, or until done if * count < 0. * *********************************************************************/ static void em_process_receive_interrupts(struct adapter * adapter, int count) { struct ifnet *ifp; struct mbuf *mp; u_int8_t accept_frame = 0; u_int8_t eop = 0; u_int16_t len, desc_len, prev_len_adj; int i; /* Pointer to the receive descriptor being examined. */ struct em_rx_desc *current_desc; mtx_assert(&adapter->mtx, MA_OWNED); ifp = adapter->ifp; i = adapter->next_rx_desc_to_check; current_desc = &adapter->rx_desc_base[i]; bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, BUS_DMASYNC_POSTREAD); if (!((current_desc->status) & E1000_RXD_STAT_DD)) { return; } while ((current_desc->status & E1000_RXD_STAT_DD) && (count != 0) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) { struct mbuf *m = NULL; mp = adapter->rx_buffer_area[i].m_head; bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(adapter->rxtag, adapter->rx_buffer_area[i].map); accept_frame = 1; prev_len_adj = 0; desc_len = le16toh(current_desc->length); if (current_desc->status & E1000_RXD_STAT_EOP) { count--; eop = 1; if (desc_len < ETHER_CRC_LEN) { len = 0; prev_len_adj = ETHER_CRC_LEN - desc_len; } else { len = desc_len - ETHER_CRC_LEN; } } else { eop = 0; len = desc_len; } if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { u_int8_t last_byte; u_int32_t pkt_len = desc_len; if (adapter->fmp != NULL) pkt_len += adapter->fmp->m_pkthdr.len; last_byte = *(mtod(mp, caddr_t) + desc_len - 1); if (TBI_ACCEPT(&adapter->hw, current_desc->status, current_desc->errors, pkt_len, last_byte)) { em_tbi_adjust_stats(&adapter->hw, &adapter->stats, pkt_len, adapter->hw.mac_addr); if (len > 0) len--; } else { accept_frame = 0; } } if (accept_frame) { if (em_get_buf(i, adapter, NULL) == ENOBUFS) { adapter->dropped_pkts++; em_get_buf(i, adapter, mp); if (adapter->fmp != NULL) m_freem(adapter->fmp); adapter->fmp = NULL; adapter->lmp = NULL; break; } /* Assign correct length to the current fragment */ mp->m_len = len; if (adapter->fmp == NULL) { mp->m_pkthdr.len = len; adapter->fmp = mp; /* Store the first mbuf */ adapter->lmp = mp; } else { /* Chain mbuf's together */ mp->m_flags &= ~M_PKTHDR; /* * Adjust length of previous mbuf in chain if we * received less than 4 bytes in the last descriptor. */ if (prev_len_adj > 0) { adapter->lmp->m_len -= prev_len_adj; adapter->fmp->m_pkthdr.len -= prev_len_adj; } adapter->lmp->m_next = mp; adapter->lmp = adapter->lmp->m_next; adapter->fmp->m_pkthdr.len += len; } if (eop) { adapter->fmp->m_pkthdr.rcvif = ifp; ifp->if_ipackets++; em_receive_checksum(adapter, current_desc, adapter->fmp); if (current_desc->status & E1000_RXD_STAT_VP) VLAN_INPUT_TAG(ifp, adapter->fmp, (le16toh(current_desc->special) & E1000_RXD_SPC_VLAN_MASK), adapter->fmp = NULL); m = adapter->fmp; adapter->fmp = NULL; adapter->lmp = NULL; } } else { adapter->dropped_pkts++; em_get_buf(i, adapter, mp); if (adapter->fmp != NULL) m_freem(adapter->fmp); adapter->fmp = NULL; adapter->lmp = NULL; } /* Zero out the receive descriptors status */ current_desc->status = 0; bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ E1000_WRITE_REG(&adapter->hw, RDT, i); /* Advance our pointers to the next descriptor */ if (++i == adapter->num_rx_desc) i = 0; if (m != NULL) { adapter->next_rx_desc_to_check = i; EM_UNLOCK(adapter); (*ifp->if_input)(ifp, m); EM_LOCK(adapter); i = adapter->next_rx_desc_to_check; } current_desc = &adapter->rx_desc_base[i]; } adapter->next_rx_desc_to_check = i; return; } /********************************************************************* * * Verify that the hardware indicated that the checksum is valid. * Inform the stack about the status of checksum so that stack * doesn't spend time verifying the checksum. * *********************************************************************/ static void em_receive_checksum(struct adapter *adapter, struct em_rx_desc *rx_desc, struct mbuf *mp) { /* 82543 or newer only */ if ((adapter->hw.mac_type < em_82543) || /* Ignore Checksum bit is set */ (rx_desc->status & E1000_RXD_STAT_IXSM)) { mp->m_pkthdr.csum_flags = 0; return; } if (rx_desc->status & E1000_RXD_STAT_IPCS) { /* Did it pass? */ if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { /* IP Checksum Good */ mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; } else { mp->m_pkthdr.csum_flags = 0; } } if (rx_desc->status & E1000_RXD_STAT_TCPCS) { /* Did it pass? */ if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { mp->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); mp->m_pkthdr.csum_data = htons(0xffff); } } return; } static void em_enable_vlans(struct adapter *adapter) { uint32_t ctrl; E1000_WRITE_REG(&adapter->hw, VET, ETHERTYPE_VLAN); ctrl = E1000_READ_REG(&adapter->hw, CTRL); ctrl |= E1000_CTRL_VME; E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); return; } static void em_disable_vlans(struct adapter *adapter) { uint32_t ctrl; ctrl = E1000_READ_REG(&adapter->hw, CTRL); ctrl &= ~E1000_CTRL_VME; E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); return; } static void em_enable_intr(struct adapter * adapter) { E1000_WRITE_REG(&adapter->hw, IMS, (IMS_ENABLE_MASK)); return; } static void em_disable_intr(struct adapter *adapter) { /* * The first version of 82542 had an errata where when link was forced it * would stay up even up even if the cable was disconnected. Sequence errors * were used to detect the disconnect and then the driver would unforce the link. * This code in the in the ISR. For this to work correctly the Sequence error * interrupt had to be enabled all the time. */ if (adapter->hw.mac_type == em_82542_rev2_0) E1000_WRITE_REG(&adapter->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ)); else E1000_WRITE_REG(&adapter->hw, IMC, 0xffffffff); return; } static int em_is_valid_ether_addr(u_int8_t *addr) { char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { return (FALSE); } return(TRUE); } void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) { pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); } void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) { *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); return; } void em_pci_set_mwi(struct em_hw *hw) { pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); return; } void em_pci_clear_mwi(struct em_hw *hw) { pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); return; } /********************************************************************* * 82544 Coexistence issue workaround. * There are 2 issues. * 1. Transmit Hang issue. * To detect this issue, following equation can be used... * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. * If SUM[3:0] is in between 1 to 4, we will have this issue. * * 2. DAC issue. * To detect this issue, following equation can be used... * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. * If SUM[3:0] is in between 9 to c, we will have this issue. * * * WORKAROUND: * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) * *** *********************************************************************/ static u_int32_t em_fill_descriptors (bus_addr_t address, u_int32_t length, PDESC_ARRAY desc_array) { /* Since issue is sensitive to length and address.*/ /* Let us first check the address...*/ u_int32_t safe_terminator; if (length <= 4) { desc_array->descriptor[0].address = address; desc_array->descriptor[0].length = length; desc_array->elements = 1; return desc_array->elements; } safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF); /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ if (safe_terminator == 0 || (safe_terminator > 4 && safe_terminator < 9) || (safe_terminator > 0xC && safe_terminator <= 0xF)) { desc_array->descriptor[0].address = address; desc_array->descriptor[0].length = length; desc_array->elements = 1; return desc_array->elements; } desc_array->descriptor[0].address = address; desc_array->descriptor[0].length = length - 4; desc_array->descriptor[1].address = address + (length - 4); desc_array->descriptor[1].length = 4; desc_array->elements = 2; return desc_array->elements; } /********************************************************************** * * Update the board statistics counters. * **********************************************************************/ static void em_update_stats_counters(struct adapter *adapter) { struct ifnet *ifp; if(adapter->hw.media_type == em_media_type_copper || (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) { adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, SYMERRS); adapter->stats.sec += E1000_READ_REG(&adapter->hw, SEC); } adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, CRCERRS); adapter->stats.mpc += E1000_READ_REG(&adapter->hw, MPC); adapter->stats.scc += E1000_READ_REG(&adapter->hw, SCC); adapter->stats.ecol += E1000_READ_REG(&adapter->hw, ECOL); adapter->stats.mcc += E1000_READ_REG(&adapter->hw, MCC); adapter->stats.latecol += E1000_READ_REG(&adapter->hw, LATECOL); adapter->stats.colc += E1000_READ_REG(&adapter->hw, COLC); adapter->stats.dc += E1000_READ_REG(&adapter->hw, DC); adapter->stats.rlec += E1000_READ_REG(&adapter->hw, RLEC); adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, XONRXC); adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, XONTXC); adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, XOFFRXC); adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, XOFFTXC); adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, FCRUC); adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, PRC64); adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, PRC127); adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, PRC255); adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, PRC511); adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, PRC1023); adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, PRC1522); adapter->stats.gprc += E1000_READ_REG(&adapter->hw, GPRC); adapter->stats.bprc += E1000_READ_REG(&adapter->hw, BPRC); adapter->stats.mprc += E1000_READ_REG(&adapter->hw, MPRC); adapter->stats.gptc += E1000_READ_REG(&adapter->hw, GPTC); /* For the 64-bit byte counters the low dword must be read first. */ /* Both registers clear on the read of the high dword */ adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, GORCL); adapter->stats.gorch += E1000_READ_REG(&adapter->hw, GORCH); adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, GOTCL); adapter->stats.gotch += E1000_READ_REG(&adapter->hw, GOTCH); adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, RNBC); adapter->stats.ruc += E1000_READ_REG(&adapter->hw, RUC); adapter->stats.rfc += E1000_READ_REG(&adapter->hw, RFC); adapter->stats.roc += E1000_READ_REG(&adapter->hw, ROC); adapter->stats.rjc += E1000_READ_REG(&adapter->hw, RJC); adapter->stats.torl += E1000_READ_REG(&adapter->hw, TORL); adapter->stats.torh += E1000_READ_REG(&adapter->hw, TORH); adapter->stats.totl += E1000_READ_REG(&adapter->hw, TOTL); adapter->stats.toth += E1000_READ_REG(&adapter->hw, TOTH); adapter->stats.tpr += E1000_READ_REG(&adapter->hw, TPR); adapter->stats.tpt += E1000_READ_REG(&adapter->hw, TPT); adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, PTC64); adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, PTC127); adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, PTC255); adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, PTC511); adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, PTC1023); adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, PTC1522); adapter->stats.mptc += E1000_READ_REG(&adapter->hw, MPTC); adapter->stats.bptc += E1000_READ_REG(&adapter->hw, BPTC); if (adapter->hw.mac_type >= em_82543) { adapter->stats.algnerrc += E1000_READ_REG(&adapter->hw, ALGNERRC); adapter->stats.rxerrc += E1000_READ_REG(&adapter->hw, RXERRC); adapter->stats.tncrs += E1000_READ_REG(&adapter->hw, TNCRS); adapter->stats.cexterr += E1000_READ_REG(&adapter->hw, CEXTERR); adapter->stats.tsctc += E1000_READ_REG(&adapter->hw, TSCTC); adapter->stats.tsctfc += E1000_READ_REG(&adapter->hw, TSCTFC); } ifp = adapter->ifp; ifp->if_collisions = adapter->stats.colc; /* Rx Errors */ ifp->if_ierrors = adapter->dropped_pkts + adapter->stats.rxerrc + adapter->stats.crcerrs + adapter->stats.algnerrc + adapter->stats.rlec + adapter->stats.mpc + adapter->stats.cexterr; /* Tx Errors */ ifp->if_oerrors = adapter->stats.ecol + adapter->stats.latecol + adapter->watchdog_events; } /********************************************************************** * * This routine is called only when em_display_debug_stats is enabled. * This routine provides a way to take a look at important statistics * maintained by the driver and hardware. * **********************************************************************/ static void em_print_debug_info(struct adapter *adapter) { - int unit = adapter->unit; + int unit = adapter->unit; uint8_t *hw_addr = adapter->hw.hw_addr; printf("em%d: Adapter hardware address = %p \n", unit, hw_addr); - printf("em%d:CTRL = 0x%x\n", unit, - E1000_READ_REG(&adapter->hw, CTRL)); - printf("em%d:RCTL = 0x%x PS=(0x8402)\n", unit, - E1000_READ_REG(&adapter->hw, RCTL)); - printf("em%d:tx_int_delay = %d, tx_abs_int_delay = %d\n", unit, - E1000_READ_REG(&adapter->hw, TIDV), - E1000_READ_REG(&adapter->hw, TADV)); - printf("em%d:rx_int_delay = %d, rx_abs_int_delay = %d\n", unit, - E1000_READ_REG(&adapter->hw, RDTR), - E1000_READ_REG(&adapter->hw, RADV)); - printf("em%d: fifo workaround = %lld, fifo_reset = %lld\n", unit, - (long long)adapter->tx_fifo_wrk_cnt, - (long long)adapter->tx_fifo_reset_cnt); - printf("em%d: hw tdh = %d, hw tdt = %d\n", unit, - E1000_READ_REG(&adapter->hw, TDH), - E1000_READ_REG(&adapter->hw, TDT)); - printf("em%d: Num Tx descriptors avail = %d\n", unit, - adapter->num_tx_desc_avail); - printf("em%d: Tx Descriptors not avail1 = %ld\n", unit, - adapter->no_tx_desc_avail1); - printf("em%d: Tx Descriptors not avail2 = %ld\n", unit, - adapter->no_tx_desc_avail2); - printf("em%d: Std mbuf failed = %ld\n", unit, - adapter->mbuf_alloc_failed); - printf("em%d: Std mbuf cluster failed = %ld\n", unit, - adapter->mbuf_cluster_failed); - printf("em%d: Driver dropped packets = %ld\n", unit, - adapter->dropped_pkts); + printf("em%d: CTRL = 0x%x RCTL = 0x%x \n", unit, + E1000_READ_REG(&adapter->hw, CTRL), + E1000_READ_REG(&adapter->hw, RCTL)); + printf("em%d: Packet buffer = Tx=%dk Rx=%dk \n", unit, + ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff0000) >> 16),\ + (E1000_READ_REG(&adapter->hw, PBA) & 0xffff) ); + printf("em%d: Flow control watermarks high = %d low = %d\n", unit, + adapter->hw.fc_high_water, + adapter->hw.fc_low_water); + printf("em%d: tx_int_delay = %d, tx_abs_int_delay = %d\n", unit, + E1000_READ_REG(&adapter->hw, TIDV), + E1000_READ_REG(&adapter->hw, TADV)); + printf("em%d: rx_int_delay = %d, rx_abs_int_delay = %d\n", unit, + E1000_READ_REG(&adapter->hw, RDTR), + E1000_READ_REG(&adapter->hw, RADV)); + printf("em%d: fifo workaround = %lld, fifo_reset_count = %lld\n", + unit, (long long)adapter->tx_fifo_wrk_cnt, + (long long)adapter->tx_fifo_reset_cnt); + printf("em%d: hw tdh = %d, hw tdt = %d\n", unit, + E1000_READ_REG(&adapter->hw, TDH), + E1000_READ_REG(&adapter->hw, TDT)); + printf("em%d: Num Tx descriptors avail = %d\n", unit, + adapter->num_tx_desc_avail); + printf("em%d: Tx Descriptors not avail1 = %ld\n", unit, + adapter->no_tx_desc_avail1); + printf("em%d: Tx Descriptors not avail2 = %ld\n", unit, + adapter->no_tx_desc_avail2); + printf("em%d: Std mbuf failed = %ld\n", unit, + adapter->mbuf_alloc_failed); + printf("em%d: Std mbuf cluster failed = %ld\n", unit, + adapter->mbuf_cluster_failed); + printf("em%d: Driver dropped packets = %ld\n", unit, + adapter->dropped_pkts); - return; + return; } static void em_print_hw_stats(struct adapter *adapter) { int unit = adapter->unit; printf("em%d: Excessive collisions = %lld\n", unit, (long long)adapter->stats.ecol); printf("em%d: Symbol errors = %lld\n", unit, (long long)adapter->stats.symerrs); printf("em%d: Sequence errors = %lld\n", unit, (long long)adapter->stats.sec); printf("em%d: Defer count = %lld\n", unit, (long long)adapter->stats.dc); printf("em%d: Missed Packets = %lld\n", unit, (long long)adapter->stats.mpc); printf("em%d: Receive No Buffers = %lld\n", unit, (long long)adapter->stats.rnbc); printf("em%d: Receive length errors = %lld\n", unit, (long long)adapter->stats.rlec); printf("em%d: Receive errors = %lld\n", unit, (long long)adapter->stats.rxerrc); printf("em%d: Crc errors = %lld\n", unit, (long long)adapter->stats.crcerrs); printf("em%d: Alignment errors = %lld\n", unit, (long long)adapter->stats.algnerrc); printf("em%d: Carrier extension errors = %lld\n", unit, (long long)adapter->stats.cexterr); printf("em%d: RX overruns = %ld\n", unit, adapter->rx_overruns); printf("em%d: watchdog timeouts = %ld\n", unit, adapter->watchdog_events); printf("em%d: XON Rcvd = %lld\n", unit, (long long)adapter->stats.xonrxc); printf("em%d: XON Xmtd = %lld\n", unit, (long long)adapter->stats.xontxc); printf("em%d: XOFF Rcvd = %lld\n", unit, (long long)adapter->stats.xoffrxc); printf("em%d: XOFF Xmtd = %lld\n", unit, (long long)adapter->stats.xofftxc); printf("em%d: Good Packets Rcvd = %lld\n", unit, (long long)adapter->stats.gprc); printf("em%d: Good Packets Xmtd = %lld\n", unit, (long long)adapter->stats.gptc); return; } static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) { int error; int result; struct adapter *adapter; result = -1; error = sysctl_handle_int(oidp, &result, 0, req); if (error || !req->newptr) return (error); if (result == 1) { adapter = (struct adapter *)arg1; em_print_debug_info(adapter); } return error; } static int em_sysctl_stats(SYSCTL_HANDLER_ARGS) { int error; int result; struct adapter *adapter; result = -1; error = sysctl_handle_int(oidp, &result, 0, req); if (error || !req->newptr) return (error); if (result == 1) { adapter = (struct adapter *)arg1; em_print_hw_stats(adapter); } return error; } static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) { struct em_int_delay_info *info; struct adapter *adapter; u_int32_t regval; int error; int usecs; int ticks; info = (struct em_int_delay_info *)arg1; usecs = info->value; error = sysctl_handle_int(oidp, &usecs, 0, req); if (error != 0 || req->newptr == NULL) return error; if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) return EINVAL; info->value = usecs; ticks = E1000_USECS_TO_TICKS(usecs); adapter = info->adapter; EM_LOCK(adapter); regval = E1000_READ_OFFSET(&adapter->hw, info->offset); regval = (regval & ~0xffff) | (ticks & 0xffff); /* Handle a few special cases. */ switch (info->offset) { case E1000_RDTR: case E1000_82542_RDTR: regval |= E1000_RDT_FPDB; break; case E1000_TIDV: case E1000_82542_TIDV: if (ticks == 0) { adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; /* Don't write 0 into the TIDV register. */ regval++; } else adapter->txd_cmd |= E1000_TXD_CMD_IDE; break; } E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); EM_UNLOCK(adapter); return 0; } static void em_add_int_delay_sysctl(struct adapter *adapter, const char *name, const char *description, struct em_int_delay_info *info, int offset, int value) { info->adapter = adapter; info->offset = offset; info->value = value; SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, info, 0, em_sysctl_int_delay, "I", description); } diff --git a/sys/dev/em/if_em_hw.c b/sys/dev/em/if_em_hw.c index 8795f6d1e7c4..179a2eed6a32 100644 --- a/sys/dev/em/if_em_hw.c +++ b/sys/dev/em/if_em_hw.c @@ -1,6624 +1,6821 @@ /******************************************************************************* Copyright (c) 2001-2005, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ /* if_em_hw.c * Shared functions for accessing and configuring the MAC */ #include __FBSDID("$FreeBSD$"); #include static int32_t em_set_phy_type(struct em_hw *hw); static void em_phy_init_script(struct em_hw *hw); static int32_t em_setup_copper_link(struct em_hw *hw); static int32_t em_setup_fiber_serdes_link(struct em_hw *hw); static int32_t em_adjust_serdes_amplitude(struct em_hw *hw); static int32_t em_phy_force_speed_duplex(struct em_hw *hw); static int32_t em_config_mac_to_phy(struct em_hw *hw); static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl); static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl); static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count); static uint16_t em_shift_in_mdi_bits(struct em_hw *hw); static int32_t em_phy_reset_dsp(struct em_hw *hw); static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); static int32_t em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); static int32_t em_spi_eeprom_ready(struct em_hw *hw); static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd); static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd); static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count); static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data); static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr, uint16_t *phy_data); static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count); static int32_t em_acquire_eeprom(struct em_hw *hw); static void em_release_eeprom(struct em_hw *hw); static void em_standby_eeprom(struct em_hw *hw); static int32_t em_set_vco_speed(struct em_hw *hw); static int32_t em_polarity_reversal_workaround(struct em_hw *hw); static int32_t em_set_phy_mode(struct em_hw *hw); static int32_t em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer); static uint8_t em_calculate_mng_checksum(char *buffer, uint32_t length); /* IGP cable length table */ static const uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; static const uint16_t em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = - { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, - 22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58, - 32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74, - 43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90, - 57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108, - 73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124, - 91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128, - 108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128}; - + { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, + 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, + 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, + 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, + 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, + 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, + 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, + 104, 109, 114, 118, 121, 124}; /****************************************************************************** * Set the phy type member in the hw struct. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_set_phy_type(struct em_hw *hw) { DEBUGFUNC("em_set_phy_type"); if(hw->mac_type == em_undefined) return -E1000_ERR_PHY_TYPE; switch(hw->phy_id) { case M88E1000_E_PHY_ID: case M88E1000_I_PHY_ID: case M88E1011_I_PHY_ID: case M88E1111_I_PHY_ID: hw->phy_type = em_phy_m88; break; case IGP01E1000_I_PHY_ID: if(hw->mac_type == em_82541 || hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547 || hw->mac_type == em_82547_rev_2) { hw->phy_type = em_phy_igp; break; } /* Fall Through */ default: /* Should never have loaded on this device */ hw->phy_type = em_phy_undefined; return -E1000_ERR_PHY_TYPE; } return E1000_SUCCESS; } /****************************************************************************** * IGP phy init script - initializes the GbE PHY * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static void em_phy_init_script(struct em_hw *hw) { uint32_t ret_val; uint16_t phy_saved_data; DEBUGFUNC("em_phy_init_script"); if(hw->phy_init_script) { msec_delay(20); /* Save off the current value of register 0x2F5B to be restored at * the end of this routine. */ ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); /* Disabled the PHY transmitter */ em_write_phy_reg(hw, 0x2F5B, 0x0003); msec_delay(20); em_write_phy_reg(hw,0x0000,0x0140); msec_delay(5); switch(hw->mac_type) { case em_82541: case em_82547: em_write_phy_reg(hw, 0x1F95, 0x0001); em_write_phy_reg(hw, 0x1F71, 0xBD21); em_write_phy_reg(hw, 0x1F79, 0x0018); em_write_phy_reg(hw, 0x1F30, 0x1600); em_write_phy_reg(hw, 0x1F31, 0x0014); em_write_phy_reg(hw, 0x1F32, 0x161C); em_write_phy_reg(hw, 0x1F94, 0x0003); em_write_phy_reg(hw, 0x1F96, 0x003F); em_write_phy_reg(hw, 0x2010, 0x0008); break; case em_82541_rev_2: case em_82547_rev_2: em_write_phy_reg(hw, 0x1F73, 0x0099); break; default: break; } em_write_phy_reg(hw, 0x0000, 0x3300); msec_delay(20); /* Now enable the transmitter */ em_write_phy_reg(hw, 0x2F5B, phy_saved_data); if(hw->mac_type == em_82547) { uint16_t fused, fine, coarse; /* Move to analog registers page */ em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; fine -= IGP01E1000_ANALOG_FUSE_FINE_1; } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) fine -= IGP01E1000_ANALOG_FUSE_FINE_10; fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); } } } } /****************************************************************************** * Set the mac type member in the hw struct. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_set_mac_type(struct em_hw *hw) { DEBUGFUNC("em_set_mac_type"); switch (hw->device_id) { case E1000_DEV_ID_82542: switch (hw->revision_id) { case E1000_82542_2_0_REV_ID: hw->mac_type = em_82542_rev2_0; break; case E1000_82542_2_1_REV_ID: hw->mac_type = em_82542_rev2_1; break; default: /* Invalid 82542 revision ID */ return -E1000_ERR_MAC_TYPE; } break; case E1000_DEV_ID_82543GC_FIBER: case E1000_DEV_ID_82543GC_COPPER: hw->mac_type = em_82543; break; case E1000_DEV_ID_82544EI_COPPER: case E1000_DEV_ID_82544EI_FIBER: case E1000_DEV_ID_82544GC_COPPER: case E1000_DEV_ID_82544GC_LOM: hw->mac_type = em_82544; break; case E1000_DEV_ID_82540EM: case E1000_DEV_ID_82540EM_LOM: case E1000_DEV_ID_82540EP: case E1000_DEV_ID_82540EP_LOM: case E1000_DEV_ID_82540EP_LP: hw->mac_type = em_82540; break; case E1000_DEV_ID_82545EM_COPPER: case E1000_DEV_ID_82545EM_FIBER: hw->mac_type = em_82545; break; case E1000_DEV_ID_82545GM_COPPER: case E1000_DEV_ID_82545GM_FIBER: case E1000_DEV_ID_82545GM_SERDES: hw->mac_type = em_82545_rev_3; break; case E1000_DEV_ID_82546EB_COPPER: case E1000_DEV_ID_82546EB_FIBER: case E1000_DEV_ID_82546EB_QUAD_COPPER: hw->mac_type = em_82546; break; case E1000_DEV_ID_82546GB_COPPER: case E1000_DEV_ID_82546GB_FIBER: case E1000_DEV_ID_82546GB_SERDES: case E1000_DEV_ID_82546GB_PCIE: case E1000_DEV_ID_82546GB_QUAD_COPPER: hw->mac_type = em_82546_rev_3; break; case E1000_DEV_ID_82541EI: case E1000_DEV_ID_82541ER_LOM: case E1000_DEV_ID_82541EI_MOBILE: hw->mac_type = em_82541; break; case E1000_DEV_ID_82541ER: case E1000_DEV_ID_82541GI: case E1000_DEV_ID_82541GI_LF: case E1000_DEV_ID_82541GI_MOBILE: hw->mac_type = em_82541_rev_2; break; case E1000_DEV_ID_82547EI: case E1000_DEV_ID_82547EI_MOBILE: hw->mac_type = em_82547; break; case E1000_DEV_ID_82547GI: hw->mac_type = em_82547_rev_2; break; + case E1000_DEV_ID_82571EB_COPPER: + case E1000_DEV_ID_82571EB_FIBER: + case E1000_DEV_ID_82571EB_SERDES: + hw->mac_type = em_82571; + break; + case E1000_DEV_ID_82572EI_COPPER: + case E1000_DEV_ID_82572EI_FIBER: + case E1000_DEV_ID_82572EI_SERDES: + hw->mac_type = em_82572; + break; case E1000_DEV_ID_82573E: case E1000_DEV_ID_82573E_IAMT: + case E1000_DEV_ID_82573L: hw->mac_type = em_82573; break; default: /* Should never have loaded on this device */ return -E1000_ERR_MAC_TYPE; } switch(hw->mac_type) { + case em_82571: + case em_82572: case em_82573: hw->eeprom_semaphore_present = TRUE; /* fall through */ case em_82541: case em_82547: case em_82541_rev_2: case em_82547_rev_2: hw->asf_firmware_present = TRUE; - break; default: - break; + break; } return E1000_SUCCESS; } /***************************************************************************** * Set media type and TBI compatibility. * * hw - Struct containing variables accessed by shared code * **************************************************************************/ void em_set_media_type(struct em_hw *hw) { uint32_t status; DEBUGFUNC("em_set_media_type"); if(hw->mac_type != em_82543) { /* tbi_compatibility is only valid on 82543 */ hw->tbi_compatibility_en = FALSE; } switch (hw->device_id) { case E1000_DEV_ID_82545GM_SERDES: case E1000_DEV_ID_82546GB_SERDES: + case E1000_DEV_ID_82571EB_SERDES: + case E1000_DEV_ID_82572EI_SERDES: hw->media_type = em_media_type_internal_serdes; break; default: - if(hw->mac_type >= em_82543) { - status = E1000_READ_REG(hw, STATUS); - if(status & E1000_STATUS_TBIMODE) { - hw->media_type = em_media_type_fiber; - /* tbi_compatibility not valid on fiber */ - hw->tbi_compatibility_en = FALSE; - } else { - hw->media_type = em_media_type_copper; - } - } else { - /* This is an 82542 (fiber only) */ - hw->media_type = em_media_type_fiber; + switch (hw->mac_type) { + case em_82542_rev2_0: + case em_82542_rev2_1: + hw->media_type = em_media_type_fiber; + break; + case em_82573: + /* + * The STATUS_TBIMODE bit is reserved or reused for + * this device. + */ + hw->media_type = em_media_type_copper; + break; + default: + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_TBIMODE) { + hw->media_type = em_media_type_fiber; + /* tbi_compatibility not valid on fiber */ + hw->tbi_compatibility_en = FALSE; + } else + hw->media_type = em_media_type_copper; } } } /****************************************************************************** * Reset the transmit and receive units; mask and clear all interrupts. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_reset_hw(struct em_hw *hw) { uint32_t ctrl; uint32_t ctrl_ext; uint32_t icr; uint32_t manc; uint32_t led_ctrl; uint32_t timeout; uint32_t extcnf_ctrl; int32_t ret_val; DEBUGFUNC("em_reset_hw"); /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ if(hw->mac_type == em_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); em_pci_clear_mwi(hw); } if(hw->bus_type == em_bus_type_pci_express) { /* Prevent the PCI-E bus from sticking if there is no TLP connection * on the last TLP read/write transaction when MAC is reset. */ if(em_disable_pciex_master(hw) != E1000_SUCCESS) { DEBUGOUT("PCI-E Master disable polling has failed.\n"); } } /* Clear interrupt mask to stop board from generating interrupts */ DEBUGOUT("Masking off all interrupts\n"); E1000_WRITE_REG(hw, IMC, 0xffffffff); /* Disable the Transmit and Receive units. Then delay to allow * any pending transactions to complete before we hit the MAC with * the global reset. */ E1000_WRITE_REG(hw, RCTL, 0); E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); E1000_WRITE_FLUSH(hw); /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ hw->tbi_compatibility_on = FALSE; /* Delay to allow any outstanding PCI transactions to complete before * resetting the device */ msec_delay(10); ctrl = E1000_READ_REG(hw, CTRL); /* Must reset the PHY before resetting the MAC */ if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); msec_delay(5); } /* Must acquire the MDIO ownership before MAC reset. * Ownership defaults to firmware after a reset. */ if(hw->mac_type == em_82573) { timeout = 10; extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; do { E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) break; else extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; msec_delay(2); timeout--; } while(timeout); } /* Issue a global reset to the MAC. This will reset the chip's * transmit, receive, DMA, and link units. It will not effect * the current PCI configuration. The global reset bit is self- * clearing, and should clear within a microsecond. */ DEBUGOUT("Issuing a global reset to MAC\n"); switch(hw->mac_type) { case em_82544: case em_82540: case em_82545: #ifndef __arm__ case em_82546: #endif case em_82541: case em_82541_rev_2: /* These controllers can't ack the 64-bit write when issuing the * reset, so use IO-mapping as a workaround to issue the reset */ E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); break; case em_82545_rev_3: case em_82546_rev_3: /* Reset is performed on a shadow of the control register */ E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); break; default: E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); break; } /* After MAC reset, force reload of EEPROM to restore power-on settings to * device. Later controllers reload the EEPROM automatically, so just wait * for reload to complete. */ switch(hw->mac_type) { case em_82542_rev2_0: case em_82542_rev2_1: case em_82543: case em_82544: /* Wait for reset to complete */ usec_delay(10); ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); ctrl_ext |= E1000_CTRL_EXT_EE_RST; E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); E1000_WRITE_FLUSH(hw); /* Wait for EEPROM reload */ msec_delay(2); break; case em_82541: case em_82541_rev_2: case em_82547: case em_82547_rev_2: /* Wait for EEPROM reload */ msec_delay(20); break; - case em_82573: - usec_delay(10); - ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - ctrl_ext |= E1000_CTRL_EXT_EE_RST; - E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); - E1000_WRITE_FLUSH(hw); - /* fall through */ - ret_val = em_get_auto_rd_done(hw); - if(ret_val) - /* We don't want to continue accessing MAC registers. */ - return ret_val; - break; - default: + case em_82573: + if (em_is_onboard_nvm_eeprom(hw) == FALSE) { + usec_delay(10); + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_EE_RST; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + } + /* fall through */ + case em_82571: + case em_82572: + ret_val = em_get_auto_rd_done(hw); + if(ret_val) + /* We don't want to continue accessing MAC registers. */ + return ret_val; + break; + default: /* Wait for EEPROM reload (it happens automatically) */ msec_delay(5); break; } /* Disable HW ARPs on ASF enabled adapters */ if(hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2) { manc = E1000_READ_REG(hw, MANC); manc &= ~(E1000_MANC_ARP_EN); E1000_WRITE_REG(hw, MANC, manc); } if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { em_phy_init_script(hw); /* Configure activity LED after PHY reset */ led_ctrl = E1000_READ_REG(hw, LEDCTL); led_ctrl &= IGP_ACTIVITY_LED_MASK; led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); E1000_WRITE_REG(hw, LEDCTL, led_ctrl); } /* Clear interrupt mask to stop board from generating interrupts */ DEBUGOUT("Masking off all interrupts\n"); E1000_WRITE_REG(hw, IMC, 0xffffffff); /* Clear any pending interrupt events. */ icr = E1000_READ_REG(hw, ICR); /* If MWI was previously enabled, reenable it. */ if(hw->mac_type == em_82542_rev2_0) { if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) em_pci_set_mwi(hw); } return E1000_SUCCESS; } /****************************************************************************** * Performs basic configuration of the adapter. * * hw - Struct containing variables accessed by shared code * * Assumes that the controller has previously been reset and is in a * post-reset uninitialized state. Initializes the receive address registers, * multicast table, and VLAN filter table. Calls routines to setup link * configuration and flow control settings. Clears all on-chip counters. Leaves * the transmit and receive units disabled and uninitialized. *****************************************************************************/ int32_t em_init_hw(struct em_hw *hw) { uint32_t ctrl; uint32_t i; int32_t ret_val; uint16_t pcix_cmd_word; uint16_t pcix_stat_hi_word; uint16_t cmd_mmrbc; uint16_t stat_mmrbc; uint32_t mta_size; DEBUGFUNC("em_init_hw"); /* Initialize Identification LED */ ret_val = em_id_led_init(hw); if(ret_val) { DEBUGOUT("Error Initializing Identification LED\n"); return ret_val; } /* Set the media type and TBI compatibility */ em_set_media_type(hw); /* Disabling VLAN filtering. */ DEBUGOUT("Initializing the IEEE VLAN\n"); if (hw->mac_type < em_82545_rev_3) E1000_WRITE_REG(hw, VET, 0); em_clear_vfta(hw); /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ if(hw->mac_type == em_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); em_pci_clear_mwi(hw); E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); E1000_WRITE_FLUSH(hw); msec_delay(5); } /* Setup the receive address. This involves initializing all of the Receive * Address Registers (RARs 0 - 15). */ em_init_rx_addrs(hw); /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ if(hw->mac_type == em_82542_rev2_0) { E1000_WRITE_REG(hw, RCTL, 0); E1000_WRITE_FLUSH(hw); msec_delay(1); if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) em_pci_set_mwi(hw); } /* Zero out the Multicast HASH table */ DEBUGOUT("Zeroing the MTA\n"); mta_size = E1000_MC_TBL_SIZE; for(i = 0; i < mta_size; i++) E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); /* Set the PCI priority bit correctly in the CTRL register. This * determines if the adapter gives priority to receives, or if it * gives equal priority to transmits and receives. Valid only on * 82542 and 82543 silicon. */ if(hw->dma_fairness && hw->mac_type <= em_82543) { ctrl = E1000_READ_REG(hw, CTRL); E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); } switch(hw->mac_type) { case em_82545_rev_3: case em_82546_rev_3: break; default: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ if(hw->bus_type == em_bus_type_pcix) { em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> PCIX_COMMAND_MMRBC_SHIFT; stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> PCIX_STATUS_HI_MMRBC_SHIFT; if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; if(cmd_mmrbc > stat_mmrbc) { pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); } } break; } /* Call a subroutine to configure the link and setup flow control. */ ret_val = em_setup_link(hw); /* Set the transmit descriptor write-back policy */ if(hw->mac_type > em_82544) { ctrl = E1000_READ_REG(hw, TXDCTL); ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; - switch (hw->mac_type) { - default: - break; + switch (hw->mac_type) { + case em_82571: + case em_82572: + ctrl |= (1 << 22); case em_82573: - ctrl |= E1000_TXDCTL_COUNT_DESC; - break; + ctrl |= E1000_TXDCTL_COUNT_DESC; + default: + break; } E1000_WRITE_REG(hw, TXDCTL, ctrl); } if (hw->mac_type == em_82573) { em_enable_tx_pkt_filtering(hw); } + switch (hw->mac_type) { + case em_82571: + case em_82572: + ctrl = E1000_READ_REG(hw, TXDCTL1); + ctrl &= ~E1000_TXDCTL_WTHRESH; + ctrl |= E1000_TXDCTL_COUNT_DESC | E1000_TXDCTL_FULL_TX_DESC_WB; + ctrl |= (1 << 22); + E1000_WRITE_REG(hw, TXDCTL1, ctrl); + default: + break; + } + + if (hw->mac_type == em_82573) { + uint32_t gcr = E1000_READ_REG(hw, GCR); + gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; + E1000_WRITE_REG(hw, GCR, gcr); + } /* Clear all of the statistics registers (clear on read). It is * important that we do this after we have tried to establish link * because the symbol error count will increment wildly if there * is no link. */ em_clear_hw_cntrs(hw); return ret_val; } /****************************************************************************** * Adjust SERDES output amplitude based on EEPROM setting. * * hw - Struct containing variables accessed by shared code. *****************************************************************************/ static int32_t em_adjust_serdes_amplitude(struct em_hw *hw) { uint16_t eeprom_data; int32_t ret_val; DEBUGFUNC("em_adjust_serdes_amplitude"); if(hw->media_type != em_media_type_internal_serdes) return E1000_SUCCESS; switch(hw->mac_type) { case em_82545_rev_3: case em_82546_rev_3: break; default: return E1000_SUCCESS; } ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); if (ret_val) { return ret_val; } if(eeprom_data != EEPROM_RESERVED_WORD) { /* Adjust SERDES output amplitude only. */ eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); if(ret_val) return ret_val; } return E1000_SUCCESS; } /****************************************************************************** * Configures flow control and link settings. * * hw - Struct containing variables accessed by shared code * * Determines which flow control settings to use. Calls the apropriate media- * specific link configuration function. Configures the flow control settings. * Assuming the adapter has a valid link partner, a valid link should be * established. Assumes the hardware has previously been reset and the * transmitter and receiver are not enabled. *****************************************************************************/ int32_t em_setup_link(struct em_hw *hw) { uint32_t ctrl_ext; int32_t ret_val; uint16_t eeprom_data; DEBUGFUNC("em_setup_link"); + /* In the case of the phy reset being blocked, we already have a link. + * We do not have to set it up again. */ + if (em_check_phy_reset_block(hw)) + return E1000_SUCCESS; + /* Read and store word 0x0F of the EEPROM. This word contains bits * that determine the hardware's default PAUSE (flow control) mode, * a bit that determines whether the HW defaults to enabling or * disabling auto-negotiation, and the direction of the * SW defined pins. If there is no SW over-ride of the flow * control setting, then the variable hw->fc will * be initialized based on a value in the EEPROM. */ - if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) { - DEBUGOUT("EEPROM Read Error\n"); - return -E1000_ERR_EEPROM; - } - - if(hw->fc == em_fc_default) { - if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) - hw->fc = em_fc_none; - else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == - EEPROM_WORD0F_ASM_DIR) - hw->fc = em_fc_tx_pause; - else - hw->fc = em_fc_full; + if (hw->fc == em_fc_default) { + switch (hw->mac_type) { + case em_82573: + hw->fc = em_fc_full; + break; + default: + ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, + 1, &eeprom_data); + if (ret_val) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + + if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) + hw->fc = em_fc_none; + else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == + EEPROM_WORD0F_ASM_DIR) + hw->fc = em_fc_tx_pause; + else + hw->fc = em_fc_full; + } } /* We want to save off the original Flow Control configuration just * in case we get disconnected and then reconnected into a different * hub or switch with different Flow Control capabilities. */ if(hw->mac_type == em_82542_rev2_0) hw->fc &= (~em_fc_tx_pause); if((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) hw->fc &= (~em_fc_rx_pause); hw->original_fc = hw->fc; DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); /* Take the 4 bits from EEPROM word 0x0F that determine the initial * polarity value for the SW controlled pins, and setup the * Extended Device Control reg with that info. * This is needed because one of the SW controlled pins is used for * signal detection. So this should be done before em_setup_pcs_link() * or em_phy_setup() is called. */ if(hw->mac_type == em_82543) { ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << SWDPIO__EXT_SHIFT); E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); } /* Call the necessary subroutine to configure the link. */ ret_val = (hw->media_type == em_media_type_copper) ? em_setup_copper_link(hw) : em_setup_fiber_serdes_link(hw); /* Initialize the flow control address, type, and PAUSE timer * registers to their default values. This is done even if flow * control is disabled, because it does not hurt anything to * initialize these registers. */ DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); /* Set the flow control receive threshold registers. Normally, * these registers will be set to a default threshold that may be * adjusted later by the driver's runtime code. However, if the * ability to transmit pause frames in not enabled, then these * registers will be set to 0. */ if(!(hw->fc & em_fc_tx_pause)) { E1000_WRITE_REG(hw, FCRTL, 0); E1000_WRITE_REG(hw, FCRTH, 0); } else { /* We need to set up the Receive Threshold high and low water marks * as well as (optionally) enabling the transmission of XON frames. */ if(hw->fc_send_xon) { E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); } else { E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); } } return ret_val; } /****************************************************************************** * Sets up link for a fiber based or serdes based adapter * * hw - Struct containing variables accessed by shared code * * Manipulates Physical Coding Sublayer functions in order to configure * link. Assumes the hardware has been previously reset and the transmitter * and receiver are not enabled. *****************************************************************************/ static int32_t em_setup_fiber_serdes_link(struct em_hw *hw) { uint32_t ctrl; uint32_t status; uint32_t txcw = 0; uint32_t i; uint32_t signal = 0; int32_t ret_val; DEBUGFUNC("em_setup_fiber_serdes_link"); + /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists + * until explicitly turned off or a power cycle is performed. A read to + * the register does not indicate its status. Therefore, we ensure + * loopback mode is disabled during initialization. + */ + if (hw->mac_type == em_82571 || hw->mac_type == em_82572) + E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); + /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be * set when the optics detect a signal. On older adapters, it will be * cleared when there is a signal. This applies to fiber media only. * If we're on serdes media, adjust the output amplitude to value set in * the EEPROM. */ ctrl = E1000_READ_REG(hw, CTRL); if(hw->media_type == em_media_type_fiber) signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; ret_val = em_adjust_serdes_amplitude(hw); if(ret_val) return ret_val; /* Take the link out of reset */ ctrl &= ~(E1000_CTRL_LRST); /* Adjust VCO speed to improve BER performance */ ret_val = em_set_vco_speed(hw); if(ret_val) return ret_val; em_config_collision_dist(hw); /* Check for a software override of the flow control settings, and setup * the device accordingly. If auto-negotiation is enabled, then software * will have to set the "PAUSE" bits to the correct value in the Tranmsit * Config Word Register (TXCW) and re-start auto-negotiation. However, if * auto-negotiation is disabled, then software will have to manually * configure the two flow control enable bits in the CTRL register. * * The possible values of the "fc" parameter are: * 0: Flow control is completely disabled * 1: Rx flow control is enabled (we can receive pause frames, but * not send pause frames). * 2: Tx flow control is enabled (we can send pause frames but we do * not support receiving pause frames). * 3: Both Rx and TX flow control (symmetric) are enabled. */ switch (hw->fc) { case em_fc_none: /* Flow control is completely disabled by a software over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); break; case em_fc_rx_pause: /* RX Flow control is enabled and TX Flow control is disabled by a * software over-ride. Since there really isn't a way to advertise * that we are capable of RX Pause ONLY, we will advertise that we * support both symmetric and asymmetric RX PAUSE. Later, we will * disable the adapter's ability to send PAUSE frames. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); break; case em_fc_tx_pause: /* TX Flow control is enabled, and RX Flow control is disabled, by a * software over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); break; case em_fc_full: /* Flow control (both RX and TX) is enabled by a software over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); break; default: DEBUGOUT("Flow control param set incorrectly\n"); return -E1000_ERR_CONFIG; break; } /* Since auto-negotiation is enabled, take the link out of reset (the link * will be in reset, because we previously reset the chip). This will * restart auto-negotiation. If auto-neogtiation is successful then the * link-up status bit will be set and the flow control enable bits (RFCE * and TFCE) will be set according to their negotiated value. */ DEBUGOUT("Auto-negotiation enabled\n"); E1000_WRITE_REG(hw, TXCW, txcw); E1000_WRITE_REG(hw, CTRL, ctrl); E1000_WRITE_FLUSH(hw); hw->txcw = txcw; msec_delay(1); /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" * indication in the Device Status Register. Time-out if a link isn't * seen in 500 milliseconds seconds (Auto-negotiation should complete in * less than 500 milliseconds even if the other end is doing it in SW). * For internal serdes, we just assume a signal is present, then poll. */ if(hw->media_type == em_media_type_internal_serdes || (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { DEBUGOUT("Looking for Link\n"); for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { msec_delay(10); status = E1000_READ_REG(hw, STATUS); if(status & E1000_STATUS_LU) break; } if(i == (LINK_UP_TIMEOUT / 10)) { DEBUGOUT("Never got a valid link from auto-neg!!!\n"); hw->autoneg_failed = 1; /* AutoNeg failed to achieve a link, so we'll call * em_check_for_link. This routine will force the link up if * we detect a signal. This will allow us to communicate with * non-autonegotiating link partners. */ ret_val = em_check_for_link(hw); if(ret_val) { DEBUGOUT("Error while checking for link\n"); return ret_val; } hw->autoneg_failed = 0; } else { hw->autoneg_failed = 0; DEBUGOUT("Valid Link Found\n"); } } else { DEBUGOUT("No Signal Detected\n"); } return E1000_SUCCESS; } /****************************************************************************** * Make sure we have a valid PHY and change PHY mode before link setup. * * hw - Struct containing variables accessed by shared code ******************************************************************************/ static int32_t em_copper_link_preconfig(struct em_hw *hw) { uint32_t ctrl; int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_copper_link_preconfig"); ctrl = E1000_READ_REG(hw, CTRL); /* With 82543, we need to force speed and duplex on the MAC equal to what * the PHY speed and duplex configuration is. In addition, we need to * perform a hardware reset on the PHY to take it out of reset. */ if(hw->mac_type > em_82543) { ctrl |= E1000_CTRL_SLU; ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); E1000_WRITE_REG(hw, CTRL, ctrl); } else { ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); E1000_WRITE_REG(hw, CTRL, ctrl); ret_val = em_phy_hw_reset(hw); if(ret_val) return ret_val; } /* Make sure we have a valid PHY */ ret_val = em_detect_gig_phy(hw); if(ret_val) { DEBUGOUT("Error, did not detect valid phy.\n"); return ret_val; } DEBUGOUT1("Phy ID = %x \n", hw->phy_id); /* Set PHY to class A mode (if necessary) */ ret_val = em_set_phy_mode(hw); if(ret_val) return ret_val; if((hw->mac_type == em_82545_rev_3) || (hw->mac_type == em_82546_rev_3)) { ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); phy_data |= 0x00000008; ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); } if(hw->mac_type <= em_82543 || hw->mac_type == em_82541 || hw->mac_type == em_82547 || hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) hw->phy_reset_disable = FALSE; return E1000_SUCCESS; } /******************************************************************** * Copper link setup for em_phy_igp series. * * hw - Struct containing variables accessed by shared code *********************************************************************/ static int32_t em_copper_link_igp_setup(struct em_hw *hw) { uint32_t led_ctrl; int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_copper_link_igp_setup"); if (hw->phy_reset_disable) return E1000_SUCCESS; ret_val = em_phy_reset(hw); if (ret_val) { DEBUGOUT("Error Resetting the PHY\n"); return ret_val; } /* Wait 10ms for MAC to configure PHY from eeprom settings */ msec_delay(15); /* Configure activity LED after PHY reset */ led_ctrl = E1000_READ_REG(hw, LEDCTL); led_ctrl &= IGP_ACTIVITY_LED_MASK; led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); E1000_WRITE_REG(hw, LEDCTL, led_ctrl); /* disable lplu d3 during driver init */ ret_val = em_set_d3_lplu_state(hw, FALSE); if (ret_val) { DEBUGOUT("Error Disabling LPLU D3\n"); return ret_val; } /* disable lplu d0 during driver init */ ret_val = em_set_d0_lplu_state(hw, FALSE); if (ret_val) { DEBUGOUT("Error Disabling LPLU D0\n"); return ret_val; } /* Configure mdi-mdix settings */ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); if (ret_val) return ret_val; if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { hw->dsp_config_state = em_dsp_config_disabled; /* Force MDI for earlier revs of the IGP PHY */ phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); hw->mdix = 1; } else { hw->dsp_config_state = em_dsp_config_enabled; phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; switch (hw->mdix) { case 1: phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; break; case 2: phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; break; case 0: default: phy_data |= IGP01E1000_PSCR_AUTO_MDIX; break; } } ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); if(ret_val) return ret_val; /* set auto-master slave resolution settings */ if(hw->autoneg) { em_ms_type phy_ms_setting = hw->master_slave; if(hw->ffe_config_state == em_ffe_config_active) hw->ffe_config_state = em_ffe_config_enabled; if(hw->dsp_config_state == em_dsp_config_activated) hw->dsp_config_state = em_dsp_config_enabled; /* when autonegotiation advertisment is only 1000Mbps then we * should disable SmartSpeed and enable Auto MasterSlave * resolution as hardware default. */ if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { /* Disable SmartSpeed */ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); if(ret_val) return ret_val; phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); if(ret_val) return ret_val; /* Set auto Master/Slave resolution process */ ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); if(ret_val) return ret_val; phy_data &= ~CR_1000T_MS_ENABLE; ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); if(ret_val) return ret_val; } ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); if(ret_val) return ret_val; /* load defaults for future use */ hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : em_ms_force_slave) : em_ms_auto; switch (phy_ms_setting) { case em_ms_force_master: phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); break; case em_ms_force_slave: phy_data |= CR_1000T_MS_ENABLE; phy_data &= ~(CR_1000T_MS_VALUE); break; case em_ms_auto: phy_data &= ~CR_1000T_MS_ENABLE; default: break; } ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); if(ret_val) return ret_val; } return E1000_SUCCESS; } /******************************************************************** * Copper link setup for em_phy_m88 series. * * hw - Struct containing variables accessed by shared code *********************************************************************/ static int32_t em_copper_link_mgp_setup(struct em_hw *hw) { int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_copper_link_mgp_setup"); if(hw->phy_reset_disable) return E1000_SUCCESS; /* Enable CRS on TX. This must be set for half-duplex operation. */ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); if(ret_val) return ret_val; phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; /* Options: * MDI/MDI-X = 0 (default) * 0 - Auto for all speeds * 1 - MDI mode * 2 - MDI-X mode * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) */ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; switch (hw->mdix) { case 1: phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; break; case 2: phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; break; case 3: phy_data |= M88E1000_PSCR_AUTO_X_1000T; break; case 0: default: phy_data |= M88E1000_PSCR_AUTO_X_MODE; break; } /* Options: * disable_polarity_correction = 0 (default) * Automatic Correction for Reversed Cable Polarity * 0 - Disabled * 1 - Enabled */ phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; if(hw->disable_polarity_correction == 1) phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); if(ret_val) return ret_val; /* Force TX_CLK in the Extended PHY Specific Control Register * to 25MHz clock. */ ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); if(ret_val) return ret_val; phy_data |= M88E1000_EPSCR_TX_CLK_25; if (hw->phy_revision < M88E1011_I_REV_4) { /* Configure Master and Slave downshift values */ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); if(ret_val) return ret_val; } /* SW Reset the PHY so all changes take effect */ ret_val = em_phy_reset(hw); if(ret_val) { DEBUGOUT("Error Resetting the PHY\n"); return ret_val; } return E1000_SUCCESS; } /******************************************************************** * Setup auto-negotiation and flow control advertisements, * and then perform auto-negotiation. * * hw - Struct containing variables accessed by shared code *********************************************************************/ static int32_t em_copper_link_autoneg(struct em_hw *hw) { int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_copper_link_autoneg"); /* Perform some bounds checking on the hw->autoneg_advertised * parameter. If this variable is zero, then set it to the default. */ hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; /* If autoneg_advertised is zero, we assume it was not defaulted * by the calling code so we set to advertise full capability. */ if(hw->autoneg_advertised == 0) hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); ret_val = em_phy_setup_autoneg(hw); if(ret_val) { DEBUGOUT("Error Setting up Auto-Negotiation\n"); return ret_val; } DEBUGOUT("Restarting Auto-Neg\n"); /* Restart auto-negotiation by setting the Auto Neg Enable bit and * the Auto Neg Restart bit in the PHY control register. */ ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); if(ret_val) return ret_val; phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); if(ret_val) return ret_val; /* Does the user want to wait for Auto-Neg to complete here, or * check at a later time (for example, callback routine). */ if(hw->wait_autoneg_complete) { ret_val = em_wait_autoneg(hw); if(ret_val) { DEBUGOUT("Error while waiting for autoneg to complete\n"); return ret_val; } } hw->get_link_status = TRUE; return E1000_SUCCESS; } /****************************************************************************** * Config the MAC and the PHY after link is up. * 1) Set up the MAC to the current PHY speed/duplex * if we are on 82543. If we * are on newer silicon, we only need to configure * collision distance in the Transmit Control Register. * 2) Set up flow control on the MAC to that established with * the link partner. * 3) Config DSP to improve Gigabit link quality for some PHY revisions. * * hw - Struct containing variables accessed by shared code ******************************************************************************/ static int32_t em_copper_link_postconfig(struct em_hw *hw) { int32_t ret_val; DEBUGFUNC("em_copper_link_postconfig"); if(hw->mac_type >= em_82544) { em_config_collision_dist(hw); } else { ret_val = em_config_mac_to_phy(hw); if(ret_val) { DEBUGOUT("Error configuring MAC to PHY settings\n"); return ret_val; } } ret_val = em_config_fc_after_link_up(hw); if(ret_val) { DEBUGOUT("Error Configuring Flow Control\n"); return ret_val; } /* Config DSP to improve Giga link quality */ if(hw->phy_type == em_phy_igp) { ret_val = em_config_dsp_after_link_change(hw, TRUE); if(ret_val) { DEBUGOUT("Error Configuring DSP after link up\n"); return ret_val; } } return E1000_SUCCESS; } /****************************************************************************** * Detects which PHY is present and setup the speed and duplex * * hw - Struct containing variables accessed by shared code ******************************************************************************/ static int32_t em_setup_copper_link(struct em_hw *hw) { int32_t ret_val; uint16_t i; uint16_t phy_data; DEBUGFUNC("em_setup_copper_link"); /* Check if it is a valid PHY and set PHY mode if necessary. */ ret_val = em_copper_link_preconfig(hw); if(ret_val) return ret_val; if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) { ret_val = em_copper_link_igp_setup(hw); if(ret_val) return ret_val; } else if (hw->phy_type == em_phy_m88) { ret_val = em_copper_link_mgp_setup(hw); if(ret_val) return ret_val; } if(hw->autoneg) { /* Setup autoneg and flow control advertisement * and perform autonegotiation */ ret_val = em_copper_link_autoneg(hw); if(ret_val) return ret_val; } else { /* PHY will be set to 10H, 10F, 100H,or 100F * depending on value from forced_speed_duplex. */ DEBUGOUT("Forcing speed and duplex\n"); ret_val = em_phy_force_speed_duplex(hw); if(ret_val) { DEBUGOUT("Error Forcing Speed and Duplex\n"); return ret_val; } } /* Check link status. Wait up to 100 microseconds for link to become * valid. */ for(i = 0; i < 10; i++) { ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); if(ret_val) return ret_val; if(phy_data & MII_SR_LINK_STATUS) { /* Config the MAC and PHY after link is up */ ret_val = em_copper_link_postconfig(hw); if(ret_val) return ret_val; DEBUGOUT("Valid link established!!!\n"); return E1000_SUCCESS; } usec_delay(10); } DEBUGOUT("Unable to establish link!!!\n"); return E1000_SUCCESS; } /****************************************************************************** * Configures PHY autoneg and flow control advertisement settings * * hw - Struct containing variables accessed by shared code ******************************************************************************/ int32_t em_phy_setup_autoneg(struct em_hw *hw) { int32_t ret_val; uint16_t mii_autoneg_adv_reg; uint16_t mii_1000t_ctrl_reg; DEBUGFUNC("em_phy_setup_autoneg"); /* Read the MII Auto-Neg Advertisement Register (Address 4). */ ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); if(ret_val) return ret_val; /* Read the MII 1000Base-T Control Register (Address 9). */ ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); if(ret_val) return ret_val; /* Need to parse both autoneg_advertised and fc and set up * the appropriate PHY registers. First we will parse for * autoneg_advertised software override. Since we can advertise * a plethora of combinations, we need to check each bit * individually. */ /* First we clear all the 10/100 mb speed bits in the Auto-Neg * Advertisement Register (Address 4) and the 1000 mb speed bits in * the 1000Base-T Control Register (Address 9). */ mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); /* Do we want to advertise 10 Mb Half Duplex? */ if(hw->autoneg_advertised & ADVERTISE_10_HALF) { DEBUGOUT("Advertise 10mb Half duplex\n"); mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; } /* Do we want to advertise 10 Mb Full Duplex? */ if(hw->autoneg_advertised & ADVERTISE_10_FULL) { DEBUGOUT("Advertise 10mb Full duplex\n"); mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; } /* Do we want to advertise 100 Mb Half Duplex? */ if(hw->autoneg_advertised & ADVERTISE_100_HALF) { DEBUGOUT("Advertise 100mb Half duplex\n"); mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; } /* Do we want to advertise 100 Mb Full Duplex? */ if(hw->autoneg_advertised & ADVERTISE_100_FULL) { DEBUGOUT("Advertise 100mb Full duplex\n"); mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; } /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); } /* Do we want to advertise 1000 Mb Full Duplex? */ if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { DEBUGOUT("Advertise 1000mb Full duplex\n"); mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; } /* Check for a software override of the flow control settings, and * setup the PHY advertisement registers accordingly. If * auto-negotiation is enabled, then software will have to set the * "PAUSE" bits to the correct value in the Auto-Negotiation * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. * * The possible values of the "fc" parameter are: * 0: Flow control is completely disabled * 1: Rx flow control is enabled (we can receive pause frames * but not send pause frames). * 2: Tx flow control is enabled (we can send pause frames * but we do not support receiving pause frames). * 3: Both Rx and TX flow control (symmetric) are enabled. * other: No software override. The flow control configuration * in the EEPROM is used. */ switch (hw->fc) { case em_fc_none: /* 0 */ /* Flow control (RX & TX) is completely disabled by a * software over-ride. */ mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); break; case em_fc_rx_pause: /* 1 */ /* RX Flow control is enabled, and TX Flow control is * disabled, by a software over-ride. */ /* Since there really isn't a way to advertise that we are * capable of RX Pause ONLY, we will advertise that we * support both symmetric and asymmetric RX PAUSE. Later * (in em_config_fc_after_link_up) we will disable the *hw's ability to send PAUSE frames. */ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); break; case em_fc_tx_pause: /* 2 */ /* TX Flow control is enabled, and RX Flow control is * disabled, by a software over-ride. */ mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; break; case em_fc_full: /* 3 */ /* Flow control (both RX and TX) is enabled by a software * over-ride. */ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); break; default: DEBUGOUT("Flow control param set incorrectly\n"); return -E1000_ERR_CONFIG; } ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); if(ret_val) return ret_val; DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); if(ret_val) return ret_val; return E1000_SUCCESS; } /****************************************************************************** * Force PHY speed and duplex settings to hw->forced_speed_duplex * * hw - Struct containing variables accessed by shared code ******************************************************************************/ static int32_t em_phy_force_speed_duplex(struct em_hw *hw) { uint32_t ctrl; int32_t ret_val; uint16_t mii_ctrl_reg; uint16_t mii_status_reg; uint16_t phy_data; uint16_t i; DEBUGFUNC("em_phy_force_speed_duplex"); /* Turn off Flow control if we are forcing speed and duplex. */ hw->fc = em_fc_none; DEBUGOUT1("hw->fc = %d\n", hw->fc); /* Read the Device Control Register. */ ctrl = E1000_READ_REG(hw, CTRL); /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ctrl &= ~(DEVICE_SPEED_MASK); /* Clear the Auto Speed Detect Enable bit. */ ctrl &= ~E1000_CTRL_ASDE; /* Read the MII Control Register. */ ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); if(ret_val) return ret_val; /* We need to disable autoneg in order to force link and duplex. */ mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; /* Are we forcing Full or Half Duplex? */ if(hw->forced_speed_duplex == em_100_full || hw->forced_speed_duplex == em_10_full) { /* We want to force full duplex so we SET the full duplex bits in the * Device and MII Control Registers. */ ctrl |= E1000_CTRL_FD; mii_ctrl_reg |= MII_CR_FULL_DUPLEX; DEBUGOUT("Full Duplex\n"); } else { /* We want to force half duplex so we CLEAR the full duplex bits in * the Device and MII Control Registers. */ ctrl &= ~E1000_CTRL_FD; mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; DEBUGOUT("Half Duplex\n"); } /* Are we forcing 100Mbps??? */ if(hw->forced_speed_duplex == em_100_full || hw->forced_speed_duplex == em_100_half) { /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ ctrl |= E1000_CTRL_SPD_100; mii_ctrl_reg |= MII_CR_SPEED_100; mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); DEBUGOUT("Forcing 100mb "); } else { /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); mii_ctrl_reg |= MII_CR_SPEED_10; mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); DEBUGOUT("Forcing 10mb "); } em_config_collision_dist(hw); /* Write the configured values back to the Device Control Reg. */ E1000_WRITE_REG(hw, CTRL, ctrl); if (hw->phy_type == em_phy_m88) { ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); if(ret_val) return ret_val; /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI * forced whenever speed are duplex are forced. */ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); if(ret_val) return ret_val; DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); /* Need to reset the PHY or these changes will be ignored */ mii_ctrl_reg |= MII_CR_RESET; } else { /* Clear Auto-Crossover to force MDI manually. IGP requires MDI * forced whenever speed or duplex are forced. */ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); if(ret_val) return ret_val; phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); if(ret_val) return ret_val; } /* Write back the modified PHY MII control register. */ ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); if(ret_val) return ret_val; usec_delay(1); /* The wait_autoneg_complete flag may be a little misleading here. * Since we are forcing speed and duplex, Auto-Neg is not enabled. * But we do want to delay for a period while forcing only so we * don't generate false No Link messages. So we will wait here * only if the user has set wait_autoneg_complete to 1, which is * the default. */ if(hw->wait_autoneg_complete) { /* We will wait for autoneg to complete. */ DEBUGOUT("Waiting for forced speed/duplex link.\n"); mii_status_reg = 0; /* We will wait for autoneg to complete or 4.5 seconds to expire. */ for(i = PHY_FORCE_TIME; i > 0; i--) { /* Read the MII Status Register and wait for Auto-Neg Complete bit * to be set. */ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); if(ret_val) return ret_val; if(mii_status_reg & MII_SR_LINK_STATUS) break; msec_delay(100); } if((i == 0) && (hw->phy_type == em_phy_m88)) { /* We didn't get link. Reset the DSP and wait again for link. */ ret_val = em_phy_reset_dsp(hw); if(ret_val) { DEBUGOUT("Error Resetting PHY DSP\n"); return ret_val; } } /* This loop will early-out if the link condition has been met. */ for(i = PHY_FORCE_TIME; i > 0; i--) { if(mii_status_reg & MII_SR_LINK_STATUS) break; msec_delay(100); /* Read the MII Status Register and wait for Auto-Neg Complete bit * to be set. */ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); if(ret_val) return ret_val; } } if (hw->phy_type == em_phy_m88) { /* Because we reset the PHY above, we need to re-force TX_CLK in the * Extended PHY Specific Control Register to 25MHz clock. This value * defaults back to a 2.5MHz clock when the PHY is reset. */ ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); if(ret_val) return ret_val; phy_data |= M88E1000_EPSCR_TX_CLK_25; ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); if(ret_val) return ret_val; /* In addition, because of the s/w reset above, we need to enable CRS on * TX. This must be set for both full and half duplex operation. */ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); if(ret_val) return ret_val; phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); if(ret_val) return ret_val; if((hw->mac_type == em_82544 || hw->mac_type == em_82543) && (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || hw->forced_speed_duplex == em_10_half)) { ret_val = em_polarity_reversal_workaround(hw); if(ret_val) return ret_val; } } return E1000_SUCCESS; } /****************************************************************************** * Sets the collision distance in the Transmit Control register * * hw - Struct containing variables accessed by shared code * * Link should have been established previously. Reads the speed and duplex * information from the Device Status register. ******************************************************************************/ void em_config_collision_dist(struct em_hw *hw) { uint32_t tctl; DEBUGFUNC("em_config_collision_dist"); tctl = E1000_READ_REG(hw, TCTL); tctl &= ~E1000_TCTL_COLD; tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; E1000_WRITE_REG(hw, TCTL, tctl); E1000_WRITE_FLUSH(hw); } /****************************************************************************** * Sets MAC speed and duplex settings to reflect the those in the PHY * * hw - Struct containing variables accessed by shared code * mii_reg - data to write to the MII control register * * The contents of the PHY register containing the needed information need to * be passed in. ******************************************************************************/ static int32_t em_config_mac_to_phy(struct em_hw *hw) { uint32_t ctrl; int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_config_mac_to_phy"); /* 82544 or newer MAC, Auto Speed Detection takes care of * MAC speed/duplex configuration.*/ if (hw->mac_type >= em_82544) return E1000_SUCCESS; /* Read the Device Control Register and set the bits to Force Speed * and Duplex. */ ctrl = E1000_READ_REG(hw, CTRL); ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); /* Set up duplex in the Device Control and Transmit Control * registers depending on negotiated values. */ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); if(ret_val) return ret_val; if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD; else ctrl &= ~E1000_CTRL_FD; em_config_collision_dist(hw); /* Set up speed in the Device Control register depending on * negotiated values. */ if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) ctrl |= E1000_CTRL_SPD_1000; else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) ctrl |= E1000_CTRL_SPD_100; /* Write the configured values back to the Device Control Reg. */ E1000_WRITE_REG(hw, CTRL, ctrl); return E1000_SUCCESS; } /****************************************************************************** * Forces the MAC's flow control settings. * * hw - Struct containing variables accessed by shared code * * Sets the TFCE and RFCE bits in the device control register to reflect * the adapter settings. TFCE and RFCE need to be explicitly set by * software when a Copper PHY is used because autonegotiation is managed * by the PHY rather than the MAC. Software must also configure these * bits when link is forced on a fiber connection. *****************************************************************************/ int32_t em_force_mac_fc(struct em_hw *hw) { uint32_t ctrl; DEBUGFUNC("em_force_mac_fc"); /* Get the current configuration of the Device Control Register */ ctrl = E1000_READ_REG(hw, CTRL); /* Because we didn't get link via the internal auto-negotiation * mechanism (we either forced link or we got link via PHY * auto-neg), we have to manually enable/disable transmit an * receive flow control. * * The "Case" statement below enables/disable flow control * according to the "hw->fc" parameter. * * The possible values of the "fc" parameter are: * 0: Flow control is completely disabled * 1: Rx flow control is enabled (we can receive pause * frames but not send pause frames). * 2: Tx flow control is enabled (we can send pause frames * frames but we do not receive pause frames). * 3: Both Rx and TX flow control (symmetric) is enabled. * other: No other values should be possible at this point. */ switch (hw->fc) { case em_fc_none: ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); break; case em_fc_rx_pause: ctrl &= (~E1000_CTRL_TFCE); ctrl |= E1000_CTRL_RFCE; break; case em_fc_tx_pause: ctrl &= (~E1000_CTRL_RFCE); ctrl |= E1000_CTRL_TFCE; break; case em_fc_full: ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); break; default: DEBUGOUT("Flow control param set incorrectly\n"); return -E1000_ERR_CONFIG; } /* Disable TX Flow Control for 82542 (rev 2.0) */ if(hw->mac_type == em_82542_rev2_0) ctrl &= (~E1000_CTRL_TFCE); E1000_WRITE_REG(hw, CTRL, ctrl); return E1000_SUCCESS; } /****************************************************************************** * Configures flow control settings after link is established * * hw - Struct containing variables accessed by shared code * * Should be called immediately after a valid link has been established. * Forces MAC flow control settings if link was forced. When in MII/GMII mode * and autonegotiation is enabled, the MAC flow control settings will be set * based on the flow control negotiated by the PHY. In TBI mode, the TFCE * and RFCE bits will be automaticaly set to the negotiated flow control mode. *****************************************************************************/ int32_t em_config_fc_after_link_up(struct em_hw *hw) { int32_t ret_val; uint16_t mii_status_reg; uint16_t mii_nway_adv_reg; uint16_t mii_nway_lp_ability_reg; uint16_t speed; uint16_t duplex; DEBUGFUNC("em_config_fc_after_link_up"); /* Check for the case where we have fiber media and auto-neg failed * so we had to force link. In this case, we need to force the * configuration of the MAC to match the "fc" parameter. */ if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) || ((hw->media_type == em_media_type_internal_serdes) && (hw->autoneg_failed)) || ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) { ret_val = em_force_mac_fc(hw); if(ret_val) { DEBUGOUT("Error forcing flow control settings\n"); return ret_val; } } /* Check for the case where we have copper media and auto-neg is * enabled. In this case, we need to check and see if Auto-Neg * has completed, and if so, how the PHY and link partner has * flow control configured. */ if((hw->media_type == em_media_type_copper) && hw->autoneg) { /* Read the MII Status Register and check to see if AutoNeg * has completed. We read this twice because this reg has * some "sticky" (latched) bits. */ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); if(ret_val) return ret_val; if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { /* The AutoNeg process has completed, so we now need to * read both the Auto Negotiation Advertisement Register * (Address 4) and the Auto_Negotiation Base Page Ability * Register (Address 5) to determine how flow control was * negotiated. */ ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); if(ret_val) return ret_val; /* Two bits in the Auto Negotiation Advertisement Register * (Address 4) and two bits in the Auto Negotiation Base * Page Ability Register (Address 5) determine flow control * for both the PHY and the link partner. The following * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, * 1999, describes these PAUSE resolution bits and how flow * control is determined based upon these settings. * NOTE: DC = Don't Care * * LOCAL DEVICE | LINK PARTNER * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution *-------|---------|-------|---------|-------------------- * 0 | 0 | DC | DC | em_fc_none * 0 | 1 | 0 | DC | em_fc_none * 0 | 1 | 1 | 0 | em_fc_none * 0 | 1 | 1 | 1 | em_fc_tx_pause * 1 | 0 | 0 | DC | em_fc_none * 1 | DC | 1 | DC | em_fc_full * 1 | 1 | 0 | 0 | em_fc_none * 1 | 1 | 0 | 1 | em_fc_rx_pause * */ /* Are both PAUSE bits set to 1? If so, this implies * Symmetric Flow Control is enabled at both ends. The * ASM_DIR bits are irrelevant per the spec. * * For Symmetric Flow Control: * * LOCAL DEVICE | LINK PARTNER * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result *-------|---------|-------|---------|-------------------- * 1 | DC | 1 | DC | em_fc_full * */ if((mii_nway_adv_reg & NWAY_AR_PAUSE) && (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { /* Now we need to check if the user selected RX ONLY * of pause frames. In this case, we had to advertise * FULL flow control because we could not advertise RX * ONLY. Hence, we must now check to see if we need to * turn OFF the TRANSMISSION of PAUSE frames. */ if(hw->original_fc == em_fc_full) { hw->fc = em_fc_full; DEBUGOUT("Flow Control = FULL.\r\n"); } else { hw->fc = em_fc_rx_pause; DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); } } /* For receiving PAUSE frames ONLY. * * LOCAL DEVICE | LINK PARTNER * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result *-------|---------|-------|---------|-------------------- * 0 | 1 | 1 | 1 | em_fc_tx_pause * */ else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { hw->fc = em_fc_tx_pause; DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); } /* For transmitting PAUSE frames ONLY. * * LOCAL DEVICE | LINK PARTNER * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result *-------|---------|-------|---------|-------------------- * 1 | 1 | 0 | 1 | em_fc_rx_pause * */ else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { hw->fc = em_fc_rx_pause; DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); } /* Per the IEEE spec, at this point flow control should be * disabled. However, we want to consider that we could * be connected to a legacy switch that doesn't advertise * desired flow control, but can be forced on the link * partner. So if we advertised no flow control, that is * what we will resolve to. If we advertised some kind of * receive capability (Rx Pause Only or Full Flow Control) * and the link partner advertised none, we will configure * ourselves to enable Rx Flow Control only. We can do * this safely for two reasons: If the link partner really * didn't want flow control enabled, and we enable Rx, no * harm done since we won't be receiving any PAUSE frames * anyway. If the intent on the link partner was to have * flow control enabled, then by us enabling RX only, we * can at least receive pause frames and process them. * This is a good idea because in most cases, since we are * predominantly a server NIC, more times than not we will * be asked to delay transmission of packets than asking * our link partner to pause transmission of frames. */ else if((hw->original_fc == em_fc_none || hw->original_fc == em_fc_tx_pause) || hw->fc_strict_ieee) { hw->fc = em_fc_none; DEBUGOUT("Flow Control = NONE.\r\n"); } else { hw->fc = em_fc_rx_pause; DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); } /* Now we need to do one last check... If we auto- * negotiated to HALF DUPLEX, flow control should not be * enabled per IEEE 802.3 spec. */ ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); if(ret_val) { DEBUGOUT("Error getting link speed and duplex\n"); return ret_val; } if(duplex == HALF_DUPLEX) hw->fc = em_fc_none; /* Now we call a subroutine to actually force the MAC * controller to use the correct flow control settings. */ ret_val = em_force_mac_fc(hw); if(ret_val) { DEBUGOUT("Error forcing flow control settings\n"); return ret_val; } } else { DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n"); } } return E1000_SUCCESS; } /****************************************************************************** * Checks to see if the link status of the hardware has changed. * * hw - Struct containing variables accessed by shared code * * Called by any function that needs to check the link status of the adapter. *****************************************************************************/ int32_t em_check_for_link(struct em_hw *hw) { uint32_t rxcw = 0; uint32_t ctrl; uint32_t status; uint32_t rctl; uint32_t icr; uint32_t signal = 0; int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_check_for_link"); ctrl = E1000_READ_REG(hw, CTRL); status = E1000_READ_REG(hw, STATUS); /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be * set when the optics detect a signal. On older adapters, it will be * cleared when there is a signal. This applies to fiber media only. */ if((hw->media_type == em_media_type_fiber) || (hw->media_type == em_media_type_internal_serdes)) { rxcw = E1000_READ_REG(hw, RXCW); if(hw->media_type == em_media_type_fiber) { signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; if(status & E1000_STATUS_LU) hw->get_link_status = FALSE; } } /* If we have a copper PHY then we only want to go out to the PHY * registers to see if Auto-Neg has completed and/or if our link * status has changed. The get_link_status flag will be set if we * receive a Link Status Change interrupt or we have Rx Sequence * Errors. */ if((hw->media_type == em_media_type_copper) && hw->get_link_status) { /* First we want to see if the MII Status Register reports * link. If so, then we want to get the current speed/duplex * of the PHY. * Read the register twice since the link bit is sticky. */ ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); if(ret_val) return ret_val; if(phy_data & MII_SR_LINK_STATUS) { hw->get_link_status = FALSE; /* Check if there was DownShift, must be checked immediately after * link-up */ em_check_downshift(hw); /* If we are on 82544 or 82543 silicon and speed/duplex * are forced to 10H or 10F, then we will implement the polarity * reversal workaround. We disable interrupts first, and upon * returning, place the devices interrupt state to its previous * value except for the link status change interrupt which will * happen due to the execution of this workaround. */ if((hw->mac_type == em_82544 || hw->mac_type == em_82543) && (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || hw->forced_speed_duplex == em_10_half)) { E1000_WRITE_REG(hw, IMC, 0xffffffff); ret_val = em_polarity_reversal_workaround(hw); icr = E1000_READ_REG(hw, ICR); E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); } } else { /* No link detected */ em_config_dsp_after_link_change(hw, FALSE); return 0; } /* If we are forcing speed/duplex, then we simply return since * we have already determined whether we have link or not. */ if(!hw->autoneg) return -E1000_ERR_CONFIG; /* optimize the dsp settings for the igp phy */ em_config_dsp_after_link_change(hw, TRUE); /* We have a M88E1000 PHY and Auto-Neg is enabled. If we * have Si on board that is 82544 or newer, Auto * Speed Detection takes care of MAC speed/duplex * configuration. So we only need to configure Collision * Distance in the MAC. Otherwise, we need to force * speed/duplex on the MAC to the current PHY speed/duplex * settings. */ if(hw->mac_type >= em_82544) em_config_collision_dist(hw); else { ret_val = em_config_mac_to_phy(hw); if(ret_val) { DEBUGOUT("Error configuring MAC to PHY settings\n"); return ret_val; } } /* Configure Flow Control now that Auto-Neg has completed. First, we * need to restore the desired flow control settings because we may * have had to re-autoneg with a different link partner. */ ret_val = em_config_fc_after_link_up(hw); if(ret_val) { DEBUGOUT("Error configuring flow control\n"); return ret_val; } /* At this point we know that we are on copper and we have * auto-negotiated link. These are conditions for checking the link * partner capability register. We use the link speed to determine if * TBI compatibility needs to be turned on or off. If the link is not * at gigabit speed, then TBI compatibility is not needed. If we are * at gigabit speed, we turn on TBI compatibility. */ if(hw->tbi_compatibility_en) { uint16_t speed, duplex; em_get_speed_and_duplex(hw, &speed, &duplex); if(speed != SPEED_1000) { /* If link speed is not set to gigabit speed, we do not need * to enable TBI compatibility. */ if(hw->tbi_compatibility_on) { /* If we previously were in the mode, turn it off. */ rctl = E1000_READ_REG(hw, RCTL); rctl &= ~E1000_RCTL_SBP; E1000_WRITE_REG(hw, RCTL, rctl); hw->tbi_compatibility_on = FALSE; } } else { /* If TBI compatibility is was previously off, turn it on. For * compatibility with a TBI link partner, we will store bad * packets. Some frames have an additional byte on the end and * will look like CRC errors to to the hardware. */ if(!hw->tbi_compatibility_on) { hw->tbi_compatibility_on = TRUE; rctl = E1000_READ_REG(hw, RCTL); rctl |= E1000_RCTL_SBP; E1000_WRITE_REG(hw, RCTL, rctl); } } } } /* If we don't have link (auto-negotiation failed or link partner cannot * auto-negotiate), the cable is plugged in (we have signal), and our * link partner is not trying to auto-negotiate with us (we are receiving * idles or data), we need to force link up. We also need to give * auto-negotiation time to complete, in case the cable was just plugged * in. The autoneg_failed flag does this. */ else if((((hw->media_type == em_media_type_fiber) && ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || (hw->media_type == em_media_type_internal_serdes)) && (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { if(hw->autoneg_failed == 0) { hw->autoneg_failed = 1; return 0; } DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); /* Disable auto-negotiation in the TXCW register */ E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); /* Force link-up and also force full-duplex. */ ctrl = E1000_READ_REG(hw, CTRL); ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); E1000_WRITE_REG(hw, CTRL, ctrl); /* Configure Flow Control after forcing link up. */ ret_val = em_config_fc_after_link_up(hw); if(ret_val) { DEBUGOUT("Error configuring flow control\n"); return ret_val; } } /* If we are forcing link and we are receiving /C/ ordered sets, re-enable * auto-negotiation in the TXCW register and disable forced link in the * Device Control register in an attempt to auto-negotiate with our link * partner. */ else if(((hw->media_type == em_media_type_fiber) || (hw->media_type == em_media_type_internal_serdes)) && (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); E1000_WRITE_REG(hw, TXCW, hw->txcw); E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); hw->serdes_link_down = FALSE; } /* If we force link for non-auto-negotiation switch, check link status * based on MAC synchronization for internal serdes media type. */ else if((hw->media_type == em_media_type_internal_serdes) && !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { /* SYNCH bit and IV bit are sticky. */ usec_delay(10); if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { if(!(rxcw & E1000_RXCW_IV)) { hw->serdes_link_down = FALSE; DEBUGOUT("SERDES: Link is up.\n"); } } else { hw->serdes_link_down = TRUE; DEBUGOUT("SERDES: Link is down.\n"); } } if((hw->media_type == em_media_type_internal_serdes) && (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); } return E1000_SUCCESS; } /****************************************************************************** * Detects the current speed and duplex settings of the hardware. * * hw - Struct containing variables accessed by shared code * speed - Speed of the connection * duplex - Duplex setting of the connection *****************************************************************************/ int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) { uint32_t status; int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_get_speed_and_duplex"); if(hw->mac_type >= em_82543) { status = E1000_READ_REG(hw, STATUS); if(status & E1000_STATUS_SPEED_1000) { *speed = SPEED_1000; DEBUGOUT("1000 Mbs, "); } else if(status & E1000_STATUS_SPEED_100) { *speed = SPEED_100; DEBUGOUT("100 Mbs, "); } else { *speed = SPEED_10; DEBUGOUT("10 Mbs, "); } if(status & E1000_STATUS_FD) { *duplex = FULL_DUPLEX; DEBUGOUT("Full Duplex\r\n"); } else { *duplex = HALF_DUPLEX; DEBUGOUT(" Half Duplex\r\n"); } } else { DEBUGOUT("1000 Mbs, Full Duplex\r\n"); *speed = SPEED_1000; *duplex = FULL_DUPLEX; } /* IGP01 PHY may advertise full duplex operation after speed downgrade even * if it is operating at half duplex. Here we set the duplex settings to * match the duplex in the link partner's capabilities. */ if(hw->phy_type == em_phy_igp && hw->speed_downgraded) { ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); if(ret_val) return ret_val; if(!(phy_data & NWAY_ER_LP_NWAY_CAPS)) *duplex = HALF_DUPLEX; else { ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); if(ret_val) return ret_val; if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) *duplex = HALF_DUPLEX; } } return E1000_SUCCESS; } /****************************************************************************** * Blocks until autoneg completes or times out (~4.5 seconds) * * hw - Struct containing variables accessed by shared code ******************************************************************************/ int32_t em_wait_autoneg(struct em_hw *hw) { int32_t ret_val; uint16_t i; uint16_t phy_data; DEBUGFUNC("em_wait_autoneg"); DEBUGOUT("Waiting for Auto-Neg to complete.\n"); /* We will wait for autoneg to complete or 4.5 seconds to expire. */ for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { /* Read the MII Status Register and wait for Auto-Neg * Complete bit to be set. */ ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); if(ret_val) return ret_val; if(phy_data & MII_SR_AUTONEG_COMPLETE) { return E1000_SUCCESS; } msec_delay(100); } return E1000_SUCCESS; } /****************************************************************************** * Raises the Management Data Clock * * hw - Struct containing variables accessed by shared code * ctrl - Device control register's current value ******************************************************************************/ static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) { /* Raise the clock input to the Management Data Clock (by setting the MDC * bit), and then delay 10 microseconds. */ E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); E1000_WRITE_FLUSH(hw); usec_delay(10); } /****************************************************************************** * Lowers the Management Data Clock * * hw - Struct containing variables accessed by shared code * ctrl - Device control register's current value ******************************************************************************/ static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) { /* Lower the clock input to the Management Data Clock (by clearing the MDC * bit), and then delay 10 microseconds. */ E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); E1000_WRITE_FLUSH(hw); usec_delay(10); } /****************************************************************************** * Shifts data bits out to the PHY * * hw - Struct containing variables accessed by shared code * data - Data to send out to the PHY * count - Number of bits to shift out * * Bits are shifted out in MSB to LSB order. ******************************************************************************/ static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) { uint32_t ctrl; uint32_t mask; /* We need to shift "count" number of bits out to the PHY. So, the value * in the "data" parameter will be shifted out to the PHY one bit at a * time. In order to do this, "data" must be broken down into bits. */ mask = 0x01; mask <<= (count - 1); ctrl = E1000_READ_REG(hw, CTRL); /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); while(mask) { /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and * then raising and lowering the Management Data Clock. A "0" is * shifted out to the PHY by setting the MDIO bit to "0" and then * raising and lowering the clock. */ if(data & mask) ctrl |= E1000_CTRL_MDIO; else ctrl &= ~E1000_CTRL_MDIO; E1000_WRITE_REG(hw, CTRL, ctrl); E1000_WRITE_FLUSH(hw); usec_delay(10); em_raise_mdi_clk(hw, &ctrl); em_lower_mdi_clk(hw, &ctrl); mask = mask >> 1; } } /****************************************************************************** * Shifts data bits in from the PHY * * hw - Struct containing variables accessed by shared code * * Bits are shifted in in MSB to LSB order. ******************************************************************************/ static uint16_t em_shift_in_mdi_bits(struct em_hw *hw) { uint32_t ctrl; uint16_t data = 0; uint8_t i; /* In order to read a register from the PHY, we need to shift in a total * of 18 bits from the PHY. The first two bit (turnaround) times are used * to avoid contention on the MDIO pin when a read operation is performed. * These two bits are ignored by us and thrown away. Bits are "shifted in" * by raising the input to the Management Data Clock (setting the MDC bit), * and then reading the value of the MDIO bit. */ ctrl = E1000_READ_REG(hw, CTRL); /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ ctrl &= ~E1000_CTRL_MDIO_DIR; ctrl &= ~E1000_CTRL_MDIO; E1000_WRITE_REG(hw, CTRL, ctrl); E1000_WRITE_FLUSH(hw); /* Raise and Lower the clock before reading in the data. This accounts for * the turnaround bits. The first clock occurred when we clocked out the * last bit of the Register Address. */ em_raise_mdi_clk(hw, &ctrl); em_lower_mdi_clk(hw, &ctrl); for(data = 0, i = 0; i < 16; i++) { data = data << 1; em_raise_mdi_clk(hw, &ctrl); ctrl = E1000_READ_REG(hw, CTRL); /* Check to see if we shifted in a "1". */ if(ctrl & E1000_CTRL_MDIO) data |= 1; em_lower_mdi_clk(hw, &ctrl); } em_raise_mdi_clk(hw, &ctrl); em_lower_mdi_clk(hw, &ctrl); return data; } /***************************************************************************** * Reads the value from a PHY register, if the value is on a specific non zero * page, sets the page first. * hw - Struct containing variables accessed by shared code * reg_addr - address of the PHY register to read ******************************************************************************/ int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) { uint32_t ret_val; DEBUGFUNC("em_read_phy_reg"); if((hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) && (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, (uint16_t)reg_addr); if(ret_val) { return ret_val; } } ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, phy_data); return ret_val; } int32_t em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) { uint32_t i; uint32_t mdic = 0; const uint32_t phy_addr = 1; DEBUGFUNC("em_read_phy_reg_ex"); if(reg_addr > MAX_PHY_REG_ADDRESS) { DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); return -E1000_ERR_PARAM; } if(hw->mac_type > em_82543) { /* Set up Op-code, Phy Address, and register address in the MDI * Control register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | (phy_addr << E1000_MDIC_PHY_SHIFT) | (E1000_MDIC_OP_READ)); E1000_WRITE_REG(hw, MDIC, mdic); /* Poll the ready bit to see if the MDI read completed */ for(i = 0; i < 64; i++) { usec_delay(50); mdic = E1000_READ_REG(hw, MDIC); if(mdic & E1000_MDIC_READY) break; } if(!(mdic & E1000_MDIC_READY)) { DEBUGOUT("MDI Read did not complete\n"); return -E1000_ERR_PHY; } if(mdic & E1000_MDIC_ERROR) { DEBUGOUT("MDI Error\n"); return -E1000_ERR_PHY; } *phy_data = (uint16_t) mdic; } else { /* We must first send a preamble through the MDIO pin to signal the * beginning of an MII instruction. This is done by sending 32 * consecutive "1" bits. */ em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); /* Now combine the next few fields that are required for a read * operation. We use this method instead of calling the * em_shift_out_mdi_bits routine five different times. The format of * a MII read instruction consists of a shift out of 14 bits and is * defined as follows: * * followed by a shift in of 18 bits. This first two bits shifted in * are TurnAround bits used to avoid contention on the MDIO pin when a * READ operation is performed. These two bits are thrown away * followed by a shift in of 16 bits which contains the desired data. */ mdic = ((reg_addr) | (phy_addr << 5) | (PHY_OP_READ << 10) | (PHY_SOF << 12)); em_shift_out_mdi_bits(hw, mdic, 14); /* Now that we've shifted out the read command to the MII, we need to * "shift in" the 16-bit value (18 total bits) of the requested PHY * register address. */ *phy_data = em_shift_in_mdi_bits(hw); } return E1000_SUCCESS; } /****************************************************************************** * Writes a value to a PHY register * * hw - Struct containing variables accessed by shared code * reg_addr - address of the PHY register to write * data - data to write to the PHY ******************************************************************************/ int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) { uint32_t ret_val; DEBUGFUNC("em_write_phy_reg"); if((hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) && (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, (uint16_t)reg_addr); if(ret_val) { return ret_val; } } ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, phy_data); return ret_val; } int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) { uint32_t i; uint32_t mdic = 0; const uint32_t phy_addr = 1; DEBUGFUNC("em_write_phy_reg_ex"); if(reg_addr > MAX_PHY_REG_ADDRESS) { DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); return -E1000_ERR_PARAM; } if(hw->mac_type > em_82543) { /* Set up Op-code, Phy Address, register address, and data intended * for the PHY register in the MDI Control register. The MAC will take * care of interfacing with the PHY to send the desired data. */ mdic = (((uint32_t) phy_data) | (reg_addr << E1000_MDIC_REG_SHIFT) | (phy_addr << E1000_MDIC_PHY_SHIFT) | (E1000_MDIC_OP_WRITE)); E1000_WRITE_REG(hw, MDIC, mdic); /* Poll the ready bit to see if the MDI read completed */ for(i = 0; i < 640; i++) { usec_delay(5); mdic = E1000_READ_REG(hw, MDIC); if(mdic & E1000_MDIC_READY) break; } if(!(mdic & E1000_MDIC_READY)) { DEBUGOUT("MDI Write did not complete\n"); return -E1000_ERR_PHY; } } else { /* We'll need to use the SW defined pins to shift the write command * out to the PHY. We first send a preamble to the PHY to signal the * beginning of the MII instruction. This is done by sending 32 * consecutive "1" bits. */ em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); /* Now combine the remaining required fields that will indicate a * write operation. We use this method instead of calling the * em_shift_out_mdi_bits routine for each field in the command. The * format of a MII write instruction is as follows: * . */ mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); mdic <<= 16; mdic |= (uint32_t) phy_data; em_shift_out_mdi_bits(hw, mdic, 32); } return E1000_SUCCESS; } /****************************************************************************** * Returns the PHY to the power-on reset state * * hw - Struct containing variables accessed by shared code ******************************************************************************/ int32_t em_phy_hw_reset(struct em_hw *hw) { uint32_t ctrl, ctrl_ext; uint32_t led_ctrl; int32_t ret_val; DEBUGFUNC("em_phy_hw_reset"); /* In the case of the phy reset being blocked, it's not an error, we * simply return success without performing the reset. */ ret_val = em_check_phy_reset_block(hw); if (ret_val) return E1000_SUCCESS; DEBUGOUT("Resetting Phy...\n"); if(hw->mac_type > em_82543) { - /* Read the device control register and assert the E1000_CTRL_PHY_RST - * bit. Then, take it out of reset. - */ - ctrl = E1000_READ_REG(hw, CTRL); - E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); - E1000_WRITE_FLUSH(hw); - msec_delay(10); - E1000_WRITE_REG(hw, CTRL, ctrl); - E1000_WRITE_FLUSH(hw); + /* + * Read the device control register and assert the E1000_CTRL_PHY_RST + * bit. Then, take it out of reset. + * For pre-em_82571 hardware, we delay for 10ms between the assert + * and deassert. For em_82571 hardware and later, we instead delay + * for 10ms after the deassertion. + */ + ctrl = E1000_READ_REG(hw, CTRL); + E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); + E1000_WRITE_FLUSH(hw); + if (hw->mac_type < em_82571) + msec_delay(10); + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + if (hw->mac_type >= em_82571) + msec_delay(10); } else { /* Read the Extended Device Control Register, assert the PHY_RESET_DIR * bit to put the PHY into reset. Then, take it out of reset. */ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); E1000_WRITE_FLUSH(hw); msec_delay(10); ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); E1000_WRITE_FLUSH(hw); } usec_delay(150); if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { /* Configure activity LED after PHY reset */ led_ctrl = E1000_READ_REG(hw, LEDCTL); led_ctrl &= IGP_ACTIVITY_LED_MASK; led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); E1000_WRITE_REG(hw, LEDCTL, led_ctrl); } /* Wait for FW to finish PHY configuration. */ ret_val = em_get_phy_cfg_done(hw); return ret_val; } /****************************************************************************** * Resets the PHY * * hw - Struct containing variables accessed by shared code * * Sets bit 15 of the MII Control regiser ******************************************************************************/ int32_t em_phy_reset(struct em_hw *hw) { int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_phy_reset"); /* In the case of the phy reset being blocked, it's not an error, we * simply return success without performing the reset. */ ret_val = em_check_phy_reset_block(hw); if (ret_val) return E1000_SUCCESS; switch (hw->mac_type) { case em_82541_rev_2: + case em_82571: + case em_82572: ret_val = em_phy_hw_reset(hw); if(ret_val) return ret_val; break; default: ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); if(ret_val) return ret_val; phy_data |= MII_CR_RESET; ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); if(ret_val) return ret_val; usec_delay(1); break; } if(hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) em_phy_init_script(hw); return E1000_SUCCESS; } /****************************************************************************** * Probes the expected PHY address for known PHY IDs * * hw - Struct containing variables accessed by shared code ******************************************************************************/ int32_t em_detect_gig_phy(struct em_hw *hw) { int32_t phy_init_status, ret_val; uint16_t phy_id_high, phy_id_low; boolean_t match = FALSE; DEBUGFUNC("em_detect_gig_phy"); + /* The 82571 firmware may still be configuring the PHY. In this + * case, we cannot access the PHY until the configuration is done. So + * we explicitly set the PHY values. */ + if(hw->mac_type == em_82571 || hw->mac_type == em_82572) { + hw->phy_id = IGP01E1000_I_PHY_ID; + hw->phy_type = em_phy_igp_2; + return E1000_SUCCESS; + } + /* Read the PHY ID Registers to identify which PHY is onboard. */ ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); if(ret_val) return ret_val; hw->phy_id = (uint32_t) (phy_id_high << 16); usec_delay(20); ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); if(ret_val) return ret_val; hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; switch(hw->mac_type) { case em_82543: if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; break; case em_82544: if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; break; case em_82540: case em_82545: case em_82545_rev_3: case em_82546: case em_82546_rev_3: if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; break; case em_82541: case em_82541_rev_2: case em_82547: case em_82547_rev_2: if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; break; case em_82573: if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; break; default: DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); return -E1000_ERR_CONFIG; } phy_init_status = em_set_phy_type(hw); if ((match) && (phy_init_status == E1000_SUCCESS)) { DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); return E1000_SUCCESS; } DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); return -E1000_ERR_PHY; } /****************************************************************************** * Resets the PHY's DSP * * hw - Struct containing variables accessed by shared code ******************************************************************************/ static int32_t em_phy_reset_dsp(struct em_hw *hw) { int32_t ret_val; DEBUGFUNC("em_phy_reset_dsp"); do { ret_val = em_write_phy_reg(hw, 29, 0x001d); if(ret_val) break; ret_val = em_write_phy_reg(hw, 30, 0x00c1); if(ret_val) break; ret_val = em_write_phy_reg(hw, 30, 0x0000); if(ret_val) break; ret_val = E1000_SUCCESS; } while(0); return ret_val; } /****************************************************************************** * Get PHY information from various PHY registers for igp PHY only. * * hw - Struct containing variables accessed by shared code * phy_info - PHY information structure ******************************************************************************/ int32_t em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info) { int32_t ret_val; uint16_t phy_data, polarity, min_length, max_length, average; DEBUGFUNC("em_phy_igp_get_info"); /* The downshift status is checked only once, after link is established, * and it stored in the hw->speed_downgraded parameter. */ phy_info->downshift = (em_downshift)hw->speed_downgraded; /* IGP01E1000 does not need to support it. */ phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal; /* IGP01E1000 always correct polarity reversal */ phy_info->polarity_correction = em_polarity_reversal_enabled; /* Check polarity status */ ret_val = em_check_polarity(hw, &polarity); if(ret_val) return ret_val; phy_info->cable_polarity = polarity; ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); if(ret_val) return ret_val; phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> IGP01E1000_PSSR_MDIX_SHIFT; if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == IGP01E1000_PSSR_SPEED_1000MBPS) { /* Local/Remote Receiver Information are only valid at 1000 Mbps */ ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); if(ret_val) return ret_val; phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> SR_1000T_LOCAL_RX_STATUS_SHIFT; phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> SR_1000T_REMOTE_RX_STATUS_SHIFT; /* Get cable length */ ret_val = em_get_cable_length(hw, &min_length, &max_length); if(ret_val) return ret_val; /* Translate to old method */ average = (max_length + min_length) / 2; if(average <= em_igp_cable_length_50) phy_info->cable_length = em_cable_length_50; else if(average <= em_igp_cable_length_80) phy_info->cable_length = em_cable_length_50_80; else if(average <= em_igp_cable_length_110) phy_info->cable_length = em_cable_length_80_110; else if(average <= em_igp_cable_length_140) phy_info->cable_length = em_cable_length_110_140; else phy_info->cable_length = em_cable_length_140; } return E1000_SUCCESS; } /****************************************************************************** * Get PHY information from various PHY registers fot m88 PHY only. * * hw - Struct containing variables accessed by shared code * phy_info - PHY information structure ******************************************************************************/ int32_t em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info) { int32_t ret_val; uint16_t phy_data, polarity; DEBUGFUNC("em_phy_m88_get_info"); /* The downshift status is checked only once, after link is established, * and it stored in the hw->speed_downgraded parameter. */ phy_info->downshift = (em_downshift)hw->speed_downgraded; ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); if(ret_val) return ret_val; phy_info->extended_10bt_distance = (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT; phy_info->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> M88E1000_PSCR_POLARITY_REVERSAL_SHIFT; /* Check polarity status */ ret_val = em_check_polarity(hw, &polarity); if(ret_val) return ret_val; phy_info->cable_polarity = polarity; ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); if(ret_val) return ret_val; phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> M88E1000_PSSR_MDIX_SHIFT; if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { /* Cable Length Estimation and Local/Remote Receiver Information * are only valid at 1000 Mbps. */ phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> M88E1000_PSSR_CABLE_LENGTH_SHIFT); ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); if(ret_val) return ret_val; phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> SR_1000T_LOCAL_RX_STATUS_SHIFT; phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> SR_1000T_REMOTE_RX_STATUS_SHIFT; } return E1000_SUCCESS; } /****************************************************************************** * Get PHY information from various PHY registers * * hw - Struct containing variables accessed by shared code * phy_info - PHY information structure ******************************************************************************/ int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info) { int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_phy_get_info"); phy_info->cable_length = em_cable_length_undefined; phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined; phy_info->cable_polarity = em_rev_polarity_undefined; phy_info->downshift = em_downshift_undefined; phy_info->polarity_correction = em_polarity_reversal_undefined; phy_info->mdix_mode = em_auto_x_mode_undefined; phy_info->local_rx = em_1000t_rx_status_undefined; phy_info->remote_rx = em_1000t_rx_status_undefined; if(hw->media_type != em_media_type_copper) { DEBUGOUT("PHY info is only valid for copper media\n"); return -E1000_ERR_CONFIG; } ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); if(ret_val) return ret_val; if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { DEBUGOUT("PHY info is only valid if link is up\n"); return -E1000_ERR_CONFIG; } if(hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) return em_phy_igp_get_info(hw, phy_info); else return em_phy_m88_get_info(hw, phy_info); } int32_t em_validate_mdi_setting(struct em_hw *hw) { DEBUGFUNC("em_validate_mdi_settings"); if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { DEBUGOUT("Invalid MDI setting detected\n"); hw->mdix = 1; return -E1000_ERR_CONFIG; } return E1000_SUCCESS; } /****************************************************************************** * Sets up eeprom variables in the hw struct. Must be called after mac_type * is configured. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_init_eeprom_params(struct em_hw *hw) { struct em_eeprom_info *eeprom = &hw->eeprom; uint32_t eecd = E1000_READ_REG(hw, EECD); int32_t ret_val = E1000_SUCCESS; uint16_t eeprom_size; DEBUGFUNC("em_init_eeprom_params"); switch (hw->mac_type) { case em_82542_rev2_0: case em_82542_rev2_1: case em_82543: case em_82544: eeprom->type = em_eeprom_microwire; eeprom->word_size = 64; eeprom->opcode_bits = 3; eeprom->address_bits = 6; eeprom->delay_usec = 50; eeprom->use_eerd = FALSE; eeprom->use_eewr = FALSE; break; case em_82540: case em_82545: case em_82545_rev_3: case em_82546: case em_82546_rev_3: eeprom->type = em_eeprom_microwire; eeprom->opcode_bits = 3; eeprom->delay_usec = 50; if(eecd & E1000_EECD_SIZE) { eeprom->word_size = 256; eeprom->address_bits = 8; } else { eeprom->word_size = 64; eeprom->address_bits = 6; } eeprom->use_eerd = FALSE; eeprom->use_eewr = FALSE; break; case em_82541: case em_82541_rev_2: case em_82547: case em_82547_rev_2: if (eecd & E1000_EECD_TYPE) { eeprom->type = em_eeprom_spi; eeprom->opcode_bits = 8; eeprom->delay_usec = 1; if (eecd & E1000_EECD_ADDR_BITS) { eeprom->page_size = 32; eeprom->address_bits = 16; } else { eeprom->page_size = 8; eeprom->address_bits = 8; } } else { eeprom->type = em_eeprom_microwire; eeprom->opcode_bits = 3; eeprom->delay_usec = 50; if (eecd & E1000_EECD_ADDR_BITS) { eeprom->word_size = 256; eeprom->address_bits = 8; } else { eeprom->word_size = 64; eeprom->address_bits = 6; } } eeprom->use_eerd = FALSE; eeprom->use_eewr = FALSE; break; + case em_82571: + case em_82572: + eeprom->type = em_eeprom_spi; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->page_size = 32; + eeprom->address_bits = 16; + } else { + eeprom->page_size = 8; + eeprom->address_bits = 8; + } + eeprom->use_eerd = FALSE; + eeprom->use_eewr = FALSE; + break; case em_82573: eeprom->type = em_eeprom_spi; eeprom->opcode_bits = 8; eeprom->delay_usec = 1; if (eecd & E1000_EECD_ADDR_BITS) { eeprom->page_size = 32; eeprom->address_bits = 16; } else { eeprom->page_size = 8; eeprom->address_bits = 8; } eeprom->use_eerd = TRUE; eeprom->use_eewr = TRUE; if(em_is_onboard_nvm_eeprom(hw) == FALSE) { eeprom->type = em_eeprom_flash; eeprom->word_size = 2048; /* Ensure that the Autonomous FLASH update bit is cleared due to * Flash update issue on parts which use a FLASH for NVM. */ eecd &= ~E1000_EECD_AUPDEN; E1000_WRITE_REG(hw, EECD, eecd); } break; default: break; } if (eeprom->type == em_eeprom_spi) { /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to * 32KB (incremented by powers of 2). */ if(hw->mac_type <= em_82547_rev_2) { /* Set to default value for initial eeprom read. */ eeprom->word_size = 64; ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); if(ret_val) return ret_val; eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; /* 256B eeprom size was not supported in earlier hardware, so we * bump eeprom_size up one to ensure that "1" (which maps to 256B) * is never the result used in the shifting logic below. */ if(eeprom_size) eeprom_size++; } else { eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> E1000_EECD_SIZE_EX_SHIFT); } eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); } return ret_val; } /****************************************************************************** * Raises the EEPROM's clock input. * * hw - Struct containing variables accessed by shared code * eecd - EECD's current value *****************************************************************************/ static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) { /* Raise the clock input to the EEPROM (by setting the SK bit), and then * wait microseconds. */ *eecd = *eecd | E1000_EECD_SK; E1000_WRITE_REG(hw, EECD, *eecd); E1000_WRITE_FLUSH(hw); usec_delay(hw->eeprom.delay_usec); } /****************************************************************************** * Lowers the EEPROM's clock input. * * hw - Struct containing variables accessed by shared code * eecd - EECD's current value *****************************************************************************/ static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) { /* Lower the clock input to the EEPROM (by clearing the SK bit), and then * wait 50 microseconds. */ *eecd = *eecd & ~E1000_EECD_SK; E1000_WRITE_REG(hw, EECD, *eecd); E1000_WRITE_FLUSH(hw); usec_delay(hw->eeprom.delay_usec); } /****************************************************************************** * Shift data bits out to the EEPROM. * * hw - Struct containing variables accessed by shared code * data - data to send to the EEPROM * count - number of bits to shift out *****************************************************************************/ static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) { struct em_eeprom_info *eeprom = &hw->eeprom; uint32_t eecd; uint32_t mask; /* We need to shift "count" bits out to the EEPROM. So, value in the * "data" parameter will be shifted out to the EEPROM one bit at a time. * In order to do this, "data" must be broken down into bits. */ mask = 0x01 << (count - 1); eecd = E1000_READ_REG(hw, EECD); if (eeprom->type == em_eeprom_microwire) { eecd &= ~E1000_EECD_DO; } else if (eeprom->type == em_eeprom_spi) { eecd |= E1000_EECD_DO; } do { /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", * and then raising and then lowering the clock (the SK bit controls * the clock input to the EEPROM). A "0" is shifted out to the EEPROM * by setting "DI" to "0" and then raising and then lowering the clock. */ eecd &= ~E1000_EECD_DI; if(data & mask) eecd |= E1000_EECD_DI; E1000_WRITE_REG(hw, EECD, eecd); E1000_WRITE_FLUSH(hw); usec_delay(eeprom->delay_usec); em_raise_ee_clk(hw, &eecd); em_lower_ee_clk(hw, &eecd); mask = mask >> 1; } while(mask); /* We leave the "DI" bit set to "0" when we leave this routine. */ eecd &= ~E1000_EECD_DI; E1000_WRITE_REG(hw, EECD, eecd); } /****************************************************************************** * Shift data bits in from the EEPROM * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) { uint32_t eecd; uint32_t i; uint16_t data; /* In order to read a register from the EEPROM, we need to shift 'count' * bits in from the EEPROM. Bits are "shifted in" by raising the clock * input to the EEPROM (setting the SK bit), and then reading the value of * the "DO" bit. During this "shifting in" process the "DI" bit should * always be clear. */ eecd = E1000_READ_REG(hw, EECD); eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); data = 0; for(i = 0; i < count; i++) { data = data << 1; em_raise_ee_clk(hw, &eecd); eecd = E1000_READ_REG(hw, EECD); eecd &= ~(E1000_EECD_DI); if(eecd & E1000_EECD_DO) data |= 1; em_lower_ee_clk(hw, &eecd); } return data; } /****************************************************************************** * Prepares EEPROM for access * * hw - Struct containing variables accessed by shared code * * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This * function should be called before issuing a command to the EEPROM. *****************************************************************************/ static int32_t em_acquire_eeprom(struct em_hw *hw) { struct em_eeprom_info *eeprom = &hw->eeprom; uint32_t eecd, i=0; DEBUGFUNC("em_acquire_eeprom"); if(em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_EEPROM; eecd = E1000_READ_REG(hw, EECD); if (hw->mac_type != em_82573) { /* Request EEPROM Access */ if(hw->mac_type > em_82544) { eecd |= E1000_EECD_REQ; E1000_WRITE_REG(hw, EECD, eecd); eecd = E1000_READ_REG(hw, EECD); while((!(eecd & E1000_EECD_GNT)) && (i < E1000_EEPROM_GRANT_ATTEMPTS)) { i++; usec_delay(5); eecd = E1000_READ_REG(hw, EECD); } if(!(eecd & E1000_EECD_GNT)) { eecd &= ~E1000_EECD_REQ; E1000_WRITE_REG(hw, EECD, eecd); DEBUGOUT("Could not acquire EEPROM grant\n"); + em_put_hw_eeprom_semaphore(hw); return -E1000_ERR_EEPROM; } } } /* Setup EEPROM for Read/Write */ if (eeprom->type == em_eeprom_microwire) { /* Clear SK and DI */ eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); E1000_WRITE_REG(hw, EECD, eecd); /* Set CS */ eecd |= E1000_EECD_CS; E1000_WRITE_REG(hw, EECD, eecd); } else if (eeprom->type == em_eeprom_spi) { /* Clear SK and CS */ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); E1000_WRITE_REG(hw, EECD, eecd); usec_delay(1); } return E1000_SUCCESS; } /****************************************************************************** * Returns EEPROM to a "standby" state * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static void em_standby_eeprom(struct em_hw *hw) { struct em_eeprom_info *eeprom = &hw->eeprom; uint32_t eecd; eecd = E1000_READ_REG(hw, EECD); if(eeprom->type == em_eeprom_microwire) { eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); E1000_WRITE_REG(hw, EECD, eecd); E1000_WRITE_FLUSH(hw); usec_delay(eeprom->delay_usec); /* Clock high */ eecd |= E1000_EECD_SK; E1000_WRITE_REG(hw, EECD, eecd); E1000_WRITE_FLUSH(hw); usec_delay(eeprom->delay_usec); /* Select EEPROM */ eecd |= E1000_EECD_CS; E1000_WRITE_REG(hw, EECD, eecd); E1000_WRITE_FLUSH(hw); usec_delay(eeprom->delay_usec); /* Clock low */ eecd &= ~E1000_EECD_SK; E1000_WRITE_REG(hw, EECD, eecd); E1000_WRITE_FLUSH(hw); usec_delay(eeprom->delay_usec); } else if(eeprom->type == em_eeprom_spi) { /* Toggle CS to flush commands */ eecd |= E1000_EECD_CS; E1000_WRITE_REG(hw, EECD, eecd); E1000_WRITE_FLUSH(hw); usec_delay(eeprom->delay_usec); eecd &= ~E1000_EECD_CS; E1000_WRITE_REG(hw, EECD, eecd); E1000_WRITE_FLUSH(hw); usec_delay(eeprom->delay_usec); } } /****************************************************************************** * Terminates a command by inverting the EEPROM's chip select pin * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static void em_release_eeprom(struct em_hw *hw) { uint32_t eecd; DEBUGFUNC("em_release_eeprom"); eecd = E1000_READ_REG(hw, EECD); if (hw->eeprom.type == em_eeprom_spi) { eecd |= E1000_EECD_CS; /* Pull CS high */ eecd &= ~E1000_EECD_SK; /* Lower SCK */ E1000_WRITE_REG(hw, EECD, eecd); usec_delay(hw->eeprom.delay_usec); } else if(hw->eeprom.type == em_eeprom_microwire) { /* cleanup eeprom */ /* CS on Microwire is active-high */ eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); E1000_WRITE_REG(hw, EECD, eecd); /* Rising edge of clock */ eecd |= E1000_EECD_SK; E1000_WRITE_REG(hw, EECD, eecd); E1000_WRITE_FLUSH(hw); usec_delay(hw->eeprom.delay_usec); /* Falling edge of clock */ eecd &= ~E1000_EECD_SK; E1000_WRITE_REG(hw, EECD, eecd); E1000_WRITE_FLUSH(hw); usec_delay(hw->eeprom.delay_usec); } /* Stop requesting EEPROM access */ if(hw->mac_type > em_82544) { eecd &= ~E1000_EECD_REQ; E1000_WRITE_REG(hw, EECD, eecd); } em_put_hw_eeprom_semaphore(hw); } /****************************************************************************** * Reads a 16 bit word from the EEPROM. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_spi_eeprom_ready(struct em_hw *hw) { uint16_t retry_count = 0; uint8_t spi_stat_reg; DEBUGFUNC("em_spi_eeprom_ready"); /* Read "Status Register" repeatedly until the LSB is cleared. The * EEPROM will signal that the command has been completed by clearing * bit 0 of the internal status register. If it's not cleared within * 5 milliseconds, then error out. */ retry_count = 0; do { em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, hw->eeprom.opcode_bits); spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8); if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) break; usec_delay(5); retry_count += 5; em_standby_eeprom(hw); } while(retry_count < EEPROM_MAX_RETRY_SPI); /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and * only 0-5mSec on 5V devices) */ if(retry_count >= EEPROM_MAX_RETRY_SPI) { DEBUGOUT("SPI EEPROM Status error\n"); return -E1000_ERR_EEPROM; } return E1000_SUCCESS; } /****************************************************************************** * Reads a 16 bit word from the EEPROM. * * hw - Struct containing variables accessed by shared code * offset - offset of word in the EEPROM to read * data - word read from the EEPROM * words - number of words to read *****************************************************************************/ int32_t em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data) { struct em_eeprom_info *eeprom = &hw->eeprom; uint32_t i = 0; int32_t ret_val; DEBUGFUNC("em_read_eeprom"); /* A check for invalid values: offset too large, too many words, and not * enough words. */ if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || (words == 0)) { DEBUGOUT("\"words\" parameter out of bounds\n"); return -E1000_ERR_EEPROM; } /* FLASH reads without acquiring the semaphore are safe in 82573-based * controllers. */ if ((em_is_onboard_nvm_eeprom(hw) == TRUE) || (hw->mac_type != em_82573)) { /* Prepare the EEPROM for reading */ if(em_acquire_eeprom(hw) != E1000_SUCCESS) return -E1000_ERR_EEPROM; } if(eeprom->use_eerd == TRUE) { ret_val = em_read_eeprom_eerd(hw, offset, words, data); if ((em_is_onboard_nvm_eeprom(hw) == TRUE) || (hw->mac_type != em_82573)) em_release_eeprom(hw); return ret_val; } if(eeprom->type == em_eeprom_spi) { uint16_t word_in; uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; if(em_spi_eeprom_ready(hw)) { em_release_eeprom(hw); return -E1000_ERR_EEPROM; } em_standby_eeprom(hw); /* Some SPI eeproms use the 8th address bit embedded in the opcode */ if((eeprom->address_bits == 8) && (offset >= 128)) read_opcode |= EEPROM_A8_OPCODE_SPI; /* Send the READ command (opcode + addr) */ em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); /* Read the data. The address of the eeprom internally increments with * each byte (spi) being read, saving on the overhead of eeprom setup * and tear-down. The address counter will roll over if reading beyond * the size of the eeprom, thus allowing the entire memory to be read * starting from any offset. */ for (i = 0; i < words; i++) { word_in = em_shift_in_ee_bits(hw, 16); data[i] = (word_in >> 8) | (word_in << 8); } } else if(eeprom->type == em_eeprom_microwire) { for (i = 0; i < words; i++) { /* Send the READ command (opcode + addr) */ em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, eeprom->opcode_bits); em_shift_out_ee_bits(hw, (uint16_t)(offset + i), eeprom->address_bits); /* Read the data. For microwire, each word requires the overhead * of eeprom setup and tear-down. */ data[i] = em_shift_in_ee_bits(hw, 16); em_standby_eeprom(hw); } } /* End this read operation */ em_release_eeprom(hw); return E1000_SUCCESS; } /****************************************************************************** * Reads a 16 bit word from the EEPROM using the EERD register. * * hw - Struct containing variables accessed by shared code * offset - offset of word in the EEPROM to read * data - word read from the EEPROM * words - number of words to read *****************************************************************************/ int32_t em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data) { uint32_t i, eerd = 0; int32_t error = 0; for (i = 0; i < words; i++) { eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + E1000_EEPROM_RW_REG_START; E1000_WRITE_REG(hw, EERD, eerd); error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); if(error) { break; } data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); } return error; } /****************************************************************************** * Writes a 16 bit word from the EEPROM using the EEWR register. * * hw - Struct containing variables accessed by shared code * offset - offset of word in the EEPROM to read * data - word read from the EEPROM * words - number of words to read *****************************************************************************/ int32_t em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data) { uint32_t register_value = 0; uint32_t i = 0; int32_t error = 0; for (i = 0; i < words; i++) { register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | E1000_EEPROM_RW_REG_START; error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); if(error) { break; } E1000_WRITE_REG(hw, EEWR, register_value); error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); if(error) { break; } } return error; } /****************************************************************************** * Polls the status bit (bit 1) of the EERD to determine when the read is done. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) { uint32_t attempts = 100000; uint32_t i, reg = 0; int32_t done = E1000_ERR_EEPROM; for(i = 0; i < attempts; i++) { if(eerd == E1000_EEPROM_POLL_READ) reg = E1000_READ_REG(hw, EERD); else reg = E1000_READ_REG(hw, EEWR); if(reg & E1000_EEPROM_RW_REG_DONE) { done = E1000_SUCCESS; break; } usec_delay(5); } return done; } /*************************************************************************** * Description: Determines if the onboard NVM is FLASH or EEPROM. * * hw - Struct containing variables accessed by shared code ****************************************************************************/ boolean_t em_is_onboard_nvm_eeprom(struct em_hw *hw) { uint32_t eecd = 0; if(hw->mac_type == em_82573) { eecd = E1000_READ_REG(hw, EECD); /* Isolate bits 15 & 16 */ eecd = ((eecd >> 15) & 0x03); /* If both bits are set, device is Flash type */ if(eecd == 0x03) { return FALSE; } } return TRUE; } /****************************************************************************** * Verifies that the EEPROM has a valid checksum * * hw - Struct containing variables accessed by shared code * * Reads the first 64 16 bit words of the EEPROM and sums the values read. * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is * valid. *****************************************************************************/ int32_t em_validate_eeprom_checksum(struct em_hw *hw) { uint16_t checksum = 0; uint16_t i, eeprom_data; DEBUGFUNC("em_validate_eeprom_checksum"); if ((hw->mac_type == em_82573) && (em_is_onboard_nvm_eeprom(hw) == FALSE)) { /* Check bit 4 of word 10h. If it is 0, firmware is done updating * 10h-12h. Checksum may need to be fixed. */ em_read_eeprom(hw, 0x10, 1, &eeprom_data); if ((eeprom_data & 0x10) == 0) { /* Read 0x23 and check bit 15. This bit is a 1 when the checksum * has already been fixed. If the checksum is still wrong and this * bit is a 1, we need to return bad checksum. Otherwise, we need * to set this bit to a 1 and update the checksum. */ em_read_eeprom(hw, 0x23, 1, &eeprom_data); if ((eeprom_data & 0x8000) == 0) { eeprom_data |= 0x8000; em_write_eeprom(hw, 0x23, 1, &eeprom_data); em_update_eeprom_checksum(hw); } } } for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } checksum += eeprom_data; } if(checksum == (uint16_t) EEPROM_SUM) return E1000_SUCCESS; else { DEBUGOUT("EEPROM Checksum Invalid\n"); return -E1000_ERR_EEPROM; } } /****************************************************************************** * Calculates the EEPROM checksum and writes it to the EEPROM * * hw - Struct containing variables accessed by shared code * * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. * Writes the difference to word offset 63 of the EEPROM. *****************************************************************************/ int32_t em_update_eeprom_checksum(struct em_hw *hw) { uint16_t checksum = 0; uint16_t i, eeprom_data; DEBUGFUNC("em_update_eeprom_checksum"); for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } checksum += eeprom_data; } checksum = (uint16_t) EEPROM_SUM - checksum; if(em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { DEBUGOUT("EEPROM Write Error\n"); return -E1000_ERR_EEPROM; } else if (hw->eeprom.type == em_eeprom_flash) { em_commit_shadow_ram(hw); } return E1000_SUCCESS; } /****************************************************************************** * Parent function for writing words to the different EEPROM types. * * hw - Struct containing variables accessed by shared code * offset - offset within the EEPROM to be written to * words - number of words to write * data - 16 bit word to be written to the EEPROM * * If em_update_eeprom_checksum is not called after this function, the * EEPROM will most likely contain an invalid checksum. *****************************************************************************/ int32_t em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data) { struct em_eeprom_info *eeprom = &hw->eeprom; int32_t status = 0; DEBUGFUNC("em_write_eeprom"); /* A check for invalid values: offset too large, too many words, and not * enough words. */ if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || (words == 0)) { DEBUGOUT("\"words\" parameter out of bounds\n"); return -E1000_ERR_EEPROM; } - /* 82573 reads only through eerd */ + /* 82573 writes only through eewr */ if(eeprom->use_eewr == TRUE) return em_write_eeprom_eewr(hw, offset, words, data); /* Prepare the EEPROM for writing */ if (em_acquire_eeprom(hw) != E1000_SUCCESS) return -E1000_ERR_EEPROM; if(eeprom->type == em_eeprom_microwire) { status = em_write_eeprom_microwire(hw, offset, words, data); } else { status = em_write_eeprom_spi(hw, offset, words, data); msec_delay(10); } /* Done with writing */ em_release_eeprom(hw); return status; } /****************************************************************************** * Writes a 16 bit word to a given offset in an SPI EEPROM. * * hw - Struct containing variables accessed by shared code * offset - offset within the EEPROM to be written to * words - number of words to write * data - pointer to array of 8 bit words to be written to the EEPROM * *****************************************************************************/ int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data) { struct em_eeprom_info *eeprom = &hw->eeprom; uint16_t widx = 0; DEBUGFUNC("em_write_eeprom_spi"); while (widx < words) { uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; em_standby_eeprom(hw); /* Send the WRITE ENABLE command (8 bit opcode ) */ em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, eeprom->opcode_bits); em_standby_eeprom(hw); /* Some SPI eeproms use the 8th address bit embedded in the opcode */ if((eeprom->address_bits == 8) && (offset >= 128)) write_opcode |= EEPROM_A8_OPCODE_SPI; /* Send the Write command (8-bit opcode + addr) */ em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), eeprom->address_bits); /* Send the data */ /* Loop to allow for up to whole page write (32 bytes) of eeprom */ while (widx < words) { uint16_t word_out = data[widx]; word_out = (word_out >> 8) | (word_out << 8); em_shift_out_ee_bits(hw, word_out, 16); widx++; /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE * operation, while the smaller eeproms are capable of an 8-byte * PAGE WRITE operation. Break the inner loop to pass new address */ if((((offset + widx)*2) % eeprom->page_size) == 0) { em_standby_eeprom(hw); break; } } } return E1000_SUCCESS; } /****************************************************************************** * Writes a 16 bit word to a given offset in a Microwire EEPROM. * * hw - Struct containing variables accessed by shared code * offset - offset within the EEPROM to be written to * words - number of words to write * data - pointer to array of 16 bit words to be written to the EEPROM * *****************************************************************************/ int32_t em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data) { struct em_eeprom_info *eeprom = &hw->eeprom; uint32_t eecd; uint16_t words_written = 0; uint16_t i = 0; DEBUGFUNC("em_write_eeprom_microwire"); /* Send the write enable command to the EEPROM (3-bit opcode plus * 6/8-bit dummy address beginning with 11). It's less work to include * the 11 of the dummy address as part of the opcode than it is to shift * it over the correct number of bits for the address. This puts the * EEPROM into write/erase mode. */ em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, (uint16_t)(eeprom->opcode_bits + 2)); em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); /* Prepare the EEPROM */ em_standby_eeprom(hw); while (words_written < words) { /* Send the Write command (3-bit opcode + addr) */ em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, eeprom->opcode_bits); em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), eeprom->address_bits); /* Send the data */ em_shift_out_ee_bits(hw, data[words_written], 16); /* Toggle the CS line. This in effect tells the EEPROM to execute * the previous command. */ em_standby_eeprom(hw); /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will * signal that the command has been completed by raising the DO signal. * If DO does not go high in 10 milliseconds, then error out. */ for(i = 0; i < 200; i++) { eecd = E1000_READ_REG(hw, EECD); if(eecd & E1000_EECD_DO) break; usec_delay(50); } if(i == 200) { DEBUGOUT("EEPROM Write did not complete\n"); return -E1000_ERR_EEPROM; } /* Recover from write */ em_standby_eeprom(hw); words_written++; } /* Send the write disable command to the EEPROM (3-bit opcode plus * 6/8-bit dummy address beginning with 10). It's less work to include * the 10 of the dummy address as part of the opcode than it is to shift * it over the correct number of bits for the address. This takes the * EEPROM out of write/erase mode. */ em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, (uint16_t)(eeprom->opcode_bits + 2)); em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); return E1000_SUCCESS; } /****************************************************************************** * Flushes the cached eeprom to NVM. This is done by saving the modified values * in the eeprom cache and the non modified values in the currently active bank * to the new bank. * * hw - Struct containing variables accessed by shared code * offset - offset of word in the EEPROM to read * data - word read from the EEPROM * words - number of words to read *****************************************************************************/ int32_t em_commit_shadow_ram(struct em_hw *hw) { uint32_t attempts = 100000; uint32_t eecd = 0; uint32_t flop = 0; uint32_t i = 0; int32_t error = E1000_SUCCESS; /* The flop register will be used to determine if flash type is STM */ flop = E1000_READ_REG(hw, FLOP); if (hw->mac_type == em_82573) { for (i=0; i < attempts; i++) { eecd = E1000_READ_REG(hw, EECD); if ((eecd & E1000_EECD_FLUPD) == 0) { break; } usec_delay(5); } if (i == attempts) { return -E1000_ERR_EEPROM; } /* If STM opcode located in bits 15:8 of flop, reset firmware */ if ((flop & 0xFF00) == E1000_STM_OPCODE) { E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); } /* Perform the flash update */ E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); for (i=0; i < attempts; i++) { eecd = E1000_READ_REG(hw, EECD); if ((eecd & E1000_EECD_FLUPD) == 0) { break; } usec_delay(5); } if (i == attempts) { return -E1000_ERR_EEPROM; } } return error; } /****************************************************************************** * Reads the adapter's part number from the EEPROM * * hw - Struct containing variables accessed by shared code * part_num - Adapter's part number *****************************************************************************/ int32_t em_read_part_num(struct em_hw *hw, uint32_t *part_num) { uint16_t offset = EEPROM_PBA_BYTE_1; uint16_t eeprom_data; DEBUGFUNC("em_read_part_num"); /* Get word 0 from EEPROM */ if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } /* Save word 0 in upper half of part_num */ *part_num = (uint32_t) (eeprom_data << 16); /* Get word 1 from EEPROM */ if(em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } /* Save word 1 in lower half of part_num */ *part_num |= eeprom_data; return E1000_SUCCESS; } /****************************************************************************** * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the * second function of dual function devices * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_read_mac_addr(struct em_hw * hw) { uint16_t offset; uint16_t eeprom_data, i; DEBUGFUNC("em_read_mac_addr"); for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { offset = i >> 1; if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); } - if(((hw->mac_type == em_82546) || (hw->mac_type == em_82546_rev_3)) && - (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) - hw->perm_mac_addr[5] ^= 0x01; + switch (hw->mac_type) { + case em_82546: + case em_82546_rev_3: + case em_82571: + if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) + hw->perm_mac_addr[5] ^= 0x01; + default: + break; + } for(i = 0; i < NODE_ADDRESS_SIZE; i++) hw->mac_addr[i] = hw->perm_mac_addr[i]; return E1000_SUCCESS; } /****************************************************************************** * Initializes receive address filters. * * hw - Struct containing variables accessed by shared code * * Places the MAC address in receive address register 0 and clears the rest * of the receive addresss registers. Clears the multicast table. Assumes * the receiver is in reset when the routine is called. *****************************************************************************/ void em_init_rx_addrs(struct em_hw *hw) { uint32_t i; uint32_t rar_num; DEBUGFUNC("em_init_rx_addrs"); /* Setup the receive address. */ DEBUGOUT("Programming MAC Address into RAR[0]\n"); em_rar_set(hw, hw->mac_addr, 0); rar_num = E1000_RAR_ENTRIES; + + /* Reserve a spot for the Locally Administered Address to work around + * an 82571 issue in which a reset on one port will reload the MAC on + * the other port. */ + if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) + rar_num -= 1; /* Zero out the other 15 receive addresses. */ DEBUGOUT("Clearing RAR[1-15]\n"); for(i = 1; i < rar_num; i++) { E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); } } /****************************************************************************** * Updates the MAC's list of multicast addresses. * * hw - Struct containing variables accessed by shared code * mc_addr_list - the list of new multicast addresses * mc_addr_count - number of addresses * pad - number of bytes between addresses in the list * rar_used_count - offset where to start adding mc addresses into the RAR's * * The given list replaces any existing list. Clears the last 15 receive * address registers and the multicast table. Uses receive address registers * for the first 15 multicast addresses, and hashes the rest into the * multicast table. *****************************************************************************/ void em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) { uint32_t hash_value; uint32_t i; uint32_t num_rar_entry; uint32_t num_mta_entry; DEBUGFUNC("em_mc_addr_list_update"); /* Set the new number of MC addresses that we are being requested to use. */ hw->num_mc_addrs = mc_addr_count; /* Clear RAR[1-15] */ DEBUGOUT(" Clearing RAR[1-15]\n"); num_rar_entry = E1000_RAR_ENTRIES; + /* Reserve a spot for the Locally Administered Address to work around + * an 82571 issue in which a reset on one port will reload the MAC on + * the other port. */ + if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) + num_rar_entry -= 1; + for(i = rar_used_count; i < num_rar_entry; i++) { E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); } /* Clear the MTA */ DEBUGOUT(" Clearing MTA\n"); num_mta_entry = E1000_NUM_MTA_REGISTERS; for(i = 0; i < num_mta_entry; i++) { E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); } /* Add the new addresses */ for(i = 0; i < mc_addr_count; i++) { DEBUGOUT(" Adding the multicast addresses:\n"); DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); hash_value = em_hash_mc_addr(hw, mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad))); DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); /* Place this multicast address in the RAR if there is room, * * else put it in the MTA */ if (rar_used_count < num_rar_entry) { em_rar_set(hw, mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), rar_used_count); rar_used_count++; } else { em_mta_set(hw, hash_value); } } DEBUGOUT("MC Update Complete\n"); } /****************************************************************************** * Hashes an address to determine its location in the multicast table * * hw - Struct containing variables accessed by shared code * mc_addr - the multicast address to hash *****************************************************************************/ uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) { uint32_t hash_value = 0; /* The portion of the address that is used for the hash table is * determined by the mc_filter_type setting. */ switch (hw->mc_filter_type) { /* [0] [1] [2] [3] [4] [5] * 01 AA 00 12 34 56 * LSB MSB */ case 0: /* [47:36] i.e. 0x563 for above example address */ hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); break; case 1: /* [46:35] i.e. 0xAC6 for above example address */ hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); break; case 2: /* [45:34] i.e. 0x5D8 for above example address */ hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); break; case 3: /* [43:32] i.e. 0x634 for above example address */ hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); break; } hash_value &= 0xFFF; return hash_value; } /****************************************************************************** * Sets the bit in the multicast table corresponding to the hash value. * * hw - Struct containing variables accessed by shared code * hash_value - Multicast address hash value *****************************************************************************/ void em_mta_set(struct em_hw *hw, uint32_t hash_value) { uint32_t hash_bit, hash_reg; uint32_t mta; uint32_t temp; /* The MTA is a register array of 128 32-bit registers. * It is treated like an array of 4096 bits. We want to set * bit BitArray[hash_value]. So we figure out what register * the bit is in, read it, OR in the new bit, then write * back the new value. The register is determined by the * upper 7 bits of the hash value and the bit within that * register are determined by the lower 5 bits of the value. */ hash_reg = (hash_value >> 5) & 0x7F; hash_bit = hash_value & 0x1F; mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); mta |= (1 << hash_bit); /* If we are on an 82544 and we are trying to write an odd offset * in the MTA, save off the previous entry before writing and * restore the old value after writing. */ if((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); } else { E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); } } /****************************************************************************** * Puts an ethernet address into a receive address register. * * hw - Struct containing variables accessed by shared code * addr - Address to put into receive address register * index - Receive address register to write *****************************************************************************/ void em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) { uint32_t rar_low, rar_high; /* HW expects these in little endian so we reverse the byte order * from network order (big endian) to little endian */ rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV); E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); } /****************************************************************************** * Writes a value to the specified offset in the VLAN filter table. * * hw - Struct containing variables accessed by shared code * offset - Offset in VLAN filer table to write * value - Value to write into VLAN filter table *****************************************************************************/ void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value) { uint32_t temp; if((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) { temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); } else { E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); } } /****************************************************************************** * Clears the VLAN filer table * * hw - Struct containing variables accessed by shared code *****************************************************************************/ void em_clear_vfta(struct em_hw *hw) { uint32_t offset; uint32_t vfta_value = 0; uint32_t vfta_offset = 0; uint32_t vfta_bit_in_reg = 0; if (hw->mac_type == em_82573) { if (hw->mng_cookie.vlan_id != 0) { /* The VFTA is a 4096b bit-field, each identifying a single VLAN * ID. The following operations determine which 32b entry * (i.e. offset) into the array we want to set the VLAN ID * (i.e. bit) of the manageability unit. */ vfta_offset = (hw->mng_cookie.vlan_id >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK); } } for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { /* If the offset we want to clear is the same offset of the * manageability VLAN ID, then clear all bits except that of the * manageability unit */ vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); } } int32_t em_id_led_init(struct em_hw * hw) { uint32_t ledctl; const uint32_t ledctl_mask = 0x000000FF; const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; uint16_t eeprom_data, i, temp; const uint16_t led_mask = 0x0F; DEBUGFUNC("em_id_led_init"); if(hw->mac_type < em_82540) { /* Nothing to do */ return E1000_SUCCESS; } ledctl = E1000_READ_REG(hw, LEDCTL); hw->ledctl_default = ledctl; hw->ledctl_mode1 = hw->ledctl_default; hw->ledctl_mode2 = hw->ledctl_default; if(em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } if((eeprom_data== ID_LED_RESERVED_0000) || (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; for(i = 0; i < 4; i++) { temp = (eeprom_data >> (i << 2)) & led_mask; switch(temp) { case ID_LED_ON1_DEF2: case ID_LED_ON1_ON2: case ID_LED_ON1_OFF2: hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); hw->ledctl_mode1 |= ledctl_on << (i << 3); break; case ID_LED_OFF1_DEF2: case ID_LED_OFF1_ON2: case ID_LED_OFF1_OFF2: hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); hw->ledctl_mode1 |= ledctl_off << (i << 3); break; default: /* Do nothing */ break; } switch(temp) { case ID_LED_DEF1_ON2: case ID_LED_ON1_ON2: case ID_LED_OFF1_ON2: hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); hw->ledctl_mode2 |= ledctl_on << (i << 3); break; case ID_LED_DEF1_OFF2: case ID_LED_ON1_OFF2: case ID_LED_OFF1_OFF2: hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); hw->ledctl_mode2 |= ledctl_off << (i << 3); break; default: /* Do nothing */ break; } } return E1000_SUCCESS; } /****************************************************************************** * Prepares SW controlable LED for use and saves the current state of the LED. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_setup_led(struct em_hw *hw) { uint32_t ledctl; int32_t ret_val = E1000_SUCCESS; DEBUGFUNC("em_setup_led"); switch(hw->mac_type) { case em_82542_rev2_0: case em_82542_rev2_1: case em_82543: case em_82544: /* No setup necessary */ break; case em_82541: case em_82547: case em_82541_rev_2: case em_82547_rev_2: /* Turn off PHY Smart Power Down (if enabled) */ ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &hw->phy_spd_default); if(ret_val) return ret_val; ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, (uint16_t)(hw->phy_spd_default & ~IGP01E1000_GMII_SPD)); if(ret_val) return ret_val; /* Fall Through */ default: if(hw->media_type == em_media_type_fiber) { ledctl = E1000_READ_REG(hw, LEDCTL); /* Save current LEDCTL settings */ hw->ledctl_default = ledctl; /* Turn off LED0 */ ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | E1000_LEDCTL_LED0_MODE_MASK); ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT); E1000_WRITE_REG(hw, LEDCTL, ledctl); } else if(hw->media_type == em_media_type_copper) E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); break; } return E1000_SUCCESS; } /****************************************************************************** * Restores the saved state of the SW controlable LED. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_cleanup_led(struct em_hw *hw) { int32_t ret_val = E1000_SUCCESS; DEBUGFUNC("em_cleanup_led"); switch(hw->mac_type) { case em_82542_rev2_0: case em_82542_rev2_1: case em_82543: case em_82544: /* No cleanup necessary */ break; case em_82541: case em_82547: case em_82541_rev_2: case em_82547_rev_2: /* Turn on PHY Smart Power Down (if previously enabled) */ ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, hw->phy_spd_default); if(ret_val) return ret_val; /* Fall Through */ default: /* Restore LEDCTL settings */ E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); break; } return E1000_SUCCESS; } /****************************************************************************** * Turns on the software controllable LED * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_led_on(struct em_hw *hw) { uint32_t ctrl = E1000_READ_REG(hw, CTRL); DEBUGFUNC("em_led_on"); switch(hw->mac_type) { case em_82542_rev2_0: case em_82542_rev2_1: case em_82543: /* Set SW Defineable Pin 0 to turn on the LED */ ctrl |= E1000_CTRL_SWDPIN0; ctrl |= E1000_CTRL_SWDPIO0; break; case em_82544: if(hw->media_type == em_media_type_fiber) { /* Set SW Defineable Pin 0 to turn on the LED */ ctrl |= E1000_CTRL_SWDPIN0; ctrl |= E1000_CTRL_SWDPIO0; } else { /* Clear SW Defineable Pin 0 to turn on the LED */ ctrl &= ~E1000_CTRL_SWDPIN0; ctrl |= E1000_CTRL_SWDPIO0; } break; default: if(hw->media_type == em_media_type_fiber) { /* Clear SW Defineable Pin 0 to turn on the LED */ ctrl &= ~E1000_CTRL_SWDPIN0; ctrl |= E1000_CTRL_SWDPIO0; } else if(hw->media_type == em_media_type_copper) { E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); return E1000_SUCCESS; } break; } E1000_WRITE_REG(hw, CTRL, ctrl); return E1000_SUCCESS; } /****************************************************************************** * Turns off the software controllable LED * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t em_led_off(struct em_hw *hw) { uint32_t ctrl = E1000_READ_REG(hw, CTRL); DEBUGFUNC("em_led_off"); switch(hw->mac_type) { case em_82542_rev2_0: case em_82542_rev2_1: case em_82543: /* Clear SW Defineable Pin 0 to turn off the LED */ ctrl &= ~E1000_CTRL_SWDPIN0; ctrl |= E1000_CTRL_SWDPIO0; break; case em_82544: if(hw->media_type == em_media_type_fiber) { /* Clear SW Defineable Pin 0 to turn off the LED */ ctrl &= ~E1000_CTRL_SWDPIN0; ctrl |= E1000_CTRL_SWDPIO0; } else { /* Set SW Defineable Pin 0 to turn off the LED */ ctrl |= E1000_CTRL_SWDPIN0; ctrl |= E1000_CTRL_SWDPIO0; } break; default: if(hw->media_type == em_media_type_fiber) { /* Set SW Defineable Pin 0 to turn off the LED */ ctrl |= E1000_CTRL_SWDPIN0; ctrl |= E1000_CTRL_SWDPIO0; } else if(hw->media_type == em_media_type_copper) { E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); return E1000_SUCCESS; } break; } E1000_WRITE_REG(hw, CTRL, ctrl); return E1000_SUCCESS; } /****************************************************************************** * Clears all hardware statistics counters. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ void em_clear_hw_cntrs(struct em_hw *hw) { volatile uint32_t temp; temp = E1000_READ_REG(hw, CRCERRS); temp = E1000_READ_REG(hw, SYMERRS); temp = E1000_READ_REG(hw, MPC); temp = E1000_READ_REG(hw, SCC); temp = E1000_READ_REG(hw, ECOL); temp = E1000_READ_REG(hw, MCC); temp = E1000_READ_REG(hw, LATECOL); temp = E1000_READ_REG(hw, COLC); temp = E1000_READ_REG(hw, DC); temp = E1000_READ_REG(hw, SEC); temp = E1000_READ_REG(hw, RLEC); temp = E1000_READ_REG(hw, XONRXC); temp = E1000_READ_REG(hw, XONTXC); temp = E1000_READ_REG(hw, XOFFRXC); temp = E1000_READ_REG(hw, XOFFTXC); temp = E1000_READ_REG(hw, FCRUC); temp = E1000_READ_REG(hw, PRC64); temp = E1000_READ_REG(hw, PRC127); temp = E1000_READ_REG(hw, PRC255); temp = E1000_READ_REG(hw, PRC511); temp = E1000_READ_REG(hw, PRC1023); temp = E1000_READ_REG(hw, PRC1522); temp = E1000_READ_REG(hw, GPRC); temp = E1000_READ_REG(hw, BPRC); temp = E1000_READ_REG(hw, MPRC); temp = E1000_READ_REG(hw, GPTC); temp = E1000_READ_REG(hw, GORCL); temp = E1000_READ_REG(hw, GORCH); temp = E1000_READ_REG(hw, GOTCL); temp = E1000_READ_REG(hw, GOTCH); temp = E1000_READ_REG(hw, RNBC); temp = E1000_READ_REG(hw, RUC); temp = E1000_READ_REG(hw, RFC); temp = E1000_READ_REG(hw, ROC); temp = E1000_READ_REG(hw, RJC); temp = E1000_READ_REG(hw, TORL); temp = E1000_READ_REG(hw, TORH); temp = E1000_READ_REG(hw, TOTL); temp = E1000_READ_REG(hw, TOTH); temp = E1000_READ_REG(hw, TPR); temp = E1000_READ_REG(hw, TPT); temp = E1000_READ_REG(hw, PTC64); temp = E1000_READ_REG(hw, PTC127); temp = E1000_READ_REG(hw, PTC255); temp = E1000_READ_REG(hw, PTC511); temp = E1000_READ_REG(hw, PTC1023); temp = E1000_READ_REG(hw, PTC1522); temp = E1000_READ_REG(hw, MPTC); temp = E1000_READ_REG(hw, BPTC); if(hw->mac_type < em_82543) return; temp = E1000_READ_REG(hw, ALGNERRC); temp = E1000_READ_REG(hw, RXERRC); temp = E1000_READ_REG(hw, TNCRS); temp = E1000_READ_REG(hw, CEXTERR); temp = E1000_READ_REG(hw, TSCTC); temp = E1000_READ_REG(hw, TSCTFC); if(hw->mac_type <= em_82544) return; temp = E1000_READ_REG(hw, MGTPRC); temp = E1000_READ_REG(hw, MGTPDC); temp = E1000_READ_REG(hw, MGTPTC); if(hw->mac_type <= em_82547_rev_2) return; temp = E1000_READ_REG(hw, IAC); temp = E1000_READ_REG(hw, ICRXOC); temp = E1000_READ_REG(hw, ICRXPTC); temp = E1000_READ_REG(hw, ICRXATC); temp = E1000_READ_REG(hw, ICTXPTC); temp = E1000_READ_REG(hw, ICTXATC); temp = E1000_READ_REG(hw, ICTXQEC); temp = E1000_READ_REG(hw, ICTXQMTC); temp = E1000_READ_REG(hw, ICRXDMTC); } /****************************************************************************** * Resets Adaptive IFS to its default state. * * hw - Struct containing variables accessed by shared code * * Call this after em_init_hw. You may override the IFS defaults by setting * hw->ifs_params_forced to TRUE. However, you must initialize hw-> * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio * before calling this function. *****************************************************************************/ void em_reset_adaptive(struct em_hw *hw) { DEBUGFUNC("em_reset_adaptive"); if(hw->adaptive_ifs) { if(!hw->ifs_params_forced) { hw->current_ifs_val = 0; hw->ifs_min_val = IFS_MIN; hw->ifs_max_val = IFS_MAX; hw->ifs_step_size = IFS_STEP; hw->ifs_ratio = IFS_RATIO; } hw->in_ifs_mode = FALSE; E1000_WRITE_REG(hw, AIT, 0); } else { DEBUGOUT("Not in Adaptive IFS mode!\n"); } } /****************************************************************************** * Called during the callback/watchdog routine to update IFS value based on * the ratio of transmits to collisions. * * hw - Struct containing variables accessed by shared code * tx_packets - Number of transmits since last callback * total_collisions - Number of collisions since last callback *****************************************************************************/ void em_update_adaptive(struct em_hw *hw) { DEBUGFUNC("em_update_adaptive"); if(hw->adaptive_ifs) { if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { if(hw->tx_packet_delta > MIN_NUM_XMITS) { hw->in_ifs_mode = TRUE; if(hw->current_ifs_val < hw->ifs_max_val) { if(hw->current_ifs_val == 0) hw->current_ifs_val = hw->ifs_min_val; else hw->current_ifs_val += hw->ifs_step_size; E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); } } } else { if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { hw->current_ifs_val = 0; hw->in_ifs_mode = FALSE; E1000_WRITE_REG(hw, AIT, 0); } } } else { DEBUGOUT("Not in Adaptive IFS mode!\n"); } } /****************************************************************************** * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT * * hw - Struct containing variables accessed by shared code * frame_len - The length of the frame in question * mac_addr - The Ethernet destination address of the frame in question *****************************************************************************/ void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t *mac_addr) { uint64_t carry_bit; /* First adjust the frame length. */ frame_len--; /* We need to adjust the statistics counters, since the hardware * counters overcount this packet as a CRC error and undercount * the packet as a good packet */ /* This packet should not be counted as a CRC error. */ stats->crcerrs--; /* This packet does count as a Good Packet Received. */ stats->gprc++; /* Adjust the Good Octets received counters */ carry_bit = 0x80000000 & stats->gorcl; stats->gorcl += frame_len; /* If the high bit of Gorcl (the low 32 bits of the Good Octets * Received Count) was one before the addition, * AND it is zero after, then we lost the carry out, * need to add one to Gorch (Good Octets Received Count High). * This could be simplified if all environments supported * 64-bit integers. */ if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) stats->gorch++; /* Is this a broadcast or multicast? Check broadcast first, * since the test for a multicast frame will test positive on * a broadcast frame. */ if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) /* Broadcast packet */ stats->bprc++; else if(*mac_addr & 0x01) /* Multicast packet */ stats->mprc++; if(frame_len == hw->max_frame_size) { /* In this case, the hardware has overcounted the number of * oversize frames. */ if(stats->roc > 0) stats->roc--; } /* Adjust the bin counters when the extra byte put the frame in the * wrong bin. Remember that the frame_len was adjusted above. */ if(frame_len == 64) { stats->prc64++; stats->prc127--; } else if(frame_len == 127) { stats->prc127++; stats->prc255--; } else if(frame_len == 255) { stats->prc255++; stats->prc511--; } else if(frame_len == 511) { stats->prc511++; stats->prc1023--; } else if(frame_len == 1023) { stats->prc1023++; stats->prc1522--; } else if(frame_len == 1522) { stats->prc1522++; } } /****************************************************************************** * Gets the current PCI bus type, speed, and width of the hardware * * hw - Struct containing variables accessed by shared code *****************************************************************************/ void em_get_bus_info(struct em_hw *hw) { uint32_t status; switch (hw->mac_type) { case em_82542_rev2_0: case em_82542_rev2_1: hw->bus_type = em_bus_type_unknown; hw->bus_speed = em_bus_speed_unknown; hw->bus_width = em_bus_width_unknown; break; + case em_82572: case em_82573: hw->bus_type = em_bus_type_pci_express; hw->bus_speed = em_bus_speed_2500; + hw->bus_width = em_bus_width_pciex_1; + break; + case em_82571: + hw->bus_type = em_bus_type_pci_express; + hw->bus_speed = em_bus_speed_2500; hw->bus_width = em_bus_width_pciex_4; break; default: status = E1000_READ_REG(hw, STATUS); hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? em_bus_type_pcix : em_bus_type_pci; if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? em_bus_speed_66 : em_bus_speed_120; } else if(hw->bus_type == em_bus_type_pci) { hw->bus_speed = (status & E1000_STATUS_PCI66) ? em_bus_speed_66 : em_bus_speed_33; } else { switch (status & E1000_STATUS_PCIX_SPEED) { case E1000_STATUS_PCIX_SPEED_66: hw->bus_speed = em_bus_speed_66; break; case E1000_STATUS_PCIX_SPEED_100: hw->bus_speed = em_bus_speed_100; break; case E1000_STATUS_PCIX_SPEED_133: hw->bus_speed = em_bus_speed_133; break; default: hw->bus_speed = em_bus_speed_reserved; break; } } hw->bus_width = (status & E1000_STATUS_BUS64) ? em_bus_width_64 : em_bus_width_32; break; } } /****************************************************************************** * Reads a value from one of the devices registers using port I/O (as opposed * memory mapped I/O). Only 82544 and newer devices support port I/O. * * hw - Struct containing variables accessed by shared code * offset - offset to read from *****************************************************************************/ uint32_t em_read_reg_io(struct em_hw *hw, uint32_t offset) { unsigned long io_addr = hw->io_base; unsigned long io_data = hw->io_base + 4; em_io_write(hw, io_addr, offset); return em_io_read(hw, io_data); } /****************************************************************************** * Writes a value to one of the devices registers using port I/O (as opposed to * memory mapped I/O). Only 82544 and newer devices support port I/O. * * hw - Struct containing variables accessed by shared code * offset - offset to write to * value - value to write *****************************************************************************/ void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) { unsigned long io_addr = hw->io_base; unsigned long io_data = hw->io_base + 4; em_io_write(hw, io_addr, offset); em_io_write(hw, io_data, value); } /****************************************************************************** * Estimates the cable length. * * hw - Struct containing variables accessed by shared code * min_length - The estimated minimum length * max_length - The estimated maximum length * * returns: - E1000_ERR_XXX * E1000_SUCCESS * * This function always returns a ranged length (minimum & maximum). * So for M88 phy's, this function interprets the one value returned from the * register to the minimum and maximum range. * For IGP phy's, the function calculates the range by the AGC registers. *****************************************************************************/ int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length) { int32_t ret_val; uint16_t agc_value = 0; uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE; + uint16_t max_agc = 0; uint16_t i, phy_data; uint16_t cable_length; DEBUGFUNC("em_get_cable_length"); *min_length = *max_length = 0; /* Use old method for Phy older than IGP */ if(hw->phy_type == em_phy_m88) { ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); if(ret_val) return ret_val; cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> M88E1000_PSSR_CABLE_LENGTH_SHIFT; /* Convert the enum value to ranged values */ switch (cable_length) { case em_cable_length_50: *min_length = 0; *max_length = em_igp_cable_length_50; break; case em_cable_length_50_80: *min_length = em_igp_cable_length_50; *max_length = em_igp_cable_length_80; break; case em_cable_length_80_110: *min_length = em_igp_cable_length_80; *max_length = em_igp_cable_length_110; break; case em_cable_length_110_140: *min_length = em_igp_cable_length_110; *max_length = em_igp_cable_length_140; break; case em_cable_length_140: *min_length = em_igp_cable_length_140; *max_length = em_igp_cable_length_170; break; default: return -E1000_ERR_PHY; break; } } else if(hw->phy_type == em_phy_igp) { /* For IGP PHY */ uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; /* Read the AGC registers for all channels */ for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data); if(ret_val) return ret_val; cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; /* Array bound check. */ if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || (cur_agc == 0)) return -E1000_ERR_PHY; agc_value += cur_agc; /* Update minimal AGC value. */ if(min_agc > cur_agc) min_agc = cur_agc; } /* Remove the minimal AGC result for length < 50m */ if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) { agc_value -= min_agc; /* Get the average length of the remaining 3 channels */ agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); } else { /* Get the average length of all the 4 channels. */ agc_value /= IGP01E1000_PHY_CHANNEL_NUM; } /* Set the range of the calculated length. */ *min_length = ((em_igp_cable_length_table[agc_value] - IGP01E1000_AGC_RANGE) > 0) ? (em_igp_cable_length_table[agc_value] - IGP01E1000_AGC_RANGE) : 0; *max_length = em_igp_cable_length_table[agc_value] + IGP01E1000_AGC_RANGE; + } else if (hw->phy_type == em_phy_igp_2) { + uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = + {IGP02E1000_PHY_AGC_A, + IGP02E1000_PHY_AGC_B, + IGP02E1000_PHY_AGC_C, + IGP02E1000_PHY_AGC_D}; + + /* Read the AGC registers for all channels */ + for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { + ret_val = em_read_phy_reg(hw, agc_reg_array[i], + &phy_data); + if (ret_val) + return ret_val; + + /* + * Getting bits 15:9, which represent the combination + * of course and fine gain values. The result is a + * number that can be put into the lookup table to + * obtain the approximate cable length. + */ + cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & + IGP02E1000_AGC_LENGTH_MASK; + + /* Remove min & max AGC values from calculation. */ + if (em_igp_2_cable_length_table[min_agc] > + em_igp_2_cable_length_table[cur_agc]) + min_agc = cur_agc; + if (em_igp_2_cable_length_table[max_agc] < + em_igp_2_cable_length_table[cur_agc]) + max_agc = cur_agc; + + agc_value += em_igp_2_cable_length_table[cur_agc]; + } + + agc_value -= (em_igp_2_cable_length_table[min_agc] + + em_igp_2_cable_length_table[max_agc]); + agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); + + /* + * Calculate cable length with the error range + * of +/- 10 meters. + */ + *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? + (agc_value - IGP02E1000_AGC_RANGE) : 0; + *max_length = agc_value + IGP02E1000_AGC_RANGE; } return E1000_SUCCESS; } /****************************************************************************** * Check the cable polarity * * hw - Struct containing variables accessed by shared code * polarity - output parameter : 0 - Polarity is not reversed * 1 - Polarity is reversed. * * returns: - E1000_ERR_XXX * E1000_SUCCESS * * For phy's older then IGP, this function simply reads the polarity bit in the * Phy Status register. For IGP phy's, this bit is valid only if link speed is * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will * return 0. If the link speed is 1000 Mbps the polarity status is in the * IGP01E1000_PHY_PCS_INIT_REG. *****************************************************************************/ int32_t em_check_polarity(struct em_hw *hw, uint16_t *polarity) { int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_check_polarity"); if(hw->phy_type == em_phy_m88) { /* return the Polarity bit in the Status register. */ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); if(ret_val) return ret_val; *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> M88E1000_PSSR_REV_POLARITY_SHIFT; } else if(hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) { /* Read the Status register to check the speed */ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); if(ret_val) return ret_val; /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to * find the polarity status */ if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == IGP01E1000_PSSR_SPEED_1000MBPS) { /* Read the GIG initialization PCS register (0x00B4) */ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, &phy_data); if(ret_val) return ret_val; /* Check the polarity bits */ *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0; } else { /* For 10 Mbps, read the polarity bit in the status register. (for * 100 Mbps this bit is always 0) */ *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; } } return E1000_SUCCESS; } /****************************************************************************** * Check if Downshift occured * * hw - Struct containing variables accessed by shared code * downshift - output parameter : 0 - No Downshift ocured. * 1 - Downshift ocured. * * returns: - E1000_ERR_XXX * E1000_SUCCESS * * For phy's older then IGP, this function reads the Downshift bit in the Phy * Specific Status register. For IGP phy's, it reads the Downgrade bit in the * Link Health register. In IGP this bit is latched high, so the driver must * read it immediately after link is established. *****************************************************************************/ int32_t em_check_downshift(struct em_hw *hw) { int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_check_downshift"); if(hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) { ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, &phy_data); if(ret_val) return ret_val; hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; } else if(hw->phy_type == em_phy_m88) { ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); if(ret_val) return ret_val; hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> M88E1000_PSSR_DOWNSHIFT_SHIFT; } return E1000_SUCCESS; } /***************************************************************************** * * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a * gigabit link is achieved to improve link quality. * * hw: Struct containing variables accessed by shared code * * returns: - E1000_ERR_PHY if fail to read/write the PHY * E1000_SUCCESS at any other case. * ****************************************************************************/ int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) { int32_t ret_val; uint16_t phy_data, phy_saved_data, speed, duplex, i; uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; uint16_t min_length, max_length; DEBUGFUNC("em_config_dsp_after_link_change"); if(hw->phy_type != em_phy_igp) return E1000_SUCCESS; if(link_up) { ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); if(ret_val) { DEBUGOUT("Error getting link speed and duplex\n"); return ret_val; } if(speed == SPEED_1000) { em_get_cable_length(hw, &min_length, &max_length); if((hw->dsp_config_state == em_dsp_config_enabled) && min_length >= em_igp_cable_length_50) { for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data); if(ret_val) return ret_val; phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; ret_val = em_write_phy_reg(hw, dsp_reg_array[i], phy_data); if(ret_val) return ret_val; } hw->dsp_config_state = em_dsp_config_activated; } if((hw->ffe_config_state == em_ffe_config_enabled) && (min_length < em_igp_cable_length_50)) { uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; uint32_t idle_errs = 0; /* clear previous idle error counts */ ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); if(ret_val) return ret_val; for(i = 0; i < ffe_idle_err_timeout; i++) { usec_delay(1000); ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); if(ret_val) return ret_val; idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { hw->ffe_config_state = em_ffe_config_active; ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, IGP01E1000_PHY_DSP_FFE_CM_CP); if(ret_val) return ret_val; break; } if(idle_errs) ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; } } } } else { if(hw->dsp_config_state == em_dsp_config_activated) { /* Save off the current value of register 0x2F5B to be restored at * the end of the routines. */ ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); if(ret_val) return ret_val; /* Disable the PHY transmitter */ ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); if(ret_val) return ret_val; msec_delay_irq(20); ret_val = em_write_phy_reg(hw, 0x0000, IGP01E1000_IEEE_FORCE_GIGA); if(ret_val) return ret_val; for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data); if(ret_val) return ret_val; phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; ret_val = em_write_phy_reg(hw,dsp_reg_array[i], phy_data); if(ret_val) return ret_val; } ret_val = em_write_phy_reg(hw, 0x0000, IGP01E1000_IEEE_RESTART_AUTONEG); if(ret_val) return ret_val; msec_delay_irq(20); /* Now enable the transmitter */ ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); if(ret_val) return ret_val; hw->dsp_config_state = em_dsp_config_enabled; } if(hw->ffe_config_state == em_ffe_config_active) { /* Save off the current value of register 0x2F5B to be restored at * the end of the routines. */ ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); if(ret_val) return ret_val; /* Disable the PHY transmitter */ ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); if(ret_val) return ret_val; msec_delay_irq(20); ret_val = em_write_phy_reg(hw, 0x0000, IGP01E1000_IEEE_FORCE_GIGA); if(ret_val) return ret_val; ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, IGP01E1000_PHY_DSP_FFE_DEFAULT); if(ret_val) return ret_val; ret_val = em_write_phy_reg(hw, 0x0000, IGP01E1000_IEEE_RESTART_AUTONEG); if(ret_val) return ret_val; msec_delay_irq(20); /* Now enable the transmitter */ ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); if(ret_val) return ret_val; hw->ffe_config_state = em_ffe_config_enabled; } } return E1000_SUCCESS; } /***************************************************************************** * Set PHY to class A mode * Assumes the following operations will follow to enable the new class mode. * 1. Do a PHY soft reset * 2. Restart auto-negotiation or force link. * * hw - Struct containing variables accessed by shared code ****************************************************************************/ static int32_t em_set_phy_mode(struct em_hw *hw) { int32_t ret_val; uint16_t eeprom_data; DEBUGFUNC("em_set_phy_mode"); if((hw->mac_type == em_82545_rev_3) && (hw->media_type == em_media_type_copper)) { ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); if(ret_val) { return ret_val; } if((eeprom_data != EEPROM_RESERVED_WORD) && (eeprom_data & EEPROM_PHY_CLASS_A)) { ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); if(ret_val) return ret_val; ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); if(ret_val) return ret_val; hw->phy_reset_disable = FALSE; } } return E1000_SUCCESS; } /***************************************************************************** * * This function sets the lplu state according to the active flag. When * activating lplu this function also disables smart speed and vise versa. * lplu will not be activated unless the device autonegotiation advertisment * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. * hw: Struct containing variables accessed by shared code * active - true to enable lplu false to disable lplu. * * returns: - E1000_ERR_PHY if fail to read/write the PHY * E1000_SUCCESS at any other case. * ****************************************************************************/ int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) { int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_set_d3_lplu_state"); if(hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2) return E1000_SUCCESS; /* During driver activity LPLU should not be used or it will attain link * from the lowest speeds starting from 10Mbps. The capability is used for * Dx transitions and states */ if(hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); if(ret_val) return ret_val; } else { ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); if(ret_val) return ret_val; } if(!active) { if(hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { phy_data &= ~IGP01E1000_GMII_FLEX_SPD; ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); if(ret_val) return ret_val; } else { phy_data &= ~IGP02E1000_PM_D3_LPLU; ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); if (ret_val) return ret_val; } /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during * Dx states where the power conservation is most important. During * driver activity we should enable SmartSpeed, so performance is * maintained. */ if (hw->smart_speed == em_smart_speed_on) { ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); if(ret_val) return ret_val; phy_data |= IGP01E1000_PSCFR_SMART_SPEED; ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); if(ret_val) return ret_val; } else if (hw->smart_speed == em_smart_speed_off) { ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); if (ret_val) return ret_val; phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); if(ret_val) return ret_val; } } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { if(hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { phy_data |= IGP01E1000_GMII_FLEX_SPD; ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); if(ret_val) return ret_val; } else { phy_data |= IGP02E1000_PM_D3_LPLU; ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); if (ret_val) return ret_val; } /* When LPLU is enabled we should disable SmartSpeed */ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); if(ret_val) return ret_val; phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); if(ret_val) return ret_val; } return E1000_SUCCESS; } /***************************************************************************** * * This function sets the lplu d0 state according to the active flag. When * activating lplu this function also disables smart speed and vise versa. * lplu will not be activated unless the device autonegotiation advertisment * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. * hw: Struct containing variables accessed by shared code * active - true to enable lplu false to disable lplu. * * returns: - E1000_ERR_PHY if fail to read/write the PHY * E1000_SUCCESS at any other case. * ****************************************************************************/ int32_t em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) { int32_t ret_val; uint16_t phy_data; DEBUGFUNC("em_set_d0_lplu_state"); if(hw->mac_type <= em_82547_rev_2) return E1000_SUCCESS; ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); if(ret_val) return ret_val; if (!active) { phy_data &= ~IGP02E1000_PM_D0_LPLU; ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); if (ret_val) return ret_val; /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during * Dx states where the power conservation is most important. During * driver activity we should enable SmartSpeed, so performance is * maintained. */ if (hw->smart_speed == em_smart_speed_on) { ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); if(ret_val) return ret_val; phy_data |= IGP01E1000_PSCFR_SMART_SPEED; ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); if(ret_val) return ret_val; } else if (hw->smart_speed == em_smart_speed_off) { ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); if (ret_val) return ret_val; phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); if(ret_val) return ret_val; } } else { phy_data |= IGP02E1000_PM_D0_LPLU; ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); if (ret_val) return ret_val; /* When LPLU is enabled we should disable SmartSpeed */ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); if(ret_val) return ret_val; phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); if(ret_val) return ret_val; } return E1000_SUCCESS; } /****************************************************************************** * Change VCO speed register to improve Bit Error Rate performance of SERDES. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static int32_t em_set_vco_speed(struct em_hw *hw) { int32_t ret_val; uint16_t default_page = 0; uint16_t phy_data; DEBUGFUNC("em_set_vco_speed"); switch(hw->mac_type) { case em_82545_rev_3: case em_82546_rev_3: break; default: return E1000_SUCCESS; } /* Set PHY register 30, page 5, bit 8 to 0 */ ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); if(ret_val) return ret_val; ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); if(ret_val) return ret_val; phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); if(ret_val) return ret_val; /* Set PHY register 30, page 4, bit 11 to 1 */ ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); if(ret_val) return ret_val; phy_data |= M88E1000_PHY_VCO_REG_BIT11; ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); if(ret_val) return ret_val; ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); if(ret_val) return ret_val; return E1000_SUCCESS; } /***************************************************************************** * This function reads the cookie from ARC ram. * * returns: - E1000_SUCCESS . ****************************************************************************/ int32_t em_host_if_read_cookie(struct em_hw * hw, uint8_t *buffer) { uint8_t i; uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; length = (length >> 2); offset = (offset >> 2); for (i = 0; i < length; i++) { *((uint32_t *) buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); } return E1000_SUCCESS; } /***************************************************************************** * This function checks whether the HOST IF is enabled for command operaton * and also checks whether the previous command is completed. * It busy waits in case of previous command is not completed. * * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or * timeout * - E1000_SUCCESS for success. ****************************************************************************/ int32_t em_mng_enable_host_if(struct em_hw * hw) { uint32_t hicr; uint8_t i; /* Check that the host interface is enabled. */ hicr = E1000_READ_REG(hw, HICR); if ((hicr & E1000_HICR_EN) == 0) { DEBUGOUT("E1000_HOST_EN bit disabled.\n"); return -E1000_ERR_HOST_INTERFACE_COMMAND; } /* check the previous command is completed */ for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { hicr = E1000_READ_REG(hw, HICR); if (!(hicr & E1000_HICR_C)) break; msec_delay_irq(1); } if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { DEBUGOUT("Previous command timeout failed .\n"); return -E1000_ERR_HOST_INTERFACE_COMMAND; } return E1000_SUCCESS; } /***************************************************************************** * This function writes the buffer content at the offset given on the host if. * It also does alignment considerations to do the writes in most efficient way. * Also fills up the sum of the buffer in *buffer parameter. * * returns - E1000_SUCCESS for success. ****************************************************************************/ int32_t em_mng_host_if_write(struct em_hw * hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum) { uint8_t *tmp; uint8_t *bufptr = buffer; uint32_t data; uint16_t remaining, i, j, prev_bytes; /* sum = only sum of the data and it is not checksum */ if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { return -E1000_ERR_PARAM; } tmp = (uint8_t *)&data; prev_bytes = offset & 0x3; offset &= 0xFFFC; offset >>= 2; if (prev_bytes) { data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); for (j = prev_bytes; j < sizeof(uint32_t); j++) { *(tmp + j) = *bufptr++; *sum += *(tmp + j); } E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); length -= j - prev_bytes; offset++; } remaining = length & 0x3; length -= remaining; /* Calculate length in DWORDs */ length >>= 2; /* The device driver writes the relevant command block into the * ram area. */ for (i = 0; i < length; i++) { for (j = 0; j < sizeof(uint32_t); j++) { *(tmp + j) = *bufptr++; *sum += *(tmp + j); } E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); } if (remaining) { for (j = 0; j < sizeof(uint32_t); j++) { if (j < remaining) *(tmp + j) = *bufptr++; else *(tmp + j) = 0; *sum += *(tmp + j); } E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); } return E1000_SUCCESS; } /***************************************************************************** * This function writes the command header after does the checksum calculation. * * returns - E1000_SUCCESS for success. ****************************************************************************/ int32_t em_mng_write_cmd_header(struct em_hw * hw, struct em_host_mng_command_header * hdr) { uint16_t i; uint8_t sum; uint8_t *buffer; /* Write the whole command header structure which includes sum of * the buffer */ uint16_t length = sizeof(struct em_host_mng_command_header); sum = hdr->checksum; hdr->checksum = 0; buffer = (uint8_t *) hdr; i = length; while(i--) sum += buffer[i]; hdr->checksum = 0 - sum; length >>= 2; /* The device driver writes the relevant command block into the ram area. */ for (i = 0; i < length; i++) E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); return E1000_SUCCESS; } /***************************************************************************** * This function indicates to ARC that a new command is pending which completes * one write operation by the driver. * * returns - E1000_SUCCESS for success. ****************************************************************************/ int32_t em_mng_write_commit( struct em_hw * hw) { uint32_t hicr; hicr = E1000_READ_REG(hw, HICR); /* Setting this bit tells the ARC that a new command is pending. */ E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); return E1000_SUCCESS; } /***************************************************************************** * This function checks the mode of the firmware. * * returns - TRUE when the mode is IAMT or FALSE. ****************************************************************************/ boolean_t em_check_mng_mode( struct em_hw *hw) { uint32_t fwsm; fwsm = E1000_READ_REG(hw, FWSM); if((fwsm & E1000_FWSM_MODE_MASK) == (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) return TRUE; return FALSE; } /***************************************************************************** * This function writes the dhcp info . ****************************************************************************/ int32_t em_mng_write_dhcp_info(struct em_hw * hw, uint8_t *buffer, uint16_t length) { int32_t ret_val; struct em_host_mng_command_header hdr; hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; hdr.command_length = length; hdr.reserved1 = 0; hdr.reserved2 = 0; hdr.checksum = 0; ret_val = em_mng_enable_host_if(hw); if (ret_val == E1000_SUCCESS) { ret_val = em_mng_host_if_write(hw, buffer, length, sizeof(hdr), &(hdr.checksum)); if (ret_val == E1000_SUCCESS) { ret_val = em_mng_write_cmd_header(hw, &hdr); if (ret_val == E1000_SUCCESS) ret_val = em_mng_write_commit(hw); } } return ret_val; } /***************************************************************************** * This function calculates the checksum. * * returns - checksum of buffer contents. ****************************************************************************/ uint8_t em_calculate_mng_checksum(char *buffer, uint32_t length) { uint8_t sum = 0; uint32_t i; if (!buffer) return 0; for (i=0; i < length; i++) sum += buffer[i]; return (uint8_t) (0 - sum); } /***************************************************************************** * This function checks whether tx pkt filtering needs to be enabled or not. * * returns - TRUE for packet filtering or FALSE. ****************************************************************************/ boolean_t em_enable_tx_pkt_filtering(struct em_hw *hw) { /* called in init as well as watchdog timer functions */ int32_t ret_val, checksum; boolean_t tx_filter = FALSE; struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); if (em_check_mng_mode(hw)) { ret_val = em_mng_enable_host_if(hw); if (ret_val == E1000_SUCCESS) { ret_val = em_host_if_read_cookie(hw, buffer); if (ret_val == E1000_SUCCESS) { checksum = hdr->checksum; hdr->checksum = 0; if ((hdr->signature == E1000_IAMT_SIGNATURE) && checksum == em_calculate_mng_checksum((char *)buffer, E1000_MNG_DHCP_COOKIE_LENGTH)) { if (hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) tx_filter = TRUE; } else tx_filter = TRUE; } else tx_filter = TRUE; } } hw->tx_pkt_filtering = tx_filter; return tx_filter; } /****************************************************************************** * Verifies the hardware needs to allow ARPs to be processed by the host * * hw - Struct containing variables accessed by shared code * * returns: - TRUE/FALSE * *****************************************************************************/ uint32_t em_enable_mng_pass_thru(struct em_hw *hw) { uint32_t manc; uint32_t fwsm, factps; if (hw->asf_firmware_present) { manc = E1000_READ_REG(hw, MANC); if (!(manc & E1000_MANC_RCV_TCO_EN) || !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) return FALSE; if (em_arc_subsystem_valid(hw) == TRUE) { fwsm = E1000_READ_REG(hw, FWSM); factps = E1000_READ_REG(hw, FACTPS); if (((fwsm & E1000_FWSM_MODE_MASK) == (em_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) && (factps & E1000_FACTPS_MNGCG)) return TRUE; } else if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) return TRUE; } return FALSE; } static int32_t em_polarity_reversal_workaround(struct em_hw *hw) { int32_t ret_val; uint16_t mii_status_reg; uint16_t i; /* Polarity reversal workaround for forced 10F/10H links. */ /* Disable the transmitter on the PHY */ ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); if(ret_val) return ret_val; ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); if(ret_val) return ret_val; ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); if(ret_val) return ret_val; /* This loop will early-out if the NO link condition has been met. */ for(i = PHY_FORCE_TIME; i > 0; i--) { /* Read the MII Status Register and wait for Link Status bit * to be clear. */ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); if(ret_val) return ret_val; if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; msec_delay_irq(100); } /* Recommended delay time after link has been lost */ msec_delay_irq(1000); /* Now we will re-enable th transmitter on the PHY */ ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); if(ret_val) return ret_val; msec_delay_irq(50); ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); if(ret_val) return ret_val; msec_delay_irq(50); ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); if(ret_val) return ret_val; msec_delay_irq(50); ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); if(ret_val) return ret_val; ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); if(ret_val) return ret_val; /* This loop will early-out if the link condition has been met. */ for(i = PHY_FORCE_TIME; i > 0; i--) { /* Read the MII Status Register and wait for Link Status bit * to be set. */ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); if(ret_val) return ret_val; ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); if(ret_val) return ret_val; if(mii_status_reg & MII_SR_LINK_STATUS) break; msec_delay_irq(100); } return E1000_SUCCESS; } /*************************************************************************** * * Disables PCI-Express master access. * * hw: Struct containing variables accessed by shared code * * returns: - none. * ***************************************************************************/ void em_set_pci_express_master_disable(struct em_hw *hw) { uint32_t ctrl; DEBUGFUNC("em_set_pci_express_master_disable"); if (hw->bus_type != em_bus_type_pci_express) return; ctrl = E1000_READ_REG(hw, CTRL); ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; E1000_WRITE_REG(hw, CTRL, ctrl); } /*************************************************************************** * * Enables PCI-Express master access. * * hw: Struct containing variables accessed by shared code * * returns: - none. * ***************************************************************************/ void em_enable_pciex_master(struct em_hw *hw) { uint32_t ctrl; DEBUGFUNC("em_enable_pciex_master"); if (hw->bus_type != em_bus_type_pci_express) return; ctrl = E1000_READ_REG(hw, CTRL); ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; E1000_WRITE_REG(hw, CTRL, ctrl); } /******************************************************************************* * * Disables PCI-Express master access and verifies there are no pending requests * * hw: Struct containing variables accessed by shared code * * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't * caused the master requests to be disabled. * E1000_SUCCESS master requests disabled. * ******************************************************************************/ int32_t em_disable_pciex_master(struct em_hw *hw) { int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ DEBUGFUNC("em_disable_pciex_master"); if (hw->bus_type != em_bus_type_pci_express) return E1000_SUCCESS; em_set_pci_express_master_disable(hw); while(timeout) { if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) break; else usec_delay(100); timeout--; } if(!timeout) { DEBUGOUT("Master requests are pending.\n"); return -E1000_ERR_MASTER_REQUESTS_PENDING; } return E1000_SUCCESS; } /******************************************************************************* * * Check for EEPROM Auto Read bit done. * * hw: Struct containing variables accessed by shared code * * returns: - E1000_ERR_RESET if fail to reset MAC * E1000_SUCCESS at any other case. * ******************************************************************************/ int32_t em_get_auto_rd_done(struct em_hw *hw) { int32_t timeout = AUTO_READ_DONE_TIMEOUT; DEBUGFUNC("em_get_auto_rd_done"); switch (hw->mac_type) { - default: - msec_delay(5); - break; case em_82573: + case em_82571: + case em_82572: while(timeout) { if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; else msec_delay(1); timeout--; } if(!timeout) { DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); return -E1000_ERR_RESET; } break; + default: + msec_delay(5); } + /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. + * Need to wait for PHY configuration completion before accessing NVM + * and PHY. */ + if (hw->mac_type == em_82573) + msec_delay(25); + return E1000_SUCCESS; } /*************************************************************************** * Checks if the PHY configuration is done * * hw: Struct containing variables accessed by shared code * * returns: - E1000_ERR_RESET if fail to reset MAC * E1000_SUCCESS at any other case. * ***************************************************************************/ int32_t em_get_phy_cfg_done(struct em_hw *hw) { - DEBUGFUNC("em_get_phy_cfg_done"); - - /* Simply wait for 10ms */ - msec_delay(10); - - return E1000_SUCCESS; + int32_t timeout = PHY_CFG_TIMEOUT; + uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; + + DEBUGFUNC("em_get_phy_cfg_done"); + + switch (hw->mac_type) { + case em_82571: + case em_82572: + while (timeout) { + if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) + break; + else + msec_delay(1); + timeout--; + } + + if (!timeout) { + DEBUGOUT("MNG configuration cycle has not completed.\n"); + return -E1000_ERR_RESET; + } + break; + default: + msec_delay(10); + } + + return E1000_SUCCESS; } /*************************************************************************** * * Using the combination of SMBI and SWESMBI semaphore bits when resetting * adapter or Eeprom access. * * hw: Struct containing variables accessed by shared code * * returns: - E1000_ERR_EEPROM if fail to access EEPROM. * E1000_SUCCESS at any other case. * ***************************************************************************/ int32_t em_get_hw_eeprom_semaphore(struct em_hw *hw) { int32_t timeout; uint32_t swsm; DEBUGFUNC("em_get_hw_eeprom_semaphore"); if(!hw->eeprom_semaphore_present) return E1000_SUCCESS; /* Get the FW semaphore. */ timeout = hw->eeprom.word_size + 1; while(timeout) { swsm = E1000_READ_REG(hw, SWSM); swsm |= E1000_SWSM_SWESMBI; E1000_WRITE_REG(hw, SWSM, swsm); /* if we managed to set the bit we got the semaphore. */ swsm = E1000_READ_REG(hw, SWSM); if(swsm & E1000_SWSM_SWESMBI) break; usec_delay(50); timeout--; } if(!timeout) { /* Release semaphores */ em_put_hw_eeprom_semaphore(hw); DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); return -E1000_ERR_EEPROM; } return E1000_SUCCESS; } /*************************************************************************** * This function clears HW semaphore bits. * * hw: Struct containing variables accessed by shared code * * returns: - None. * ***************************************************************************/ void em_put_hw_eeprom_semaphore(struct em_hw *hw) { uint32_t swsm; DEBUGFUNC("em_put_hw_eeprom_semaphore"); if(!hw->eeprom_semaphore_present) return; swsm = E1000_READ_REG(hw, SWSM); - /* Release both semaphores. */ - swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); + swsm &= ~(E1000_SWSM_SWESMBI); E1000_WRITE_REG(hw, SWSM, swsm); } /****************************************************************************** * Checks if PHY reset is blocked due to SOL/IDER session, for example. * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to * the caller to figure out how to deal with it. * * hw - Struct containing variables accessed by shared code * * returns: - E1000_BLK_PHY_RESET * E1000_SUCCESS * *****************************************************************************/ int32_t em_check_phy_reset_block(struct em_hw *hw) { uint32_t manc = 0; - if(hw->mac_type > em_82547_rev_2) + if (hw->mac_type > em_82547_rev_2) manc = E1000_READ_REG(hw, MANC); return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : E1000_SUCCESS; } uint8_t em_arc_subsystem_valid(struct em_hw *hw) { uint32_t fwsm; /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC * may not be provided a DMA clock when no manageability features are * enabled. We do not want to perform any reads/writes to these registers * if this is the case. We read FWSM to determine the manageability mode. */ switch (hw->mac_type) { + case em_82571: + case em_82572: case em_82573: fwsm = E1000_READ_REG(hw, FWSM); if((fwsm & E1000_FWSM_MODE_MASK) != 0) return TRUE; break; default: break; } return FALSE; } diff --git a/sys/dev/em/if_em_hw.h b/sys/dev/em/if_em_hw.h index 34b7304117e8..d23d2b6814e0 100644 --- a/sys/dev/em/if_em_hw.h +++ b/sys/dev/em/if_em_hw.h @@ -1,2689 +1,2765 @@ /******************************************************************************* Copyright (c) 2001-2005, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ /*$FreeBSD$*/ /* if_em_hw.h * Structures, enums, and macros for the MAC */ #ifndef _EM_HW_H_ #define _EM_HW_H_ #include /* Forward declarations of structures used by the shared code */ struct em_hw; struct em_hw_stats; /* Enumerated types specific to the e1000 hardware */ /* Media Access Controlers */ typedef enum { em_undefined = 0, em_82542_rev2_0, em_82542_rev2_1, em_82543, em_82544, em_82540, em_82545, em_82545_rev_3, em_82546, em_82546_rev_3, em_82541, em_82541_rev_2, em_82547, em_82547_rev_2, + em_82571, + em_82572, em_82573, em_num_macs } em_mac_type; typedef enum { em_eeprom_uninitialized = 0, em_eeprom_spi, em_eeprom_microwire, em_eeprom_flash, + em_eeprom_none, /* No NVM support */ em_num_eeprom_types } em_eeprom_type; /* Media Types */ typedef enum { em_media_type_copper = 0, em_media_type_fiber = 1, em_media_type_internal_serdes = 2, em_num_media_types } em_media_type; typedef enum { em_10_half = 0, em_10_full = 1, em_100_half = 2, em_100_full = 3 } em_speed_duplex_type; /* Flow Control Settings */ typedef enum { em_fc_none = 0, em_fc_rx_pause = 1, em_fc_tx_pause = 2, em_fc_full = 3, em_fc_default = 0xFF } em_fc_type; /* PCI bus types */ typedef enum { em_bus_type_unknown = 0, em_bus_type_pci, em_bus_type_pcix, em_bus_type_pci_express, em_bus_type_reserved } em_bus_type; /* PCI bus speeds */ typedef enum { em_bus_speed_unknown = 0, em_bus_speed_33, em_bus_speed_66, em_bus_speed_100, em_bus_speed_120, em_bus_speed_133, em_bus_speed_2500, em_bus_speed_reserved } em_bus_speed; /* PCI bus widths */ typedef enum { em_bus_width_unknown = 0, em_bus_width_32, em_bus_width_64, em_bus_width_pciex_1, + em_bus_width_pciex_2, em_bus_width_pciex_4, em_bus_width_reserved } em_bus_width; /* PHY status info structure and supporting enums */ typedef enum { em_cable_length_50 = 0, em_cable_length_50_80, em_cable_length_80_110, em_cable_length_110_140, em_cable_length_140, em_cable_length_undefined = 0xFF } em_cable_length; typedef enum { em_igp_cable_length_10 = 10, em_igp_cable_length_20 = 20, em_igp_cable_length_30 = 30, em_igp_cable_length_40 = 40, em_igp_cable_length_50 = 50, em_igp_cable_length_60 = 60, em_igp_cable_length_70 = 70, em_igp_cable_length_80 = 80, em_igp_cable_length_90 = 90, em_igp_cable_length_100 = 100, em_igp_cable_length_110 = 110, + em_igp_cable_length_115 = 115, em_igp_cable_length_120 = 120, em_igp_cable_length_130 = 130, em_igp_cable_length_140 = 140, em_igp_cable_length_150 = 150, em_igp_cable_length_160 = 160, em_igp_cable_length_170 = 170, em_igp_cable_length_180 = 180 } em_igp_cable_length; typedef enum { em_10bt_ext_dist_enable_normal = 0, em_10bt_ext_dist_enable_lower, em_10bt_ext_dist_enable_undefined = 0xFF } em_10bt_ext_dist_enable; typedef enum { em_rev_polarity_normal = 0, em_rev_polarity_reversed, em_rev_polarity_undefined = 0xFF } em_rev_polarity; typedef enum { em_downshift_normal = 0, em_downshift_activated, em_downshift_undefined = 0xFF } em_downshift; typedef enum { em_smart_speed_default = 0, em_smart_speed_on, em_smart_speed_off } em_smart_speed; typedef enum { em_polarity_reversal_enabled = 0, em_polarity_reversal_disabled, em_polarity_reversal_undefined = 0xFF } em_polarity_reversal; typedef enum { em_auto_x_mode_manual_mdi = 0, em_auto_x_mode_manual_mdix, em_auto_x_mode_auto1, em_auto_x_mode_auto2, em_auto_x_mode_undefined = 0xFF } em_auto_x_mode; typedef enum { em_1000t_rx_status_not_ok = 0, em_1000t_rx_status_ok, em_1000t_rx_status_undefined = 0xFF } em_1000t_rx_status; typedef enum { em_phy_m88 = 0, em_phy_igp, em_phy_igp_2, em_phy_undefined = 0xFF } em_phy_type; typedef enum { em_ms_hw_default = 0, em_ms_force_master, em_ms_force_slave, em_ms_auto } em_ms_type; typedef enum { em_ffe_config_enabled = 0, em_ffe_config_active, em_ffe_config_blocked } em_ffe_config; typedef enum { em_dsp_config_disabled = 0, em_dsp_config_enabled, em_dsp_config_activated, em_dsp_config_undefined = 0xFF } em_dsp_config; struct em_phy_info { em_cable_length cable_length; em_10bt_ext_dist_enable extended_10bt_distance; em_rev_polarity cable_polarity; em_downshift downshift; em_polarity_reversal polarity_correction; em_auto_x_mode mdix_mode; em_1000t_rx_status local_rx; em_1000t_rx_status remote_rx; }; struct em_phy_stats { uint32_t idle_errors; uint32_t receive_errors; }; struct em_eeprom_info { em_eeprom_type type; uint16_t word_size; uint16_t opcode_bits; uint16_t address_bits; uint16_t delay_usec; uint16_t page_size; boolean_t use_eerd; boolean_t use_eewr; }; /* Flex ASF Information */ #define E1000_HOST_IF_MAX_SIZE 2048 typedef enum { em_byte_align = 0, em_word_align = 1, em_dword_align = 2 } em_align_type; /* Error Codes */ #define E1000_SUCCESS 0 #define E1000_ERR_EEPROM 1 #define E1000_ERR_PHY 2 #define E1000_ERR_CONFIG 3 #define E1000_ERR_PARAM 4 #define E1000_ERR_MAC_TYPE 5 #define E1000_ERR_PHY_TYPE 6 #define E1000_ERR_RESET 9 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 #define E1000_BLK_PHY_RESET 12 /* Function prototypes */ /* Initialization */ int32_t em_reset_hw(struct em_hw *hw); int32_t em_init_hw(struct em_hw *hw); int32_t em_id_led_init(struct em_hw * hw); int32_t em_set_mac_type(struct em_hw *hw); void em_set_media_type(struct em_hw *hw); /* Link Configuration */ int32_t em_setup_link(struct em_hw *hw); int32_t em_phy_setup_autoneg(struct em_hw *hw); void em_config_collision_dist(struct em_hw *hw); int32_t em_config_fc_after_link_up(struct em_hw *hw); int32_t em_check_for_link(struct em_hw *hw); int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t * speed, uint16_t * duplex); int32_t em_wait_autoneg(struct em_hw *hw); int32_t em_force_mac_fc(struct em_hw *hw); /* PHY */ int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data); int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data); int32_t em_phy_hw_reset(struct em_hw *hw); int32_t em_phy_reset(struct em_hw *hw); int32_t em_detect_gig_phy(struct em_hw *hw); int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info); int32_t em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info); int32_t em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info); int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length); int32_t em_check_polarity(struct em_hw *hw, uint16_t *polarity); int32_t em_check_downshift(struct em_hw *hw); int32_t em_validate_mdi_setting(struct em_hw *hw); /* EEPROM Functions */ int32_t em_init_eeprom_params(struct em_hw *hw); boolean_t em_is_onboard_nvm_eeprom(struct em_hw *hw); int32_t em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); int32_t em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); int32_t em_poll_eerd_eewr_done(struct em_hw *hw, int eerd); /* MNG HOST IF functions */ uint32_t em_enable_mng_pass_thru(struct em_hw *hw); #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ #define E1000_MNG_IAMT_MODE 0x3 #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ #define E1000_VFTA_ENTRY_SHIFT 0x5 #define E1000_VFTA_ENTRY_MASK 0x7F #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F struct em_host_mng_command_header { uint8_t command_id; uint8_t checksum; uint16_t reserved1; uint16_t reserved2; uint16_t command_length; }; struct em_host_mng_command_info { struct em_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ }; #ifdef __BIG_ENDIAN struct em_host_mng_dhcp_cookie{ uint32_t signature; uint16_t vlan_id; uint8_t reserved0; uint8_t status; uint32_t reserved1; uint8_t checksum; uint8_t reserved3; uint16_t reserved2; }; #else struct em_host_mng_dhcp_cookie{ uint32_t signature; uint8_t status; uint8_t reserved0; uint16_t vlan_id; uint32_t reserved1; uint16_t reserved2; uint8_t reserved3; uint8_t checksum; }; #endif int32_t em_mng_write_dhcp_info(struct em_hw *hw, uint8_t *buffer, uint16_t length); boolean_t em_check_mng_mode(struct em_hw *hw); boolean_t em_enable_tx_pkt_filtering(struct em_hw *hw); int32_t em_mng_enable_host_if(struct em_hw *hw); int32_t em_mng_host_if_write(struct em_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); int32_t em_mng_write_cmd_header(struct em_hw* hw, struct em_host_mng_command_header* hdr); int32_t em_mng_write_commit(struct em_hw *hw); int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); int32_t em_validate_eeprom_checksum(struct em_hw *hw); int32_t em_update_eeprom_checksum(struct em_hw *hw); int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); int32_t em_read_part_num(struct em_hw *hw, uint32_t * part_num); int32_t em_read_mac_addr(struct em_hw * hw); int32_t em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask); void em_swfw_sync_release(struct em_hw *hw, uint16_t mask); /* Filters (multicast, vlan, receive) */ void em_init_rx_addrs(struct em_hw *hw); void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count); uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t * mc_addr); void em_mta_set(struct em_hw *hw, uint32_t hash_value); void em_rar_set(struct em_hw *hw, uint8_t * mc_addr, uint32_t rar_index); void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value); void em_clear_vfta(struct em_hw *hw); /* LED functions */ int32_t em_setup_led(struct em_hw *hw); int32_t em_cleanup_led(struct em_hw *hw); int32_t em_led_on(struct em_hw *hw); int32_t em_led_off(struct em_hw *hw); /* Adaptive IFS Functions */ /* Everything else */ void em_clear_hw_cntrs(struct em_hw *hw); void em_reset_adaptive(struct em_hw *hw); void em_update_adaptive(struct em_hw *hw); void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr); void em_get_bus_info(struct em_hw *hw); void em_pci_set_mwi(struct em_hw *hw); void em_pci_clear_mwi(struct em_hw *hw); void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value); void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value); /* Port I/O is only supported on 82544 and newer */ uint32_t em_read_reg_io(struct em_hw *hw, uint32_t offset); void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value); int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up); int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active); int32_t em_set_d0_lplu_state(struct em_hw *hw, boolean_t active); void em_set_pci_express_master_disable(struct em_hw *hw); void em_enable_pciex_master(struct em_hw *hw); int32_t em_disable_pciex_master(struct em_hw *hw); int32_t em_get_auto_rd_done(struct em_hw *hw); int32_t em_get_phy_cfg_done(struct em_hw *hw); int32_t em_get_software_semaphore(struct em_hw *hw); void em_release_software_semaphore(struct em_hw *hw); int32_t em_check_phy_reset_block(struct em_hw *hw); int32_t em_get_hw_eeprom_semaphore(struct em_hw *hw); void em_put_hw_eeprom_semaphore(struct em_hw *hw); int32_t em_commit_shadow_ram(struct em_hw *hw); uint8_t em_arc_subsystem_valid(struct em_hw *hw); #define E1000_BAR_TYPE(v) ((v) & E1000_BAR_TYPE_MASK) #define E1000_BAR_TYPE_MASK 0x00000001 #define E1000_BAR_TYPE_MEM 0x00000000 #define E1000_BAR_TYPE_IO 0x00000001 #define E1000_BAR_MEM_TYPE(v) ((v) & E1000_BAR_MEM_TYPE_MASK) #define E1000_BAR_MEM_TYPE_MASK 0x00000006 #define E1000_BAR_MEM_TYPE_32BIT 0x00000000 #define E1000_BAR_MEM_TYPE_64BIT 0x00000004 #define E1000_READ_REG_IO(a, reg) \ em_read_reg_io((a), E1000_##reg) #define E1000_WRITE_REG_IO(a, reg, val) \ em_write_reg_io((a), E1000_##reg, val) /* PCI Device IDs */ #define E1000_DEV_ID_82542 0x1000 #define E1000_DEV_ID_82543GC_FIBER 0x1001 #define E1000_DEV_ID_82543GC_COPPER 0x1004 #define E1000_DEV_ID_82544EI_COPPER 0x1008 #define E1000_DEV_ID_82544EI_FIBER 0x1009 #define E1000_DEV_ID_82544GC_COPPER 0x100C #define E1000_DEV_ID_82544GC_LOM 0x100D #define E1000_DEV_ID_82540EM 0x100E #define E1000_DEV_ID_82541ER_LOM 0x1014 #define E1000_DEV_ID_82540EM_LOM 0x1015 #define E1000_DEV_ID_82540EP_LOM 0x1016 #define E1000_DEV_ID_82540EP 0x1017 #define E1000_DEV_ID_82540EP_LP 0x101E #define E1000_DEV_ID_82545EM_COPPER 0x100F #define E1000_DEV_ID_82545EM_FIBER 0x1011 #define E1000_DEV_ID_82545GM_COPPER 0x1026 #define E1000_DEV_ID_82545GM_FIBER 0x1027 #define E1000_DEV_ID_82545GM_SERDES 0x1028 #define E1000_DEV_ID_82546EB_COPPER 0x1010 #define E1000_DEV_ID_82546EB_FIBER 0x1012 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D #define E1000_DEV_ID_82541EI 0x1013 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 #define E1000_DEV_ID_82541ER 0x1078 #define E1000_DEV_ID_82547GI 0x1075 #define E1000_DEV_ID_82541GI 0x1076 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 #define E1000_DEV_ID_82541GI_LF 0x107C #define E1000_DEV_ID_82546GB_COPPER 0x1079 #define E1000_DEV_ID_82546GB_FIBER 0x107A #define E1000_DEV_ID_82546GB_SERDES 0x107B #define E1000_DEV_ID_82546GB_PCIE 0x108A #define E1000_DEV_ID_82547EI 0x1019 #define E1000_DEV_ID_82547EI_MOBILE 0x101A +#define E1000_DEV_ID_82571EB_COPPER 0x105E +#define E1000_DEV_ID_82571EB_FIBER 0x105F +#define E1000_DEV_ID_82571EB_SERDES 0x1060 +#define E1000_DEV_ID_82572EI_COPPER 0x107D +#define E1000_DEV_ID_82572EI_FIBER 0x107E +#define E1000_DEV_ID_82572EI_SERDES 0x107F #define E1000_DEV_ID_82573E 0x108B #define E1000_DEV_ID_82573E_IAMT 0x108C +#define E1000_DEV_ID_82573L 0x109A #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 #define NODE_ADDRESS_SIZE 6 #define ETH_LENGTH_OF_ADDRESS 6 /* MAC decode size is 128K - This is the size of BAR0 */ #define MAC_DECODE_SIZE (128 * 1024) #define E1000_82542_2_0_REV_ID 2 #define E1000_82542_2_1_REV_ID 3 #define E1000_REVISION_0 0 #define E1000_REVISION_1 1 #define E1000_REVISION_2 2 #define E1000_REVISION_3 3 #define SPEED_10 10 #define SPEED_100 100 #define SPEED_1000 1000 #define HALF_DUPLEX 1 #define FULL_DUPLEX 2 /* The sizes (in bytes) of a ethernet packet */ #define ENET_HEADER_SIZE 14 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ #define ETHERNET_FCS_SIZE 4 #define MAXIMUM_ETHERNET_PACKET_SIZE \ (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) #define MINIMUM_ETHERNET_PACKET_SIZE \ (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) #define CRC_LENGTH ETHERNET_FCS_SIZE #define MAX_JUMBO_FRAME_SIZE 0x3F00 /* 802.1q VLAN Packet Sizes */ #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ /* Ethertype field values */ #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ /* Packet Header defines */ #define IP_PROTOCOL_TCP 6 #define IP_PROTOCOL_UDP 0x11 /* This defines the bits that are set in the Interrupt Mask * Set/Read Register. Each bit is documented below: * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) * o RXSEQ = Receive Sequence Error */ #define POLL_IMS_ENABLE_MASK ( \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ) /* This defines the bits that are set in the Interrupt Mask * Set/Read Register. Each bit is documented below: * o RXT0 = Receiver Timer Interrupt (ring 0) * o TXDW = Transmit Descriptor Written Back * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) * o RXSEQ = Receive Sequence Error * o LSC = Link Status Change */ #define IMS_ENABLE_MASK ( \ E1000_IMS_RXT0 | \ E1000_IMS_TXDW | \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ | \ E1000_IMS_RXO | \ E1000_IMS_LSC) /* Number of high/low register pairs in the RAR. The RAR (Receive Address * Registers) holds the directed and multicast addresses that we monitor. We * reserve one of these spots for our directed address, allowing us room for * E1000_RAR_ENTRIES - 1 multicast addresses. */ #define E1000_RAR_ENTRIES 15 #define MIN_NUMBER_OF_DESCRIPTORS 8 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* Receive Descriptor */ struct em_rx_desc { uint64_t buffer_addr; /* Address of the descriptor's data buffer */ uint16_t length; /* Length of data DMAed into data buffer */ uint16_t csum; /* Packet checksum */ uint8_t status; /* Descriptor status */ uint8_t errors; /* Descriptor Errors */ uint16_t special; }; /* Receive Descriptor - Extended */ union em_rx_desc_extended { struct { uint64_t buffer_addr; uint64_t reserved; } read; struct { struct { uint32_t mrq; /* Multiple Rx Queues */ union { uint32_t rss; /* RSS Hash */ struct { uint16_t ip_id; /* IP id */ uint16_t csum; /* Packet Checksum */ } csum_ip; } hi_dword; } lower; struct { uint32_t status_error; /* ext status/error */ uint16_t length; uint16_t vlan; /* VLAN tag */ } upper; } wb; /* writeback */ }; #define MAX_PS_BUFFERS 4 /* Receive Descriptor - Packet Split */ union em_rx_desc_packet_split { struct { /* one buffer for protocol header(s), three data buffers */ uint64_t buffer_addr[MAX_PS_BUFFERS]; } read; struct { struct { uint32_t mrq; /* Multiple Rx Queues */ union { uint32_t rss; /* RSS Hash */ struct { uint16_t ip_id; /* IP id */ uint16_t csum; /* Packet Checksum */ } csum_ip; } hi_dword; } lower; struct { uint32_t status_error; /* ext status/error */ uint16_t length0; /* length of buffer 0 */ uint16_t vlan; /* VLAN tag */ } middle; struct { uint16_t header_status; uint16_t length[3]; /* length of buffers 1-3 */ } upper; uint64_t reserved; } wb; /* writeback */ }; /* Receive Decriptor bit definitions */ #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ #define E1000_RXD_SPC_PRI_SHIFT 13 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ #define E1000_RXD_SPC_CFI_SHIFT 12 #define E1000_RXDEXT_STATERR_CE 0x01000000 #define E1000_RXDEXT_STATERR_SE 0x02000000 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 #define E1000_RXDEXT_STATERR_CXE 0x10000000 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 #define E1000_RXDEXT_STATERR_IPE 0x40000000 #define E1000_RXDEXT_STATERR_RXE 0x80000000 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF /* mask to determine if packets should be dropped due to frame errors */ #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ E1000_RXD_ERR_CE | \ E1000_RXD_ERR_SE | \ E1000_RXD_ERR_SEQ | \ E1000_RXD_ERR_CXE | \ E1000_RXD_ERR_RXE) /* Same mask, but for extended and packet split descriptors */ #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ E1000_RXDEXT_STATERR_CE | \ E1000_RXDEXT_STATERR_SE | \ E1000_RXDEXT_STATERR_SEQ | \ E1000_RXDEXT_STATERR_CXE | \ E1000_RXDEXT_STATERR_RXE) /* Transmit Descriptor */ struct em_tx_desc { uint64_t buffer_addr; /* Address of the descriptor's data buffer */ union { uint32_t data; struct { uint16_t length; /* Data buffer length */ uint8_t cso; /* Checksum offset */ uint8_t cmd; /* Descriptor control */ } flags; } lower; union { uint32_t data; struct { uint8_t status; /* Descriptor status */ uint8_t css; /* Checksum start */ uint16_t special; } fields; } upper; }; /* * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will * also optimize cache line size effect. H/W supports up to cache line size 128. */ #define E1000_DBA_ALIGN 128 /* Transmit Descriptor bit definitions */ #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ /* Offload Context Descriptor */ struct em_context_desc { union { uint32_t ip_config; struct { uint8_t ipcss; /* IP checksum start */ uint8_t ipcso; /* IP checksum offset */ uint16_t ipcse; /* IP checksum end */ } ip_fields; } lower_setup; union { uint32_t tcp_config; struct { uint8_t tucss; /* TCP checksum start */ uint8_t tucso; /* TCP checksum offset */ uint16_t tucse; /* TCP checksum end */ } tcp_fields; } upper_setup; uint32_t cmd_and_length; /* */ union { uint32_t data; struct { uint8_t status; /* Descriptor status */ uint8_t hdr_len; /* Header length */ uint16_t mss; /* Maximum segment size */ } fields; } tcp_seg_setup; }; /* Offload data descriptor */ struct em_data_desc { uint64_t buffer_addr; /* Address of the descriptor's buffer address */ union { uint32_t data; struct { uint16_t length; /* Data buffer length */ uint8_t typ_len_ext; /* */ uint8_t cmd; /* */ } flags; } lower; union { uint32_t data; struct { uint8_t status; /* Descriptor status */ uint8_t popts; /* Packet Options */ uint16_t special; /* */ } fields; } upper; }; /* Filters */ #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ /* Receive Address Register */ struct em_rar { volatile uint32_t low; /* receive address low */ volatile uint32_t high; /* receive address high */ }; /* Number of entries in the Multicast Table Array (MTA). */ #define E1000_NUM_MTA_REGISTERS 128 /* IPv4 Address Table Entry */ struct em_ipv4_at_entry { volatile uint32_t ipv4_addr; /* IP Address (RW) */ volatile uint32_t reserved; }; /* Four wakeup IP addresses are supported */ #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX #define E1000_IP6AT_SIZE 1 /* IPv6 Address Table Entry */ struct em_ipv6_at_entry { volatile uint8_t ipv6_addr[16]; }; /* Flexible Filter Length Table Entry */ struct em_fflt_entry { volatile uint32_t length; /* Flexible Filter Length (RW) */ volatile uint32_t reserved; }; /* Flexible Filter Mask Table Entry */ struct em_ffmt_entry { volatile uint32_t mask; /* Flexible Filter Mask (RW) */ volatile uint32_t reserved; }; /* Flexible Filter Value Table Entry */ struct em_ffvt_entry { volatile uint32_t value; /* Flexible Filter Value (RW) */ volatile uint32_t reserved; }; /* Four Flexible Filters are supported */ #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX +#define E1000_DISABLE_SERDES_LOOPBACK 0x0400 /* Register Set. (82543, 82544) * * Registers are defined to be 32 bits and should be accessed as 32 bit values. * These registers are physically located on the NIC, but are mapped into the * host memory address space. * * RW - register is both readable and writable * RO - register is read only * WO - register is write only * R/clr - register is read only and is cleared when read * A - register array */ #define E1000_CTRL 0x00000 /* Device Control - RW */ #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ #define E1000_STATUS 0x00008 /* Device Status - RO */ #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ #define E1000_EERD 0x00014 /* EEPROM Read - RW */ #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ #define E1000_FLA 0x0001C /* Flash Access - RW */ #define E1000_MDIC 0x00020 /* MDI Control - RW */ +#define E1000_SCTL 0x00024 /* SerDes Control - RW */ #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ #define E1000_FCT 0x00030 /* Flow Control Type - RW */ #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ #define E1000_RCTL 0x00100 /* RX Control - RW */ +#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ +#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ +#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ +#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ +#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ +#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ #define E1000_TCTL 0x00400 /* TX Control - RW */ #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ #define E1000_PBS 0x01008 /* Packet Buffer Size */ #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ #define E1000_FLASH_UPDATES 1000 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ #define E1000_FLSWCTL 0x01030 /* FLASH control register */ #define E1000_FLSWDATA 0x01034 /* FLASH data register */ #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ +#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ +#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ +#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ +#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ +#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ +#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ #define E1000_COLC 0x04028 /* Collision Count - R/clr */ #define E1000_DC 0x04030 /* Defer Count - R/clr */ #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ -#define E1000_IAC 0x4100 /* Interrupt Assertion Count */ -#define E1000_ICRXPTC 0x4104 /* Interrupt Cause Rx Packet Timer Expire Count */ -#define E1000_ICRXATC 0x4108 /* Interrupt Cause Rx Absolute Timer Expire Count */ -#define E1000_ICTXPTC 0x410C /* Interrupt Cause Tx Packet Timer Expire Count */ -#define E1000_ICTXATC 0x4110 /* Interrupt Cause Tx Absolute Timer Expire Count */ -#define E1000_ICTXQEC 0x4118 /* Interrupt Cause Tx Queue Empty Count */ -#define E1000_ICTXQMTC 0x411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ -#define E1000_ICRXDMTC 0x4120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ -#define E1000_ICRXOC 0x4124 /* Interrupt Cause Receiver Overrun Count */ +#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ +#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ +#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ +#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ +#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ +#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ +#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ +#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ +#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ #define E1000_RA 0x05400 /* Receive Address - RW Array */ #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ #define E1000_WUC 0x05800 /* Wakeup Control - RW */ #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ #define E1000_WUS 0x05810 /* Wakeup Status - RO */ #define E1000_MANC 0x05820 /* Management Control - RW */ #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ #define E1000_HOST_IF 0x08800 /* Host Interface */ #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ #define E1000_GCR 0x05B00 /* PCI-Ex Control */ #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ #define E1000_SWSM 0x05B50 /* SW Semaphore */ #define E1000_FWSM 0x05B54 /* FW Semaphore */ #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ #define E1000_HICR 0x08F00 /* Host Inteface Control */ + +/* RSS registers */ +#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ +#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ +#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ +#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ +#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ +#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ /* Register Set (82542) * * Some of the 82542 registers are located at different offsets than they are * in more current versions of the 8254x. Despite the difference in location, * the registers function in the same manner. */ #define E1000_82542_CTRL E1000_CTRL #define E1000_82542_CTRL_DUP E1000_CTRL_DUP #define E1000_82542_STATUS E1000_STATUS #define E1000_82542_EECD E1000_EECD #define E1000_82542_EERD E1000_EERD #define E1000_82542_CTRL_EXT E1000_CTRL_EXT #define E1000_82542_FLA E1000_FLA #define E1000_82542_MDIC E1000_MDIC +#define E1000_82542_SCTL E1000_SCTL #define E1000_82542_FCAL E1000_FCAL #define E1000_82542_FCAH E1000_FCAH #define E1000_82542_FCT E1000_FCT #define E1000_82542_VET E1000_VET #define E1000_82542_RA 0x00040 #define E1000_82542_ICR E1000_ICR #define E1000_82542_ITR E1000_ITR #define E1000_82542_ICS E1000_ICS #define E1000_82542_IMS E1000_IMS #define E1000_82542_IMC E1000_IMC #define E1000_82542_RCTL E1000_RCTL #define E1000_82542_RDTR 0x00108 #define E1000_82542_RDBAL 0x00110 #define E1000_82542_RDBAH 0x00114 #define E1000_82542_RDLEN 0x00118 #define E1000_82542_RDH 0x00120 #define E1000_82542_RDT 0x00128 +#define E1000_82542_RDTR0 E1000_82542_RDTR +#define E1000_82542_RDBAL0 E1000_82542_RDBAL +#define E1000_82542_RDBAH0 E1000_82542_RDBAH +#define E1000_82542_RDLEN0 E1000_82542_RDLEN +#define E1000_82542_RDH0 E1000_82542_RDH +#define E1000_82542_RDT0 E1000_82542_RDT +#define E1000_82542_RDTR1 0x00130 +#define E1000_82542_RDBAL1 0x00138 +#define E1000_82542_RDBAH1 0x0013C +#define E1000_82542_RDLEN1 0x00140 +#define E1000_82542_RDH1 0x00148 +#define E1000_82542_RDT1 0x00150 #define E1000_82542_FCRTH 0x00160 #define E1000_82542_FCRTL 0x00168 #define E1000_82542_FCTTV E1000_FCTTV #define E1000_82542_TXCW E1000_TXCW #define E1000_82542_RXCW E1000_RXCW #define E1000_82542_MTA 0x00200 #define E1000_82542_TCTL E1000_TCTL #define E1000_82542_TIPG E1000_TIPG #define E1000_82542_TDBAL 0x00420 #define E1000_82542_TDBAH 0x00424 #define E1000_82542_TDLEN 0x00428 #define E1000_82542_TDH 0x00430 #define E1000_82542_TDT 0x00438 #define E1000_82542_TIDV 0x00440 #define E1000_82542_TBT E1000_TBT #define E1000_82542_AIT E1000_AIT #define E1000_82542_VFTA 0x00600 #define E1000_82542_LEDCTL E1000_LEDCTL #define E1000_82542_PBA E1000_PBA #define E1000_82542_PBS E1000_PBS #define E1000_82542_EEMNGCTL E1000_EEMNGCTL #define E1000_82542_EEARBC E1000_EEARBC #define E1000_82542_FLASHT E1000_FLASHT #define E1000_82542_EEWR E1000_EEWR #define E1000_82542_FLSWCTL E1000_FLSWCTL #define E1000_82542_FLSWDATA E1000_FLSWDATA #define E1000_82542_FLSWCNT E1000_FLSWCNT #define E1000_82542_FLOP E1000_FLOP #define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL #define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE #define E1000_82542_ERT E1000_ERT #define E1000_82542_RXDCTL E1000_RXDCTL #define E1000_82542_RADV E1000_RADV #define E1000_82542_RSRPD E1000_RSRPD #define E1000_82542_TXDMAC E1000_TXDMAC #define E1000_82542_TDFHS E1000_TDFHS #define E1000_82542_TDFTS E1000_TDFTS #define E1000_82542_TDFPC E1000_TDFPC #define E1000_82542_TXDCTL E1000_TXDCTL #define E1000_82542_TADV E1000_TADV #define E1000_82542_TSPMT E1000_TSPMT #define E1000_82542_CRCERRS E1000_CRCERRS #define E1000_82542_ALGNERRC E1000_ALGNERRC #define E1000_82542_SYMERRS E1000_SYMERRS #define E1000_82542_RXERRC E1000_RXERRC #define E1000_82542_MPC E1000_MPC #define E1000_82542_SCC E1000_SCC #define E1000_82542_ECOL E1000_ECOL #define E1000_82542_MCC E1000_MCC #define E1000_82542_LATECOL E1000_LATECOL #define E1000_82542_COLC E1000_COLC #define E1000_82542_DC E1000_DC #define E1000_82542_TNCRS E1000_TNCRS #define E1000_82542_SEC E1000_SEC #define E1000_82542_CEXTERR E1000_CEXTERR #define E1000_82542_RLEC E1000_RLEC #define E1000_82542_XONRXC E1000_XONRXC #define E1000_82542_XONTXC E1000_XONTXC #define E1000_82542_XOFFRXC E1000_XOFFRXC #define E1000_82542_XOFFTXC E1000_XOFFTXC #define E1000_82542_FCRUC E1000_FCRUC #define E1000_82542_PRC64 E1000_PRC64 #define E1000_82542_PRC127 E1000_PRC127 #define E1000_82542_PRC255 E1000_PRC255 #define E1000_82542_PRC511 E1000_PRC511 #define E1000_82542_PRC1023 E1000_PRC1023 #define E1000_82542_PRC1522 E1000_PRC1522 #define E1000_82542_GPRC E1000_GPRC #define E1000_82542_BPRC E1000_BPRC #define E1000_82542_MPRC E1000_MPRC #define E1000_82542_GPTC E1000_GPTC #define E1000_82542_GORCL E1000_GORCL #define E1000_82542_GORCH E1000_GORCH #define E1000_82542_GOTCL E1000_GOTCL #define E1000_82542_GOTCH E1000_GOTCH #define E1000_82542_RNBC E1000_RNBC #define E1000_82542_RUC E1000_RUC #define E1000_82542_RFC E1000_RFC #define E1000_82542_ROC E1000_ROC #define E1000_82542_RJC E1000_RJC #define E1000_82542_MGTPRC E1000_MGTPRC #define E1000_82542_MGTPDC E1000_MGTPDC #define E1000_82542_MGTPTC E1000_MGTPTC #define E1000_82542_TORL E1000_TORL #define E1000_82542_TORH E1000_TORH #define E1000_82542_TOTL E1000_TOTL #define E1000_82542_TOTH E1000_TOTH #define E1000_82542_TPR E1000_TPR #define E1000_82542_TPT E1000_TPT #define E1000_82542_PTC64 E1000_PTC64 #define E1000_82542_PTC127 E1000_PTC127 #define E1000_82542_PTC255 E1000_PTC255 #define E1000_82542_PTC511 E1000_PTC511 #define E1000_82542_PTC1023 E1000_PTC1023 #define E1000_82542_PTC1522 E1000_PTC1522 #define E1000_82542_MPTC E1000_MPTC #define E1000_82542_BPTC E1000_BPTC #define E1000_82542_TSCTC E1000_TSCTC #define E1000_82542_TSCTFC E1000_TSCTFC #define E1000_82542_RXCSUM E1000_RXCSUM #define E1000_82542_WUC E1000_WUC #define E1000_82542_WUFC E1000_WUFC #define E1000_82542_WUS E1000_WUS #define E1000_82542_MANC E1000_MANC #define E1000_82542_IPAV E1000_IPAV #define E1000_82542_IP4AT E1000_IP4AT #define E1000_82542_IP6AT E1000_IP6AT #define E1000_82542_WUPL E1000_WUPL #define E1000_82542_WUPM E1000_WUPM #define E1000_82542_FFLT E1000_FFLT #define E1000_82542_TDFH 0x08010 #define E1000_82542_TDFT 0x08018 #define E1000_82542_FFMT E1000_FFMT #define E1000_82542_FFVT E1000_FFVT #define E1000_82542_HOST_IF E1000_HOST_IF #define E1000_82542_IAM E1000_IAM #define E1000_82542_EEMNGCTL E1000_EEMNGCTL #define E1000_82542_PSRCTL E1000_PSRCTL #define E1000_82542_RAID E1000_RAID #define E1000_82542_TARC0 E1000_TARC0 #define E1000_82542_TDBAL1 E1000_TDBAL1 #define E1000_82542_TDBAH1 E1000_TDBAH1 #define E1000_82542_TDLEN1 E1000_TDLEN1 #define E1000_82542_TDH1 E1000_TDH1 #define E1000_82542_TDT1 E1000_TDT1 #define E1000_82542_TXDCTL1 E1000_TXDCTL1 #define E1000_82542_TARC1 E1000_TARC1 #define E1000_82542_RFCTL E1000_RFCTL #define E1000_82542_GCR E1000_GCR #define E1000_82542_GSCL_1 E1000_GSCL_1 #define E1000_82542_GSCL_2 E1000_GSCL_2 #define E1000_82542_GSCL_3 E1000_GSCL_3 #define E1000_82542_GSCL_4 E1000_GSCL_4 #define E1000_82542_FACTPS E1000_FACTPS #define E1000_82542_SWSM E1000_SWSM #define E1000_82542_FWSM E1000_FWSM #define E1000_82542_FFLT_DBG E1000_FFLT_DBG #define E1000_82542_IAC E1000_IAC #define E1000_82542_ICRXPTC E1000_ICRXPTC #define E1000_82542_ICRXATC E1000_ICRXATC #define E1000_82542_ICTXPTC E1000_ICTXPTC #define E1000_82542_ICTXATC E1000_ICTXATC #define E1000_82542_ICTXQEC E1000_ICTXQEC #define E1000_82542_ICTXQMTC E1000_ICTXQMTC #define E1000_82542_ICRXDMTC E1000_ICRXDMTC #define E1000_82542_ICRXOC E1000_ICRXOC #define E1000_82542_HICR E1000_HICR +#define E1000_82542_CPUVEC E1000_CPUVEC +#define E1000_82542_MRQC E1000_MRQC +#define E1000_82542_RETA E1000_RETA +#define E1000_82542_RSSRK E1000_RSSRK +#define E1000_82542_RSSIM E1000_RSSIM +#define E1000_82542_RSSIR E1000_RSSIR + /* Statistics counters collected by the MAC */ struct em_hw_stats { uint64_t crcerrs; uint64_t algnerrc; uint64_t symerrs; uint64_t rxerrc; uint64_t mpc; uint64_t scc; uint64_t ecol; uint64_t mcc; uint64_t latecol; uint64_t colc; uint64_t dc; uint64_t tncrs; uint64_t sec; uint64_t cexterr; uint64_t rlec; uint64_t xonrxc; uint64_t xontxc; uint64_t xoffrxc; uint64_t xofftxc; uint64_t fcruc; uint64_t prc64; uint64_t prc127; uint64_t prc255; uint64_t prc511; uint64_t prc1023; uint64_t prc1522; uint64_t gprc; uint64_t bprc; uint64_t mprc; uint64_t gptc; uint64_t gorcl; uint64_t gorch; uint64_t gotcl; uint64_t gotch; uint64_t rnbc; uint64_t ruc; uint64_t rfc; uint64_t roc; uint64_t rjc; uint64_t mgprc; uint64_t mgpdc; uint64_t mgptc; uint64_t torl; uint64_t torh; uint64_t totl; uint64_t toth; uint64_t tpr; uint64_t tpt; uint64_t ptc64; uint64_t ptc127; uint64_t ptc255; uint64_t ptc511; uint64_t ptc1023; uint64_t ptc1522; uint64_t mptc; uint64_t bptc; uint64_t tsctc; uint64_t tsctfc; uint64_t iac; uint64_t icrxptc; uint64_t icrxatc; uint64_t ictxptc; uint64_t ictxatc; uint64_t ictxqec; uint64_t ictxqmtc; uint64_t icrxdmtc; uint64_t icrxoc; }; /* Structure containing variables used by the shared code (em_hw.c) */ struct em_hw { uint8_t *hw_addr; uint8_t *flash_address; em_mac_type mac_type; em_phy_type phy_type; uint32_t phy_init_script; em_media_type media_type; void *back; em_fc_type fc; em_bus_speed bus_speed; em_bus_width bus_width; em_bus_type bus_type; struct em_eeprom_info eeprom; em_ms_type master_slave; em_ms_type original_master_slave; em_ffe_config ffe_config_state; uint32_t asf_firmware_present; uint32_t eeprom_semaphore_present; unsigned long io_base; uint32_t phy_id; uint32_t phy_revision; uint32_t phy_addr; uint32_t original_fc; uint32_t txcw; uint32_t autoneg_failed; uint32_t max_frame_size; uint32_t min_frame_size; uint32_t mc_filter_type; uint32_t num_mc_addrs; uint32_t collision_delta; uint32_t tx_packet_delta; uint32_t ledctl_default; uint32_t ledctl_mode1; uint32_t ledctl_mode2; boolean_t tx_pkt_filtering; struct em_host_mng_dhcp_cookie mng_cookie; uint16_t phy_spd_default; uint16_t autoneg_advertised; uint16_t pci_cmd_word; uint16_t fc_high_water; uint16_t fc_low_water; uint16_t fc_pause_time; uint16_t current_ifs_val; uint16_t ifs_min_val; uint16_t ifs_max_val; uint16_t ifs_step_size; uint16_t ifs_ratio; uint16_t device_id; uint16_t vendor_id; uint16_t subsystem_id; uint16_t subsystem_vendor_id; uint8_t revision_id; uint8_t autoneg; uint8_t mdix; uint8_t forced_speed_duplex; uint8_t wait_autoneg_complete; uint8_t dma_fairness; uint8_t mac_addr[NODE_ADDRESS_SIZE]; uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; boolean_t disable_polarity_correction; boolean_t speed_downgraded; em_smart_speed smart_speed; em_dsp_config dsp_config_state; boolean_t get_link_status; boolean_t serdes_link_down; boolean_t tbi_compatibility_en; boolean_t tbi_compatibility_on; + boolean_t laa_is_present; boolean_t phy_reset_disable; boolean_t fc_send_xon; boolean_t fc_strict_ieee; boolean_t report_tx_early; boolean_t adaptive_ifs; boolean_t ifs_params_forced; boolean_t in_ifs_mode; boolean_t mng_reg_access_disabled; }; #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ /* Register Bit Masks */ /* Device Control */ #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ #define E1000_CTRL_RST 0x04000000 /* Global reset */ #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ /* Device Status */ #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ #define E1000_STATUS_FUNC_SHIFT 2 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ #define E1000_STATUS_SPEED_MASK 0x000000C0 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ /* Constants used to intrepret the masked PCI-X bus speed. */ #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ /* EEPROM/Flash Control */ #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ #define E1000_EECD_FWE_MASK 0x00000030 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ #define E1000_EECD_FWE_SHIFT 4 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type * (0-small, 1-large) */ #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ #ifndef E1000_EEPROM_GRANT_ATTEMPTS #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ #endif #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ #define E1000_EECD_SIZE_EX_SHIFT 11 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ +#define E1000_EECD_SECVAL_SHIFT 22 #define E1000_STM_OPCODE 0xDB00 #define E1000_HICR_FW_RESET 0xC0 /* EEPROM Read */ #define E1000_EERD_START 0x00000001 /* Start Read */ #define E1000_EERD_DONE 0x00000010 /* Read Done */ #define E1000_EERD_ADDR_SHIFT 8 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ #define E1000_EERD_DATA_SHIFT 16 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ /* SPI EEPROM Status Register */ #define EEPROM_STATUS_RDY_SPI 0x01 #define EEPROM_STATUS_WEN_SPI 0x02 #define EEPROM_STATUS_BP0_SPI 0x04 #define EEPROM_STATUS_BP1_SPI 0x08 #define EEPROM_STATUS_WPEN_SPI 0x80 /* Extended Device Control */ #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 +#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */ +#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ /* MDI Control */ #define E1000_MDIC_DATA_MASK 0x0000FFFF #define E1000_MDIC_REG_MASK 0x001F0000 #define E1000_MDIC_REG_SHIFT 16 #define E1000_MDIC_PHY_MASK 0x03E00000 #define E1000_MDIC_PHY_SHIFT 21 #define E1000_MDIC_OP_WRITE 0x04000000 #define E1000_MDIC_OP_READ 0x08000000 #define E1000_MDIC_READY 0x10000000 #define E1000_MDIC_INT_EN 0x20000000 #define E1000_MDIC_ERROR 0x40000000 /* LED Control */ #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F #define E1000_LEDCTL_LED0_MODE_SHIFT 0 #define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020 #define E1000_LEDCTL_LED0_IVRT 0x00000040 #define E1000_LEDCTL_LED0_BLINK 0x00000080 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 #define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000 #define E1000_LEDCTL_LED1_IVRT 0x00004000 #define E1000_LEDCTL_LED1_BLINK 0x00008000 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 #define E1000_LEDCTL_LED2_IVRT 0x00400000 #define E1000_LEDCTL_LED2_BLINK 0x00800000 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 +#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 #define E1000_LEDCTL_LED3_IVRT 0x40000000 #define E1000_LEDCTL_LED3_BLINK 0x80000000 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 #define E1000_LEDCTL_MODE_LINK_UP 0x2 #define E1000_LEDCTL_MODE_ACTIVITY 0x3 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 #define E1000_LEDCTL_MODE_LINK_10 0x5 #define E1000_LEDCTL_MODE_LINK_100 0x6 #define E1000_LEDCTL_MODE_LINK_1000 0x7 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 #define E1000_LEDCTL_MODE_COLLISION 0xA #define E1000_LEDCTL_MODE_BUS_SPEED 0xB #define E1000_LEDCTL_MODE_BUS_SIZE 0xC #define E1000_LEDCTL_MODE_PAUSED 0xD #define E1000_LEDCTL_MODE_LED_ON 0xE #define E1000_LEDCTL_MODE_LED_OFF 0xF /* Receive Address */ #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ /* Interrupt Cause Read */ #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ #define E1000_ICR_RXO 0x00000040 /* rx overrun */ #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ #define E1000_ICR_TXD_LOW 0x00008000 #define E1000_ICR_SRPD 0x00010000 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ #define E1000_ICR_MNG 0x00040000 /* Manageability event */ #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ /* Interrupt Cause Set */ #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW #define E1000_ICS_SRPD E1000_ICR_SRPD #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ /* Interrupt Mask Set */ #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW #define E1000_IMS_SRPD E1000_ICR_SRPD #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ /* Interrupt Mask Clear */ #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW #define E1000_IMC_SRPD E1000_ICR_SRPD #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ /* Receive Control */ #define E1000_RCTL_RST 0x00000001 /* Software reset */ #define E1000_RCTL_EN 0x00000002 /* enable */ #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ /* Use byte values for the following shift parameters * Usage: * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & * E1000_PSRCTL_BSIZE0_MASK) | * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & * E1000_PSRCTL_BSIZE1_MASK) | * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & * E1000_PSRCTL_BSIZE2_MASK) | * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; * E1000_PSRCTL_BSIZE3_MASK)) * where value0 = [128..16256], default=256 * value1 = [1024..64512], default=4096 * value2 = [0..64512], default=4096 * value3 = [0..64512], default=0 */ #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ /* Receive Descriptor */ #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ /* Flow Control */ #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ /* Header split receive */ #define E1000_RFCTL_ISCSI_DIS 0x00000001 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E #define E1000_RFCTL_ISCSI_DWC_SHIFT 1 #define E1000_RFCTL_NFSW_DIS 0x00000040 #define E1000_RFCTL_NFSR_DIS 0x00000080 #define E1000_RFCTL_NFS_VER_MASK 0x00000300 #define E1000_RFCTL_NFS_VER_SHIFT 8 #define E1000_RFCTL_IPV6_DIS 0x00000400 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 #define E1000_RFCTL_ACK_DIS 0x00001000 #define E1000_RFCTL_ACKD_DIS 0x00002000 #define E1000_RFCTL_IPFRSP_DIS 0x00004000 #define E1000_RFCTL_EXTEN 0x00008000 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 /* Receive Descriptor Control */ #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ /* Transmit Descriptor Control */ #define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */ #define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */ #define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */ #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. still to be processed. */ /* Transmit Configuration Word */ #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ /* Receive Configuration Word */ #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ #define E1000_RXCW_CC 0x10000000 /* Receive config change */ #define E1000_RXCW_C 0x20000000 /* Receive config */ #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ /* Transmit Control */ #define E1000_TCTL_RST 0x00000001 /* software reset */ #define E1000_TCTL_EN 0x00000002 /* enable tx */ #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ /* Receive Checksum Control */ #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ +/* Multiple Receive Queue Control */ +#define E1000_MRQC_ENABLE_MASK 0x00000003 +#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 +#define E1000_MRQC_ENABLE_RSS_INT 0x00000004 +#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 +#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 +#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 +#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000 +#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 +#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 /* Definitions for power management and wakeup registers */ /* Wake Up Control */ #define E1000_WUC_APME 0x00000001 /* APM Enable */ #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ /* Wake Up Filter Control */ #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ /* Wake Up Status */ #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ /* Management Control */ #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery * Filtering */ #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address * filtering */ #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host * memory */ #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address * filtering */ #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ /* SW Semaphore Register */ #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ /* FW Semaphore Register */ #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ #define E1000_FWSM_MODE_SHIFT 1 #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ /* FFLT Debug Register */ #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ typedef enum { em_mng_mode_none = 0, em_mng_mode_asf, em_mng_mode_pt, em_mng_mode_ipmi, em_mng_mode_host_interface_only } em_mng_mode; /* Host Inteface Control Register */ #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done * to put command in RAM */ #define E1000_HICR_SV 0x00000004 /* Status Validity */ #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ /* Host Interface Command Interface - Address range 0x8800-0x8EFF */ #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ struct em_host_command_header { uint8_t command_id; uint8_t command_length; uint8_t command_options; /* I/F bits for command, status for return */ uint8_t checksum; }; struct em_host_command_info { struct em_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ }; /* Host SMB register #0 */ #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ /* Host SMB register #1 */ #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN #define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN #define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT /* FW Status Register */ #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ /* Wake Up Packet Length */ #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ #define E1000_MDALIGN 4096 -#define E1000_GCR_BEM32 0x00400000 +#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 /* Function Active and Power State to MNG */ #define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 #define E1000_FACTPS_LAN0_VALID 0x00000004 #define E1000_FACTPS_FUNC0_AUX_EN 0x00000008 #define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0 #define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6 #define E1000_FACTPS_LAN1_VALID 0x00000100 #define E1000_FACTPS_FUNC1_AUX_EN 0x00000200 #define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000 #define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12 #define E1000_FACTPS_IDE_ENABLE 0x00004000 #define E1000_FACTPS_FUNC2_AUX_EN 0x00008000 #define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000 #define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18 #define E1000_FACTPS_SP_ENABLE 0x00100000 #define E1000_FACTPS_FUNC3_AUX_EN 0x00200000 #define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000 #define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24 #define E1000_FACTPS_IPMI_ENABLE 0x04000000 #define E1000_FACTPS_FUNC4_AUX_EN 0x08000000 #define E1000_FACTPS_MNGCG 0x20000000 #define E1000_FACTPS_LAN_FUNC_SEL 0x40000000 #define E1000_FACTPS_PM_STATE_CHANGED 0x80000000 /* EEPROM Commands - Microwire */ #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ /* EEPROM Commands - SPI */ #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ /* EEPROM Size definitions */ #define EEPROM_WORD_SIZE_SHIFT 6 #define EEPROM_SIZE_SHIFT 10 #define EEPROM_SIZE_MASK 0x1C00 /* EEPROM Word Offsets */ #define EEPROM_COMPAT 0x0003 #define EEPROM_ID_LED_SETTINGS 0x0004 +#define EEPROM_VERSION 0x0005 #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ #define EEPROM_PHY_CLASS_WORD 0x0007 #define EEPROM_INIT_CONTROL1_REG 0x000A #define EEPROM_INIT_CONTROL2_REG 0x000F #define EEPROM_INIT_CONTROL3_PORT_B 0x0014 #define EEPROM_INIT_CONTROL3_PORT_A 0x0024 #define EEPROM_CFG 0x0012 #define EEPROM_FLASH_VERSION 0x0032 #define EEPROM_CHECKSUM_REG 0x003F +#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ + /* Word definitions for ID LED Settings */ #define ID_LED_RESERVED_0000 0x0000 #define ID_LED_RESERVED_FFFF 0xFFFF #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) #define ID_LED_DEF1_DEF2 0x1 #define ID_LED_DEF1_ON2 0x2 #define ID_LED_DEF1_OFF2 0x3 #define ID_LED_ON1_DEF2 0x4 #define ID_LED_ON1_ON2 0x5 #define ID_LED_ON1_OFF2 0x6 #define ID_LED_OFF1_DEF2 0x7 #define ID_LED_OFF1_ON2 0x8 #define ID_LED_OFF1_OFF2 0x9 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF #define IGP_ACTIVITY_LED_ENABLE 0x0300 #define IGP_LED3_MODE 0x07000000 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F /* Mask bit for PHY class in Word 7 of the EEPROM */ #define EEPROM_PHY_CLASS_A 0x8000 /* Mask bits for fields in Word 0x0a of the EEPROM */ #define EEPROM_WORD0A_ILOS 0x0010 #define EEPROM_WORD0A_SWDPIO 0x01E0 #define EEPROM_WORD0A_LRST 0x0200 #define EEPROM_WORD0A_FD 0x0400 #define EEPROM_WORD0A_66MHZ 0x0800 /* Mask bits for fields in Word 0x0f of the EEPROM */ #define EEPROM_WORD0F_PAUSE_MASK 0x3000 #define EEPROM_WORD0F_PAUSE 0x1000 #define EEPROM_WORD0F_ASM_DIR 0x2000 #define EEPROM_WORD0F_ANE 0x0800 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ #define EEPROM_SUM 0xBABA /* EEPROM Map defines (WORD OFFSETS)*/ #define EEPROM_NODE_ADDRESS_BYTE_0 0 #define EEPROM_PBA_BYTE_1 8 #define EEPROM_RESERVED_WORD 0xFFFF /* EEPROM Map Sizes (Byte Counts) */ #define PBA_SIZE 4 /* Collision related configuration parameters */ #define E1000_COLLISION_THRESHOLD 15 #define E1000_CT_SHIFT 4 #define E1000_COLLISION_DISTANCE 64 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE #define E1000_COLD_SHIFT 12 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ #define REQ_TX_DESCRIPTOR_MULTIPLE 8 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 /* Default values for the transmit IPG register */ #define DEFAULT_82542_TIPG_IPGT 10 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 #define E1000_TIPG_IPGT_MASK 0x000003FF #define E1000_TIPG_IPGR1_MASK 0x000FFC00 #define E1000_TIPG_IPGR2_MASK 0x3FF00000 #define DEFAULT_82542_TIPG_IPGR1 2 #define DEFAULT_82543_TIPG_IPGR1 8 #define E1000_TIPG_IPGR1_SHIFT 10 #define DEFAULT_82542_TIPG_IPGR2 10 #define DEFAULT_82543_TIPG_IPGR2 6 #define E1000_TIPG_IPGR2_SHIFT 20 #define E1000_TXDMAC_DPP 0x00000001 /* Adaptive IFS defines */ #define TX_THRESHOLD_START 8 #define TX_THRESHOLD_INCREMENT 10 #define TX_THRESHOLD_DECREMENT 1 #define TX_THRESHOLD_STOP 190 #define TX_THRESHOLD_DISABLE 0 #define TX_THRESHOLD_TIMER_MS 10000 #define MIN_NUM_XMITS 1000 #define IFS_MAX 80 #define IFS_STEP 10 #define IFS_MIN 40 #define IFS_RATIO 4 /* Extended Configuration Control and Size */ #define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001 #define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002 #define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004 #define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008 #define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 #define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000 #define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF #define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 /* PBA constants */ #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ #define E1000_PBA_22K 0x0016 #define E1000_PBA_24K 0x0018 #define E1000_PBA_30K 0x001E +#define E1000_PBA_32K 0x0020 +#define E1000_PBA_38K 0x0026 #define E1000_PBA_40K 0x0028 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ /* Flow Control Constants */ #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 #define FLOW_CONTROL_TYPE 0x8808 /* The historical defaults for the flow control values are given below. */ #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ /* PCIX Config space */ #define PCIX_COMMAND_REGISTER 0xE6 #define PCIX_STATUS_REGISTER_LO 0xE8 #define PCIX_STATUS_REGISTER_HI 0xEA #define PCIX_COMMAND_MMRBC_MASK 0x000C #define PCIX_COMMAND_MMRBC_SHIFT 0x2 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 #define PCIX_STATUS_HI_MMRBC_4K 0x3 #define PCIX_STATUS_HI_MMRBC_2K 0x2 /* Number of bits required to shift right the "pause" bits from the * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. */ #define PAUSE_SHIFT 5 /* Number of bits required to shift left the "SWDPIO" bits from the * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register. */ #define SWDPIO_SHIFT 17 /* Number of bits required to shift left the "SWDPIO_EXT" bits from the * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register. */ #define SWDPIO__EXT_SHIFT 4 /* Number of bits required to shift left the "ILOS" bit from the EEPROM * (bit 4) to the "ILOS" (bit 7) field in the CTRL register. */ #define ILOS_SHIFT 3 #define RECEIVE_BUFFER_ALIGN_SIZE (256) /* Number of milliseconds we wait for auto-negotiation to complete */ #define LINK_UP_TIMEOUT 500 /* Number of 100 microseconds we wait for PCI Express master disable */ #define MASTER_DISABLE_TIMEOUT 800 /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ #define AUTO_READ_DONE_TIMEOUT 10 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ #define PHY_CFG_TIMEOUT 40 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) /* The carrier extension symbol, as received by the NIC. */ #define CARRIER_EXTENSION 0x0F /* TBI_ACCEPT macro definition: * * This macro requires: * adapter = a pointer to struct em_hw * status = the 8 bit status field of the RX descriptor with EOP set * error = the 8 bit error field of the RX descriptor with EOP set * length = the sum of all the length fields of the RX descriptors that * make up the current frame * last_byte = the last byte of the frame DMAed by the hardware * max_frame_length = the maximum frame length we want to accept. * min_frame_length = the minimum frame length we want to accept. * * This macro is a conditional that should be used in the interrupt * handler's Rx processing routine when RxErrors have been detected. * * Typical use: * ... * if (TBI_ACCEPT) { * accept_frame = TRUE; * em_tbi_adjust_stats(adapter, MacAddress); * frame_length--; * } else { * accept_frame = FALSE; * } * ... */ #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ ((adapter)->tbi_compatibility_on && \ (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ ((last_byte) == CARRIER_EXTENSION) && \ (((status) & E1000_RXD_STAT_VP) ? \ (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ ((length) <= ((adapter)->max_frame_size + 1))) : \ (((length) > (adapter)->min_frame_size) && \ ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) /* Structures, enums, and macros for the PHY */ /* Bit definitions for the Management Data IO (MDIO) and Management Data * Clock (MDC) pins in the Device Control Register. */ #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA /* PHY 1000 MII Register/Bit Definitions */ /* PHY Registers defined by IEEE */ #define PHY_CTRL 0x00 /* Control Register */ #define PHY_STATUS 0x01 /* Status Regiser */ #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ +#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ + /* M88E1000 Specific Registers */ #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ #define IGP01E1000_IEEE_REGS_PAGE 0x0000 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 /* IGP01E1000 Specific Registers */ #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ #define IGP02E1000_PHY_POWER_MGMT 0x19 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ /* IGP01E1000 AGC Registers - stores the cable length values*/ #define IGP01E1000_PHY_AGC_A 0x1172 #define IGP01E1000_PHY_AGC_B 0x1272 #define IGP01E1000_PHY_AGC_C 0x1472 #define IGP01E1000_PHY_AGC_D 0x1872 /* IGP02E1000 AGC Registers for cable length values */ #define IGP02E1000_PHY_AGC_A 0x11B1 #define IGP02E1000_PHY_AGC_B 0x12B1 #define IGP02E1000_PHY_AGC_C 0x14B1 #define IGP02E1000_PHY_AGC_D 0x18B1 /* IGP01E1000 DSP Reset Register */ #define IGP01E1000_PHY_DSP_RESET 0x1F33 #define IGP01E1000_PHY_DSP_SET 0x1F71 #define IGP01E1000_PHY_DSP_FFE 0x1F35 #define IGP01E1000_PHY_CHANNEL_NUM 4 #define IGP02E1000_PHY_CHANNEL_NUM 4 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A /* IGP01E1000 PCS Initialization register - stores the polarity status when * speed = 1000 Mbps. */ #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 -#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ -#define MAX_PHY_MULTI_PAGE_REG 0xF /*Registers that are equal on all pages*/ /* PHY Control Register */ #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ #define MII_CR_POWER_DOWN 0x0800 /* Power down */ #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ /* PHY Status Register */ #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ /* Autoneg Advertisement Register */ #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ /* Link Partner Ability Register (Base Page) */ #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ /* Autoneg Expansion Register */ #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ /* Next Page TX Register */ #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges * of different NP */ #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg * 0 = cannot comply with msg */ #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow * 0 = sending last NP */ /* Link Partner Next Page Register */ #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges * of different NP */ #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg * 0 = cannot comply with msg */ #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow * 0 = sending last NP */ /* 1000BASE-T Control Register */ #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ /* 0=DTE device */ #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ /* 0=Configure PHY as Slave */ #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ /* 0=Automatic Master/Slave config */ #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ /* 1000BASE-T Status Register */ #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 /* Extended Status Register */ #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ /* (0=enable, 1=disable) */ /* M88E1000 PHY Specific Control Register */ #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, * 0=CLK125 toggling */ #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ /* Manual MDI configuration */ #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, * 100BASE-TX/10BASE-T: * MDI Mode */ #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled * all speeds. */ #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance * (Lower 10BASE-T RX Threshold) * 0=Normal 10BASE-T RX Threshold */ #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 100BASE-TX * 0=MII interface in 100BASE-TX */ #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 /* M88E1000 PHY Specific Status Register */ #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; * 3=110-140M;4=>140M */ #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 #define M88E1000_PSSR_MDIX_SHIFT 6 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 /* M88E1000 Extended PHY Specific Control Register */ #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. * Will assert lost lock and bring * link down if idle not seen * within 1ms in 1000BASE-T */ /* Number of times we will attempt to autonegotiate before downshifting if we * are the master */ #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 /* Number of times we will attempt to autonegotiate before downshifting if we * are the slave */ #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ /* IGP01E1000 Specific Port Config Register - R/W */ #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 #define IGP01E1000_PSCFR_PRE_EN 0x0020 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 /* IGP01E1000 Specific Port Status Register - R/O */ #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 #define IGP01E1000_PSSR_LINK_UP 0x0400 #define IGP01E1000_PSSR_MDIX 0x0800 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ /* IGP01E1000 Specific Port Control Register - R/W */ #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 #define IGP01E1000_PSCR_FLIP_CHIP 0x0800 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ /* IGP01E1000 Specific Port Link Health Register */ #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 #define IGP01E1000_PLHR_MASTER_FAULT 0x2000 #define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ #define IGP01E1000_PLHR_DATA_ERR_0 0x0100 #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 #define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008 #define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004 #define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002 #define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001 /* IGP01E1000 Channel Quality Register */ #define IGP01E1000_MSE_CHANNEL_D 0x000F #define IGP01E1000_MSE_CHANNEL_C 0x00F0 #define IGP01E1000_MSE_CHANNEL_B 0x0F00 #define IGP01E1000_MSE_CHANNEL_A 0xF000 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ /* IGP01E1000 DSP reset macros */ #define DSP_RESET_ENABLE 0x0 #define DSP_RESET_DISABLE 0x2 #define E1000_MAX_DSP_RESETS 10 /* IGP01E1000 & IGP02E1000 AGC Registers */ #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ /* IGP02E1000 AGC Register Length 9-bit mask */ #define IGP02E1000_AGC_LENGTH_MASK 0x7F /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 -#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 128 +#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113 /* The precision error of the cable length is +/- 10 meters */ #define IGP01E1000_AGC_RANGE 10 -#define IGP02E1000_AGC_RANGE 10 +#define IGP02E1000_AGC_RANGE 15 /* IGP01E1000 PCS Initialization register */ /* bits 3:6 in the PCS registers stores the channels polarity */ #define IGP01E1000_PHY_POLARITY_MASK 0x0078 /* IGP01E1000 GMII FIFO Register */ #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed * on Link-Up */ #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ /* IGP01E1000 Analog Register */ #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 /* Bit definitions for valid PHY IDs. */ /* I = Integrated * E = External */ #define M88E1000_E_PHY_ID 0x01410C50 #define M88E1000_I_PHY_ID 0x01410C30 #define M88E1011_I_PHY_ID 0x01410C20 #define IGP01E1000_I_PHY_ID 0x02A80380 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID #define M88E1011_I_REV_4 0x04 #define M88E1111_I_PHY_ID 0x01410CC0 #define L1LXT971A_PHY_ID 0x001378E0 /* Miscellaneous PHY bit definitions. */ #define PHY_PREAMBLE 0xFFFFFFFF #define PHY_SOF 0x01 #define PHY_OP_READ 0x02 #define PHY_OP_WRITE 0x01 #define PHY_TURNAROUND 0x02 #define PHY_PREAMBLE_SIZE 32 #define MII_CR_SPEED_1000 0x0040 #define MII_CR_SPEED_100 0x2000 #define MII_CR_SPEED_10 0x0000 #define E1000_PHY_ADDRESS 0x01 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ #define PHY_REVISION_MASK 0xFFFFFFF0 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ #define REG4_SPEED_MASK 0x01E0 #define REG9_SPEED_MASK 0x0300 #define ADVERTISE_10_HALF 0x0001 #define ADVERTISE_10_FULL 0x0002 #define ADVERTISE_100_HALF 0x0004 #define ADVERTISE_100_FULL 0x0008 #define ADVERTISE_1000_HALF 0x0010 #define ADVERTISE_1000_FULL 0x0020 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ #endif /* _EM_HW_H_ */