diff --git a/sys/dev/axgbe/xgbe-phy-v2.c b/sys/dev/axgbe/xgbe-phy-v2.c
index 5fb6e960eab5..df8a75a145b9 100644
--- a/sys/dev/axgbe/xgbe-phy-v2.c
+++ b/sys/dev/axgbe/xgbe-phy-v2.c
@@ -1,3771 +1,3785 @@
/*
* AMD 10Gb Ethernet driver
*
* Copyright (c) 2020 Advanced Micro Devices, Inc.
*
* This file is available to you under your choice of the following two
* licenses:
*
* License 1: GPLv2
*
* This file is free software; you may copy, redistribute and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or (at
* your option) any later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*
* This file incorporates work covered by the following copyright and
* permission notice:
* The Synopsys DWC ETHER XGMAC Software Driver and documentation
* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
* Inc. unless otherwise expressly agreed to in writing between Synopsys
* and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product
* under any End User Software License Agreement or Agreement for Licensed
* Product with Synopsys or any supplement thereto. Permission is hereby
* granted, free of charge, to any person obtaining a copy of this software
* annotated with this license and the Software, to deal in the Software
* without restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
*
* License 2: Modified BSD
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* The Synopsys DWC ETHER XGMAC Software Driver and documentation
* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
* Inc. unless otherwise expressly agreed to in writing between Synopsys
* and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product
* under any End User Software License Agreement or Agreement for Licensed
* Product with Synopsys or any supplement thereto. Permission is hereby
* granted, free of charge, to any person obtaining a copy of this software
* annotated with this license and the Software, to deal in the Software
* without restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#include
__FBSDID("$FreeBSD$");
#include "xgbe.h"
#include "xgbe-common.h"
struct mtx xgbe_phy_comm_lock;
#define XGBE_PHY_PORT_SPEED_100 BIT(0)
#define XGBE_PHY_PORT_SPEED_1000 BIT(1)
#define XGBE_PHY_PORT_SPEED_2500 BIT(2)
#define XGBE_PHY_PORT_SPEED_10000 BIT(3)
#define XGBE_MUTEX_RELEASE 0x80000000
#define XGBE_SFP_DIRECT 7
#define GPIO_MASK_WIDTH 4
/* I2C target addresses */
#define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
#define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
#define XGBE_SFP_PHY_ADDRESS 0x56
#define XGBE_GPIO_ADDRESS_PCA9555 0x20
/* SFP sideband signal indicators */
#define XGBE_GPIO_NO_TX_FAULT BIT(0)
#define XGBE_GPIO_NO_RATE_SELECT BIT(1)
#define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
#define XGBE_GPIO_NO_RX_LOS BIT(3)
/* Rate-change complete wait/retry count */
#define XGBE_RATECHANGE_COUNT 500
/* CDR delay values for KR support (in usec) */
#define XGBE_CDR_DELAY_INIT 10000
#define XGBE_CDR_DELAY_INC 10000
#define XGBE_CDR_DELAY_MAX 100000
/* RRC frequency during link status check */
#define XGBE_RRC_FREQUENCY 10
enum xgbe_port_mode {
XGBE_PORT_MODE_RSVD = 0,
XGBE_PORT_MODE_BACKPLANE,
XGBE_PORT_MODE_BACKPLANE_2500,
XGBE_PORT_MODE_1000BASE_T,
XGBE_PORT_MODE_1000BASE_X,
XGBE_PORT_MODE_NBASE_T,
XGBE_PORT_MODE_10GBASE_T,
XGBE_PORT_MODE_10GBASE_R,
XGBE_PORT_MODE_SFP,
XGBE_PORT_MODE_MAX,
};
enum xgbe_conn_type {
XGBE_CONN_TYPE_NONE = 0,
XGBE_CONN_TYPE_SFP,
XGBE_CONN_TYPE_MDIO,
XGBE_CONN_TYPE_RSVD1,
XGBE_CONN_TYPE_BACKPLANE,
XGBE_CONN_TYPE_MAX,
};
/* SFP/SFP+ related definitions */
enum xgbe_sfp_comm {
XGBE_SFP_COMM_DIRECT = 0,
XGBE_SFP_COMM_PCA9545,
};
enum xgbe_sfp_cable {
XGBE_SFP_CABLE_UNKNOWN = 0,
XGBE_SFP_CABLE_ACTIVE,
XGBE_SFP_CABLE_PASSIVE,
};
enum xgbe_sfp_base {
XGBE_SFP_BASE_UNKNOWN = 0,
XGBE_SFP_BASE_1000_T,
XGBE_SFP_BASE_1000_SX,
XGBE_SFP_BASE_1000_LX,
XGBE_SFP_BASE_1000_CX,
XGBE_SFP_BASE_10000_SR,
XGBE_SFP_BASE_10000_LR,
XGBE_SFP_BASE_10000_LRM,
XGBE_SFP_BASE_10000_ER,
XGBE_SFP_BASE_10000_CR,
};
enum xgbe_sfp_speed {
XGBE_SFP_SPEED_UNKNOWN = 0,
XGBE_SFP_SPEED_100_1000,
XGBE_SFP_SPEED_1000,
XGBE_SFP_SPEED_10000,
};
/* SFP Serial ID Base ID values relative to an offset of 0 */
#define XGBE_SFP_BASE_ID 0
#define XGBE_SFP_ID_SFP 0x03
#define XGBE_SFP_BASE_EXT_ID 1
#define XGBE_SFP_EXT_ID_SFP 0x04
+#define XGBE_SFP_BASE_CV 2
+#define XGBE_SFP_BASE_CV_CP 0x21
+
#define XGBE_SFP_BASE_10GBE_CC 3
#define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
#define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
#define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
#define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
#define XGBE_SFP_BASE_1GBE_CC 6
#define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
#define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
#define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
#define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
#define XGBE_SFP_BASE_CABLE 8
#define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
#define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
#define XGBE_SFP_BASE_BR 12
#define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
#define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
#define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
#define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
#define XGBE_SFP_BASE_CU_CABLE_LEN 18
#define XGBE_SFP_BASE_VENDOR_NAME 20
#define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
#define XGBE_SFP_BASE_VENDOR_PN 40
#define XGBE_SFP_BASE_VENDOR_PN_LEN 16
#define XGBE_SFP_BASE_VENDOR_REV 56
#define XGBE_SFP_BASE_VENDOR_REV_LEN 4
#define XGBE_SFP_BASE_CC 63
/* SFP Serial ID Extended ID values relative to an offset of 64 */
#define XGBE_SFP_BASE_VENDOR_SN 4
#define XGBE_SFP_BASE_VENDOR_SN_LEN 16
#define XGBE_SFP_EXTD_OPT1 1
#define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
#define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
#define XGBE_SFP_EXTD_DIAG 28
#define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
#define XGBE_SFP_EXTD_SFF_8472 30
#define XGBE_SFP_EXTD_CC 31
struct xgbe_sfp_eeprom {
uint8_t base[64];
uint8_t extd[32];
uint8_t vendor[32];
};
#define XGBE_SFP_DIAGS_SUPPORTED(_x) \
((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
!((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
#define XGBE_SFP_EEPROM_BASE_LEN 256
#define XGBE_SFP_EEPROM_DIAG_LEN 256
#define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
XGBE_SFP_EEPROM_DIAG_LEN)
#define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
#define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
struct xgbe_sfp_ascii {
union {
char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
} u;
};
/* MDIO PHY reset types */
enum xgbe_mdio_reset {
XGBE_MDIO_RESET_NONE = 0,
XGBE_MDIO_RESET_I2C_GPIO,
XGBE_MDIO_RESET_INT_GPIO,
XGBE_MDIO_RESET_MAX,
};
/* Re-driver related definitions */
enum xgbe_phy_redrv_if {
XGBE_PHY_REDRV_IF_MDIO = 0,
XGBE_PHY_REDRV_IF_I2C,
XGBE_PHY_REDRV_IF_MAX,
};
enum xgbe_phy_redrv_model {
XGBE_PHY_REDRV_MODEL_4223 = 0,
XGBE_PHY_REDRV_MODEL_4227,
XGBE_PHY_REDRV_MODEL_MAX,
};
enum xgbe_phy_redrv_mode {
XGBE_PHY_REDRV_MODE_CX = 5,
XGBE_PHY_REDRV_MODE_SR = 9,
};
#define XGBE_PHY_REDRV_MODE_REG 0x12b0
/* PHY related configuration information */
struct xgbe_phy_data {
enum xgbe_port_mode port_mode;
unsigned int port_id;
unsigned int port_speeds;
enum xgbe_conn_type conn_type;
enum xgbe_mode cur_mode;
enum xgbe_mode start_mode;
unsigned int rrc_count;
unsigned int mdio_addr;
/* SFP Support */
enum xgbe_sfp_comm sfp_comm;
unsigned int sfp_mux_address;
unsigned int sfp_mux_channel;
unsigned int sfp_gpio_address;
unsigned int sfp_gpio_mask;
unsigned int sfp_gpio_inputs;
unsigned int sfp_gpio_rx_los;
unsigned int sfp_gpio_tx_fault;
unsigned int sfp_gpio_mod_absent;
unsigned int sfp_gpio_rate_select;
unsigned int sfp_rx_los;
unsigned int sfp_tx_fault;
unsigned int sfp_mod_absent;
unsigned int sfp_changed;
unsigned int sfp_phy_avail;
unsigned int sfp_cable_len;
enum xgbe_sfp_base sfp_base;
enum xgbe_sfp_cable sfp_cable;
enum xgbe_sfp_speed sfp_speed;
struct xgbe_sfp_eeprom sfp_eeprom;
/* External PHY support */
enum xgbe_mdio_mode phydev_mode;
uint32_t phy_id;
int phydev;
enum xgbe_mdio_reset mdio_reset;
unsigned int mdio_reset_addr;
unsigned int mdio_reset_gpio;
/* Re-driver support */
unsigned int redrv;
unsigned int redrv_if;
unsigned int redrv_addr;
unsigned int redrv_lane;
unsigned int redrv_model;
/* KR AN support */
unsigned int phy_cdr_notrack;
unsigned int phy_cdr_delay;
uint8_t port_sfp_inputs;
};
static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
+static int xgbe_phy_reset(struct xgbe_prv_data *pdata);
static int
xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *i2c_op)
{
return (pdata->i2c_if.i2c_xfer(pdata, i2c_op));
}
static int
xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
unsigned int val)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
struct xgbe_i2c_op i2c_op;
__be16 *redrv_val;
uint8_t redrv_data[5], csum;
unsigned int i, retry;
int ret;
/* High byte of register contains read/write indicator */
redrv_data[0] = ((reg >> 8) & 0xff) << 1;
redrv_data[1] = reg & 0xff;
redrv_val = (__be16 *)&redrv_data[2];
*redrv_val = cpu_to_be16(val);
/* Calculate 1 byte checksum */
csum = 0;
for (i = 0; i < 4; i++) {
csum += redrv_data[i];
if (redrv_data[i] > csum)
csum++;
}
redrv_data[4] = ~csum;
retry = 1;
again1:
i2c_op.cmd = XGBE_I2C_CMD_WRITE;
i2c_op.target = phy_data->redrv_addr;
i2c_op.len = sizeof(redrv_data);
i2c_op.buf = redrv_data;
ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
if (ret) {
if ((ret == -EAGAIN) && retry--)
goto again1;
return (ret);
}
retry = 1;
again2:
i2c_op.cmd = XGBE_I2C_CMD_READ;
i2c_op.target = phy_data->redrv_addr;
i2c_op.len = 1;
i2c_op.buf = redrv_data;
ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
if (ret) {
if ((ret == -EAGAIN) && retry--)
goto again2;
return (ret);
}
if (redrv_data[0] != 0xff) {
axgbe_error("Redriver write checksum error\n");
ret = -EIO;
}
return (ret);
}
static int
xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, void *val,
unsigned int val_len)
{
struct xgbe_i2c_op i2c_op;
int retry, ret;
retry = 1;
again:
/* Write the specfied register */
i2c_op.cmd = XGBE_I2C_CMD_WRITE;
i2c_op.target = target;
i2c_op.len = val_len;
i2c_op.buf = val;
ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
if ((ret == -EAGAIN) && retry--)
goto again;
return (ret);
}
static int
xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, void *reg,
unsigned int reg_len, void *val, unsigned int val_len)
{
struct xgbe_i2c_op i2c_op;
int retry, ret;
axgbe_printf(3, "%s: target 0x%x reg_len %d val_len %d\n", __func__,
target, reg_len, val_len);
retry = 1;
again1:
/* Set the specified register to read */
i2c_op.cmd = XGBE_I2C_CMD_WRITE;
i2c_op.target = target;
i2c_op.len = reg_len;
i2c_op.buf = reg;
ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
axgbe_printf(3, "%s: ret1 %d retry %d\n", __func__, ret, retry);
if (ret) {
if ((ret == -EAGAIN) && retry--)
goto again1;
return (ret);
}
retry = 1;
again2:
/* Read the specfied register */
i2c_op.cmd = XGBE_I2C_CMD_READ;
i2c_op.target = target;
i2c_op.len = val_len;
i2c_op.buf = val;
ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
axgbe_printf(3, "%s: ret2 %d retry %d\n", __func__, ret, retry);
if ((ret == -EAGAIN) && retry--)
goto again2;
return (ret);
}
static int
xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
struct xgbe_i2c_op i2c_op;
uint8_t mux_channel;
if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
return (0);
/* Select no mux channels */
mux_channel = 0;
i2c_op.cmd = XGBE_I2C_CMD_WRITE;
i2c_op.target = phy_data->sfp_mux_address;
i2c_op.len = sizeof(mux_channel);
i2c_op.buf = &mux_channel;
return (xgbe_phy_i2c_xfer(pdata, &i2c_op));
}
static int
xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
struct xgbe_i2c_op i2c_op;
uint8_t mux_channel;
if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
return (0);
/* Select desired mux channel */
mux_channel = 1 << phy_data->sfp_mux_channel;
i2c_op.cmd = XGBE_I2C_CMD_WRITE;
i2c_op.target = phy_data->sfp_mux_address;
i2c_op.len = sizeof(mux_channel);
i2c_op.buf = &mux_channel;
return (xgbe_phy_i2c_xfer(pdata, &i2c_op));
}
static void
xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
{
mtx_unlock(&xgbe_phy_comm_lock);
}
static int
xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
unsigned long timeout;
unsigned int mutex_id;
/* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
* the driver needs to take the software mutex and then the hardware
* mutexes before being able to use the busses.
*/
mtx_lock(&xgbe_phy_comm_lock);
/* Clear the mutexes */
XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
/* Mutex formats are the same for I2C and MDIO/GPIO */
mutex_id = 0;
XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
timeout = ticks + (5 * hz);
while (ticks < timeout) {
/* Must be all zeroes in order to obtain the mutex */
if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
DELAY(200);
continue;
}
/* Obtain the mutex */
XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
return (0);
}
mtx_unlock(&xgbe_phy_comm_lock);
axgbe_error("unable to obtain hardware mutexes\n");
return (-ETIMEDOUT);
}
static int
xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, int reg,
uint16_t val)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
if (reg & MII_ADDR_C45) {
if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
return (-ENOTSUP);
} else {
if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
return (-ENOTSUP);
}
return (pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val));
}
static int
xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, uint16_t val)
{
__be16 *mii_val;
uint8_t mii_data[3];
int ret;
ret = xgbe_phy_sfp_get_mux(pdata);
if (ret)
return (ret);
mii_data[0] = reg & 0xff;
mii_val = (__be16 *)&mii_data[1];
*mii_val = cpu_to_be16(val);
ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
mii_data, sizeof(mii_data));
xgbe_phy_sfp_put_mux(pdata);
return (ret);
}
int
xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, uint16_t val)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
int ret;
axgbe_printf(3, "%s: addr %d reg %d val %#x\n", __func__, addr, reg, val);
ret = xgbe_phy_get_comm_ownership(pdata);
if (ret)
return (ret);
if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
else
ret = -ENOTSUP;
xgbe_phy_put_comm_ownership(pdata);
return (ret);
}
static int
xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
if (reg & MII_ADDR_C45) {
if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
return (-ENOTSUP);
} else {
if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
return (-ENOTSUP);
}
return (pdata->hw_if.read_ext_mii_regs(pdata, addr, reg));
}
static int
xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
{
__be16 mii_val;
uint8_t mii_reg;
int ret;
ret = xgbe_phy_sfp_get_mux(pdata);
if (ret)
return (ret);
mii_reg = reg;
ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
&mii_reg, sizeof(mii_reg),
&mii_val, sizeof(mii_val));
if (!ret)
ret = be16_to_cpu(mii_val);
xgbe_phy_sfp_put_mux(pdata);
return (ret);
}
int
xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
int ret;
axgbe_printf(3, "%s: addr %d reg %d\n", __func__, addr, reg);
ret = xgbe_phy_get_comm_ownership(pdata);
if (ret)
return (ret);
if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
ret = xgbe_phy_i2c_mii_read(pdata, reg);
else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
else
ret = -ENOTSUP;
xgbe_phy_put_comm_ownership(pdata);
return (ret);
}
static void
xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
return;
XGBE_ZERO_SUP(&pdata->phy);
if (phy_data->sfp_mod_absent) {
pdata->phy.speed = SPEED_UNKNOWN;
pdata->phy.duplex = DUPLEX_UNKNOWN;
pdata->phy.autoneg = AUTONEG_ENABLE;
pdata->phy.pause_autoneg = AUTONEG_ENABLE;
XGBE_SET_SUP(&pdata->phy, Autoneg);
XGBE_SET_SUP(&pdata->phy, Pause);
XGBE_SET_SUP(&pdata->phy, Asym_Pause);
XGBE_SET_SUP(&pdata->phy, TP);
XGBE_SET_SUP(&pdata->phy, FIBRE);
XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
return;
}
switch (phy_data->sfp_base) {
case XGBE_SFP_BASE_1000_T:
case XGBE_SFP_BASE_1000_SX:
case XGBE_SFP_BASE_1000_LX:
case XGBE_SFP_BASE_1000_CX:
pdata->phy.speed = SPEED_UNKNOWN;
pdata->phy.duplex = DUPLEX_UNKNOWN;
pdata->phy.autoneg = AUTONEG_ENABLE;
pdata->phy.pause_autoneg = AUTONEG_ENABLE;
XGBE_SET_SUP(&pdata->phy, Autoneg);
XGBE_SET_SUP(&pdata->phy, Pause);
XGBE_SET_SUP(&pdata->phy, Asym_Pause);
if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
} else {
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
}
break;
case XGBE_SFP_BASE_10000_SR:
case XGBE_SFP_BASE_10000_LR:
case XGBE_SFP_BASE_10000_LRM:
case XGBE_SFP_BASE_10000_ER:
case XGBE_SFP_BASE_10000_CR:
pdata->phy.speed = SPEED_10000;
pdata->phy.duplex = DUPLEX_FULL;
pdata->phy.autoneg = AUTONEG_DISABLE;
pdata->phy.pause_autoneg = AUTONEG_DISABLE;
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
switch (phy_data->sfp_base) {
case XGBE_SFP_BASE_10000_SR:
XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
break;
case XGBE_SFP_BASE_10000_LR:
XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
break;
case XGBE_SFP_BASE_10000_LRM:
XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
break;
case XGBE_SFP_BASE_10000_ER:
XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
break;
case XGBE_SFP_BASE_10000_CR:
XGBE_SET_SUP(&pdata->phy, 10000baseCR_Full);
break;
default:
break;
}
}
break;
default:
pdata->phy.speed = SPEED_UNKNOWN;
pdata->phy.duplex = DUPLEX_UNKNOWN;
pdata->phy.autoneg = AUTONEG_DISABLE;
pdata->phy.pause_autoneg = AUTONEG_DISABLE;
break;
}
switch (phy_data->sfp_base) {
case XGBE_SFP_BASE_1000_T:
case XGBE_SFP_BASE_1000_CX:
case XGBE_SFP_BASE_10000_CR:
XGBE_SET_SUP(&pdata->phy, TP);
break;
default:
XGBE_SET_SUP(&pdata->phy, FIBRE);
break;
}
XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
axgbe_printf(1, "%s: link speed %d spf_base 0x%x pause_autoneg %d "
"advert 0x%x support 0x%x\n", __func__, pdata->phy.speed,
phy_data->sfp_base, pdata->phy.pause_autoneg,
pdata->phy.advertising, pdata->phy.supported);
}
static bool
xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
enum xgbe_sfp_speed sfp_speed)
{
uint8_t *sfp_base, min, max;
sfp_base = sfp_eeprom->base;
switch (sfp_speed) {
case XGBE_SFP_SPEED_1000:
min = XGBE_SFP_BASE_BR_1GBE_MIN;
max = XGBE_SFP_BASE_BR_1GBE_MAX;
break;
case XGBE_SFP_SPEED_10000:
min = XGBE_SFP_BASE_BR_10GBE_MIN;
max = XGBE_SFP_BASE_BR_10GBE_MAX;
break;
default:
return (false);
}
return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
(sfp_base[XGBE_SFP_BASE_BR] <= max));
}
static void
xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
if (phy_data->phydev)
phy_data->phydev = 0;
}
static bool
xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
unsigned int phy_id = phy_data->phy_id;
if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
return (false);
if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
return (false);
/* Enable Base-T AN */
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0001);
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0000);
/* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1b, 0x9084);
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x09, 0x0e00);
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x8140);
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x04, 0x0d01);
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
axgbe_printf(3, "Finisar PHY quirk in place\n");
return (true);
}
static bool
xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
unsigned int phy_id = phy_data->phy_id;
int reg;
if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
return (false);
if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
return (false);
/* For Bel-Fuse, use the extra AN flag */
pdata->an_again = 1;
if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
return (false);
if ((phy_id & 0xfffffff0) != 0x03625d10)
return (false);
/* Disable RGMII mode */
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, 0x7007);
reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x18);
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, reg & ~0x0080);
/* Enable fiber register bank */
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
reg &= 0x03ff;
reg &= ~0x0001;
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
reg | 0x0001);
/* Power down SerDes */
reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg | 0x00800);
/* Configure SGMII-to-Copper mode */
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
reg &= 0x03ff;
reg &= ~0x0006;
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
reg | 0x0004);
/* Power up SerDes */
reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
/* Enable copper register bank */
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
reg &= 0x03ff;
reg &= ~0x0001;
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
reg);
/* Power up SerDes */
reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
axgbe_printf(3, "BelFuse PHY quirk in place\n");
return (true);
}
static void
xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
{
if (xgbe_phy_belfuse_phy_quirks(pdata))
return;
if (xgbe_phy_finisar_phy_quirks(pdata))
return;
}
static int
xgbe_get_phy_id(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
uint32_t oui, model, phy_id1, phy_id2;
int phy_reg;
phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x02);
if (phy_reg < 0)
return (-EIO);
phy_id1 = (phy_reg & 0xffff);
phy_data->phy_id = (phy_reg & 0xffff) << 16;
phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x03);
if (phy_reg < 0)
return (-EIO);
phy_id2 = (phy_reg & 0xffff);
phy_data->phy_id |= (phy_reg & 0xffff);
oui = MII_OUI(phy_id1, phy_id2);
model = MII_MODEL(phy_id2);
axgbe_printf(2, "%s: phy_id1: 0x%x phy_id2: 0x%x oui: %#x model %#x\n",
__func__, phy_id1, phy_id2, oui, model);
return (0);
}
static int
xgbe_phy_start_aneg(struct xgbe_prv_data *pdata)
{
uint16_t ctl = 0;
int changed = 0;
int ret;
if (AUTONEG_ENABLE != pdata->phy.autoneg) {
if (SPEED_1000 == pdata->phy.speed)
ctl |= BMCR_SPEED1;
else if (SPEED_100 == pdata->phy.speed)
ctl |= BMCR_SPEED100;
if (DUPLEX_FULL == pdata->phy.duplex)
ctl |= BMCR_FDX;
ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
if (ret)
return (ret);
ret = xgbe_phy_mii_write(pdata, pdata->mdio_addr, MII_BMCR,
(ret & ~(~(BMCR_LOOP | BMCR_ISO | BMCR_PDOWN))) | ctl);
}
ctl = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
if (ctl < 0)
return (ctl);
if (!(ctl & BMCR_AUTOEN) || (ctl & BMCR_ISO))
changed = 1;
if (changed > 0) {
ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
if (ret)
return (ret);
ret = xgbe_phy_mii_write(pdata, pdata->mdio_addr, MII_BMCR,
(ret & ~(BMCR_ISO)) | (BMCR_AUTOEN | BMCR_STARTNEG));
}
return (0);
}
static int
xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
int ret;
axgbe_printf(2, "%s: phydev %d phydev_mode %d sfp_phy_avail %d phy_id "
"0x%08x\n", __func__, phy_data->phydev, phy_data->phydev_mode,
phy_data->sfp_phy_avail, phy_data->phy_id);
/* If we already have a PHY, just return */
if (phy_data->phydev) {
axgbe_printf(3, "%s: phy present already\n", __func__);
return (0);
}
/* Clear the extra AN flag */
pdata->an_again = 0;
/* Check for the use of an external PHY */
if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) {
axgbe_printf(3, "%s: phydev_mode %d\n", __func__,
phy_data->phydev_mode);
return (0);
}
/* For SFP, only use an external PHY if available */
if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
!phy_data->sfp_phy_avail) {
axgbe_printf(3, "%s: port_mode %d avail %d\n", __func__,
phy_data->port_mode, phy_data->sfp_phy_avail);
return (0);
}
/* Set the proper MDIO mode for the PHY */
ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
phy_data->phydev_mode);
if (ret) {
axgbe_error("mdio port/clause not compatible (%u/%u) ret %d\n",
phy_data->mdio_addr, phy_data->phydev_mode, ret);
return (ret);
}
ret = xgbe_get_phy_id(pdata);
if (ret)
return (ret);
axgbe_printf(2, "Get phy_id 0x%08x\n", phy_data->phy_id);
phy_data->phydev = 1;
xgbe_phy_external_phy_quirks(pdata);
xgbe_phy_start_aneg(pdata);
return (0);
}
static void
xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
int ret;
axgbe_printf(3, "%s: sfp_changed: 0x%x\n", __func__,
phy_data->sfp_changed);
if (!phy_data->sfp_changed)
return;
phy_data->sfp_phy_avail = 0;
if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
return;
/* Check access to the PHY by reading CTRL1 */
ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
if (ret < 0) {
axgbe_error("%s: ext phy fail %d\n", __func__, ret);
return;
}
/* Successfully accessed the PHY */
phy_data->sfp_phy_avail = 1;
axgbe_printf(3, "Successfully accessed External PHY\n");
}
static bool
xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
{
uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
return (false);
if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
return (false);
if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
return (true);
return (false);
}
static bool
xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
{
uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
return (false);
if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
return (false);
if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
return (true);
return (false);
}
static bool
xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
{
if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
return (false);
if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
return (true);
return (false);
}
static void
xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
uint8_t *sfp_base;
sfp_base = sfp_eeprom->base;
if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) {
axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_ID]);
return;
}
if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) {
axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_EXT_ID]);
return;
}
/* Update transceiver signals (eeprom extd/options) */
phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
/* Assume ACTIVE cable unless told it is PASSIVE */
if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
} else
phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
- /* Determine the type of SFP */
- if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
+ /*
+ * Determine the type of SFP. Certain 10G SFP+ modules read as
+ * 1000BASE-CX. To prevent 10G DAC cables to be recognized as
+ * 1G, we first check if it is a DAC and the bitrate is 10G.
+ */
+ if (((sfp_base[XGBE_SFP_BASE_CV] & XGBE_SFP_BASE_CV_CP) ||
+ (phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE)) &&
+ xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
+ phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
+ else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
- else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
- xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
- phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
switch (phy_data->sfp_base) {
case XGBE_SFP_BASE_1000_T:
phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
break;
case XGBE_SFP_BASE_1000_SX:
case XGBE_SFP_BASE_1000_LX:
case XGBE_SFP_BASE_1000_CX:
phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
break;
case XGBE_SFP_BASE_10000_SR:
case XGBE_SFP_BASE_10000_LR:
case XGBE_SFP_BASE_10000_LRM:
case XGBE_SFP_BASE_10000_ER:
case XGBE_SFP_BASE_10000_CR:
phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
break;
default:
break;
}
axgbe_printf(3, "%s: sfp_base: 0x%x sfp_speed: 0x%x sfp_cable: 0x%x "
"rx_los 0x%x tx_fault 0x%x\n", __func__, phy_data->sfp_base,
phy_data->sfp_speed, phy_data->sfp_cable, phy_data->sfp_rx_los,
phy_data->sfp_tx_fault);
}
static void
xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
struct xgbe_sfp_eeprom *sfp_eeprom)
{
struct xgbe_sfp_ascii sfp_ascii;
char *sfp_data = (char *)&sfp_ascii;
axgbe_printf(3, "SFP detected:\n");
memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
XGBE_SFP_BASE_VENDOR_NAME_LEN);
sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
axgbe_printf(3, " vendor: %s\n",
sfp_data);
memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
XGBE_SFP_BASE_VENDOR_PN_LEN);
sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
axgbe_printf(3, " part number: %s\n",
sfp_data);
memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
XGBE_SFP_BASE_VENDOR_REV_LEN);
sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
axgbe_printf(3, " revision level: %s\n",
sfp_data);
memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
XGBE_SFP_BASE_VENDOR_SN_LEN);
sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
axgbe_printf(3, " serial number: %s\n",
sfp_data);
}
static bool
xgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, unsigned int len)
{
uint8_t cc;
for (cc = 0; len; buf++, len--)
cc += *buf;
return ((cc == cc_in) ? true : false);
}
static void
dump_sfp_eeprom(struct xgbe_prv_data *pdata, uint8_t *sfp_base)
{
axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_ID] : 0x%04x\n",
sfp_base[XGBE_SFP_BASE_ID]);
axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_EXT_ID] : 0x%04x\n",
sfp_base[XGBE_SFP_BASE_EXT_ID]);
axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_CABLE] : 0x%04x\n",
sfp_base[XGBE_SFP_BASE_CABLE]);
}
static int
xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
struct xgbe_sfp_eeprom sfp_eeprom, *eeprom;
uint8_t eeprom_addr, *base;
int ret;
ret = xgbe_phy_sfp_get_mux(pdata);
if (ret) {
axgbe_error("I2C error setting SFP MUX\n");
return (ret);
}
/* Read the SFP serial ID eeprom */
eeprom_addr = 0;
ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
&eeprom_addr, sizeof(eeprom_addr),
&sfp_eeprom, sizeof(sfp_eeprom));
eeprom = &sfp_eeprom;
base = eeprom->base;
dump_sfp_eeprom(pdata, base);
if (ret) {
axgbe_error("I2C error reading SFP EEPROM\n");
goto put;
}
/* Validate the contents read */
if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
sfp_eeprom.base, sizeof(sfp_eeprom.base) - 1)) {
axgbe_error("verify eeprom base failed\n");
ret = -EINVAL;
goto put;
}
if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
sfp_eeprom.extd, sizeof(sfp_eeprom.extd) - 1)) {
axgbe_error("verify eeprom extd failed\n");
ret = -EINVAL;
goto put;
}
/* Check for an added or changed SFP */
if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
phy_data->sfp_changed = 1;
xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
xgbe_phy_free_phy_device(pdata);
} else
phy_data->sfp_changed = 0;
put:
xgbe_phy_sfp_put_mux(pdata);
return (ret);
}
static void
xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
uint8_t gpio_reg, gpio_ports[2];
int ret, prev_sfp_inputs = phy_data->port_sfp_inputs;
int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id);
/* Read the input port registers */
axgbe_printf(3, "%s: befor sfp_mod:%d sfp_gpio_address:0x%x\n",
__func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_address);
gpio_reg = 0;
ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, &gpio_reg,
sizeof(gpio_reg), gpio_ports, sizeof(gpio_ports));
if (ret) {
axgbe_error("%s: I2C error reading SFP GPIO addr:0x%x\n",
__func__, phy_data->sfp_gpio_address);
return;
}
phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
phy_data->port_sfp_inputs = (phy_data->sfp_gpio_inputs >> shift) & 0x0F;
if (prev_sfp_inputs != phy_data->port_sfp_inputs)
axgbe_printf(0, "%s: port_sfp_inputs: 0x%0x\n", __func__,
phy_data->port_sfp_inputs);
phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
axgbe_printf(3, "%s: after sfp_mod:%d sfp_gpio_inputs:0x%x\n",
__func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_inputs);
}
static void
xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
xgbe_phy_free_phy_device(pdata);
phy_data->sfp_mod_absent = 1;
phy_data->sfp_phy_avail = 0;
memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
}
static void
xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
{
phy_data->sfp_rx_los = 0;
phy_data->sfp_tx_fault = 0;
phy_data->sfp_mod_absent = 1;
phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
}
static void
xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
int ret, prev_sfp_state = phy_data->sfp_mod_absent;
/* Reset the SFP signals and info */
xgbe_phy_sfp_reset(phy_data);
ret = xgbe_phy_get_comm_ownership(pdata);
if (ret)
return;
/* Read the SFP signals and check for module presence */
xgbe_phy_sfp_signals(pdata);
if (phy_data->sfp_mod_absent) {
if (prev_sfp_state != phy_data->sfp_mod_absent)
axgbe_error("%s: mod absent\n", __func__);
xgbe_phy_sfp_mod_absent(pdata);
goto put;
}
ret = xgbe_phy_sfp_read_eeprom(pdata);
if (ret) {
/* Treat any error as if there isn't an SFP plugged in */
axgbe_error("%s: eeprom read failed\n", __func__);
xgbe_phy_sfp_reset(phy_data);
xgbe_phy_sfp_mod_absent(pdata);
goto put;
}
xgbe_phy_sfp_parse_eeprom(pdata);
xgbe_phy_sfp_external_phy(pdata);
put:
xgbe_phy_sfp_phy_settings(pdata);
axgbe_printf(3, "%s: phy speed: 0x%x duplex: 0x%x autoneg: 0x%x "
"pause_autoneg: 0x%x\n", __func__, pdata->phy.speed,
pdata->phy.duplex, pdata->phy.autoneg, pdata->phy.pause_autoneg);
xgbe_phy_put_comm_ownership(pdata);
}
static int
xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
uint8_t eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
struct xgbe_sfp_eeprom *sfp_eeprom;
int ret;
if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
ret = -ENXIO;
goto done;
}
if (phy_data->sfp_mod_absent) {
ret = -EIO;
goto done;
}
ret = xgbe_phy_get_comm_ownership(pdata);
if (ret) {
ret = -EIO;
goto done;
}
ret = xgbe_phy_sfp_get_mux(pdata);
if (ret) {
axgbe_error("I2C error setting SFP MUX\n");
ret = -EIO;
goto put_own;
}
/* Read the SFP serial ID eeprom */
eeprom_addr = 0;
ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
&eeprom_addr, sizeof(eeprom_addr),
eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
if (ret) {
axgbe_error("I2C error reading SFP EEPROM\n");
ret = -EIO;
goto put_mux;
}
sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
/* Read the SFP diagnostic eeprom */
eeprom_addr = 0;
ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
&eeprom_addr, sizeof(eeprom_addr),
eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
XGBE_SFP_EEPROM_DIAG_LEN);
if (ret) {
axgbe_error("I2C error reading SFP DIAGS\n");
ret = -EIO;
goto put_mux;
}
}
put_mux:
xgbe_phy_sfp_put_mux(pdata);
put_own:
xgbe_phy_put_comm_ownership(pdata);
done:
return (ret);
}
static int
xgbe_phy_module_info(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
return (-ENXIO);
if (phy_data->sfp_mod_absent)
return (-EIO);
return (0);
}
static void
xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
pdata->phy.tx_pause = 0;
pdata->phy.rx_pause = 0;
if (!phy_data->phydev)
return;
if (pdata->phy.pause)
XGBE_SET_LP_ADV(&pdata->phy, Pause);
if (pdata->phy.asym_pause)
XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__,
pdata->phy.tx_pause, pdata->phy.rx_pause);
}
static enum xgbe_mode
xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
{
enum xgbe_mode mode;
XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
XGBE_SET_LP_ADV(&pdata->phy, TP);
axgbe_printf(1, "%s: pause_autoneg %d\n", __func__,
pdata->phy.pause_autoneg);
/* Use external PHY to determine flow control */
if (pdata->phy.pause_autoneg)
xgbe_phy_phydev_flowctrl(pdata);
switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
case XGBE_SGMII_AN_LINK_SPEED_100:
if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Full);
mode = XGBE_MODE_SGMII_100;
} else {
/* Half-duplex not supported */
XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Half);
mode = XGBE_MODE_UNKNOWN;
}
break;
case XGBE_SGMII_AN_LINK_SPEED_1000:
if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Full);
mode = XGBE_MODE_SGMII_1000;
} else {
/* Half-duplex not supported */
XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Half);
mode = XGBE_MODE_UNKNOWN;
}
break;
default:
mode = XGBE_MODE_UNKNOWN;
}
return (mode);
}
static enum xgbe_mode
xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
{
enum xgbe_mode mode;
unsigned int ad_reg, lp_reg;
XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
XGBE_SET_LP_ADV(&pdata->phy, FIBRE);
/* Compare Advertisement and Link Partner register */
ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
if (lp_reg & 0x100)
XGBE_SET_LP_ADV(&pdata->phy, Pause);
if (lp_reg & 0x80)
XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n",
__func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
if (pdata->phy.pause_autoneg) {
/* Set flow control based on auto-negotiation result */
pdata->phy.tx_pause = 0;
pdata->phy.rx_pause = 0;
if (ad_reg & lp_reg & 0x100) {
pdata->phy.tx_pause = 1;
pdata->phy.rx_pause = 1;
} else if (ad_reg & lp_reg & 0x80) {
if (ad_reg & 0x100)
pdata->phy.rx_pause = 1;
else if (lp_reg & 0x100)
pdata->phy.tx_pause = 1;
}
}
axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
pdata->phy.rx_pause);
if (lp_reg & 0x20)
XGBE_SET_LP_ADV(&pdata->phy, 1000baseX_Full);
/* Half duplex is not supported */
ad_reg &= lp_reg;
mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
return (mode);
}
static enum xgbe_mode
xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
enum xgbe_mode mode;
unsigned int ad_reg, lp_reg;
XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
XGBE_SET_LP_ADV(&pdata->phy, Backplane);
axgbe_printf(1, "%s: pause_autoneg %d\n", __func__,
pdata->phy.pause_autoneg);
/* Use external PHY to determine flow control */
if (pdata->phy.pause_autoneg)
xgbe_phy_phydev_flowctrl(pdata);
/* Compare Advertisement and Link Partner register 2 */
ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
if (lp_reg & 0x80)
XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
if (lp_reg & 0x20)
XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
ad_reg &= lp_reg;
if (ad_reg & 0x80) {
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_BACKPLANE:
mode = XGBE_MODE_KR;
break;
default:
mode = XGBE_MODE_SFI;
break;
}
} else if (ad_reg & 0x20) {
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_BACKPLANE:
mode = XGBE_MODE_KX_1000;
break;
case XGBE_PORT_MODE_1000BASE_X:
mode = XGBE_MODE_X;
break;
case XGBE_PORT_MODE_SFP:
switch (phy_data->sfp_base) {
case XGBE_SFP_BASE_1000_T:
if ((phy_data->phydev) &&
(pdata->phy.speed == SPEED_100))
mode = XGBE_MODE_SGMII_100;
else
mode = XGBE_MODE_SGMII_1000;
break;
case XGBE_SFP_BASE_1000_SX:
case XGBE_SFP_BASE_1000_LX:
case XGBE_SFP_BASE_1000_CX:
default:
mode = XGBE_MODE_X;
break;
}
break;
default:
if ((phy_data->phydev) &&
(pdata->phy.speed == SPEED_100))
mode = XGBE_MODE_SGMII_100;
else
mode = XGBE_MODE_SGMII_1000;
break;
}
} else {
mode = XGBE_MODE_UNKNOWN;
}
/* Compare Advertisement and Link Partner register 3 */
ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
if (lp_reg & 0xc000)
XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
return (mode);
}
static enum xgbe_mode
xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
{
enum xgbe_mode mode;
unsigned int ad_reg, lp_reg;
XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
XGBE_SET_LP_ADV(&pdata->phy, Backplane);
/* Compare Advertisement and Link Partner register 1 */
ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
if (lp_reg & 0x400)
XGBE_SET_LP_ADV(&pdata->phy, Pause);
if (lp_reg & 0x800)
XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n",
__func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
if (pdata->phy.pause_autoneg) {
/* Set flow control based on auto-negotiation result */
pdata->phy.tx_pause = 0;
pdata->phy.rx_pause = 0;
if (ad_reg & lp_reg & 0x400) {
pdata->phy.tx_pause = 1;
pdata->phy.rx_pause = 1;
} else if (ad_reg & lp_reg & 0x800) {
if (ad_reg & 0x400)
pdata->phy.rx_pause = 1;
else if (lp_reg & 0x400)
pdata->phy.tx_pause = 1;
}
}
axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
pdata->phy.rx_pause);
/* Compare Advertisement and Link Partner register 2 */
ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
if (lp_reg & 0x80)
XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
if (lp_reg & 0x20)
XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
ad_reg &= lp_reg;
if (ad_reg & 0x80)
mode = XGBE_MODE_KR;
else if (ad_reg & 0x20)
mode = XGBE_MODE_KX_1000;
else
mode = XGBE_MODE_UNKNOWN;
/* Compare Advertisement and Link Partner register 3 */
ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
if (lp_reg & 0xc000)
XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
return (mode);
}
static enum xgbe_mode
xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
{
switch (pdata->an_mode) {
case XGBE_AN_MODE_CL73:
return (xgbe_phy_an73_outcome(pdata));
case XGBE_AN_MODE_CL73_REDRV:
return (xgbe_phy_an73_redrv_outcome(pdata));
case XGBE_AN_MODE_CL37:
return (xgbe_phy_an37_outcome(pdata));
case XGBE_AN_MODE_CL37_SGMII:
return (xgbe_phy_an37_sgmii_outcome(pdata));
default:
return (XGBE_MODE_UNKNOWN);
}
}
static void
xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, struct xgbe_phy *dphy)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);
/* Without a re-driver, just return current advertising */
if (!phy_data->redrv)
return;
/* With the KR re-driver we need to advertise a single speed */
XGBE_CLR_ADV(dphy, 1000baseKX_Full);
XGBE_CLR_ADV(dphy, 10000baseKR_Full);
/* Advertise FEC support is present */
if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
XGBE_SET_ADV(dphy, 10000baseR_FEC);
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_BACKPLANE:
XGBE_SET_ADV(dphy, 10000baseKR_Full);
break;
case XGBE_PORT_MODE_BACKPLANE_2500:
XGBE_SET_ADV(dphy, 1000baseKX_Full);
break;
case XGBE_PORT_MODE_1000BASE_T:
case XGBE_PORT_MODE_1000BASE_X:
case XGBE_PORT_MODE_NBASE_T:
XGBE_SET_ADV(dphy, 1000baseKX_Full);
break;
case XGBE_PORT_MODE_10GBASE_T:
if ((phy_data->phydev) &&
(pdata->phy.speed == SPEED_10000))
XGBE_SET_ADV(dphy, 10000baseKR_Full);
else
XGBE_SET_ADV(dphy, 1000baseKX_Full);
break;
case XGBE_PORT_MODE_10GBASE_R:
XGBE_SET_ADV(dphy, 10000baseKR_Full);
break;
case XGBE_PORT_MODE_SFP:
switch (phy_data->sfp_base) {
case XGBE_SFP_BASE_1000_T:
case XGBE_SFP_BASE_1000_SX:
case XGBE_SFP_BASE_1000_LX:
case XGBE_SFP_BASE_1000_CX:
XGBE_SET_ADV(dphy, 1000baseKX_Full);
break;
default:
XGBE_SET_ADV(dphy, 10000baseKR_Full);
break;
}
break;
default:
XGBE_SET_ADV(dphy, 10000baseKR_Full);
break;
}
}
static int
xgbe_phy_an_config(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
int ret;
ret = xgbe_phy_find_phy_device(pdata);
if (ret)
return (ret);
axgbe_printf(2, "%s: find_phy_device return %s.\n", __func__,
ret ? "Failure" : "Success");
if (!phy_data->phydev)
return (0);
ret = xgbe_phy_start_aneg(pdata);
return (ret);
}
static enum xgbe_an_mode
xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
{
switch (phy_data->sfp_base) {
case XGBE_SFP_BASE_1000_T:
return (XGBE_AN_MODE_CL37_SGMII);
case XGBE_SFP_BASE_1000_SX:
case XGBE_SFP_BASE_1000_LX:
case XGBE_SFP_BASE_1000_CX:
return (XGBE_AN_MODE_CL37);
default:
return (XGBE_AN_MODE_NONE);
}
}
static enum xgbe_an_mode
xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
/* A KR re-driver will always require CL73 AN */
if (phy_data->redrv)
return (XGBE_AN_MODE_CL73_REDRV);
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_BACKPLANE:
return (XGBE_AN_MODE_CL73);
case XGBE_PORT_MODE_BACKPLANE_2500:
return (XGBE_AN_MODE_NONE);
case XGBE_PORT_MODE_1000BASE_T:
return (XGBE_AN_MODE_CL37_SGMII);
case XGBE_PORT_MODE_1000BASE_X:
return (XGBE_AN_MODE_CL37);
case XGBE_PORT_MODE_NBASE_T:
return (XGBE_AN_MODE_CL37_SGMII);
case XGBE_PORT_MODE_10GBASE_T:
return (XGBE_AN_MODE_CL73);
case XGBE_PORT_MODE_10GBASE_R:
return (XGBE_AN_MODE_NONE);
case XGBE_PORT_MODE_SFP:
return (xgbe_phy_an_sfp_mode(phy_data));
default:
return (XGBE_AN_MODE_NONE);
}
}
static int
xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
enum xgbe_phy_redrv_mode mode)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
uint16_t redrv_reg, redrv_val;
redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
redrv_val = (uint16_t)mode;
return (pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
redrv_reg, redrv_val));
}
static int
xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
enum xgbe_phy_redrv_mode mode)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
unsigned int redrv_reg;
int ret;
/* Calculate the register to write */
redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
return (ret);
}
static void
xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
enum xgbe_phy_redrv_mode mode;
int ret;
if (!phy_data->redrv)
return;
mode = XGBE_PHY_REDRV_MODE_CX;
if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
(phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
(phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
mode = XGBE_PHY_REDRV_MODE_SR;
ret = xgbe_phy_get_comm_ownership(pdata);
if (ret)
return;
axgbe_printf(2, "%s: redrv_if set: %d\n", __func__, phy_data->redrv_if);
if (phy_data->redrv_if)
xgbe_phy_set_redrv_mode_i2c(pdata, mode);
else
xgbe_phy_set_redrv_mode_mdio(pdata, mode);
xgbe_phy_put_comm_ownership(pdata);
}
static void
xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, unsigned int cmd,
unsigned int sub_cmd)
{
unsigned int s0 = 0;
unsigned int wait;
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
axgbe_error("firmware mailbox not ready for command\n");
/* Construct the command */
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
/* Issue the command */
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
/* Wait for command to complete */
wait = XGBE_RATECHANGE_COUNT;
while (wait--) {
if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
axgbe_printf(3, "%s: Rate change done\n", __func__);
return;
}
DELAY(2000);
}
axgbe_printf(3, "firmware mailbox command did not complete\n");
}
static void
xgbe_phy_rrc(struct xgbe_prv_data *pdata)
{
/* Receiver Reset Cycle */
xgbe_phy_perform_ratechange(pdata, 5, 0);
axgbe_printf(3, "receiver reset complete\n");
}
static void
xgbe_phy_power_off(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
/* Power off */
xgbe_phy_perform_ratechange(pdata, 0, 0);
phy_data->cur_mode = XGBE_MODE_UNKNOWN;
axgbe_printf(3, "phy powered off\n");
}
static void
xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
xgbe_phy_set_redrv_mode(pdata);
/* 10G/SFI */
axgbe_printf(3, "%s: cable %d len %d\n", __func__, phy_data->sfp_cable,
phy_data->sfp_cable_len);
if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE)
xgbe_phy_perform_ratechange(pdata, 3, 0);
else {
if (phy_data->sfp_cable_len <= 1)
xgbe_phy_perform_ratechange(pdata, 3, 1);
else if (phy_data->sfp_cable_len <= 3)
xgbe_phy_perform_ratechange(pdata, 3, 2);
else
xgbe_phy_perform_ratechange(pdata, 3, 3);
}
phy_data->cur_mode = XGBE_MODE_SFI;
axgbe_printf(3, "10GbE SFI mode set\n");
}
static void
xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
xgbe_phy_set_redrv_mode(pdata);
/* 1G/X */
xgbe_phy_perform_ratechange(pdata, 1, 3);
phy_data->cur_mode = XGBE_MODE_X;
axgbe_printf(3, "1GbE X mode set\n");
}
static void
xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
xgbe_phy_set_redrv_mode(pdata);
/* 1G/SGMII */
xgbe_phy_perform_ratechange(pdata, 1, 2);
phy_data->cur_mode = XGBE_MODE_SGMII_1000;
axgbe_printf(2, "1GbE SGMII mode set\n");
}
static void
xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
xgbe_phy_set_redrv_mode(pdata);
/* 100M/SGMII */
xgbe_phy_perform_ratechange(pdata, 1, 1);
phy_data->cur_mode = XGBE_MODE_SGMII_100;
axgbe_printf(3, "100MbE SGMII mode set\n");
}
static void
xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
xgbe_phy_set_redrv_mode(pdata);
/* 10G/KR */
xgbe_phy_perform_ratechange(pdata, 4, 0);
phy_data->cur_mode = XGBE_MODE_KR;
axgbe_printf(3, "10GbE KR mode set\n");
}
static void
xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
xgbe_phy_set_redrv_mode(pdata);
/* 2.5G/KX */
xgbe_phy_perform_ratechange(pdata, 2, 0);
phy_data->cur_mode = XGBE_MODE_KX_2500;
axgbe_printf(3, "2.5GbE KX mode set\n");
}
static void
xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
xgbe_phy_set_redrv_mode(pdata);
/* 1G/KX */
xgbe_phy_perform_ratechange(pdata, 1, 3);
phy_data->cur_mode = XGBE_MODE_KX_1000;
axgbe_printf(3, "1GbE KX mode set\n");
}
static enum xgbe_mode
xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
return (phy_data->cur_mode);
}
static enum xgbe_mode
xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
/* No switching if not 10GBase-T */
if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
return (xgbe_phy_cur_mode(pdata));
switch (xgbe_phy_cur_mode(pdata)) {
case XGBE_MODE_SGMII_100:
case XGBE_MODE_SGMII_1000:
return (XGBE_MODE_KR);
case XGBE_MODE_KR:
default:
return (XGBE_MODE_SGMII_1000);
}
}
static enum xgbe_mode
xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
{
return (XGBE_MODE_KX_2500);
}
static enum xgbe_mode
xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
{
/* If we are in KR switch to KX, and vice-versa */
switch (xgbe_phy_cur_mode(pdata)) {
case XGBE_MODE_KX_1000:
return (XGBE_MODE_KR);
case XGBE_MODE_KR:
default:
return (XGBE_MODE_KX_1000);
}
}
static enum xgbe_mode
xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_BACKPLANE:
return (xgbe_phy_switch_bp_mode(pdata));
case XGBE_PORT_MODE_BACKPLANE_2500:
return (xgbe_phy_switch_bp_2500_mode(pdata));
case XGBE_PORT_MODE_1000BASE_T:
case XGBE_PORT_MODE_NBASE_T:
case XGBE_PORT_MODE_10GBASE_T:
return (xgbe_phy_switch_baset_mode(pdata));
case XGBE_PORT_MODE_1000BASE_X:
case XGBE_PORT_MODE_10GBASE_R:
case XGBE_PORT_MODE_SFP:
/* No switching, so just return current mode */
return (xgbe_phy_cur_mode(pdata));
default:
return (XGBE_MODE_UNKNOWN);
}
}
static enum xgbe_mode
xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, int speed)
{
switch (speed) {
case SPEED_1000:
return (XGBE_MODE_X);
case SPEED_10000:
return (XGBE_MODE_KR);
default:
return (XGBE_MODE_UNKNOWN);
}
}
static enum xgbe_mode
xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, int speed)
{
switch (speed) {
case SPEED_100:
return (XGBE_MODE_SGMII_100);
case SPEED_1000:
return (XGBE_MODE_SGMII_1000);
case SPEED_2500:
return (XGBE_MODE_KX_2500);
case SPEED_10000:
return (XGBE_MODE_KR);
default:
return (XGBE_MODE_UNKNOWN);
}
}
static enum xgbe_mode
xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, int speed)
{
switch (speed) {
case SPEED_100:
return (XGBE_MODE_SGMII_100);
case SPEED_1000:
if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
return (XGBE_MODE_SGMII_1000);
else
return (XGBE_MODE_X);
case SPEED_10000:
case SPEED_UNKNOWN:
return (XGBE_MODE_SFI);
default:
return (XGBE_MODE_UNKNOWN);
}
}
static enum xgbe_mode
xgbe_phy_get_bp_2500_mode(int speed)
{
switch (speed) {
case SPEED_2500:
return (XGBE_MODE_KX_2500);
default:
return (XGBE_MODE_UNKNOWN);
}
}
static enum xgbe_mode
xgbe_phy_get_bp_mode(int speed)
{
switch (speed) {
case SPEED_1000:
return (XGBE_MODE_KX_1000);
case SPEED_10000:
return (XGBE_MODE_KR);
default:
return (XGBE_MODE_UNKNOWN);
}
}
static enum xgbe_mode
xgbe_phy_get_mode(struct xgbe_prv_data *pdata, int speed)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_BACKPLANE:
return (xgbe_phy_get_bp_mode(speed));
case XGBE_PORT_MODE_BACKPLANE_2500:
return (xgbe_phy_get_bp_2500_mode(speed));
case XGBE_PORT_MODE_1000BASE_T:
case XGBE_PORT_MODE_NBASE_T:
case XGBE_PORT_MODE_10GBASE_T:
return (xgbe_phy_get_baset_mode(phy_data, speed));
case XGBE_PORT_MODE_1000BASE_X:
case XGBE_PORT_MODE_10GBASE_R:
return (xgbe_phy_get_basex_mode(phy_data, speed));
case XGBE_PORT_MODE_SFP:
return (xgbe_phy_get_sfp_mode(phy_data, speed));
default:
return (XGBE_MODE_UNKNOWN);
}
}
static void
xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
{
switch (mode) {
case XGBE_MODE_KX_1000:
xgbe_phy_kx_1000_mode(pdata);
break;
case XGBE_MODE_KX_2500:
xgbe_phy_kx_2500_mode(pdata);
break;
case XGBE_MODE_KR:
xgbe_phy_kr_mode(pdata);
break;
case XGBE_MODE_SGMII_100:
xgbe_phy_sgmii_100_mode(pdata);
break;
case XGBE_MODE_SGMII_1000:
xgbe_phy_sgmii_1000_mode(pdata);
break;
case XGBE_MODE_X:
xgbe_phy_x_mode(pdata);
break;
case XGBE_MODE_SFI:
xgbe_phy_sfi_mode(pdata);
break;
default:
break;
}
}
static void
xgbe_phy_get_type(struct xgbe_prv_data *pdata, struct ifmediareq * ifmr)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
switch (pdata->phy.speed) {
case SPEED_10000:
if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
ifmr->ifm_active |= IFM_10G_KR;
else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T)
ifmr->ifm_active |= IFM_10G_T;
else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R)
ifmr->ifm_active |= IFM_10G_KR;
else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
ifmr->ifm_active |= IFM_10G_SFI;
else
ifmr->ifm_active |= IFM_OTHER;
break;
case SPEED_2500:
if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE_2500)
ifmr->ifm_active |= IFM_2500_KX;
else
ifmr->ifm_active |= IFM_OTHER;
break;
case SPEED_1000:
if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
ifmr->ifm_active |= IFM_1000_KX;
else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_T)
ifmr->ifm_active |= IFM_1000_T;
#if 0
else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X)
ifmr->ifm_active |= IFM_1000_SX;
ifmr->ifm_active |= IFM_1000_LX;
ifmr->ifm_active |= IFM_1000_CX;
#endif
else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
ifmr->ifm_active |= IFM_1000_SGMII;
else
ifmr->ifm_active |= IFM_OTHER;
break;
case SPEED_100:
if(phy_data->port_mode == XGBE_PORT_MODE_NBASE_T)
ifmr->ifm_active |= IFM_100_T;
else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
ifmr->ifm_active |= IFM_1000_SGMII;
else
ifmr->ifm_active |= IFM_OTHER;
break;
default:
ifmr->ifm_active |= IFM_OTHER;
axgbe_printf(1, "Unknown mode detected\n");
break;
}
}
static bool
xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode,
bool advert)
{
if (pdata->phy.autoneg == AUTONEG_ENABLE)
return (advert);
else {
enum xgbe_mode cur_mode;
cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
if (cur_mode == mode)
return (true);
}
return (false);
}
static bool
xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
{
switch (mode) {
case XGBE_MODE_X:
return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
1000baseX_Full)));
case XGBE_MODE_KR:
return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
10000baseKR_Full)));
default:
return (false);
}
}
static bool
xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
{
axgbe_printf(3, "%s: check mode %d\n", __func__, mode);
switch (mode) {
case XGBE_MODE_SGMII_100:
return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
100baseT_Full)));
case XGBE_MODE_SGMII_1000:
return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
1000baseT_Full)));
case XGBE_MODE_KX_2500:
return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2500baseT_Full)));
case XGBE_MODE_KR:
return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
10000baseT_Full)));
default:
return (false);
}
}
static bool
xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
switch (mode) {
case XGBE_MODE_X:
if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
return (false);
return (xgbe_phy_check_mode(pdata, mode,
XGBE_ADV(&pdata->phy, 1000baseX_Full)));
case XGBE_MODE_SGMII_100:
if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
return (false);
return (xgbe_phy_check_mode(pdata, mode,
XGBE_ADV(&pdata->phy, 100baseT_Full)));
case XGBE_MODE_SGMII_1000:
if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
return (false);
return (xgbe_phy_check_mode(pdata, mode,
XGBE_ADV(&pdata->phy, 1000baseT_Full)));
case XGBE_MODE_SFI:
if (phy_data->sfp_mod_absent)
return (true);
return (xgbe_phy_check_mode(pdata, mode,
XGBE_ADV(&pdata->phy, 10000baseSR_Full) ||
XGBE_ADV(&pdata->phy, 10000baseLR_Full) ||
XGBE_ADV(&pdata->phy, 10000baseLRM_Full) ||
XGBE_ADV(&pdata->phy, 10000baseER_Full) ||
XGBE_ADV(&pdata->phy, 10000baseCR_Full)));
default:
return (false);
}
}
static bool
xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
{
switch (mode) {
case XGBE_MODE_KX_2500:
return (xgbe_phy_check_mode(pdata, mode,
XGBE_ADV(&pdata->phy, 2500baseX_Full)));
default:
return (false);
}
}
static bool
xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
{
switch (mode) {
case XGBE_MODE_KX_1000:
return (xgbe_phy_check_mode(pdata, mode,
XGBE_ADV(&pdata->phy, 1000baseKX_Full)));
case XGBE_MODE_KR:
return (xgbe_phy_check_mode(pdata, mode,
XGBE_ADV(&pdata->phy, 10000baseKR_Full)));
default:
return (false);
}
}
static bool
xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_BACKPLANE:
return (xgbe_phy_use_bp_mode(pdata, mode));
case XGBE_PORT_MODE_BACKPLANE_2500:
return (xgbe_phy_use_bp_2500_mode(pdata, mode));
case XGBE_PORT_MODE_1000BASE_T:
axgbe_printf(3, "use_mode %s\n",
xgbe_phy_use_baset_mode(pdata, mode) ? "found" : "Not found");
case XGBE_PORT_MODE_NBASE_T:
case XGBE_PORT_MODE_10GBASE_T:
return (xgbe_phy_use_baset_mode(pdata, mode));
case XGBE_PORT_MODE_1000BASE_X:
case XGBE_PORT_MODE_10GBASE_R:
return (xgbe_phy_use_basex_mode(pdata, mode));
case XGBE_PORT_MODE_SFP:
return (xgbe_phy_use_sfp_mode(pdata, mode));
default:
return (false);
}
}
static bool
xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, int speed)
{
switch (speed) {
case SPEED_1000:
return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
case SPEED_10000:
return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
default:
return (false);
}
}
static bool
xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, int speed)
{
switch (speed) {
case SPEED_100:
case SPEED_1000:
return (true);
case SPEED_2500:
return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
case SPEED_10000:
return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
default:
return (false);
}
}
static bool
xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, int speed)
{
switch (speed) {
case SPEED_100:
return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
case SPEED_1000:
return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
(phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
case SPEED_10000:
return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
default:
return (false);
}
}
static bool
xgbe_phy_valid_speed_bp_2500_mode(int speed)
{
switch (speed) {
case SPEED_2500:
return (true);
default:
return (false);
}
}
static bool
xgbe_phy_valid_speed_bp_mode(int speed)
{
switch (speed) {
case SPEED_1000:
case SPEED_10000:
return (true);
default:
return (false);
}
}
static bool
xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_BACKPLANE:
return (xgbe_phy_valid_speed_bp_mode(speed));
case XGBE_PORT_MODE_BACKPLANE_2500:
return (xgbe_phy_valid_speed_bp_2500_mode(speed));
case XGBE_PORT_MODE_1000BASE_T:
case XGBE_PORT_MODE_NBASE_T:
case XGBE_PORT_MODE_10GBASE_T:
return (xgbe_phy_valid_speed_baset_mode(phy_data, speed));
case XGBE_PORT_MODE_1000BASE_X:
case XGBE_PORT_MODE_10GBASE_R:
return (xgbe_phy_valid_speed_basex_mode(phy_data, speed));
case XGBE_PORT_MODE_SFP:
return (xgbe_phy_valid_speed_sfp_mode(phy_data, speed));
default:
return (false);
}
}
static int
xgbe_upd_link(struct xgbe_prv_data *pdata)
{
int reg;
axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link);
reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
if (reg < 0)
return (reg);
if ((reg & BMSR_LINK) == 0)
pdata->phy.link = 0;
else
pdata->phy.link = 1;
axgbe_printf(2, "Link: %d updated reg %#x\n", pdata->phy.link, reg);
return (0);
}
static int
xgbe_phy_read_status(struct xgbe_prv_data *pdata)
{
int common_adv_gb = 0;
int common_adv;
int lpagb = 0;
int adv, lpa;
int ret;
ret = xgbe_upd_link(pdata);
if (ret) {
axgbe_printf(2, "Link Update return %d\n", ret);
return (ret);
}
if (AUTONEG_ENABLE == pdata->phy.autoneg) {
if (pdata->phy.supported == SUPPORTED_1000baseT_Half ||
pdata->phy.supported == SUPPORTED_1000baseT_Full) {
lpagb = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
MII_100T2SR);
if (lpagb < 0)
return (lpagb);
adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
MII_100T2CR);
if (adv < 0)
return (adv);
if (lpagb & GTSR_MAN_MS_FLT) {
if (adv & GTCR_MAN_MS)
axgbe_printf(2, "Master/Slave Resolution "
"failed, maybe conflicting manual settings\n");
else
axgbe_printf(2, "Master/Slave Resolution failed\n");
return (-ENOLINK);
}
if (pdata->phy.supported == SUPPORTED_1000baseT_Half)
XGBE_SET_ADV(&pdata->phy, 1000baseT_Half);
else if (pdata->phy.supported == SUPPORTED_1000baseT_Full)
XGBE_SET_ADV(&pdata->phy, 1000baseT_Full);
common_adv_gb = lpagb & adv << 2;
}
lpa = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANLPAR);
if (lpa < 0)
return (lpa);
if (pdata->phy.supported == SUPPORTED_Autoneg)
XGBE_SET_ADV(&pdata->phy, Autoneg);
adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANAR);
if (adv < 0)
return (adv);
common_adv = lpa & adv;
pdata->phy.speed = SPEED_10;
pdata->phy.duplex = DUPLEX_HALF;
pdata->phy.pause = 0;
pdata->phy.asym_pause = 0;
axgbe_printf(2, "%s: lpa %#x adv %#x common_adv_gb %#x "
"common_adv %#x\n", __func__, lpa, adv, common_adv_gb,
common_adv);
if (common_adv_gb & (GTSR_LP_1000TFDX | GTSR_LP_1000THDX)) {
axgbe_printf(2, "%s: SPEED 1000\n", __func__);
pdata->phy.speed = SPEED_1000;
if (common_adv_gb & GTSR_LP_1000TFDX)
pdata->phy.duplex = DUPLEX_FULL;
} else if (common_adv & (ANLPAR_TX_FD | ANLPAR_TX)) {
axgbe_printf(2, "%s: SPEED 100\n", __func__);
pdata->phy.speed = SPEED_100;
if (common_adv & ANLPAR_TX_FD)
pdata->phy.duplex = DUPLEX_FULL;
} else
if (common_adv & ANLPAR_10_FD)
pdata->phy.duplex = DUPLEX_FULL;
if (pdata->phy.duplex == DUPLEX_FULL) {
pdata->phy.pause = lpa & ANLPAR_FC ? 1 : 0;
pdata->phy.asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
}
} else {
int bmcr = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
if (bmcr < 0)
return (bmcr);
if (bmcr & BMCR_FDX)
pdata->phy.duplex = DUPLEX_FULL;
else
pdata->phy.duplex = DUPLEX_HALF;
if (bmcr & BMCR_SPEED1)
pdata->phy.speed = SPEED_1000;
else if (bmcr & BMCR_SPEED100)
pdata->phy.speed = SPEED_100;
else
pdata->phy.speed = SPEED_10;
pdata->phy.pause = 0;
pdata->phy.asym_pause = 0;
axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x "
"autoneg %#x\n", __func__, pdata->phy.speed,
pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
}
return (0);
}
static int
xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
struct mii_data *mii = NULL;
unsigned int reg;
int ret;
*an_restart = 0;
if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
/* Check SFP signals */
axgbe_printf(3, "%s: calling phy detect\n", __func__);
xgbe_phy_sfp_detect(pdata);
if (phy_data->sfp_changed) {
axgbe_printf(1, "%s: SFP changed observed\n", __func__);
*an_restart = 1;
return (0);
}
if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {
axgbe_printf(1, "%s: SFP absent 0x%x & sfp_rx_los 0x%x\n",
__func__, phy_data->sfp_mod_absent,
phy_data->sfp_rx_los);
return (0);
}
} else {
mii = device_get_softc(pdata->axgbe_miibus);
mii_tick(mii);
ret = xgbe_phy_read_status(pdata);
if (ret) {
axgbe_printf(2, "Link: Read status returned %d\n", ret);
return (ret);
}
axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x "
"autoneg %#x\n", __func__, pdata->phy.speed,
pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
ret = (ret < 0) ? ret : (ret & BMSR_ACOMP);
axgbe_printf(2, "Link: BMCR returned %d\n", ret);
if ((pdata->phy.autoneg == AUTONEG_ENABLE) && !ret)
return (0);
return (pdata->phy.link);
}
/* Link status is latched low, so read once to clear
* and then read again to get current state
*/
reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
axgbe_printf(1, "%s: link_status reg: 0x%x\n", __func__, reg);
if (reg & MDIO_STAT1_LSTATUS)
return (1);
/* No link, attempt a receiver reset cycle */
if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
axgbe_printf(1, "ENTERED RRC: rrc_count: %d\n",
phy_data->rrc_count);
phy_data->rrc_count = 0;
- xgbe_phy_rrc(pdata);
+ if (pdata->link_workaround) {
+ ret = xgbe_phy_reset(pdata);
+ if (ret)
+ axgbe_error("Error resetting phy\n");
+ } else
+ xgbe_phy_rrc(pdata);
}
return (0);
}
static void
xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR);
phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
GPIO_MASK);
phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
GPIO_RX_LOS);
phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
GPIO_TX_FAULT);
phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
GPIO_MOD_ABS);
phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
GPIO_RATE_SELECT);
DBGPR("SFP: gpio_address=%#x\n", phy_data->sfp_gpio_address);
DBGPR("SFP: gpio_mask=%#x\n", phy_data->sfp_gpio_mask);
DBGPR("SFP: gpio_rx_los=%u\n", phy_data->sfp_gpio_rx_los);
DBGPR("SFP: gpio_tx_fault=%u\n", phy_data->sfp_gpio_tx_fault);
DBGPR("SFP: gpio_mod_absent=%u\n",
phy_data->sfp_gpio_mod_absent);
DBGPR("SFP: gpio_rate_select=%u\n",
phy_data->sfp_gpio_rate_select);
}
static void
xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
unsigned int mux_addr_hi, mux_addr_lo;
mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
if (mux_addr_lo == XGBE_SFP_DIRECT)
return;
phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
MUX_CHAN);
DBGPR("SFP: mux_address=%#x\n", phy_data->sfp_mux_address);
DBGPR("SFP: mux_channel=%u\n", phy_data->sfp_mux_channel);
}
static void
xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
{
xgbe_phy_sfp_comm_setup(pdata);
xgbe_phy_sfp_gpio_setup(pdata);
}
static int
xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
unsigned int ret;
ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
if (ret)
return (ret);
ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
return (ret);
}
static int
xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
uint8_t gpio_reg, gpio_ports[2], gpio_data[3];
int ret;
/* Read the output port registers */
gpio_reg = 2;
ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
&gpio_reg, sizeof(gpio_reg),
gpio_ports, sizeof(gpio_ports));
if (ret)
return (ret);
/* Prepare to write the GPIO data */
gpio_data[0] = 2;
gpio_data[1] = gpio_ports[0];
gpio_data[2] = gpio_ports[1];
/* Set the GPIO pin */
if (phy_data->mdio_reset_gpio < 8)
gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
else
gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
/* Write the output port registers */
ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
gpio_data, sizeof(gpio_data));
if (ret)
return (ret);
/* Clear the GPIO pin */
if (phy_data->mdio_reset_gpio < 8)
gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
else
gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
/* Write the output port registers */
ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
gpio_data, sizeof(gpio_data));
return (ret);
}
static int
xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
int ret;
if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
return (0);
ret = xgbe_phy_get_comm_ownership(pdata);
if (ret)
return (ret);
if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
ret = xgbe_phy_i2c_mdio_reset(pdata);
else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
ret = xgbe_phy_int_mdio_reset(pdata);
xgbe_phy_put_comm_ownership(pdata);
return (ret);
}
static bool
xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
{
if (!phy_data->redrv)
return (false);
if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
return (true);
switch (phy_data->redrv_model) {
case XGBE_PHY_REDRV_MODEL_4223:
if (phy_data->redrv_lane > 3)
return (true);
break;
case XGBE_PHY_REDRV_MODEL_4227:
if (phy_data->redrv_lane > 1)
return (true);
break;
default:
return (true);
}
return (false);
}
static int
xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
return (0);
phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
switch (phy_data->mdio_reset) {
case XGBE_MDIO_RESET_NONE:
case XGBE_MDIO_RESET_I2C_GPIO:
case XGBE_MDIO_RESET_INT_GPIO:
break;
default:
axgbe_error("unsupported MDIO reset (%#x)\n",
phy_data->mdio_reset);
return (-EINVAL);
}
if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET_I2C_ADDR);
phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
MDIO_RESET_I2C_GPIO);
} else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
MDIO_RESET_INT_GPIO);
return (0);
}
static bool
xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_BACKPLANE:
if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
return (false);
break;
case XGBE_PORT_MODE_BACKPLANE_2500:
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
return (false);
break;
case XGBE_PORT_MODE_1000BASE_T:
if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
return (false);
break;
case XGBE_PORT_MODE_1000BASE_X:
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
return (false);
break;
case XGBE_PORT_MODE_NBASE_T:
if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
return (false);
break;
case XGBE_PORT_MODE_10GBASE_T:
if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
return (false);
break;
case XGBE_PORT_MODE_10GBASE_R:
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
return (false);
break;
case XGBE_PORT_MODE_SFP:
if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
return (false);
break;
default:
break;
}
return (true);
}
static bool
xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_BACKPLANE:
case XGBE_PORT_MODE_BACKPLANE_2500:
if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
return (false);
break;
case XGBE_PORT_MODE_1000BASE_T:
case XGBE_PORT_MODE_1000BASE_X:
case XGBE_PORT_MODE_NBASE_T:
case XGBE_PORT_MODE_10GBASE_T:
case XGBE_PORT_MODE_10GBASE_R:
if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
return (false);
break;
case XGBE_PORT_MODE_SFP:
if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
return (false);
break;
default:
break;
}
return (true);
}
static bool
xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
{
if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
return (false);
if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
return (false);
return (true);
}
static void
xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n",
__func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
if (!pdata->sysctl_an_cdr_workaround)
return;
if (!phy_data->phy_cdr_notrack)
return;
DELAY(phy_data->phy_cdr_delay + 500);
XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_ON);
phy_data->phy_cdr_notrack = 0;
axgbe_printf(2, "CDR TRACK DONE\n");
}
static void
xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n",
__func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
if (!pdata->sysctl_an_cdr_workaround)
return;
if (phy_data->phy_cdr_notrack)
return;
XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_OFF);
xgbe_phy_rrc(pdata);
phy_data->phy_cdr_notrack = 1;
}
static void
xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
{
if (!pdata->sysctl_an_cdr_track_early)
xgbe_phy_cdr_track(pdata);
}
static void
xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
{
if (pdata->sysctl_an_cdr_track_early)
xgbe_phy_cdr_track(pdata);
}
static void
xgbe_phy_an_post(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
switch (pdata->an_mode) {
case XGBE_AN_MODE_CL73:
case XGBE_AN_MODE_CL73_REDRV:
if (phy_data->cur_mode != XGBE_MODE_KR)
break;
xgbe_phy_cdr_track(pdata);
switch (pdata->an_result) {
case XGBE_AN_READY:
case XGBE_AN_COMPLETE:
break;
default:
if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
else
phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
break;
}
break;
default:
break;
}
}
static void
xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
switch (pdata->an_mode) {
case XGBE_AN_MODE_CL73:
case XGBE_AN_MODE_CL73_REDRV:
if (phy_data->cur_mode != XGBE_MODE_KR)
break;
xgbe_phy_cdr_notrack(pdata);
break;
default:
break;
}
}
static void
xgbe_phy_stop(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
/* If we have an external PHY, free it */
xgbe_phy_free_phy_device(pdata);
/* Reset SFP data */
xgbe_phy_sfp_reset(phy_data);
xgbe_phy_sfp_mod_absent(pdata);
/* Reset CDR support */
xgbe_phy_cdr_track(pdata);
/* Power off the PHY */
xgbe_phy_power_off(pdata);
/* Stop the I2C controller */
pdata->i2c_if.i2c_stop(pdata);
}
static int
xgbe_phy_start(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
int ret;
axgbe_printf(2, "%s: redrv %d redrv_if %d start_mode %d\n", __func__,
phy_data->redrv, phy_data->redrv_if, phy_data->start_mode);
/* Start the I2C controller */
ret = pdata->i2c_if.i2c_start(pdata);
if (ret) {
axgbe_error("%s: impl i2c start ret %d\n", __func__, ret);
return (ret);
}
/* Set the proper MDIO mode for the re-driver */
if (phy_data->redrv && !phy_data->redrv_if) {
ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
XGBE_MDIO_MODE_CL22);
if (ret) {
axgbe_error("redriver mdio port not compatible (%u)\n",
phy_data->redrv_addr);
return (ret);
}
}
/* Start in highest supported mode */
xgbe_phy_set_mode(pdata, phy_data->start_mode);
/* Reset CDR support */
xgbe_phy_cdr_track(pdata);
/* After starting the I2C controller, we can check for an SFP */
switch (phy_data->port_mode) {
case XGBE_PORT_MODE_SFP:
axgbe_printf(3, "%s: calling phy detect\n", __func__);
xgbe_phy_sfp_detect(pdata);
break;
default:
break;
}
/* If we have an external PHY, start it */
ret = xgbe_phy_find_phy_device(pdata);
if (ret) {
axgbe_error("%s: impl find phy dev ret %d\n", __func__, ret);
goto err_i2c;
}
axgbe_printf(3, "%s: impl return success\n", __func__);
return (0);
err_i2c:
pdata->i2c_if.i2c_stop(pdata);
return (ret);
}
static int
xgbe_phy_reset(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data = pdata->phy_data;
enum xgbe_mode cur_mode;
int ret;
/* Reset by power cycling the PHY */
cur_mode = phy_data->cur_mode;
xgbe_phy_power_off(pdata);
xgbe_phy_set_mode(pdata, cur_mode);
axgbe_printf(3, "%s: mode %d\n", __func__, cur_mode);
if (!phy_data->phydev) {
axgbe_printf(1, "%s: no phydev\n", __func__);
return (0);
}
/* Reset the external PHY */
ret = xgbe_phy_mdio_reset(pdata);
if (ret) {
axgbe_error("%s: mdio reset %d\n", __func__, ret);
return (ret);
}
axgbe_printf(3, "%s: return success\n", __func__);
return (0);
}
static void
axgbe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
{
struct axgbe_if_softc *sc;
struct xgbe_prv_data *pdata;
struct mii_data *mii;
sc = ifp->if_softc;
pdata = &sc->pdata;
axgbe_printf(2, "%s: Invoked\n", __func__);
mtx_lock_spin(&pdata->mdio_mutex);
mii = device_get_softc(pdata->axgbe_miibus);
axgbe_printf(2, "%s: media_active %#x media_status %#x\n", __func__,
mii->mii_media_active, mii->mii_media_status);
mii_pollstat(mii);
ifmr->ifm_active = mii->mii_media_active;
ifmr->ifm_status = mii->mii_media_status;
mtx_unlock_spin(&pdata->mdio_mutex);
}
static int
axgbe_ifmedia_upd(struct ifnet *ifp)
{
struct xgbe_prv_data *pdata;
struct axgbe_if_softc *sc;
struct mii_data *mii;
struct mii_softc *miisc;
int ret;
sc = ifp->if_softc;
pdata = &sc->pdata;
axgbe_printf(2, "%s: Invoked\n", __func__);
mtx_lock_spin(&pdata->mdio_mutex);
mii = device_get_softc(pdata->axgbe_miibus);
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
PHY_RESET(miisc);
ret = mii_mediachg(mii);
mtx_unlock_spin(&pdata->mdio_mutex);
return (ret);
}
static void
xgbe_phy_exit(struct xgbe_prv_data *pdata)
{
if (pdata->axgbe_miibus != NULL)
device_delete_child(pdata->dev, pdata->axgbe_miibus);
/* free phy_data structure */
free(pdata->phy_data, M_AXGBE);
}
static int
xgbe_phy_init(struct xgbe_prv_data *pdata)
{
struct xgbe_phy_data *phy_data;
int ret;
/* Initialize the global lock */
if (!mtx_initialized(&xgbe_phy_comm_lock))
mtx_init(&xgbe_phy_comm_lock, "xgbe phy common lock", NULL, MTX_DEF);
/* Check if enabled */
if (!xgbe_phy_port_enabled(pdata)) {
axgbe_error("device is not enabled\n");
return (-ENODEV);
}
/* Initialize the I2C controller */
ret = pdata->i2c_if.i2c_init(pdata);
if (ret)
return (ret);
phy_data = malloc(sizeof(*phy_data), M_AXGBE, M_WAITOK | M_ZERO);
if (!phy_data)
return (-ENOMEM);
pdata->phy_data = phy_data;
phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
pdata->mdio_addr = phy_data->mdio_addr;
DBGPR("port mode=%u\n", phy_data->port_mode);
DBGPR("port id=%u\n", phy_data->port_id);
DBGPR("port speeds=%#x\n", phy_data->port_speeds);
DBGPR("conn type=%u\n", phy_data->conn_type);
DBGPR("mdio addr=%u\n", phy_data->mdio_addr);
phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
if (phy_data->redrv) {
DBGPR("redrv present\n");
DBGPR("redrv i/f=%u\n", phy_data->redrv_if);
DBGPR("redrv addr=%#x\n", phy_data->redrv_addr);
DBGPR("redrv lane=%u\n", phy_data->redrv_lane);
DBGPR("redrv model=%u\n", phy_data->redrv_model);
}
DBGPR("%s: redrv addr=%#x redrv i/f=%u\n", __func__,
phy_data->redrv_addr, phy_data->redrv_if);
/* Validate the connection requested */
if (xgbe_phy_conn_type_mismatch(pdata)) {
axgbe_error("phy mode/connection mismatch "
"(%#x/%#x)\n", phy_data->port_mode, phy_data->conn_type);
return (-EINVAL);
}
/* Validate the mode requested */
if (xgbe_phy_port_mode_mismatch(pdata)) {
axgbe_error("phy mode/speed mismatch "
"(%#x/%#x)\n", phy_data->port_mode, phy_data->port_speeds);
return (-EINVAL);
}
/* Check for and validate MDIO reset support */
ret = xgbe_phy_mdio_reset_setup(pdata);
if (ret) {
axgbe_error("%s, mdio_reset_setup ret %d\n", __func__, ret);
return (ret);
}
/* Validate the re-driver information */
if (xgbe_phy_redrv_error(phy_data)) {
axgbe_error("phy re-driver settings error\n");
return (-EINVAL);
}
pdata->kr_redrv = phy_data->redrv;
/* Indicate current mode is unknown */
phy_data->cur_mode = XGBE_MODE_UNKNOWN;
/* Initialize supported features. Current code does not support ethtool */
XGBE_ZERO_SUP(&pdata->phy);
DBGPR("%s: port mode %d\n", __func__, phy_data->port_mode);
switch (phy_data->port_mode) {
/* Backplane support */
case XGBE_PORT_MODE_BACKPLANE:
XGBE_SET_SUP(&pdata->phy, Autoneg);
XGBE_SET_SUP(&pdata->phy, Pause);
XGBE_SET_SUP(&pdata->phy, Asym_Pause);
XGBE_SET_SUP(&pdata->phy, Backplane);
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);
phy_data->start_mode = XGBE_MODE_KX_1000;
}
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);
if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
phy_data->start_mode = XGBE_MODE_KR;
}
phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
break;
case XGBE_PORT_MODE_BACKPLANE_2500:
XGBE_SET_SUP(&pdata->phy, Pause);
XGBE_SET_SUP(&pdata->phy, Asym_Pause);
XGBE_SET_SUP(&pdata->phy, Backplane);
XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);
phy_data->start_mode = XGBE_MODE_KX_2500;
phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
break;
/* MDIO 1GBase-T support */
case XGBE_PORT_MODE_1000BASE_T:
XGBE_SET_SUP(&pdata->phy, Autoneg);
XGBE_SET_SUP(&pdata->phy, Pause);
XGBE_SET_SUP(&pdata->phy, Asym_Pause);
XGBE_SET_SUP(&pdata->phy, TP);
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
phy_data->start_mode = XGBE_MODE_SGMII_100;
}
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
phy_data->start_mode = XGBE_MODE_SGMII_1000;
}
phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
break;
/* MDIO Base-X support */
case XGBE_PORT_MODE_1000BASE_X:
XGBE_SET_SUP(&pdata->phy, Autoneg);
XGBE_SET_SUP(&pdata->phy, Pause);
XGBE_SET_SUP(&pdata->phy, Asym_Pause);
XGBE_SET_SUP(&pdata->phy, FIBRE);
XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
phy_data->start_mode = XGBE_MODE_X;
phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
break;
/* MDIO NBase-T support */
case XGBE_PORT_MODE_NBASE_T:
XGBE_SET_SUP(&pdata->phy, Autoneg);
XGBE_SET_SUP(&pdata->phy, Pause);
XGBE_SET_SUP(&pdata->phy, Asym_Pause);
XGBE_SET_SUP(&pdata->phy, TP);
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
phy_data->start_mode = XGBE_MODE_SGMII_100;
}
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
phy_data->start_mode = XGBE_MODE_SGMII_1000;
}
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
XGBE_SET_SUP(&pdata->phy, 2500baseT_Full);
phy_data->start_mode = XGBE_MODE_KX_2500;
}
phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
break;
/* 10GBase-T support */
case XGBE_PORT_MODE_10GBASE_T:
XGBE_SET_SUP(&pdata->phy, Autoneg);
XGBE_SET_SUP(&pdata->phy, Pause);
XGBE_SET_SUP(&pdata->phy, Asym_Pause);
XGBE_SET_SUP(&pdata->phy, TP);
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
phy_data->start_mode = XGBE_MODE_SGMII_100;
}
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
phy_data->start_mode = XGBE_MODE_SGMII_1000;
}
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
XGBE_SET_SUP(&pdata->phy, 10000baseT_Full);
phy_data->start_mode = XGBE_MODE_KR;
}
phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
break;
/* 10GBase-R support */
case XGBE_PORT_MODE_10GBASE_R:
XGBE_SET_SUP(&pdata->phy, Autoneg);
XGBE_SET_SUP(&pdata->phy, Pause);
XGBE_SET_SUP(&pdata->phy, Asym_Pause);
XGBE_SET_SUP(&pdata->phy, FIBRE);
XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
phy_data->start_mode = XGBE_MODE_SFI;
phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
break;
/* SFP support */
case XGBE_PORT_MODE_SFP:
XGBE_SET_SUP(&pdata->phy, Autoneg);
XGBE_SET_SUP(&pdata->phy, Pause);
XGBE_SET_SUP(&pdata->phy, Asym_Pause);
XGBE_SET_SUP(&pdata->phy, TP);
XGBE_SET_SUP(&pdata->phy, FIBRE);
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
phy_data->start_mode = XGBE_MODE_SGMII_100;
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
phy_data->start_mode = XGBE_MODE_SGMII_1000;
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
phy_data->start_mode = XGBE_MODE_SFI;
phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
xgbe_phy_sfp_setup(pdata);
DBGPR("%s: start %d mode %d adv 0x%x\n", __func__,
phy_data->start_mode, phy_data->phydev_mode,
pdata->phy.advertising);
break;
default:
return (-EINVAL);
}
axgbe_printf(2, "%s: start %d mode %d adv 0x%x\n", __func__,
phy_data->start_mode, phy_data->phydev_mode, pdata->phy.advertising);
DBGPR("%s: conn type %d mode %d\n", __func__,
phy_data->conn_type, phy_data->phydev_mode);
if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
(phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
phy_data->phydev_mode);
if (ret) {
axgbe_error("mdio port/clause not compatible (%d/%u)\n",
phy_data->mdio_addr, phy_data->phydev_mode);
return (-EINVAL);
}
}
if (phy_data->redrv && !phy_data->redrv_if) {
ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
XGBE_MDIO_MODE_CL22);
if (ret) {
axgbe_error("redriver mdio port not compatible (%u)\n",
phy_data->redrv_addr);
return (-EINVAL);
}
}
phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev,
(ifm_change_cb_t)axgbe_ifmedia_upd,
(ifm_stat_cb_t)axgbe_ifmedia_sts, BMSR_DEFCAPMASK,
pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);
if (ret){
axgbe_printf(2, "mii attach failed with err=(%d)\n", ret);
return (-EINVAL);
}
}
DBGPR("%s: return success\n", __func__);
return (0);
}
void
xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
{
struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
phy_impl->init = xgbe_phy_init;
phy_impl->exit = xgbe_phy_exit;
phy_impl->reset = xgbe_phy_reset;
phy_impl->start = xgbe_phy_start;
phy_impl->stop = xgbe_phy_stop;
phy_impl->link_status = xgbe_phy_link_status;
phy_impl->valid_speed = xgbe_phy_valid_speed;
phy_impl->use_mode = xgbe_phy_use_mode;
phy_impl->set_mode = xgbe_phy_set_mode;
phy_impl->get_mode = xgbe_phy_get_mode;
phy_impl->switch_mode = xgbe_phy_switch_mode;
phy_impl->cur_mode = xgbe_phy_cur_mode;
phy_impl->get_type = xgbe_phy_get_type;
phy_impl->an_mode = xgbe_phy_an_mode;
phy_impl->an_config = xgbe_phy_an_config;
phy_impl->an_advertising = xgbe_phy_an_advertising;
phy_impl->an_outcome = xgbe_phy_an_outcome;
phy_impl->an_pre = xgbe_phy_an_pre;
phy_impl->an_post = xgbe_phy_an_post;
phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
phy_impl->kr_training_post = xgbe_phy_kr_training_post;
phy_impl->module_info = xgbe_phy_module_info;
phy_impl->module_eeprom = xgbe_phy_module_eeprom;
}
diff --git a/sys/dev/axgbe/xgbe-sysctl.c b/sys/dev/axgbe/xgbe-sysctl.c
index a3e777e0ca26..f7998b943b16 100644
--- a/sys/dev/axgbe/xgbe-sysctl.c
+++ b/sys/dev/axgbe/xgbe-sysctl.c
@@ -1,1719 +1,1723 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2020 Advanced Micro Devices, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* Contact Information :
* Rajesh Kumar
* Arpan Palit
*/
#include
__FBSDID("$FreeBSD$");
#include
#include
#include
#include "xgbe.h"
#include "xgbe-common.h"
#define SYSCTL_BUF_LEN 64
typedef enum{
/* Coalesce flag */
rx_coalesce_usecs = 1,
rx_max_coalesced_frames,
rx_coalesce_usecs_irq,
rx_max_coalesced_frames_irq,
tx_coalesce_usecs,
tx_max_coalesced_frames,
tx_coalesce_usecs_irq,
tx_max_coalesced_frames_irq,
stats_block_coalesce_usecs,
use_adaptive_rx_coalesce,
use_adaptive_tx_coalesce,
pkt_rate_low,
rx_coalesce_usecs_low,
rx_max_coalesced_frames_low,
tx_coalesce_usecs_low,
tx_max_coalesced_frames_low,
pkt_rate_high,
rx_coalesce_usecs_high,
rx_max_coalesced_frames_high,
tx_coalesce_usecs_high,
tx_max_coalesced_frames_high,
rate_sample_interval,
/* Pasue flag */
autoneg,
tx_pause,
rx_pause,
/* link settings */
speed,
duplex,
/* Ring settings */
rx_pending,
rx_mini_pending,
rx_jumbo_pending,
tx_pending,
/* Channels settings */
rx_count,
tx_count,
other_count,
combined_count,
} sysctl_variable_t;
typedef enum {
SYSL_NONE,
SYSL_BOOL,
SYSL_S32,
SYSL_U8,
SYSL_U16,
SYSL_U32,
SYSL_U64,
SYSL_BE16,
SYSL_IP4,
SYSL_STR,
SYSL_FLAG,
SYSL_MAC,
} sysctl_type_t;
struct sysctl_info {
uint8_t name[32];
sysctl_type_t type;
sysctl_variable_t flag;
uint8_t support[16];
};
struct sysctl_op {
/* Coalesce options */
unsigned int rx_coalesce_usecs;
unsigned int rx_max_coalesced_frames;
unsigned int rx_coalesce_usecs_irq;
unsigned int rx_max_coalesced_frames_irq;
unsigned int tx_coalesce_usecs;
unsigned int tx_max_coalesced_frames;
unsigned int tx_coalesce_usecs_irq;
unsigned int tx_max_coalesced_frames_irq;
unsigned int stats_block_coalesce_usecs;
unsigned int use_adaptive_rx_coalesce;
unsigned int use_adaptive_tx_coalesce;
unsigned int pkt_rate_low;
unsigned int rx_coalesce_usecs_low;
unsigned int rx_max_coalesced_frames_low;
unsigned int tx_coalesce_usecs_low;
unsigned int tx_max_coalesced_frames_low;
unsigned int pkt_rate_high;
unsigned int rx_coalesce_usecs_high;
unsigned int rx_max_coalesced_frames_high;
unsigned int tx_coalesce_usecs_high;
unsigned int tx_max_coalesced_frames_high;
unsigned int rate_sample_interval;
/* Pasue options */
unsigned int autoneg;
unsigned int tx_pause;
unsigned int rx_pause;
/* Link settings options */
unsigned int speed;
unsigned int duplex;
/* Ring param options */
unsigned int rx_max_pending;
unsigned int rx_mini_max_pending;
unsigned int rx_jumbo_max_pending;
unsigned int tx_max_pending;
unsigned int rx_pending;
unsigned int rx_mini_pending;
unsigned int rx_jumbo_pending;
unsigned int tx_pending;
/* Channels options */
unsigned int max_rx;
unsigned int max_tx;
unsigned int max_other;
unsigned int max_combined;
unsigned int rx_count;
unsigned int tx_count;
unsigned int other_count;
unsigned int combined_count;
} sys_op;
#define GSTRING_LEN 32
struct xgbe_stats {
char stat_string[GSTRING_LEN];
int stat_size;
int stat_offset;
};
#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
#define XGMAC_MMC_STAT(_string, _var) \
{ _string, \
FIELD_SIZEOF(struct xgbe_mmc_stats, _var), \
offsetof(struct xgbe_prv_data, mmc_stats._var), \
}
#define XGMAC_EXT_STAT(_string, _var) \
{ _string, \
FIELD_SIZEOF(struct xgbe_ext_stats, _var), \
offsetof(struct xgbe_prv_data, ext_stats._var), \
}
static const struct xgbe_stats xgbe_gstring_stats[] = {
XGMAC_MMC_STAT("tx_bytes", txoctetcount_gb),
XGMAC_MMC_STAT("tx_packets", txframecount_gb),
XGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb),
XGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb),
XGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb),
XGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g),
XGMAC_EXT_STAT("tx_vxlan_packets", tx_vxlan_packets),
XGMAC_EXT_STAT("tx_tso_packets", tx_tso_packets),
XGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb),
XGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb),
XGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb),
XGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb),
XGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb),
XGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb),
XGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror),
XGMAC_MMC_STAT("tx_pause_frames", txpauseframes),
XGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb),
XGMAC_MMC_STAT("rx_packets", rxframecount_gb),
XGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g),
XGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g),
XGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g),
XGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb),
XGMAC_EXT_STAT("rx_vxlan_packets", rx_vxlan_packets),
XGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb),
XGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb),
XGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb),
XGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb),
XGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb),
XGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb),
XGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g),
XGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g),
XGMAC_MMC_STAT("rx_crc_errors", rxcrcerror),
XGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror),
XGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror),
XGMAC_MMC_STAT("rx_length_errors", rxlengtherror),
XGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype),
XGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow),
XGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror),
XGMAC_EXT_STAT("rx_csum_errors", rx_csum_errors),
XGMAC_EXT_STAT("rx_vxlan_csum_errors", rx_vxlan_csum_errors),
XGMAC_MMC_STAT("rx_pause_frames", rxpauseframes),
XGMAC_EXT_STAT("rx_split_header_packets", rx_split_header_packets),
XGMAC_EXT_STAT("rx_buffer_unavailable", rx_buffer_unavailable),
};
#define XGBE_STATS_COUNT ARRAY_SIZE(xgbe_gstring_stats)
char** alloc_sysctl_buffer(void);
void get_val(char *buf, char **op, char **val, int *n_op);
void fill_data(struct sysctl_op *sys_op, int flag, unsigned int value);
static int
exit_bad_op(void)
{
printf("SYSCTL: bad command line option (s)\n");
return(-EINVAL);
}
static inline unsigned
fls_long(unsigned long l)
{
if (sizeof(l) == 4)
return (fls(l));
return (fls64(l));
}
static inline __attribute__((const))
unsigned long __rounddown_pow_of_two(unsigned long n)
{
return (1UL << (fls_long(n) - 1));
}
static inline int
get_ubuf(struct sysctl_req *req, char *ubuf)
{
int rc;
printf("%s: len:0x%li idx:0x%li\n", __func__, req->newlen,
req->newidx);
if (req->newlen >= SYSCTL_BUF_LEN)
return (-EINVAL);
rc = SYSCTL_IN(req, ubuf, req->newlen);
if (rc)
return (rc);
ubuf[req->newlen] = '\0';
return (0);
}
char**
alloc_sysctl_buffer(void)
{
char **buffer;
int i;
buffer = malloc(sizeof(char *)*32, M_AXGBE, M_WAITOK | M_ZERO);
for(i = 0; i < 32; i++)
buffer[i] = malloc(sizeof(char)*32, M_AXGBE, M_WAITOK | M_ZERO);
return (buffer);
}
void
get_val(char *buf, char **op, char **val, int *n_op)
{
int blen = strlen(buf);
int count = 0;
int i, j;
*n_op = 0;
for (i = 0; i < blen; i++) {
count++;
/* Get sysctl command option */
for (j = 0; buf[i] != ' '; j++) {
if (i >= blen)
break;
op[*n_op][j] = buf[i++];
}
op[*n_op][j+1] = '\0';
if (i >= strlen(buf))
goto out;
/* Get sysctl value*/
i++;
for (j = 0; buf[i] != ' '; j++) {
if (i >= blen)
break;
val[*n_op][j] = buf[i++];
}
val[*n_op][j+1] = '\0';
if (i >= strlen(buf))
goto out;
*n_op = count;
}
out:
*n_op = count;
}
void
fill_data(struct sysctl_op *sys_op, int flag, unsigned int value)
{
switch(flag) {
case 1:
sys_op->rx_coalesce_usecs = value;
break;
case 2:
sys_op->rx_max_coalesced_frames = value;
break;
case 3:
sys_op->rx_coalesce_usecs_irq = value;
break;
case 4:
sys_op->rx_max_coalesced_frames_irq = value;
break;
case 5:
sys_op->tx_coalesce_usecs = value;
break;
case 6:
sys_op->tx_max_coalesced_frames = value;
break;
case 7:
sys_op->tx_coalesce_usecs_irq = value;
break;
case 8:
sys_op->tx_max_coalesced_frames_irq = value;
break;
case 9:
sys_op->stats_block_coalesce_usecs = value;
break;
case 10:
sys_op->use_adaptive_rx_coalesce = value;
break;
case 11:
sys_op->use_adaptive_tx_coalesce = value;
break;
case 12:
sys_op->pkt_rate_low = value;
break;
case 13:
sys_op->rx_coalesce_usecs_low = value;
break;
case 14:
sys_op->rx_max_coalesced_frames_low = value;
break;
case 15:
sys_op->tx_coalesce_usecs_low = value;
break;
case 16:
sys_op->tx_max_coalesced_frames_low = value;
break;
case 17:
sys_op->pkt_rate_high = value;
break;
case 18:
sys_op->rx_coalesce_usecs_high = value;
break;
case 19:
sys_op->rx_max_coalesced_frames_high = value;
break;
case 20:
sys_op->tx_coalesce_usecs_high = value;
break;
case 21:
sys_op->tx_max_coalesced_frames_high = value;
break;
case 22:
sys_op->rate_sample_interval = value;
break;
case 23:
sys_op->autoneg = value;
break;
case 24:
sys_op->rx_pause = value;
break;
case 25:
sys_op->tx_pause = value;
break;
case 26:
sys_op->speed = value;
break;
case 27:
sys_op->duplex = value;
break;
case 28:
sys_op->rx_pending = value;
break;
case 29:
sys_op->rx_mini_pending = value;
break;
case 30:
sys_op->rx_jumbo_pending = value;
break;
case 31:
sys_op->tx_pending = value;
break;
default:
printf("Option error\n");
}
}
static int
parse_generic_sysctl(struct xgbe_prv_data *pdata, char *buf,
struct sysctl_info *info, unsigned int n_info)
{
struct sysctl_op *sys_op = pdata->sys_op;
unsigned int value;
char **op, **val;
int n_op = 0;
int rc = 0;
int i, idx;
op = alloc_sysctl_buffer();
val = alloc_sysctl_buffer();
get_val(buf, op, val, &n_op);
for (i = 0; i < n_op; i++) {
for (idx = 0; idx < n_info; idx++) {
if (strcmp(info[idx].name, op[i]) == 0) {
if (strcmp(info[idx].support,
"not-supported") == 0){
axgbe_printf(1, "ignoring not-supported "
"option \"%s\"\n", info[idx].name);
break;
}
switch(info[idx].type) {
case SYSL_BOOL: {
if (!strcmp(val[i], "on"))
fill_data(sys_op,
info[idx].flag, 1);
else if (!strcmp(val[i], "off"))
fill_data(sys_op,
info[idx].flag, 0);
else
rc = exit_bad_op();
break;
}
case SYSL_S32:
sscanf(val[i], "%u", &value);
fill_data(sys_op, info[idx].flag, value);
break;
case SYSL_U8:
if (!strcmp(val[i], "half"))
fill_data(sys_op,
info[idx].flag, DUPLEX_HALF);
else if (!strcmp(val[i], "full"))
fill_data(sys_op,
info[idx].flag, DUPLEX_FULL);
else
exit_bad_op();
default:
rc = exit_bad_op();
}
}
}
}
for(i = 0; i < 32; i++)
free(op[i], M_AXGBE);
free(op, M_AXGBE);
for(i = 0; i < 32; i++)
free(val[i], M_AXGBE);
free(val, M_AXGBE);
return (rc);
}
static int
sysctl_xgmac_reg_addr_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
char buf[buf_size];
struct sbuf *sb;
unsigned int reg;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
axgbe_printf(2, "READ: %s: sysctl_xgmac_reg: 0x%x\n", __func__,
pdata->sysctl_xgmac_reg);
sbuf_printf(sb, "\nXGMAC reg_addr: 0x%x\n",
pdata->sysctl_xgmac_reg);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%x", ®);
axgbe_printf(2, "WRITE: %s: reg: 0x%x\n", __func__, reg);
pdata->sysctl_xgmac_reg = reg;
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_get_drv_info_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
ssize_t buf_size = 64;
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
sbuf_printf(sb, "\ndriver: %s", XGBE_DRV_NAME);
sbuf_printf(sb, "\nversion: %s", XGBE_DRV_VERSION);
sbuf_printf(sb, "\nfirmware-version: %d.%d.%d",
XGMAC_GET_BITS(hw_feat->version, MAC_VR, USERVER),
XGMAC_GET_BITS(hw_feat->version, MAC_VR, DEVID),
XGMAC_GET_BITS(hw_feat->version, MAC_VR, SNPSVER));
sbuf_printf(sb, "\nbus-info: %04d:%02d:%02d",
pdata->pcie_bus, pdata->pcie_device, pdata->pcie_func);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
return (-EINVAL);
}
static int
sysctl_get_link_info_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
sbuf_printf(sb, "\nLink is %s", pdata->phy.link ? "Up" : "Down");
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (0);
}
return (-EINVAL);
}
#define COALESCE_SYSCTL_INFO(__coalop) \
{ \
{ "adaptive-rx", SYSL_BOOL, use_adaptive_rx_coalesce, "not-supported" }, \
{ "adaptive-tx", SYSL_BOOL, use_adaptive_tx_coalesce, "not-supported" }, \
{ "sample-interval", SYSL_S32, rate_sample_interval, "not-supported" }, \
{ "stats-block-usecs", SYSL_S32, stats_block_coalesce_usecs, "not-supported" }, \
{ "pkt-rate-low", SYSL_S32, pkt_rate_low, "not-supported" }, \
{ "pkt-rate-high", SYSL_S32, pkt_rate_high, "not-supported" }, \
{ "rx-usecs", SYSL_S32, rx_coalesce_usecs, "supported" }, \
{ "rx-frames", SYSL_S32, rx_max_coalesced_frames, "supported" }, \
{ "rx-usecs-irq", SYSL_S32, rx_coalesce_usecs_irq, "not-supported" }, \
{ "rx-frames-irq", SYSL_S32, rx_max_coalesced_frames_irq, "not-supported" }, \
{ "tx-usecs", SYSL_S32, tx_coalesce_usecs, "not-supported" }, \
{ "tx-frames", SYSL_S32, tx_max_coalesced_frames, "supported" }, \
{ "tx-usecs-irq", SYSL_S32, tx_coalesce_usecs_irq, "not-supported" }, \
{ "tx-frames-irq", SYSL_S32, tx_max_coalesced_frames_irq, "not-supported" }, \
{ "rx-usecs-low", SYSL_S32, rx_coalesce_usecs_low, "not-supported" }, \
{ "rx-frames-low", SYSL_S32, rx_max_coalesced_frames_low, "not-supported"}, \
{ "tx-usecs-low", SYSL_S32, tx_coalesce_usecs_low, "not-supported" }, \
{ "tx-frames-low", SYSL_S32, tx_max_coalesced_frames_low, "not-supported" }, \
{ "rx-usecs-high", SYSL_S32, rx_coalesce_usecs_high, "not-supported" }, \
{ "rx-frames-high", SYSL_S32, rx_max_coalesced_frames_high, "not-supported" }, \
{ "tx-usecs-high", SYSL_S32, tx_coalesce_usecs_high, "not-supported" }, \
{ "tx-frames-high", SYSL_S32, tx_max_coalesced_frames_high, "not-supported" }, \
}
static int
sysctl_coalesce_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
struct xgbe_hw_if *hw_if = &pdata->hw_if;
struct sysctl_op *sys_op = pdata->sys_op;
struct sysctl_info sysctl_coalesce[] = COALESCE_SYSCTL_INFO(coalop);
unsigned int rx_frames, rx_riwt, rx_usecs;
unsigned int tx_frames;
ssize_t buf_size = 64;
char buf[buf_size];
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
sys_op->rx_coalesce_usecs = pdata->rx_usecs;
sys_op->rx_max_coalesced_frames = pdata->rx_frames;
sys_op->tx_max_coalesced_frames = pdata->tx_frames;
sbuf_printf(sb, "\nAdaptive RX: %s TX: %s\n",
sys_op->use_adaptive_rx_coalesce ? "on" : "off",
sys_op->use_adaptive_tx_coalesce ? "on" : "off");
sbuf_printf(sb, "stats-block-usecs: %u\n"
"sample-interval: %u\n"
"pkt-rate-low: %u\n"
"pkt-rate-high: %u\n"
"\n"
"rx-usecs: %u\n"
"rx-frames: %u\n"
"rx-usecs-irq: %u\n"
"rx-frames-irq: %u\n"
"\n"
"tx-usecs: %u\n"
"tx-frames: %u\n"
"tx-usecs-irq: %u\n"
"tx-frames-irq: %u\n"
"\n"
"rx-usecs-low: %u\n"
"rx-frames-low: %u\n"
"tx-usecs-low: %u\n"
"tx-frames-low: %u\n"
"\n"
"rx-usecs-high: %u\n"
"rx-frames-high: %u\n"
"tx-usecs-high: %u\n"
"tx-frames-high: %u\n",
sys_op->stats_block_coalesce_usecs,
sys_op->rate_sample_interval,
sys_op->pkt_rate_low,
sys_op->pkt_rate_high,
sys_op->rx_coalesce_usecs,
sys_op->rx_max_coalesced_frames,
sys_op->rx_coalesce_usecs_irq,
sys_op->rx_max_coalesced_frames_irq,
sys_op->tx_coalesce_usecs,
sys_op->tx_max_coalesced_frames,
sys_op->tx_coalesce_usecs_irq,
sys_op->tx_max_coalesced_frames_irq,
sys_op->rx_coalesce_usecs_low,
sys_op->rx_max_coalesced_frames_low,
sys_op->tx_coalesce_usecs_low,
sys_op->tx_max_coalesced_frames_low,
sys_op->rx_coalesce_usecs_high,
sys_op->rx_max_coalesced_frames_high,
sys_op->tx_coalesce_usecs_high,
sys_op->tx_max_coalesced_frames_high);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (0);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
parse_generic_sysctl(pdata, buf, sysctl_coalesce,
ARRAY_SIZE(sysctl_coalesce));
rx_riwt = hw_if->usec_to_riwt(pdata, sys_op->rx_coalesce_usecs);
rx_usecs = sys_op->rx_coalesce_usecs;
rx_frames = sys_op->rx_max_coalesced_frames;
/* Use smallest possible value if conversion resulted in zero */
if (rx_usecs && !rx_riwt)
rx_riwt = 1;
/* Check the bounds of values for Rx */
if (rx_riwt > XGMAC_MAX_DMA_RIWT) {
axgbe_printf(2, "rx-usec is limited to %d usecs\n",
hw_if->riwt_to_usec(pdata, XGMAC_MAX_DMA_RIWT));
return (-EINVAL);
}
if (rx_frames > pdata->rx_desc_count) {
axgbe_printf(2, "rx-frames is limited to %d frames\n",
pdata->rx_desc_count);
return (-EINVAL);
}
tx_frames = sys_op->tx_max_coalesced_frames;
/* Check the bounds of values for Tx */
if (tx_frames > pdata->tx_desc_count) {
axgbe_printf(2, "tx-frames is limited to %d frames\n",
pdata->tx_desc_count);
return (-EINVAL);
}
pdata->rx_riwt = rx_riwt;
pdata->rx_usecs = rx_usecs;
pdata->rx_frames = rx_frames;
hw_if->config_rx_coalesce(pdata);
pdata->tx_frames = tx_frames;
hw_if->config_tx_coalesce(pdata);
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_pauseparam_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
struct sysctl_op *sys_op = pdata->sys_op;
struct sysctl_info sysctl_pauseparam[] = {
{ "autoneg", SYSL_BOOL, autoneg, "supported" },
{ "rx", SYSL_BOOL, rx_pause, "supported" },
{ "tx", SYSL_BOOL, tx_pause, "supported" },
};
ssize_t buf_size = 512;
char buf[buf_size];
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
sys_op->autoneg = pdata->phy.pause_autoneg;
sys_op->tx_pause = pdata->phy.tx_pause;
sys_op->rx_pause = pdata->phy.rx_pause;
sbuf_printf(sb,
"\nAutonegotiate: %s\n"
"RX: %s\n"
"TX: %s\n",
sys_op->autoneg ? "on" : "off",
sys_op->rx_pause ? "on" : "off",
sys_op->tx_pause ? "on" : "off");
if (pdata->phy.lp_advertising) {
int an_rx = 0, an_tx = 0;
if (pdata->phy.advertising & pdata->phy.lp_advertising &
ADVERTISED_Pause) {
an_tx = 1;
an_rx = 1;
} else if (pdata->phy.advertising &
pdata->phy.lp_advertising & ADVERTISED_Asym_Pause) {
if (pdata->phy.advertising & ADVERTISED_Pause)
an_rx = 1;
else if (pdata->phy.lp_advertising &
ADVERTISED_Pause)
an_tx = 1;
}
sbuf_printf(sb,
"\n->\nRX negotiated: %s\n"
"TX negotiated: %s\n",
an_rx ? "on" : "off",
an_tx ? "on" : "off");
}
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (0);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
parse_generic_sysctl(pdata, buf, sysctl_pauseparam,
ARRAY_SIZE(sysctl_pauseparam));
if (sys_op->autoneg && (pdata->phy.autoneg != AUTONEG_ENABLE)) {
axgbe_error("autoneg disabled, pause autoneg not available\n");
return (-EINVAL);
}
pdata->phy.pause_autoneg = sys_op->autoneg;
pdata->phy.tx_pause = sys_op->tx_pause;
pdata->phy.rx_pause = sys_op->rx_pause;
XGBE_CLR_ADV(&pdata->phy, Pause);
XGBE_CLR_ADV(&pdata->phy, Asym_Pause);
if (sys_op->rx_pause) {
XGBE_SET_ADV(&pdata->phy, Pause);
XGBE_SET_ADV(&pdata->phy, Asym_Pause);
}
if (sys_op->tx_pause) {
/* Equivalent to XOR of Asym_Pause */
if (XGBE_ADV(&pdata->phy, Asym_Pause))
XGBE_CLR_ADV(&pdata->phy, Asym_Pause);
else
XGBE_SET_ADV(&pdata->phy, Asym_Pause);
}
if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
rc = pdata->phy_if.phy_config_aneg(pdata);
}
return (rc);
}
static int
sysctl_link_ksettings_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
struct sysctl_op *sys_op = pdata->sys_op;
struct sysctl_info sysctl_linksettings[] = {
{ "autoneg", SYSL_BOOL, autoneg, "supported" },
{ "speed", SYSL_U32, speed, "supported" },
{ "duplex", SYSL_U8, duplex, "supported" },
};
ssize_t buf_size = 512;
char buf[buf_size], link_modes[16], speed_modes[16];
struct sbuf *sb;
uint32_t speed;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
sys_op->autoneg = pdata->phy.autoneg;
sys_op->speed = pdata->phy.speed;
sys_op->duplex = pdata->phy.duplex;
XGBE_LM_COPY(&pdata->phy, supported, &pdata->phy, supported);
XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, advertising);
XGBE_LM_COPY(&pdata->phy, lp_advertising, &pdata->phy, lp_advertising);
switch (sys_op->speed) {
case 1:
strcpy(link_modes, "Unknown");
strcpy(speed_modes, "Unknown");
break;
case 2:
strcpy(link_modes, "10Gbps/Full");
strcpy(speed_modes, "10000");
break;
case 3:
strcpy(link_modes, "2.5Gbps/Full");
strcpy(speed_modes, "2500");
break;
case 4:
strcpy(link_modes, "1Gbps/Full");
strcpy(speed_modes, "1000");
break;
case 5:
strcpy(link_modes, "100Mbps/Full");
strcpy(speed_modes, "100");
break;
case 6:
strcpy(link_modes, "10Mbps/Full");
strcpy(speed_modes, "10");
break;
}
sbuf_printf(sb,
"\nlink_modes: %s\n"
"autonegotiation: %s\n"
"speed: %sMbps\n",
link_modes,
(sys_op->autoneg == AUTONEG_DISABLE) ? "off" : "on",
speed_modes);
switch (sys_op->duplex) {
case DUPLEX_HALF:
sbuf_printf(sb, "Duplex: Half\n");
break;
case DUPLEX_FULL:
sbuf_printf(sb, "Duplex: Full\n");
break;
default:
sbuf_printf(sb, "Duplex: Unknown\n");
break;
}
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (0);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
parse_generic_sysctl(pdata, buf, sysctl_linksettings,
ARRAY_SIZE(sysctl_linksettings));
speed = sys_op->speed;
if ((sys_op->autoneg != AUTONEG_ENABLE) &&
(sys_op->autoneg != AUTONEG_DISABLE)) {
axgbe_error("unsupported autoneg %hhu\n",
(unsigned char)sys_op->autoneg);
return (-EINVAL);
}
if (sys_op->autoneg == AUTONEG_DISABLE) {
if (!pdata->phy_if.phy_valid_speed(pdata, speed)) {
axgbe_error("unsupported speed %u\n", speed);
return (-EINVAL);
}
if (sys_op->duplex != DUPLEX_FULL) {
axgbe_error("unsupported duplex %hhu\n",
(unsigned char)sys_op->duplex);
return (-EINVAL);
}
}
pdata->phy.autoneg = sys_op->autoneg;
pdata->phy.speed = speed;
pdata->phy.duplex = sys_op->duplex;
if (sys_op->autoneg == AUTONEG_ENABLE)
XGBE_SET_ADV(&pdata->phy, Autoneg);
else
XGBE_CLR_ADV(&pdata->phy, Autoneg);
if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
rc = pdata->phy_if.phy_config_aneg(pdata);
}
return (rc);
}
static int
sysctl_ringparam_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
struct sysctl_op *sys_op = pdata->sys_op;
struct sysctl_info sysctl_ringparam[] = {
{ "rx", SYSL_S32, rx_pending, "supported" },
{ "rx-mini", SYSL_S32, rx_mini_pending, "supported" },
{ "rx-jumbo", SYSL_S32, rx_jumbo_pending, "supported" },
{ "tx", SYSL_S32, tx_pending, "supported" },
};
ssize_t buf_size = 512;
unsigned int rx, tx;
char buf[buf_size];
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
sys_op->rx_max_pending = XGBE_RX_DESC_CNT_MAX;
sys_op->tx_max_pending = XGBE_TX_DESC_CNT_MAX;
sys_op->rx_pending = pdata->rx_desc_count;
sys_op->tx_pending = pdata->tx_desc_count;
sbuf_printf(sb,
"\nPre-set maximums:\n"
"RX: %u\n"
"RX Mini: %u\n"
"RX Jumbo: %u\n"
"TX: %u\n",
sys_op->rx_max_pending,
sys_op->rx_mini_max_pending,
sys_op->rx_jumbo_max_pending,
sys_op->tx_max_pending);
sbuf_printf(sb,
"\nCurrent hardware settings:\n"
"RX: %u\n"
"RX Mini: %u\n"
"RX Jumbo: %u\n"
"TX: %u\n",
sys_op->rx_pending,
sys_op->rx_mini_pending,
sys_op->rx_jumbo_pending,
sys_op->tx_pending);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (0);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
parse_generic_sysctl(pdata, buf, sysctl_ringparam,
ARRAY_SIZE(sysctl_ringparam));
if (sys_op->rx_mini_pending || sys_op->rx_jumbo_pending) {
axgbe_error("unsupported ring parameter\n");
return (-EINVAL);
}
if ((sys_op->rx_pending < XGBE_RX_DESC_CNT_MIN) ||
(sys_op->rx_pending > XGBE_RX_DESC_CNT_MAX)) {
axgbe_error("rx ring param must be between %u and %u\n",
XGBE_RX_DESC_CNT_MIN, XGBE_RX_DESC_CNT_MAX);
return (-EINVAL);
}
if ((sys_op->tx_pending < XGBE_TX_DESC_CNT_MIN) ||
(sys_op->tx_pending > XGBE_TX_DESC_CNT_MAX)) {
axgbe_error("tx ring param must be between %u and %u\n",
XGBE_TX_DESC_CNT_MIN, XGBE_TX_DESC_CNT_MAX);
return (-EINVAL);
}
rx = __rounddown_pow_of_two(sys_op->rx_pending);
if (rx != sys_op->rx_pending)
axgbe_printf(1, "rx ring param rounded to power of 2: %u\n",
rx);
tx = __rounddown_pow_of_two(sys_op->tx_pending);
if (tx != sys_op->tx_pending)
axgbe_printf(1, "tx ring param rounded to power of 2: %u\n",
tx);
if ((rx == pdata->rx_desc_count) &&
(tx == pdata->tx_desc_count))
goto out;
pdata->rx_desc_count = rx;
pdata->tx_desc_count = tx;
/* TODO - restart dev */
}
out:
return (0);
}
static int
sysctl_channels_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
struct sysctl_op *sys_op = pdata->sys_op;
struct sysctl_info sysctl_channels[] = {
{ "rx", SYSL_S32, rx_count, "supported" },
{ "tx", SYSL_S32, tx_count, "supported" },
{ "other", SYSL_S32, other_count, "supported" },
{ "combined", SYSL_S32, combined_count, "supported" },
};
unsigned int rx, tx, combined;
ssize_t buf_size = 512;
char buf[buf_size];
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
rx = min(pdata->hw_feat.rx_ch_cnt, pdata->rx_max_channel_count);
rx = min(rx, pdata->channel_irq_count);
tx = min(pdata->hw_feat.tx_ch_cnt, pdata->tx_max_channel_count);
tx = min(tx, pdata->channel_irq_count);
tx = min(tx, pdata->tx_max_q_count);
combined = min(rx, tx);
sys_op->max_combined = combined;
sys_op->max_rx = rx ? rx - 1 : 0;
sys_op->max_tx = tx ? tx - 1 : 0;
/* Get current settings based on device state */
rx = pdata->rx_ring_count;
tx = pdata->tx_ring_count;
combined = min(rx, tx);
rx -= combined;
tx -= combined;
sys_op->combined_count = combined;
sys_op->rx_count = rx;
sys_op->tx_count = tx;
sbuf_printf(sb,
"\nPre-set maximums:\n"
"RX: %u\n"
"TX: %u\n"
"Other: %u\n"
"Combined: %u\n",
sys_op->max_rx, sys_op->max_tx,
sys_op->max_other,
sys_op->max_combined);
sbuf_printf(sb,
"\nCurrent hardware settings:\n"
"RX: %u\n"
"TX: %u\n"
"Other: %u\n"
"Combined: %u\n",
sys_op->rx_count, sys_op->tx_count,
sys_op->other_count,
sys_op->combined_count);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (0);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
parse_generic_sysctl(pdata, buf, sysctl_channels,
ARRAY_SIZE(sysctl_channels));
axgbe_error( "channel inputs: combined=%u, rx-only=%u,"
" tx-only=%u\n", sys_op->combined_count,
sys_op->rx_count, sys_op->tx_count);
}
return (rc);
}
static int
sysctl_mac_stats_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
struct sbuf *sb;
int rc = 0;
int i;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
pdata->hw_if.read_mmc_stats(pdata);
for (i = 0; i < XGBE_STATS_COUNT; i++) {
sbuf_printf(sb, "\n %s: %lu",
xgbe_gstring_stats[i].stat_string,
*(uint64_t *)((uint8_t *)pdata + xgbe_gstring_stats[i].stat_offset));
}
for (i = 0; i < pdata->tx_ring_count; i++) {
sbuf_printf(sb,
"\n txq_packets[%d]: %lu"
"\n txq_bytes[%d]: %lu",
i, pdata->ext_stats.txq_packets[i],
i, pdata->ext_stats.txq_bytes[i]);
}
for (i = 0; i < pdata->rx_ring_count; i++) {
sbuf_printf(sb,
"\n rxq_packets[%d]: %lu"
"\n rxq_bytes[%d]: %lu",
i, pdata->ext_stats.rxq_packets[i],
i, pdata->ext_stats.rxq_bytes[i]);
}
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
return (-EINVAL);
}
static int
sysctl_xgmac_reg_value_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
char buf[buf_size];
unsigned int value;
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
value = XGMAC_IOREAD(pdata, pdata->sysctl_xgmac_reg);
axgbe_printf(2, "READ: %s: value: 0x%x\n", __func__, value);
sbuf_printf(sb, "\nXGMAC reg_value: 0x%x\n", value);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%x", &value);
axgbe_printf(2, "WRITE: %s: value: 0x%x\n", __func__, value);
XGMAC_IOWRITE(pdata, pdata->sysctl_xgmac_reg, value);
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_xpcs_mmd_reg_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
char buf[buf_size];
struct sbuf *sb;
unsigned int reg;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
axgbe_printf(2, "READ: %s: xpcs_mmd: 0x%x\n", __func__,
pdata->sysctl_xpcs_mmd);
sbuf_printf(sb, "\nXPCS mmd_reg: 0x%x\n",
pdata->sysctl_xpcs_mmd);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%x", ®);
axgbe_printf(2, "WRITE: %s: mmd_reg: 0x%x\n", __func__, reg);
pdata->sysctl_xpcs_mmd = reg;
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_xpcs_reg_addr_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
char buf[buf_size];
struct sbuf *sb;
unsigned int reg;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
axgbe_printf(2, "READ: %s: sysctl_xpcs_reg: 0x%x\n", __func__,
pdata->sysctl_xpcs_reg);
sbuf_printf(sb, "\nXPCS reg_addr: 0x%x\n",
pdata->sysctl_xpcs_reg);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%x", ®);
axgbe_printf(2, "WRITE: %s: reg: 0x%x\n", __func__, reg);
pdata->sysctl_xpcs_reg = reg;
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_xpcs_reg_value_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
char buf[buf_size];
unsigned int value;
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
value = XMDIO_READ(pdata, pdata->sysctl_xpcs_mmd,
pdata->sysctl_xpcs_reg);
axgbe_printf(2, "READ: %s: value: 0x%x\n", __func__, value);
sbuf_printf(sb, "\nXPCS reg_value: 0x%x\n", value);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%x", &value);
axgbe_printf(2, "WRITE: %s: value: 0x%x\n", __func__, value);
XMDIO_WRITE(pdata, pdata->sysctl_xpcs_mmd,
pdata->sysctl_xpcs_reg, value);
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_xprop_reg_addr_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
char buf[buf_size];
struct sbuf *sb;
unsigned int reg;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
axgbe_printf(2, "READ: %s: sysctl_xprop_reg: 0x%x\n", __func__,
pdata->sysctl_xprop_reg);
sbuf_printf(sb, "\nXPROP reg_addr: 0x%x\n",
pdata->sysctl_xprop_reg);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%x", ®);
axgbe_printf(2, "WRITE: %s: reg: 0x%x\n", __func__, reg);
pdata->sysctl_xprop_reg = reg;
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_xprop_reg_value_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
char buf[buf_size];
unsigned int value;
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
value = XP_IOREAD(pdata, pdata->sysctl_xprop_reg);
axgbe_printf(2, "READ: %s: value: 0x%x\n", __func__, value);
sbuf_printf(sb, "\nXPROP reg_value: 0x%x\n", value);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%x", &value);
axgbe_printf(2, "WRITE: %s: value: 0x%x\n", __func__, value);
XP_IOWRITE(pdata, pdata->sysctl_xprop_reg, value);
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_xi2c_reg_addr_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
char buf[buf_size];
struct sbuf *sb;
unsigned int reg;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
axgbe_printf(2, "READ: %s: sysctl_xi2c_reg: 0x%x\n", __func__,
pdata->sysctl_xi2c_reg);
sbuf_printf(sb, "\nXI2C reg_addr: 0x%x\n",
pdata->sysctl_xi2c_reg);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%x", ®);
axgbe_printf(2, "WRITE: %s: reg: 0x%x\n", __func__, reg);
pdata->sysctl_xi2c_reg = reg;
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_xi2c_reg_value_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
ssize_t buf_size = 64;
char buf[buf_size];
unsigned int value;
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
value = XI2C_IOREAD(pdata, pdata->sysctl_xi2c_reg);
axgbe_printf(2, "READ: %s: value: 0x%x\n", __func__, value);
sbuf_printf(sb, "\nXI2C reg_value: 0x%x\n", value);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%x", &value);
axgbe_printf(2, "WRITE: %s: value: 0x%x\n", __func__, value);
XI2C_IOWRITE(pdata, pdata->sysctl_xi2c_reg, value);
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_an_cdr_wr_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
unsigned int an_cdr_wr = 0;
ssize_t buf_size = 64;
char buf[buf_size];
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
axgbe_printf(2, "READ: %s: an_cdr_wr: %d\n", __func__,
pdata->sysctl_an_cdr_workaround);
sbuf_printf(sb, "%d\n", pdata->sysctl_an_cdr_workaround);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%u", &an_cdr_wr);
axgbe_printf(2, "WRITE: %s: an_cdr_wr: 0x%d\n", __func__,
an_cdr_wr);
if (an_cdr_wr)
pdata->sysctl_an_cdr_workaround = 1;
else
pdata->sysctl_an_cdr_workaround = 0;
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
static int
sysctl_an_cdr_track_early_handler(SYSCTL_HANDLER_ARGS)
{
struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)arg1;
unsigned int an_cdr_track_early = 0;
ssize_t buf_size = 64;
char buf[buf_size];
struct sbuf *sb;
int rc = 0;
if (req->newptr == NULL) {
sb = sbuf_new_for_sysctl(NULL, NULL, buf_size, req);
if (sb == NULL) {
rc = sb->s_error;
return (rc);
}
axgbe_printf(2, "READ: %s: an_cdr_track_early %d\n", __func__,
pdata->sysctl_an_cdr_track_early);
sbuf_printf(sb, "%d\n", pdata->sysctl_an_cdr_track_early);
rc = sbuf_finish(sb);
sbuf_delete(sb);
return (rc);
}
rc = get_ubuf(req, buf);
if (rc == 0) {
sscanf(buf, "%u", &an_cdr_track_early);
axgbe_printf(2, "WRITE: %s: an_cdr_track_early: %d\n", __func__,
an_cdr_track_early);
if (an_cdr_track_early)
pdata->sysctl_an_cdr_track_early = 1;
else
pdata->sysctl_an_cdr_track_early = 0;
}
axgbe_printf(2, "%s: rc= %d\n", __func__, rc);
return (rc);
}
void
axgbe_sysctl_exit(struct xgbe_prv_data *pdata)
{
if (pdata->sys_op)
free(pdata->sys_op, M_AXGBE);
}
void
axgbe_sysctl_init(struct xgbe_prv_data *pdata)
{
struct sysctl_ctx_list *clist;
struct sysctl_oid_list *top;
struct sysctl_oid *parent;
struct sysctl_op *sys_op;
sys_op = malloc(sizeof(*sys_op), M_AXGBE, M_WAITOK | M_ZERO);
pdata->sys_op = sys_op;
clist = device_get_sysctl_ctx(pdata->dev);
parent = device_get_sysctl_tree(pdata->dev);
top = SYSCTL_CHILDREN(parent);
/* Set defaults */
pdata->sysctl_xgmac_reg = 0;
pdata->sysctl_xpcs_mmd = 1;
pdata->sysctl_xpcs_reg = 0;
SYSCTL_ADD_UINT(clist, top, OID_AUTO, "axgbe_debug_level", CTLFLAG_RWTUN,
&pdata->debug_level, 0, "axgbe log level -- higher is verbose");
SYSCTL_ADD_UINT(clist, top, OID_AUTO, "sph_enable",
CTLFLAG_RDTUN, &pdata->sph_enable, 1,
"shows the split header feature state (1 - enable, 0 - disable");
+ SYSCTL_ADD_UINT(clist, top, OID_AUTO, "link_workaround",
+ CTLFLAG_RWTUN, &pdata->link_workaround, 0,
+ "enable the workaround for link issue in coming up");
+
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "xgmac_register",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_xgmac_reg_addr_handler, "IU",
"xgmac register addr");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "xgmac_register_value",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_xgmac_reg_value_handler, "IU",
"xgmac register value");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "xpcs_mmd",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_xpcs_mmd_reg_handler, "IU", "xpcs mmd register");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "xpcs_register",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_xpcs_reg_addr_handler, "IU", "xpcs register");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "xpcs_register_value",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_xpcs_reg_value_handler, "IU",
"xpcs register value");
if (pdata->xpcs_res) {
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "xprop_register",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_xprop_reg_addr_handler,
"IU", "xprop register");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "xprop_register_value",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_xprop_reg_value_handler,
"IU", "xprop register value");
}
if (pdata->xpcs_res) {
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "xi2c_register",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_xi2c_reg_addr_handler,
"IU", "xi2c register");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "xi2c_register_value",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_xi2c_reg_value_handler,
"IU", "xi2c register value");
}
if (pdata->vdata->an_cdr_workaround) {
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "an_cdr_workaround",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_an_cdr_wr_handler, "IU",
"an cdr workaround");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "an_cdr_track_early",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_an_cdr_track_early_handler, "IU",
"an cdr track early");
}
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "drv_info",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_get_drv_info_handler, "IU",
"xgbe drv info");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "link_info",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_get_link_info_handler, "IU",
"xgbe link info");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "coalesce_info",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_coalesce_handler, "IU",
"xgbe coalesce info");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "pauseparam_info",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_pauseparam_handler, "IU",
"xgbe pauseparam info");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "link_ksettings_info",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_link_ksettings_handler, "IU",
"xgbe link_ksettings info");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "ringparam_info",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_ringparam_handler, "IU",
"xgbe ringparam info");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "channels_info",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_channels_handler, "IU",
"xgbe channels info");
SYSCTL_ADD_PROC(clist, top, OID_AUTO, "mac_stats",
CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
pdata, 0, sysctl_mac_stats_handler, "IU",
"xgbe mac stats");
}
diff --git a/sys/dev/axgbe/xgbe.h b/sys/dev/axgbe/xgbe.h
index 766c0c6f551a..85b4c0c5c5d0 100644
--- a/sys/dev/axgbe/xgbe.h
+++ b/sys/dev/axgbe/xgbe.h
@@ -1,1363 +1,1364 @@
/*
* AMD 10Gb Ethernet driver
*
* Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
*
* This file is available to you under your choice of the following two
* licenses:
*
* License 1: GPLv2
*
* This file is free software; you may copy, redistribute and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or (at
* your option) any later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*
* This file incorporates work covered by the following copyright and
* permission notice:
* The Synopsys DWC ETHER XGMAC Software Driver and documentation
* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
* Inc. unless otherwise expressly agreed to in writing between Synopsys
* and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product
* under any End User Software License Agreement or Agreement for Licensed
* Product with Synopsys or any supplement thereto. Permission is hereby
* granted, free of charge, to any person obtaining a copy of this software
* annotated with this license and the Software, to deal in the Software
* without restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
*
* License 2: Modified BSD
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* The Synopsys DWC ETHER XGMAC Software Driver and documentation
* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
* Inc. unless otherwise expressly agreed to in writing between Synopsys
* and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product
* under any End User Software License Agreement or Agreement for Licensed
* Product with Synopsys or any supplement thereto. Permission is hereby
* granted, free of charge, to any person obtaining a copy of this software
* annotated with this license and the Software, to deal in the Software
* without restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef __XGBE_H__
#define __XGBE_H__
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "xgbe_osdep.h"
/* From linux/dcbnl.h */
#define IEEE_8021QAZ_MAX_TCS 8
#define XGBE_DRV_NAME "amd-xgbe"
#define XGBE_DRV_VERSION "1.0.3"
#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
/* Descriptor related defines */
#define XGBE_TX_DESC_CNT 512
#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
#define XGBE_RX_DESC_CNT 512
#define XGBE_TX_DESC_CNT_MIN 64
#define XGBE_TX_DESC_CNT_MAX 4096
#define XGBE_RX_DESC_CNT_MIN 64
#define XGBE_RX_DESC_CNT_MAX 4096
#define XGBE_TX_DESC_CNT_DEFAULT 512
#define XGBE_RX_DESC_CNT_DEFAULT 512
#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
/* Descriptors required for maximum contiguous TSO/GSO packet */
#define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
/* Maximum possible descriptors needed for an SKB:
* - Maximum number of SKB frags
* - Maximum descriptors for contiguous TSO/GSO packet
* - Possible context descriptor
* - Possible TSO header descriptor
*/
#define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
#define XGBE_RX_MIN_BUF_SIZE 1522
#define XGBE_RX_BUF_ALIGN 64
#define XGBE_SKB_ALLOC_SIZE 256
#define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZ */
#define XGBE_MAX_DMA_CHANNELS 16
#define XGBE_MAX_QUEUES 16
#define XGBE_PRIORITY_QUEUES 8
#define XGBE_DMA_STOP_TIMEOUT 5
/* DMA cache settings - Outer sharable, write-back, write-allocate */
#define XGBE_DMA_OS_ARCR 0x002b2b2b
#define XGBE_DMA_OS_AWCR 0x2f2f2f2f
/* DMA cache settings - System, no caches used */
#define XGBE_DMA_SYS_ARCR 0x00303030
#define XGBE_DMA_SYS_AWCR 0x30303030
/* DMA cache settings - PCI device */
#define XGBE_DMA_PCI_ARCR 0x00000003
#define XGBE_DMA_PCI_AWCR 0x13131313
#define XGBE_DMA_PCI_AWARCR 0x00000313
/* DMA channel interrupt modes */
#define XGBE_IRQ_MODE_EDGE 0
#define XGBE_IRQ_MODE_LEVEL 1
#define XGMAC_MIN_PACKET 60
#define XGMAC_STD_PACKET_MTU 1500
#define XGMAC_MAX_STD_PACKET 1518
#define XGMAC_JUMBO_PACKET_MTU 9000
#define XGMAC_MAX_JUMBO_PACKET 9018
#define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */
#define XGMAC_PFC_DATA_LEN 46
#define XGMAC_PFC_DELAYS 14000
#define XGMAC_PRIO_QUEUES(_cnt) \
min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt))
/* Common property names */
#define XGBE_MAC_ADDR_PROPERTY "mac-address"
#define XGBE_PHY_MODE_PROPERTY "phy-mode"
#define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
#define XGBE_SPEEDSET_PROPERTY "amd,speed-set"
#define XGBE_BLWC_PROPERTY "amd,serdes-blwc"
#define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
#define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
#define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp"
#define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config"
#define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable"
/* Device-tree clock names */
#define XGBE_DMA_CLOCK "dma_clk"
#define XGBE_PTP_CLOCK "ptp_clk"
/* ACPI property names */
#define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
#define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
/* PCI BAR mapping */
#define XGBE_XGMAC_BAR 0
#define XGBE_XPCS_BAR 1
#define XGBE_MAC_PROP_OFFSET 0x1d000
#define XGBE_I2C_CTRL_OFFSET 0x1e000
/* PCI MSI/MSIx support */
#define XGBE_MSI_BASE_COUNT 4
#define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1)
/* PCI clock frequencies */
#define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */
#define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */
/* Timestamp support - values based on 50MHz PTP clock
* 50MHz => 20 nsec
*/
#define XGBE_TSTAMP_SSINC 20
#define XGBE_TSTAMP_SNSINC 0
/* Driver PMT macros */
#define XGMAC_DRIVER_CONTEXT 1
#define XGMAC_IOCTL_CONTEXT 2
#define XGMAC_FIFO_MIN_ALLOC 2048
#define XGMAC_FIFO_UNIT 256
#define XGMAC_FIFO_ALIGN(_x) \
(((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
#define XGMAC_FIFO_FC_OFF 2048
#define XGMAC_FIFO_FC_MIN 4096
#define XGBE_FIFO_MAX 81920
#define XGBE_TC_MIN_QUANTUM 10
/* Helper macro for descriptor handling
* Always use XGBE_GET_DESC_DATA to access the descriptor data
* since the index is free-running and needs to be and-ed
* with the descriptor count value of the ring to index to
* the proper descriptor data.
*/
#define XGBE_GET_DESC_DATA(_ring, _idx) \
((_ring)->rdata + \
((_idx) & ((_ring)->rdesc_count - 1)))
/* Default coalescing parameters */
#define XGMAC_INIT_DMA_TX_USECS 1000
#define XGMAC_INIT_DMA_TX_FRAMES 25
#define XGMAC_MAX_DMA_RIWT 0xff
#define XGMAC_INIT_DMA_RX_USECS 30
#define XGMAC_INIT_DMA_RX_FRAMES 25
/* Flow control queue count */
#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
/* Flow control threshold units */
#define XGMAC_FLOW_CONTROL_UNIT 512
#define XGMAC_FLOW_CONTROL_ALIGN(_x) \
(((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1))
#define XGMAC_FLOW_CONTROL_VALUE(_x) \
(((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2)
#define XGMAC_FLOW_CONTROL_MAX 33280
/* Maximum MAC address hash table size (256 bits = 8 bytes) */
#define XGBE_MAC_HASH_TABLE_SIZE 8
/* Receive Side Scaling */
#define XGBE_RSS_HASH_KEY_SIZE 40
#define XGBE_RSS_MAX_TABLE_SIZE 256
#define XGBE_RSS_LOOKUP_TABLE_TYPE 0
#define XGBE_RSS_HASH_KEY_TYPE 1
/* Auto-negotiation */
#define XGBE_AN_MS_TIMEOUT 500
#define XGBE_LINK_TIMEOUT 10
#define XGBE_SGMII_AN_LINK_STATUS BIT(1)
#define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
#define XGBE_SGMII_AN_LINK_SPEED_100 0x04
#define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
#define XGBE_SGMII_AN_LINK_DUPLEX BIT(4)
/* ECC correctable error notification window (seconds) */
#define XGBE_ECC_LIMIT 60
#define XGBE_AN_INT_CMPLT 0x01
#define XGBE_AN_INC_LINK 0x02
#define XGBE_AN_PG_RCV 0x04
#define XGBE_AN_INT_MASK 0x07
#define XGBE_SGMII_AN_LINK_STATUS BIT(1)
#define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
#define XGBE_SGMII_AN_LINK_SPEED_100 0x04
#define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
#define XGBE_SGMII_AN_LINK_DUPLEX BIT(4)
/* Rate-change complete wait/retry count */
#define XGBE_RATECHANGE_COUNT 500
/* Default SerDes settings */
#define XGBE_SPEED_10000_BLWC 0
#define XGBE_SPEED_10000_CDR 0x7
#define XGBE_SPEED_10000_PLL 0x1
#define XGBE_SPEED_10000_PQ 0x12
#define XGBE_SPEED_10000_RATE 0x0
#define XGBE_SPEED_10000_TXAMP 0xa
#define XGBE_SPEED_10000_WORD 0x7
#define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1
#define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f
#define XGBE_SPEED_2500_BLWC 1
#define XGBE_SPEED_2500_CDR 0x2
#define XGBE_SPEED_2500_PLL 0x0
#define XGBE_SPEED_2500_PQ 0xa
#define XGBE_SPEED_2500_RATE 0x1
#define XGBE_SPEED_2500_TXAMP 0xf
#define XGBE_SPEED_2500_WORD 0x1
#define XGBE_SPEED_2500_DFE_TAP_CONFIG 0x3
#define XGBE_SPEED_2500_DFE_TAP_ENABLE 0x0
#define XGBE_SPEED_1000_BLWC 1
#define XGBE_SPEED_1000_CDR 0x2
#define XGBE_SPEED_1000_PLL 0x0
#define XGBE_SPEED_1000_PQ 0xa
#define XGBE_SPEED_1000_RATE 0x3
#define XGBE_SPEED_1000_TXAMP 0xf
#define XGBE_SPEED_1000_WORD 0x1
#define XGBE_SPEED_1000_DFE_TAP_CONFIG 0x3
#define XGBE_SPEED_1000_DFE_TAP_ENABLE 0x0
/* TSO related macros */
#define XGBE_TSO_MAX_SIZE UINT16_MAX
/* MDIO port types */
#define XGMAC_MAX_C22_PORT 3
/* Link mode bit operations */
#define XGBE_ZERO_SUP(_phy) \
((_phy)->supported = 0)
#define XGBE_SET_SUP(_phy, _mode) \
((_phy)->supported |= SUPPORTED_##_mode)
#define XGBE_CLR_SUP(_phy, _mode) \
((_phy)->supported &= ~SUPPORTED_##_mode)
#define XGBE_IS_SUP(_phy, _mode) \
((_phy)->supported & SUPPORTED_##_mode)
#define XGBE_ZERO_ADV(_phy) \
((_phy)->advertising = 0)
#define XGBE_SET_ADV(_phy, _mode) \
((_phy)->advertising |= ADVERTISED_##_mode)
#define XGBE_CLR_ADV(_phy, _mode) \
((_phy)->advertising &= ~ADVERTISED_##_mode)
#define XGBE_ADV(_phy, _mode) \
((_phy)->advertising & ADVERTISED_##_mode)
#define XGBE_ZERO_LP_ADV(_phy) \
((_phy)->lp_advertising = 0)
#define XGBE_SET_LP_ADV(_phy, _mode) \
((_phy)->lp_advertising |= ADVERTISED_##_mode)
#define XGBE_CLR_LP_ADV(_phy, _mode) \
((_phy)->lp_advertising &= ~ADVERTISED_##_mode)
#define XGBE_LP_ADV(_phy, _mode) \
((_phy)->lp_advertising & ADVERTISED_##_mode)
#define XGBE_LM_COPY(_dphy, _dname, _sphy, _sname) \
((_dphy)->_dname = (_sphy)->_sname)
struct xgbe_prv_data;
struct xgbe_packet_data {
struct mbuf *m;
unsigned int attributes;
unsigned int errors;
unsigned int rdesc_count;
unsigned int length;
unsigned int header_len;
unsigned int tcp_header_len;
unsigned int tcp_payload_len;
unsigned short mss;
unsigned short vlan_ctag;
uint64_t rx_tstamp;
unsigned int tx_packets;
unsigned int tx_bytes;
uint32_t rss_hash;
uint32_t rss_hash_type;
};
/* Common Rx and Tx descriptor mapping */
struct xgbe_ring_desc {
__le32 desc0;
__le32 desc1;
__le32 desc2;
__le32 desc3;
};
/* Tx-related ring data */
struct xgbe_tx_ring_data {
unsigned int packets; /* BQL packet count */
unsigned int bytes; /* BQL byte count */
};
/* Rx-related ring data */
struct xgbe_rx_ring_data {
unsigned short hdr_len; /* Length of received header */
unsigned short len; /* Length of received packet */
};
/* Structure used to hold information related to the descriptor
* and the packet associated with the descriptor (always use
* use the XGBE_GET_DESC_DATA macro to access this data from the ring)
*/
struct xgbe_ring_data {
struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
bus_addr_t rdata_paddr;
struct xgbe_tx_ring_data tx; /* Tx-related data */
struct xgbe_rx_ring_data rx; /* Rx-related data */
/* Incomplete receive save location. If the budget is exhausted
* or the last descriptor (last normal descriptor or a following
* context descriptor) has not been DMA'd yet the current state
* of the receive processing needs to be saved.
*/
unsigned int state_saved;
struct {
struct mbuf *m;
unsigned int len;
unsigned int error;
} state;
};
struct xgbe_ring {
/* Ring lock - used just for TX rings at the moment */
spinlock_t lock;
/* Per packet related information */
struct xgbe_packet_data packet_data;
/* Virtual/DMA addresses and count of allocated descriptor memory */
struct xgbe_ring_desc *rdesc;
bus_addr_t rdesc_paddr;
unsigned int rdesc_count;
/* Array of descriptor data corresponding the descriptor memory
* (always use the XGBE_GET_DESC_DATA macro to access this data)
*/
struct xgbe_ring_data *rdata;
/* Ring index values
* cur - Tx: index of descriptor to be used for current transfer
* Rx: index of descriptor to check for packet availability
* dirty - Tx: index of descriptor to check for transfer complete
* Rx: index of descriptor to check for buffer reallocation
*/
unsigned int cur;
unsigned int dirty;
/* Coalesce frame count used for interrupt bit setting */
unsigned int coalesce_count;
union {
struct {
unsigned int queue_stopped;
unsigned int xmit_more;
unsigned short cur_mss;
unsigned short cur_vlan_ctag;
} tx;
};
uint16_t prev_pidx;
uint8_t prev_count;
} __aligned(CACHE_LINE_SIZE);
/* Structure used to describe the descriptor rings associated with
* a DMA channel.
*/
struct xgbe_channel {
char name[16];
/* Address of private data area for device */
struct xgbe_prv_data *pdata;
/* Queue index and base address of queue's DMA registers */
unsigned int queue_index;
bus_space_tag_t dma_tag;
bus_space_handle_t dma_handle;
int dma_irq_rid;
/* Per channel interrupt irq number */
struct resource *dma_irq_res;
void *dma_irq_tag;
/* Per channel interrupt enablement tracker */
unsigned int curr_ier;
unsigned int saved_ier;
struct xgbe_ring *tx_ring;
struct xgbe_ring *rx_ring;
} __aligned(CACHE_LINE_SIZE);
enum xgbe_state {
XGBE_DOWN,
XGBE_LINK_INIT,
XGBE_LINK_ERR,
XGBE_STOPPED,
};
enum xgbe_int {
XGMAC_INT_DMA_CH_SR_TI,
XGMAC_INT_DMA_CH_SR_TPS,
XGMAC_INT_DMA_CH_SR_TBU,
XGMAC_INT_DMA_CH_SR_RI,
XGMAC_INT_DMA_CH_SR_RBU,
XGMAC_INT_DMA_CH_SR_RPS,
XGMAC_INT_DMA_CH_SR_TI_RI,
XGMAC_INT_DMA_CH_SR_FBE,
XGMAC_INT_DMA_ALL,
};
enum xgbe_int_state {
XGMAC_INT_STATE_SAVE,
XGMAC_INT_STATE_RESTORE,
};
enum xgbe_ecc_sec {
XGBE_ECC_SEC_TX,
XGBE_ECC_SEC_RX,
XGBE_ECC_SEC_DESC,
};
enum xgbe_speed {
XGBE_SPEED_1000 = 0,
XGBE_SPEED_2500,
XGBE_SPEED_10000,
XGBE_SPEEDS,
};
enum xgbe_xpcs_access {
XGBE_XPCS_ACCESS_V1 = 0,
XGBE_XPCS_ACCESS_V2,
};
enum xgbe_an_mode {
XGBE_AN_MODE_CL73 = 0,
XGBE_AN_MODE_CL73_REDRV,
XGBE_AN_MODE_CL37,
XGBE_AN_MODE_CL37_SGMII,
XGBE_AN_MODE_NONE,
};
enum xgbe_an {
XGBE_AN_READY = 0,
XGBE_AN_PAGE_RECEIVED,
XGBE_AN_INCOMPAT_LINK,
XGBE_AN_COMPLETE,
XGBE_AN_NO_LINK,
XGBE_AN_ERROR,
};
enum xgbe_rx {
XGBE_RX_BPA = 0,
XGBE_RX_XNP,
XGBE_RX_COMPLETE,
XGBE_RX_ERROR,
};
enum xgbe_mode {
XGBE_MODE_KR = 0,
XGBE_MODE_KX,
XGBE_MODE_KX_1000,
XGBE_MODE_KX_2500,
XGBE_MODE_X,
XGBE_MODE_SGMII_100,
XGBE_MODE_SGMII_1000,
XGBE_MODE_SFI,
XGBE_MODE_UNKNOWN,
};
enum xgbe_speedset {
XGBE_SPEEDSET_1000_10000 = 0,
XGBE_SPEEDSET_2500_10000,
};
enum xgbe_mdio_mode {
XGBE_MDIO_MODE_NONE = 0,
XGBE_MDIO_MODE_CL22,
XGBE_MDIO_MODE_CL45,
};
struct xgbe_phy {
uint32_t supported;
uint32_t advertising;
uint32_t lp_advertising;
int address;
int autoneg;
int speed;
int duplex;
int link;
int pause_autoneg;
int tx_pause;
int rx_pause;
int pause;
int asym_pause;
};
enum xgbe_i2c_cmd {
XGBE_I2C_CMD_READ = 0,
XGBE_I2C_CMD_WRITE,
};
struct xgbe_i2c_op {
enum xgbe_i2c_cmd cmd;
unsigned int target;
void *buf;
unsigned int len;
};
struct xgbe_i2c_op_state {
struct xgbe_i2c_op *op;
unsigned int tx_len;
unsigned char *tx_buf;
unsigned int rx_len;
unsigned char *rx_buf;
unsigned int tx_abort_source;
int ret;
};
struct xgbe_i2c {
unsigned int started;
unsigned int max_speed_mode;
unsigned int rx_fifo_size;
unsigned int tx_fifo_size;
struct xgbe_i2c_op_state op_state;
};
struct xgbe_mmc_stats {
/* Tx Stats */
uint64_t txoctetcount_gb;
uint64_t txframecount_gb;
uint64_t txbroadcastframes_g;
uint64_t txmulticastframes_g;
uint64_t tx64octets_gb;
uint64_t tx65to127octets_gb;
uint64_t tx128to255octets_gb;
uint64_t tx256to511octets_gb;
uint64_t tx512to1023octets_gb;
uint64_t tx1024tomaxoctets_gb;
uint64_t txunicastframes_gb;
uint64_t txmulticastframes_gb;
uint64_t txbroadcastframes_gb;
uint64_t txunderflowerror;
uint64_t txoctetcount_g;
uint64_t txframecount_g;
uint64_t txpauseframes;
uint64_t txvlanframes_g;
/* Rx Stats */
uint64_t rxframecount_gb;
uint64_t rxoctetcount_gb;
uint64_t rxoctetcount_g;
uint64_t rxbroadcastframes_g;
uint64_t rxmulticastframes_g;
uint64_t rxcrcerror;
uint64_t rxrunterror;
uint64_t rxjabbererror;
uint64_t rxundersize_g;
uint64_t rxoversize_g;
uint64_t rx64octets_gb;
uint64_t rx65to127octets_gb;
uint64_t rx128to255octets_gb;
uint64_t rx256to511octets_gb;
uint64_t rx512to1023octets_gb;
uint64_t rx1024tomaxoctets_gb;
uint64_t rxunicastframes_g;
uint64_t rxlengtherror;
uint64_t rxoutofrangetype;
uint64_t rxpauseframes;
uint64_t rxfifooverflow;
uint64_t rxvlanframes_gb;
uint64_t rxwatchdogerror;
};
struct xgbe_ext_stats {
uint64_t tx_tso_packets;
uint64_t rx_split_header_packets;
uint64_t rx_buffer_unavailable;
uint64_t txq_packets[XGBE_MAX_DMA_CHANNELS];
uint64_t txq_bytes[XGBE_MAX_DMA_CHANNELS];
uint64_t rxq_packets[XGBE_MAX_DMA_CHANNELS];
uint64_t rxq_bytes[XGBE_MAX_DMA_CHANNELS];
uint64_t tx_vxlan_packets;
uint64_t rx_vxlan_packets;
uint64_t rx_csum_errors;
uint64_t rx_vxlan_csum_errors;
};
struct xgbe_hw_if {
int (*tx_complete)(struct xgbe_ring_desc *);
int (*set_mac_address)(struct xgbe_prv_data *, uint8_t *addr);
int (*config_rx_mode)(struct xgbe_prv_data *);
int (*enable_rx_csum)(struct xgbe_prv_data *);
int (*disable_rx_csum)(struct xgbe_prv_data *);
int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
int (*update_vlan_hash_table)(struct xgbe_prv_data *);
int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
int (*set_speed)(struct xgbe_prv_data *, int);
int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int,
enum xgbe_mdio_mode);
int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int);
int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, uint16_t);
int (*set_gpio)(struct xgbe_prv_data *, unsigned int);
int (*clr_gpio)(struct xgbe_prv_data *, unsigned int);
void (*enable_tx)(struct xgbe_prv_data *);
void (*disable_tx)(struct xgbe_prv_data *);
void (*enable_rx)(struct xgbe_prv_data *);
void (*disable_rx)(struct xgbe_prv_data *);
void (*powerup_tx)(struct xgbe_prv_data *);
void (*powerdown_tx)(struct xgbe_prv_data *);
void (*powerup_rx)(struct xgbe_prv_data *);
void (*powerdown_rx)(struct xgbe_prv_data *);
int (*init)(struct xgbe_prv_data *);
int (*exit)(struct xgbe_prv_data *);
int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
int (*dev_read)(struct xgbe_channel *);
void (*tx_desc_init)(struct xgbe_channel *);
void (*rx_desc_init)(struct xgbe_channel *);
void (*tx_desc_reset)(struct xgbe_ring_data *);
int (*is_last_desc)(struct xgbe_ring_desc *);
int (*is_context_desc)(struct xgbe_ring_desc *);
/* For FLOW ctrl */
int (*config_tx_flow_control)(struct xgbe_prv_data *);
int (*config_rx_flow_control)(struct xgbe_prv_data *);
/* For RX coalescing */
int (*config_rx_coalesce)(struct xgbe_prv_data *);
int (*config_tx_coalesce)(struct xgbe_prv_data *);
unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
/* For RX and TX threshold config */
int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
/* For RX and TX Store and Forward Mode config */
int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
/* For TX DMA Operate on Second Frame config */
int (*config_osp_mode)(struct xgbe_prv_data *);
/* For MMC statistics */
void (*rx_mmc_int)(struct xgbe_prv_data *);
void (*tx_mmc_int)(struct xgbe_prv_data *);
void (*read_mmc_stats)(struct xgbe_prv_data *);
/* For Receive Side Scaling */
int (*enable_rss)(struct xgbe_prv_data *);
int (*disable_rss)(struct xgbe_prv_data *);
int (*set_rss_hash_key)(struct xgbe_prv_data *, const uint8_t *);
int (*set_rss_lookup_table)(struct xgbe_prv_data *, const uint32_t *);
};
/* This structure represents implementation specific routines for an
* implementation of a PHY. All routines are required unless noted below.
* Optional routines:
* an_pre, an_post
* kr_training_pre, kr_training_post
* module_info, module_eeprom
*/
struct xgbe_phy_impl_if {
/* Perform Setup/teardown actions */
int (*init)(struct xgbe_prv_data *);
void (*exit)(struct xgbe_prv_data *);
/* Perform start/stop specific actions */
int (*reset)(struct xgbe_prv_data *);
int (*start)(struct xgbe_prv_data *);
void (*stop)(struct xgbe_prv_data *);
/* Return the link status */
int (*link_status)(struct xgbe_prv_data *, int *);
/* Indicate if a particular speed is valid */
bool (*valid_speed)(struct xgbe_prv_data *, int);
/* Check if the specified mode can/should be used */
bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode);
/* Switch the PHY into various modes */
void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode);
/* Retrieve mode needed for a specific speed */
enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int);
/* Retrieve new/next mode when trying to auto-negotiate */
enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *);
/* Retrieve current mode */
enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *);
/* Retrieve interface sub-type */
void (*get_type)(struct xgbe_prv_data *, struct ifmediareq *);
/* Retrieve current auto-negotiation mode */
enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
/* Configure auto-negotiation settings */
int (*an_config)(struct xgbe_prv_data *);
/* Set/override auto-negotiation advertisement settings */
void (*an_advertising)(struct xgbe_prv_data *,
struct xgbe_phy *);
/* Process results of auto-negotiation */
enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
/* Pre/Post auto-negotiation support */
void (*an_pre)(struct xgbe_prv_data *);
void (*an_post)(struct xgbe_prv_data *);
/* Pre/Post KR training enablement support */
void (*kr_training_pre)(struct xgbe_prv_data *);
void (*kr_training_post)(struct xgbe_prv_data *);
/* SFP module related info */
int (*module_info)(struct xgbe_prv_data *pdata);
int (*module_eeprom)(struct xgbe_prv_data *pdata);
};
struct xgbe_phy_if {
/* For PHY setup/teardown */
int (*phy_init)(struct xgbe_prv_data *);
void (*phy_exit)(struct xgbe_prv_data *);
/* For PHY support when setting device up/down */
int (*phy_reset)(struct xgbe_prv_data *);
int (*phy_start)(struct xgbe_prv_data *);
void (*phy_stop)(struct xgbe_prv_data *);
/* For PHY support while device is up */
void (*phy_status)(struct xgbe_prv_data *);
int (*phy_config_aneg)(struct xgbe_prv_data *);
/* For PHY settings validation */
bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
/* For single interrupt support */
void (*an_isr)(struct xgbe_prv_data *);
/* PHY implementation specific services */
struct xgbe_phy_impl_if phy_impl;
};
struct xgbe_i2c_if {
/* For initial I2C setup */
int (*i2c_init)(struct xgbe_prv_data *);
/* For I2C support when setting device up/down */
int (*i2c_start)(struct xgbe_prv_data *);
void (*i2c_stop)(struct xgbe_prv_data *);
/* For performing I2C operations */
int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);
/* For single interrupt support */
void (*i2c_isr)(struct xgbe_prv_data *);
};
struct xgbe_desc_if {
int (*alloc_ring_resources)(struct xgbe_prv_data *);
void (*free_ring_resources)(struct xgbe_prv_data *);
int (*map_tx_skb)(struct xgbe_channel *, struct mbuf *);
int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
struct xgbe_ring_data *);
void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
};
/* This structure contains flags that indicate what hardware features
* or configurations are present in the device.
*/
struct xgbe_hw_features {
/* HW Version */
unsigned int version;
/* HW Feature Register0 */
unsigned int gmii; /* 1000 Mbps support */
unsigned int vlhash; /* VLAN Hash Filter */
unsigned int sma; /* SMA(MDIO) Interface */
unsigned int rwk; /* PMT remote wake-up packet */
unsigned int mgk; /* PMT magic packet */
unsigned int mmc; /* RMON module */
unsigned int aoe; /* ARP Offload */
unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
unsigned int eee; /* Energy Efficient Ethernet */
unsigned int tx_coe; /* Tx Checksum Offload */
unsigned int rx_coe; /* Rx Checksum Offload */
unsigned int addn_mac; /* Additional MAC Addresses */
unsigned int ts_src; /* Timestamp Source */
unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
unsigned int vxn; /* VXLAN/NVGRE */
/* HW Feature Register1 */
unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
unsigned int adv_ts_hi; /* Advance Timestamping High Word */
unsigned int dma_width; /* DMA width */
unsigned int dcb; /* DCB Feature */
unsigned int sph; /* Split Header Feature */
unsigned int tso; /* TCP Segmentation Offload */
unsigned int dma_debug; /* DMA Debug Registers */
unsigned int rss; /* Receive Side Scaling */
unsigned int tc_cnt; /* Number of Traffic Classes */
unsigned int hash_table_size; /* Hash Table Size */
unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
/* HW Feature Register2 */
unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
unsigned int pps_out_num; /* Number of PPS outputs */
unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
};
struct xgbe_version_data {
void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
enum xgbe_xpcs_access xpcs_access;
unsigned int mmc_64bit;
unsigned int tx_max_fifo_size;
unsigned int rx_max_fifo_size;
unsigned int tx_tstamp_workaround;
unsigned int ecc_support;
unsigned int i2c_support;
unsigned int irq_reissue_support;
unsigned int tx_desc_prefetch;
unsigned int rx_desc_prefetch;
unsigned int an_cdr_workaround;
};
struct xgbe_prv_data {
struct ifnet *netdev;
struct platform_device *pdev;
struct acpi_device *adev;
device_t dev;
/* Version related data */
struct xgbe_version_data *vdata;
/* ACPI or DT flag */
unsigned int use_acpi;
/* XGMAC/XPCS related mmio registers */
struct resource *xgmac_res; /* XGMAC CSRs */
struct resource *xpcs_res; /* XPCS MMD registers */
struct resource *rxtx_res; /* SerDes Rx/Tx CSRs */
struct resource *sir0_res; /* SerDes integration registers (1/2) */
struct resource *sir1_res; /* SerDes integration registers (2/2) */
/* Port property registers */
unsigned int pp0;
unsigned int pp1;
unsigned int pp2;
unsigned int pp3;
unsigned int pp4;
/* DMA tag */
bus_dma_tag_t dmat;
/* XPCS indirect addressing lock */
spinlock_t xpcs_lock;
unsigned int xpcs_window_def_reg;
unsigned int xpcs_window_sel_reg;
unsigned int xpcs_window;
unsigned int xpcs_window_size;
unsigned int xpcs_window_mask;
/* RSS addressing mutex */
struct mtx rss_mutex;
/* Flags representing xgbe_state */
unsigned long dev_state;
/* ECC support */
unsigned long tx_sec_period;
unsigned long tx_ded_period;
unsigned long rx_sec_period;
unsigned long rx_ded_period;
unsigned long desc_sec_period;
unsigned long desc_ded_period;
unsigned int tx_sec_count;
unsigned int tx_ded_count;
unsigned int rx_sec_count;
unsigned int rx_ded_count;
unsigned int desc_ded_count;
unsigned int desc_sec_count;
struct if_irq dev_irq;
struct resource *dev_irq_res;
struct resource *ecc_irq_res;
struct resource *i2c_irq_res;
struct resource *an_irq_res;
int ecc_rid;
int i2c_rid;
int an_rid;
void *dev_irq_tag;
void *ecc_irq_tag;
void *i2c_irq_tag;
void *an_irq_tag;
struct resource *chan_irq_res[XGBE_MAX_DMA_CHANNELS];
unsigned int per_channel_irq;
unsigned int irq_count;
unsigned int channel_irq_count;
unsigned int channel_irq_mode;
char ecc_name[IFNAMSIZ + 32];
unsigned int isr_as_tasklet;
struct xgbe_hw_if hw_if;
struct xgbe_phy_if phy_if;
struct xgbe_desc_if desc_if;
struct xgbe_i2c_if i2c_if;
/* AXI DMA settings */
unsigned int coherent;
unsigned int arcr;
unsigned int awcr;
unsigned int awarcr;
/* Service routine support */
struct taskqueue *dev_workqueue;
struct task service_work;
struct callout service_timer;
struct mtx timer_mutex;
/* Rings for Tx/Rx on a DMA channel */
struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS];
unsigned int tx_max_channel_count;
unsigned int rx_max_channel_count;
unsigned int total_channel_count;
unsigned int channel_count;
unsigned int tx_ring_count;
unsigned int tx_desc_count;
unsigned int rx_ring_count;
unsigned int rx_desc_count;
unsigned int new_tx_ring_count;
unsigned int new_rx_ring_count;
unsigned int tx_max_q_count;
unsigned int rx_max_q_count;
unsigned int tx_q_count;
unsigned int rx_q_count;
/* Tx/Rx common settings */
unsigned int blen;
unsigned int pbl;
unsigned int aal;
unsigned int rd_osr_limit;
unsigned int wr_osr_limit;
/* Tx settings */
unsigned int tx_sf_mode;
unsigned int tx_threshold;
unsigned int tx_osp_mode;
unsigned int tx_max_fifo_size;
/* Rx settings */
unsigned int rx_sf_mode;
unsigned int rx_threshold;
unsigned int rx_max_fifo_size;
/* Tx coalescing settings */
unsigned int tx_usecs;
unsigned int tx_frames;
/* Rx coalescing settings */
unsigned int rx_riwt;
unsigned int rx_usecs;
unsigned int rx_frames;
/* Current Rx buffer size */
unsigned int rx_buf_size;
/* Flow control settings */
unsigned int pause_autoneg;
unsigned int tx_pause;
unsigned int rx_pause;
unsigned int rx_rfa[XGBE_MAX_QUEUES];
unsigned int rx_rfd[XGBE_MAX_QUEUES];
/* Receive Side Scaling settings */
uint8_t rss_key[XGBE_RSS_HASH_KEY_SIZE];
uint32_t rss_table[XGBE_RSS_MAX_TABLE_SIZE];
uint32_t rss_options;
unsigned int enable_rss;
/* VXLAN settings */
unsigned int vxlan_port_set;
unsigned int vxlan_offloads_set;
unsigned int vxlan_force_disable;
unsigned int vxlan_port_count;
uint16_t vxlan_port;
uint64_t vxlan_features;
/* Netdev related settings */
unsigned char mac_addr[ETH_ALEN];
uint64_t netdev_features;
struct xgbe_mmc_stats mmc_stats;
struct xgbe_ext_stats ext_stats;
/* Filtering support */
bitstr_t *active_vlans;
unsigned int num_active_vlans;
/* Device clocks */
struct clk *sysclk;
unsigned long sysclk_rate;
struct clk *ptpclk;
unsigned long ptpclk_rate;
/* DCB support */
unsigned int q2tc_map[XGBE_MAX_QUEUES];
unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
/* Hardware features of the device */
struct xgbe_hw_features hw_feat;
/* Device work structure */
struct task restart_work;
struct task stopdev_work;
/* Keeps track of power mode */
unsigned int power_down;
/* Network interface message level setting */
uint32_t msg_enable;
/* Current PHY settings */
int phy_link;
int phy_speed;
/* MDIO/PHY related settings */
unsigned int phy_started;
void *phy_data;
struct xgbe_phy phy;
int mdio_mmd;
unsigned long link_check;
struct mtx mdio_mutex;
unsigned int mdio_addr;
unsigned int kr_redrv;
char an_name[IFNAMSIZ + 32];
struct taskqueue *an_workqueue;
struct task an_irq_work;
unsigned int speed_set;
/* SerDes UEFI configurable settings.
* Switching between modes/speeds requires new values for some
* SerDes settings. The values can be supplied as device
* properties in array format. The first array entry is for
* 1GbE, second for 2.5GbE and third for 10GbE
*/
uint32_t serdes_blwc[XGBE_SPEEDS];
uint32_t serdes_cdr_rate[XGBE_SPEEDS];
uint32_t serdes_pq_skew[XGBE_SPEEDS];
uint32_t serdes_tx_amp[XGBE_SPEEDS];
uint32_t serdes_dfe_tap_cfg[XGBE_SPEEDS];
uint32_t serdes_dfe_tap_ena[XGBE_SPEEDS];
/* Auto-negotiation state machine support */
unsigned int an_int;
unsigned int an_status;
struct sx an_mutex;
enum xgbe_an an_result;
enum xgbe_an an_state;
enum xgbe_rx kr_state;
enum xgbe_rx kx_state;
struct task an_work;
unsigned int an_again;
unsigned int an_supported;
unsigned int parallel_detect;
unsigned int fec_ability;
unsigned long an_start;
enum xgbe_an_mode an_mode;
/* I2C support */
struct xgbe_i2c i2c;
struct mtx i2c_mutex;
bool i2c_complete;
unsigned int lpm_ctrl; /* CTRL1 for resume */
unsigned int an_cdr_track_early;
uint64_t features;
device_t axgbe_miibus;
unsigned int sysctl_xgmac_reg;
unsigned int sysctl_xpcs_mmd;
unsigned int sysctl_xpcs_reg;
unsigned int sysctl_xprop_reg;
unsigned int sysctl_xi2c_reg;
bool sysctl_an_cdr_workaround;
bool sysctl_an_cdr_track_early;
int pcie_bus; /* PCIe bus number */
int pcie_device; /* PCIe device/slot number */
int pcie_func; /* PCIe function number */
void *sys_op;
uint64_t use_adaptive_rx_coalesce;
uint64_t use_adaptive_tx_coalesce;
uint64_t rx_coalesce_usecs;
unsigned int debug_level;
/*
* Toggles the split header feature.
* This requires a complete restart.
*/
unsigned int sph_enable;
+ unsigned int link_workaround;
};
struct axgbe_if_softc {
struct xgbe_prv_data pdata;
if_softc_ctx_t scctx;
if_shared_ctx_t sctx;
if_ctx_t ctx;
struct ifnet *ifp;
struct ifmedia *media;
unsigned int link_status;
};
/* Function prototypes*/
void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *);
void xgbe_get_all_hw_features(struct xgbe_prv_data *);
void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
int xgbe_calc_rx_buf_size(struct ifnet *netdev, unsigned int mtu);
void axgbe_sysctl_init(struct xgbe_prv_data *pdata);
void axgbe_sysctl_exit(struct xgbe_prv_data *pdata);
int xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg,
uint16_t val);
int xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg);
void xgbe_dump_i2c_registers(struct xgbe_prv_data *);
uint32_t bitrev32(uint32_t);
/* For debug prints */
#ifdef YDEBUG
#define DBGPR(x...) device_printf(pdata->dev, x)
#else
#define DBGPR(x...) do { } while (0)
#endif
#ifdef YDEBUG_MDIO
#define DBGPR_MDIO(x...) device_printf(pdata->dev, x)
#else
#define DBGPR_MDIO(x...) do { } while (0)
#endif
#define axgbe_printf(lvl, ...) do { \
if (lvl <= pdata->debug_level) \
device_printf(pdata->dev, __VA_ARGS__); \
} while (0)
#define axgbe_error(...) do { \
device_printf(pdata->dev, __VA_ARGS__); \
} while (0)
#endif /* __XGBE_H__ */