diff --git a/sys/dev/ath/ath_hal/ah_eeprom.h b/sys/dev/ath/ath_hal/ah_eeprom.h index 2ca058982f30..b77fb6427c02 100644 --- a/sys/dev/ath/ath_hal/ah_eeprom.h +++ b/sys/dev/ath/ath_hal/ah_eeprom.h @@ -1,139 +1,140 @@ /* * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting * Copyright (c) 2002-2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _ATH_AH_EEPROM_H_ #define _ATH_AH_EEPROM_H_ #define AR_EEPROM_VER1 0x1000 /* Version 1.0; 5210 only */ /* * Version 3 EEPROMs are all 16K. * 3.1 adds turbo limit, antenna gain, 16 CTL's, 11g info, * and 2.4Ghz ob/db for B & G * 3.2 has more accurate pcdac intercepts and analog chip * calibration. * 3.3 adds ctl in-band limit, 32 ctl's, and frequency * expansion * 3.4 adds xr power, gainI, and 2.4 turbo params */ #define AR_EEPROM_VER3 0x3000 /* Version 3.0; start of 16k EEPROM */ #define AR_EEPROM_VER3_1 0x3001 /* Version 3.1 */ #define AR_EEPROM_VER3_2 0x3002 /* Version 3.2 */ #define AR_EEPROM_VER3_3 0x3003 /* Version 3.3 */ #define AR_EEPROM_VER3_4 0x3004 /* Version 3.4 */ #define AR_EEPROM_VER4 0x4000 /* Version 4.x */ #define AR_EEPROM_VER4_0 0x4000 /* Version 4.0 */ #define AR_EEPROM_VER4_1 0x4001 /* Version 4.0 */ #define AR_EEPROM_VER4_2 0x4002 /* Version 4.0 */ #define AR_EEPROM_VER4_3 0x4003 /* Version 4.0 */ #define AR_EEPROM_VER4_6 0x4006 /* Version 4.0 */ #define AR_EEPROM_VER4_7 0x3007 /* Version 4.7 */ #define AR_EEPROM_VER4_9 0x4009 /* EEPROM EAR futureproofing */ #define AR_EEPROM_VER5 0x5000 /* Version 5.x */ #define AR_EEPROM_VER5_0 0x5000 /* Adds new 2413 cal powers and added params */ #define AR_EEPROM_VER5_1 0x5001 /* Adds capability values */ #define AR_EEPROM_VER5_3 0x5003 /* Adds spur mitigation table */ #define AR_EEPROM_VER5_4 0x5004 /* * Version 14 EEPROMs came in with AR5416. * 14.2 adds txFrameToPaOn, txFrameToDataStart, ht40PowerInc * 14.3 adds bswAtten, bswMargin, swSettle, and base OpFlags for HT20/40 */ #define AR_EEPROM_VER14 0xE000 /* Version 14.x */ #define AR_EEPROM_VER14_1 0xE001 /* Adds 11n support */ #define AR_EEPROM_VER14_2 0xE002 #define AR_EEPROM_VER14_3 0xE003 #define AR_EEPROM_VER14_7 0xE007 #define AR_EEPROM_VER14_9 0xE009 #define AR_EEPROM_VER14_16 0xE010 #define AR_EEPROM_VER14_17 0xE011 #define AR_EEPROM_VER14_19 0xE013 enum { AR_EEP_RFKILL, /* use ath_hal_eepromGetFlag */ AR_EEP_AMODE, /* use ath_hal_eepromGetFlag */ AR_EEP_BMODE, /* use ath_hal_eepromGetFlag */ AR_EEP_GMODE, /* use ath_hal_eepromGetFlag */ AR_EEP_TURBO5DISABLE, /* use ath_hal_eepromGetFlag */ AR_EEP_TURBO2DISABLE, /* use ath_hal_eepromGetFlag */ AR_EEP_ISTALON, /* use ath_hal_eepromGetFlag */ AR_EEP_32KHZCRYSTAL, /* use ath_hal_eepromGetFlag */ AR_EEP_MACADDR, /* uint8_t* */ AR_EEP_COMPRESS, /* use ath_hal_eepromGetFlag */ AR_EEP_FASTFRAME, /* use ath_hal_eepromGetFlag */ AR_EEP_AES, /* use ath_hal_eepromGetFlag */ AR_EEP_BURST, /* use ath_hal_eepromGetFlag */ AR_EEP_MAXQCU, /* uint16_t* */ AR_EEP_KCENTRIES, /* uint16_t* */ AR_EEP_NFTHRESH_5, /* int16_t* */ AR_EEP_NFTHRESH_2, /* int16_t* */ AR_EEP_REGDMN_0, /* uint16_t* */ AR_EEP_REGDMN_1, /* uint16_t* */ AR_EEP_OPCAP, /* uint16_t* */ AR_EEP_OPMODE, /* uint16_t* */ AR_EEP_RFSILENT, /* uint16_t* */ AR_EEP_OB_5, /* uint8_t* */ AR_EEP_DB_5, /* uint8_t* */ AR_EEP_OB_2, /* uint8_t* */ AR_EEP_DB_2, /* uint8_t* */ AR_EEP_TXMASK, /* uint8_t* */ AR_EEP_RXMASK, /* uint8_t* */ AR_EEP_RXGAIN_TYPE, /* uint8_t* */ AR_EEP_TXGAIN_TYPE, /* uint8_t* */ AR_EEP_DAC_HPWR_5G, /* uint8_t* */ AR_EEP_OL_PWRCTRL, /* use ath_hal_eepromGetFlag */ AR_EEP_FSTCLK_5G, /* use ath_hal_eepromGetFlag */ AR_EEP_ANTGAINMAX_5, /* int8_t* */ AR_EEP_ANTGAINMAX_2, /* int8_t* */ AR_EEP_WRITEPROTECT, /* use ath_hal_eepromGetFlag */ AR_EEP_PWR_TABLE_OFFSET,/* int8_t* */ AR_EEP_PWDCLKIND, /* uint8_t* */ AR_EEP_TEMPSENSE_SLOPE, /* int8_t* */ AR_EEP_TEMPSENSE_SLOPE_PAL_ON, /* int8_t* */ + AR_EEP_FRAC_N_5G, /* uint8_t* */ }; typedef struct { uint16_t rdEdge; uint16_t twice_rdEdgePower; HAL_BOOL flag; } RD_EDGES_POWER; /* XXX should probably be version-dependent */ #define SD_NO_CTL 0xf0 #define NO_CTL 0xff #define CTL_MODE_M 0x0f #define CTL_11A 0 #define CTL_11B 1 #define CTL_11G 2 #define CTL_TURBO 3 #define CTL_108G 4 #define CTL_2GHT20 5 #define CTL_5GHT20 6 #define CTL_2GHT40 7 #define CTL_5GHT40 8 #define AR_NO_SPUR 0x8000 /* XXX exposed to chip code */ #define MAX_RATE_POWER 63 HAL_STATUS ath_hal_v1EepromAttach(struct ath_hal *ah); HAL_STATUS ath_hal_legacyEepromAttach(struct ath_hal *ah); HAL_STATUS ath_hal_v14EepromAttach(struct ath_hal *ah); HAL_STATUS ath_hal_v4kEepromAttach(struct ath_hal *ah); HAL_STATUS ath_hal_9287EepromAttach(struct ath_hal *ah); #endif /* _ATH_AH_EEPROM_H_ */ diff --git a/sys/dev/ath/ath_hal/ah_eeprom_v14.c b/sys/dev/ath/ath_hal/ah_eeprom_v14.c index fdddea10605b..37e973c16921 100644 --- a/sys/dev/ath/ath_hal/ah_eeprom_v14.c +++ b/sys/dev/ath/ath_hal/ah_eeprom_v14.c @@ -1,441 +1,447 @@ /* * Copyright (c) 2008 Sam Leffler, Errno Consulting * Copyright (c) 2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #include "opt_ah.h" #include "ah.h" #include "ah_internal.h" #include "ah_eeprom_v14.h" static HAL_STATUS v14EepromGet(struct ath_hal *ah, int param, void *val) { #define CHAN_A_IDX 0 #define CHAN_B_IDX 1 #define IS_VERS(op, v) ((pBase->version & AR5416_EEP_VER_MINOR_MASK) op (v)) HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; const MODAL_EEP_HEADER *pModal = ee->ee_base.modalHeader; const BASE_EEP_HEADER *pBase = &ee->ee_base.baseEepHeader; uint32_t sum; uint8_t *macaddr; int i; switch (param) { case AR_EEP_NFTHRESH_5: *(int16_t *)val = pModal[0].noiseFloorThreshCh[0]; return HAL_OK; case AR_EEP_NFTHRESH_2: *(int16_t *)val = pModal[1].noiseFloorThreshCh[0]; return HAL_OK; case AR_EEP_MACADDR: /* Get MAC Address */ sum = 0; macaddr = val; for (i = 0; i < 6; i++) { macaddr[i] = pBase->macAddr[i]; sum += pBase->macAddr[i]; } if (sum == 0 || sum == 0xffff*3) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n", __func__, ath_hal_ether_sprintf(macaddr)); return HAL_EEBADMAC; } return HAL_OK; case AR_EEP_REGDMN_0: return pBase->regDmn[0]; case AR_EEP_REGDMN_1: return pBase->regDmn[1]; case AR_EEP_OPCAP: return pBase->deviceCap; case AR_EEP_OPMODE: return pBase->opCapFlags; case AR_EEP_RFSILENT: return pBase->rfSilent; case AR_EEP_OB_5: return pModal[CHAN_A_IDX].ob; case AR_EEP_DB_5: return pModal[CHAN_A_IDX].db; case AR_EEP_OB_2: return pModal[CHAN_B_IDX].ob; case AR_EEP_DB_2: return pModal[CHAN_B_IDX].db; case AR_EEP_TXMASK: return pBase->txMask; case AR_EEP_RXMASK: return pBase->rxMask; case AR_EEP_RXGAIN_TYPE: return IS_VERS(>=, AR5416_EEP_MINOR_VER_17) ? pBase->rxGainType : AR5416_EEP_RXGAIN_ORIG; case AR_EEP_TXGAIN_TYPE: return IS_VERS(>=, AR5416_EEP_MINOR_VER_19) ? pBase->txGainType : AR5416_EEP_TXGAIN_ORIG; case AR_EEP_FSTCLK_5G: /* 5ghz fastclock is always enabled for Merlin minor <= 16 */ if (IS_VERS(<=, AR5416_EEP_MINOR_VER_16)) return HAL_OK; return pBase->fastClk5g ? HAL_OK : HAL_EIO; case AR_EEP_OL_PWRCTRL: HALASSERT(val == AH_NULL); return pBase->openLoopPwrCntl ? HAL_OK : HAL_EIO; case AR_EEP_DAC_HPWR_5G: if (IS_VERS(>=, AR5416_EEP_MINOR_VER_20)) { *(uint8_t *) val = pBase->dacHiPwrMode_5G; return HAL_OK; } else return HAL_EIO; + case AR_EEP_FRAC_N_5G: + if (IS_VERS(>=, AR5416_EEP_MINOR_VER_22)) { + *(uint8_t *) val = pBase->frac_n_5g; + } else + *(uint8_t *) val = 0; + return HAL_OK; case AR_EEP_AMODE: HALASSERT(val == AH_NULL); return pBase->opCapFlags & AR5416_OPFLAGS_11A ? HAL_OK : HAL_EIO; case AR_EEP_BMODE: case AR_EEP_GMODE: HALASSERT(val == AH_NULL); return pBase->opCapFlags & AR5416_OPFLAGS_11G ? HAL_OK : HAL_EIO; case AR_EEP_32KHZCRYSTAL: case AR_EEP_COMPRESS: case AR_EEP_FASTFRAME: /* XXX policy decision, h/w can do it */ case AR_EEP_WRITEPROTECT: /* NB: no write protect bit */ HALASSERT(val == AH_NULL); /* fall thru... */ case AR_EEP_MAXQCU: /* NB: not in opCapFlags */ case AR_EEP_KCENTRIES: /* NB: not in opCapFlags */ return HAL_EIO; case AR_EEP_AES: case AR_EEP_BURST: case AR_EEP_RFKILL: case AR_EEP_TURBO5DISABLE: case AR_EEP_TURBO2DISABLE: HALASSERT(val == AH_NULL); return HAL_OK; case AR_EEP_ANTGAINMAX_2: *(int8_t *) val = ee->ee_antennaGainMax[1]; return HAL_OK; case AR_EEP_ANTGAINMAX_5: *(int8_t *) val = ee->ee_antennaGainMax[0]; return HAL_OK; case AR_EEP_PWR_TABLE_OFFSET: if (IS_VERS(>=, AR5416_EEP_MINOR_VER_21)) *(int8_t *) val = pBase->pwr_table_offset; else *(int8_t *) val = AR5416_PWR_TABLE_OFFSET_DB; return HAL_OK; case AR_EEP_PWDCLKIND: if (IS_VERS(>=, AR5416_EEP_MINOR_VER_10)) { *(uint8_t *) val = pBase->pwdclkind; return HAL_OK; } return HAL_EIO; default: HALASSERT(0); return HAL_EINVAL; } #undef IS_VERS #undef CHAN_A_IDX #undef CHAN_B_IDX } static HAL_STATUS v14EepromSet(struct ath_hal *ah, int param, int v) { HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; switch (param) { case AR_EEP_ANTGAINMAX_2: ee->ee_antennaGainMax[1] = (int8_t) v; return HAL_OK; case AR_EEP_ANTGAINMAX_5: ee->ee_antennaGainMax[0] = (int8_t) v; return HAL_OK; } return HAL_EINVAL; } static HAL_BOOL v14EepromDiag(struct ath_hal *ah, int request, const void *args, uint32_t argsize, void **result, uint32_t *resultsize) { HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; switch (request) { case HAL_DIAG_EEPROM: *result = ee; *resultsize = sizeof(HAL_EEPROM_v14); return AH_TRUE; } return AH_FALSE; } /* Do structure specific swaps if Eeprom format is non native to host */ static void eepromSwap(struct ar5416eeprom *ee) { uint32_t integer, i, j; uint16_t word; MODAL_EEP_HEADER *pModal; /* convert Base Eep header */ word = __bswap16(ee->baseEepHeader.length); ee->baseEepHeader.length = word; word = __bswap16(ee->baseEepHeader.checksum); ee->baseEepHeader.checksum = word; word = __bswap16(ee->baseEepHeader.version); ee->baseEepHeader.version = word; word = __bswap16(ee->baseEepHeader.regDmn[0]); ee->baseEepHeader.regDmn[0] = word; word = __bswap16(ee->baseEepHeader.regDmn[1]); ee->baseEepHeader.regDmn[1] = word; word = __bswap16(ee->baseEepHeader.rfSilent); ee->baseEepHeader.rfSilent = word; word = __bswap16(ee->baseEepHeader.blueToothOptions); ee->baseEepHeader.blueToothOptions = word; word = __bswap16(ee->baseEepHeader.deviceCap); ee->baseEepHeader.deviceCap = word; /* convert Modal Eep header */ for (j = 0; j < 2; j++) { pModal = &ee->modalHeader[j]; /* XXX linux/ah_osdep.h only defines __bswap32 for BE */ integer = __bswap32(pModal->antCtrlCommon); pModal->antCtrlCommon = integer; for (i = 0; i < AR5416_MAX_CHAINS; i++) { integer = __bswap32(pModal->antCtrlChain[i]); pModal->antCtrlChain[i] = integer; } for (i = 0; i < 3; i++) { word = __bswap16(pModal->xpaBiasLvlFreq[i]); pModal->xpaBiasLvlFreq[i] = word; } for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { word = __bswap16(pModal->spurChans[i].spurChan); pModal->spurChans[i].spurChan = word; } } } static uint16_t v14EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz) { HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; HALASSERT(0 <= ix && ix < AR5416_EEPROM_MODAL_SPURS); return ee->ee_base.modalHeader[is2GHz].spurChans[ix].spurChan; } /************************************************************************** * fbin2freq * * Get channel value from binary representation held in eeprom * RETURNS: the frequency in MHz */ static uint16_t fbin2freq(uint8_t fbin, HAL_BOOL is2GHz) { /* * Reserved value 0xFF provides an empty definition both as * an fbin and as a frequency - do not convert */ if (fbin == AR5416_BCHAN_UNUSED) return fbin; return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); } /* * Copy EEPROM Conformance Testing Limits contents * into the allocated space */ /* USE CTLS from chain zero */ #define CTL_CHAIN 0 static void v14EepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_v14 *ee) { RD_EDGES_POWER *rep = ee->ee_rdEdgesPower; int i, j; HALASSERT(AR5416_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES); for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR5416_NUM_CTLS; i++) { for (j = 0; j < NUM_EDGES; j ++) { /* XXX Confirm this is the right thing to do when an invalid channel is stored */ if (ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].bChannel == AR5416_BCHAN_UNUSED) { rep[j].rdEdge = 0; rep[j].twice_rdEdgePower = 0; rep[j].flag = 0; } else { rep[j].rdEdge = fbin2freq( ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].bChannel, (ee->ee_base.ctlIndex[i] & CTL_MODE_M) != CTL_11A); rep[j].twice_rdEdgePower = MS(ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].tPowerFlag, CAL_CTL_EDGES_POWER); rep[j].flag = MS(ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].tPowerFlag, CAL_CTL_EDGES_FLAG) != 0; } } rep += NUM_EDGES; } ee->ee_numCtls = i; HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM, "%s Numctls = %u\n",__func__,i); } /* * Reclaim any EEPROM-related storage. */ static void v14EepromDetach(struct ath_hal *ah) { HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; ath_hal_free(ee); AH_PRIVATE(ah)->ah_eeprom = AH_NULL; } #define owl_get_eep_ver(_ee) \ (((_ee)->ee_base.baseEepHeader.version >> 12) & 0xF) #define owl_get_eep_rev(_ee) \ (((_ee)->ee_base.baseEepHeader.version) & 0xFFF) /* * Howl is (hopefully) a special case where the endian-ness of the EEPROM * matches the native endian-ness; and that supplied EEPROMs don't have * a magic value to check. */ HAL_STATUS ath_hal_v14EepromAttach(struct ath_hal *ah) { #define NW(a) (sizeof(a) / sizeof(uint16_t)) HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; uint16_t *eep_data, magic; HAL_BOOL need_swap; u_int w, off, len; uint32_t sum; HALASSERT(ee == AH_NULL); /* * Don't check magic if we're supplied with an EEPROM block, * typically this is from Howl but it may also be from later * boards w/ an embedded Merlin. */ if (ah->ah_eepromdata == NULL) { if (!ath_hal_eepromRead(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s Error reading Eeprom MAGIC\n", __func__); return HAL_EEREAD; } HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n", __func__, magic); if (magic != AR5416_EEPROM_MAGIC) { HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n"); return HAL_EEMAGIC; } } ee = ath_hal_malloc(sizeof(HAL_EEPROM_v14)); if (ee == AH_NULL) { /* XXX message */ return HAL_ENOMEM; } eep_data = (uint16_t *)&ee->ee_base; for (w = 0; w < NW(struct ar5416eeprom); w++) { off = owl_eep_start_loc + w; /* NB: AP71 starts at 0 */ if (!ath_hal_eepromRead(ah, off, &eep_data[w])) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s eeprom read error at offset 0x%x\n", __func__, off); return HAL_EEREAD; } } /* Convert to eeprom native eeprom endian format */ /* XXX this is likely incorrect but will do for now to get howl/ap83 working. */ if (ah->ah_eepromdata == NULL && isBigEndian()) { for (w = 0; w < NW(struct ar5416eeprom); w++) eep_data[w] = __bswap16(eep_data[w]); } /* * At this point, we're in the native eeprom endian format * Now, determine the eeprom endian by looking at byte 26?? */ need_swap = ((ee->ee_base.baseEepHeader.eepMisc & AR5416_EEPMISC_BIG_ENDIAN) != 0) ^ isBigEndian(); if (need_swap) { HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM, "Byte swap EEPROM contents.\n"); len = __bswap16(ee->ee_base.baseEepHeader.length); } else { len = ee->ee_base.baseEepHeader.length; } len = AH_MIN(len, sizeof(struct ar5416eeprom)) / sizeof(uint16_t); /* Apply the checksum, done in native eeprom format */ /* XXX - Need to check to make sure checksum calculation is done * in the correct endian format. Right now, it seems it would * cast the raw data to host format and do the calculation, which may * not be correct as the calculation may need to be done in the native * eeprom format */ sum = 0; for (w = 0; w < len; w++) sum ^= eep_data[w]; /* Check CRC - Attach should fail on a bad checksum */ if (sum != 0xffff) { HALDEBUG(ah, HAL_DEBUG_ANY, "Bad EEPROM checksum 0x%x (Len=%u)\n", sum, len); return HAL_EEBADSUM; } if (need_swap) eepromSwap(&ee->ee_base); /* byte swap multi-byte data */ /* swap words 0+2 so version is at the front */ magic = eep_data[0]; eep_data[0] = eep_data[2]; eep_data[2] = magic; HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM, "%s Eeprom Version %u.%u\n", __func__, owl_get_eep_ver(ee), owl_get_eep_rev(ee)); /* NB: must be after all byte swapping */ if (owl_get_eep_ver(ee) != AR5416_EEP_VER) { HALDEBUG(ah, HAL_DEBUG_ANY, "Bad EEPROM version 0x%x\n", owl_get_eep_ver(ee)); return HAL_EEBADSUM; } v14EepromReadCTLInfo(ah, ee); /* Get CTLs */ AH_PRIVATE(ah)->ah_eeprom = ee; AH_PRIVATE(ah)->ah_eeversion = ee->ee_base.baseEepHeader.version; AH_PRIVATE(ah)->ah_eepromDetach = v14EepromDetach; AH_PRIVATE(ah)->ah_eepromGet = v14EepromGet; AH_PRIVATE(ah)->ah_eepromSet = v14EepromSet; AH_PRIVATE(ah)->ah_getSpurChan = v14EepromGetSpurChan; AH_PRIVATE(ah)->ah_eepromDiag = v14EepromDiag; return HAL_OK; #undef NW } diff --git a/sys/dev/ath/ath_hal/ah_eeprom_v14.h b/sys/dev/ath/ath_hal/ah_eeprom_v14.h index 6061b2f85d31..7b2c898ce6ee 100644 --- a/sys/dev/ath/ath_hal/ah_eeprom_v14.h +++ b/sys/dev/ath/ath_hal/ah_eeprom_v14.h @@ -1,289 +1,292 @@ /* * Copyright (c) 2008 Sam Leffler, Errno Consulting * Copyright (c) 2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _AH_EEPROM_V14_H_ #define _AH_EEPROM_V14_H_ #include "ah_eeprom.h" /* reg_off = 4 * (eep_off) */ #define AR5416_EEPROM_S 2 #define AR5416_EEPROM_OFFSET 0x2000 #define AR5416_EEPROM_START_ADDR 0x503f1200 #define AR5416_EEPROM_MAX 0xae0 /* Ignore for the moment used only on the flash implementations */ #define AR5416_EEPROM_MAGIC 0xa55a #define AR5416_EEPROM_MAGIC_OFFSET 0x0 #define owl_get_ntxchains(_txchainmask) \ (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) #ifdef __LINUX_ARM_ARCH__ /* AP71 */ #define owl_eep_start_loc 0 #else #define owl_eep_start_loc 256 #endif /* End temp defines */ #define AR5416_EEP_NO_BACK_VER 0x1 #define AR5416_EEP_VER 0xE #define AR5416_EEP_VER_MINOR_MASK 0xFFF // Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc #define AR5416_EEP_MINOR_VER_2 0x2 // Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable #define AR5416_EEP_MINOR_VER_3 0x3 #define AR5416_EEP_MINOR_VER_7 0x7 #define AR5416_EEP_MINOR_VER_9 0x9 #define AR5416_EEP_MINOR_VER_10 0xa #define AR5416_EEP_MINOR_VER_16 0x10 #define AR5416_EEP_MINOR_VER_17 0x11 #define AR5416_EEP_MINOR_VER_19 0x13 #define AR5416_EEP_MINOR_VER_20 0x14 #define AR5416_EEP_MINOR_VER_21 0x15 #define AR5416_EEP_MINOR_VER_22 0x16 // 16-bit offset location start of calibration struct #define AR5416_EEP_START_LOC 256 #define AR5416_NUM_5G_CAL_PIERS 8 #define AR5416_NUM_2G_CAL_PIERS 4 #define AR5416_NUM_5G_20_TARGET_POWERS 8 #define AR5416_NUM_5G_40_TARGET_POWERS 8 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 #define AR5416_NUM_2G_20_TARGET_POWERS 4 #define AR5416_NUM_2G_40_TARGET_POWERS 4 #define AR5416_NUM_CTLS 24 #define AR5416_NUM_BAND_EDGES 8 #define AR5416_NUM_PD_GAINS 4 #define AR5416_PD_GAINS_IN_MASK 4 #define AR5416_PD_GAIN_ICEPTS 5 #define AR5416_EEPROM_MODAL_SPURS 5 #define AR5416_MAX_RATE_POWER 63 #define AR5416_NUM_PDADC_VALUES 128 #define AR5416_NUM_RATES 16 #define AR5416_BCHAN_UNUSED 0xFF #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 #define AR5416_EEPMISC_BIG_ENDIAN 0x01 #define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) #define AR5416_MAX_CHAINS 3 #define AR5416_PWR_TABLE_OFFSET_DB -5 #define AR5416_ANT_16S 25 #define AR5416_NUM_ANT_CHAIN_FIELDS 7 #define AR5416_NUM_ANT_COMMON_FIELDS 4 #define AR5416_SIZE_ANT_CHAIN_FIELD 3 #define AR5416_SIZE_ANT_COMMON_FIELD 4 #define AR5416_ANT_CHAIN_MASK 0x7 #define AR5416_ANT_COMMON_MASK 0xf #define AR5416_CHAIN_0_IDX 0 #define AR5416_CHAIN_1_IDX 1 #define AR5416_CHAIN_2_IDX 2 #define AR5416_OPFLAGS_11A 0x01 #define AR5416_OPFLAGS_11G 0x02 #define AR5416_OPFLAGS_N_5G_HT40 0x04 /* If set, disable 5G HT40 */ #define AR5416_OPFLAGS_N_2G_HT40 0x08 #define AR5416_OPFLAGS_N_5G_HT20 0x10 #define AR5416_OPFLAGS_N_2G_HT20 0x20 /* RF silent fields in EEPROM */ #define EEP_RFSILENT_ENABLED 0x0001 /* enabled/disabled */ #define EEP_RFSILENT_ENABLED_S 0 #define EEP_RFSILENT_POLARITY 0x0002 /* polarity */ #define EEP_RFSILENT_POLARITY_S 1 #define EEP_RFSILENT_GPIO_SEL 0x001c /* gpio PIN */ #define EEP_RFSILENT_GPIO_SEL_S 2 /* Rx gain type values */ #define AR5416_EEP_RXGAIN_23dB_BACKOFF 0 #define AR5416_EEP_RXGAIN_13dB_BACKOFF 1 #define AR5416_EEP_RXGAIN_ORIG 2 /* Tx gain type values */ #define AR5416_EEP_TXGAIN_ORIG 0 #define AR5416_EEP_TXGAIN_HIGH_POWER 1 typedef struct spurChanStruct { uint16_t spurChan; uint8_t spurRangeLow; uint8_t spurRangeHigh; } __packed SPUR_CHAN; typedef struct CalTargetPowerLegacy { uint8_t bChannel; uint8_t tPow2x[4]; } __packed CAL_TARGET_POWER_LEG; typedef struct CalTargetPowerHt { uint8_t bChannel; uint8_t tPow2x[8]; } __packed CAL_TARGET_POWER_HT; typedef struct CalCtlEdges { uint8_t bChannel; uint8_t tPowerFlag; /* [0..5] tPower [6..7] flag */ #define CAL_CTL_EDGES_POWER 0x3f #define CAL_CTL_EDGES_POWER_S 0 #define CAL_CTL_EDGES_FLAG 0xc0 #define CAL_CTL_EDGES_FLAG_S 6 } __packed CAL_CTL_EDGES; /* * These are the secondary regulatory domain flags * for regDmn[1]. */ #define AR5416_REGDMN_EN_FCC_MID 0x01 /* 5.47 - 5.7GHz operation */ #define AR5416_REGDMN_EN_JAP_MID 0x02 /* 5.47 - 5.7GHz operation */ #define AR5416_REGDMN_EN_FCC_DFS_HT40 0x04 /* FCC HT40 + DFS operation */ #define AR5416_REGDMN_EN_JAP_HT40 0x08 /* JP HT40 operation */ #define AR5416_REGDMN_EN_JAP_DFS_HT40 0x10 /* JP HT40 + DFS operation */ /* * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version * and length are swapped). We reverse their position after reading * the data into host memory so the version field is at the same * offset as in previous EEPROM layouts. This makes utilities that * inspect the EEPROM contents work without looking at the PCI device * id which may or may not be reliable. */ typedef struct BaseEepHeader { uint16_t version; /* NB: length in EEPROM */ uint16_t checksum; uint16_t length; /* NB: version in EEPROM */ uint8_t opCapFlags; uint8_t eepMisc; uint16_t regDmn[2]; uint8_t macAddr[6]; uint8_t rxMask; uint8_t txMask; uint16_t rfSilent; uint16_t blueToothOptions; uint16_t deviceCap; uint32_t binBuildNumber; uint8_t deviceType; uint8_t pwdclkind; uint8_t fastClk5g; uint8_t divChain; uint8_t rxGainType; uint8_t dacHiPwrMode_5G;/* use the DAC high power mode (MB91) */ uint8_t openLoopPwrCntl;/* 1: use open loop power control, 0: use closed loop power control */ uint8_t dacLpMode; uint8_t txGainType; /* high power tx gain table support */ uint8_t rcChainMask; /* "1" if the card is an HB93 1x2 */ uint8_t desiredScaleCCK; uint8_t pwr_table_offset; - uint8_t frac_n_5g; + uint8_t frac_n_5g; /* + * bit 0: indicates that fracN synth + * mode applies to all 5G channels + */ uint8_t futureBase[21]; } __packed BASE_EEP_HEADER; // 64 B typedef struct ModalEepHeader { uint32_t antCtrlChain[AR5416_MAX_CHAINS]; // 12 uint32_t antCtrlCommon; // 4 int8_t antennaGainCh[AR5416_MAX_CHAINS]; // 3 uint8_t switchSettling; // 1 uint8_t txRxAttenCh[AR5416_MAX_CHAINS]; // 3 uint8_t rxTxMarginCh[AR5416_MAX_CHAINS]; // 3 uint8_t adcDesiredSize; // 1 int8_t pgaDesiredSize; // 1 uint8_t xlnaGainCh[AR5416_MAX_CHAINS]; // 3 uint8_t txEndToXpaOff; // 1 uint8_t txEndToRxOn; // 1 uint8_t txFrameToXpaOn; // 1 uint8_t thresh62; // 1 uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS]; // 3 uint8_t xpdGain; // 1 uint8_t xpd; // 1 int8_t iqCalICh[AR5416_MAX_CHAINS]; // 1 int8_t iqCalQCh[AR5416_MAX_CHAINS]; // 1 uint8_t pdGainOverlap; // 1 uint8_t ob; // 1 uint8_t db; // 1 uint8_t xpaBiasLvl; // 1 uint8_t pwrDecreaseFor2Chain; // 1 uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B uint8_t txFrameToDataStart; // 1 uint8_t txFrameToPaOn; // 1 uint8_t ht40PowerIncForPdadc; // 1 uint8_t bswAtten[AR5416_MAX_CHAINS]; // 3 uint8_t bswMargin[AR5416_MAX_CHAINS]; // 3 uint8_t swSettleHt40; // 1 uint8_t xatten2Db[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 11:6) uint8_t xatten2Margin[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 21:17) uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280 uint8_t db_ch1; // 1 uint8_t flagBits; // 1 #define AR5416_EEP_FLAG_USEANT1 0x80 /* +1 configured antenna */ #define AR5416_EEP_FLAG_FORCEXPAON 0x40 /* force XPA bit for 5G */ #define AR5416_EEP_FLAG_LOCALBIAS 0x20 /* enable local bias */ #define AR5416_EEP_FLAG_FEMBANDSELECT 0x10 /* FEM band select used */ #define AR5416_EEP_FLAG_XLNABUFIN 0x08 #define AR5416_EEP_FLAG_XLNAISEL1 0x04 #define AR5416_EEP_FLAG_XLNAISEL2 0x02 #define AR5416_EEP_FLAG_XLNABUFMODE 0x01 uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck uint16_t xpaBiasLvlFreq[3]; // 3 uint8_t futureModal[6]; // 6 SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B } __packed MODAL_EEP_HEADER; // == 100 B typedef struct calDataPerFreqOpLoop { uint8_t pwrPdg[2][5]; /* power measurement */ uint8_t vpdPdg[2][5]; /* pdadc voltage at power measurement */ uint8_t pcdac[2][5]; /* pcdac used for power measurement */ uint8_t empty[2][5]; /* future use */ } __packed CAL_DATA_PER_FREQ_OP_LOOP; typedef struct CalCtlData { CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; } __packed CAL_CTL_DATA; typedef struct calDataPerFreq { uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; } __packed CAL_DATA_PER_FREQ; struct ar5416eeprom { BASE_EEP_HEADER baseEepHeader; // 64 B uint8_t custData[64]; // 64 B MODAL_EEP_HEADER modalHeader[2]; // 200 B uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; CAL_TARGET_POWER_HT calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; CAL_TARGET_POWER_HT calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; uint8_t ctlIndex[AR5416_NUM_CTLS]; CAL_CTL_DATA ctlData[AR5416_NUM_CTLS]; uint8_t padding; } __packed; typedef struct { struct ar5416eeprom ee_base; #define NUM_EDGES 8 uint16_t ee_numCtls; RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_NUM_CTLS]; /* XXX these are dynamically calculated for use by shared code */ int8_t ee_antennaGainMax[2]; } HAL_EEPROM_v14; #endif /* _AH_EEPROM_V14_H_ */ diff --git a/sys/dev/ath/ath_hal/ar9002/ar9280.c b/sys/dev/ath/ath_hal/ar9002/ar9280.c index f1bb4fe3f6bd..99fd1d790d2e 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9280.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9280.c @@ -1,376 +1,386 @@ /* * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting * Copyright (c) 2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #include "opt_ah.h" /* * NB: Merlin and later have a simpler RF backend. */ #include "ah.h" #include "ah_internal.h" #include "ah_eeprom_v14.h" #include "ar9002/ar9280.h" #include "ar5416/ar5416reg.h" #include "ar5416/ar5416phy.h" #define N(a) (sizeof(a)/sizeof(a[0])) struct ar9280State { RF_HAL_FUNCS base; /* public state, must be first */ uint16_t pcdacTable[1]; /* XXX */ }; #define AR9280(ah) ((struct ar9280State *) AH5212(ah)->ah_rfHal) static HAL_BOOL ar9280GetChannelMaxMinPower(struct ath_hal *, const struct ieee80211_channel *, int16_t *maxPow,int16_t *minPow); int16_t ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c); static void ar9280WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex, int writes) { (void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain, freqIndex, writes); } /* * Take the MHz channel value and set the Channel value * * ASSUMES: Writes enabled to analog bus * * Actual Expression, * * For 2GHz channel, * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) * (freq_ref = 40MHz) * * For 5GHz channel, * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) * (freq_ref = 40MHz/(24>>amodeRefSel)) * * For 5GHz channels which are 5MHz spaced, * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) * (freq_ref = 40MHz) */ static HAL_BOOL ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) { uint16_t bMode, fracMode, aModeRefSel = 0; uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; CHAN_CENTERS centers; uint32_t refDivA = 24; + uint8_t frac_n_5g; OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq); ar5416GetChannelCenters(ah, chan, ¢ers); freq = centers.synth_center; reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL); reg32 &= 0xc0000000; + if (ath_hal_eepromGet(ah, AR_EEP_FRAC_N_5G, &frac_n_5g) != HAL_OK) + frac_n_5g = 0; + if (freq < 4800) { /* 2 GHz, fractional mode */ uint32_t txctl; bMode = 1; fracMode = 1; aModeRefSel = 0; channelSel = (freq * 0x10000)/15; txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL); if (freq == 2484) { /* Enable channel spreading for channel 14 */ OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl | AR_PHY_CCK_TX_CTRL_JAPAN); } else { OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN); } } else { bMode = 0; fracMode = 0; - if ((freq % 20) == 0) { - aModeRefSel = 3; - } else if ((freq % 10) == 0) { - aModeRefSel = 2; - } else { + switch (frac_n_5g) { + case 0: + if ((freq % 20) == 0) { + aModeRefSel = 3; + } else if ((freq % 10) == 0) { + aModeRefSel = 2; + } + if (aModeRefSel) break; + case 1: + default: aModeRefSel = 0; /* Enable 2G (fractional) mode for channels which are 5MHz spaced */ fracMode = 1; refDivA = 1; channelSel = (freq * 0x8000)/15; /* RefDivA setting */ OS_A_REG_RMW_FIELD(ah, AR_AN_SYNTH9, AR_AN_SYNTH9_REFDIVA, refDivA); } + if (!fracMode) { ndiv = (freq * (refDivA >> aModeRefSel))/60; channelSel = ndiv & 0x1ff; channelFrac = (ndiv & 0xfffffe00) * 2; channelSel = (channelSel << 17) | channelFrac; } } reg32 = reg32 | (bMode << 29) | (fracMode << 28) | (aModeRefSel << 26) | (channelSel); OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); AH_PRIVATE(ah)->ah_curchan = chan; return AH_TRUE; } /* * Return a reference to the requested RF Bank. */ static uint32_t * ar9280GetRfBank(struct ath_hal *ah, int bank) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n", __func__, bank); return AH_NULL; } /* * Reads EEPROM header info from device structure and programs * all rf registers */ static HAL_BOOL ar9280SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan, uint16_t modesIndex, uint16_t *rfXpdGain) { return AH_TRUE; /* nothing to do */ } /* * Read the transmit power levels from the structures taken from EEPROM * Interpolate read transmit power values for this channel * Organize the transmit power values into a table for writing into the hardware */ static HAL_BOOL ar9280SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax, const struct ieee80211_channel *chan, uint16_t *rfXpdGain) { return AH_TRUE; } #if 0 static int16_t ar9280GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data) { int i, minIndex; int16_t minGain,minPwr,minPcdac,retVal; /* Assume NUM_POINTS_XPD0 > 0 */ minGain = data->pDataPerXPD[0].xpd_gain; for (minIndex=0,i=1; ipDataPerXPD[i].xpd_gain < minGain) { minIndex = i; minGain = data->pDataPerXPD[i].xpd_gain; } } minPwr = data->pDataPerXPD[minIndex].pwr_t4[0]; minPcdac = data->pDataPerXPD[minIndex].pcdac[0]; for (i=1; ipDataPerXPD[minIndex].pwr_t4[i] < minPwr) { minPwr = data->pDataPerXPD[minIndex].pwr_t4[i]; minPcdac = data->pDataPerXPD[minIndex].pcdac[i]; } } retVal = minPwr - (minPcdac*2); return(retVal); } #endif static HAL_BOOL ar9280GetChannelMaxMinPower(struct ath_hal *ah, const struct ieee80211_channel *chan, int16_t *maxPow, int16_t *minPow) { #if 0 struct ath_hal_5212 *ahp = AH5212(ah); int numChannels=0,i,last; int totalD, totalF,totalMin; EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL; EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL; *maxPow = 0; if (IS_CHAN_A(chan)) { powerArray = ahp->ah_modePowerArray5112; data = powerArray[headerInfo11A].pDataPerChannel; numChannels = powerArray[headerInfo11A].numChannels; } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) { /* XXX - is this correct? Should we also use the same power for turbo G? */ powerArray = ahp->ah_modePowerArray5112; data = powerArray[headerInfo11G].pDataPerChannel; numChannels = powerArray[headerInfo11G].numChannels; } else if (IS_CHAN_B(chan)) { powerArray = ahp->ah_modePowerArray5112; data = powerArray[headerInfo11B].pDataPerChannel; numChannels = powerArray[headerInfo11B].numChannels; } else { return (AH_TRUE); } /* Make sure the channel is in the range of the TP values * (freq piers) */ if ((numChannels < 1) || (chan->channel < data[0].channelValue) || (chan->channel > data[numChannels-1].channelValue)) return(AH_FALSE); /* Linearly interpolate the power value now */ for (last=0,i=0; (ichannel > data[i].channelValue); last=i++); totalD = data[i].channelValue - data[last].channelValue; if (totalD > 0) { totalF = data[i].maxPower_t4 - data[last].maxPower_t4; *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD); totalMin = ar9280GetMinPower(ah,&data[i]) - ar9280GetMinPower(ah, &data[last]); *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar9280GetMinPower(ah, &data[last])*totalD)/totalD); return (AH_TRUE); } else { if (chan->channel == data[i].channelValue) { *maxPow = data[i].maxPower_t4; *minPow = ar9280GetMinPower(ah, &data[i]); return(AH_TRUE); } else return(AH_FALSE); } #else *maxPow = *minPow = 0; return AH_FALSE; #endif } /* * The ordering of nfarray is thus: * * nfarray[0]: Chain 0 ctl * nfarray[1]: Chain 1 ctl * nfarray[2]: Chain 2 ctl * nfarray[3]: Chain 0 ext * nfarray[4]: Chain 1 ext * nfarray[5]: Chain 2 ext */ static void ar9280GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[]) { int16_t nf; nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); if (nf & 0x100) nf = 0 - ((nf ^ 0x1ff) + 1); HALDEBUG(ah, HAL_DEBUG_NFCAL, "NF calibrated [ctl] [chain 0] is %d\n", nf); nfarray[0] = nf; nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); if (nf & 0x100) nf = 0 - ((nf ^ 0x1ff) + 1); HALDEBUG(ah, HAL_DEBUG_NFCAL, "NF calibrated [ctl] [chain 1] is %d\n", nf); nfarray[1] = nf; nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); if (nf & 0x100) nf = 0 - ((nf ^ 0x1ff) + 1); HALDEBUG(ah, HAL_DEBUG_NFCAL, "NF calibrated [ext] [chain 0] is %d\n", nf); nfarray[3] = nf; nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); if (nf & 0x100) nf = 0 - ((nf ^ 0x1ff) + 1); HALDEBUG(ah, HAL_DEBUG_NFCAL, "NF calibrated [ext] [chain 1] is %d\n", nf); nfarray[4] = nf; /* Chain 2 - invalid */ nfarray[2] = 0; nfarray[5] = 0; } /* * Adjust NF based on statistical values for 5GHz frequencies. * Stubbed:Not used by Fowl */ int16_t ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) { return 0; } /* * Free memory for analog bank scratch buffers */ static void ar9280RfDetach(struct ath_hal *ah) { struct ath_hal_5212 *ahp = AH5212(ah); HALASSERT(ahp->ah_rfHal != AH_NULL); ath_hal_free(ahp->ah_rfHal); ahp->ah_rfHal = AH_NULL; } HAL_BOOL ar9280RfAttach(struct ath_hal *ah, HAL_STATUS *status) { struct ath_hal_5212 *ahp = AH5212(ah); struct ar9280State *priv; HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR9280 radio\n", __func__); HALASSERT(ahp->ah_rfHal == AH_NULL); priv = ath_hal_malloc(sizeof(struct ar9280State)); if (priv == AH_NULL) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cannot allocate private state\n", __func__); *status = HAL_ENOMEM; /* XXX */ return AH_FALSE; } priv->base.rfDetach = ar9280RfDetach; priv->base.writeRegs = ar9280WriteRegs; priv->base.getRfBank = ar9280GetRfBank; priv->base.setChannel = ar9280SetChannel; priv->base.setRfRegs = ar9280SetRfRegs; priv->base.setPowerTable = ar9280SetPowerTable; priv->base.getChannelMaxMinPower = ar9280GetChannelMaxMinPower; priv->base.getNfAdjust = ar9280GetNfAdjust; ahp->ah_pcdacTable = priv->pcdacTable; ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable); ahp->ah_rfHal = &priv->base; /* * Set noise floor adjust method; we arrange a * direct call instead of thunking. */ AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust; AH_PRIVATE(ah)->ah_getNoiseFloor = ar9280GetNoiseFloor; return AH_TRUE; }