diff --git a/sys/dev/ath/ath_hal/ah.h b/sys/dev/ath/ath_hal/ah.h index 657d14850d90..450864c70de1 100644 --- a/sys/dev/ath/ath_hal/ah.h +++ b/sys/dev/ath/ath_hal/ah.h @@ -1,1185 +1,1318 @@ /* * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting * Copyright (c) 2002-2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _ATH_AH_H_ #define _ATH_AH_H_ /* * Atheros Hardware Access Layer * * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal * structure for use with the device. Hardware-related operations that * follow must call back into the HAL through interface, supplying the * reference as the first parameter. */ #include "ah_osdep.h" /* * The maximum number of TX/RX chains supported. * This is intended to be used by various statistics gathering operations * (NF, RSSI, EVM). */ #define AH_MIMO_MAX_CHAINS 3 #define AH_MIMO_MAX_EVM_PILOTS 6 /* * __ahdecl is analogous to _cdecl; it defines the calling * convention used within the HAL. For most systems this * can just default to be empty and the compiler will (should) * use _cdecl. For systems where _cdecl is not compatible this * must be defined. See linux/ah_osdep.h for an example. */ #ifndef __ahdecl #define __ahdecl #endif /* * Status codes that may be returned by the HAL. Note that * interfaces that return a status code set it only when an * error occurs--i.e. you cannot check it for success. */ typedef enum { HAL_OK = 0, /* No error */ HAL_ENXIO = 1, /* No hardware present */ HAL_ENOMEM = 2, /* Memory allocation failed */ HAL_EIO = 3, /* Hardware didn't respond as expected */ HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ HAL_EEVERSION = 5, /* EEPROM version invalid */ HAL_EELOCKED = 6, /* EEPROM unreadable */ HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ HAL_EEREAD = 8, /* EEPROM read problem */ HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ HAL_EESIZE = 10, /* EEPROM size not supported */ HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ HAL_EINVAL = 12, /* Invalid parameter to function */ HAL_ENOTSUPP = 13, /* Hardware revision not supported */ HAL_ESELFTEST = 14, /* Hardware self-test failed */ HAL_EINPROGRESS = 15, /* Operation incomplete */ HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ HAL_EEBADCC = 17, /* EEPROM invalid country code */ } HAL_STATUS; typedef enum { AH_FALSE = 0, /* NB: lots of code assumes false is zero */ AH_TRUE = 1, } HAL_BOOL; typedef enum { HAL_CAP_REG_DMN = 0, /* current regulatory domain */ HAL_CAP_CIPHER = 1, /* hardware supports cipher */ HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ HAL_CAP_DIAG = 11, /* hardware diagnostic support */ HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ HAL_CAP_BURST = 13, /* hardware supports packet bursting */ HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ HAL_CAP_TXPOW = 15, /* global tx power limit */ HAL_CAP_TPC = 16, /* per-packet tx power control */ HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ /* 21 was HAL_CAP_XR */ HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ /* 23 was HAL_CAP_CHAN_HALFRATE */ /* 24 was HAL_CAP_CHAN_QUARTERRATE */ HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ HAL_CAP_HT = 30, /* hardware can support HT */ HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ HAL_CAP_DFS_DMN = 44, /* current DFS domain */ HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep automatically after waking up to receive TIM */ HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ /* The following are private to the FreeBSD HAL (224 onward) */ HAL_CAP_INTMIT = 229, /* interference mitigation */ HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ HAL_CAP_BB_HANG = 235, /* can baseband hang */ HAL_CAP_MAC_HANG = 236, /* can MAC hang */ HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ } HAL_CAPABILITY_TYPE; /* * "States" for setting the LED. These correspond to * the possible 802.11 operational states and there may * be a many-to-one mapping between these states and the * actual hardware state for the LED's (i.e. the hardware * may have fewer states). */ typedef enum { HAL_LED_INIT = 0, HAL_LED_SCAN = 1, HAL_LED_AUTH = 2, HAL_LED_ASSOC = 3, HAL_LED_RUN = 4 } HAL_LED_STATE; /* * Transmit queue types/numbers. These are used to tag * each transmit queue in the hardware and to identify a set * of transmit queues for operations such as start/stop dma. */ typedef enum { HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ } HAL_TX_QUEUE; #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ /* * Transmit queue subtype. These map directly to * WME Access Categories (except for UPSD). Refer * to Table 5 of the WME spec. */ typedef enum { HAL_WME_AC_BK = 0, /* background access category */ HAL_WME_AC_BE = 1, /* best effort access category*/ HAL_WME_AC_VI = 2, /* video access category */ HAL_WME_AC_VO = 3, /* voice access category */ HAL_WME_UPSD = 4, /* uplink power save */ } HAL_TX_QUEUE_SUBTYPE; /* * Transmit queue flags that control various * operational parameters. */ typedef enum { /* * Per queue interrupt enables. When set the associated * interrupt may be delivered for packets sent through * the queue. Without these enabled no interrupts will * be delivered for transmits through the queue. */ HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ /* * Enable hardware compression for packets sent through * the queue. The compression buffer must be setup and * packets must have a key entry marked in the tx descriptor. */ HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ /* * Disable queue when veol is hit or ready time expires. * By default the queue is disabled only on reaching the * physical end of queue (i.e. a null link ptr in the * descriptor chain). */ HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, /* * Schedule frames on delivery of a DBA (DMA Beacon Alert) * event. Frames will be transmitted only when this timer * fires, e.g to transmit a beacon in ap or adhoc modes. */ HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ /* * Each transmit queue has a counter that is incremented * each time the queue is enabled and decremented when * the list of frames to transmit is traversed (or when * the ready time for the queue expires). This counter * must be non-zero for frames to be scheduled for * transmission. The following controls disable bumping * this counter under certain conditions. Typically this * is used to gate frames based on the contents of another * queue (e.g. CAB traffic may only follow a beacon frame). * These are meaningful only when frames are scheduled * with a non-ASAP policy (e.g. DBA-gated). */ HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ /* * Fragment burst backoff policy. Normally the no backoff * is done after a successful transmission, the next fragment * is sent at SIFS. If this flag is set backoff is done * after each fragment, regardless whether it was ack'd or * not, after the backoff count reaches zero a normal channel * access procedure is done before the next transmit (i.e. * wait AIFS instead of SIFS). */ HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, /* * Disable post-tx backoff following each frame. */ HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ /* * DCU arbiter lockout control. This controls how * lower priority tx queues are handled with respect to * to a specific queue when multiple queues have frames * to send. No lockout means lower priority queues arbitrate * concurrently with this queue. Intra-frame lockout * means lower priority queues are locked out until the * current frame transmits (e.g. including backoffs and bursting). * Global lockout means nothing lower can arbitrary so * long as there is traffic activity on this queue (frames, * backoff, etc). */ HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ } HAL_TX_QUEUE_FLAGS; typedef struct { uint32_t tqi_ver; /* hal TXQ version */ HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ uint32_t tqi_priority; /* (not used) */ uint32_t tqi_aifs; /* aifs */ uint32_t tqi_cwmin; /* cwMin */ uint32_t tqi_cwmax; /* cwMax */ uint16_t tqi_shretry; /* rts retry limit */ uint16_t tqi_lgretry; /* long retry limit (not used)*/ uint32_t tqi_cbrPeriod; /* CBR period (us) */ uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ uint32_t tqi_burstTime; /* max burst duration (us) */ uint32_t tqi_readyTime; /* frame schedule time (us) */ uint32_t tqi_compBuf; /* comp buffer phys addr */ } HAL_TXQ_INFO; #define HAL_TQI_NONVAL 0xffff /* token to use for aifs, cwmin, cwmax */ #define HAL_TXQ_USEDEFAULT ((uint32_t) -1) /* compression definitions */ #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ #define HAL_COMP_BUF_ALIGN_SIZE 512 /* * Transmit packet types. This belongs in ah_desc.h, but * is here so we can give a proper type to various parameters * (and not require everyone include the file). * * NB: These values are intentionally assigned for * direct use when setting up h/w descriptors. */ typedef enum { HAL_PKT_TYPE_NORMAL = 0, HAL_PKT_TYPE_ATIM = 1, HAL_PKT_TYPE_PSPOLL = 2, HAL_PKT_TYPE_BEACON = 3, HAL_PKT_TYPE_PROBE_RESP = 4, HAL_PKT_TYPE_CHIRP = 5, HAL_PKT_TYPE_GRP_POLL = 6, HAL_PKT_TYPE_AMPDU = 7, } HAL_PKT_TYPE; /* Rx Filter Frame Types */ typedef enum { /* * These bits correspond to AR_RX_FILTER for all chips. * Not all bits are supported by all chips. */ HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, /* Allow all mcast/bcast frames */ /* * Magic RX filter flags that aren't targetting hardware bits * but instead the HAL sets individual bits - eg PHYERR will result * in OFDM/CCK timing error frames being received. */ HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ } HAL_RX_FILTER; typedef enum { HAL_PM_AWAKE = 0, HAL_PM_FULL_SLEEP = 1, HAL_PM_NETWORK_SLEEP = 2, HAL_PM_UNDEFINED = 3 } HAL_POWER_MODE; /* * NOTE WELL: * These are mapped to take advantage of the common locations for many of * the bits on all of the currently supported MAC chips. This is to make * the ISR as efficient as possible, while still abstracting HW differences. * When new hardware breaks this commonality this enumerated type, as well * as the HAL functions using it, must be modified. All values are directly * mapped unless commented otherwise. */ typedef enum { HAL_INT_RX = 0x00000001, /* Non-common mapping */ HAL_INT_RXDESC = 0x00000002, HAL_INT_RXNOFRM = 0x00000008, HAL_INT_RXEOL = 0x00000010, HAL_INT_RXORN = 0x00000020, HAL_INT_TX = 0x00000040, /* Non-common mapping */ HAL_INT_TXDESC = 0x00000080, HAL_INT_TIM_TIMER= 0x00000100, HAL_INT_TXURN = 0x00000800, HAL_INT_MIB = 0x00001000, HAL_INT_RXPHY = 0x00004000, HAL_INT_RXKCM = 0x00008000, HAL_INT_SWBA = 0x00010000, HAL_INT_BMISS = 0x00040000, HAL_INT_BNR = 0x00100000, HAL_INT_TIM = 0x00200000, /* Non-common mapping */ HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ HAL_INT_GPIO = 0x01000000, HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ HAL_INT_CST = 0x10000000, /* Non-common mapping */ HAL_INT_GTT = 0x20000000, /* Non-common mapping */ HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ HAL_INT_BMISC = HAL_INT_TIM | HAL_INT_DTIM | HAL_INT_DTIMSYNC | HAL_INT_CABEND | HAL_INT_TBTT, /* Interrupt bits that map directly to ISR/IMR bits */ HAL_INT_COMMON = HAL_INT_RXNOFRM | HAL_INT_RXDESC | HAL_INT_RXEOL | HAL_INT_RXORN | HAL_INT_TXDESC | HAL_INT_TXURN | HAL_INT_MIB | HAL_INT_RXPHY | HAL_INT_RXKCM | HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_BNR | HAL_INT_GPIO, } HAL_INT; typedef enum { - HAL_GPIO_MUX_OUTPUT = 0, - HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, - HAL_GPIO_MUX_PCIE_POWER_LED = 2, - HAL_GPIO_MUX_TX_FRAME = 3, - HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, - HAL_GPIO_MUX_MAC_NETWORK_LED = 5, - HAL_GPIO_MUX_MAC_POWER_LED = 6 + HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, + HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, + HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, + HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, + HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, + HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, + HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6 } HAL_GPIO_MUX_TYPE; typedef enum { HAL_GPIO_INTR_LOW = 0, HAL_GPIO_INTR_HIGH = 1, HAL_GPIO_INTR_DISABLE = 2 } HAL_GPIO_INTR_TYPE; typedef enum { HAL_RFGAIN_INACTIVE = 0, HAL_RFGAIN_READ_REQUESTED = 1, HAL_RFGAIN_NEED_CHANGE = 2 } HAL_RFGAIN; typedef uint16_t HAL_CTRY_CODE; /* country code */ typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ #define HAL_ANTENNA_MIN_MODE 0 #define HAL_ANTENNA_FIXED_A 1 #define HAL_ANTENNA_FIXED_B 2 #define HAL_ANTENNA_MAX_MODE 3 typedef struct { uint32_t ackrcv_bad; uint32_t rts_bad; uint32_t rts_good; uint32_t fcs_bad; uint32_t beacons; } HAL_MIB_STATS; enum { HAL_MODE_11A = 0x001, /* 11a channels */ HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ HAL_MODE_11B = 0x004, /* 11b channels */ HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ #ifdef notdef HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ #else HAL_MODE_11G = 0x008, /* XXX historical */ #endif HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ HAL_MODE_11NG_HT20 = 0x008000, HAL_MODE_11NA_HT20 = 0x010000, HAL_MODE_11NG_HT40PLUS = 0x020000, HAL_MODE_11NG_HT40MINUS = 0x040000, HAL_MODE_11NA_HT40PLUS = 0x080000, HAL_MODE_11NA_HT40MINUS = 0x100000, HAL_MODE_ALL = 0xffffff }; typedef struct { int rateCount; /* NB: for proper padding */ uint8_t rateCodeToIndex[144]; /* back mapping */ struct { uint8_t valid; /* valid for rate control use */ uint8_t phy; /* CCK/OFDM/XR */ uint32_t rateKbps; /* transfer rate in kbs */ uint8_t rateCode; /* rate for h/w descriptors */ uint8_t shortPreamble; /* mask for enabling short * preamble in CCK rate code */ uint8_t dot11Rate; /* value for supported rates * info element of MLME */ uint8_t controlRate; /* index of next lower basic * rate; used for dur. calcs */ uint16_t lpAckDuration; /* long preamble ACK duration */ uint16_t spAckDuration; /* short preamble ACK duration*/ } info[32]; } HAL_RATE_TABLE; typedef struct { u_int rs_count; /* number of valid entries */ uint8_t rs_rates[32]; /* rates */ } HAL_RATE_SET; /* * 802.11n specific structures and enums */ typedef enum { HAL_CHAINTYPE_TX = 1, /* Tx chain type */ HAL_CHAINTYPE_RX = 2, /* RX chain type */ } HAL_CHAIN_TYPE; typedef struct { u_int Tries; u_int Rate; u_int PktDuration; u_int ChSel; u_int RateFlags; #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ } HAL_11N_RATE_SERIES; typedef enum { HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ } HAL_HT_MACMODE; typedef enum { HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ } HAL_HT_PHYMODE; typedef enum { HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ } HAL_HT_EXTPROTSPACING; typedef enum { HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ } HAL_HT_RXCLEAR; /* * Antenna switch control. By default antenna selection * enables multiple (2) antenna use. To force use of the * A or B antenna only specify a fixed setting. Fixing * the antenna will also disable any diversity support. */ typedef enum { HAL_ANT_VARIABLE = 0, /* variable by programming */ HAL_ANT_FIXED_A = 1, /* fixed antenna A */ HAL_ANT_FIXED_B = 2, /* fixed antenna B */ } HAL_ANT_SETTING; typedef enum { HAL_M_STA = 1, /* infrastructure station */ HAL_M_IBSS = 0, /* IBSS (adhoc) station */ HAL_M_HOSTAP = 6, /* Software Access Point */ HAL_M_MONITOR = 8 /* Monitor mode */ } HAL_OPMODE; typedef struct { uint8_t kv_type; /* one of HAL_CIPHER */ uint8_t kv_pad; uint16_t kv_len; /* length in bits */ uint8_t kv_val[16]; /* enough for 128-bit keys */ uint8_t kv_mic[8]; /* TKIP MIC key */ uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ } HAL_KEYVAL; typedef enum { HAL_CIPHER_WEP = 0, HAL_CIPHER_AES_OCB = 1, HAL_CIPHER_AES_CCM = 2, HAL_CIPHER_CKIP = 3, HAL_CIPHER_TKIP = 4, HAL_CIPHER_CLR = 5, /* no encryption */ HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ } HAL_CIPHER; enum { HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ HAL_SLOT_TIME_9 = 9, HAL_SLOT_TIME_20 = 20, }; /* * Per-station beacon timer state. Note that the specified * beacon interval (given in TU's) can also include flags * to force a TSF reset and to enable the beacon xmit logic. * If bs_cfpmaxduration is non-zero the hardware is setup to * coexist with a PCF-capable AP. */ typedef struct { uint32_t bs_nexttbtt; /* next beacon in TU */ uint32_t bs_nextdtim; /* next DTIM in TU */ uint32_t bs_intval; /* beacon interval+flags */ #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ uint32_t bs_dtimperiod; uint16_t bs_cfpperiod; /* CFP period in TU */ uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ uint32_t bs_cfpnext; /* next CFP in TU */ uint16_t bs_timoffset; /* byte offset to TIM bitmap */ uint16_t bs_bmissthreshold; /* beacon miss threshold */ uint32_t bs_sleepduration; /* max sleep duration */ } HAL_BEACON_STATE; /* * Like HAL_BEACON_STATE but for non-station mode setup. * NB: see above flag definitions for bt_intval. */ typedef struct { uint32_t bt_intval; /* beacon interval+flags */ uint32_t bt_nexttbtt; /* next beacon in TU */ uint32_t bt_nextatim; /* next ATIM in TU */ uint32_t bt_nextdba; /* next DBA in 1/8th TU */ uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ uint32_t bt_flags; /* timer enables */ #define HAL_BEACON_TBTT_EN 0x00000001 #define HAL_BEACON_DBA_EN 0x00000002 #define HAL_BEACON_SWBA_EN 0x00000004 } HAL_BEACON_TIMERS; /* * Per-node statistics maintained by the driver for use in * optimizing signal quality and other operational aspects. */ typedef struct { uint32_t ns_avgbrssi; /* average beacon rssi */ uint32_t ns_avgrssi; /* average data rssi */ uint32_t ns_avgtxrssi; /* average tx rssi */ } HAL_NODE_STATS; #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ struct ath_desc; struct ath_tx_status; struct ath_rx_status; struct ieee80211_channel; /* * This is a channel survey sample entry. * * The AR5212 ANI routines fill these samples. The ANI code then uses it * when calculating listen time; it is also exported via a diagnostic * API. */ typedef struct { uint32_t seq_num; uint32_t tx_busy; uint32_t rx_busy; uint32_t chan_busy; uint32_t ext_chan_busy; uint32_t cycle_count; /* XXX TODO */ uint32_t ofdm_phyerr_count; uint32_t cck_phyerr_count; } HAL_SURVEY_SAMPLE; /* * This provides 3.2 seconds of sample space given an * ANI time of 1/10th of a second. This may not be enough! */ #define CHANNEL_SURVEY_SAMPLE_COUNT 32 typedef struct { HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; uint32_t cur_sample; /* current sample in sequence */ uint32_t cur_seq; /* current sequence number */ } HAL_CHANNEL_SURVEY; /* * ANI commands. * * These are used both internally and externally via the diagnostic * API. * * Note that this is NOT the ANI commands being used via the INTMIT * capability - that has a different mapping for some reason. */ typedef enum { HAL_ANI_PRESENT = 0, /* is ANI support present */ HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ } HAL_ANI_CMD; /* * This is the layout of the ANI INTMIT capability. * * Notice that the command values differ to HAL_ANI_CMD. */ typedef enum { HAL_CAP_INTMIT_PRESENT = 0, HAL_CAP_INTMIT_ENABLE = 1, HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 } HAL_CAP_INTMIT_CMD; typedef struct { int32_t pe_firpwr; /* FIR pwr out threshold */ int32_t pe_rrssi; /* Radar rssi thresh */ int32_t pe_height; /* Pulse height thresh */ int32_t pe_prssi; /* Pulse rssi thresh */ int32_t pe_inband; /* Inband thresh */ /* The following params are only for AR5413 and later */ u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ int32_t pe_blockradar; /* * Enable to block radar check if pkt detect is done via OFDM * weak signal detect or pkt is detected immediately after tx * to rx transition */ int32_t pe_enmaxrssi; /* * Enable to use the max rssi instead of the last rssi during * fine gain changes for radar detection */ int32_t pe_extchannel; /* Enable DFS on ext channel */ int32_t pe_enabled; /* Whether radar detection is enabled */ int32_t pe_enrelpwr; int32_t pe_en_relstep_check; } HAL_PHYERR_PARAM; #define HAL_PHYERR_PARAM_NOVAL 65535 /* * DFS operating mode flags. */ typedef enum { HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ } HAL_DFS_DOMAIN; /* * Flag for setting QUIET period */ typedef enum { HAL_QUIET_DISABLE = 0x0, HAL_QUIET_ENABLE = 0x1, HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ } HAL_QUIET_FLAG; #define HAL_DFS_EVENT_PRICH 0x0000001 #define HAL_DFS_EVENT_EXTCH 0x0000002 #define HAL_DFS_EVENT_EXTEARLY 0x0000004 #define HAL_DFS_EVENT_ISDC 0x0000008 struct hal_dfs_event { uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ uint32_t re_ts; /* Original 15 bit recv timestamp */ uint8_t re_rssi; /* rssi of radar event */ uint8_t re_dur; /* duration of radar pulse */ uint32_t re_flags; /* Flags (see above) */ }; typedef struct hal_dfs_event HAL_DFS_EVENT; +/* + * BT Co-existence definitions + */ +typedef enum { + HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ + HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ + HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ + HAL_MAX_BT_MODULES +} HAL_BT_MODULE; + +typedef struct { + HAL_BT_MODULE bt_module; + u_int8_t bt_coex_config; + u_int8_t bt_gpio_bt_active; + u_int8_t bt_gpio_bt_priority; + u_int8_t bt_gpio_wlan_active; + u_int8_t bt_active_polarity; + HAL_BOOL bt_single_ant; + u_int8_t bt_dutyCycle; + u_int8_t bt_isolation; + u_int8_t bt_period; +} HAL_BT_COEX_INFO; + +typedef enum { + HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ + HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ + HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ + HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ +} HAL_BT_COEX_MODE; + +typedef enum { + HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ + HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ + HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ + HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ + HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ + HAL_BT_COEX_CFG_MCI /* MCI */ +} HAL_BT_COEX_CFG; + +typedef enum { + HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ + HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ + HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ +} HAL_BT_COEX_SET_PARAMETER; + +#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 +#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 +/* Check Rx Diversity is allowed */ +#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 +/* Check Diversity is on or off */ +#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 + +#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b +/* main: LNA1, alt: LNA2 */ +#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 +#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 +#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 +#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 +#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 + +#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 + +#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 + +#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 + +#define HAL_BT_COEX_LOW_ACK_POWER 0x0 +#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f + +typedef enum { + HAL_BT_COEX_NO_STOMP = 0, + HAL_BT_COEX_STOMP_ALL, + HAL_BT_COEX_STOMP_LOW, + HAL_BT_COEX_STOMP_NONE, + HAL_BT_COEX_STOMP_ALL_FORCE, + HAL_BT_COEX_STOMP_LOW_FORCE, +} HAL_BT_COEX_STOMP_TYPE; + +typedef struct { + /* extend rx_clear after tx/rx to protect the burst (in usec). */ + u_int8_t bt_time_extend; + + /* + * extend rx_clear as long as txsm is + * transmitting or waiting for ack. + */ + HAL_BOOL bt_txstate_extend; + + /* + * extend rx_clear so that when tx_frame + * is asserted, rx_clear will drop. + */ + HAL_BOOL bt_txframe_extend; + + /* + * coexistence mode + */ + HAL_BT_COEX_MODE bt_mode; + + /* + * treat BT high priority traffic as + * a quiet collision + */ + HAL_BOOL bt_quiet_collision; + + /* + * invert rx_clear as WLAN_ACTIVE + */ + HAL_BOOL bt_rxclear_polarity; + + /* + * slotted mode only. indicate the time in usec + * from the rising edge of BT_ACTIVE to the time + * BT_PRIORITY can be sampled to indicate priority. + */ + u_int8_t bt_priority_time; + + /* + * slotted mode only. indicate the time in usec + * from the rising edge of BT_ACTIVE to the time + * BT_PRIORITY can be sampled to indicate tx/rx and + * BT_FREQ is sampled. + */ + u_int8_t bt_first_slot_time; + + /* + * slotted mode only. rx_clear and bt_ant decision + * will be held the entire time that BT_ACTIVE is asserted, + * otherwise the decision is made before every slot boundry. + */ + HAL_BOOL bt_hold_rxclear; +} HAL_BT_COEX_CONFIG; + typedef struct { int ah_debug; /* only used if AH_DEBUG is defined */ int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ /* NB: these are deprecated; they exist for now for compatibility */ int ah_dma_beacon_response_time;/* in TU's */ int ah_sw_beacon_response_time; /* in TU's */ int ah_additional_swba_backoff; /* in TU's */ int ah_force_full_reset; /* force full chip reset rather then warm reset */ int ah_serialise_reg_war; /* force serialisation of register IO */ } HAL_OPS_CONFIG; /* * Hardware Access Layer (HAL) API. * * Clients of the HAL call ath_hal_attach to obtain a reference to an * ath_hal structure for use with the device. Hardware-related operations * that follow must call back into the HAL through interface, supplying * the reference as the first parameter. Note that before using the * reference returned by ath_hal_attach the caller should verify the * ABI version number. */ struct ath_hal { uint32_t ah_magic; /* consistency check magic number */ uint16_t ah_devid; /* PCI device ID */ uint16_t ah_subvendorid; /* PCI subvendor ID */ HAL_SOFTC ah_sc; /* back pointer to driver/os state */ HAL_BUS_TAG ah_st; /* params for register r+w */ HAL_BUS_HANDLE ah_sh; HAL_CTRY_CODE ah_countryCode; uint32_t ah_macVersion; /* MAC version id */ uint16_t ah_macRev; /* MAC revision */ uint16_t ah_phyRev; /* PHY revision */ /* NB: when only one radio is present the rev is in 5Ghz */ uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ uint32_t ah_intrstate[8]; /* last int state */ uint32_t ah_syncstate; /* last sync intr state */ HAL_OPS_CONFIG ah_config; const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, u_int mode); void __ahdecl(*ah_detach)(struct ath_hal*); /* Reset functions */ HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, struct ieee80211_channel *, HAL_BOOL bChannelChange, HAL_STATUS *status); HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, HAL_BOOL power_off); void __ahdecl(*ah_disablePCIE)(struct ath_hal *); void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, struct ieee80211_channel *, HAL_BOOL *); HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, struct ieee80211_channel *, u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone); HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, const struct ieee80211_channel *); HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, const struct ieee80211_channel *, uint16_t *); HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, const struct ieee80211_channel *); /* Transmit functions */ HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, HAL_BOOL incTrigLevel); int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, const HAL_TXQ_INFO *qInfo); HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, const HAL_TXQ_INFO *qInfo); HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, HAL_TXQ_INFO *qInfo); HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, u_int txRate0, u_int txTries0, u_int keyIx, u_int antMode, u_int flags, u_int rtsctsRate, u_int rtsctsDuration, u_int compicvLen, u_int compivLen, u_int comp); HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, u_int txRate1, u_int txTries1, u_int txRate2, u_int txTries2, u_int txRate3, u_int txTries3); HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_desc *); HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_desc *, struct ath_tx_status *); void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, const struct ath_desc *ds, int *rates, int *tries); /* Receive Functions */ uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); void __ahdecl(*ah_enableReceive)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, uint32_t filter0, uint32_t filter1); HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, uint32_t index); HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, uint32_t index); uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, uint32_t size, u_int flags); HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *, uint32_t phyAddr, struct ath_desc *next, uint64_t tsf, struct ath_rx_status *); void __ahdecl(*ah_rxMonitor)(struct ath_hal *, const HAL_NODE_STATS *, const struct ieee80211_channel *); void __ahdecl(*ah_aniPoll)(struct ath_hal *, const struct ieee80211_channel *); void __ahdecl(*ah_procMibEvent)(struct ath_hal *, const HAL_NODE_STATS *); void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, struct ath_rx_status *, unsigned long, int); /* Misc Functions */ HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, HAL_CAPABILITY_TYPE, uint32_t capability, uint32_t *result); HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, HAL_CAPABILITY_TYPE, uint32_t capability, uint32_t setting, HAL_STATUS *); HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, const void *args, uint32_t argsize, void **result, uint32_t *resultsize); void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, uint16_t, HAL_STATUS *); void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); void __ahdecl(*ah_writeAssocid)(struct ath_hal*, const uint8_t *bssid, uint16_t assocId); HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio, HAL_GPIO_MUX_TYPE); HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, uint32_t gpio, uint32_t val); void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); void __ahdecl(*ah_resetTsf)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, HAL_MIB_STATS*); HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, HAL_ANT_SETTING); HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag); /* DFS functions */ void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf, HAL_DFS_EVENT *event); HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); /* Key Cache Functions */ uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, uint16_t); HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, uint16_t, const HAL_KEYVAL *, const uint8_t *, int); HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, uint16_t, const uint8_t *); /* Power Management Functions */ HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, HAL_POWER_MODE mode, int setChip); HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, const struct ieee80211_channel *); /* Beacon Management Functions */ void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, const HAL_BEACON_TIMERS *); /* NB: deprecated, use ah_setBeaconTimers instead */ void __ahdecl(*ah_beaconInit)(struct ath_hal *, uint32_t nexttbtt, uint32_t intval); void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, const HAL_BEACON_STATE *); void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); /* 802.11n Functions */ HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, struct ath_desc *, u_int, u_int, HAL_PKT_TYPE, u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL, HAL_BOOL, HAL_BOOL); HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, struct ath_desc *, u_int, u_int, u_int, u_int, u_int, u_int, u_int, u_int); HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, struct ath_desc *, const struct ath_desc *); void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, struct ath_desc *, u_int, u_int, HAL_11N_RATE_SERIES [], u_int, u_int); void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, struct ath_desc *, u_int, u_int); void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, struct ath_desc *, u_int); void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, struct ath_desc *); void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, struct ath_desc *); void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, struct ath_desc *, u_int); HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, HAL_SURVEY_SAMPLE *); uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, HAL_HT_MACMODE); HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, HAL_HT_RXCLEAR); /* Interrupt functions */ HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); }; /* * Check the PCI vendor ID and device ID against Atheros' values * and return a printable description for any Atheros hardware. * AH_NULL is returned if the ID's do not describe Atheros hardware. */ extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); /* * Attach the HAL for use with the specified device. The device is * defined by the PCI device ID. The caller provides an opaque pointer * to an upper-layer data structure (HAL_SOFTC) that is stored in the * HAL state block for later use. Hardware register accesses are done * using the specified bus tag and handle. On successful return a * reference to a state block is returned that must be supplied in all * subsequent HAL calls. Storage associated with this reference is * dynamically allocated and must be freed by calling the ah_detach * method when the client is done. If the attach operation fails a * null (AH_NULL) reference will be returned and a status code will * be returned if the status parameter is non-zero. */ extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); extern const char *ath_hal_mac_name(struct ath_hal *); extern const char *ath_hal_rf_name(struct ath_hal *); /* * Regulatory interfaces. Drivers should use ath_hal_init_channels to * request a set of channels for a particular country code and/or * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then * this list is constructed according to the contents of the EEPROM. * ath_hal_getchannels acts similarly but does not alter the operating * state; this can be used to collect information for a particular * regulatory configuration. Finally ath_hal_set_channels installs a * channel list constructed outside the driver. The HAL will adopt the * channel list and setup internal state according to the specified * regulatory configuration (e.g. conformance test limits). * * For all interfaces the channel list is returned in the supplied array. * maxchans defines the maximum size of this array. nchans contains the * actual number of channels returned. If a problem occurred then a * status code != HAL_OK is returned. */ struct ieee80211_channel; /* * Return a list of channels according to the specified regulatory. */ extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, struct ieee80211_channel *chans, u_int maxchans, int *nchans, u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, HAL_BOOL enableExtendedChannels); /* * Return a list of channels and install it as the current operating * regulatory list. */ extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, struct ieee80211_channel *chans, u_int maxchans, int *nchans, u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, HAL_BOOL enableExtendedChannels); /* * Install the list of channels as the current operating regulatory * and setup related state according to the country code and sku. */ extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, struct ieee80211_channel *chans, int nchans, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); /* * Fetch the ctl/ext noise floor values reported by a MIMO * radio. Returns 1 for valid results, 0 for invalid channel. */ extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, const struct ieee80211_channel *chan, int16_t *nf_ctl, int16_t *nf_ext); /* * Calibrate noise floor data following a channel scan or similar. * This must be called prior retrieving noise floor data. */ extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); /* * Return bit mask of wireless modes supported by the hardware. */ extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); /* * Calculate the packet TX time for a legacy or 11n frame */ extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, const HAL_RATE_TABLE *rates, uint32_t frameLen, uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); /* * Calculate the duration of an 11n frame. */ extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); /* * Calculate the transmit duration of a legacy frame. */ extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, const HAL_RATE_TABLE *rates, uint32_t frameLen, uint16_t rateix, HAL_BOOL shortPreamble); /* * Adjust the TSF. */ extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); /* * Enable or disable CCA. */ void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); /* * Get CCA setting. */ int __ahdecl ath_hal_getcca(struct ath_hal *ah); /* * Read EEPROM data from ah_eepromdata */ HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, u_int off, uint16_t *data); #endif /* _ATH_AH_H_ */ diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416.h b/sys/dev/ath/ath_hal/ar5416/ar5416.h index b95bdaf0ace6..5a0e7ef7e6c3 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416.h +++ b/sys/dev/ath/ath_hal/ar5416/ar5416.h @@ -1,362 +1,399 @@ /* * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting * Copyright (c) 2002-2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _ATH_AR5416_H_ #define _ATH_AR5416_H_ #include "ar5212/ar5212.h" #include "ar5416_cal.h" #include "ah_eeprom_v14.h" /* for CAL_TARGET_POWER_* */ #define AR5416_MAGIC 0x20065416 enum { HAL_RESET_POWER_ON, HAL_RESET_WARM, HAL_RESET_COLD, }; typedef struct { uint16_t synth_center; uint16_t ctl_center; uint16_t ext_center; } CHAN_CENTERS; typedef enum Ar5416_Rates { rate6mb, rate9mb, rate12mb, rate18mb, rate24mb, rate36mb, rate48mb, rate54mb, rate1l, rate2l, rate2s, rate5_5l, rate5_5s, rate11l, rate11s, rateXr, rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, Ar5416RateSize } AR5416_RATES; #define AR5416_DEFAULT_RXCHAINMASK 7 #define AR5416_DEFAULT_TXCHAINMASK 1 #define AR5416_MAX_RATE_POWER 63 #define AR5416_KEYTABLE_SIZE 128 #define AR5416_CCA_MAX_GOOD_VALUE -85 #define AR5416_CCA_MAX_HIGH_VALUE -62 #define AR5416_CCA_MIN_BAD_VALUE -140 #define AR9285_CCA_MAX_GOOD_VALUE -118 #define AR5416_SPUR_RSSI_THRESH 40 struct ar5416NfLimits { int16_t max; int16_t min; int16_t nominal; }; struct ath_hal_5416 { struct ath_hal_5212 ah_5212; /* NB: RF data setup at attach */ HAL_INI_ARRAY ah_ini_bb_rfgain; HAL_INI_ARRAY ah_ini_bank0; HAL_INI_ARRAY ah_ini_bank1; HAL_INI_ARRAY ah_ini_bank2; HAL_INI_ARRAY ah_ini_bank3; HAL_INI_ARRAY ah_ini_bank6; HAL_INI_ARRAY ah_ini_bank7; HAL_INI_ARRAY ah_ini_addac; HAL_INI_ARRAY ah_ini_pcieserdes; void (*ah_writeIni)(struct ath_hal *, const struct ieee80211_channel *); void (*ah_spurMitigate)(struct ath_hal *, const struct ieee80211_channel *); /* calibration ops */ HAL_BOOL (*ah_cal_initcal)(struct ath_hal *, const struct ieee80211_channel *); void (*ah_cal_pacal)(struct ath_hal *, HAL_BOOL is_reset); /* optional open-loop tx power control related methods */ void (*ah_olcInit)(struct ath_hal *); void (*ah_olcTempCompensation)(struct ath_hal *); /* tx power control */ HAL_BOOL (*ah_setPowerCalTable) (struct ath_hal *ah, struct ar5416eeprom *pEepData, const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset); /* baseband operations */ void (*ah_initPLL) (struct ath_hal *ah, const struct ieee80211_channel *chan); u_int ah_globaltxtimeout; /* global tx timeout */ u_int ah_gpioMask; int ah_hangs; /* h/w hangs state */ uint8_t ah_keytype[AR5416_KEYTABLE_SIZE]; /* * Primary/Extension Channel Tx, Rx, Rx Clear State */ uint32_t ah_cycleCount; uint32_t ah_ctlBusy; uint32_t ah_extBusy; uint32_t ah_rxBusy; uint32_t ah_txBusy; uint32_t ah_rx_chainmask; uint32_t ah_tx_chainmask; HAL_ANI_CMD ah_ani_function; struct ar5416PerCal ah_cal; /* periodic calibration state */ struct ar5416NfLimits nf_2g; struct ar5416NfLimits nf_5g; int initPDADC; int ah_need_an_top2_fixup; /* merlin or later chips that may need this workaround */ + + /* + * Bluetooth coexistence static setup according to the registry + */ + HAL_BT_MODULE ah_btModule; /* Bluetooth module identifier */ + uint8_t ah_btCoexConfigType; /* BT coex configuration */ + uint8_t ah_btActiveGpioSelect; /* GPIO pin for BT_ACTIVE */ + uint8_t ah_btPriorityGpioSelect; /* GPIO pin for BT_PRIORITY */ + uint8_t ah_wlanActiveGpioSelect; /* GPIO pin for WLAN_ACTIVE */ + uint8_t ah_btActivePolarity; /* Polarity of BT_ACTIVE */ + HAL_BOOL ah_btCoexSingleAnt; /* Single or dual antenna configuration */ + uint8_t ah_btWlanIsolation; /* Isolation between BT and WLAN in dB */ + + /* + * Bluetooth coexistence runtime settings + */ + HAL_BOOL ah_btCoexEnabled; /* If Bluetooth coexistence is enabled */ + uint32_t ah_btCoexMode; /* Register setting for AR_BT_COEX_MODE */ + uint32_t ah_btCoexBTWeight; /* Register setting for AR_BT_COEX_WEIGHT */ + uint32_t ah_btCoexWLANWeight; /* Register setting for AR_BT_COEX_WEIGHT */ + uint32_t ah_btCoexMode2; /* Register setting for AR_BT_COEX_MODE2 */ + uint32_t ah_btCoexFlag; /* Special tuning flags for BT coex */ }; #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) #define IS_5416_PCI(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_OWL_PCI) #define IS_5416_PCIE(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_OWL_PCIE) #undef IS_PCIE #define IS_PCIE(ah) (IS_5416_PCIE(ah)) extern HAL_BOOL ar2133RfAttach(struct ath_hal *, HAL_STATUS *); struct ath_hal; extern uint32_t ar5416GetRadioRev(struct ath_hal *ah); extern void ar5416InitState(struct ath_hal_5416 *, uint16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); extern void ar5416Detach(struct ath_hal *ah); extern void ar5416AttachPCIE(struct ath_hal *ah); extern HAL_BOOL ar5416FillCapabilityInfo(struct ath_hal *ah); extern void ar5416AniAttach(struct ath_hal *, const struct ar5212AniParams *, const struct ar5212AniParams *, HAL_BOOL ena); extern void ar5416AniDetach(struct ath_hal *); extern HAL_BOOL ar5416AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); extern HAL_BOOL ar5416AniSetParams(struct ath_hal *, const struct ar5212AniParams *, const struct ar5212AniParams *); extern void ar5416ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); extern void ar5416RxMonitor(struct ath_hal *, const HAL_NODE_STATS *, const struct ieee80211_channel *); extern void ar5416AniPoll(struct ath_hal *, const struct ieee80211_channel *); extern void ar5416AniReset(struct ath_hal *, const struct ieee80211_channel *, HAL_OPMODE, int); extern void ar5416SetBeaconTimers(struct ath_hal *, const HAL_BEACON_TIMERS *); extern void ar5416BeaconInit(struct ath_hal *ah, uint32_t next_beacon, uint32_t beacon_period); extern void ar5416ResetStaBeaconTimers(struct ath_hal *ah); extern void ar5416SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *); extern uint64_t ar5416GetNextTBTT(struct ath_hal *); +/* ar5416_btcoex.c */ +extern void ar5416SetBTCoexInfo(struct ath_hal *ah, + HAL_BT_COEX_INFO *btinfo); +extern void ar5416BTCoexConfig(struct ath_hal *ah, + HAL_BT_COEX_CONFIG *btconf); +extern void ar5416BTCoexSetQcuThresh(struct ath_hal *ah, int qnum); +extern void ar5416BTCoexSetWeights(struct ath_hal *ah, uint32_t stompType); +extern void ar5416BTCoexSetupBmissThresh(struct ath_hal *ah, + uint32_t thresh); +extern void ar5416BTCoexSetParameter(struct ath_hal *ah, uint32_t type, + uint32_t value); +extern void ar5416BTCoexDisable(struct ath_hal *ah); +extern int ar5416BTCoexEnable(struct ath_hal *ah); +extern void ar5416InitBTCoex(struct ath_hal *ah); + extern HAL_BOOL ar5416EepromRead(struct ath_hal *, u_int off, uint16_t *data); extern HAL_BOOL ar5416EepromWrite(struct ath_hal *, u_int off, uint16_t data); extern HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah); extern HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *, HAL_INT *masked); extern HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints); extern HAL_BOOL ar5416GpioCfgOutput(struct ath_hal *, uint32_t gpio, HAL_GPIO_MUX_TYPE); extern HAL_BOOL ar5416GpioCfgInput(struct ath_hal *, uint32_t gpio); extern HAL_BOOL ar5416GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); extern uint32_t ar5416GpioGet(struct ath_hal *ah, uint32_t gpio); extern void ar5416GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); extern u_int ar5416GetWirelessModes(struct ath_hal *ah); extern void ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state); extern uint64_t ar5416GetTsf64(struct ath_hal *ah); extern void ar5416SetTsf64(struct ath_hal *ah, uint64_t tsf64); extern void ar5416ResetTsf(struct ath_hal *ah); extern uint32_t ar5416GetCurRssi(struct ath_hal *ah); extern HAL_BOOL ar5416SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); extern HAL_BOOL ar5416SetDecompMask(struct ath_hal *, uint16_t, int); extern void ar5416SetCoverageClass(struct ath_hal *, uint8_t, int); extern HAL_BOOL ar5416GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample); extern uint32_t ar5416Get11nExtBusy(struct ath_hal *ah); extern void ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode); extern HAL_HT_RXCLEAR ar5416Get11nRxClear(struct ath_hal *ah); extern void ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); extern HAL_STATUS ar5416SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag); extern HAL_STATUS ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, uint32_t capability, uint32_t *result); extern HAL_BOOL ar5416SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, uint32_t capability, uint32_t val, HAL_STATUS *status); extern HAL_BOOL ar5416GetDiagState(struct ath_hal *ah, int request, const void *args, uint32_t argsize, void **result, uint32_t *resultsize); extern HAL_BOOL ar5416SetRifsDelay(struct ath_hal *ah, const struct ieee80211_channel *chan, HAL_BOOL enable); extern void ar5416EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); extern void ar5416GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); extern HAL_BOOL ar5416ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf, HAL_DFS_EVENT *event); extern HAL_BOOL ar5416IsFastClockEnabled(struct ath_hal *ah); extern HAL_BOOL ar5416SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip); extern HAL_POWER_MODE ar5416GetPowerMode(struct ath_hal *ah); extern HAL_BOOL ar5416GetPowerStatus(struct ath_hal *ah); extern HAL_BOOL ar5416ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); extern HAL_BOOL ar5416SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); extern uint32_t ar5416GetRxFilter(struct ath_hal *ah); extern void ar5416SetRxFilter(struct ath_hal *ah, uint32_t bits); extern HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah); extern void ar5416StartPcuReceive(struct ath_hal *ah); extern void ar5416StopPcuReceive(struct ath_hal *ah); extern HAL_BOOL ar5416SetupRxDesc(struct ath_hal *, struct ath_desc *, uint32_t size, u_int flags); extern HAL_STATUS ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *, uint32_t, struct ath_desc *, uint64_t, struct ath_rx_status *); extern HAL_BOOL ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, HAL_BOOL bChannelChange, HAL_STATUS *status); extern HAL_BOOL ar5416PhyDisable(struct ath_hal *ah); extern HAL_RFGAIN ar5416GetRfgain(struct ath_hal *ah); extern HAL_BOOL ar5416Disable(struct ath_hal *ah); extern HAL_BOOL ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *); extern int ar5416GetRegChainOffset(struct ath_hal *ah, int i); extern HAL_BOOL ar5416SetBoardValues(struct ath_hal *, const struct ieee80211_channel *); extern HAL_BOOL ar5416SetResetReg(struct ath_hal *, uint32_t type); extern HAL_BOOL ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); extern HAL_BOOL ar5416SetTransmitPower(struct ath_hal *, const struct ieee80211_channel *, uint16_t *); extern HAL_BOOL ar5416GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan); extern void ar5416GetChannelCenters(struct ath_hal *, const struct ieee80211_channel *chan, CHAN_CENTERS *centers); extern void ar5416SetRatesArrayFromTargetPower(struct ath_hal *ah, const struct ieee80211_channel *chan, int16_t *ratesArray, const CAL_TARGET_POWER_LEG *targetPowerCck, const CAL_TARGET_POWER_LEG *targetPowerCckExt, const CAL_TARGET_POWER_LEG *targetPowerOfdm, const CAL_TARGET_POWER_LEG *targetPowerOfdmExt, const CAL_TARGET_POWER_HT *targetPowerHt20, const CAL_TARGET_POWER_HT *targetPowerHt40); extern void ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels, CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates, HAL_BOOL isHt40Target); extern void ar5416GetTargetPowersLeg(struct ath_hal *ah, const struct ieee80211_channel *chan, CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates, HAL_BOOL isExtTarget); extern void ar5416InitChainMasks(struct ath_hal *ah); extern void ar5416RestoreChainMask(struct ath_hal *ah); extern void ar5416EepromSetAddac(struct ath_hal *ah, const struct ieee80211_channel *chan); extern uint16_t ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz); extern void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan); /* TX power setup related routines in ar5416_reset.c */ extern void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ *pRawDataSet, uint8_t * bChans, uint16_t availPiers, uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, uint16_t numXpdGains); extern void ar5416SetGainBoundariesClosedLoop(struct ath_hal *ah, int i, uint16_t pdGainOverlap_t2, uint16_t gainBoundaries[]); extern uint16_t ar5416GetXpdGainValues(struct ath_hal *ah, uint16_t xpdMask, uint16_t xpdGainValues[]); extern void ar5416WriteDetectorGainBiases(struct ath_hal *ah, uint16_t numXpdGain, uint16_t xpdGainValues[]); extern void ar5416WritePdadcValues(struct ath_hal *ah, int i, uint8_t pdadcValues[]); extern HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset); extern void ar5416WriteTxPowerRateRegisters(struct ath_hal *ah, const struct ieee80211_channel *chan, const int16_t ratesArray[]); extern HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, u_int q); extern HAL_BOOL ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, u_int txRate0, u_int txTries0, u_int keyIx, u_int antMode, u_int flags, u_int rtsctsRate, u_int rtsctsDuration, u_int compicvLen, u_int compivLen, u_int comp); extern HAL_BOOL ar5416SetupXTxDesc(struct ath_hal *, struct ath_desc *, u_int txRate1, u_int txRetries1, u_int txRate2, u_int txRetries2, u_int txRate3, u_int txRetries3); extern HAL_BOOL ar5416FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_desc *ds0); extern HAL_STATUS ar5416ProcTxDesc(struct ath_hal *ah, struct ath_desc *, struct ath_tx_status *); extern HAL_BOOL ar5416GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries); extern HAL_BOOL ar5416ResetTxQueue(struct ath_hal *ah, u_int q); extern int ar5416SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, const HAL_TXQ_INFO *qInfo); extern HAL_BOOL ar5416ChainTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int keyIx, HAL_CIPHER cipher, uint8_t delims, u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, HAL_BOOL lastAggr); extern HAL_BOOL ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int aggrLen, u_int flags, u_int txPower, u_int txRate0, u_int txTries0, u_int antMode, u_int rtsctsRate, u_int rtsctsDuration); extern HAL_BOOL ar5416SetupLastTxDesc(struct ath_hal *ah, struct ath_desc *ds, const struct ath_desc *ds0); extern HAL_BOOL ar5416SetGlobalTxTimeout(struct ath_hal *ah, u_int tu); extern u_int ar5416GetGlobalTxTimeout(struct ath_hal *ah); extern void ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds, u_int durUpdateEn, u_int rtsctsRate, HAL_11N_RATE_SERIES series[], u_int nseries, u_int flags); extern void ar5416Set11nAggrFirst(struct ath_hal *ah, struct ath_desc *ds, u_int aggrLen, u_int numDelims); extern void ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims); extern void ar5416Set11nAggrLast(struct ath_hal *ah, struct ath_desc *ds); extern void ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds); extern void ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds, u_int burstDuration); extern const HAL_RATE_TABLE *ar5416GetRateTable(struct ath_hal *, u_int mode); #endif /* _ATH_AR5416_H_ */ diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c b/sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c new file mode 100644 index 000000000000..b7ac1184cb01 --- /dev/null +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.c @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * Copyright (c) 2002-2005 Atheros Communications, Inc. + * Copyright (c) 2008-2010, Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $FreeBSD$ + */ + +#include "opt_ah.h" + +#include "ah.h" +#include "ah_internal.h" +#include "ah_devid.h" +#ifdef AH_DEBUG +#include "ah_desc.h" /* NB: for HAL_PHYERR* */ +#endif + +#include "ar5416/ar5416.h" +#include "ar5416/ar5416reg.h" +#include "ar5416/ar5416phy.h" +#include "ar5416/ar5416desc.h" /* AR5416_CONTTXMODE */ +#include "ar5416/ar5416_btcoex.h" + +void +ar5416SetBTCoexInfo(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + + ahp->ah_btModule = btinfo->bt_module; + ahp->ah_btCoexConfigType = btinfo->bt_coex_config; + ahp->ah_btActiveGpioSelect = btinfo->bt_gpio_bt_active; + ahp->ah_btPriorityGpioSelect = btinfo->bt_gpio_bt_priority; + ahp->ah_wlanActiveGpioSelect = btinfo->bt_gpio_wlan_active; + ahp->ah_btActivePolarity = btinfo->bt_active_polarity; + ahp->ah_btCoexSingleAnt = btinfo->bt_single_ant; + ahp->ah_btWlanIsolation = btinfo->bt_isolation; +} + +void +ar5416BTCoexConfig(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + HAL_BOOL rxClearPolarity = btconf->bt_rxclear_polarity; + + /* + * For Kiwi and Osprey, the polarity of rx_clear is active high. + * The bt_rxclear_polarity flag from ath(4) needs to be inverted. + */ + if (AR_SREV_KIWI(ah)) { + rxClearPolarity = !btconf->bt_rxclear_polarity; + } + + ahp->ah_btCoexMode = (ahp->ah_btCoexMode & AR_BT_QCU_THRESH) | + SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | + SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | + SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | + SM(btconf->bt_mode, AR_BT_MODE) | + SM(btconf->bt_quiet_collision, AR_BT_QUIET) | + SM(rxClearPolarity, AR_BT_RX_CLEAR_POLARITY) | + SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | + SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); + + ahp->ah_btCoexMode2 |= SM(btconf->bt_hold_rxclear, + AR_BT_HOLD_RX_CLEAR); + + if (ahp->ah_btCoexSingleAnt == AH_FALSE) { + /* Enable ACK to go out even though BT has higher priority. */ + ahp->ah_btCoexMode2 |= AR_BT_DISABLE_BT_ANT; + } +} + +void +ar5416BTCoexSetQcuThresh(struct ath_hal *ah, int qnum) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + + ahp->ah_btCoexMode |= SM(qnum, AR_BT_QCU_THRESH); +} + +void +ar5416BTCoexSetWeights(struct ath_hal *ah, u_int32_t stompType) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + + if (AR_SREV_KIWI_10_OR_LATER(ah)) { + /* TODO: TX RX seperate is not enabled. */ + switch (stompType) { + case HAL_BT_COEX_STOMP_ALL: + ahp->ah_btCoexBTWeight = AR5416_BT_WGHT; + ahp->ah_btCoexWLANWeight = AR5416_STOMP_ALL_WLAN_WGHT; + break; + case HAL_BT_COEX_STOMP_LOW: + ahp->ah_btCoexBTWeight = AR5416_BT_WGHT; + ahp->ah_btCoexWLANWeight = AR5416_STOMP_LOW_WLAN_WGHT; + break; + case HAL_BT_COEX_STOMP_ALL_FORCE: + ahp->ah_btCoexBTWeight = AR5416_BT_WGHT; + ahp->ah_btCoexWLANWeight = + AR5416_STOMP_ALL_FORCE_WLAN_WGHT; + break; + case HAL_BT_COEX_STOMP_LOW_FORCE: + ahp->ah_btCoexBTWeight = AR5416_BT_WGHT; + ahp->ah_btCoexWLANWeight = + AR5416_STOMP_LOW_FORCE_WLAN_WGHT; + break; + case HAL_BT_COEX_STOMP_NONE: + case HAL_BT_COEX_NO_STOMP: + ahp->ah_btCoexBTWeight = AR5416_BT_WGHT; + ahp->ah_btCoexWLANWeight = AR5416_STOMP_NONE_WLAN_WGHT; + break; + default: + /* There is a forceWeight from registry */ + ahp->ah_btCoexBTWeight = stompType & 0xffff; + ahp->ah_btCoexWLANWeight = stompType >> 16; + break; + } + } else { + switch (stompType) { + case HAL_BT_COEX_STOMP_ALL: + ahp->ah_btCoexBTWeight = AR5416_BT_WGHT; + ahp->ah_btCoexWLANWeight = AR5416_STOMP_ALL_WLAN_WGHT; + break; + case HAL_BT_COEX_STOMP_LOW: + ahp->ah_btCoexBTWeight = AR5416_BT_WGHT; + ahp->ah_btCoexWLANWeight = AR5416_STOMP_LOW_WLAN_WGHT; + break; + case HAL_BT_COEX_STOMP_ALL_FORCE: + ahp->ah_btCoexBTWeight = AR5416_BT_WGHT; + ahp->ah_btCoexWLANWeight = + AR5416_STOMP_ALL_FORCE_WLAN_WGHT; + break; + case HAL_BT_COEX_STOMP_LOW_FORCE: + ahp->ah_btCoexBTWeight = AR5416_BT_WGHT; + ahp->ah_btCoexWLANWeight = + AR5416_STOMP_LOW_FORCE_WLAN_WGHT; + break; + case HAL_BT_COEX_STOMP_NONE: + case HAL_BT_COEX_NO_STOMP: + ahp->ah_btCoexBTWeight = AR5416_BT_WGHT; + ahp->ah_btCoexWLANWeight = AR5416_STOMP_NONE_WLAN_WGHT; + break; + default: + /* There is a forceWeight from registry */ + ahp->ah_btCoexBTWeight = stompType & 0xffff; + ahp->ah_btCoexWLANWeight = stompType >> 16; + break; + } + } +} + +void +ar5416BTCoexSetupBmissThresh(struct ath_hal *ah, u_int32_t thresh) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + + ahp->ah_btCoexMode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); +} + +/* + * There is no antenna diversity for Owl, Kiwi, etc. + * + * Kite will override this particular method. + */ +static void +ar5416BTCoexAntennaDiversity(struct ath_hal *ah) +{ +} + +void +ar5416BTCoexSetParameter(struct ath_hal *ah, u_int32_t type, u_int32_t value) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + + switch (type) { + case HAL_BT_COEX_SET_ACK_PWR: + if (value) { + ahp->ah_btCoexFlag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; + OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); + } else { + ahp->ah_btCoexFlag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; + OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); + } + break; + case HAL_BT_COEX_ANTENNA_DIVERSITY: + /* This is overridden for Kite */ + break; +#if 0 + case HAL_BT_COEX_LOWER_TX_PWR: + if (value) { + if ((ahp->ah_btCoexFlag & HAL_BT_COEX_FLAG_LOWER_TX_PWR) == 0) { + ahp->ah_btCoexFlag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; + AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = 1; + ar5416SetTxPowerLimit(ah, AH_PRIVATE(ah)->ah_power_limit, AH_PRIVATE(ah)->ah_extra_txpow, 0); + } + } + else { + if (ahp->ah_btCoexFlag & HAL_BT_COEX_FLAG_LOWER_TX_PWR) { + ahp->ah_btCoexFlag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; + AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = 0; + ar5416SetTxPowerLimit(ah, AH_PRIVATE(ah)->ah_power_limit, AH_PRIVATE(ah)->ah_extra_txpow, 0); + } + } + break; +#endif + default: + break; + } +} + +void +ar5416BTCoexDisable(struct ath_hal *ah) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + + /* Always drive rx_clear_external output as 0 */ + ar5416GpioSet(ah, ahp->ah_wlanActiveGpioSelect, 0); + ar5416GpioCfgOutput(ah, ahp->ah_wlanActiveGpioSelect, + HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); + + if (AR_SREV_9271(ah)) { + /* + * Set wlanActiveGpio to input when disabling BT-COEX to + * reduce power consumption + */ + ar5416GpioCfgInput(ah, ahp->ah_wlanActiveGpioSelect); + } + + if (ahp->ah_btCoexSingleAnt == AH_TRUE) { + OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, + 1); + OS_REG_RMW_FIELD(ah, AR_MISC_MODE, AR_PCU_BT_ANT_PREVENT_RX, + 0); + } + + OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); + OS_REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0); + if (AR_SREV_KIWI_10_OR_LATER(ah)) + OS_REG_WRITE(ah, AR_BT_COEX_WEIGHT2, 0); + OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); + + ahp->ah_btCoexEnabled = AH_FALSE; +} + +int +ar5416BTCoexEnable(struct ath_hal *ah) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + + /* Program coex mode and weight registers to actually enable coex */ + OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_btCoexMode); + OS_REG_WRITE(ah, AR_BT_COEX_WEIGHT, + SM(ahp->ah_btCoexWLANWeight & 0xFFFF, AR_BT_WL_WGHT) | + SM(ahp->ah_btCoexBTWeight & 0xFFFF, AR_BT_BT_WGHT)); + if (AR_SREV_KIWI_10_OR_LATER(ah)) { + OS_REG_WRITE(ah, AR_BT_COEX_WEIGHT2, + SM(ahp->ah_btCoexWLANWeight >> 16, AR_BT_WL_WGHT)); + } + OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_btCoexMode2); + +#if 0 + /* Added Select GPIO5~8 instaed SPI */ + if (AR_SREV_9271(ah)) { + val = OS_REG_READ(ah, AR9271_CLOCK_CONTROL); + val &= 0xFFFFFEFF; + OS_REG_WRITE(ah, AR9271_CLOCK_CONTROL, val); + } +#endif + + if (ahp->ah_btCoexFlag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) + OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); + else + OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); + + if (ahp->ah_btCoexSingleAnt == AH_TRUE) { + OS_REG_RMW_FIELD(ah, AR_QUIET1, + AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); + /* XXX should update miscMode? */ + OS_REG_RMW_FIELD(ah, AR_MISC_MODE, + AR_PCU_BT_ANT_PREVENT_RX, 1); + } else { + OS_REG_RMW_FIELD(ah, AR_QUIET1, + AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); + /* XXX should update miscMode? */ + OS_REG_RMW_FIELD(ah, AR_MISC_MODE, + AR_PCU_BT_ANT_PREVENT_RX, 0); + } + + if (ahp->ah_btCoexConfigType == HAL_BT_COEX_CFG_3WIRE) { + /* For 3-wire, configure the desired GPIO port for rx_clear */ + ar5416GpioCfgOutput(ah, ahp->ah_wlanActiveGpioSelect, + HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); + } else { + /* + * For 2-wire, configure the desired GPIO port + * for TX_FRAME output + */ + ar5416GpioCfgOutput(ah, ahp->ah_wlanActiveGpioSelect, + HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); + } + + /* + * Enable a weak pull down on BT_ACTIVE. + * When BT device is disabled, BT_ACTIVE might be floating. + */ + OS_REG_RMW(ah, AR_GPIO_PDPU, + (0x2 << (ahp->ah_btActiveGpioSelect * 2)), + (0x3 << (ahp->ah_btActiveGpioSelect * 2))); + + ahp->ah_btCoexEnabled = AH_TRUE; + + return (0); +} + +void +ar5416InitBTCoex(struct ath_hal *ah) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + + if (ahp->ah_btCoexConfigType == HAL_BT_COEX_CFG_3WIRE) { + OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, + (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | + AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); + + /* + * Set input mux for bt_prority_async and + * bt_active_async to GPIO pins + */ + OS_REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, + AR_GPIO_INPUT_MUX1_BT_ACTIVE, + ahp->ah_btActiveGpioSelect); + OS_REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, + AR_GPIO_INPUT_MUX1_BT_PRIORITY, + ahp->ah_btPriorityGpioSelect); + + /* + * Configure the desired GPIO ports for input + */ + ar5416GpioCfgInput(ah, ahp->ah_btActiveGpioSelect); + ar5416GpioCfgInput(ah, ahp->ah_btPriorityGpioSelect); + + if (AR_SREV_KITE(ah)) + ar5416BTCoexAntennaDiversity(ah); + + if (ahp->ah_btCoexEnabled) + ar5416BTCoexEnable(ah); + else + ar5416BTCoexDisable(ah); + } else if (ahp->ah_btCoexConfigType != HAL_BT_COEX_CFG_NONE) { + /* 2-wire */ + if (ahp->ah_btCoexEnabled) { + /* Connect bt_active_async to baseband */ + OS_REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, + (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | + AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); + OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, + AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); + + /* + * Set input mux for bt_prority_async and + * bt_active_async to GPIO pins + */ + OS_REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, + AR_GPIO_INPUT_MUX1_BT_ACTIVE, + ahp->ah_btActiveGpioSelect); + + /* Configure the desired GPIO ports for input */ + ar5416GpioCfgInput(ah, ahp->ah_btActiveGpioSelect); + + /* Enable coexistence on initialization */ + ar5416BTCoexEnable(ah); + } + } +} diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.h b/sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.h new file mode 100644 index 000000000000..7abdfa0f7376 --- /dev/null +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_btcoex.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2011 Atheros Communications, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $FreeBSD$ + */ + +#ifndef __ATH_AR5416_BTCOEX_H__ +#define __ATH_AR5416_BTCOEX_H__ +/* + * Weight table configurations. + */ +#define AR5416_BT_WGHT 0xff55 +#define AR5416_STOMP_ALL_WLAN_WGHT 0xfcfc +#define AR5416_STOMP_LOW_WLAN_WGHT 0xa8a8 +#define AR5416_STOMP_NONE_WLAN_WGHT 0x0000 +#define AR5416_STOMP_ALL_FORCE_WLAN_WGHT 0xffff // Stomp BT even when WLAN is idle +#define AR5416_STOMP_LOW_FORCE_WLAN_WGHT 0xaaaa // Stomp BT even when WLAN is idle + +#define AR9300_BT_WGHT 0xcccc4444 +#define AR9300_STOMP_ALL_WLAN_WGHT0 0xfffffff0 +#define AR9300_STOMP_ALL_WLAN_WGHT1 0xfffffff0 +#define AR9300_STOMP_LOW_WLAN_WGHT0 0x88888880 +#define AR9300_STOMP_LOW_WLAN_WGHT1 0x88888880 +#define AR9300_STOMP_NONE_WLAN_WGHT0 0x00000000 +#define AR9300_STOMP_NONE_WLAN_WGHT1 0x00000000 +#define AR9300_STOMP_ALL_FORCE_WLAN_WGHT0 0xffffffff // Stomp BT even when WLAN is idle +#define AR9300_STOMP_ALL_FORCE_WLAN_WGHT1 0xffffffff +#define AR9300_STOMP_LOW_FORCE_WLAN_WGHT0 0x88888888 // Stomp BT even when WLAN is idle +#define AR9300_STOMP_LOW_FORCE_WLAN_WGHT1 0x88888888 + +#define JUPITER_STOMP_ALL_WLAN_WGHT0 0x00007d00 +#define JUPITER_STOMP_ALL_WLAN_WGHT1 0x7d7d7d00 +#define JUPITER_STOMP_ALL_WLAN_WGHT2 0x7d7d7d00 +#define JUPITER_STOMP_ALL_WLAN_WGHT3 0x7d7d7d7d +#define JUPITER_STOMP_LOW_WLAN_WGHT0 0x00007d00 +#define JUPITER_STOMP_LOW_WLAN_WGHT1 0x7d3b3b00 +#define JUPITER_STOMP_LOW_WLAN_WGHT2 0x3b3b3b00 +#define JUPITER_STOMP_LOW_WLAN_WGHT3 0x3b3b3b3b +#define JUPITER_STOMP_NONE_WLAN_WGHT0 0x00007d00 +#define JUPITER_STOMP_NONE_WLAN_WGHT1 0x7d000000 +#define JUPITER_STOMP_NONE_WLAN_WGHT2 0x00000000 +#define JUPITER_STOMP_NONE_WLAN_WGHT3 0x00000000 +#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0 0x00007d7d +#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1 0x7d7d7d00 +#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT2 0x7d7d7d7d +#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT3 0x7d7d7d7d +#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT0 0x00003b3b +#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT1 0x3b3b3b00 +#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT2 0x3b3b3b3b +#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT3 0x3b3b3b3b + +#endif /* __ATH_AR5416_BTCOEX_H__ */ diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c b/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c index 89334f55f297..3c493b43f4eb 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c @@ -1,252 +1,278 @@ /* * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting * Copyright (c) 2002-2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #include "opt_ah.h" #include "ah.h" #include "ah_internal.h" #include "ah_devid.h" #include "ar5416/ar5416.h" #include "ar5416/ar5416reg.h" #include "ar5416/ar5416phy.h" #define AR_GPIO_BIT(_gpio) (1 << _gpio) /* * Configure GPIO Output Mux control */ static void cfgOutputMux(struct ath_hal *ah, uint32_t gpio, uint32_t type) { int addr; uint32_t gpio_shift, tmp; HALDEBUG(ah, HAL_DEBUG_GPIO, "%s: gpio=%d, type=%d\n", __func__, gpio, type); /* each MUX controls 6 GPIO pins */ if (gpio > 11) addr = AR_GPIO_OUTPUT_MUX3; else if (gpio > 5) addr = AR_GPIO_OUTPUT_MUX2; else addr = AR_GPIO_OUTPUT_MUX1; /* * 5 bits per GPIO pin. Bits 0..4 for 1st pin in that mux, * bits 5..9 for 2nd pin, etc. */ gpio_shift = (gpio % 6) * 5; /* * From Owl to Merlin 1.0, the value read from MUX1 bit 4 to bit * 9 are wrong. Here is hardware's coding: * PRDATA[4:0] <= gpio_output_mux[0]; * PRDATA[9:4] <= gpio_output_mux[1]; * <==== Bit 4 is used by both gpio_output_mux[0] [1]. * Currently the max value for gpio_output_mux[] is 6. So bit 4 * will never be used. So it should be fine that bit 4 won't be * able to recover. */ if (AR_SREV_MERLIN_20_OR_LATER(ah) || (addr != AR_GPIO_OUTPUT_MUX1)) { OS_REG_RMW(ah, addr, (type << gpio_shift), (0x1f << gpio_shift)); } else { tmp = OS_REG_READ(ah, addr); tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); tmp &= ~(0x1f << gpio_shift); tmp |= type << gpio_shift; OS_REG_WRITE(ah, addr, tmp); } } /* * Configure GPIO Output lines */ HAL_BOOL ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type) { uint32_t gpio_shift, reg; +#define N(a) (sizeof(a) / sizeof(a[0])) + HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); + /* + * This table maps the HAL GPIO pins to the actual hardware + * values. + */ + static const u_int32_t MuxSignalConversionTable[] = { + AR_GPIO_OUTPUT_MUX_AS_OUTPUT, + AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED, + AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED, + AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED, + AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED, + AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL, + AR_GPIO_OUTPUT_MUX_AS_TX_FRAME, + }; + HALDEBUG(ah, HAL_DEBUG_GPIO, "%s: gpio=%d, type=%d\n", __func__, gpio, type); - /* NB: type maps directly to hardware */ - /* XXX this may not actually be the case, for anything but output */ - cfgOutputMux(ah, gpio, type); - gpio_shift = gpio << 1; /* 2 bits per output mode */ + /* + * Convert HAL signal type definitions to hardware-specific values. + */ + if (type >= N(MuxSignalConversionTable)) { + ath_hal_printf(ah, "%s: mux %d is invalid!\n", + __func__, + type); + return AH_FALSE; + } + cfgOutputMux(ah, gpio, MuxSignalConversionTable[type]); + + /* 2 bits per output mode */ + gpio_shift = gpio << 1; + /* Always drive, rather than tristate/drive low/drive high */ reg = OS_REG_READ(ah, AR_GPIO_OE_OUT); reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift); - /* Always drive, rather than tristate/drive low/drive high */ reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift; OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg); return AH_TRUE; +#undef N } /* * Configure GPIO Input lines */ HAL_BOOL ar5416GpioCfgInput(struct ath_hal *ah, uint32_t gpio) { uint32_t gpio_shift, reg; HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); HALDEBUG(ah, HAL_DEBUG_GPIO, "%s: gpio=%d\n", __func__, gpio); /* TODO: configure input mux for AR5416 */ /* If configured as input, set output to tristate */ gpio_shift = gpio << 1; reg = OS_REG_READ(ah, AR_GPIO_OE_OUT); reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift); reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift; OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg); return AH_TRUE; } /* * Once configured for I/O - set output lines */ HAL_BOOL ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val) { uint32_t reg; HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); HALDEBUG(ah, HAL_DEBUG_GPIO, "%s: gpio=%d, val=%d\n", __func__, gpio, val); reg = OS_REG_READ(ah, AR_GPIO_IN_OUT); if (val & 1) reg |= AR_GPIO_BIT(gpio); else reg &= ~AR_GPIO_BIT(gpio); OS_REG_WRITE(ah, AR_GPIO_IN_OUT, reg); return AH_TRUE; } /* * Once configured for I/O - get input lines */ uint32_t ar5416GpioGet(struct ath_hal *ah, uint32_t gpio) { uint32_t bits; if (gpio >= AH_PRIVATE(ah)->ah_caps.halNumGpioPins) return 0xffffffff; /* * Read output value for all gpio's, shift it, * and verify whether the specific bit is set. */ if (AR_SREV_KIWI_10_OR_LATER(ah)) bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9287_GPIO_IN_VAL); if (AR_SREV_KITE_10_OR_LATER(ah)) bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL); else if (AR_SREV_MERLIN_10_OR_LATER(ah)) bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR928X_GPIO_IN_VAL); else bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL); return ((bits & AR_GPIO_BIT(gpio)) != 0); } /* * Set the GPIO Interrupt Sync and Async interrupts are both set/cleared. * Async GPIO interrupts may not be raised when the chip is put to sleep. */ void ar5416GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel) { uint32_t val, mask; HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); HALDEBUG(ah, HAL_DEBUG_GPIO, "%s: gpio=%d, ilevel=%d\n", __func__, gpio, ilevel); if (ilevel == HAL_GPIO_INTR_DISABLE) { val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE), AR_INTR_ASYNC_ENABLE_GPIO) &~ AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_ASYNC_ENABLE_GPIO, val); mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK), AR_INTR_ASYNC_MASK_GPIO) &~ AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK, AR_INTR_ASYNC_MASK_GPIO, mask); /* Clear synchronous GPIO interrupt registers and pending interrupt flag */ val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE), AR_INTR_SYNC_ENABLE_GPIO) &~ AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ENABLE_GPIO, val); mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK), AR_INTR_SYNC_MASK_GPIO) &~ AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK, AR_INTR_SYNC_MASK_GPIO, mask); val = MS(OS_REG_READ(ah, AR_INTR_SYNC_CAUSE), AR_INTR_SYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_CAUSE, AR_INTR_SYNC_ENABLE_GPIO, val); } else { val = MS(OS_REG_READ(ah, AR_GPIO_INTR_POL), AR_GPIO_INTR_POL_VAL); if (ilevel == HAL_GPIO_INTR_HIGH) { /* 0 == interrupt on pin high */ val &= ~AR_GPIO_BIT(gpio); } else if (ilevel == HAL_GPIO_INTR_LOW) { /* 1 == interrupt on pin low */ val |= AR_GPIO_BIT(gpio); } OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_POL, AR_GPIO_INTR_POL_VAL, val); /* Change the interrupt mask. */ val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE), AR_INTR_ASYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_ASYNC_ENABLE_GPIO, val); mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK), AR_INTR_ASYNC_MASK_GPIO) | AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK, AR_INTR_ASYNC_MASK_GPIO, mask); /* Set synchronous GPIO interrupt registers as well */ val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE), AR_INTR_SYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ENABLE_GPIO, val); mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK), AR_INTR_SYNC_MASK_GPIO) | AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK, AR_INTR_SYNC_MASK_GPIO, mask); } AH5416(ah)->ah_gpioMask = mask; /* for ar5416SetInterrupts */ } diff --git a/sys/dev/ath/ath_hal/ar9002/ar9285.h b/sys/dev/ath/ath_hal/ar9002/ar9285.h index 3f6b48143c43..a1451d2d1da3 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9285.h +++ b/sys/dev/ath/ath_hal/ar9002/ar9285.h @@ -1,89 +1,94 @@ /* * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _ATH_AR9285_H_ #define _ATH_AR9285_H_ #include "ar5416/ar5416.h" enum ar9285_ant_div_comb_lna_conf { ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, ATH_ANT_DIV_COMB_LNA2 = 1, ATH_ANT_DIV_COMB_LNA1 = 2, ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, }; struct ar9285_ant_comb { uint16_t count; uint16_t total_pkt_count; HAL_BOOL scan; HAL_BOOL scan_not_start; int main_total_rssi; int alt_total_rssi; int alt_recv_cnt; int main_recv_cnt; int rssi_lna1; int rssi_lna2; int rssi_add; int rssi_sub; int rssi_first; int rssi_second; int rssi_third; HAL_BOOL alt_good; int quick_scan_cnt; int main_conf; enum ar9285_ant_div_comb_lna_conf first_quick_scan_conf; enum ar9285_ant_div_comb_lna_conf second_quick_scan_conf; int first_bias; int second_bias; HAL_BOOL first_ratio; HAL_BOOL second_ratio; unsigned long scan_start_time; }; struct ath_hal_9285 { struct ath_hal_5416 ah_5416; HAL_INI_ARRAY ah_ini_txgain; HAL_INI_ARRAY ah_ini_rxgain; struct ar9285_ant_comb ant_comb; /* Kite Antenna comb/diversity */ struct { int32_t prev_offset; /* Previous value of PA offset value */ int8_t max_skipcount; /* Max No. of times PACAL can be skipped */ int8_t skipcount; /* No. of times the PACAL to be skipped */ } pacal_info; }; #define AH9285(_ah) ((struct ath_hal_9285 *)(_ah)) #define AR9285_DEFAULT_RXCHAINMASK 1 #define AR9285_DEFAULT_TXCHAINMASK 1 #define AR_PHY_CCA_NOM_VAL_9285_2GHZ -118 #define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ -127 #define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ -108 HAL_BOOL ar9285SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); HAL_BOOL ar9285RfAttach(struct ath_hal *, HAL_STATUS *); extern HAL_BOOL ar9285SetTransmitPower(struct ath_hal *, const struct ieee80211_channel *, uint16_t *); extern HAL_BOOL ar9285SetBoardValues(struct ath_hal *, const struct ieee80211_channel *); +/* ar9285_btcoex.h */ +extern void ar9285BTCoexAntennaDiversity(struct ath_hal *ah); +extern void ar9285BTCoexSetParameter(struct ath_hal *ah, + u_int32_t value, u_int32_t type); + #endif /* _ATH_AR9285_H_ */ diff --git a/sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c b/sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c new file mode 100644 index 000000000000..256039c47e55 --- /dev/null +++ b/sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * Copyright (c) 2002-2005 Atheros Communications, Inc. + * Copyright (c) 2008-2010, Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $FreeBSD$ + */ + +#include "opt_ah.h" + +#include "ah.h" +#include "ah_internal.h" +#include "ah_devid.h" +#ifdef AH_DEBUG +#include "ah_desc.h" /* NB: for HAL_PHYERR* */ +#endif + +#include "ar5416/ar5416.h" +#include "ar5416/ar5416reg.h" +#include "ar5416/ar5416phy.h" +#include "ar5416/ar5416desc.h" /* AR5416_CONTTXMODE */ + +#include "ar9002/ar9285phy.h" +#include "ar9002/ar9285.h" + +/* + * This is specific to Kite. + * + * Kiwi and others don't have antenna diversity like this. + */ +void +ar9285BTCoexAntennaDiversity(struct ath_hal *ah) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + u_int32_t regVal; + u_int8_t ant_div_control1, ant_div_control2; + + if ((ahp->ah_btCoexFlag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) || + (AH5212(ah)->ah_diversity != HAL_ANT_VARIABLE)) { + if ((ahp->ah_btCoexFlag & HAL_BT_COEX_FLAG_ANT_DIV_ENABLE) && + (AH5212(ah)->ah_diversity == HAL_ANT_VARIABLE)) { + /* Enable antenna diversity */ + ant_div_control1 = HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE; + ant_div_control2 = HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE; + + /* Don't disable BT ant to allow BB to control SWCOM */ + ahp->ah_btCoexMode2 &= (~(AR_BT_DISABLE_BT_ANT)); + OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_btCoexMode2); + + /* Program the correct SWCOM table */ + OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, + HAL_BT_COEX_ANT_DIV_SWITCH_COM); + OS_REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); + } else if (AH5212(ah)->ah_diversity == HAL_ANT_FIXED_B) { + /* Disable antenna diversity. Use antenna B(LNA2) only. */ + ant_div_control1 = HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B; + ant_div_control2 = HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B; + + /* Disable BT ant to allow concurrent BT and WLAN receive */ + ahp->ah_btCoexMode2 |= AR_BT_DISABLE_BT_ANT; + OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_btCoexMode2); + + /* Program SWCOM talbe to make sure RF switch always parks at WLAN side */ + OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, HAL_BT_COEX_ANT_DIV_SWITCH_COM); + OS_REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0x60000000, 0xf0000000); + } else { + /* Disable antenna diversity. Use antenna A(LNA1) only */ + ant_div_control1 = HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A; + ant_div_control2 = HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A; + + /* Disable BT ant to allow concurrent BT and WLAN receive */ + ahp->ah_btCoexMode2 |= AR_BT_DISABLE_BT_ANT; + OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_btCoexMode2); + + /* Program SWCOM talbe to make sure RF switch always parks at BT side */ + OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0); + OS_REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); + } + + regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); + regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); + /* Clear ant_fast_div_bias [14:9] since for Janus the main LNA is always LNA1. */ + regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS)); + + regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL); + regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); + regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); + regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); + regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); + OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); + + regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); + regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); + regVal |= SM((ant_div_control1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); + OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); + } +} + +void +ar9285BTCoexSetParameter(struct ath_hal *ah, u_int32_t type, u_int32_t value) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + + switch (type) { + case HAL_BT_COEX_ANTENNA_DIVERSITY: + if (AR_SREV_KITE(ah)) { + ahp->ah_btCoexFlag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; + if (value) + ahp->ah_btCoexFlag |= + HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; + else + ahp->ah_btCoexFlag &= + ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; + ar9285BTCoexAntennaDiversity(ah); + } + break; + default: + ar5416BTCoexSetParameter(ah, type, value); + break; + } +} + + diff --git a/sys/dev/ath/ath_hal/ar9003/ar9300_btcoex.h b/sys/dev/ath/ath_hal/ar9003/ar9300_btcoex.h new file mode 100644 index 000000000000..583636ec8097 --- /dev/null +++ b/sys/dev/ath/ath_hal/ar9003/ar9300_btcoex.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2011 Atheros Communications, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $FreeBSD$ + */ + +#ifndef __ATH_AR9300_BTCOEX_H__ +#define __ATH_AR9300_BTCOEX_H__ +/* + * Weight table configurations. + */ +#define AR9300_BT_WGHT 0xcccc4444 +#define AR9300_STOMP_ALL_WLAN_WGHT0 0xfffffff0 +#define AR9300_STOMP_ALL_WLAN_WGHT1 0xfffffff0 +#define AR9300_STOMP_LOW_WLAN_WGHT0 0x88888880 +#define AR9300_STOMP_LOW_WLAN_WGHT1 0x88888880 +#define AR9300_STOMP_NONE_WLAN_WGHT0 0x00000000 +#define AR9300_STOMP_NONE_WLAN_WGHT1 0x00000000 +/* Stomp BT even when WLAN is idle */ +#define AR9300_STOMP_ALL_FORCE_WLAN_WGHT0 0xffffffff +#define AR9300_STOMP_ALL_FORCE_WLAN_WGHT1 0xffffffff +/* Stomp BT even when WLAN is idle */ +#define AR9300_STOMP_LOW_FORCE_WLAN_WGHT0 0x88888888 +#define AR9300_STOMP_LOW_FORCE_WLAN_WGHT1 0x88888888 + +#define JUPITER_STOMP_ALL_WLAN_WGHT0 0x00007d00 +#define JUPITER_STOMP_ALL_WLAN_WGHT1 0x7d7d7d00 +#define JUPITER_STOMP_ALL_WLAN_WGHT2 0x7d7d7d00 +#define JUPITER_STOMP_ALL_WLAN_WGHT3 0x7d7d7d7d +#define JUPITER_STOMP_LOW_WLAN_WGHT0 0x00007d00 +#define JUPITER_STOMP_LOW_WLAN_WGHT1 0x7d3b3b00 +#define JUPITER_STOMP_LOW_WLAN_WGHT2 0x3b3b3b00 +#define JUPITER_STOMP_LOW_WLAN_WGHT3 0x3b3b3b3b +#define JUPITER_STOMP_NONE_WLAN_WGHT0 0x00007d00 +#define JUPITER_STOMP_NONE_WLAN_WGHT1 0x7d000000 +#define JUPITER_STOMP_NONE_WLAN_WGHT2 0x00000000 +#define JUPITER_STOMP_NONE_WLAN_WGHT3 0x00000000 +#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0 0x00007d7d +#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1 0x7d7d7d00 +#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT2 0x7d7d7d7d +#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT3 0x7d7d7d7d +#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT0 0x00003b3b +#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT1 0x3b3b3b00 +#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT2 0x3b3b3b3b +#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT3 0x3b3b3b3b + +#endif /* __ATH_AR9300_BTCOEX_H__ */ diff --git a/sys/dev/ath/if_ath_led.c b/sys/dev/ath/if_ath_led.c index 47ae3e101172..33cc512ebf1e 100644 --- a/sys/dev/ath/if_ath_led.c +++ b/sys/dev/ath/if_ath_led.c @@ -1,190 +1,190 @@ /*- * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Driver for the Atheros Wireless LAN controller. * * This software is derived from work of Atsushi Onoe; his contribution * is greatly appreciated. */ #include "opt_inet.h" #include "opt_ath.h" /* * This is needed for register operations which are performed * by the driver - eg, calls to ath_hal_gettsf32(). */ #include "opt_ah.h" #include "opt_wlan.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* for mp_ncpus */ #include #include #include #include #include #include #include #include #include #include #ifdef IEEE80211_SUPPORT_SUPERG #include #endif #ifdef IEEE80211_SUPPORT_TDMA #include #endif #include #ifdef INET #include #include #endif #include #include /* XXX for softled */ #include #include #include #include /* * Software LED driver routines. */ /* * XXX TODO: move the LED sysctls here. */ /* * Configure the hardware for software and LED blinking. * The user may choose to configure part of each, depending upon the * NIC being used. * * This requires the configuration to be set before this function * is called. */ void ath_led_config(struct ath_softc *sc) { /* Software LED blinking - GPIO controlled LED */ if (sc->sc_softled) { ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, - HAL_GPIO_MUX_OUTPUT); + HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); } /* Hardware LED blinking - MAC controlled LED */ if (sc->sc_hardled) { /* * Only enable each LED if required. * * Some NICs only have one LED connected; others may * have GPIO1/GPIO2 connected to other hardware. */ if (sc->sc_led_pwr_pin > 0) ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_led_pwr_pin, - HAL_GPIO_MUX_MAC_POWER_LED); + HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED); if (sc->sc_led_net_pin > 0) ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_led_net_pin, - HAL_GPIO_MUX_MAC_NETWORK_LED); + HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED); } } static void ath_led_done(void *arg) { struct ath_softc *sc = arg; sc->sc_blinking = 0; } /* * Turn the LED off: flip the pin and then set a timer so no * update will happen for the specified duration. */ static void ath_led_off(void *arg) { struct ath_softc *sc = arg; ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); } /* * Blink the LED according to the specified on/off times. */ static void ath_led_blink(struct ath_softc *sc, int on, int off) { DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); sc->sc_blinking = 1; sc->sc_ledoff = off; callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); } void ath_led_event(struct ath_softc *sc, int rix) { sc->sc_ledevent = ticks; /* time of last event */ if (sc->sc_blinking) /* don't interrupt active blink */ return; ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff); }